PIC18F97J60 Family Data Sheet 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet  2011 Microchip Technology Inc. DS39762F

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-069-1 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39762F-page 2  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 64/80/100-Pin High-Performance, 1-Mbit Flash Microcontrollers with Ethernet Ethernet Features: Peripheral Highlights: • IEEE 802.3™ Compatible Ethernet Controller • High-Current Sink/Source: 25 mA/25 mA on PORTB • Fully Compatible with 10/100/1000Base-T Networks and PORTC • Integrated MAC and 10Base-T PHY • Five Timer modules (Timer0 to Timer4) • 8-Kbyte Transmit/Receive Packet Buffer SRAM • Four External Interrupt pins • Supports One 10Base-T Port • Two Capture/Compare/PWM (CCP) modules • Programmable Automatic Retransmit on Collision • Three Enhanced Capture/Compare/PWM (ECCP) • Programmable Padding and CRC Generation modules: • Programmable Automatic Rejection of Erroneous - One, two or four PWM outputs Packets - Selectable polarity • Activity Outputs for 2 LED Indicators - Programmable dead time • Buffer: - Auto-shutdown and auto-restart - Configurable transmit/receive buffer size • Up to Two Master Synchronous Serial Port (MSSP) - Hardware-managed circular receive FIFO modules supporting SPI (all 4 modes) and I2C™ - Byte-wide random and sequential access Master and Slave modes - Internal DMA for fast memory copying • Up to Two Enhanced USART modules: - Hardware assisted checksum calculation for - Supports RS-485, RS-232 and LIN/J2602 various protocols - Auto-wake-up on Start bit • MAC: - Auto-Baud Detect (ABD) - Support for Unicast, Multicast and Broadcast • 10-Bit, Up to 16-Channel Analog-to-Digital Converter packets module (A/D): - Programmable Pattern Match of up to 64bytes - Auto-acquisition capability within packet at user-defined offset - Conversion available during Sleep - Programmable wake-up on multiple packet • Dual Analog Comparators with Input Multiplexing formats • Parallel Slave Port (PSP) module • PHY: (100-pin devices only) - Wave shaping output filter Special Microcontroller Features: Flexible Oscillator Structure: • 5.5V Tolerant Inputs (digital-only pins) • Selectable System Clock derived from Single • Low-Power, High-Speed CMOS Flash Technology: 25MHz External Source: - Self-reprogrammable under software control - 2.778 to 41.667MHz • C compiler Optimized Architecture for Reentrant Code • Internal 31 kHz Oscillator • Power Management Features: • Secondary Oscillator using Timer1 @ 32kHz - Run: CPU on, peripherals on • Fail-Safe Clock Monitor: - Idle: CPU off, peripherals on - Allows for safe shutdown if oscillator stops - Sleep: CPU off, peripherals off • Two-Speed Oscillator Start-up • Priority Levels for Interrupts • 8 x 8 Single-Cycle Hardware Multiplier External Memory Bus • Extended Watchdog Timer (WDT): (100-pin devices only): - Programmable period from 4ms to 134s • Single-Supply 3.3V In-Circuit Serial Programming™ • Address Capability of up to 2 Mbytes (ICSP™) via Two Pins • 8-Bit or 16-Bit Interface • In-Circuit Debug (ICD) with 3 Breakpoints via • 12-Bit, 16-Bit and 20-Bit Addressing modes Two Pins • Operating Voltage Range of 2.35V to 3.6V (3.1V to 3.6V using Ethernet module) • On-Chip 2.5V Regulator  2011 Microchip Technology Inc. DS39762F-page 3

PIC18F97J60 FAMILY Device PM(rFbeolymagtseroahsrm) y M(SbeDRymatAetoaMsr )y E(TBtbhXuye/ftRrfenesXre) t I/O A1/D0- B(ciht ) ECCCCPP/ SMPISSPMI2aCs™ter EUSART omparators 8T/i1m6e-Brsit PSP External emory Bus C M PIC18F66J60 64K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N PIC18F66J65 96K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N PIC18F67J60 128K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N PIC18F86J60 64K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N PIC18F86J65 96K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N PIC18F87J60 128K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N PIC18F96J60 64K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y PIC18F96J65 96K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y PIC18F97J60 128K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y DS39762F-page 4  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY Pin Diagrams 64-Pin TQFP A 3 D P 3 P3/ 4/P E2/P2B E3/P3C E4/P3B E5/P1C D0/P1B D1/ECC D2/CCP DD SS SSPLL DDPLL BIAS SSTX POUT+ POUT- DDTX R R R R R R R V V V V R V T T V 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/P2C 1 48 VDDRX RE0/P2D 2 47 TPIN+ RB0/INT0/FLT0 3 46 TPIN- RB1/INT1 4 45 VSSRX RB2/INT2 5 44 RB4/KBI0 RB3/INT3 6 43 RB5/KBI1 MCLR 7 PIC18F66J60 42 RB6/KBI2/PGC RG4/CCP5/P1D 8 41 VSS PIC18F66J65 VSS 9 40 OSC2/CLKO VDDCORE/VCAP 10 PIC18F67J60 39 OSC1/CLKI RF7/SS1 11 38 VDD RF6/AN11 12 37 RB7/KBI3/PGD RF5/AN10/CVREF 13 36 RC5/SDO1 RF4/AN9 14 35 RC4/SDI1/SDA1 RF3/AN8 15 34 RC3/SCK1/SCL1 RF2/AN7/C1OUT 16 33 RC2/ECCP1/P1A 1718 19 2021 22 23 24 25 26 27 28 29 30 31 32 RF1/AN6/C2OUT ENVREG AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/LEDB/AN1 RA0/LEDA/AN0 VSS VDD RA5/AN4 RA4/T0CKI T1OSI/ECCP2/P2A C0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 1/ R C R  2011 Microchip Technology Inc. DS39762F-page 5

PIC18F97J60 FAMILY Pin Diagrams (Continued) 80-Pin TQFP 1) (A 2 P 1)/ H1 H0 E2/P2B (2)E3/P3C(2)E4/P3B(2)E5/P1C(2)E6/P1B(E7/ECCP2 D0 DD SS D1 D2 SSPLL DDPLL BIAS SSTX POUT+ POUT- DDTX R R R R R R R R R V V R R V V R V T T V 807978 777675 74 73 727170 69 68 67 6665 64 63 62 61 RH2 1 60 VDDRX RH3 2 59 TPIN+ RE1/P2C 3 58 TPIN- RE0/P2D 4 57 VSSRX RB0/INT0/FLT0 5 56 RG0/ECCP3/P3A RB1/INT1 6 55 RG1/TX2/CK2 RB2/INT2 7 54 RB4/KBI0 RB3/INT3 8 53 RB5/KBI1 MCLR 9 PIC18F86J60 52 RB6/KBI2/PGC RG4/CCP5/P1D 10 PIC18F86J65 51 VSS VSS 11 50 OSC2/CLKO PIC18F87J60 VDDCORE/VCAP 12 49 OSC1/CLKI RF7/SS1 13 48 VDD RF6/AN11 14 47 RB7/KBI3/PGD RF5/AN10/CVREF 15 46 RC5/SDO1 RF4/AN9 16 45 RC4/SDI1/SDA1 RF3/AN8 17 44 RC3/SCK1/SCL1 RF2/AN7/C1OUT 18 43 RC2/ECCP1/P1A RH7/AN15/P1B(2) 19 42 RG2/RX2/DT2 RH6/AN14/P1C(2) 20 41 RG3/CCP4/P3D 2122 23 2425 26 27 28 29 30 31 32 33 34 35 36 37 383940 (2)RH5/AN13/P3B(2)RH4/AN12/P3C RF1/AN6/C2OUT ENVREG AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/LEDB/AN1 RA0/LEDA/AN0 VSS VDD RA5/AN4 RA4/T0CKI (1)(1)SI/ECCP2/P2A C0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 RJ4 RJ5 O R 1 T 1/ C R Note1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting. 2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting. DS39762F-page 6  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY Pin Diagrams (Continued) 100-Pin TQFP H1/A17H0/A16E2/AD10/CS/P2B(2)E3/AD11/P3C(2)E4/AD12/P3B(2)E5/AD13/P1C(2)E6/AD14/P1B(1)(1)E7/AD15/ECCP2/P2AD0/AD0/PSP0D1/AD1/PSP1D2/AD2/PSP2D3/AD3/PSP3D4/AD4/PSP4/SDO2D5/AD5/PSP5/SDI2/SDA2 DD SSD6/AD6/PSP6/SCK2/SCL2D7/AD7/PSP7/SS2 SSPLL DDPLLBIAS SSTXPOUT+POUT- DDTX RRR RRRRRRRRRRRVVRRVVRVTTV 09876543210987654322110099887766 09999999999888888888888877777777 1 RH2/A18 1 75 VDDRX RH3/A19 2 74 TPIN+ RE1/AD9/WR/P2C 3 73 TPIN- RE0/AD8/RD/P2D 4 72 VSSRX RB0/INT0/FLT0 5 71 RG0/ECCP3/P3A RB1/INT1 6 70 RG1/TX2/CK2 RB2/INT2 7 69 RB4/KBI0 RB3/INT3/ECCP2(1)/P2A(1) 8 68 RB5/KBI1 NC 9 67 RB6/KBI2/PGC RG6 10 66 RJ2/WRL RG5 11 PIC18F96J60 65 VSS RF0/AN5 12 64 OSC2/CLKO PIC18F96J65 MCLR 13 63 OSC1/CLKI RG4/CCP5/P1D 14 PIC18F97J60 62 VDD VSS 15 61 RJ3/WRH VDDCORE/VCAP 16 60 VSS VDD 17 59 VDD RF7/SS1 18 58 RJ6/LB RF6/AN11 19 57 RB7/KBI3/PGD RF5/AN10/CVREF 20 56 RC5/SDO1 RF4/AN9 21 55 RC4/SDI1/SDA1 RF3/AN8 22 54 RC3/SCK1/SCL1 RF2/AN7/C1OUT 23 53 RC2/ECCP1/P1A RH7/AN15/P1B(2) 24 52 RG2/RX2/DT2 RH6/AN14/P1C(2) 25 51 RG3/CCP4/P3D 6789012345678901234567890 2222333333333344444444445 (2)RH5/AN13/P3B(2)RH4/AN12/P3CRF1/AN6/C2OUTENVREGAVDD AVSS RA3/AN3/V+REFRA2/AN2/V-REF RA1/LEDB/AN1RA0/LEDA/AN0VSSVDD RG7RJ7/UBVSSRA5/AN4RA4/T0CKI(1)(1)SI/ECCP2/P2AC0/T1OSO/T13CKIRC6/TX1/CK1RC7/RX1/DT1RJ4/BA0RJ5/CERJ0/ALE RJ1/OE OR 1 T 1/ C R Note1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings. 2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting.  2011 Microchip Technology Inc. DS39762F-page 7

PIC18F97J60 FAMILY Table of Contents 1.0 Device Overview........................................................................................................................................................................11 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers...................................................................................................43 3.0 Oscillator Configurations............................................................................................................................................................49 4.0 Power-Managed Modes.............................................................................................................................................................55 5.0 Reset..........................................................................................................................................................................................63 6.0 Memory Organization.................................................................................................................................................................77 7.0 Flash Program Memory............................................................................................................................................................105 8.0 External Memory Bus...............................................................................................................................................................115 9.0 8 x 8 Hardware Multiplier..........................................................................................................................................................127 10.0 Interrupts..................................................................................................................................................................................129 11.0 I/O Ports...................................................................................................................................................................................145 12.0 Timer0 Module.........................................................................................................................................................................171 13.0 Timer1 Module.........................................................................................................................................................................175 14.0 Timer2 Module.........................................................................................................................................................................180 15.0 Timer3 Module.........................................................................................................................................................................183 16.0 Timer4 Module.........................................................................................................................................................................187 17.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................189 18.0 Enhanced Capture/Compare/PWM (ECCP) Modules..............................................................................................................197 19.0 Ethernet Module.......................................................................................................................................................................217 20.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................269 21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................315 22.0 10-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................339 23.0 Comparator Module..................................................................................................................................................................349 24.0 Comparator Voltage Reference Module...................................................................................................................................355 25.0 Special Features of the CPU....................................................................................................................................................359 26.0 Instruction Set Summary..........................................................................................................................................................375 27.0 Development Support...............................................................................................................................................................425 28.0 Electrical Characteristics..........................................................................................................................................................429 29.0 Packaging Information..............................................................................................................................................................465 Appendix A: Revision History.............................................................................................................................................................475 Appendix B: Device Differences.........................................................................................................................................................476 Index..................................................................................................................................................................................................477 The Microchip Web Site.....................................................................................................................................................................489 Customer Change Notification Service..............................................................................................................................................489 Customer Support..............................................................................................................................................................................489 Reader Response..............................................................................................................................................................................490 Product Identification System.............................................................................................................................................................491 DS39762F-page 8  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2011 Microchip Technology Inc. DS39762F-page 9

PIC18F97J60 FAMILY NOTES: DS39762F-page 10  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 1.0 DEVICE OVERVIEW 1.1.2 EXPANDED MEMORY The PIC18F97J60 family provides ample room for This document contains device-specific information for application code, from 64Kbytes to 128Kbytes of code the following devices: space. The Flash cells for program memory are rated • PIC18F66J60 • PIC18F87J60 to last 100 erase/write cycles. Data retention without • PIC18F66J65 • PIC18F96J60 refresh is conservatively estimated to be greater than 20 years. • PIC18F67J60 • PIC18F96J65 The PIC18F97J60 family also provides plenty of room • PIC18F86J60 • PIC18F97J60 for dynamic application data with 3808 bytes of data • PIC18F86J65 RAM. This family introduces a new line of low-voltage devices 1.1.3 EXTERNAL MEMORY BUS with the foremost traditional advantage of all PIC18 microcontrollers – namely, high computational per- In the unlikely event that 128Kbytes of memory are formance and a rich feature set at an extremely inadequate for an application, the 100-pin members of competitive price point. These features make the the PIC18F97J60 family also implement an External PIC18F97J60 family a logical choice for many Memory Bus (EMB). This allows the controller’s inter- high-performance applications where cost is a primary nal program counter to address a memory space of up consideration. to 2Mbytes, permitting a level of data access that few 8-bit devices can claim. This allows additional memory 1.1 Core Features options, including: • Using combinations of on-chip and external 1.1.1 OSCILLATOR OPTIONS AND memory up to the 2-Mbyte limit FEATURES • Using external Flash memory for reprogrammable All of the devices in the PIC18F97J60 family offer five application code or large data tables different oscillator options, allowing users a range of • Using external RAM devices for storing large choices in developing application hardware. These amounts of variable data options include: 1.1.4 EXTENDED INSTRUCTION SET • Two Crystal modes, using crystals or ceramic resonators. The PIC18F97J60 family implements the optional • Two External Clock modes, offering the option of extension to the PIC18 instruction set, adding eight a divide-by-4 clock output. new instructions and an Indexed Addressing mode. • A Phase Lock Loop (PLL) frequency multiplier, Enabled as a device configuration option, the extension available to the external oscillator modes, which has been specifically designed to optimize reentrant allows clock speeds of up to 41.667MHz. application code originally developed in high-level languages, such as C. • An internal RC oscillator with a fixed 31 kHz output which provides an extremely low-power 1.1.5 EASY MIGRATION option for timing-insensitive applications. Regardless of the memory size, all devices share the The internal oscillator block provides a stable reference same rich set of peripherals, allowing for a smooth source that gives the family additional features for migration path as applications grow and evolve. robust operation: • Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.  2011 Microchip Technology Inc. DS39762F-page 11

PIC18F97J60 FAMILY 1.2 Other Special Features 1.3 Details on Individual Family Members • Communications: The PIC18F97J60 family incorporates a range of serial communication Devices in the PIC18F97J60 family are available in peripherals, including up to two independent 64-pin, 80-pin and 100-pin packages. Block diagrams Enhanced USARTs and up to two Master SSP for the three groups are shown in Figure1-1, modules, capable of both SPI and I2C™ (Master Figure1-2 and Figure1-3. and Slave) modes of operation. In addition, one of The devices are differentiated from each other in four the general purpose I/O ports can be reconfigured ways: as an 8-bit Parallel Slave Port for direct processor-to-processor communications. 1. Flash program memory (three sizes, ranging • CCP Modules: All devices in the family incorporate from 64Kbytes for PIC18FX6J60 devices to two Capture/Compare/PWM (CCP) modules and 128Kbytes for PIC18FX7J60 devices). three Enhanced CCP (ECCP) modules to maximize 2. A/D channels (eleven for 64-pin devices, fifteen flexibility in control applications. Up to four different for 80-pin pin devices and sixteen for 100-pin time bases may be used to perform several devices). different operations at once. Each of the three 3. Serial communication modules (one EUSART ECCP modules offers up to four PWM outputs, module and one MSSP module on 64-pin allowing for a total of twelve PWMs. The ECCP devices, two EUSART modules and one MSSP modules also offer many beneficial features, module on 80-pin devices and two EUSART including polarity selection, programmable dead modules and two MSSP modules on 100-pin time, auto-shutdown and restart and Half-Bridge devices). and Full-Bridge Output modes. 4. I/O pins (39 on 64-pin devices, 55 on 80-pin • 10-Bit A/D Converter: This module incorporates devices and 70 on 100-pin devices). programmable acquisition time, allowing for a All other features for devices in this family are identical. channel to be selected and a conversion to be These are summarized in Table1-1, Table1-2 and initiated without waiting for a sampling period and Table1-3. thus, reducing code overhead. The pinouts for all devices are listed in Table1-4, • Extended Watchdog Timer (WDT): This Table1-5 and Table1-6. enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range. See Section28.0 “Electrical Characteristics” for time-out periods. DS39762F-page 12  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (64-PIN DEVICES) Features PIC18F66J60 PIC18F66J65 PIC18F67J60 Operating Frequency DC – 41.667 MHz DC – 41.667 MHz DC – 41.667 MHz Program Memory (Bytes) 64K 96K 128K Program Memory (Instructions) 32764 49148 65532 Data Memory (Bytes) 3808 Interrupt Sources 26 I/O Ports Ports A, B, C, D, E, F, G I/O Pins 39 Timers 5 Capture/Compare/PWM Modules 2 Enhanced Capture/Compare/PWM Modules 3 Serial Communications MSSP (1), Enhanced USART (1) Ethernet Communications (10Base-T) Yes Parallel Slave Port Communications (PSP) No External Memory Bus No 10-Bit Analog-to-Digital Module 11 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR , WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 64-Pin TQFP TABLE 1-2: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (80-PIN DEVICES) Features PIC18F86J60 PIC18F86J65 PIC18F87J60 Operating Frequency DC – 41.667 MHz DC – 41.667 MHz DC – 41.667 MHz Program Memory (Bytes) 64K 96K 128K Program Memory (Instructions) 32764 49148 65532 Data Memory (Bytes) 3808 Interrupt Sources 27 I/O Ports Ports A, B, C, D, E, F, G, H, J I/O Pins 55 Timers 5 Capture/Compare/PWM Modules 2 Enhanced Capture/Compare/PWM Modules 3 Serial Communications MSSP (1), Enhanced USART (2) Ethernet Communications (10Base-T) Yes Parallel Slave Port Communications (PSP) No External Memory Bus No 10-Bit Analog-to-Digital Module 15 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR , WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 80-Pin TQFP  2011 Microchip Technology Inc. DS39762F-page 13

PIC18F97J60 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (100-PIN DEVICES) Features PIC18F96J60 PIC18F96J65 PIC18F97J60 Operating Frequency DC – 41.667 MHz DC – 41.667 MHz DC – 41.667 MHz Program Memory (Bytes) 64K 96K 128K Program Memory (Instructions) 32764 49148 65532 Data Memory (Bytes) 3808 Interrupt Sources 29 I/O Ports Ports A, B, C, D, E, F, G, H, J I/O Pins 70 Timers 5 Capture/Compare/PWM Modules 2 Enhanced Capture/Compare/PWM Modules 3 Serial Communications MSSP (2), Enhanced USART (2) Ethernet Communications (10Base-T) Yes Parallel Slave Port Communications (PSP) Yes External Memory Bus Yes 10-Bit Analog-to-Digital Module 16 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR , WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 100-Pin TQFP DS39762F-page 14  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 1-1: PIC18F66J60/66J65/67J60 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch inc/dec logic 8 8 RA0:RA5(1) Data Memory (3808 Bytes) 21 PCLAT U PCLATH 20 Address Latch PCU PCH PCL Program Counter 12 PORTB Data Address<12> RB0:RB7(1) 31 Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (64, 96, 128 Kbytes) FSR1 FSR2 12 Data Latch PORTC inc/dec RC0:RC7(1) 8 logic Table Latch Address ROM Latch Instruction Bus <16> Decode PORTD IR RD0:RD2(1) 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL PORTE RE0:RE5(1) 8 x 8 Multiply 3 OSC2/CLKO Timing Power-up 8 OSC1/CLKI Generation Timer BITOP W Oscillator 8 8 8 Start-up Timer INTRC Oscillator Power-on 8 8 PORTF Reset RF1:RF7(1) Precision ALU<8> Band Gap Watchdog Reference Timer 8 ENVREG Brown-out Voltage Reset(2) Regulator PORTG RG4(1) VDDCORE/VCAP VDD,VSS MCLR ADC Timer0 Timer1 Timer2 Timer3 Timer4 Comparators 10-Bit ECCP1 ECCP2 ECCP3 CCP4 CCP5 MSSP1 EUSART1 Ethernet Note 1: See Table1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled.  2011 Microchip Technology Inc. DS39762F-page 15

PIC18F97J60 FAMILY FIGURE 1-2: PIC18F86J60/86J65/87J60 (80-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch inc/dec logic 8 8 RA0:RA5(1) Data Memory (3808 Bytes) 21 PCLAT U PCLATH 20 Address Latch PCU PCH PCL PORTB Program Counter 12 RB0:RB7(1) Data Address<12> 31 Level Stack Address Latch 4 12 4 BSR Access PORTC Program Memory STKPTR FSR0 Bank (64, 96, 128 Kbytes) FSR1 RC0:RC7(1) FSR2 12 Data Latch inc/dec 8 logic PORTD Table Latch RD0:RD2(1) Address ROM Latch Instruction Bus <16> Decode PORTE IR RE0:RE7(1) 8 Instruction State Machine DCecoondtreo l& Control Signals PORTF PRODH PRODL RF1:RF7(1) 8 x 8 Multiply OSC2/CLKO Timing Power-up 3 8 OSC1/CLKI Generation Timer BITOP W PORTG Oscillator 8 8 8 Start-up Timer RG0:RG4(1) INTRC Oscillator Power-on 8 8 Reset Precision ALU<8> Band Gap Watchdog PORTH Reference Timer 8 RH0:RH7(1) ENVREG Brown-out Voltage Reset(2) Regulator PORTJ VDDCORE/VCAP VDD, VSS MCLR RJ4:RJ5(1) ADC 10-Bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators ECCP1 ECCP2 ECCP3 CCP4 CCP5 EUSART1 EUSART2 MSSP1 Ethernet Note 1: See Table1-5 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. DS39762F-page 16  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 1-3: PIC18F96J60/96J65/97J60 (100-PIN) BLOCK DIAGRAM Data Bus<8> PORTA Table Pointer<21> 8 8 Data Latch RA0:RA5(1) Data Memory inc/dec logic PCLAT U PCLATH (3808 Bytes) 21 20 Address Latch PCU PCH PCL PORTB Program Counter 12 RB0:RB7(1) Data Address<12> 31 Level Stack e Address Latch 4 12 4 nterfac (6P4r,o 9g6ra, m12 M8 Kembyotreys) STKPTR BSR FFSSRR01 ABccaensks RCP0O:RRTCC7(1) s I FSR2 12 Bu Data Latch m ste 8 inloc/gdiecc PORTD Sy Table Latch RD0:RD7(1) Address ROM Latch Decode Instruction Bus <16> PORTE IR AD15:AD0, A19:A16 RE0:RE7(1) (Multiplexed with PORTD, 8 PORTE and PORTH) PORTF PRODH PRODL State Machine IDnestcroudcteio &n RF0:RF7(1) Control Signals Control 8 x 8 Multiply 3 8 BITOP W OSC2/CLKO Timing Power-up 8 8 8 PORTG OSC1/CLKI Generation Timer RG0:RG7(1) Oscillator 8 8 Start-up Timer INTRC Oscillator Power-on ALU<8> Reset PORTH 8 Precision RH0:RH7(1) Band Gap Watchdog Reference Timer ENVREG Brown-out RVeoglutalagteor Reset(2) PORTJ RJ0:RJ7(1) VDDCORE/VCAP VDD, VSS MCLR ADC Timer0 Timer1 Timer2 Timer3 Timer4 Comparators 10-Bit ECCP1 ECCP2 ECCP3 CCP4 CCP5 EUSART1 EUSART2 MSSP1 MSSP2 Ethernet Note 1: See Table1-6 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled.  2011 Microchip Technology Inc. DS39762F-page 17

PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type TQFP MCLR 7 I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OSC1/CLKI 39 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in internal RC mode; CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC2/CLKO pin.) OSC2/CLKO 40 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In Internal RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. PORTA is a bidirectional I/O port. RA0/LEDA/AN0 24 RA0 I/O TTL Digital I/O. LEDA O — Ethernet LEDA indicator output. AN0 I Analog Analog Input 0. RA1/LEDB/AN1 23 RA1 I/O TTL Digital I/O. LEDB O — Ethernet LEDB indicator output. AN1 I Analog Analog Input 1. RA2/AN2/VREF- 22 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 21 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 28 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4 27 RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DS39762F-page 18  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 3 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. FLT0 I ST Enhanced PWM Fault input (ECCP modules); enabled in software. RB1/INT1 4 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. RB2/INT2 5 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. RB3/INT3 6 RB3 I/O TTL Digital I/O. INT3 I ST External Interrupt 3. RB4/KBI0 44 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1 43 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. RB6/KBI2/PGC 42 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 37 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD)  2011 Microchip Technology Inc. DS39762F-page 19

PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 30 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/ECCP2/P2A 29 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. ECCP2 I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A O — ECCP2 PWM Output A. RC2/ECCP1/P1A 33 RC2 I/O ST Digital I/O. ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O — ECCP1 PWM Output A. RC3/SCK1/SCL1 34 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI1/SDA1 35 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O ST I2C data I/O. RC5/SDO1 36 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. RC6/TX1/CK1 31 RC6 I/O ST Digital I/O. TX1 O — EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1 pin). RC7/RX1/DT1 32 RC7 I/O ST Digital I/O. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1 pin). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DS39762F-page 20  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTD is a bidirectional I/O port. RD0/P1B 60 RD0 I/O ST Digital I/O. P1B O — ECCP1 PWM Output B. RD1/ECCP3/P3A 59 RD1 I/O ST Digital I/O. ECCP3 I/O ST Capture 3 input/Compare 3 output/PWM3 output. P3A O — ECCP3 PWM Output A. RD2/CCP4/P3D 58 RD2 I/O ST Digital I/O. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM4 output. P3D O — CCP4 PWM Output D. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD)  2011 Microchip Technology Inc. DS39762F-page 21

PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTE is a bidirectional I/O port. RE0/P2D 2 RE0 I/O ST Digital I/O. P2D O — ECCP2 PWM Output D. RE1/P2C 1 RE1 I/O ST Digital I/O. P2C O — ECCP2 PWM Output C. RE2/P2B 64 RE2 I/O ST Digital I/O. P2B O — ECCP2 PWM Output B. RE3/P3C 63 RE3 I/O ST Digital I/O. P3C O — ECCP3 PWM Output C. RE4/P3B 62 RE4 I/O ST Digital I/O. P3B O — ECCP3 PWM Output B. RE5/P1C 61 RE5 I/O ST Digital I/O. P1C O — ECCP1 PWM Output C. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DS39762F-page 22  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTF is a bidirectional I/O port. RF1/AN6/C2OUT 17 RF1 I/O ST Digital I/O. AN6 I Analog Analog Input 6. C2OUT O — Comparator 2 output. RF2/AN7/C1OUT 16 RF2 I/O ST Digital I/O. AN7 I Analog Analog Input 7. C1OUT O — Comparator 1 output. RF3/AN8 15 RF3 I/O ST Digital I/O. AN8 I Analog Analog Input 8. RF4/AN9 14 RF4 I/O ST Digital I/O. AN9 I Analog Analog Input 9. RF5/AN10/CVREF 13 RF5 I/O ST Digital I/O. AN10 I Analog Analog Input 10. CVREF O — Comparator reference voltage output. RF6/AN11 12 RF6 I/O ST Digital I/O. AN11 I Analog Analog Input 11. RF7/SS1 11 RF7 I/O ST Digital I/O. SS1 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD)  2011 Microchip Technology Inc. DS39762F-page 23

PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTG is a bidirectional I/O port. RG4/CCP5/P1D 8 RG4 I/O ST Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM5 output. P1D O — ECCP1 PWM Output D. VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins. VDD 26, 38, 57 P — Positive supply for peripheral digital logic and I/O pins. AVSS 20 P — Ground reference for analog modules. AVDD 19 P — Positive supply for analog modules. ENVREG 18 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP 10 Core logic power or external filter capacitor connection. VDDCORE P — Positive supply for microcontroller core logic (regulator disabled). VCAP P — External filter capacitor connection (regulator enabled). VSSPLL 55 P — Ground reference for Ethernet PHY PLL. VDDPLL 54 P — Positive 3.3V supply for Ethernet PHY PLL. VSSTX 52 P — Ground reference for Ethernet PHY transmit subsystem. VDDTX 49 P — Positive 3.3V supply for Ethernet PHY transmit subsystem. VSSRX 45 P — Ground reference for Ethernet PHY receive subsystem. VDDRX 48 P — Positive 3.3V supply for Ethernet PHY receive subsystem. RBIAS 53 I Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor; see Section19.0 “Ethernet Module” for specification. TPOUT+ 51 O — Ethernet differential signal output. TPOUT- 50 O — Ethernet differential signal output. TPIN+ 47 I Analog Ethernet differential signal input. TPIN- 46 I Analog Ethernet differential signal input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DS39762F-page 24  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type TQFP MCLR 9 I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OSC1/CLKI 49 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in internal RC mode; CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC2/CLKO pin.) OSC2/CLKO 50 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In Internal RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. PORTA is a bidirectional I/O port. RA0/LEDA/AN0 30 RA0 I/O TTL Digital I/O. LEDA O — Ethernet LEDA indicator output. AN0 I Analog Analog Input 0. RA1/LEDB/AN1 29 RA1 I/O TTL Digital I/O. LEDB O — Ethernet LEDB indicator output. AN1 I Analog Analog Input 1. RA2/AN2/VREF- 28 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 27 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 34 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4 33 RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).  2011 Microchip Technology Inc. DS39762F-page 25

PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 5 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. FLT0 I ST Enhanced PWM Fault input (ECCP modules); enabled in software. RB1/INT1 6 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. RB2/INT2 7 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. RB3/INT3 8 RB3 I/O TTL Digital I/O. INT3 I ST External Interrupt 3. RB4/KBI0 54 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1 53 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. RB6/KBI2/PGC 52 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 47 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 26  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 36 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/ECCP2/P2A 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. ECCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A(1) O — ECCP2 PWM Output A. RC2/ECCP1/P1A 43 RC2 I/O ST Digital I/O. ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O — ECCP1 PWM Output A. RC3/SCK1/SCL1 44 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI1/SDA1 45 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O ST I2C data I/O. RC5/SDO1 46 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. RC6/TX1/CK1 37 RC6 I/O ST Digital I/O. TX1 O — EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1 pin). RC7/RX1/DT1 38 RC7 I/O ST Digital I/O. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1 pin). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).  2011 Microchip Technology Inc. DS39762F-page 27

PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTD is a bidirectional I/O port. RD0 72 I/O ST Digital I/O. RD1 69 I/O ST Digital I/O. RD2 68 I/O ST Digital I/O. PORTE is a bidirectional I/O port. RE0/P2D 4 RE0 I/O ST Digital I/O. P2D O — ECCP2 PWM Output D. RE1/P2C 3 RE1 I/O ST Digital I/O. P2C O — ECCP2 PWM Output C. RE2/P2B 78 RE2 I/O ST Digital I/O. P2B O — ECCP2 PWM Output B. RE3/P3C 77 RE3 I/O ST Digital I/O. P3C(2) O — ECCP3 PWM Output C. RE4/P3B 76 RE4 I/O ST Digital I/O. P3B(2) O — ECCP3 PWM Output B. RE5/P1C 75 RE5 I/O ST Digital I/O. P1C(2) O — ECCP1 PWM Output C. RE6/P1B 74 RE6 I/O ST Digital I/O. P1B(2) O — ECCP1 PWM Output B. RE7/ECCP2/P2A 73 RE7 I/O ST Digital I/O. ECCP2(3) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A(3) O — ECCP2 PWM Output A. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 28  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTF is a bidirectional I/O port. RF1/AN6/C2OUT 23 RF1 I/O ST Digital I/O. AN6 I Analog Analog Input 6. C2OUT O — Comparator 2 output. RF2/AN7/C1OUT 18 RF2 I/O ST Digital I/O. AN7 I Analog Analog Input 7. C1OUT O — Comparator 1 output. RF3/AN8 17 RF3 I/O ST Digital I/O. AN8 I Analog Analog Input 8. RF4/AN9 16 RF4 I/O ST Digital I/O. AN9 I Analog Analog Input 9. RF5/AN10/CVREF 15 RF5 I/O ST Digital I/O. AN10 I Analog Analog Input 10. CVREF O — Comparator reference voltage output. RF6/AN11 14 RF6 I/O ST Digital I/O. AN11 I Analog Analog Input 11. RF7/SS1 13 RF7 I/O ST Digital I/O. SS1 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).  2011 Microchip Technology Inc. DS39762F-page 29

PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTG is a bidirectional I/O port. RG0/ECCP3/P3A 56 RG0 I/O ST Digital I/O. ECCP3 I/O ST Capture 3 input/Compare 3 output/PWM3 output. P3A O — ECCP3 PWM Output A. RG1/TX2/CK2 55 RG1 I/O ST Digital I/O. TX2 O — EUSART2 asynchronous transmit. CK2 I/O ST EUSART2 synchronous clock (see related RX2/DT2 pin). RG2/RX2/DT2 42 RG2 I/O ST Digital I/O. RX2 I ST EUSART2 asynchronous receive. DT2 I/O ST EUSART2 synchronous data (see related TX2/CK2 pin). RG3/CCP4/P3D 41 RG3 I/O ST Digital I/O. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM4 output. P3D O — ECCP3 PWM Output D. RG4/CCP5/P1D 10 RG4 I/O ST Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM5 output. P1D O — ECCP1 PWM Output D. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 30  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTH is a bidirectional I/O port. RH0 79 I/O ST Digital I/O. RH1 80 I/O ST Digital I/O. RH2 1 I/O ST Digital I/O. RH3 2 I/O ST Digital I/O. RH4/AN12/P3C 22 RH4 I/O ST Digital I/O. AN12 I Analog Analog Input 12. P3C(4) O — ECCP3 PWM Output C. RH5/AN13/P3B 21 RH5 I/O ST Digital I/O. AN13 I Analog Analog Input 13. P3B(4) O — ECCP3 PWM Output B. RH6/AN14/P1C 20 RH6 I/O ST Digital I/O. AN14 I Analog Analog Input 14. P1C(4) O — ECCP1 PWM Output C. RH7/AN15/P1B 19 RH7 I/O ST Digital I/O. AN15 I Analog Analog Input 15. P1B(4) O — ECCP1 PWM Output B. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).  2011 Microchip Technology Inc. DS39762F-page 31

PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTJ is a bidirectional I/O port. RJ4 39 I/O ST Digital I/O. RJ5 40 I/O ST Digital I/O VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins. VDD 32, 48, 71 P — Positive supply for peripheral digital logic and I/O pins. AVSS 26 P — Ground reference for analog modules. AVDD 25 P — Positive supply for analog modules. ENVREG 24 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP 12 Core logic power or external filter capacitor connection. VDDCORE P — Positive supply for microcontroller core logic (regulator disabled). VCAP P — External filter capacitor connection (regulator enabled). VSSPLL 67 P — Ground reference for Ethernet PHY PLL. VDDPLL 66 P — Positive 3.3V supply for Ethernet PHY PLL. VSSTX 64 P — Ground reference for Ethernet PHY transmit subsystem. VDDTX 61 P — Positive 3.3V supply for Ethernet PHY transmit subsystem. VSSRX 57 P — Ground reference for Ethernet PHY receive subsystem. VDDRX 60 P — Positive 3.3V supply for Ethernet PHY receive subsystem. RBIAS 65 I Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor; see Section19.0 “Ethernet Module” for specification. TPOUT+ 63 O — Ethernet differential signal output. TPOUT- 62 O — Ethernet differential signal output. TPIN+ 59 I Analog Ethernet differential signal input. TPIN- 58 I Analog Ethernet differential signal input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 32  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type TQFP MCLR 13 I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OSC1/CLKI 63 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in internal RC mode; CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC2/CLKO pin.) OSC2/CLKO 64 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In Internal RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. PORTA is a bidirectional I/O port. RA0/LEDA/AN0 35 RA0 I/O TTL Digital I/O. LEDA O — Ethernet LEDA indicator output. AN0 I Analog Analog Input 0. RA1/LEDB/AN1 34 RA1 I/O TTL Digital I/O. LEDB O — Ethernet LEDB indicator output. AN1 I Analog Analog Input 1. RA2/AN2/VREF- 33 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 32 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 42 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4 41 RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).  2011 Microchip Technology Inc. DS39762F-page 33

PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 5 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. FLT0 I ST Enhanced PWM Fault input (ECCP modules); enabled in software. RB1/INT1 6 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. RB2/INT2 7 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. RB3/INT3/ECCP2/P2A 8 RB3 I/O TTL Digital I/O. INT3 I ST External Interrupt 3. ECCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A(1) O — ECCP2 PWM Output A. RB4/KBI0 69 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1 68 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. RB6/KBI2/PGC 67 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 57 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 34  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 44 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/ECCP2/P2A 43 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. ECCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A(2) O — ECCP2 PWM Output A. RC2/ECCP1/P1A 53 RC2 I/O ST Digital I/O. ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O — ECCP1 PWM Output A. RC3/SCK1/SCL1 54 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI1/SDA1 55 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O ST I2C data I/O. RC5/SDO1 56 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. RC6/TX1/CK1 45 RC6 I/O ST Digital I/O. TX1 O — EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1 pin). RC7/RX1/DT1 46 RC7 I/O ST Digital I/O. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1 pin). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).  2011 Microchip Technology Inc. DS39762F-page 35

PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTD is a bidirectional I/O port. RD0/AD0/PSP0 92 RD0 I/O ST Digital I/O. AD0 I/O TTL External Memory Address/Data 0. PSP0 I/O TTL Parallel Slave Port data. RD1/AD1/PSP1 91 RD1 I/O ST Digital I/O. AD1 I/O TTL External Memory Address/Data 1. PSP1 I/O TTL Parallel Slave Port data. RD2/AD2/PSP2 90 RD2 I/O ST Digital I/O. AD2 I/O TTL External Memory Address/Data 2. PSP2 I/O TTL Parallel Slave Port data. RD3/AD3/PSP3 89 RD3 I/O ST Digital I/O. AD3 I/O TTL External Memory Address/Data 3. PSP3 I/O TTL Parallel Slave Port data. RD4/AD4/PSP4/SDO2 88 RD4 I/O ST Digital I/O. AD4 I/O TTL External Memory Address/Data 4. PSP4 I/O TTL Parallel Slave Port data. SDO2 O — SPI data out. RD5/AD5/PSP5/ 87 SDI2/SDA2 RD5 I/O ST Digital I/O. AD5 I/O TTL External Memory Address/Data 5. PSP5 I/O TTL Parallel Slave Port data. SDI2 I ST SPI data in. SDA2 I/O ST I2C™ data I/O. RD6/AD6/PSP6/ 84 SCK2/SCL2 RD6 I/O ST Digital I/O. AD6 I/O TTL External Memory Address/Data 6. PSP6 I/O TTL Parallel Slave Port data. SCK2 I/O ST Synchronous serial clock input/output for SPI mode. SCL2 I/O ST Synchronous serial clock input/output for I2C™ mode. RD7/AD7/PSP7/SS2 83 RD7 I/O ST Digital I/O. AD7 I/O TTL External Memory Address/Data 7. PSP7 I/O TTL Parallel Slave Port data. SS2 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 36  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTE is a bidirectional I/O port. RE0/AD8/RD/P2D 4 RE0 I/O ST Digital I/O. AD8 I/O TTL External Memory Address/Data 8. RD I TTL Read control for Parallel Slave Port. P2D O — ECCP2 PWM Output D. RE1/AD9/WR/P2C 3 RE1 I/O ST Digital I/O. AD9 I/O TTL External Memory Address/Data 9. WR I TTL Write control for Parallel Slave Port. P2C O — ECCP2 PWM Output C. RE2/AD10/CS/P2B 98 RE2 I/O ST Digital I/O. AD10 I/O TTL External Memory Address/Data 10. CS I TTL Chip select control for Parallel Slave Port. P2B O — ECCP2 PWM Output B. RE3/AD11/P3C 97 RE3 I/O ST Digital I/O. AD11 I/O TTL External Memory Address/Data 11. P3C(3) O — ECCP3 PWM Output C. RE4/AD12/P3B 96 RE4 I/O ST Digital I/O. AD12 I/O TTL External Memory Address/Data 12. P3B(3) O — ECCP3 PWM Output B. RE5/AD13/P1C 95 RE5 I/O ST Digital I/O. AD13 I/O TTL External Memory Address/Data 13. P1C(3) O — ECCP1 PWM Output C. RE6/AD14/P1B 94 RE6 I/O ST Digital I/O. AD14 I/O TTL External Memory Address/Data 14. P1B(3) O — ECCP1 PWM Output B. RE7/AD15/ECCP2/P2A 93 RE7 I/O ST Digital I/O. AD15 I/O TTL External Memory Address/Data 15. ECCP2(4) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A(4) O — ECCP2 PWM Output A. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).  2011 Microchip Technology Inc. DS39762F-page 37

PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTF is a bidirectional I/O port. RF0/AN5 12 RF0 I/O ST Digital I/O. AN5 I Analog Analog Input 5. RF1/AN6/C2OUT 28 RF1 I/O ST Digital I/O. AN6 I Analog Analog Input 6. C2OUT O — Comparator 2 output. RF2/AN7/C1OUT 23 RF2 I/O ST Digital I/O. AN7 I Analog Analog Input 7. C1OUT O — Comparator 1 output. RF3/AN8 22 RF3 I/O ST Digital I/O. AN8 I Analog Analog Input 8. RF4/AN9 21 RF4 I/O ST Digital I/O. AN9 I Analog Analog Input 9. RF5/AN10/CVREF 20 RF5 I/O ST Digital I/O. AN10 I Analog Analog Input 10. CVREF O — Comparator reference voltage output. RF6/AN11 19 RF6 I/O ST Digital I/O. AN11 I Analog Analog Input 11. RF7/SS1 18 RF7 I/O ST Digital I/O. SS1 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 38  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTG is a bidirectional I/O port. RG0/ECCP3/P3A 71 RG0 I/O ST Digital I/O. ECCP3 I/O ST Capture 3 input/Compare 3 output/PWM3 output. P3A O — ECCP3 PWM Output A. RG1/TX2/CK2 70 RG1 I/O ST Digital I/O. TX2 O — EUSART2 asynchronous transmit. CK2 I/O ST EUSART2 synchronous clock (see related RX2/DT2 pin). RG2/RX2/DT2 52 RG2 I/O ST Digital I/O. RX2 I ST EUSART2 asynchronous receive. DT2 I/O ST EUSART2 synchronous data (see related TX2/CK2 pin). RG3/CCP4/P3D 51 RG3 I/O ST Digital I/O. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM4 output. P3D O — ECCP3 PWM Output D. RG4/CCP5/P1D 14 RG4 I/O ST Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM5 output. P1D O — ECCP1 PWM Output D. RG5 11 I/O ST Digital I/O. RG6 10 I/O ST Digital I/O. RG7 38 I/O ST Digital I/O. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).  2011 Microchip Technology Inc. DS39762F-page 39

PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTH is a bidirectional I/O port. RH0/A16 99 RH0 I/O ST Digital I/O. A16 O — External Memory Address 16. RH1/A17 100 RH1 I/O ST Digital I/O. A17 O — External Memory Address 17. RH2/A18 1 RH2 I/O ST Digital I/O. A18 O — External Memory Address 18. RH3/A19 2 RH3 I/O ST Digital I/O. A19 O — External Memory Address 19. RH4/AN12/P3C 27 RH4 I/O ST Digital I/O. AN12 I Analog Analog Input 12. P3C(5) O — ECCP3 PWM Output C. RH5/AN13/P3B 26 RH5 I/O ST Digital I/O. AN13 I Analog Analog Input 13. P3B(5) O — ECCP3 PWM Output B. RH6/AN14/P1C 25 RH6 I/O ST Digital I/O. AN14 I Analog Analog Input 14. P1C(5) O — ECCP1 PWM Output C. RH7/AN15/P1B 24 RH7 I/O ST Digital I/O. AN15 I Analog Analog Input 15. P1B(5) O — ECCP1 PWM Output B. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 40  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTJ is a bidirectional I/O port. RJ0/ALE 49 RJ0 I/O ST Digital I/O. ALE O — External memory address latch enable. RJ1/OE 50 RJ1 I/O ST Digital I/O. OE O — External memory output enable. RJ2/WRL 66 RJ2 I/O ST Digital I/O. WRL O — External memory write low control. RJ3/WRH 61 RJ3 I/O ST Digital I/O. WRH O — External memory write high control. RJ4/BA0 47 RJ4 I/O ST Digital I/O. BA0 O — External Memory Byte Address 0 control. RJ5/CE 48 RJ5 I/O ST Digital I/O CE O — External memory chip enable control. RJ6/LB 58 RJ6 I/O ST Digital I/O. LB O — External memory low byte control. RJ7/UB 39 RJ7 I/O ST Digital I/O. UB O — External memory high byte control. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).  2011 Microchip Technology Inc. DS39762F-page 41

PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP NC 9 — — No connect. VSS 15, 36, 40, P — Ground reference for logic and I/O pins. 60, 65, 85 VDD 17, 37, 59, P — Positive supply for peripheral digital logic and I/O pins. 62, 86 AVSS 31 P — Ground reference for analog modules. AVDD 30 P — Positive supply for analog modules. ENVREG 29 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP 16 Core logic power or external filter capacitor connection. VDDCORE P — Positive supply for microcontroller core logic (regulator disabled). VCAP P — External filter capacitor connection (regulator enabled). VSSPLL 82 P — Ground reference for Ethernet PHY PLL. VDDPLL 81 P — Positive 3.3V supply for Ethernet PHY PLL. VSSTX 79 P — Ground reference for Ethernet PHY transmit subsystem. VDDTX 76 P — Positive 3.3V supply for Ethernet PHY transmit subsystem. VSSRX 72 P — Ground reference for Ethernet PHY receive subsystem. VDDRX 75 P — Positive 3.3V supply for Ethernet PHY receive subsystem. RBIAS 80 I Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor; see Section19.0 “Ethernet Module” for specification. TPOUT+ 78 O — Ethernet differential signal output. TPOUT- 77 O — Ethernet differential signal output. TPIN+ 74 I Analog Ethernet differential signal input. TPIN- 73 I Analog Ethernet differential signal input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 42  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH PIC18FJ MINIMUM CONNECTIONS MICROCONTROLLERS C2(2) 2.1 Basic Connection Requirements VDD Getting started with the PIC18F97J60 family family of R1 DD SS (1) (1) 8-bit microcontrollers requires attention to a minimal V V R2 set of device pin connections before proceeding with MCLR ENVREG development. VCAP/VDDCORE C1 The following pins must always be connected: C7 PIC18FXXJXX • All VDD and VSS pins (see Section2.2 “Power Supply Pins”) VSS VDD C6(2) C3(2) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S VSS D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(2) C4(2) • ENVREG (if implemented) and VCAP/VDDCORE pins (see Section2.4 “Voltage Regulator Pins (ENVREG and VCAP/VDDCORE)”) Key (all values are recommendations): These pins must also be connected if they are being C1 through C6: 0.1 F, 20V ceramic used in the end application: C7: 10 F, 6.3V or greater, tantalum or ceramic • PGC/PGD pins used for In-Circuit Serial R1: 10 kΩ Programming™ (ICSP™) and debugging purposes R2: 100Ω to 470Ω (see Section2.5 “ICSP Pins”) Note 1: See Section2.4 “Voltage Regulator Pins • OSCI and OSCO pins when an external oscillator (ENVREG and VCAP/VDDCORE)” for source is used explanation of ENVREG pin connections. (see Section2.6 “External Oscillator Pins”) 2: The example shown is for a PIC18F device Additionally, the following pins may be required: with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; • VREF+/VREF- pins are used when external voltage adjust the number of decoupling capacitors reference for analog modules is implemented appropriately. Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1.  2011 Microchip Technology Inc. DS39762F-page 43

PIC18F97J60 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: Device Reset, and Device Programming The use of decoupling capacitors on every pair of and Debugging. If programming and debugging are power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct AVSS, is required. connection to VDD may be all that is required. The Consider the following criteria when using decoupling addition of other components, to help increase the capacitors: application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical • Value and type of capacitor: A 0.1 F (100 nF), configuration is shown in Figure2-1. Other circuit 10-20V capacitor is recommended. The capacitor designs may be implemented, depending on the should be a low-ESR device, with a resonance application’s requirements. frequency in the range of 200MHz and higher. Ceramic capacitors are recommended. During programming and debugging, the resistance • Placement on the printed circuit board: The and capacitance that can be added to the pin must decoupling capacitors should be placed as close be considered. Device programmers and debuggers to the pins as possible. It is recommended to drive the MCLR pin. Consequently, specific voltage place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the capacitor can be placed on another layer on the application and PCB requirements. For example, it is PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated length from the pin to the capacitor is no greater from the MCLR pin during programming and than 0.25inch (6mm). debugging operations by using a jumper (Figure2-2). • Handling high-frequency noise: If the board is The jumper is replaced for normal run-time experiencing high-frequency noise (upward of operations. tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling Any components associated with the MCLR pin capacitor. The value of the second capacitor can should be placed within 0.25 inch (6mm) of the pin. be in the range of 0.01F to 0.001F. Place this second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN capacitor. In high-speed circuit designs, consider CONNECTIONS implementing a decade pair of capacitances as close to the power and ground pins as possible VDD (e.g., 0.1F in parallel with 0.001F). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the JP PIC18FXXJXX decoupling capacitors are first in the power chain. Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R1 10k is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10k. Ensure that the On boards with power traces running longer than MCLR pin VIH and VIL specifications are met. sixinches in length, it is suggested to use a tank capac- 2: R2470 will limit any current flowing into itor for integrated circuits, including microcontrollers, to MCLR from the external capacitor, C, in the supply a local power source. The value of the tank event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical capacitor should be determined based on the trace Overstress (EOS). Ensure that the MCLR pin resistance that connects the power supply source to VIH and VIL specifications are met. the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7F to 47F. DS39762F-page 44  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 2.4 Voltage Regulator Pins (ENVREG Note that the “LF” versions of some low pin count and VCAP/VDDCORE) PIC18FJ parts (e.g., the PIC18LF45J10) do not have the ENVREG pin. These devices are provided with the The on-chip voltage regulator enable pin, ENVREG, voltage regulator permanently disabled; they must must always be connected directly to either a supply always be provided with a supply voltage on the voltage or to ground. Tying ENVREG to VDD enables VDDCORE pin. the regulator, while tying it to ground disables the regulator. Refer to Section25.3 “On-Chip Voltage FIGURE 2-3: FREQUENCY vs. ESR Regulator” for details on connecting and using the PERFORMANCE FOR on-chip regulator. SUGGESTED VCAP When the regulator is enabled, a low-ESR (<5Ω) 10 capacitor is required on the VCAP/VDDCORE pin to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD and 1 must use a capacitor of 10 µF connected to ground. The type can be ceramic or tantalum. Suitable examples of ) capacitors are shown in Table2-1. Capacitors with R ( 0.1 S equivalent specifications can be used. E Designers may use Figure2-3 to evaluate ESR 0.01 equivalence of candidate devices. It is recommended that the trace length not exceed 0.001 0.01 0.1 1 10 100 1000 10,000 0.25inch (6mm). Refer to 28.0 “Electrical Frequency (MHz) Characteristics” for additional information. Note: Typical data measurement at 25°C, 0V DC bias. When the regulator is disabled, the VCAP/VDDCORE pin must be tied to a voltage supply at the VDDCORE level. Refer to 28.0 “Electrical Characteristics” for information on VDD and VDDCORE. . TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Nominal Make Part # Base Tolerance Rated Voltage Temp. Range Capacitance TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC  2011 Microchip Technology Inc. DS39762F-page 45

PIC18F97J60 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC FIGURE 2-4: DC BIAS VOLTAGE vs. CAPACITORS CAPACITANCE CHARACTERISTICS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic %) 10 e ( 0 capacitors very attractive in many types of applications. ng-10 16V Capacitor ha-20 Ceramic capacitors are suitable for use with the C-30 VDDCORE voltage regulator of this microcontroller. ance --5400 10V Capacitor However, some care is needed in selecting the capac- cit-60 itor to ensure that it maintains sufficient capacitance Capa--8700 6.3V Capacitor over the intended operating range of the application. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage (VDC) Typical low-cost, 10µF ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial toler- When selecting a ceramic capacitor to be used with the ance specifications for these types of capacitors are VDDCORE voltage regulator, it is suggested to select a often specified as ±10% to ±20% (X5R and X7R), or high-voltage rating, so that the operating voltage is a -20%/+80% (Y5V). However, the effective capacitance small percentage of the maximum rated capacitor volt- that these capacitors provide in an application circuit will age. For example, choose a ceramic capacitor rated at also vary based on additional factors, such as the 16V for the 2.5V VDDCORE voltage. Suggested applied DC bias voltage and the temperature. The total capacitors are shown in Table2-1. in-circuit tolerance is, therefore, much wider than the initial tolerance specification. 2.5 ICSP Pins The X5R and X7R capacitors typically exhibit satisfac- The PGC and PGD pins are used for In-Circuit Serial tory temperature stability (ex: ±15% over a wide Programming™ (ICSP™) and debugging purposes. It temperature range, but consult the manufacturer's data is recommended to keep the trace length between the sheets for exact specifications). However, Y5V capaci- ICSP connector and the ICSP pins on the device as tors typically have extreme temperature tolerance short as possible. If the ICSP connector is expected to specifications of +22%/-82%. Due to the extreme experience an ESD event, a series resistor is recom- temperature tolerance, a 10µF nominal rated Y5V type mended, with the value in the range of a few tens of capacitor may not deliver enough total capacitance to ohms, not to exceed 100Ω. meet minimum VDDCORE voltage regulator stability and Pull-up resistors, series diodes, and capacitors on the transient response requirements. Therefore, Y5V PGC and PGD pins are not recommended as they will capacitors are not recommended for use with the interfere with the programmer/debugger communica- VDDCORE regulator if the application must operate over tions to the device. If such discrete components are an a wide temperature range. application requirement, they should be removed from In addition to temperature tolerance, the effective the circuit during programming and debugging. Alter- capacitance of large value ceramic capacitors can vary natively, refer to the AC/DC characteristics and timing substantially, based on the amount of DC voltage requirements information in the respective device applied to the capacitor. This effect can be very signifi- Flash programming specification for information on cant, but is often overlooked or is not always capacitive loading limits, and pin input voltage high documented. (VIH) and input low (VIL) requirements. A typical DC bias voltage vs. capacitance graph for For device emulation, ensure that the “Communication X7R type and Y5V type capacitors is shown in Channel Select” (i.e., PGCx/PGDx pins), programmed Figure2-4. into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section27.0 “Development Support”. DS39762F-page 46  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: SUGGESTED PLACEMENT OF THE OSCILLATOR Many microcontrollers have options for at least two CIRCUIT oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Single-Sided and In-Line Layouts: Section3.0 “Oscillator Configurations” for details). Copper Pour Primary Oscillator The oscillator circuit should be placed on the same (tied to ground) Crystal side of the board as the device. Place the oscillator DEVICE PINS circuit close to the respective oscillator pins with no more than 0.5inch (12mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Primary OSC1 Oscillator of the board. C1 ` OSC2 Use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. The C2 GND grounded copper pour should be routed directly to the ` MCU ground. Do not run any signal traces or power T1OSO traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board T1OS I Timer1 Oscillator where the crystal is placed. Crystal ` Layout suggestions are shown in Figure2-5. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With T1 Oscillator: C1 T1 Oscillator: C2 fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts: ground layer. In all cases, the guard trace(s) must be returned to ground. Top Layer Copper Pour (tied to ground) In planning the application’s routing and I/O assign- ments, ensure that adjacent port pins, and other Bottom Layer signals in close proximity to the oscillator, are benign Copper Pour (i.e., free of high frequencies, short rise and fall times, (tied to ground) and other similar noise). OSCO For additional information and design guidance on oscillator circuits, please refer to these Microchip C2 Application Notes, available at the corporate web site Oscillator (www.microchip.com): GND Crystal • AN826, “Crystal Oscillator Basics and Crystal C1 Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” OSCI • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” 2.7 Unused I/Os DEVICE PINS Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the output to logic low.  2011 Microchip Technology Inc. DS39762F-page 47

PIC18F97J60 FAMILY NOTES: DS39762F-page 48  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 3.0 OSCILLATOR 3.2 Oscillator Types CONFIGURATIONS The PIC18F97J60 family of devices can be operated in five different oscillator modes: 3.1 Overview 1. HS High-Speed Crystal/Resonator Devices in the PIC18F97J60 family incorporate an 2. HSPLL High-Speed Crystal/Resonator oscillator and microcontroller clock system that differs with Software PLL Control from standard PIC18FXXJXX devices. The addition of 3. EC External Clock with FOSC/4 Output the Ethernet module, with its requirement for a stable 4. ECPLL External Clock with Software PLL 25 MHz clock source, makes it necessary to provide a Control primary oscillator that can provide this frequency as 5. INTRC Internal 31kHz Oscillator well as a range of different microcontroller clock speeds. An overview of the oscillator structure is shown 3.2.1 OSCILLATOR CONTROL in Figure3-1. The oscillator mode is selected by programming the Other oscillator features used in PIC18FXXJXX FOSC<2:0> Configuration bits. FOSC<1:0> bits select enhanced microcontrollers, such as the internal RC the default primary oscillator modes, while FOSC2 oscillator and clock switching, remain the same. They selects when INTRC may be invoked. are discussed later in this chapter. The OSCCON register (Register3-2) selects the Active Clock mode. It is primarily used in controlling clock switching in power-managed modes. Its use is discussed in Section3.7.1 “Oscillator Control Register”. The OSCTUNE register (Register3-1) is used to select the system clock frequency from the primary oscillator source by selecting combinations of prescaler/postscaler settings and enabling the PLL. Its use is described in Section3.6.1 “PLL Block”. FIGURE 3-1: PIC18F97J60 FAMILY CLOCK DIAGRAM Primary Oscillator PIC18F97J60 Family Ethernet Clock OSC2 Sleep PLL/Prescaler/Postscaler OSCTUNE<7:5>(1) OSC1 PLL PLL Clock FOSC<2:0> Prescaler 5x PLL Postscaler Control OSCCON <1:0> EC, HS, ECPLL, HSPLL Secondary Oscillator X Peripherals T1OSO U T1OSC M T1OSCEN Enable T1OSI Oscillator SINoTuRrcCe Internal Oscillator CPU IDLEN WDT, PWRT, FSCM and Two-Speed Start-up Clock Source Option for Other Modules Note 1: See Table3-2 for OSCTUNE register configurations and their corresponding frequencies.  2011 Microchip Technology Inc. DS39762F-page 49

PIC18F97J60 FAMILY 3.3 Crystal Oscillator/Ceramic Note1: Higher capacitance increases the stabil- Resonators (HS Modes) ity of the oscillator but also increases the start-up time. In HS or HSPLL Oscillator modes, a crystal is connected to the OSC1 and OSC2 pins to establish 2: Since each crystal has its own character- oscillation. Figure3-2 shows the pin connections. istics, the user should consult the crystal manufacturer for appropriate values of The oscillator design requires the use of a crystal that external components. is rated for parallel resonant operation. 3: Rs may be required to avoid overdriving Note: Use of a crystal rated for series resonant crystals with low drive level specifications. operation may give a frequency out of the 4: Always verify oscillator performance over crystal manufacturer’s specifications. the VDD and temperature range that is expected for the application. FIGURE 3-2: CRYSTAL OSCILLATOR OPERATION (HS OR 3.4 External Clock Input (EC Modes) HSPLL CONFIGURATION) The EC and ECPLL Oscillator modes require an exter- C1(1) OSC1 nal clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a To Power-on Reset or after an exit from Sleep mode. Internal XTAL RF(3) Logic In the EC Oscillator mode, the oscillator frequency, divided by 4, is available on the OSC2 pin. This signal Sleep OSC2 may be used for test purposes or to synchronize other C2(1) RS(2) PIC18FXXJ6X logic. Figure3-3 shows the pin connections for the EC Oscillator mode. Note 1: See Table3-1 for initial values of C1 and C2. FIGURE 3-3: EXTERNAL CLOCK 2: A series resistor (RS) may be required for crystals with a low drive specification. INPUT OPERATION 3: RF varies with the oscillator mode chosen. (EC CONFIGURATION) TABLE 3-1: CAPACITOR SELECTION FOR Clock from OSC1/CLKI CRYSTAL OSCILLATOR Ext. System PIC18FXXJ6X Typical Capacitor Values FOSC/4 OSC2/CLKO Crystal Tested: Osc Type Freq. C1 C2 An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure3-4. In HS 25 MHz 33 pF 33 pF this configuration, the OSC2 pin is left open. Current Capacitor values are for design guidance only. consumption in this configuration will be somewhat Different capacitor values may be required to produce higher than EC mode, as the internal oscillator’s acceptable oscillator operation. The user should test feedback circuitry will be enabled (in EC mode, the the performance of the oscillator over the expected feedback circuit is disabled). VDD and temperature range for the application. Refer to the following application notes for oscillator specific FIGURE 3-4: EXTERNAL CLOCK information: INPUT OPERATION • AN588, “PIC® Microcontroller Oscillator Design (HS CONFIGURATION) Guide” • AN826, “Crystal Oscillator Basics and Crystal Clock from OSC1 Selection for rfPIC® and PIC® Devices” Ext. System PIC18FXXJ6X • AN849, “Basic PIC® Oscillator Design” (HS Mode) • AN943, “Practical PIC® Oscillator Analysis and Open OSC2 Design” • AN949, “Making Your Oscillator Work” See the notes following this table for additional information. DS39762F-page 50  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 3.5 Internal Oscillator Block used for Ethernet applications. No provision is made for internally generating the required Ethernet clock from a The PIC18F97J60 family of devices includes an internal primary oscillator source of a different frequency. A oscillator source (INTRC) which provides a nominal frequency tolerance is specified, likely excluding the use 31kHz output. The INTRC is enabled on device of ceramic resonators. See Section28.0 “Electrical power-up and clocks the device during its configuration Characteristics”, Table28-6, Parameter 5, for more cycle until it enters operating mode. INTRC is also details. enabled if it is selected as the device clock source or if any of the following are enabled: 3.6.1 PLL BLOCK • Fail-Safe Clock Monitor To accommodate a range of applications and micro- • Watchdog Timer controller clock speeds, a separate PLL block is • Two-Speed Start-up incorporated into the clock system. It consists of three components: These features are discussed in greater detail in Section25.0 “Special Features of the CPU”. • A configurable prescaler (1:2 or 1:3) • A 5x PLL frequency multiplier The INTRC can also be optionally configured as the • A configurable postscaler (1:1, 1:2, or 1:3) default clock source on device start-up by setting the FOSC2 Configuration bit. This is discussed in The operation of the PLL block’s components is Section3.7.1 “Oscillator Control Register”. controlled by the OSCTUNE register (Register3-1). The use of the PLL block’s prescaler and postscaler, 3.6 Ethernet Operation and the with or without the PLL itself, provides a range of Microcontroller Clock system clock frequencies to choose from, including the unaltered 25MHz of the primary oscillator. The full Although devices of the PIC18F97J60 family can accept range of possible oscillator configurations compatible a wide range of crystals and external oscillator inputs, with Ethernet operation is shown in Table3-2. they must always have a 25MHz clock source when REGISTER 3-1: OSCTUNE: PLL BLOCK CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 PPST1 PLLEN(1) PPST0 PPRE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PPST1: PLL Postscaler Configuration bit 1 = Divide-by-2 0 = Divide-by-3 bit 6 PLLEN: 5x Frequency Multiplier PLL Enable bit(1) 1 = PLL is enabled 0 = PLL is disabled bit 5 PPST0: PLL Postscaler Enable bit 1 = Postscaler is enabled 0 = Postscaler is disabled bit 4 PPRE: PLL Prescaler Configuration bit 1 = Divide-by-2 0 = Divide-by-3 bit 3-0 Unimplemented: Read as ‘0’ Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and is read as ‘0’.  2011 Microchip Technology Inc. DS39762F-page 51

PIC18F97J60 FAMILY TABLE 3-2: DEVICE CLOCK SPEEDS FOR VARIOUS PLL BLOCK CONFIGURATIONS PLL Block Clock Frequency 5x PLL PLL Prescaler PLL Postscaler Configuration (MHz) (OSCTUNE<7:4>) Disabled x101 (Note 1) 2 2 1111 31.2500 3 0111 20.8333 Enabled Disabled x100 41.6667 3 2 1110 20.8333 3 0110 13.8889 Disabled(2) Disabled x00x 25 (Default) 2 1011 6.2500 2 Disabled 3 0011 4.1667 2 1010 4.1667 3 3 0010 2.7778 Legend: x = Don’t care Note 1: Reserved configuration; represents a clock frequency beyond the microcontroller’s operating range. 2: The prescaler is automatically disabled when the PLL and postscaler are both disabled. 3.7 Clock Sources and Oscillator The secondary oscillators are those external sources Switching not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller The PIC18F97J60 family of devices includes a feature is placed in a power-managed mode. The PIC18F97J60 that allows the device clock source to be switched from family of devices offers the Timer1 oscillator as a second- the main oscillator to an alternate clock source. These ary oscillator. In all power-managed modes, this oscillator devices also offer two alternate clock sources. When is often the time base for functions such as a Real-Time an alternate clock source is enabled, the various Clock (RTC). power-managed operating modes are available. Most often, a 32.768kHz watch crystal is connected Essentially, there are three clock sources for these between the RC0/T1OSO/T13CKI and RC1/T1OSI devices: pins. Loading capacitors are also connected from each • Primary oscillators pin to ground. The Timer1 oscillator is discussed in greater detail in Section13.3 “Timer1 Oscillator”. • Secondary oscillators • Internal oscillator block In addition to being a primary clock source, the internal oscillator is available as a power-managed mode The primary oscillators include the External Crystal clock source. The INTRC source is also used as the and Resonator modes and the External Clock modes. clock source for several special features, such as the The particular mode is defined by the FOSC<2:0> WDT and Fail-Safe Clock Monitor. Configuration bits. The details of these modes are covered earlier in this chapter. The clock sources for the PIC18F97J60 family devices are shown in Figure3-1. See Section25.0 “Special Features of the CPU” for Configuration register details. DS39762F-page 52  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 3.7.1 OSCILLATOR CONTROL REGISTER The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP The OSCCON register (Register3-2) controls several instruction is executed. aspects of the device clock’s operation, both in full-power operation and in power-managed modes. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section4.0 The System Clock Select bits, SCS<1:0>, select the “Power-Managed Modes”. clock source. The available clock sources are the primary clock (defined by the FOSC<2:0> Configura- Note1: The Timer1 oscillator must be enabled to tion bits), the secondary clock (Timer1 oscillator) and select the secondary clock source. The the internal oscillator. The clock source changes after Timer1 oscillator is enabled by setting the one or more of the bits are changed, following a brief T1OSCEN bit in the Timer1 Control reg- clock transition interval. ister (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select The OSTS (OSCCON<3>) and T1RUN (T1CON<6>) a secondary clock source will be ignored. bits indicate which clock source is currently providing the device clock. The T1RUN bit indicates when the 2: It is recommended that the Timer1 Timer1 oscillator is providing the device clock in oscillator be operating and stable before secondary clock modes. In power-managed modes, executing the SLEEP instruction or a very only one of these bits will be set at any time. If neither long delay may occur while the Timer1 bit is set, the INTRC source is providing the clock, or oscillator starts. the internal oscillator has just started and is not yet stable. REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 U-0 U-0 U-0 R-q U-0 R/W-0 R/W-0 IDLEN — — — OSTS(1) — SCS1 SCS0 bit 7 bit 0 Legend: q = Value determined by configuration R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 Unimplemented: Read as ‘0’ bit 3 OSTS: Oscillator Status bit(1) 1 = Device is running from oscillator source defined when SCS<1:0> = 00 0 = Device is running from oscillator source defined when SCS<1:0> = 01, 10 or 11 bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 11 = Internal oscillator 10 = Primary oscillator 01 = Timer1 oscillator When FOSC2 = 1; 00 = Primary oscillator When FOSC2 = 0; 00 = Internal oscillator Note 1: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.  2011 Microchip Technology Inc. DS39762F-page 53

PIC18F97J60 FAMILY 3.7.1.1 System Clock Selection and the In secondary clock modes (SEC_RUN and FOSC2 Configuration Bit SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may The SCS bits are cleared on all forms of Reset. In the also run in all power-managed modes if required to device’s default configuration, this means the primary clock Timer1 or Timer3. oscillator, defined by FOSC<1:0> (that is, one of the HC or EC modes), is used as the primary clock source In RC_RUN and RC_IDLE modes, the internal oscilla- on device Resets. tor provides the device clock source. The 31kHz INTRC output can be used directly to provide the clock The default clock configuration on Reset can be changed and may be enabled to support various special with the FOSC2 Configuration bit. This bit affects the features, regardless of the power-managed mode (see clock source selection setting when SCS<1:0>=00. Section25.2 “Watchdog Timer (WDT)” through When FOSC2=1 (default), the oscillator source Section25.5 “Fail-Safe Clock Monitor” for more defined by FOSC<1:0> is selected whenever information on WDT, Fail-Safe Clock Monitor and SCS<1:0>=00. When FOSC2=0, the INTRC oscillator Two-Speed Start-up). is selected whenever SCS<1:0>=00. Because the SCS bits are cleared on Reset, the FOSC2 setting also If the Sleep mode is selected, all clock sources are changes the default oscillator mode on Reset. stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current Regardless of the setting of FOSC2, INTRC will always consumption of the device (only leakage currents). be enabled on device power-up. It will serve as the clock source until the device has loaded its configura- Enabling any on-chip feature that will operate during tion values from memory. It is at this point that the Sleep will increase the current consumed during Sleep. FOSC Configuration bits are read and the oscillator The INTRC is required to support WDT operation. The selection of operational mode is made. Timer1 oscillator may be operating to support a Real-Time Clock. Other features may be operating that Note that either the primary clock or the internal do not require a device clock source (i.e., MSSP slave, oscillator will have two bit setting options, at any given PSP, INTx pins and others). Peripherals that may add time, depending on the setting of FOSC2. significant current consumption are listed in Section28.2 “DC Characteristics: Power-Down and 3.7.2 OSCILLATOR TRANSITIONS Supply Current PIC18F97J60 Family (Industrial)” PIC18F97J60 family devices contain circuitry to prevent clock “glitches” when switching between clock 3.9 Power-up Delays sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the Power-up delays are controlled by two timers, so that sum of two cycles of the old clock source and three to no external Reset circuitry is required for most applica- four cycles of the new clock source. This formula tions. The delays ensure that the device is kept in assumes that the new clock source is stable. Reset until the device power supply is stable under nor- mal circumstances, and the primary clock is operating Clock transitions are discussed in greater detail in and stable. For additional information on power-up Section4.1.2 “Entering Power-Managed Modes”. delays, see Section5.6 “Power-up Timer (PWRT)”. 3.8 Effects of Power-Managed Modes The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (Parameter 33, on the Various Clock Sources Table28-12); it is always enabled. When PRI_IDLE mode is selected, the designated The second timer is the Oscillator Start-up Timer primary oscillator continues to run without interruption. (OST), intended to keep the chip in Reset until the For all other power-managed modes, the oscillator crystal oscillator is stable (HS modes). The OST does using the OSC1 pin is disabled. The OSC1 pin (and this by counting 1024 oscillator cycles before allowing OSC2 pin if used by the oscillator) will stop oscillating. the oscillator to clock the device. There is a delay of interval, TCSD (Parameter 38, Table28-12), following POR, while the controller becomes ready to execute instructions. TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output) HS, HSPLL Feedback inverter is disabled at quiescent Feedback inverter is disabled at quiescent voltage level voltage level Note: See Table5-2 in Section5.0 “Reset” for time-outs due to Sleep and MCLR Reset. DS39762F-page 54  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 4.0 POWER-MANAGED MODES 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three The PIC18F97J60 family devices provide the ability to clock sources for power-managed modes. They are: manage power consumption by simply managing clock- ing to the CPU and the peripherals. In general, a lower • The primary clock, as defined by the FOSC<2:0> clock frequency and a reduction in the number of circuits Configuration bits being clocked constitutes lower consumed power. For • The secondary clock (Timer1 oscillator) the sake of managing power in an application, there are • The internal oscillator three primary modes of operation: • Run mode 4.1.2 ENTERING POWER-MANAGED MODES • Idle mode • Sleep mode Switching from one power-managed mode to another begins by loading the OSCCON register. The These modes define which portions of the device are SCS<1:0> bits select the clock source and determine clocked and at what speed. The Run and Idle modes which Run or Idle mode is to be used. Changing these may use any of the three available clock sources bits causes an immediate switch to the new clock (primary, secondary or internal oscillator block); the source, assuming that it is running. The switch may Sleep mode does not use a clock source. also be subject to clock transition delays. These are The power-managed modes include several discussed in Section4.1.3 “Clock Transitions and power-saving features offered on previous PIC® MCU Status Indicators” and subsequent sections. devices. One is the clock switching feature, offered in Entry to the power-managed Idle or Sleep modes is other PIC18 devices, allowing the controller to use the triggered by the execution of a SLEEP instruction. The Timer1 oscillator in place of the primary oscillator. Also actual mode that results depends on the status of the included is the Sleep mode, offered by all PIC MCU IDLEN bit. devices, where all device clocks are stopped. Depending on the current mode and the mode being 4.1 Selecting Power-Managed Modes switched to, a change to a power-managed mode does not always require setting all of these bits. Many Selecting a power-managed mode requires two transitions may be done by changing the oscillator decisions: if the CPU is to be clocked or not and which select bits, or changing the IDLEN bit, prior to issuing a clock source is to be used. The IDLEN bit SLEEP instruction. If the IDLEN bit is already (OSCCON<7>) controls CPU clocking, while the configured correctly, it may only be necessary to SCS<1:0> bits (OSCCON<1:0>) select the clock perform a SLEEP instruction to switch to the desired source. The individual modes, bit settings, clock sources mode. and affected modules are summarized in Table4-1. TABLE 4-1: POWER-MANAGED MODES OSCCON<7,1:0> Module Clocking Mode Available Clock and Oscillator Source IDLEN(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 10 Clocked Clocked Primary – HS, EC, HSPLL, ECPLL; this is the normal, full-power execution mode SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 11 Clocked Clocked Internal Oscillator PRI_IDLE 1 10 Off Clocked Primary – HS, EC, HSPLL, ECPLL SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 11 Off Clocked Internal Oscillator Note 1: IDLEN reflects its value when the SLEEP instruction is executed.  2011 Microchip Technology Inc. DS39762F-page 55

PIC18F97J60 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS 4.2.2 SEC_RUN MODE INDICATORS The SEC_RUN mode is the compatible mode to the The length of the transition between clock sources is “clock switching” feature offered in other PIC18 the sum of two cycles of the old clock source and three devices. In this mode, the CPU and peripherals are to four cycles of the new clock source. This formula clocked from the Timer1 oscillator. This gives users the assumes that the new clock source is stable. option of lower power consumption while still using a high accuracy clock source. Two bits indicate the current clock source and its status: OSTS (OSCCON<3>) and T1RUN SEC_RUN mode is entered by setting the SCS<1:0> (T1CON<6>). In general, only one of these bits will be bits to ‘01’. The device clock source is switched to the set while in a given power-managed mode. When the Timer1 oscillator (see Figure4-1), the primary OSTS bit is set, the primary clock is providing the oscillator is shut down, the T1RUN bit (T1CON<6>) is device clock. When the T1RUN bit is set, the Timer1 set and the OSTS bit is cleared. oscillator is providing the clock. If neither of these bits is set, INTRC is clocking the device. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN Note: Executing a SLEEP instruction does not mode. If the T1OSCEN bit is not set when necessarily place the device into Sleep the SCS<1:0> bits are set to ‘01’, entry to mode. It acts as the trigger to place the SEC_RUN mode will not occur. If the controller into either the Sleep mode, or Timer1 oscillator is enabled, but not yet one of the Idle modes, depending on the running, device clocks will be delayed until setting of the IDLEN bit. the oscillator has started. In such situations, initial oscillator operation is far 4.1.4 MULTIPLE SLEEP COMMANDS from stable and unpredictable operation may result. The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the On transitions from SEC_RUN mode to PRI_RUN, the IDLEN bit at the time the instruction is executed. If peripherals and CPU continue to be clocked from the another SLEEP instruction is executed, the device will Timer1 oscillator while the primary clock is started. enter the power-managed mode specified by IDLEN at When the primary clock becomes ready, a clock switch that time. If IDLEN has changed, the device will enter the back to the primary clock occurs (see Figure4-2). new power-managed mode specified by the new setting. When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is 4.2 Run Modes providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator In the Run modes, clocks to both the core and continues to run. peripherals are active. The difference between these modes is the clock source. 4.2.1 PRI_RUN MODE The PRI_RUN mode is the normal, full-power execu- tion mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section25.4 “Two-Speed Start-up” for details). In this mode, the OSTS bit is set. (see Section3.7.1 “Oscillator Control Register”). DS39762F-page 56  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI 1 2 3 n-1 n OSC1 Clock Transition CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 SCS<1:0> bits Changed OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale.  2011 Microchip Technology Inc. DS39762F-page 57

PIC18F97J60 FAMILY 4.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC In RC_RUN mode, the CPU and peripherals are while the primary clock is started. When the primary clocked from the internal oscillator; the primary clock is clock becomes ready, a clock switch to the primary shut down. This mode provides the best power conser- clock occurs (see Figure4-4). When the clock switch is vation of all the Run modes while still executing code. complete, the OSTS bit is set and the primary clock is It works well for user applications which are not highly providing the device clock. The IDLEN and SCS bits timing-sensitive or do not require high-speed clocks at are not affected by the switch. The INTRC source will all times. continue to run if either the WDT or Fail-Safe Clock This mode is entered by setting SCS<1:0> to ‘11’. Monitor is enabled. When the clock source is switched to the INTRC (see Figure4-3), the primary oscillator is shut down and the OSTS bit is cleared. FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC 1 2 3 n-1 n OSC1 Clock Transition CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 SCS<1:0> bits Changed OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS39762F-page 58  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 4.3 Sleep Mode 4.4 Idle Modes The power-managed Sleep mode is identical to the The Idle modes allow the controller’s CPU to be legacy Sleep mode offered in all other PIC MCU selectively shut down while the peripherals continue to devices. It is entered by clearing the IDLEN bit (the operate. Selecting a particular Idle mode allows users default state on device Reset) and executing the to further manage power consumption. SLEEP instruction. This shuts down the selected If the IDLEN bit is set to ‘1’ when a SLEEP instruction is oscillator (Figure4-5). All clock source status bits are executed, the peripherals will be clocked from the clock cleared. source selected using the SCS<1:0> bits; however, the Entering the Sleep mode from any other mode does not CPU will not be clocked. The clock source status bits are require a clock switch. This is because no clocks are not affected. Setting IDLEN and executing a SLEEP needed once the controller has entered Sleep. If the instruction provides a quick method of switching from a WDT is selected, the INTRC source will continue to given Run mode to its corresponding Idle mode. operate. If the Timer1 oscillator is enabled, it will also If the WDT is selected, the INTRC source will continue continue to run. to operate. If the Timer1 oscillator is enabled, it will also When a wake event occurs in Sleep mode (by interrupt, continue to run. Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only exits until the clock source selected by the SCS<1:0> bits from any of the Idle modes are by interrupt, WDT becomes ready (see Figure4-6), or it will be clocked time-out or a Reset. When a wake event occurs, CPU from the internal oscillator if either the Two-Speed execution is delayed by an interval of TCSD Start-up or the Fail-Safe Clock Monitor is enabled (see (Parameter38, Table28-12) while it becomes ready to Section25.0 “Special Features of the CPU”). In execute code. When the CPU begins executing code, it either case, the OSTS bit is set when the primary clock resumes with the same clock source for the current Idle is providing the device clocks. The IDLEN and SCS bits mode. For example, when waking from RC_IDLE mode, are not affected by the wake-up. the internal oscillator block will clock the CPU and periph- erals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 PC + 6 Wake Event OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale.  2011 Microchip Technology Inc. DS39762F-page 59

PIC18F97J60 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes in that it does not disable the primary device peripherals continue to be clocked from the Timer1 clock. For timing-sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by set- the fastest resumption of device operation with its more ting the IDLEN bit and executing a SLEEP instruction. If accurate primary clock source, since the clock source the device is in another Run mode, set IDLEN first, then does not have to “warm up” or transition from another set SCS<1:0> to ‘01’ and execute SLEEP. When the oscillator. clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared PRI_IDLE mode is entered from PRI_RUN mode by and the T1RUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then set the SCS<1:0> bits to ‘10’ and execute be clocked from the Timer1 oscillator. After an interval SLEEP. Although the CPU is disabled, the peripherals of TCSD, following the wake event, the CPU begins exe- continue to be clocked from the primary clock source cuting code being clocked by the Timer1 oscillator. The specified by the FOSC<1:0> Configuration bits. The IDLEN and SCS bits are not affected by the wake-up; OSTS bit remains set (see Figure4-7). the Timer1 oscillator continues to run (see Figure4-8). When a wake event occurs, the CPU is clocked from the Note: The Timer1 oscillator should already be primary clock source. A delay of interval, TCSD, is running prior to entering SEC_IDLE mode. required between the wake event and when code If the T1OSCEN bit is not set when the execution starts. This is required to allow the CPU to SLEEP instruction is executed, the SLEEP become ready to execute instructions. After the instruction will be ignored and entry to wake-up, the OSTS bit remains set. The IDLEN and SEC_IDLE mode will not occur. If the SCS bits are not affected by the wake-up (see Timer1 oscillator is enabled, but not yet Figure4-8). running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program Counter PC Wake Event DS39762F-page 60  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 4.4.3 RC_IDLE MODE 4.5.2 EXIT BY WDT TIME-OUT In RC_IDLE mode, the CPU is disabled but the periph- A WDT time-out will cause different actions depending erals continue to be clocked from the internal oscillator. on which power-managed mode the device is in when This mode allows for controllable power conservation the time-out occurs. during Idle periods. If the device is not executing code (all Idle modes and From RC_RUN mode, RC_IDLE mode is entered by Sleep mode), the time-out will result in an exit from the setting the IDLEN bit and executing a SLEEP instruction. power-managed mode (see Section4.2 “Run If the device is in another Run mode, first set IDLEN, Modes” and Section4.3 “Sleep Mode”). If the device then clear the SCS bits and execute SLEEP. When the is executing code (all Run modes), the time-out will clock source is switched to the INTRC, the primary result in a WDT Reset (see Section25.2 “Watchdog oscillator is shut down and the OSTS bit is cleared. Timer (WDT)”). When a wake event occurs, the peripherals continue to The WDT timer and postscaler are cleared by one of be clocked from the INTRC. After a delay of TCSD the following events: following the wake event, the CPU begins executing • Executing a SLEEP or CLRWDT instruction code being clocked by the INTRC. The IDLEN and • The loss of a currently selected clock source (if SCS bits are not affected by the wake-up. The INTRC the Fail-Safe Clock Monitor is enabled) source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. 4.5.3 EXIT BY RESET 4.5 Exiting Idle and Sleep Modes Exiting an Idle or Sleep mode by Reset automatically forces the device to run from the INTRC. An exit from Sleep mode, or any of the Idle modes, is triggered by an interrupt, a Reset or a WDT time-out. 4.5.4 EXIT WITHOUT AN OSCILLATOR This section discusses the triggers that cause exits START-UP TIMER DELAY from power-managed modes. The clocking subsystem Certain exits from power-managed modes do not actions are discussed in each of the power-managed invoke the OST at all. There are two cases: modes sections (see Section4.2 “Run Modes”, Section4.3 “Sleep Mode” and Section4.4 “Idle • PRI_IDLE mode, where the primary clock source Modes”). is not stopped • The primary clock source is either the EC or 4.5.1 EXIT BY INTERRUPT ECPLL mode Any of the available interrupt sources can cause the In these instances, the primary clock source either device to exit from an Idle mode, or the Sleep mode, to does not require an oscillator start-up delay, since it is a Run mode. To enable this functionality, an interrupt already running (PRI_IDLE), or normally does not source must be enabled by setting its enable bit in one require an oscillator start-up delay (EC). However, a of the INTCON or PIE registers. The exit sequence is fixed delay of interval, TCSD, following the wake event initiated when the corresponding interrupt flag bit is set. is still required when leaving the Sleep and Idle modes to allow the CPU to prepare for execution. Instruction On all exits from Idle or Sleep modes by interrupt, code execution resumes on the first clock cycle following this execution branches to the interrupt vector if the delay. GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section10.0 “Interrupts”). A fixed delay of interval, TCSD, following the wake event is required when leaving the Sleep and Idle modes. This delay is required for the CPU to prepare for execu- tion. Instruction execution resumes on the first clock cycle following this delay.  2011 Microchip Technology Inc. DS39762F-page 61

PIC18F97J60 FAMILY NOTES: DS39762F-page 62  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 5.0 RESET A simplified block diagram of the on-chip Reset circuit is shown in Figure5-1. The PIC18F97J60 family of devices differentiates between various kinds of Reset: 5.1 RCON Register a) MCLR Reset during normal operation Device Reset events are tracked through the RCON b) MCLR Reset during power-managed modes register (Register5-1). The lower six bits of the register c) Power-on Reset (POR) indicate that a specific Reset event has occurred. In d) Brown-out Reset (BOR) most cases, these bits can only be set by the event and e) Configuration Mismatch (CM) must be cleared by the application after the event. The f) RESET Instruction state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is g) Stack Full Reset described in more detail in Section5.7 “Reset State h) Stack Underflow Reset of Registers”. i) Watchdog Timer (WDT) Reset during execution The RCON register also has a control bit for setting This section discusses Resets generated by hard interrupt priority (IPEN). Interrupt priority is discussed events (MCLR), power events (POR and BOR) and in Section10.0 “Interrupts”. Configuration Mismatches (CM). It also covers the operation of the various start-up timers. Stack Reset events are covered in Section6.1.6.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section25.2 “Watchdog Timer (WDT)”. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Configuration Word Mismatch Stack Full/Underflow Reset Stack Pointer External Reset MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset(1) S PWRT 32 s PWRT 66 ms Chip_Reset R Q INTRC 11-Bit Ripple Counter Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation.  2011 Microchip Technology Inc. DS39762F-page 63

PIC18F97J60 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0’ bit 5 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration Mismatch Reset occurs) bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Timer Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section5.4.1 “Detecting BOR” for more information. 3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39762F-page 64  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 5.2 Master Clear (MCLR) FIGURE 5-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering a hard SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller VDD VDD devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. D(1) R(2) The MCLR pin is not driven low by any internal Resets, R1(3) including the WDT. MCLR C 5.3 Power-on Reset (POR) PIC18FXXJ6X A Power-on Reset condition is generated on-chip whenever VDD rises above a certain threshold. This Note 1: External Power-on Reset circuit is required allows the device to start in the initialized state when only if the VDD power-up slope is too slow. The diode, D, helps discharge the capacitor VDD is adequate for operation. quickly when VDD powers down. To take advantage of the POR circuitry, tie the MCLR 2: R < 40k is recommended to make sure that pin through a resistor (1k to 10k) to VDD. This will the voltage drop across R does not violate eliminate external RC components usually needed to the device’s electrical specification. create a Power-on Reset delay. A minimum rise rate for 3: R1  1 k will limit any current flowing into VDD is specified (Parameter D004). For a slow rise MCLR from external capacitor, C, in the event time, see Figure5-2. of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD), or Electrical When the device starts normal operation (i.e., exits the Overstress (EOS). Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the 5.4.1 DETECTING BOR device must be held in Reset until the operating The BOR bit always resets to ‘0’ on any Brown-out conditions are met. Reset or Power-on Reset event. This makes it difficult POR events are captured by the POR bit (RCON<1>). to determine if a Brown-out Reset event has occurred The state of the bit is set to ‘0’ whenever a Power-on just by reading the state of BOR alone. A more reliable Reset occurs; it does not change for any other Reset method is to simultaneously check the state of both event. POR is not reset to ‘1’ by any hardware event. POR and BOR. This assumes that the POR bit is reset To capture multiple events, the user manually resets to ‘1’ in software immediately after any Power-on Reset the bit to ‘1’ in software following any Power-on Reset. event. If BOR is ‘0’ while POR is ‘1’, it can be reliably assumed that a Brown-out Reset event has occurred. 5.4 Brown-out Reset (BOR) If the voltage regulator is disabled, Brown-out Reset functionality is disabled. In this case, the BOR bit The PIC18F97J60 family of devices incorporates a cannot be used to determine a Brown-out Reset event. simple BOR function when the internal regulator is The BOR bit is still cleared by a Power-on Reset event. enabled (ENVREG pin is tied to VDD). Any drop of VDD below VBOR (Parameter D005), for greater than time, 5.5 Configuration Mismatch (CM) TBOR (Parameter 35), will reset the device. A Reset may or may not occur if VDD falls below VBOR for less The Configuration Mismatch (CM) Reset is designed to than TBOR. The chip will remain in Brown-out Reset detect and attempt to recover from random, memory until VDD rises above VBOR. corrupting events. These include Electrostatic Once a BOR has occurred, the Power-up Timer will Discharge (ESD) events which can cause widespread keep the chip in Reset for TPWRT (Parameter33). If single-bit changes throughout the device and result in VDD drops below VBOR while the Power-up Timer is catastrophic failure. running, the chip will go back into a Brown-out Reset In PIC18FXXJ Flash devices, the device Configuration and the Power-up Timer will be initialized. Once VDD registers (located in the configuration memory space) rises above VBOR, the Power-up Timer will execute the are continuously monitored during operation by com- additional time delay. paring their values to complimentary shadow registers. If a mismatch is detected between the two sets of registers, a CM Reset automatically occurs. These events are captured by the CM bit (RCON<5>). The state of the bit is set to ‘0’ whenever a CM event occurs; it does not change for any other Reset event.  2011 Microchip Technology Inc. DS39762F-page 65

PIC18F97J60 FAMILY A CM Reset behaves similarly to a Master Clear Reset, The power-up time delay depends on the INTRC clock RESET instruction, WDT time-out or Stack Event Reset. and will vary from chip-to-chip due to temperature and As with all hard and power Reset events, the device process variation. See DC Parameter33 for details. Configuration Words are reloaded from the Flash Con- figuration Words in program memory as the device 5.6.1 TIME-OUT SEQUENCE restarts. The PWRT time-out is invoked after the POR pulse has cleared. The total time-out will vary based on the status 5.6 Power-up Timer (PWRT) of the PWRT. Figure5-3, Figure5-4, Figure5-5 and Figure5-6 all depict time-out sequences on power-up. PIC18F97J60 family of devices incorporates an on-chip Power-up Timer (PWRT) to help regulate the Since the time-outs occur from the POR pulse, if MCLR Power-on Reset process. The PWRT is always is kept low long enough, the PWRT will expire. Bringing enabled. The main function is to ensure that the device MCLR high will begin execution immediately voltage is stable before code is executed. (Figure5-5). This is useful for testing purposes or to synchronize more than one PIC18FXXJ6X device The Power-up Timer (PWRT) of the PIC18F97J60 fam- operating in parallel. ily devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048x32s=66ms. While the PWRT is counting, the device is held in Reset. FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET DS39762F-page 66  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET  2011 Microchip Technology Inc. DS39762F-page 67

PIC18F97J60 FAMILY 5.7 Reset State of Registers TO, PD, POR and BOR) are set or cleared differently in different Reset situations, as indicated in Table5-1. Most registers are unaffected by a Reset. Their status These bits are used in software to determine the nature is unknown on POR and unchanged by all other of the Reset. Resets. The other registers are forced to a “Reset Table5-2 describes the Reset states for all of the state” depending on the type of Reset that occurred. Special Function Registers. These are categorized by Most registers are not affected by a WDT wake-up Power-on and Brown-out Resets, Master Clear and since this is viewed as the resumption of normal WDT Resets, and WDT wake-ups. operation. Status bits from the RCON register (CM, RI, TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter(1) CM RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u 0 u u u u u u Brown-out Reset 0000h 1 1 1 1 u 0 u u Configuration Mismatch Reset 0000h 0 u u u u u u u MCLR during power-managed 0000h u u 1 u u u u u Run modes MCLR during power-managed 0000h u u 1 0 u u u u Idle modes and Sleep mode MCLR during full-power 0000h u u u u u u u u execution Stack Full Reset (STVREN = 1) 0000h u u u u u u 1 u Stack Underflow Reset 0000h u u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u u u u u u u 1 actual Reset, STVREN = 0) WDT time-out during full power 0000h u u 0 u u u u u or power-managed Run modes WDT time-out during PC + 2 u u 0 0 u u u u power-managed Idle or Sleep modes Interrupt exit from PC + 2 u u u 0 u u u u power-managed modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt, and the GIEH or GIEL bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). DS39762F-page 68  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Reset, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Reset TOSU PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---0 uuuu(1) TOSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(1) TOSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(1) STKPTR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu PCL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 000x 0000 000u uuuu uuuu(3) INTCON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu(3) INTCON3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1100 0000 1100 0000 uuuu uuuu(3) INDF0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTINC0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTDEC0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PREINC0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PLUSW0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A FSR0H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- xxxx ---- uuuu ---- uuuu FSR0L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTINC1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTDEC1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PREINC1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PLUSW1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A FSR1H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- xxxx ---- uuuu ---- uuuu FSR1L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTINC2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTDEC2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PREINC2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PLUSW2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A FSR2H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- xxxx ---- uuuu ---- uuuu FSR2L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition.  2011 Microchip Technology Inc. DS39762F-page 69

PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Reset STATUS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TMR0L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0--- q-00 0--- q-00 u--- q-uu ECON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 00-- 0000 00-- uuuu uu-- WDTCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- ---0 ---- ---0 ---- ---u RCON(4) PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-q1 1100 0-uq qquu u-uu qquu TMR1H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 u0uu uuuu uuuu uuuu TMR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 1111 1111 T2CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu SSP1BUF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu SSP1ADD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP1STAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP1CON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP1CON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ADRESH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-00 0000 0-00 0000 u-uu uuuu ADCON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu ADCON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-00 0000 0-00 0000 u-uu uuuu CCPR1H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu CCPR3H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCPR3L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCP3CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ECCP1AS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu CVRCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu CMCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0111 0000 0111 uuuu uuuu TMR3H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. DS39762F-page 70  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Reset T3CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 uuuu uuuu uuuu uuuu PSPCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 ---- 0000 ---- uuuu ---- SPBRG1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu RCREG1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TXREG1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu TXSTA1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0010 0000 0010 uuuu uuuu RCSTA1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 000x 0000 000x uuuu uuuu EECON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- ---- ---- ---- ---- ---- EECON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 x00- ---0 x00- ---u uuu- IPR3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu PIR3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(3) PIE3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu IPR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1-11 1111 1-11 uuuu u-uu PIR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0-00 0000 0-00 uuuu u-uu(3) PIE2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0-00 0000 0-00 uuuu u-uu IPR1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu PIR1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(3) PIE1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MEMCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-00 --00 0-00 --00 u-uu --uu OSCTUNE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 ---- 0000 ---- uuuu ---- TRISJ PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --11 ---- --11 ---- --uu ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu TRISH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu TRISG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---1 ---- ---1 ---- ---u ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---1 1111 ---1 1111 ---u uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu TRISF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 111- 1111 111- uuuu uuu- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu TRISE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --11 1111 --11 1111 --uu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu TRISD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -111 ---- -111 ---- -uuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu TRISA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --11 1111 --11 1111 --uu uuuu LATJ PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx ---- --uu ---- --uu ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu LATH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition.  2011 Microchip Technology Inc. DS39762F-page 71

PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Reset LATG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x ---- ---u ---- ---u ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x xxxx ---u uuuu ---u uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu LATF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxx- uuuu uuu- uuuu uuu- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu LATE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx xxxx --uu uuuu --uu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu LATD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -xxx ---- -uuu ---- -uuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu LATC PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu LATA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 00xx xxxx 00uu uuuu uuuu uuuu PORTJ PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx ---- --uu ---- --uu ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x ---- ---u ---- ---u ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x xxxx ---u uuuu ---u uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 111x xxxx 111u uuuu uuuu uuuu PORTF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X x000 000- x000 000- uuuu uuu- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X x000 000- x000 000- uuuu uuu- PORTE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx xxxx --uu uuuu --uu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -xxx ---- -uuu ---- -uuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-0x 0000 0-0u 0000 u-uu uuuu SPBRGH1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu BAUDCON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0100 0-00 0100 0-00 uuuu u-uu SPBRGH2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu BAUDCON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0100 0-00 0100 0-00 uuuu u-uu ERDPTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 1010 ---0 1010 ---u uuuu ERDPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 0101 1111 0101 uuuu uuuu ECCP1DEL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TMR4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu PR4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 1111 1111 T4CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu CCPR4H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCPR4L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. DS39762F-page 72  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Reset CCP4CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu CCPR5H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCPR5L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCP5CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu SPBRG2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu RCREG2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TXREG2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TXSTA2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0010 0000 0010 uuuu uuuu RCSTA2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 000x 0000 000x uuuu uuuu ECCP3AS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ECCP3DEL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ECCP2AS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ECCP2DEL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP2BUF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu SSP2ADD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP2STAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP2CON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP2CON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EDATA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu EIR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0-00 -000 0-00 -uuu u-uu ECON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 100- ---- 100- ---- uuu- ---- ESTAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -0-0 -000 -0-0 -000 -u-u -uuu EIE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0-00 -000 0-00 -uuu u-uu EDMACSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EDMACSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EDMADSTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EDMADSTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EDMANDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EDMANDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EDMASTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EDMASTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ERXWRPTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu ERXWRPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ERXRDPTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0101 ---0 0101 ---u uuuu ERXRDPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1010 1111 1010 uuuu uuuu ERXNDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---1 1111 ---1 1111 ---u uuuu ERXNDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu ERXSTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0101 ---0 0101 ---u uuuu ERXSTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1010 1111 1010 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition.  2011 Microchip Technology Inc. DS39762F-page 73

PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Reset ETXNDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu ETXNDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ETXSTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu ETXSTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EWRPTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EWRPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPKTCNT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ERXFCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1010 0001 1010 0001 uuuu uuuu EPMOH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EPMOL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMCSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMCSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM7 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM6 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM5 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT7 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT6 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT5 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MIRDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MIRDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MIWRH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MIWRL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MIREGADR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu MICMD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- --00 ---- --00 ---- --uu MAMXFLH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0110 0000 0110 uuuu uuuu MAMXFLL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. DS39762F-page 74  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Reset MAIPGH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu MAIPGL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu MABBIPG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu MACON4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 --00 -000 --00 -uuu --uu MACON3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MACON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EPAUSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0001 0000 0001 0000 000u uuuu EPAUSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EFLOCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -000 ---- -000 ---- -uuu MISTAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- 0000 ---- 0000 ---- uuuu MAADR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MAADR1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MAADR4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MAADR3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MAADR6 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MAADR5 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition.  2011 Microchip Technology Inc. DS39762F-page 75

PIC18F97J60 FAMILY NOTES: DS39762F-page 76  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 6.0 MEMORY ORGANIZATION 6.1 Program Memory Organization There are two types of memory in PIC18 Flash PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address will return all ‘0’s (a As Harvard architecture devices, the data and program NOP instruction). memories use separate busses. This allows for The entire PIC18F97J60 family offers three sizes of concurrent access of the two memory spaces. on-chip Flash program memory, from 64Kbytes (up Additional detailed information on the operation of the to 32,764 single-word instructions) to 128Kbytes Flash program memory is provided in Section7.0 (65,532single-word instructions). The program mem- “Flash Program Memory”. ory maps for individual family members are shown in Figure6-1. FIGURE 6-1: MEMORY MAPS FOR PIC18F97J60 FAMILY DEVICES PC<20:0> 21 CALL, CALLW, RCALL, RETURN, RETFIE, RETLW, ADDULNK, SUBULNK Stack Level 1    Stack Level 31 PIC18FX6J60 PIC18FX6J65 PIC18FX7J60 000000h On-Chip On-Chip On-Chip Memory Memory Memory Config. Words 00FFFFh Config. Words e 017FFFh ac p S y or m e Config. Words M 01FFFFh er s U Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ 1FFFFFh Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.  2011 Microchip Technology Inc. DS39762F-page 77

PIC18F97J60 FAMILY 6.1.1 HARD MEMORY VECTORS 6.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded Because the PIC18F97J60 family devices do not have return vectors in their program memory space. The persistent configuration memory, the top four words of Reset vector address is the default value to which the on-chip program memory are reserved for configuration program counter returns on all device Resets; it is information. On Reset, the configuration information is located at 0000h. copied into the Configuration registers. PIC18 devices also have two interrupt vector The Configuration Words are stored in their program addresses for the handling of high-priority and memory location in numerical order, starting with the low-priority interrupts. The high-priority interrupt vector lower byte of CONFIG1 at the lowest address and end- is located at 0008h and the low-priority interrupt vector ing with the upper byte of CONFIG4. For these devices, is at 0018h. Their locations in relation to the program only Configuration Words, CONFIG1 through memory map are shown in Figure6-2. CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Words for FIGURE 6-2: HARD VECTOR AND devices in the PIC18F97J60 family are shown in CONFIGURATION WORD Table6-1. Their location in the memory map is shown LOCATIONS FOR with the other memory vectors in Figure6-2. PIC18F97J60 FAMILY Additional details on the device Configuration Words DEVICES are provided in Section25.1 “Configuration Bits”. Reset Vector 0000h TABLE 6-1: FLASH CONFIGURATION WORDS FOR PIC18F97J60 High-Priority Interrupt Vector 0008h FAMILY DEVICES Low-Priority Interrupt Vector 0018h Program Configuration Device Memory Word Addresses (Kbytes) PIC18F66J60 On-Chip PIC18F86J60 64 FFF8h to FFFFh Program Memory PIC18F96J60 PIC18F66J65 17FF8h to PIC18F86J65 96 17FFFh PIC18F96J65 PIC18F67J60 Flash Configuration Words (Top of Memory-7) 1FFF8h to (Top of Memory) PIC18F87J60 128 1FFFFh PIC18F97J60 Read as ‘0’ 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure6-1 for device-specific values). Shaded area represents unimplemented memory. Areas are not shown to scale. DS39762F-page 78  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 6.1.3 PIC18F9XJ60/9XJ65 PROGRAM • The Extended Microcontroller Mode allows MEMORY MODES access to both internal and external program memories as a single block. The device can The 100-pin devices in this family can address up to a access its entire on-chip program memory. Above total of 2Mbytes of program memory. This is achieved this, the device accesses external program through the external memory bus. There are two memory up to the 2-Mbyte program space limit. distinct operating modes available to the controllers: Execution automatically switches between the • Microcontroller (MC) two memories as required. • Extended Microcontroller (EMC) The setting of the EMB Configuration bits also controls The program memory mode is determined by setting the address bus width of the external memory bus. This the EMB Configuration bits (CONFIG3L<5:4>), as is covered in more detail in Section8.0 “External shown in Register6-1. (Also see Section25.1 Memory Bus”. “Configuration Bits” for additional details on the In all modes, the microcontroller has complete access device Configuration bits). to data RAM. The program memory modes operate as follows: Figure6-3 compares the memory maps of the different • The Microcontroller Mode accesses only on-chip program memory modes. The differences between Flash memory. Attempts to read above the top of on-chip and external memory access limitations are on-chip memory causes a read of all ‘0’s (a NOP more fully explained in Table6-2. instruction). The Microcontroller mode is also the only operating mode available to 64-pin and 80-pin devices. REGISTER 6-1: CONFIG3L: CONFIGURATION REGISTER 3 LOW R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 WAIT(1) BW(1) EMB1(1) EMB0(1) EASHFT(1) — — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states for operations on external memory bus are disabled 0 = Wait states for operations on external memory bus are enabled and selected by MEMCON<5:4> bit 6 BW: Data Bus Width Select bit(1) 1 = 16-Bit Data Width mode 0 = 8-Bit Data Width mode bit 5-4 EMB<1:0>: External Memory Bus Configuration bits(1) 11 = Microcontroller mode, external bus disabled 10 = Extended Microcontroller mode,12-Bit Addressing mode 01 = Extended Microcontroller mode,16-Bit Addressing mode 00 = Extended Microcontroller mode, 20-Bit Addressing mode bit 3 EASHFT: External Address Bus Shift Enable bit(1) 1 = Address shifting is enabled; address on external bus is offset to start at 000000h 0 = Address shifting is disabled; address on external bus reflects the PC value bit 2-0 Unimplemented: Read as ‘0’ Note 1: Implemented on 100-pin devices only.  2011 Microchip Technology Inc. DS39762F-page 79

PIC18F97J60 FAMILY 6.1.4 EXTENDED MICROCONTROLLER To avoid this, the Extended Microcontroller mode MODE AND ADDRESS SHIFTING implements an address shifting option to enable auto- matic address translation. In this mode, addresses By default, devices in Extended Microcontroller mode presented on the external bus are shifted down by the directly present the program counter value on the size of the on-chip program memory and are remapped external address bus for those addresses in the range to start at 0000h. This allows the complete use of the of the external memory space. In practical terms, this external memory device’s memory space. means addresses in the external memory device below the top of on-chip memory are unavailable. FIGURE 6-3: MEMORY MAPS FOR PIC18F97J60 FAMILY PROGRAM MEMORY MODES Microcontroller Mode(1) Extended Microcontroller Mode(2) Extended Microcontroller Mode with Address Shifting(2) On-Chip External On-Chip External On-Chip Memory Memory Memory Memory Memory Space Space Space Space Space 000000h 000000h 000000h On-Chip On-Chip On-Chip No Program Program Program Access Memory Memory Memory (Top of Memory) (Top of Memory) External (Top of Memory) (Top of Memory) + 1 (Top of Memory) + 1 Memory (Top of Memory) + 1 Mapped R e‘0a’dss EMxetmeronrayl EMxatpteoprneadl EMxettmeoronrayl 1FFFFFh – Memory Space (Top of Memory) Space 1FFFFFh 1FFFFFh 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure6-1 for device-specific values). Shaded areas represent unimplemented or inaccessible areas depending on the mode. Note 1: This mode is the only available mode on 64-pin and 80-pin devices and the default on 100-pin devices. 2: These modes are only available in 100-pin devices. TABLE 6-2: MEMORY ACCESS FOR PIC18F9XJ60/9XJ65 PROGRAM MEMORY MODES Internal Program Memory External Program Memory Operating Mode Execution Table Read Table Write Execution Table Read Table Write From From To From From To Microcontroller Yes Yes Yes No Access No Access No Access Extended Microcontroller Yes Yes Yes Yes Yes Yes DS39762F-page 80  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 6.1.5 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and is contained in three separate 8-bit registers. The the stack is readable and writable through the low byte, known as the PCL register, is both readable Top-of-Stack Special Function Registers. Data can also and writable. The high byte, or PCH register, contains be pushed to, or popped from the stack, using these the PC<15:8> bits; it is not directly readable or writable. registers. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack. register contains the PC<20:16> bits; it is also not The Stack Pointer is first incremented and the location directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the register are performed through the PCLATU register. contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred a pop from the stack. The contents of the location to the program counter by any operation that writes to pointed to by the STKPTR are transferred to the PC the PCL. Similarly, the upper two bytes of the program and then the Stack Pointer is decremented. counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all offsets to the PC (see Section6.1.8.1 “Computed Resets. There is no RAM associated with the location GOTO”). corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is The PC addresses bytes in the program memory. To full, has overflowed or has underflowed. prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to 6.1.6.1 Top-of-Stack Access a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. Only the top of the return address stack (TOS) is read- able and writable. A set of three registers, The CALL, RCALL, GOTO and program branch TOSU:TOSH:TOSL, holds the contents of the stack instructions write to the program counter directly. For location pointed to by the STKPTR register these instructions, the contents of PCLATH and (Figure6-4). This allows users to implement a software PCLATU are not transferred to the program counter. stack if necessary. After a CALL, RCALL or interrupt (and ADDULNK and SUBULNK instructions if the 6.1.6 RETURN ADDRESS STACK extended instruction set is enabled), the software can The return address stack allows any combination of up to read the pushed value by reading the 31 program calls and interrupts to occur. The PC is TOSU:TOSH:TOSL registers. These values can be pushed onto the stack when a CALL or RCALL instruction placed on a user-defined software stack. At return time, is executed, or an interrupt is Acknowledged. The PC the software can return these values to value is pulled off the stack on a RETURN, RETLW or a TOSU:TOSH:TOSL and do a return. RETFIE instruction (and on ADDULNK and SUBULNK The user must disable the Global Interrupt Enable bits instructions if the extended instruction set is enabled). while accessing the stack to prevent inadvertent stack PCLATU and PCLATH are not affected by any of the corruption. RETURN or CALL instructions. FIGURE 6-4: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> Top-of-Stack Registers Stack Pointer 11111 TOSU TOSH TOSL 11110 STKPTR<4:0> 00h 1Ah 34h 11101 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000  2011 Microchip Technology Inc. DS39762F-page 81

PIC18F97J60 FAMILY 6.1.6.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop returns a value of zero The STKPTR register (Register6-2) contains the Stack to the PC, and sets the STKUNF bit, while the Stack Pointer value, the STKFUL (Stack Full) status bit and Pointer remains at zero. The STKUNF bit will remain the STKUNF (Stack Underflow) status bit. The value of set until cleared by software or until a POR occurs. the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System (RTOS) for return stack maintenance. not the same as a Reset, as the contents of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a 6.1.6.3 PUSH and POP Instructions POR. Since the Top-of-Stack is readable and writable, the The action that takes place when the stack becomes ability to push values onto the stack and pull values off full depends on the state of the STVREN (Stack Over- the stack, without disturbing normal program execu- flow Reset Enable) Configuration bit. (Refer to tion, is a desirable feature. The PIC18 instruction set Section25.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control. (default), the 31st push will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data onto the stack, set the STKFUL bit and reset the or a return address on the stack. device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto Pointer will be set to zero. the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st push and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by Any additional pushes will not overwrite the 31st push decrementing the Stack Pointer. The previous value and the STKPTR will remain at 31. pushed onto the stack then becomes the TOS value. REGISTER 6-2: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. DS39762F-page 82  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 6.1.6.4 Stack Full and Underflow Resets 6.1.8 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in There may be programming situations that require the Configuration Register 1L. When STVREN is set, a full creation of data structures, or look-up tables, in or underflow condition will set the appropriate STKFUL program memory. For PIC18 devices, look-up tables or STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit, but not cause • Table Reads a device Reset. The STKFUL or STKUNF bit is cleared by user software or a Power-on Reset. 6.1.8.1 Computed GOTO 6.1.7 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in A Fast Register Stack (FSR) is provided for the Example6-2. STATUS, WREG and BSR registers to provide a “fast return” option for interrupts. This stack is only one level A look-up table can be formed with an ADDWF PCL deep and is neither readable nor writable. It is loaded instruction and a group of RETLW nn instructions. The with the current value of the corresponding register W register is loaded with an offset into the table before when the processor vectors for an interrupt. All inter- executing a call to that table. The first instruction of the rupt sources will push values into the Stack registers. called routine is the ADDWF PCL instruction. The next The values in the registers are then loaded back into instruction executed will be one of the RETLW nn the working registers if the RETFIE, FAST instruction instructions, that returns the value ‘nn’ to the calling is used to return from the interrupt. function. If both low and high-priority interrupts are enabled, the The offset value (in WREG) specifies the number of Stack registers cannot be used reliably to return from bytes that the program counter should advance and low-priority interrupts. If a high-priority interrupt occurs should be multiples of 2 (LSb = 0). while servicing a low-priority interrupt, the Stack In this method, only one data byte may be stored in register values stored by the low-priority interrupt will each instruction location and room on the return be overwritten. In these cases, users must save the key address stack is required. registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 6-2: COMPUTED GOTO USING Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE interrupts are used, the Fast Register Stack can be MOVF OFFSET, W used to restore the STATUS, WREG and BSR registers CALL TABLE at the end of a subroutine call. To use the Fast Register ORG nn00h Stack for a subroutine call, a CALL label, FAST TABLE ADDWF PCL instruction must be executed to save the STATUS, RETLW nnh WREG and BSR registers to the Fast Register Stack. A RETLW nnh RETURN, FAST instruction is then executed to restore RETLW nnh these registers from the Fast Register Stack. . . Example6-1 shows a source code example that uses . the Fast Register Stack during a subroutine call and return. 6.1.8.2 Table Reads EXAMPLE 6-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored, two bytes per ;STACK program word, while programming. The Table Pointer  (TBLPTR) specifies the byte address and the Table  Latch (TABLAT) contains the data that is read from the program memory. Data is transferred from program SUB1  memory, one byte at a time.  RETURN FAST ;RESTORE VALUES SAVED Table read operation is discussed further in ;IN FAST REGISTER STACK Section7.1 “Table Reads and Table Writes”.  2011 Microchip Technology Inc. DS39762F-page 83

PIC18F97J60 FAMILY 6.2 PIC18 Instruction Cycle 6.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles, Q1 6.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are The microcontroller clock input, whether from an pipelined in such a manner that a fetch takes one internal or external source, is internally divided by four instruction cycle, while the decode and execute take to generate four non-overlapping quadrature clocks another instruction cycle. However, due to the pipelining, (Q1, Q2, Q3 and Q4). Internally, the program counter is each instruction effectively executes in one cycle. If an incremented on every Q1. The instruction is fetched instruction causes the program counter to change from the program memory and latched into the (e.g.,GOTO), then two cycles are required to complete Instruction Register (IR) during Q4. The instruction is the instruction (Example6-3). decoded and executed during the following Q1 through A fetch cycle begins with the Program Counter (PC) Q4. The clocks and instruction execution flow are incrementing in Q1. shown in Figure6-5. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-5: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS39762F-page 84  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruction. Since instructions are always stored on word boundaries, The program memory is addressed in bytes. Instruc- the data contained in the instruction is a word address. tions are stored as two bytes or four bytes in program The word address is written to PC<20:1> which memory. The Least Significant Byte (LSB) of an accesses the desired byte address in program memory. instruction word is always stored in a program memory Instruction #2 in Figure6-6 shows how the instruction, location with an even address (LSb = 0). To maintain GOTO 0006h, is encoded in the program memory. alignment with instruction boundaries, the PC incre- Program branch instructions, which encode a relative ments in steps of 2 and the LSb will always read ‘0’ (see address offset, operate in the same manner. The offset Section6.1.5 “Program Counter”). value stored in a branch instruction represents the Figure6-6 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section26.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 6-6: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0  Program Memory 000000h Byte Locations  000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 6.2.4 TWO-WORD INSTRUCTIONS used by the instruction sequence. If the first word is skipped, for some reason, and the second word is The standard PIC18 instruction set has four, two-word executed by itself, a NOP is executed instead. This is instructions: CALL, MOVFF, GOTO and LSFR. In all necessary for cases when the two-word instruction is cases, the second word of the instructions always has preceded by a conditional instruction that changes the ‘1111’ as its four Most Significant bits (MSbs); the other PC. Example6-4 shows how this works. 12 bits are literal data, usually a data memory address. Note: See Section6.5 “Program Memory and The use of ‘1111’ in the 4 MSbs of an instruction the Extended Instruction Set” for specifies a special form of NOP. If the instruction is information on two-word instructions in executed in proper sequence, immediately after the the extended instruction set. first word, the data in the second word is accessed and EXAMPLE 6-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code  2011 Microchip Technology Inc. DS39762F-page 85

PIC18F97J60 FAMILY 6.3 Data Memory Organization 6.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory is changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section6.6 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit 12-bit address, allowing up to 4096 bytes of addressable low-order address and a 4-bit Bank Pointer. memory. The memory space is divided into 16 banks Most instructions in the PIC18 instruction set make use that contain 256 bytes each. All of the PIC18F97J60 of the Bank Pointer, known as the Bank Select Register family devices implement all available banks and pro- (BSR). This SFR holds the 4 Most Significant bits of a vide 3808 bytes of data memory available to the user. location’s address; the instruction itself includes the Figure6-7 shows the data memory organization for the 8Least Significant bits (LSbs). Only the four lower bits devices. of the BSR are implemented (BSR3:BSR0). The upper The data memory contains Special Function Registers four bits are unused; they will always read ‘0’ and can- (SFRs) and General Purpose Registers (GPRs). The not be written to. The BSR can be loaded directly by SFRs are used for control and status of the controller using the MOVLB instruction. and peripheral functions, while GPRs are used for data The value of the BSR indicates the bank in data memory. storage and scratchpad operations in the user’s The 8 bits in the instruction show the location in the bank application. Any read of an unimplemented location will and can be thought of as an offset from the bank’s lower read as ‘0’s. boundary. The relationship between the BSR’s value The instruction set and architecture allow operations and the bank division in data memory is shown in across all banks. The entire data memory may be Figure6-8. accessed by Direct, Indirect or Indexed Addressing Since up to 16 registers may share the same low-order modes. Addressing modes are discussed later in this address, the user must always be careful to ensure that section. the proper bank is selected before performing a data To ensure that commonly used registers (most SFRs read or write. For example, writing what should be and select GPRs) can be accessed in a single cycle, program data to an 8-bit address of F9h, while the BSR PIC18 devices implement an Access Bank. This is a is 0Fh, will end up resetting the program counter. 256-byte memory space that provides fast access to While any bank can be selected, only those banks that the majority of SFRs and the lower portion of GPR are actually implemented can be read or written to. Bank 0 without using the BSR. Section6.3.2 “Access Writes to unimplemented banks are ignored, while Bank” provides a detailed description of the Access reads from unimplemented banks will return ‘0’s. Even RAM. so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure6-7 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. DS39762F-page 86  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 6-7: DATA MEMORY MAP FOR PIC18F97J60 FAMILY DEVICES When a = 0: BSR<3:0> Data Memory Map The BSR is ignored and the Access Bank is used. 00h 000h Access RAM The first 96 bytes are general = 0000 05Fh Bank 0 060h purpose RAM (from Bank 0). GPR FFh 0FFh The remaining 160 bytes are 00h 100h Special Function Registers = 0001 Bank 1 GPR (from Bank 15). FFh 1FFh = 0010 00h 200h When a = 1: Bank 2 GPR The BSR specifies the bank FFh 2FFh used by the instruction. 00h 300h = 0011 Bank 3 GPR FFh 3FFh 00h 400h = 0100 Bank 4 GPR FFh 4FFh 00h 500h = 0101 Bank 5 GPR FFh 5FFh 00h 600h = 0110 Bank 6 GPR FFh 6FFh Access Bank = 0111 00h 700h 00h Bank 7 GPR Access RAM Low 5Fh FFh 7FFh Access RAM High 60h 00h 800h = 1000 (SFRs) Bank 8 GPR FFh FFh 8FFh 00h 900h = 1001 Bank 9 GPR FFh 9FFh 00h A00h = 1010 Bank 10 GPR FFh AFFh 00h B00h = 1011 Bank 11 GPR FFh BFFh 00h C00h = 1100 GPR Bank 12 FFh CFFh 00h D00h = 1101 GPR Bank 13 FFh DFFh 00h E00h = 1110 GPR E7Fh Bank 14 E80h Ethernet SFR FFh EFFh = 1111 00h GPR F00h F5Fh Bank 15 SFR F60h FFh FFFh  2011 Microchip Technology Inc. DS39762F-page 87

PIC18F97J60 FAMILY FIGURE 6-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 7 BSR(1) 0 000h Data Memory 00h 7 From Opcode(2) 0 Bank 0 0 0 0 0 0 0 1 0 11 11 11 11 11 11 11 11 FFh 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR3:BSR0) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 6.3.2 ACCESS BANK Using this “forced” addressing allows the instruction to operate on a data address in a single cycle without While the use of the BSR with an embedded 8-bit updating the BSR first. For 8-bit addresses of 60h and address allows users to address the entire range of above, this means that users can evaluate and operate data memory, it also means that the user must always on SFRs more efficiently. The Access RAM below 60h ensure that the correct bank is selected. Otherwise, is a good place for data values that the user might need data may be read from or written to the wrong location. to access rapidly, such as immediate computational This can be disastrous if a GPR is the intended target results or common program variables. Access RAM of an operation but an SFR is written to instead. also allows for faster and more code efficient context Verifying and/or changing the BSR for each read or saving and switching of variables. write to data memory can become very inefficient. The mapping of the Access Bank is slightly different To streamline access for the most commonly used data when the extended instruction set is enabled (XINST memory locations, the data memory is configured with Configuration bit = 1). This is discussed in more detail an Access Bank, which allows users to access a in Section6.6.3 “Mapping the Access Bank in mapped block of memory without specifying a BSR. Indexed Literal Offset Mode”. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of 6.3.3 GENERAL PURPOSE memory (60h-FFh) in Bank 15. The lower block is REGISTER FILE known as the “Access RAM” and is composed of GPRs. The upper block is where the device’s SFRs are PIC18 devices may have banked memory in the GPR mapped. These two areas are mapped contiguously in area. This is data RAM which is available for use by all the Access Bank and can be addressed in a linear instructions. GPRs start at the bottom of Bank 0 fashion by an 8-bit address (Figure6-7). (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a The Access Bank is used by core PIC18 instructions Power-on Reset and are unchanged on all other that include the Access RAM bit (the ‘a’ parameter in Resets. the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. DS39762F-page 88  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS Reset and Interrupt registers are described in their respective chapters, while the ALU’s STATUS register The Special Function Registers (SFRs) are registers is described later in this section. Registers related to used by the CPU and peripheral modules for controlling the operation of the peripheral features are described the desired operation of the device. These registers are in the chapter for that peripheral. implemented as static RAM. The SFRs are typically distributed among the The main group of SFRs start at the top of data memory peripherals whose functions they control. Unused SFR (FFFh) and extend downward to occupy more than the locations are unimplemented and read as ‘0’s. A list of top half of Bank 15 (F60h to FFFh). These SFRs can SFRs is given in Table6-3; a full description is provided be classified into two sets: those associated with the in Table6-5. “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The TABLE 6-3: SPECIAL FUNCTION REGISTER MAP FOR PIC18F97J60 FAMILY DEVICES Address Name Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 F7Fh SPBRGH1 FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 F7Eh BAUDCON1 FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 F7Dh SPBRGH2 FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch MEMCON(4) F7Ch BAUDCON2 FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE F7Bh ERDPTH FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(3) F7Ah ERDPTL FF9h PCL FD9h FSR2L FB9h CCPR3H F99h TRISH(3) F79h ECCP1DEL FF8h TBLPTRU FD8h STATUS FB8h CCPR3L F98h TRISG F78h TMR4 FF7h TBLPTRH FD7h TMR0H FB7h CCP3CON F97h TRISF F77h PR4 FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE F76h T4CON FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD F75h CCPR4H FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h CCPR4L FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h CCP4CON FF2h INTCON FD2h ECON1 FB2h TMR3L F92h TRISA F72h CCPR5H FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(3) F71h CCPR5L FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH(3) F70h CCP5CON FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG F6Fh SPBRG2 FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF F6Eh RCREG2 FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE F6Dh TXREG2 FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD F6Ch TXSTA2 FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh RCSTA2 FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB F6Ah ECCP3AS FE9h FSR0L FC9h SSP1BUF FA9h —(2) F89h LATA F69h ECCP3DEL FE8h WREG FC8h SSP1ADD FA8h —(2) F88h PORTJ(3) F68h ECCP2AS FE7h INDF1(1) FC7h SSP1STAT FA7h EECON2(1) F87h PORTH(3) F67h ECCP2DEL FE6h POSTINC1(1) FC6h SSP1CON1 FA6h EECON1 F86h PORTG F66h SSP2BUF FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h PORTF F65h SSP2ADD FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h SSP2STAT FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h SSP2CON1 FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SSP2CON2 FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h EDATA FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h EIR Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available in 64-pin devices. 4: This register is not available in 64 and 80-pin devices.  2011 Microchip Technology Inc. DS39762F-page 89

PIC18F97J60 FAMILY 6.3.5 ETHERNET SFRs Note: To improve performance, frequently In addition to the standard SFR set in Bank 15, accessed Ethernet registers are located in members of the PIC18F97J60 family have a second the standard SFR bank (F60h through set of SFRs. This group, associated exclusively with FFFh). the Ethernet module, occupies the top half of Bank 14 A complete list of Ethernet SFRs is given in Table6-4. (E80h to EFFh). All SFRs are fully described in Table6-5. TABLE 6-4: ETHERNET SFR MAP FOR PIC18F97J60 FAMILY DEVICES Address Name Address Name Address Name Address Name EFFh —(1) EDFh —(1) EBFh —(1) E9Fh —(1) EFEh ECON2 EDEh —(1) EBEh —(1) E9Eh —(1) EFDh ESTAT EDDh —(1) EBDh —(1) E9Dh —(1) EFCh —(1) EDCh —(1) EBCh —(1) E9Ch —(1) EFBh EIE EDBh —(1) EBBh —(1) E9Bh —(1) EFAh —(1) EDAh —(1) EBAh —(1) E9Ah —(1) EF9h —(2) ED9h EPKTCNT EB9h MIRDH E99h EPAUSH EF8h —(2) ED8h ERXFCON EB8h MIRDL E98h EPAUSL EF7h EDMACSH ED7h —(1) EB7h MIWRH E97h EFLOCON EF6h EDMACSL ED6h —(1) EB6h MIWRL E96h —(2) EF5h EDMADSTH ED5h EPMOH EB5h —(1) E95h —(2) EF4h EDMADSTL ED4h EPMOL EB4h MIREGADR E94h —(2) EF3h EDMANDH ED3h —(2) EB3h —(2) E93h —(2) EF2h EDMANDL ED2h —(2) EB2h MICMD E92h —(2) EF1h EDMASTH ED1h EPMCSH EB1h —(1) E91h —(2) EF0h EDMASTL ED0h EPMCSL EB0h —(1) E90h —(2) EEFh ERXWRPTH ECFh EPMM7 EAFh —(2) E8Fh —(2) EEEh ERXWRPTL ECEh EPMM6 EAEh —(1) E8Eh —(2) EEDh ERXRDPTH ECDh EPMM5 EADh —(1) E8Dh —(2) EECh ERXRDPTL ECCh EPMM4 EACh —(1) E8Ch —(2) EEBh ERXNDH ECBh EPMM3 EABh MAMXFLH E8Bh —(2) EEAh ERXNDL ECAh EPMM2 EAAh MAMXFLL E8Ah MISTAT EE9h ERXSTH EC9h EPMM1 EA9h —(1) E89h —(1) EE8h ERXSTL EC8h EPMM0 EA8h —(1) E88h —(1) EE7h ETXNDH EC7h EHT7 EA7h MAIPGH E87h —(1) EE6h ETXNDL EC6h EHT6 EA6h MAIPGL E86h —(1) EE5h ETXSTH EC5h EHT5 EA5h —(2) E85h MAADR2 EE4h ETXSTL EC4h EHT4 EA4h MABBIPG E84h MAADR1 EE3h EWRPTH EC3h EHT3 EA3h MACON4 E83h MAADR4 EE2h EWRPTL EC2h EHT2 EA2h MACON3 E82h MAADR3 EE1h —(1) EC1h EHT1 EA1h —(1) E81h MAADR6 EE0h —(1) EC0h EHT0 EA0h MACON1 E80h MAADR5 Note 1: Reserved register location; do not modify. 2: Unimplemented registers are read as ‘0’. DS39762F-page 90  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) Values on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: TOSU — — — Top-of-Stack Register Upper Byte (TOS<20:16>) ---0 0000 69, 81 TOSH Top-of-Stack Register High Byte (TOS<15:8>) 0000 0000 69, 81 TOSL Top-of-Stack Register Low Byte (TOS<7:0>) 0000 0000 69, 81 STKPTR STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 00-0 0000 69, 82 PCLATU — — bit 21(2) Holding Register for PC<20:16> ---0 0000 69, 81 PCLATH Holding Register for PC<15:8> 0000 0000 69, 81 PCL PC Low Byte (PC<7:0>) 0000 0000 69, 81 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 69, 108 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 69, 108 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 69, 108 TABLAT Program Memory Table Latch 0000 0000 69, 108 PRODH Product Register High Byte xxxx xxxx 69, 127 PRODL Product Register Low Byte xxxx xxxx 69, 127 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 69, 131 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 69, 132 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 69, 133 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 69, 99 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 69, 100 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 69, 100 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 69, 100 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – N/A 69, 100 value of FSR0 offset by W FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 69, 99 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 69, 100 WREG Working Register xxxx xxxx 69 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 69, 99 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 69, 100 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 69, 100 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 69, 100 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – N/A 69, 100 value of FSR1 offset by W FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 69, 99 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 69, 99 BSR — — — — Bank Select Register ---- 0000 69, 99 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 69, 99 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 69, 100 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 69, 100 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 69, 100 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – N/A 69, 100 value of FSR2 offset by W FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 69, 99 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 69, 99 Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as ‘0’. Note1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’. 9: Implemented in 100-pin devices in Microcontroller mode only.  2011 Microchip Technology Inc. DS39762F-page 91

PIC18F97J60 FAMILY TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Values on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: STATUS — — — N OV Z DC C ---x xxxx 70, 97 TMR0H Timer0 Register High Byte 0000 0000 70, 171 TMR0L Timer0 Register Low Byte xxxx xxxx 70, 171 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 70, 171 OSCCON IDLEN — — — OSTS(3) — SCS1 SCS0 0--- q-00 70, 53 ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN — — 0000 00-- 70, 227 WDTCON — — — — — — — SWDTEN --- ---0 70, 368 RCON IPEN — CM RI TO PD POR BOR 0-q1 1100 70, 64, 143 TMR1H Timer1 Register High Byte xxxx xxxx 70, 175 TMR1L Timer1 Register Low Byte xxxx xxxx 70, 175 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 70, 175 TMR2 Timer2 Register 0000 0000 70, 180 PR2 Timer2 Period Register 1111 1111 70, 180 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 70, 180 SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 70, 279 SSP1ADD MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) 0000 0000 70, 279 SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 70, 270, 280 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 70, 271, 281 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 70, 282 GCEN ACKSTAT ADMSK5(4) ADMSK4(4) ADMSK3(4) ADMSK2(4) ADMSK1(4) SEN ADRESH A/D Result Register High Byte xxxx xxxx 70, 347 ADRESL A/D Result Register Low Byte xxxx xxxx 70, 347 ADCON0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0-00 0000 70, 339 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 70, 340 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 70, 341 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 70, 193 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 70, 193 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 70, 198 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 70, 193 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 70, 193 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 70, 198 CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx 70, 193 CCPR3L Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 70, 193 CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 70, 198 ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 70, 212 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 70, 355 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 70, 349 TMR3H Timer3 Register High Byte xxxx xxxx 70, 183 TMR3L Timer3 Register Low Byte xxxx xxxx 70, 183 Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as ‘0’. Note1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’. 9: Implemented in 100-pin devices in Microcontroller mode only. DS39762F-page 92  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Values on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 71, 183 PSPCON(5) IBF OBF IBOV PSPMODE — — — — 0000 ---- 71, 169 SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 71, 320 RCREG1 EUSART1 Receive Register 0000 0000 71, 327 TXREG1 EUSART1 Transmit Register xxxx xxxx 71, 329 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 71, 320 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 71, 320 EECON2 Program Memory Control Register (not a physical register) ---- ---- 71, 106 EECON1 — — — FREE WRERR WREN WR — ---0 x00- 71, 107 IPR3 SSP2IP(5) BCL2IP(5) RC2IP(6) TX2IP(6) TMR4IP CCP5IP CCP4IP CCP3IP 1111 1111 71, 142 PIR3 SSP2IF(5) BCL2IF(5) RC2IF(6) TX2IF(6) TMR4IF CCP5IF CCP4IF CCP3IF 0000 0000 71, 136 PIE3 SSP2IE(5) BCL2IE(5) RC2IE(6) TX2IE(6) TMR4IE CCP5IE CCP4IE CCP3IE 0000 0000 71, 139 IPR2 OSCFIP CMIP ETHIP r BCL1IP — TMR3IP CCP2IP 1111 1-11 71, 141 PIR2 OSCFIF CMIF ETHIF r BCL1IF — TMR3IF CCP2IF 0000 0-00 71, 135 PIE2 OSCFIE CMIE ETHIE r BCL1IE — TMR3IE CCP2IE 0000 0-00 71, 138 IPR1 PSPIP(9) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 71, 140 PIR1 PSPIF(9) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 71, 134 PIE1 PSPIE(9) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 71, 137 MEMCON(5,7) EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 71, 116 OSCTUNE PPST1 PLLEN(8) PPST0 PPRE — — — — 0000 ---- 71, 51 TRISJ(6) TRISJ7(5) TRISJ6(5) TRISJ5(6) TRISJ4(6) TRISJ3(5) TRISJ2(5) TRISJ1(5) TRISJ0(5) 1111 1111 71, 167 TRISH(6) TRISH7(6) TRISH6(6) TRISH5(6) TRISH4(6) TRISH3(6) TRISH2(6) TRISH1(6) TRISH0(6) 1111 1111 71, 165 TRISG TRISG7(5) TRISG6(5) TRISG5(5) TRISG4 TRISG3(6) TRISG2(6) TRISG1(6) TRISG0(6) 1111 1111 71, 163 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0(5) 1111 1111 71, 161 TRISE TRISE7(6) TRISE6(6) TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 71, 159 TRISD TRISD7(5) TRISD6(5) TRISD5(5) TRISD4(5) TRISD3(5) TRISD2 TRISD1 TRISD0 1111 1111 71, 156 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 71, 153 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 71, 150 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 71, 147 LATJ(6) LATJ7(5) LATJ6(5) LATJ5(6) LATJ4(6) LATJ3(5) LATJ2(5) LATJ1(5) LATJ0(5) xxxx xxxx 71, 167 LATH(6) LATH7(6) LATH6(6) LATH5(6) LATH4(6) LATH3(6) LATH2(6) LATH1(6) LATH0(6) xxxx xxxx 71, 165 LATG LATG7(5) LATG6(5) LATG5(5) LATG4 LATG3(6) LATG2(6) LATG1(6) LATG0(6) xxxx xxxx 72, 163 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0(5) xxxx xxxx 72, 161 LATE LATE7(6) LATE6(6) LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx 72, 159 LATD LATD7(5) LATD6(5) LATD5(5) LATD4(5) LATD3(5) LATD2 LATD1 LATD0 xxxx xxxx 72, 156 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 72, 153 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 72, 150 LATA RDPU REPU LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 00xx xxxx 72, 147 PORTJ(6) RJ7(5) RJ6(5) RJ5(6) RJ4(6) RJ3(5) RJ2(5) RJ1(5) RJ0(5) xxxx xxxx 72, 167 PORTH(6) RH7(6) RH6(6) RH5(6) RH4(6) RH3(6) RH2(6) RH1(6) RH0(6) 0000 xxxx 72, 165 PORTG RG7(5) RG6(5) RG5(5) RG4 RG3(6) RG2(6) RG1(6) RG0(6) 111x xxxx 72, 163 Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as ‘0’. Note1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’. 9: Implemented in 100-pin devices in Microcontroller mode only.  2011 Microchip Technology Inc. DS39762F-page 93

PIC18F97J60 FAMILY TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Values on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0(5) 0000 0000 72, 161 PORTE RE7(6) RE6(6) RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 72, 159 PORTD RD7(5) RD6(5) RD5(5) RD4(5) RD3(5) RD2 RD1 RD0 xxxx xxxx 72, 156 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 72, 153 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 72, 150 PORTA RJPU(6) — RA5 RA4 RA3 RA2 RA1 RA0 0-0x 0000 72, 147 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 72, 320 BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 72, 318 SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 72, 320 BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 72, 318 ERDPTH — — — Buffer Read Pointer High Byte ---0 0101 72, 223 ERDPTL Buffer Read Pointer Low Byte 1111 1010 72, 223 ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 72, 211 TMR4 Timer4 Register 0000 0000 72, 187 PR4 Timer4 Period Register 1111 1111 72, 187 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 72, 187 CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 72, 193 CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 72, 193 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 73, 189 CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 73, 193 CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 73, 193 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 73, 189 SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 73, 320 RCREG2 EUSART2 Receive Register 0000 0000 73, 327 TXREG2 EUSART2 Transmit Register 0000 0000 73, 329 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 73, 316 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 73, 317 ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 73, 212 ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 73, 211 ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 73, 212 ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 73, 211 SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 73, 279 SSP2ADD MSSP2 Address Register (I2C™ Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) 0000 0000 73, 279 SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 73, 270 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 73, 271, 281 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 73, 282 GCEN ACKSTAT ADMSK5(4) ADMSK4(4) ADMSK3(4) ADMSK2(4) ADMSK1(4) SEN EDATA Ethernet Transmit/Receive Buffer Register (EDATA<7:0>) xxxx xxxx 73, 223 EIR — PKTIF DMAIF LINKIF TXIF — TXERIF RXERIF -000 0-00 73, 241 ECON2 AUTOINC PKTDEC ETHEN — — — — — 100- ---- 73, 228 Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as ‘0’. Note1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’. 9: Implemented in 100-pin devices in Microcontroller mode only. DS39762F-page 94  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Values on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: ESTAT — BUFER — r — RXBUSY TXABRT PHYRDY -0-0 -000 73, 228 EIE — PKTIE DMAIE LINKIE TXIE — TXERIE RXERIE -000 0-00 73, 240 EDMACSH DMA Checksum Register High Byte 0000 0000 73, 265 EDMACSL DMA Checksum Register Low Byte 0000 0000 73, 265 EDMADSTH — — — DMA Destination Register High Byte ---0 0000 73, 265 EDMADSTL DMA Destination Register Low Byte 0000 0000 73, 265 EDMANDH — — — DMA End Register High Byte ---0 0000 73, 265 EDMANDL DMA End Register Low Byte 0000 0000 73, 265 EDMASTH — — — DMA Start Register High Byte ---0 0000 73, 265 EDMASTL DMA Start Register Low Byte 0000 0000 73, 265 ERXWRPTH — — — Receive Buffer Write Pointer High Byte ---0 0000 73, 225 ERXWRPTL Receive Buffer Write Pointer Low Byte 0000 0000 73, 225 ERXRDPTH — — — Receive Buffer Read Pointer High Byte ---0 0101 73, 225 ERXRDPTL Receive Buffer Read Pointer Low Byte 1111 1010 73, 225 ERXNDH — — — Receive End Register High Byte ---1 1111 73, 225 ERXNDL Receive End Register Low Byte 1111 1111 73, 225 ERXSTH — — — Receive Start Register High Byte ---0 0101 73, 225 ERXSTL Receive Start Register Low Byte 1111 1010 73, 225 ETXNDH — — — Transmit End Register High Byte ---0 0000 74, 226 ETXNDL Transmit End Register Low Byte 0000 0000 74, 226 ETXSTH — — — Transmit Start Register High Byte ---0 0000 74, 226 ETXSTL Transmit Start Register Low Byte 0000 0000 74, 226 EWRPTH — — — Buffer Write Pointer High Byte ---0 0000 74, 223 EWRPTL Buffer Write Pointer Low Byte 0000 0000 74, 223 EPKTCNT Ethernet Packet Count Register 0000 0000 74, 252 ERXFCON UCEN ANDOR CRCEN PMEN MPEN HTEN MCEN BCEN 1010 0001 74, 260 EPMOH — — — Pattern Match Offset Register High Byte ---0 0000 74, 263 EPMOL Pattern Match Offset Register Low Byte 0000 0000 74, 263 EPMCSH Pattern Match Checksum Register High Byte 0000 0000 74, 263 EPMCSL Pattern Match Checksum Register Low Byte 0000 0000 74, 263 EPMM7 Pattern Match Mask Register Byte 7 0000 0000 74, 263 EPMM6 Pattern Match Mask Register Byte 6 0000 0000 74, 263 EPMM5 Pattern Match Mask Register Byte 5 0000 0000 74, 263 EPMM4 Pattern Match Mask Register Byte 4 0000 0000 74, 263 EPMM3 Pattern Match Mask Register Byte 3 0000 0000 74, 263 EPMM2 Pattern Match Mask Register Byte 2 0000 0000 74, 263 EPMM1 Pattern Match Mask Register Byte 1 0000 0000 74, 263 EPMM0 Pattern Match Mask Register Byte 0 0000 0000 74, 263 Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as ‘0’. Note1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’. 9: Implemented in 100-pin devices in Microcontroller mode only.  2011 Microchip Technology Inc. DS39762F-page 95

PIC18F97J60 FAMILY TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Values on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: EHT7 Hash Table Register Byte 7 0000 0000 74, 259 EHT6 Hash Table Register Byte 6 0000 0000 74, 259 EHT5 Hash Table Register Byte 5 0000 0000 74, 259 EHT4 Hash Table Register Byte 4 0000 0000 74, 259 EHT3 Hash Table Register Byte 3 0000 0000 74, 259 EHT2 Hash Table Register Byte 2 0000 0000 74, 259 EHT1 Hash Table Register Byte 1 0000 0000 74, 259 EHT0 Hash Table Register Byte 0 0000 0000 74, 259 MIRDH MII Read Data Register High Byte 0000 0000 74, 232 MIRDL MII Read Data Register Low Byte 0000 0000 74, 232 MIWRH MII Write Data Register High Byte 0000 0000 74, 232 MIWRL MII Write Data Register Low Byte 0000 0000 74, 232 MIREGADR — — — MII Address Register ---0 0000 74, 232 MICMD — — — — — — MIISCAN MIIRD ---- --00 74, 231 MAMXFLH Maximum Frame Length Register High Byte 0000 0110 74, 245 MAMXFLL Maximum Frame Length Register Low Byte 0000 0000 74, 245 MAIPGH — MAC Non Back-to-Back Inter-Packet Gap Register High Byte -000 0000 75, 245 MAIPGL — MAC Non Back-to-Back Inter-Packet Gap Register Low Byte -000 0000 75, 245 MABBIPG — BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 -000 0000 75, 246 MACON4 — DEFER r r — — r r -000 --00 75, 231 MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX 0000 0000 75, 230 MACON1 — — — r TXPAUS RXPAUS PASSALL MARXEN ---0 0000 75, 229 EPAUSH Pause Timer Value Register High Byte 0001 0000 75, 258 EPAUSL Pause Timer Value Register Low Byte 0000 0000 75, 258 EFLOCON — — — — — r FCEN1 FCEN0 ---- -000 75, 258 MISTAT — — — — r NVALID SCAN BUSY ---- 0000 75, 232 MAADR2 MAC Address Register Byte 2 (MAADR<39:32>), OUI Byte 2 0000 0000 75, 245 MAADR1 MAC Address Register Byte 1 (MAADR<47:40>), OUI Byte 1 0000 0000 75, 245 MAADR4 MAC Address Register Byte 4 (MAADR<23:16>) 0000 0000 75, 245 MAADR3 MAC Address Register Byte 3 (MAADR<31:24>), OUI Byte 3 0000 0000 75, 245 MAADR6 MAC Address Register Byte 6 (MAADR<7:0>) 0000 0000 75, 245 MAADR5 MAC Address Register Byte 5 (MAADR<15:8>) 0000 0000 75, 245 Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as ‘0’. Note1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’. 9: Implemented in 100-pin devices in Microcontroller mode only. DS39762F-page 96  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 6.3.6 STATUS REGISTER register then reads back as ‘000u u1uu’. It is recom- mended, therefore, that only BCF, BSF, SWAPF, MOVFF The STATUS register, shown in Register6-3, contains and MOVWF instructions are used to alter the STATUS the arithmetic status of the ALU. The STATUS register register because these instructions do not affect the Z, can be the operand for any instruction, as with any C, DC, OV or N bits in the STATUS register. other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, For other instructions not affecting any Status bits, see then the write to these five bits is disabled. the instruction set summaries in Table26-2 and Table26-3. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the Note: The C and DC bits operate as a Borrow STATUS register as destination may be different than and Digit Borrow bit respectively, in intended. For example, CLRF STATUS will set the Z bit subtraction. but leave the other bits unchanged. The STATUS REGISTER 6-3: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSb = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is non-zero bit 1 DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. 2: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register.  2011 Microchip Technology Inc. DS39762F-page 97

PIC18F97J60 FAMILY 6.4 Data Addressing Modes The Access RAM bit, ‘a’, determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR Note: The execution of some instructions in the (Section6.3.1 “Bank Select Register”) are used with core PIC18 instruction set are changed the address to determine the complete 12-bit address when the PIC18 extended instruction set is of the register. When ‘a’ is ‘0’, the address is interpreted enabled. See Section6.6 “Data Memory as being a register in the Access Bank. Addressing that and the Extended Instruction Set” for uses the Access RAM is sometimes also known as more information. Direct Forced Addressing mode. While the program memory can be addressed in only A few instructions, such as MOVFF, include the entire one way, through the program counter, information in 12-bit address (either source or destination) in their the data memory space can be addressed in several opcodes. In these cases, the BSR is ignored entirely. ways. For most instructions, the addressing mode is The destination of the operation’s results is determined fixed. Other instructions may use up to three modes, by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are depending on which operands are used and whether or stored back in the source register, overwriting its origi- not the extended instruction set is enabled. nal contents. When ‘d’ is ‘0’, the results are stored in The addressing modes are: the W register. Instructions without the ‘d’ argument have a destination that is implicit in the instruction. • Inherent Their destination is either the target register being • Literal operated on or the W register. • Direct • Indirect 6.4.3 INDIRECT ADDRESSING An additional addressing mode, Indexed Literal Offset, Indirect Addressing mode allows the user to access a is available when the extended instruction set is location in data memory without giving a fixed address enabled (XINST Configuration bit = 1). Its operation is in the instruction. This is done by using File Select discussed in greater detail in Section6.6.1 “Indexed Registers (FSRs) as pointers to the locations to be read Addressing with Literal Offset”. or written to. Since the FSRs are themselves located in RAM as Special Function Registers, they can also be 6.4.1 INHERENT AND LITERAL directly manipulated under program control. This ADDRESSING makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. Many PIC18 control instructions do not need any argument at all. They either perform an operation that The registers for Indirect Addressing are also globally affects the device, or they operate implicitly on implemented with Indirect File Operands (INDFs) that one register. This addressing mode is known as Inherent permit automatic manipulation of the pointer value with Addressing. Examples include SLEEP, RESET and DAW. auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code using Other instructions work in a similar way, but require an loops, such as the example of clearing an entire RAM additional explicit argument in the opcode. This is bank in Example6-5. It also enables users to perform known as Literal Addressing mode because they Indexed Addressing and other Stack Pointer require some literal value as an argument. Examples operations for program memory in data memory. include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples EXAMPLE 6-5: HOW TO CLEAR RAM include CALL and GOTO, which include a 20-bit (BANK 1) USING INDIRECT program memory address. ADDRESSING 6.4.2 DIRECT ADDRESSING LFSRFSR0, 100h; Direct Addressing mode specifies all or part of the NEXT CLRFPOSTINC0; Clear INDF source and/or destination address of the operation ; register then within the opcode itself. The options are specified by ; inc pointer the arguments accompanying the instruction. BTFSSFSR0H, 1; All done with ; Bank1? In the core PIC18 instruction set, bit-oriented and BRA NEXT ; NO, clear next byte-oriented instructions use some version of Direct CONTINUE ; YES, continue Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section6.3.3 “General Purpose Register File”) or a location in the Access Bank (Section6.3.2 “Access Bank”) as the data source for the instruction. DS39762F-page 98  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 6.4.3.1 FSR Registers and the SFR space but are not physically implemented. Reading INDF Operand or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, At the core of Indirect Addressing are three sets of for example, reads the data at the address indicated by registers: FSR0, FSR1 and FSR2. Each represents a FSR1H:FSR1L. Instructions that use the INDF registers pair of 8-bit registers: FSRnH and FSRnL. The four as operands actually use the contents of their upper bits of the FSRnH register are not used, so each corresponding FSR as a pointer to the instruction’s FSR pair holds a 12-bit value. This represents a value target. The INDF operand is just a convenient way of that can address the entire range of the data memory using the pointer. in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Because Indirect Addressing uses a full, 12-bit address, data RAM banking is not necessary. Thus, the Indirect Addressing is accomplished with a set of Indirect current contents of the BSR and Access RAM bit have File Operands: INDF0 through INDF2. These can be no effect on determining the target address. thought of as “virtual” registers. They are mapped in the FIGURE 6-9: INDIRECT ADDRESSING 000h Using an instruction with one of the Bank 0 ADDWF, INDF1, 1 Indirect Addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... x x x x 1 1 1 1 1 1 0 0 1 1 0 0 Bank 3 through Bank 13 ...to determine the data memory location to be used in that operation. E00h In this case, the FSR1 pair contains FCCh. This means the contents of Bank 14 location FCCh will be added to that F00h of the W register and stored back in Bank 15 FCCh. FFFh Data Memory  2011 Microchip Technology Inc. DS39762F-page 99

PIC18F97J60 FAMILY 6.4.3.2 FSR Registers and POSTINC, On the other hand, using the virtual registers to write to POSTDEC, PREINC and PLUSW an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any In addition to the INDF operand, each FSR register pair incrementing or decrementing. Thus, writing to INDF2 also has four additional indirect operands. Like INDF, or POSTDEC2 will write the same value to the these are “virtual” registers that cannot be indirectly FSR2H:FSR2L pair. read or written to. Accessing these registers actually accesses the associated FSR register pair, but also Since the FSRs are physical registers mapped in the performs a specific action on its stored value. They are: SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when • POSTDEC: accesses the FSR value, then working on these registers, particularly if their code automatically decrements it by ‘1’ afterwards uses Indirect Addressing. • POSTINC: accesses the FSR value, then Similarly, operations by Indirect Addressing are gener- automatically increments it by ‘1’ afterwards ally permitted on all other SFRs. Users should exercise • PREINC: increments the FSR value by ‘1’, then the appropriate caution that they do not inadvertently uses it in the operation change settings that might affect the operation of the • PLUSW: adds the signed value of the W register device. (range of -128 to 127) to that of the FSR and uses the new value in the operation 6.5 Program Memory and the In this context, accessing an INDF register uses the Extended Instruction Set value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR The operation of program memory is unaffected by the value offset by the value in the W register; neither value use of the extended instruction set. is actually changed in the operation. Accessing the Enabling the extended instruction set adds five other virtual registers changes the value of the FSR additional two-word commands to the existing PIC18 registers. instruction set: ADDFSR, CALLW, MOVSF, MOVSS and Operations on the FSRs with POSTDEC, POSTINC SUBFSR. These instructions are executed as described and PREINC affect the entire register pair; that is, roll- in Section6.2.4 “Two-Word Instructions”. overs of the FSRnL register, from FFh to 00h, carry over to the FSRnH register. On the other hand, results 6.6 Data Memory and the Extended of these operations do not change the value of any Instruction Set flags in the STATUS register (e.g., Z, N, OV, etc.). Enabling the PIC18 extended instruction set (XINST The PLUSW register can be used to implement a form Configuration bit = 1) significantly changes certain of Indexed Addressing in the data memory space. By aspects of data memory and its addressing. Specifically, manipulating the value in the W register, users can the use of the Access Bank for many of the core PIC18 reach addresses that are fixed offsets from pointer instructions is different. This is due to the introduction of addresses. In some applications, this can be used to a new addressing mode for the data memory space. implement some powerful program control structure, This mode also alters the behavior of Indirect such as software stacks, inside of data memory. Addressing using FSR2 and its associated operands. 6.4.3.3 Operations by FSRs on FSRs What does not change is just as important. The size of the data memory space is unchanged, as well as its Indirect Addressing operations that target other FSRs, or linear addressing. The SFR map remains the same. virtual registers, represent special cases. For example, Core PIC18 instructions can still operate in both Direct using an FSR to point to one of the virtual registers will and Indirect Addressing mode; inherent and literal not result in successful operation. As a specific case, instructions do not change at all. Indirect Addressing assume that the FSR0H:FSR0L pair contains FE7h, the with FSR0 and FSR1 also remains unchanged. address of INDF1. Attempts to read the value of the INDF1, using INDF0 as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as the operand, will result in a NOP. DS39762F-page 100  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 6.6.1 INDEXED ADDRESSING WITH 6.6.2 INSTRUCTIONS AFFECTED BY LITERAL OFFSET INDEXED LITERAL OFFSET MODE Enabling the PIC18 extended instruction set changes Any of the core PIC18 instructions that can use Direct the behavior of Indirect Addressing using the FSR2 Addressing are potentially affected by the Indexed Literal register pair and its associated file operands. Under the Offset Addressing mode. This includes all byte-oriented proper conditions, instructions that use the Access and bit-oriented instructions, or almost half of the Bank – that is, most bit-oriented and byte-oriented standard PIC18 instruction set. Instructions that only use instructions – can invoke a form of Indexed Addressing Inherent or Literal Addressing modes are unaffected. using an offset specified in the instruction. This special Additionally, byte-oriented and bit-oriented instructions addressing mode is known as Indexed Addressing with are not affected if they use the Access Bank (Access Literal Offset or Indexed Literal Offset mode. RAM bit is ‘1’) or include a file address of 60h or above. When using the extended instruction set, this Instructions meeting these criteria will continue to addressing mode requires the following: execute as before. A comparison of the different possible addressing modes when the extended instruction set is • The use of the Access Bank is forced (‘a’ = 0); enabled is shown in Figure6-10. and • The file address argument is less than or equal to Those who desire to use byte-oriented or bit-oriented 5Fh. instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. Under these conditions, the file address of the This is described in more detail in Section26.2.1 instruction is not interpreted as the lower byte of an “Extended Instruction Syntax”. address (used with the BSR in Direct Addressing) or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation.  2011 Microchip Technology Inc. DS39762F-page 101

PIC18F97J60 FAMILY FIGURE 6-10: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff 000h When a = 0 and f  60h: The instruction executes in 060h Direct Forced mode. ‘f’ is Bank 0 interpreted as a location in the 100h Access RAM between 060h 00h and FFFh. This is the same as Bank 1 60h locations F60h to FFFh through (Bank15) of data memory. Bank 14 Valid Range for ‘f’ Locations below 060h are not FFh available in this addressing F00h Access RAM mode. Bank 15 F40h SFRs FFFh Data Memory When a = 0 and f5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 060h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to obtain the address of the target Bank 1 through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F40h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When a = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 060h Direct mode (also known as Direct Long mode). ‘f’ is 100h interpreted as a location in one of the 16 banks of the data 001001da ffffffff memory space. The bank is Bank 1 through designated by the Bank Select Bank 14 Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F40h SFRs FFFh Data Memory DS39762F-page 102  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue The use of Indexed Literal Offset Addressing mode to use Direct Addressing as before. Any indirect or effectively changes how the lower part of Access RAM indexed operation that explicitly uses any of the indirect (00h to 5Fh) is mapped. Rather than containing just the file operands (including FSR2) will continue to operate contents of the bottom part of Bank 0, this mode maps as standard Indirect Addressing. Any instruction that the contents from Bank 0 and a user-defined “window” uses the Access Bank, but includes a register address that can be located anywhere in the data memory of greater than 05Fh, will use Direct Addressing and space. The value of FSR2 establishes the lower the normal Access Bank map. boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 6.6.4 BSR IN INDEXED LITERAL (5Fh). Addresses in the Access RAM above 5Fh are OFFSET MODE mapped as previously described (see Section6.3.2 “Access Bank”). An example of Access Bank Although the Access Bank is remapped when the remapping in this addressing mode is shown in extended instruction set is enabled, the operation of the Figure6-11. BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. FIGURE 6-11: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a Not Accessible FSR2H:FSR2L = 120h 05Fh Locations in the region Bank 0 from the FSR2 Pointer 100h (120h) to the pointer plus 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Access RAM (000h-05Fh). 200h Bank 1 “Window” 5Fh Special Function Registers 60h at F60h through FFFh are mapped to 60h through Bank 2 FFh, as usual. through SFRs Bank 0 addresses below Bank 14 5Fh are not available in FFh this mode. They can still Access Bank be addressed by using the F00h BSR. Bank 15 F60h SFRs FFFh Data Memory  2011 Microchip Technology Inc. DS39762F-page 103

PIC18F97J60 FAMILY NOTES: DS39762F-page 104  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte • Table Read (TBLRD) at a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 64 bytes at a time. Program memory is The program memory space is 16 bits wide, while the erased in blocks of 1024 bytes at a time. A Bulk Erase data RAM space is 8 bits wide. Table reads and table operation may not be issued from user code. writes move data between these two memory spaces Writing or erasing program memory will cease through an 8-bit register (TABLAT). instruction fetches until the operation is complete. The Table read operations retrieve data from program program memory cannot be accessed during the write memory and place it into the data RAM space. or erase, therefore, code cannot execute. An internal Figure7-1 shows the operation of a table read with programming timer terminates program memory writes program memory and data RAM. and erases. Table write operations store data from the data memory A value written to program memory does not need to be space into holding registers in program memory. The a valid instruction. Executing a program memory procedure to write the contents of the holding registers location that forms an invalid instruction results in a into program memory is detailed in Section7.5 “Writing NOP. to Flash Program Memory”. Figure7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory.  2011 Microchip Technology Inc. DS39762F-page 105

PIC18F97J60 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section7.5 “Writing to Flash Program Memory”. 7.2 Control Registers The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is Several control registers are used in conjunction with set in hardware when the WR bit is set, and cleared the TBLRD and TBLWT instructions. These include the: when the internal programming timer expires and the • EECON1 register write operation is complete. • EECON2 register Note: During normal operation, the WRERR is • TABLAT register read as ‘1’. This can indicate that a write • TBLPTR registers operation was prematurely terminated by a Reset, or a write operation was 7.2.1 EECON1 AND EECON2 REGISTERS attempted improperly. The EECON1 register (Register7-1) is the control register for memory accesses. The EECON2 register is The WR control bit initiates write operations. The bit not a physical register; it is used exclusively in the cannot be cleared, only set, in software; it is cleared in memory write and erase sequences. Reading hardware at the completion of the write operation. EECON2 will read all ‘0’s. The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. DS39762F-page 106  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 — — — FREE WRERR WREN WR — bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program Write Enable bit 1 = Allows write cycles to Flash program memory 0 = Inhibits write cycles to Flash program memory bit 1 WR: Write Control bit 1 = Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle complete bit 0 Unimplemented: Read as ‘0’  2011 Microchip Technology Inc. DS39762F-page 107

PIC18F97J60 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the SFR space. The Table Latch register is used to Flash program memory. hold 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the TBLPTR memory and data RAM. determine which byte is read from program memory into TABLAT. 7.2.3 TABLE POINTER REGISTER (TBLPTR) When a TBLWT is executed, the six LSbs of the Table Pointer register (TBLPTR<5:0>) determine which of The Table Pointer (TBLPTR) register addresses a byte the 64 program memory holding registers is written to. within the program memory. The TBLPTR is comprised When the timed write to program memory begins (via of three SFR registers: Table Pointer Upper Byte, Table the WR bit), the 15 MSbs of the TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<20:6>) determine which program memory (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- block of 64 bytes is written to. For more detail, see ters join to form a 22-bit wide pointer. The low-order Section7.5 “Writing to Flash Program Memory”. 21bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to When an erase of program memory is executed, the the Device ID and Configuration bits. 11MSbs of the Table Pointer register (TBLPTR<20:10>) point to the 1024-byte block that will be erased. The The Table Pointer register, TBLPTR, is used by the Least Significant bits (TBLPTR<9:0>) are ignored. TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the Figure7-3 describes the relevant boundaries of table operation. These operations are shown in TBLPTR based on Flash program memory operations. Table7-1. The table operations on the TBLPTR only affect the low-order 21bits. TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 Table Erase TBLPTR<20:10> Table Write TBLPTR<20:6> Table Read – TBLPTR<21:0> DS39762F-page 108  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 7.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure7-4 shows the interface between the internal program memory and the TABLAT. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVFW TABLAT, W ; get data MOVF WORD_ODD  2011 Microchip Technology Inc. DS39762F-page 109

PIC18F97J60 FAMILY 7.4 Erasing Flash Program Memory 7.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 1024 bytes. Only through the use of an external programmer, or through ICSP The sequence of events for erasing a block of internal control, can larger blocks of program memory be Bulk program memory location is: Erased. Word Erase in the Flash array is not supported. 1. Load Table Pointer register with the address of When initiating an erase sequence from the micro- row being erased. controller itself, a block of 1024 bytes of program 2. Set the EECON1 register for the erase operation: memory is erased. The Most Significant 11 bits of the • set WREN bit to enable writes; TBLPTR<20:10> point to the block being erased. • set FREE bit to enable the erase. TBLPTR<9:0> are ignored. 3. Disable interrupts. The EECON1 register commands the erase operation. 4. Write 55h to EECON2. The WREN bit must be set to enable write operations. 5. Write 0AAh to EECON2. The FREE bit is set to select an erase operation. 6. Set the WR bit. This will begin the Row Erase For protection, the write initiate sequence for EECON2 cycle. must be used. 7. The CPU will stall for the duration of the erase. A long write is necessary for erasing the internal 8. Re-enable interrupts. Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. An on-chip timer controls the erase time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over most of the voltage range of the device. See Parameter D132B (VPEW) for specific limits. EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS39762F-page 110  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 7.5 Writing to Flash Program Memory An on-chip timer controls the write time. The write/erase voltages are generated by an on-chip The minimum programming block is 32 words or charge pump, rated to operate over most of the 64bytes. Word or byte programming is not supported. voltage range of the device. See Parameter D132B Table writes are used internally to load the holding (VPEW) for specific limits. registers needed to program the Flash memory. There Note1: Unlike previous PIC MCU devices, are 64 holding registers used by the table writes for members of the PIC18F97J60 family do programming. not reset the holding registers after a Since the Table Latch (TABLAT) is only a single byte, the write occurs. The holding registers must TBLWT instruction may need to be executed 64times for be cleared or overwritten before a each programming operation. All of the table write programming sequence. operations will essentially be short writes because only 2: To maintain the endurance of the pro- the holding registers are written. At the end of updating gram memory cells, each Flash byte the 64 holding registers, the EECON1 register must be should not be programmed more than written to in order to start the programming operation one time between erase operations. with a long write. Before attempting to modify the contents The long write is necessary for programming the of the target cell a second time, a Row internal Flash. Instruction execution is halted while in a Erase of the target row, or a Bulk Erase of long write cycle. The long write will be terminated by the entire memory, must be performed. the internal programming timer. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxx3F Holding Register Holding Register Holding Register Holding Register Program Memory 7.5.1 FLASH PROGRAM MEMORY WRITE 5. Write 55h to EECON2. SEQUENCE 6. Write AAh to EECON2. The sequence of events for programming an internal 7. Set the WR bit. This will begin the write cycle. program memory location should be: 8. The CPU will stall for the duration of the write. 1. If the section of program memory to be written to 9. Re-enable interrupts. has been programmed previously, then the 10. Verify the memory (table read). memory will need to be erased before the write An example of the required code is shown in occurs (see Section7.4.1 “Flash Program Example7-3. Memory Erase Sequence”). 2. Write the 64 bytes into the holding registers with Note: Before setting the WR bit, the Table auto-increment. Pointer address needs to be within the intended address range of the 64 bytes in 3. Set the WREN bit to enable byte writes. the holding register. 4. Disable interrupts.  2011 Microchip Technology Inc. DS39762F-page 111

PIC18F97J60 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts MOVLW D'16' MOVWF WRITE_COUNTER ; Need to write 16 blocks of 64 to write ; one erase block of 1024 RESTART_BUFFER MOVLW D'64' MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L FILL_BUFFER ... ; read the new data from I2C, SPI, ; PSP, USART, etc. WRITE_BUFFER MOVLW D’64 ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS MOVFF POSTINC0, WREG ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_BYTE_TO_HREGS PROGRAM_MEMORY BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory DECFSZ WRITE_COUNTER ; done with one write cycle BRA RESTART_BUFFER ; if not done replacing the erase block DS39762F-page 112  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 7.5.2 WRITE VERIFY 7.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the To protect against spurious writes to Flash program memory should be verified against the original value. memory, the write initiate sequence must also be This should be used in applications where excessive followed. See Section25.0 “Special Features of the writes can stress bits near the specification limit. CPU” for more details. 7.5.3 UNEXPECTED TERMINATION OF 7.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section25.6 “Program Verification and Code Protection” for details on code protection of Flash location just programmed should be verified and repro- grammed if needed. If the write operation is interrupted program memory. by a MCLR Reset, or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte 69 (TBLPTR<20:16>) TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 69 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 69 TABLAT Program Memory Table Latch 69 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 EECON2 EEPROM Control Register 2 (not a physical register) 71 EECON1 — — — FREE WRERR WREN WR — 71 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.  2011 Microchip Technology Inc. DS39762F-page 113

PIC18F97J60 FAMILY NOTES: DS39762F-page 114  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 8.0 EXTERNAL MEMORY BUS The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE Note: The external memory bus is not and PORTH) are multiplexed with the address/data bus implemented on 64-pin and 80-pin for a total of 20 available lines, while PORTJ is devices. multiplexed with the bus control signals. A list of the pins and their functions is provided in The External Memory Bus (EMB) allows the device to Table8-1. access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. It supports both 8 and 16-Bit Data Width modes, and three address widths of up to 20 bits. TABLE 8-1: PIC18F96J60/96J65/97J60 EXTERNAL MEMORY BUS – I/O PORT FUNCTIONS Name Port Bit External Memory Bus Function RD0/AD0 PORTD 0 Address Bit 0 or Data Bit 0 RD1/AD1 PORTD 1 Address Bit 1 or Data Bit 1 RD2/AD2 PORTD 2 Address Bit 2 or Data Bit 2 RD3/AD3 PORTD 3 Address Bit 3 or Data Bit 3 RD4/AD4 PORTD 4 Address Bit 4 or Data Bit 4 RD5/AD5 PORTD 5 Address Bit 5 or Data Bit 5 RD6/AD6 PORTD 6 Address Bit 6 or Data Bit 6 RD7/AD7 PORTD 7 Address Bit 7 or Data Bit 7 RE0/AD8 PORTE 0 Address Bit 8 or Data Bit 8 RE1/AD9 PORTE 1 Address Bit 9 or Data Bit 9 RE2/AD10 PORTE 2 Address Bit 10 or Data Bit 10 RE3/AD11 PORTE 3 Address Bit 11 or Data Bit 11 RE4/AD12 PORTE 4 Address Bit 12 or Data Bit 12 RE5/AD13 PORTE 5 Address Bit 13 or Data Bit 13 RE6/AD14 PORTE 6 Address Bit 14 or Data Bit 14 RE7/AD15 PORTE 7 Address Bit 15 or Data Bit 15 RH0/A16 PORTH 0 Address Bit 16 RH1/A17 PORTH 1 Address Bit 17 RH2/A18 PORTH 2 Address Bit 18 RH3/A19 PORTH 3 Address Bit 19 RJ0/ALE PORTJ 0 Address Latch Enable (ALE) Control bit RJ1/OE PORTJ 1 Output Enable (OE) Control bit RJ2/WRL PORTJ 2 Write Low (WRL) Control bit RJ3/WRH PORTJ 3 Write High (WRH) Control bit RJ4/BA0 PORTJ 4 Byte Address (BA0) Bit 0 RJ5/CE PORTJ 5 Chip Enable (CE) Control bit RJ6/LB PORTJ 6 Lower Byte Enable (LB) Control bit RJ7/UB PORTJ 7 Upper Byte Enable (UB) Control bit Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available in some pins.  2011 Microchip Technology Inc. DS39762F-page 115

PIC18F97J60 FAMILY 8.1 External Memory Bus Control The operation of the EBDIS bit is also influenced by the program memory mode being used. This is discussed The operation of the interface is controlled by the in more detail in Section8.5 “Program Memory MEMCON register (Register8-1). This register is Modes and the External Memory Bus”. available in all program memory operating modes, The WAIT bits allow for the addition of Wait states to except Microcontroller mode. In this mode, the register external memory operations. The use of these bits is is disabled and cannot be written to. discussed in Section8.3 “Wait States”. The EBDIS bit (MEMCON<7>) controls the operation The WM bits select the particular operating mode used of the bus and related port functions. Clearing EBDIS when the bus is operating in 16-Bit Data Width mode. enables the interface and disables the I/O functions of These operating modes are discussed in more detail in the ports, as well as any other functions multiplexed to Section8.6 “16-Bit Data Width Modes”. The WM bits those pins. Setting the bit enables the I/O ports and have no effect when an 8-Bit Data Width mode is other functions, but allows the interface to override selected. everything else on the pins when an external memory operation is required. By default, the external bus is always enabled and disables all other I/Os. REGISTER 8-1: MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EBDIS — WAIT1 WAIT0 — — WM1 WM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EBDIS: External Bus Disable bit 1 = External bus is enabled when microcontroller accesses external memory; otherwise, all external bus drivers are mapped as I/O ports 0 = External bus is always enabled, I/O ports are disabled bit 6 Unimplemented: Read as ‘0’ bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 WM<1:0>: TBLWT Operation with 16-Bit Data Bus Width Select bits 1x = Word Write mode: WRH is active when TABLAT is written to and TBLPTR contains an odd address. When TBLPTR contains an even address, writing to TABLAT loads a holding latch with the value written. 01 = Byte Select mode: TABLAT data is copied on both MSB and LSB; WRH and (UB or LB) will activate 00 = Byte Write mode: TABLAT data is copied on both MSB and LSB; WRH or WRL will activate DS39762F-page 116  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 8.2 Address and Data Width 8.2.1 ADDRESS SHIFTING ON THE EXTERNAL BUS The PIC18F97J60 family of devices can be indepen- dently configured for different address and data widths By default, the address presented on the external bus on the same memory bus. Both address and data is the value of the PC. In practical terms, this means widths are set by Configuration bits in the CONFIG3L that addresses in the external memory device below register. As Configuration bits, this means that these the top of on-chip memory are unavailable to the micro- options can only be configured by programming the controller. To access these physical locations, the glue device and are not controllable in software. logic between the microcontroller and the external memory must somehow translate addresses. The BW bit selects an 8-bit or 16-bit data bus width. Setting this bit (default) selects a data width of 16 bits. To simplify the interface, the external bus offers an extension of Extended Microcontroller mode that The EMB<1:0> bits determine both the program automatically performs address shifting. This feature is memory operating mode and the address bus width. The controlled by the EASHFT Configuration bit. Setting available options are 20-bit, 16-bit and 12-bit, as well as this bit offsets addresses on the bus by the size of the the default Microcontroller mode (external bus disabled). microcontroller’s on-chip program memory and sets Selecting a 16-bit or 12-bit width makes a corresponding the bottom address at 0000h. This allows the device to number of high-order lines available for I/O functions. use the entire range of physical addresses of the These pins are no longer affected by the setting of the external memory. EBDIS bit. For example, selecting a 16-Bit Addressing mode (EMB<1:0>=01) disables A<19:16> and allows 8.2.2 21-BIT ADDRESSING the PORTH<3:0> bits to function without interruptions As an extension of 20-bit address width operation, the from the bus. Using the smaller address widths allows external memory bus can also fully address a 2-Mbyte users to tailor the memory bus to the size of the external memory space. This is done by using the Bus Address memory space for a particular design, while freeing up Bit 0 (BA0) control line as the Least Significant bit of the pins for dedicated I/O operation. address. The UB and LB control signals may also be Because the EMB bits have the effect of disabling pins for used with certain memory devices to select the upper memory bus operations, it is important to always select and lower bytes within a 16-bit wide data word. an address width at least equal to the data width. If a This addressing mode is available in both 8-Bit Data 12-bit address width is used with a 16-bit data width, the Width and certain 16-Bit Data Width modes. Additional upper four bits of data will not be available in the bus. details are provided in Section8.6.3 “16-Bit Byte All combinations of address and data widths require Select Mode” and Section8.7 “8-Bit Data Width multiplexing of address and data information on the Mode”. same lines. The address and data multiplexing, as well as I/O ports made available by the use of smaller address widths, are summarized in Table8-2. TABLE 8-2: ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS Multiplexed Data and Address Only Lines Ports Available Data Width Address Width Address Lines (and (and corresponding for I/O corresponding ports) ports) AD<11:8> PORTE<7:4>, 12-bit (PORTE<3:0>) All of PORTH AD<15:8> 16-bit AD<7:0> All of PORTH 8-bit (PORTE<7:0>) (PORTD<7:0>) A<19:16>, AD<15:8> 20-bit (PORTH<3:0>, — PORTE<7:0>) 16-bit AD<15:0> — All of PORTH 16-bit (PORTD<7:0>, A<19:16> 20-bit — PORTE<7:0>) (PORTH<3:0>)  2011 Microchip Technology Inc. DS39762F-page 117

PIC18F97J60 FAMILY 8.3 Wait States If the device fetches or accesses external memory while EBDIS = 1, the pins will switch to the external While it may be assumed that external memory devices bus. If the EBDIS bit is set by a program executing from will operate at the microcontroller clock rate, this is external memory, the action of setting the bit will be often not the case. In fact, many devices require longer delayed until the program branches into the internal times to write or retrieve data than the time allowed by memory. At that time, the pins will change from external the execution of table read or table write operations. bus to I/O ports. To compensate for this, the external memory bus can If the device is executing out of internal memory when be configured to add a fixed delay to each table opera- EBDIS = 0, the memory bus address/data and control tion using the bus. Wait states are enabled by setting pins will not be active. They will go to a state where the the WAIT Configuration bit. When enabled, the amount active address/data pins are tri-state; the CE, OE, of delay is set by the WAIT<1:0> bits (MEMCON<5:4>). WRH, WRL, UB and LB signals are ‘1’, and ALE and The delay is based on multiples of microcontroller BA0 are ‘0’. Note that only those pins associated with instruction cycle time and is added following the the current address width are forced to tri-state; the instruction cycle when the table operation is executed. other pins continue to function as I/O. In the case of The range is from no delay to 3TCY (default value). 16-bit address width, for example, only AD<15:0> (PORTD and PORTE) are affected; A<19:16> 8.4 Port Pin Weak Pull-ups (PORTH<3:0>) continue to function as I/O. With the exception of the upper address lines, In all external memory modes, the bus takes priority A<19:16>, the pins associated with the external mem- over any other peripherals that may share pins with it. ory bus are equipped with weak pull-ups. The pull-ups This includes the Parallel Slave Port and serial are controlled by bits located at LATA<7:6> and communication modules, which would otherwise take PORTA<7>. They are named RDPU, REPU and RJPU priority over the I/O port. and control pull-ups on PORTD, PORTE and PORTJ, respectively. Setting one of these bits enables the 8.6 16-Bit Data Width Modes corresponding pull-ups for that port. All pull-ups are In 16-Bit Data Width mode, the external memory disabled by default on all device Resets. interface can be connected to external memories in In Extended Microcontroller mode, the port pull-ups three different configurations: can be useful in preserving the memory state on the • 16-Bit Byte Write external bus while the bus is temporarily disabled (EBDIS = 1). • 16-Bit Word Write • 16-Bit Byte Select 8.5 Program Memory Modes and the The configuration to be used is determined by External Memory Bus the WM<1:0> bits in the MEMCON register (MEMCON<1:0>). These three different configurations The PIC18F97J60 family of devices is capable of allow the designer maximum flexibility in using both operating in one of two program memory modes, using 8-bit and 16-bit devices with 16-bit data. combinations of on-chip and external program memory. For all 16-Bit Data Width modes, the Address Latch The functions of the multiplexed port pins depend on Enable (ALE) pin indicates that the address bits, the program memory mode selected, as well as the AD<15:0>, are available in the external memory inter- setting of the EBDIS bit. face bus. Following the address latch, the Output In Microcontroller Mode, the bus is not active and the Enable signal (OE) will enable both bytes of program pins have their port functions only. Writes to the memory at once to form a 16-bit instruction word. The MEMCOM register are not permitted. The Reset value Chip Enable signal (CE) is active at any time that the of EBDIS (‘0’) is ignored and the EMB pins behave as microcontroller accesses external memory, whether I/O ports. reading or writing. It is inactive (asserted high) In Extended Microcontroller Mode, the external whenever the device is in Sleep mode. program memory bus shares I/O port functions on the In Byte Select mode, JEDEC standard Flash memories pins. When the device is fetching, or doing table will require BA0 for the byte address line and one I/O read/table write operations on the external program line to select between Byte and Word mode. The other memory space, the pins will have the external bus 16-Bit Data Width modes do not need BA0. JEDEC function. standard, static RAM memories will use the UB or LB If the device is fetching and accessing internal program signals for byte selection. memory locations only, the EBDIS control bit will change the pins from external memory to I/O port functions. When EBDIS = 0, the pins function as the external bus. When EBDIS = 1, the pins function as I/O ports. DS39762F-page 118  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 8.6.1 16-BIT BYTE WRITE MODE During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the Figure8-1 shows an example of 16-Bit Byte Write AD<15:0> bus. The appropriate WRH or WRL control mode for PIC18F97J60 family devices. This mode is line is strobed on the LSb of the TBLPTR. used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. FIGURE 8-1: 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18F97J60 (MSB) (LSB) A<19:0> AD<7:0> 373 A<x:0> A<x:0> D<15:8> D<7:0> D<7:0> D<7:0> CE CE AD<15:8> 373 OE WR(2) OE WR(2) ALE A<19:16>(1) CE OE WRH WRL Address Bus Data Bus Control Lines Note 1: The upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”.  2011 Microchip Technology Inc. DS39762F-page 119

PIC18F97J60 FAMILY 8.6.2 16-BIT WORD WRITE MODE During a TBLWT cycle to an odd address (TBLPTR<0>= 1), the TABLAT data is presented on Figure8-2 shows an example of 16-Bit Word Write the upper byte of the AD<15:0> bus. The contents of mode for PIC18F97J60 family devices. This mode is the holding latch are presented on the lower byte of the used for word-wide memories, which include some of AD<15:0> bus. the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of The WRH signal is strobed for each write cycle; the 16-bit memory, and table writes to any type of WRL pin is unused. The signal on the BA0 pin indicates word-wide external memories. This method makes a the LSb of the TBLPTR but it is left unconnected. distinction between TBLWT cycles to even or odd Instead, the UB and LB signals are active to select both addresses. bytes. The obvious limitation to this method is that the table write must be done in pairs on a specific word During a TBLWT cycle to an even address boundary to correctly write a word location. (TBLPTR<0>= 0), the TABLAT data is transferred to a holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. No write signals are activated. FIGURE 8-2: 16-BIT WORD WRITE MODE EXAMPLE PIC18F97J60 AD<7:0> 373 A<20:1> JEDEC Word A<x:0> EPROM Memory D<15:0> D<15:0> CE OE WR(2) AD<15:8> 373 ALE A<19:16>(1) CE OE WRH Address Bus Data Bus Control Lines Note 1: The upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”. DS39762F-page 120  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 8.6.3 16-BIT BYTE SELECT MODE Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC Figure8-3 shows an example of 16-Bit Byte Select standard Flash memories require that a controller I/O mode. This mode allows table write operations to port pin be connected to the memory’s BYTE/WORD word-wide external memories with byte selection pin to provide the select signal. They also use the BA0 capability. This generally includes both word-wide signal from the controller as a byte address. JEDEC Flash and SRAM devices. standard, static RAM memories, on the other hand, use During a TBLWT cycle, the TABLAT data is presented the UB or LB signals to select the byte. on the upper and lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is not used. The BA0 or UB/LB signals are used to select the byte to be written based on the Least Significant bit of the TBLPTR register. FIGURE 8-3: 16-BIT BYTE SELECT MODE EXAMPLE PIC18F97J60 A<20:1> AD<7:0> 373 A<x:1> JEDEC Word FLASH Memory D<15:0> D<15:0> 138(3) CE AD<15:8> 373 A0 ALE BYTE/WORD OE WR(1) A<19:16>(2) OE WRH A<20:1> A<x:1> JEDEC Word BA0 SRAM Memory I/O D<15:0> CE D<15:0> LB LB UB UB OE WR(1) CE Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”. 2: The upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed.  2011 Microchip Technology Inc. DS39762F-page 121

PIC18F97J60 FAMILY 8.6.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure8-4 and Figure8-5. FIGURE 8-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:0> CF33h 9256h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD* MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW Execution FIGURE 8-5: EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:0> 3AAAh 0003h 3AABh 0E55h CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction INST(PC – 2) SLEEP Execution DS39762F-page 122  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 8.7 8-Bit Data Width Mode will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the In 8-Bit Data Width mode, the external memory bus second byte will be enabled to form the 16-bit instruc- operates only in Multiplexed mode; that is, data shares tion word. The Least Significant bit of the address, BA0, the eight Least Significant bits of the address bus. must be connected to the memory devices in this Figure8-6 shows an example of 8-Bit Multiplexed mode mode. The Chip Enable signal (CE) is active at any for 100-pin devices. This mode is used for a single 8-bit time that the microcontroller accesses external memory connected for 16-bit operation. The instructions memory, whether reading or writing. It is inactive will be fetched as two 8-bit bytes on a shared (asserted high) whenever the device is in Sleep mode. data/address bus. The two bytes are sequentially This process generally includes basic EPROM and fetched within one instruction cycle (TCY). Therefore, the Flash devices. It allows table writes to byte-wide designer must choose external memory devices accord- external memories. ing to timing calculations based on 1/2TCY (2 times the During a TBLWT instruction cycle, the TABLAT data is instruction rate). For proper memory speed selection, presented on the upper and lower bytes of the glue logic propagation delay times must be considered, AD<15:0> bus. The appropriate level of the BA0 control along with setup and hold times. line is strobed on the LSb of the TBLPTR. The Address Latch Enable (ALE) pin indicates that the address bits, AD<15:0>, are available in the external memory interface bus. The Output Enable signal (OE) FIGURE 8-6: 8-BIT MULTIPLEXED MODE EXAMPLE D<7:0> PIC18F97J60 A<19:0> AD<7:0> 373 A<x:1> ALE D<15:8> A0 D<7:0> AD<15:8>(1) CE A<19:16>(1) OE WR(2) BA0 CE OE WRL Address Bus Data Bus Control Lines Note 1: The upper order address bits are used only for 20-bit address width. The upper AD byte is used for all address widths except 8-bit. 2: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”.  2011 Microchip Technology Inc. DS39762F-page 123

PIC18F97J60 FAMILY 8.7.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure8-7 and Figure8-8. FIGURE 8-7: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:8> CFh AD<7:0> 33h 92h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD* MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction Execution INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW FIGURE 8-8: EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:8> 3Ah 3Ah AD<7:0> AAh 00h 03h ABh 0Eh 55h BA0 CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction INST(PC – 2) SLEEP Execution DS39762F-page 124  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 8.8 Operation in Power-Managed In Sleep and Idle modes, the microcontroller core does Modes not need to access data; bus operations are suspended. The state of the external bus is frozen, with In alternate power-managed Run modes, the external the address/data pins and most of the control pins bus continues to operate normally. If a clock source with holding at the same state they were in when the mode a lower speed is selected, bus operations will run at that was invoked. The only potential changes are the CE, speed. In these cases, excessive access times for the LB and UB pins, which are held at logic high. external memory may result if Wait states have been enabled and added to external memory operations. If operations in a lower power Run mode are anticipated, user applications should provide memory access time adjustments at the lower clock speeds.  2011 Microchip Technology Inc. DS39762F-page 125

PIC18F97J60 FAMILY NOTES: DS39762F-page 126  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 9.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 9-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 9.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY register. ROUTINE Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the MOVF ARG1, W advantages of higher computational throughput and MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit allows the PIC18 devices to be used in many applica- SUBWF PRODH, F ; PRODH = PRODH tions previously reserved for digital signal processors. ; - ARG1 A comparison of various hardware and software MOVF ARG2, W multiply operations, along with the savings in memory BTFSC ARG1, SB ; Test Sign Bit and execution time, is shown in Table9-1. SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 9.2 Operation Example9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the argu- ments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 s 27.6 s 69 s 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 s Without hardware multiply 33 91 9.1 s 36.4 s 91 s 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 s 6 s Without hardware multiply 21 242 24.2 s 96.8 s 242 s 16 x 16 unsigned Hardware multiply 28 28 2.8 s 11.2 s 28 s Without hardware multiply 52 254 25.4 s 102.6 s 254 s 16 x 16 signed Hardware multiply 35 40 4.0 s 16.0 s 40 s  2011 Microchip Technology Inc. DS39762F-page 127

PIC18F97J60 FAMILY Example9-3 shows the sequence to do a 16 x 16 EQUATION 9-2: 16 x 16 SIGNED unsigned multiplication. Equation9-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0=ARG1H:ARG1L  ARG2H:ARG2L = (ARG1H  ARG2H  216) + EQUATION 9-1: 16 x 16 UNSIGNED (ARG1H  ARG2L  28) + MULTIPLICATION (ARG1L  ARG2H  28) + ALGORITHM (ARG1L  ARG2L) + (-1  ARG2H<7>  ARG1H:ARG1L  216) + RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L (-1  ARG1H<7>  ARG2H:ARG2L  216) = (ARG1H  ARG2H  216) + (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + EXAMPLE 9-4: 16 x 16 SIGNED (ARG1L  ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 9-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> ; PRODH:PRODL MULTIPLY ROUTINE MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example9-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation9-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers ; (RES3:RES0). To account for the sign bits of the SIGN_ARG1 BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? arguments, the MSb for each argument pair is tested BRA CONT_CODE ; no, done and the appropriate subtractions are done. MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS39762F-page 128  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 10.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are Members of the PIC18F97J60 family of devices have compatible with PIC® mid-range devices. In multiple interrupt sources and an interrupt priority feature Compatibility mode, the interrupt priority bits for each that allows most interrupt sources to be assigned a source have no effect. INTCON<6> is the PEIE bit high-priority level or a low-priority level. The high-priority which enables/disables all peripheral interrupt sources. interrupt vector is at 0008h and the low-priority interrupt INTCON<7> is the GIE bit which enables/disables all vector is at 0018h. High-priority interrupt events will interrupt sources. All interrupts branch to address, interrupt any low-priority interrupts that may be in 0008h, in Compatibility mode. progress. When an interrupt is responded to, the Global Interrupt There are thirteen registers which are used to control Enable bit is cleared to disable further interrupts. If the interrupt operation. These registers are: IPEN bit is cleared, this is the GIE bit. If interrupt priority • RCON levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a • INTCON low-priority interrupt. Low-priority interrupts are not • INTCON2 processed while high-priority interrupts are in progress. • INTCON3 The return address is pushed onto the stack and the • PIR1, PIR2, PIR3 PC is loaded with the interrupt vector address (0008h • PIE1, PIE2, PIE3 or 0018h). Once in the Interrupt Service Routine (ISR), • IPR1, IPR2, IPR3 the source(s) of the interrupt can be determined by poll- It is recommended that the Microchip header files ing the interrupt flag bits. The interrupt flag bits must be supplied with MPLAB® IDE be used for the symbolic bit cleared in software before re-enabling interrupts to names in these registers. This allows the avoid recursive interrupts. assembler/compiler to automatically take care of the The “return from interrupt” instruction, RETFIE, exits placement of these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL In general, interrupt sources have three bits to control if priority levels are used) which re-enables interrupts. their operation. They are: For external interrupt events, such as the INTx pins or • Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. • Enable bit that allows program execution to Individual interrupt flag bits are set regardless of the branch to the interrupt vector address when the status of their corresponding enable bit or the GIE bit. flag bit is set • Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while The interrupt priority feature is enabled by setting the any interrupt is enabled. Doing so may IPEN bit (RCON<7>). When interrupt priority is enabled, cause erratic microcontroller behavior. there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate Global Interrupt Enable bit are set, the interrupt will vector immediately to address, 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits.  2011 Microchip Technology Inc. DS39762F-page 129

PIC18F97J60 FAMILY FIGURE 10-1: PIC18F97J60 FAMILY INTERRUPT LOGIC TMR0IF Wake-up if in TMR0IE Idle or Sleep modes TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE Interrupt to CPU INT1IP Vector to Location INT2IF INT2IE 0008h PIR1<7:0> INT2IP PIE1<7:0> IPR1<7:0> INT3IF INT3IE INT3IP GIE/GIEH PIR2<7:5,3,1:0> PIE2<7:5,3,1:0> IPR2<7:5,3,1:0> IPEN PIR3<7:0> IPEN PIE3<7:0> PEIE/GIEL IPR3<7:0> IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:5,3,1:0> PIE2<7:5,3,1:0> IPR2<7:5,3,1:0> Interrupt to CPU PIR3<7:0> TTMMRR00IIEF IPEN V00e1c8tohr to Location PIE3<7:0> TMR0IP IPR3<7:0> RBIF RBIE RBIP GIE/GIEH PEIE/GIEL INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP DS39762F-page 130  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 10.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt The INTCON registers are readable and writable condition occurs regardless of the state of registers which contain various enable, priority and flag its corresponding enable bit or the Global bits. Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared.  2011 Microchip Technology Inc. DS39762F-page 131

PIC18F97J60 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39762F-page 132  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2011 Microchip Technology Inc. DS39762F-page 133

PIC18F97J60 FAMILY 10.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the Global peripheral interrupts. Due to the number of peripheral Interrupt Enable bit, GIE (INTCON<7>). interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART1 receive buffer is empty bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART1 transmit buffer is full bit 3 SSP1IF: MSSP1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: Implemented in 100-pin devices in Microcontroller mode only. DS39762F-page 134  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 OSCFIF CMIF ETHIF r BCL1IF — TMR3IF CCP2IF bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTRC (must be cleared in software) 0 = System clock is operating bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5 ETHIF: Ethernet Module Interrupt Flag bit 1 = An Ethernet module interrupt event has occurred; query EIR register to resolve source 0 = No Ethernet interrupt event has occurred bit 4 Reserved: Maintain as ‘0’ bit 3 BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 Unimplemented: Read as ‘0’ bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode.  2011 Microchip Technology Inc. DS39762F-page 135

PIC18F97J60 FAMILY REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF(1) BCL2IF(1) RC2IF(2) TX2IF(2) TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: MSSP2 Interrupt Flag bit(1) 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 6 BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module)(1) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 5 RC2IF: EUSART2 Receive Interrupt Flag bit(2) 1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The EUSART2 receive buffer is empty bit 4 TX2IF: EUSART2 Transmit Interrupt Flag bit(2) 1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The EUSART2 transmit buffer is full bit 3 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred bit 2 CCP5IF: CCP5 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 1 CCP4IF: CCP4 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 0 CCP3IF: ECCP3 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. Note 1: Implemented in 100-pin devices only. 2: Implemented in 80-pin and 100-pin devices only. DS39762F-page 136  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 SSP1IE: MSSP1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: Implemented in 100-pin devices in Microcontroller mode only.  2011 Microchip Technology Inc. DS39762F-page 137

PIC18F97J60 FAMILY REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 OSCFIE CMIE ETHIE r BCL1IE — TMR3IE CCP2IE bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 ETHIE: Ethernet Module Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 Reserved: Maintain as ‘0’ bit 3 BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module) 1 = Enabled 0 = Disabled bit 2 Unimplemented: Read as ‘0’ bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39762F-page 138  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE(1) BCL2IE(1) RC2IE(2) TX2IE(2) TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IE: MSSP2 Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)(1) 1 = Enabled 0 = Disabled bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit(2) 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit(2) 1 = Enabled 0 = Disabled bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP5IE: CCP5 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: Implemented in 100-pin devices only. 2: Implemented in 80-pin and 100-pin devices only.  2011 Microchip Technology Inc. DS39762F-page 139

PIC18F97J60 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSP1IP: MSSP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: Implemented in 100-pin devices in Microcontroller mode only. DS39762F-page 140  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 OSCFIP CMIP ETHIP r BCL1IP — TMR3IP CCP2IP bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ETHIP: Ethernet Module Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 Reserved: Maintain as ‘1’ bit 3 BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority bit 2 Unimplemented: Read as ‘0’ bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority  2011 Microchip Technology Inc. DS39762F-page 141

PIC18F97J60 FAMILY REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP(1) BCL2IP(1) RC2IP(2) TX2IP(2) TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IP: MSSP2 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)(1) 1 = High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit(2) 1 = High priority 0 = Low priority bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit(2) 1 = High priority 0 = Low priority bit 3 TMR4IE: TMR4 to PR4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP5IP: CCP5 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: Implemented in 100-pin devices only. 2: Implemented in 80-pin and 100-pin devices only. DS39762F-page 142  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 10-13: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0’ bit 5 CM: Configuration Mismatch Flag bit For details of bit operation, see Register5-1. bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register5-1. bit 3 TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register5-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register5-1. bit 1 POR: Power-on Reset Status bit(2) For details of bit operation, see Register5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register5-1.  2011 Microchip Technology Inc. DS39762F-page 143

PIC18F97J60 FAMILY 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0/FLT0, RB1/INT1, In 8-bit mode (which is the default), an overflow in the RB2/INT2 and RB3/INT3 pins are edge-triggered. If the TMR0 register (FFh00h) will set flag bit, TMR0IF. In corresponding INTEDGx bit in the INTCON2 register is 16-bit mode, an overflow in the TMR0H:TMR0L register set (= 1), the interrupt is triggered by a rising edge; if pair (FFFFh0000h) will set TMR0IF. The interrupt the bit is clear, the trigger is on the falling edge. When can be enabled/disabled by setting/clearing enable bit, a valid edge appears on the RBx/INTx pin, the TMR0IE (INTCON<5>). Interrupt priority for Timer0 is corresponding flag bit, INTxIF, is set. This interrupt can determined by the value contained in the interrupt be disabled by clearing the corresponding enable bit, priority bit, TMR0IP (INTCON2<2>). See Section12.0 INTxIE. Flag bit, INTxIF, must be cleared in software in “Timer0 Module” for further details on the Timer0 the Interrupt Service Routine (ISR) before re-enabling module. the interrupt. 10.8 PORTB Interrupt-on-Change All external interrupts (INT0, INT1, INT2 and INT3) can wake-up the processor from the power-managed An input change on PORTB<7:4> sets flag bit, RBIF modes if bit, INTxIE, was set prior to going into the (INTCON<0>). The interrupt can be enabled/disabled power-managed modes. If the Global Interrupt Enable by setting/clearing enable bit, RBIE (INTCON<3>). bit, GIE, is set, the processor will branch to the interrupt Interrupt priority for PORTB interrupt-on-change is vector following wake-up. determined by the value contained in the interrupt Interrupt priority for INT1, INT2 and INT3 is determined priority bit, RBIP (INTCON2<0>). by the value contained in the Interrupt Priority bits, INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and 10.9 Context Saving During Interrupts INT3IP (INTCON2<1>). There is no priority bit associated with INT0. It is always a high-priority During interrupts, the return PC address is saved on interrupt source. the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack (FSR). If a fast return from interrupt is not used (see Section6.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 10-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS39762F-page 144  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 11.0 I/O PORTS 11.1 I/O Port Pin Capabilities Depending on the device selected and features When developing an application, the capabilities of the enabled, there are up to nine ports available. Some port pins must be considered. Outputs on some pins pins of the I/O ports are multiplexed with an alternate have higher output drive strength than others. Similarly, function from the peripheral features on the device. In some pins can tolerate higher than VDD input levels. general, when a peripheral is enabled, that pin may not 11.1.1 PIN OUTPUT DRIVE be used as a general purpose I/O pin. Each port has three registers for its operation. These The output pin drive strengths vary for groups of pins registers are: intended to meet the needs for a variety of applications. PORTB and PORTC are designed to drive higher • TRIS register (Data Direction register) loads, such as LEDs. The external memory interface • PORT register (reads the levels on the pins of the ports (PORTD, PORTE and PORTJ) are designed to device) drive medium loads. All other ports are designed for • LAT register (Output Latch register) small loads, typically indication only. Table11-1 sum- marizes the output capabilities. Refer to Section28.0 The Output Latch (LAT register) is useful for “Electrical Characteristics” for more details. read-modify-write operations on the value that the I/O pins are driving. TABLE 11-1: OUTPUT DRIVE LEVELS A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure11-1. Port Drive Description PORTA(1) Minimum Intended for indication. FIGURE 11-1: GENERIC I/O PORT PORTF(2) OPERATION PORTG(2) PORTH(3) RD LAT PORTD(2) Medium Sufficient drive levels for external memory interfacing, Data PORTE Bus as well as indication. D Q PORTJ(3) WR LAT I/O Pin PORTB High Suitable for direct LED drive or PORT CK PORTC levels. Data Latch Note 1: The exceptions are RA<1:0>, which are D Q capable of directly driving LEDs. 2: Partially implemented on 64-pin and WR TRIS CK 80-pin devices; fully implemented on TRIS Latch Input 100-pin devices. Buffer 3: Unimplemented on 64-pin devices. RD TRIS Q D ENEN RD PORT  2011 Microchip Technology Inc. DS39762F-page 145

PIC18F97J60 FAMILY 11.1.2 INPUT PINS AND VOLTAGE The RA4 pin is multiplexed with the Timer0 module CONSIDERATIONS clock input to become the RA4/T0CKI pin. The other PORTA pins are multiplexed with the analog VREF+ and The voltage tolerance of pins used as device inputs is VREF- inputs. The operation of pins, RA<5:0>, as A/D dependent on the pin’s input function. Pins that are used Converter inputs is selected by clearing or setting the as digital only inputs are able to handle DC voltages up PCFG<3:0> control bits in the ADCON1 register. to 5.5V, a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind Note: RA5 and RA<3:0> are configured as can only tolerate voltages up to VDD. Voltage excursions analog inputs on any Reset and are read beyond VDD on these pins are always to be avoided. as ‘0’. RA4 is configured as a digital input. Table11-2 summarizes the input capabilities. Refer to The RA4/T0CKI pin is a Schmitt Trigger input. All other Section28.0 “Electrical Characteristics” for more PORTA pins have TTL input levels and full CMOS details. output drivers. TABLE 11-2: INPUT VOLTAGE LEVELS The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. Tolerated Port or Pin Description The user must ensure the bits in the TRISA register are Input maintained set when using them as analog inputs. PORTA<5,3:0> VDD Only VDD input levels The RA0 and RA1 pins can also be configured as the PORTF<6:1>(1) tolerated. outputs for the two Ethernet LED indicators. When PORTH<7:4>(2) configured, these two pins are the only pins on PORTA that are capable of high output drive levels. PORTA<4> 5.5V Tolerates input levels Although the port is only six bits wide, PORTA<7> is PORTB<7:0> above VDD, useful for implemented as RJPU, the weak pull-up control bit for most standard logic. PORTC<7:0> PORTJ. In a similar fashion, the LATA<7:6> bits are PORTD<7:0>(1) implemented, not as latch bits, but the pull-up control bits, RDPU and REPU, for PORTD and PORTE. PORTE<7:0> Setting these bits enables the pull-ups for the corre- PORTF<7> sponding port. Because their port pins are not used, the PORTG<7:0>(1) TRISA<7:6> bits are not implemented. PORTH<3:0>(2) PORTJ<7:0>(2) EXAMPLE 11-1: INITIALIZING PORTA Note 1: Partially implemented on 64-pin and CLRF PORTA ; Initialize PORTA by 80-pin devices; fully implemented on ; clearing output ; data latches 100-pin devices. CLRF LATA ; Alternate method 2: Unavailable in 64-pin devices. ; to clear output ; data latches 11.2 PORTA, TRISA and MOVLW 07h ; Configure A/D MOVWF ADCON1 ; for digital inputs LATA Registers MOVWF 07h ; Configure comparators PORTA is a 6-bit wide, bidirectional port; it is fully MOVWF CMCON ; for digital input MOVLW 0CFh ; Value used to implemented on all devices. The corresponding Data ; initialize data Direction register is TRISA. Setting a TRISA bit (= 1) ; direction will make the corresponding PORTA pin an input (i.e., MOVWF TRISA ; Set RA<3:0> as inputs put the corresponding output driver in a ; RA<5:4> as outputs High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Output Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. DS39762F-page 146  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 11-3: PORTA FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RA0/LEDA/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input is enabled. LEDA 0 O DIG Ethernet LEDA output; takes priority over digital data. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. RA1/LEDB/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input is enabled. LEDB 0 O DIG Ethernet LEDB output; takes priority over digital data. AN1 1 I ANA A/D Input Channel 1. Default input configuration on POR; does not affect digital output. RA2/AN2/VREF- RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when CVREF output is enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions are enabled; disabled when CVREF output is enabled. AN2 1 I ANA A/D Input Channel 2 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. VREF- 1 I ANA A/D and comparator low reference voltage input. RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input is enabled. AN3 1 I ANA A/D Input Channel 3. Default input configuration on POR. VREF+ 1 I ANA A/D high reference voltage input. RA4/T0CKI RA4 0 O DIG LATA<4> data output. 1 I ST PORTA<4> data input; default configuration on POR. T0CKI x I ST Timer0 clock input. RA5/AN4 RA5 0 O DIG LATA<5> data output; not affected by analog input. 1 I TTL PORTA<5> data input; disabled when analog input is enabled. AN4 1 I ANA A/D Input Channel 4. Default configuration on POR. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTA RJPU(1) — RA5 RA4 RA3 RA2 RA1 RA0 72 LATA RDPU REPU LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 72 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 71 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 70 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: Implemented in 80-pin and 100-pin devices only.  2011 Microchip Technology Inc. DS39762F-page 147

PIC18F97J60 FAMILY 11.3 PORTB, TRISB and Four of the PORTB pins (RB<7:4>) have an LATB Registers interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any PORTB is an 8-bit wide, bidirectional port; it is fully RB<7:4> pin configured as an output is excluded from implemented on all devices. The corresponding Data the interrupt-on-change comparison). The input pins (of Direction register is TRISB. Setting a TRISB bit (= 1) RB<7:4>) are compared with the old value latched on will make the corresponding PORTB pin an input (i.e., the last read of PORTB. The “mismatch” outputs of put the corresponding output driver in a RB<7:4> are ORed together to generate the RB Port High-Impedance mode). Clearing a TRISB bit (= 0) will Change Interrupt Flag bit, RBIF (INTCON<0>). make the corresponding PORTB pin an output (i.e., put This interrupt can wake the device from the contents of the output latch on the selected pin). All power-managed modes. The user, in the Interrupt pins on PORTB are digital only and tolerate voltages up Service Routine, can clear the interrupt in the following to 5.5V. manner: The Output Latch register (LATB) is also memory a) Any read or write of PORTB (except with the mapped. Read-modify-write operations on the LATB MOVFF (ANY), PORTB instruction). This will register read and write the latched output value for end the mismatch condition. PORTB. b) Clear flag bit, RBIF. EXAMPLE 11-2: INITIALIZING PORTB A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and CLRF PORTB ; Initialize PORTB by allow flag bit, RBIF, to be cleared. ; clearing output ; data latches The interrupt-on-change feature is recommended for CLRF LATB ; Alternate method wake-up on key depression operation and operations ; to clear output where PORTB is only used for the interrupt-on-change ; data latches feature. Polling of PORTB is not recommended while MOVLW 0CFh ; Value used to using the interrupt-on-change feature. ; initialize data ; direction For 100-pin devices operating in Extended Micro- MOVWF TRISB ; Set RB<3:0> as inputs controller mode, RB3 can be configured as the ; RB<5:4> as outputs alternate peripheral pin for the ECCP2 module and ; RB<7:6> as inputs Enhanced PWM Output 2A by clearing the CCP2MX Configuration bit. If the devices are in Microcontroller Each of the PORTB pins has a weak internal pull-up. A mode, the alternate assignment for ECCP2 is RE7. As single control bit can turn on all of the pull-ups. This is with other ECCP2 configurations, the user must ensure performed by clearing bit, RBPU (INTCON2<7>). The that the TRISB<3> bit is set appropriately for the weak pull-up is automatically turned off when the port intended operation. pin is configured as an output. The pull-ups are disabled on all Resets. DS39762F-page 148  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 11-5: PORTB FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RB0/INT0/FLT0 RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. INT0 1 I ST External Interrupt 0 input. FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software. RB1/INT1 RB1 0 O DIG LATB<1> data output. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. INT1 1 I ST External Interrupt 1 input. RB2/INT2 RB2 0 O DIG LATB<2> data output. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. INT2 1 I ST External Interrupt 2 input. RB3/INT3/ RB3 0 O DIG LATB<3> data output. ECCP2/P2A 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. INT3 1 I ST External Interrupt 3 input. ECCP2(1) 0 O DIG ECCP2 compare output and PWM output; takes priority over port data. 1 I ST ECCP2 capture input. P2A(1) 0 O DIG ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RB4/KBI0 RB4 0 O DIG LATB<4> data output. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. KBI0 1 I TTL Interrupt-on-pin change. RB5/KBI1 RB5 0 O DIG LATB<5> data output. 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 I TTL Interrupt-on-pin change. RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-pin change. PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(2) RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-pin change. PGD x O DIG Serial execution data output for ICSP and ICD operation.(2) x I ST Serial execution data input for ICSP and ICD operation.(2) Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (100-pin devices in Extended Microcontroller mode). Default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD is enabled.  2011 Microchip Technology Inc. DS39762F-page 149

PIC18F97J60 FAMILY TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 72 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 72 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 71 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 69 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 69 Legend: Shaded cells are not used by PORTB. DS39762F-page 150  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 11.4 PORTC, TRISC and Note: These pins are configured as digital inputs LATC Registers on any device Reset. PORTC is an 8-bit wide, bidirectional port; it is fully The contents of the TRISC register are affected by implemented on all devices. The corresponding Data peripheral overrides. Reading TRISC always returns Direction register is TRISC. Setting a TRISC bit (= 1) the current contents, even though a peripheral device will make the corresponding PORTC pin an input (i.e., may be overriding one or more of the pins. put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will EXAMPLE 11-3: INITIALIZING PORTC make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). CLRF PORTC ; Initialize PORTC by ; clearing output Only PORTC pins, RC2 through RC7, are digital only ; data latches pins and can tolerate input voltages up to 5.5V. CLRF LATC ; Alternate method The Output Latch register (LATC) is also memory ; to clear output mapped. Read-modify-write operations on the LATC ; data latches register read and write the latched output value for MOVLW 0CFh ; Value used to PORTC. ; initialize data ; direction PORTC is multiplexed with several peripheral functions MOVWF TRISC ; Set RC<3:0> as inputs (Table11-7). The pins have Schmitt Trigger input ; RC<5:4> as outputs buffers. RC1 is normally configured by Configuration ; RC<7:6> as inputs bit, CCP2MX, as the default peripheral pin for the ECCP2 module and Enhanced PWM output, P2A (default state, CCP2MX = 1). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.  2011 Microchip Technology Inc. DS39762F-page 151

PIC18F97J60 FAMILY TABLE 11-7: PORTC FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RC0/T1OSO/ RC0 0 O DIG LATC<0> data output. T13CKI 1 I ST PORTC<0> data input. T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator is enabled. Disables digital I/O. T13CKI 1 I ST Timer1/Timer3 counter input. RC1/T1OSI/ RC1 0 O DIG LATC<1> data output. ECCP2/P2A 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator is enabled. Disables digital I/O. ECCP2(1) 0 O DIG ECCP2 compare output and PWM output; takes priority over port data. 1 I ST ECCP2 capture input. P2A(1) 0 O DIG ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC2/ECCP1/ RC2 0 O DIG LATC<2> data output. P1A 1 I ST PORTC<2> data input. ECCP1 0 O DIG ECCP1 compare output and PWM output; takes priority over port data. 1 I ST ECCP1 capture input. P1A 0 O DIG ECCP1 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC3/SCK1/ RC3 0 O DIG LATC<3> data output. SCL1 1 I ST PORTC<3> data input. SCK1 0 O DIG SPI clock output (MSSP1 module); takes priority over port data. 1 I ST SPI clock input (MSSP1 module). SCL1 0 O DIG I2C™ clock output (MSSP1 module); takes priority over port data. 1 I ST I2C clock input (MSSP1 module); input type depends on module setting. RC4/SDI1/ RC4 0 O DIG LATC<4> data output. SDA1 1 I ST PORTC<4> data input. SDI1 1 I ST SPI data input (MSSP1 module). SDA1 1 O DIG I2C data output (MSSP1 module); takes priority over port data. 1 I ST I2C data input (MSSP1 module); input type depends on module setting. RC5/SDO1 RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO1 0 O DIG SPI data output (MSSP1 module); takes priority over port data. RC6/TX1/CK1 RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX1 1 O DIG Synchronous serial data output (EUSART1 module); takes priority over port data. CK1 1 O DIG Synchronous serial data input (EUSART1 module). User must configure as an input. 1 I ST Synchronous serial clock input (EUSART1 module). RC7/RX1/DT1 RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX1 1 I ST Asynchronous serial receive data input (EUSART1 module). DT1 1 O DIG Synchronous serial data output (EUSART1 module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART1 module). User must configure as an input. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. DS39762F-page 152  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 72 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 72 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 71  2011 Microchip Technology Inc. DS39762F-page 153

PIC18F97J60 FAMILY 11.5 PORTD, TRISD and Each of the PORTD pins has a weak internal pull-up. A LATD Registers single control bit can turn on all of the pull-ups. This is performed by setting the RDPU bit (LATA<7>). The PORTD is implemented as a bidirectional port in two weak pull-up is automatically turned off when the port ways: pin is configured as an output. The pull-ups are • 64-pin and 80-pin devices: 3 bits (RD<2:0>) disabled on all device Resets. • 100-pin devices: 8 bits (RD<7:0>) On 100-pin devices, PORTD can also be configured to function as an 8-bit wide, parallel microprocessor port The corresponding Data Direction register is TRISD. by setting the PSPMODE control bit (PSPCON<4>). In Setting a TRISD bit (= 1) will make the corresponding this mode, parallel port data takes priority over other PORTD pin an input (i.e., put the corresponding output digital I/O (but not the external memory interface). driver in a High-Impedance mode). Clearing a TRISD When the parallel port is active, the input buffers are bit (= 0) will make the corresponding PORTD pin an TTL. For more information, refer to Section11.11 output (i.e., put the contents of the output latch on the “Parallel Slave Port (PSP)”. selected pin). All pins on PORTD are digital only and tolerate voltages up to 5.5V. EXAMPLE 11-4: INITIALIZING PORTD The Output Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD CLRF PORTD ; Initialize PORTD by register read and write the latched output value for ; clearing output PORTD. ; data latches CLRF LATD ; Alternate method All pins on PORTD are implemented with Schmitt ; to clear output Trigger input buffers. Each pin is individually ; data latches configurable as an input or output. MOVLW 0CFh ; Value used to ; initialize data Note: These pins are configured as digital inputs ; direction on any device Reset. MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs On 100-pin devices, PORTD is multiplexed with the ; RD<7:6> as inputs system bus as part of the external memory interface. I/O port and other functions are only available when the interface is disabled by setting the EBDIS bit (MEMCON<7>). When the interface is enabled, PORTD is the low-order byte of the multiplexed address/data bus (AD<7:0>). The TRISD bits are also overridden. DS39762F-page 154  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 11-9: PORTD FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RD0/AD0/PSP0 RD0 0 O DIG LATD<0> data output. (RD0/P1B) 1 I ST PORTD<0> data input; weak pull-up when RDPU bit is set. AD0(1) x O DIG External memory interface, Address/Data Bit 0 output.(2) x I TTL External memory interface, Data Bit 0 input.(2) PSP0(1) x O DIG PSP read output data (LATD<0>); takes priority over port data. x I TTL PSP write data input. P1B(3) 0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD1/AD1/PSP1 RD1 0 O DIG LATD<1> data output. (RD1/ECCP3/ 1 I ST PORTD<1> data input; weak pull-up when RDPU bit is set. P3A) AD1(1) x O DIG External memory interface, Address/Data Bit 1 output.(2) x I TTL External memory interface, Data Bit 1 input.(2) PSP1(1) x O DIG PSP read output data (LATD<1>); takes priority over port data. x I TTL PSP write data input. ECCP3(3) 0 O DIG ECCP3 compare and PWM output; takes priority over port data. 1 I ST ECCP3 capture input. P3A(3) 0 O DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD2/AD2/PSP2 RD2 0 O DIG LATD<2> data output. (RD2/CCP4/ 1 I ST PORTD<2> data input; weak pull-up when RDPU bit is set. P3D) AD2(1) x O DIG External memory interface, Address/Data Bit 2 output.(2) x I TTL External memory interface, Data Bit 2 input.(2) PSP2(1) x O DIG PSP read output data (LATD<2>); takes priority over port data. x I TTL PSP write data input. CCP4(3) 0 O DIG CCP4 compare output and PWM output; takes priority over port data. 1 I ST CCP4 capture input. P3D(3) 0 O DIG ECCP3 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD3/AD3/ RD3(1) 0 O DIG LATD<3> data output. PSP3(1) 1 I ST PORTD<3> data input; weak pull-up when RDPU bit is set. AD3(1) x O DIG External memory interface, Address/Data Bit 3 output.(2) x I TTL External memory interface, Data Bit 3 input.(2) PSP3(1) x O DIG PSP read output data (LATD<3>); takes priority over port data. x I TTL PSP write data input. RD4/AD4/ RD4(1) 0 O DIG LATD<4> data output. PSP4/SDO2(1) 1 I ST PORTD<4> data input; weak pull-up when RDPU bit is set. AD4(1) x O DIG External memory interface, Address/Data Bit 4 output.(2) x I TTL External memory interface, Data Bit 4 input.(2) PSP4(1) x O DIG PSP read output data (LATD<4>); takes priority over port data. x I TTL PSP write data input. SDO2(1) 0 O DIG SPI data output (MSSP2 module); takes priority over port data. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: These features or port pins are implemented only on 100-pin devices. 2: External memory interface I/O takes priority over all other digital and PSP I/O. 3: These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D).  2011 Microchip Technology Inc. DS39762F-page 155

PIC18F97J60 FAMILY TABLE 11-9: PORTD FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RD5/AD5/ RD5(1) 0 O DIG LATD<5> data output. PSP5/SDI2/ 1 I ST PORTD<5> data input; weak pull-up when RDPU bit is set. SDA2(1) AD5(1) x O DIG External memory interface, Address/Data Bit 5 output.(2) x I TTL External memory interface, Data Bit 5 input.(2) PSP5(1) x O DIG PSP read output data (LATD<5>); takes priority over port data. x I TTL PSP write data input. SDI2(1) 1 I ST SPI data input (MSSP2 module). SDA2(1) 1 O DIG I2C™ data output (MSSP2 module); takes priority over port data. 1 I ST I2C data input (MSSP2 module); input type depends on module setting. RD6/AD6/ RD6(1) 0 O DIG LATD<6> data output. PSP6/SCK2/ 1 I ST PORTD<6> data input; weak pull-up when RDPU bit is set. SCL2(1) AD6(1) x O DIG-3 External memory interface, Address/Data Bit 6 output.(2) x I TTL External memory interface, Data Bit 6 input.(2) PSP6(1) x O DIG PSP read output data (LATD<6>); takes priority over port data. x I TTL PSP write data input. SCK2(1) 0 O DIG SPI clock output (MSSP2 module); takes priority over port data. 1 I ST SPI clock input (MSSP2 module). SCL2(1) 0 O DIG I2C clock output (MSSP2 module); takes priority over port data. 1 I ST I2C clock input (MSSP2 module); input type depends on module setting. RD7/AD7/ RD7(1) 0 O DIG LATD<7> data output. PSP7/SS2(1) 1 I ST PORTD<7> data input; weak pull-up when RDPU bit is set. AD7(1) x O DIG External memory interface, Address/Data Bit 7 output.(2) x I TTL External memory interface, Data Bit 7 input.(2) PSP7(1) x O DIG PSP read output data (LATD<7>); takes priority over port data. x I TTL PSP write data input. SS2(1) x I TTL Slave select input for MSSP2 module. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: These features or port pins are implemented only on 100-pin devices. 2: External memory interface I/O takes priority over all other digital and PSP I/O. 3: These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D). TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTD RD7(1) RD6(1) RD5(1) RD4(1) RD3(1) RD2 RD1 RD0 72 LATD LATD7(1) LATD6(1) LATD5(1) LATD4(1) LATD3(1) LATD2 LATD1 LATD0 72 TRISD TRISD7(1) TRISD6(1) TRISD5(1) TRISD4(1) TRISD3(1) TRISD2 TRISD1 TRISD0 71 LATA RDPU REPU LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 72 Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on 64-pin and 80-pin devices; read as ‘0’. DS39762F-page 156  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 11.6 PORTE, TRISE and PORTE is also multiplexed with Enhanced PWM LATE Registers Outputs B and C for ECCP1 and ECCP3 and Outputs B, C and D for ECCP2. For 80-pin and 100-pin devices, PORTE is implemented as a bidirectional port in two their default assignments are on PORTE<6:0>. For different ways: 64-pin devices, their default assignments are on • 64-pin devices: 6 bits wide (RE<5:0>) PORTE<5:0> and PORTD<0>. On 80-pin and 100-pin devices, the multiplexing for the outputs of ECCP1 and • 80-pin and 100-pin devices: 8 bits wide (RE<7:0>) ECCP3 is controlled by the ECCPMX Configuration bit. The corresponding Data Direction register is TRISE. Clearing this bit reassigns the P1B/P1C and P3B/P3C Setting a TRISE bit (= 1) will make the corresponding outputs to PORTH. PORTE pin an input (i.e., put the corresponding output For 80-pin and 100-pin devices operating in Micro- driver in a High-Impedance mode). Clearing a TRISE controller mode, pin, RE7, can be configured as the bit (= 0) will make the corresponding PORTE pin an alternate peripheral pin for the ECCP2 module and output (i.e., put the contents of the output latch on the Enhanced PWM Output 2A. This is done by clearing selected pin). All pins on PORTE are digital only and the CCP2MX Configuration bit. tolerate voltages up to 5.5V. When the Parallel Slave Port is active on PORTD, three The Output Latch register (LATE) is also memory of the PORTE pins (RE0, RE1 and RE2) are configured mapped. Read-modify-write operations on the LATE as digital control inputs for the port. The control register read and write the latched output value for functions are summarized in Table11-11. The reconfig- PORTE. uration occurs automatically when the PSPMODE All pins on PORTE are implemented with Schmitt control bit (PSPCON<4>) is set. Users must still make Trigger input buffers. Each pin is individually certain the corresponding TRISE bits are set to configurable as an input or output. configure these pins as digital inputs. Note: These pins are configured as digital inputs EXAMPLE 11-5: INITIALIZING PORTE on any device Reset. CLRF PORTE ; Initialize PORTE by On 100-pin devices, PORTE is multiplexed with the ; clearing output system bus as part of the external memory interface. ; data latches I/O port and other functions are only available when the CLRF LATE ; Alternate method interface is disabled by setting the EBDIS bit ; to clear output (MEMCON<7>). When the interface is enabled, ; data latches PORTE is the high-order byte of the multiplexed MOVLW 03h ; Value used to ; initialize data address/data bus (AD<15:8>). The TRISE bits are also ; direction overridden. MOVWF TRISE ; Set RE<1:0> as inputs Each of the PORTE pins has a weak internal pull-up. A ; RE<7:2> as outputs single control bit can turn on all of the pull-ups. This is performed by setting bit, REPU (LATA<6>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on all device Resets.  2011 Microchip Technology Inc. DS39762F-page 157

PIC18F97J60 FAMILY TABLE 11-11: PORTE FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RE0/AD8/RD/ RE0 0 O DIG LATE<0> data output. P2D 1 I ST PORTE<0> data input; weak pull-up when REPU bit is set. AD8(1) x O DIG External memory interface, Address/Data Bit 8 output.(2) x I TTL External memory interface, Data bit 8 input.(2) RD(6) 1 I TTL Parallel Slave Port read enable control input. P2D 0 O DIG ECCP2 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE1/AD9/WR/ RE1 0 O DIG LATE<1> data output. P2C 1 I ST PORTE<1> data input; weak pull-up when REPU bit is set. AD9(1) x O DIG External memory interface, Address/Data Bit 9 output.(2) x I TTL External memory interface, Data Bit 9 input.(2) WR(6) 1 I TTL Parallel Slave Port write enable control input. P2C 0 O DIG ECCP2 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE2/AD10/CS/ RE2 0 O DIG LATE<2> data output. P2B 1 I ST PORTE<2> data input; weak pull-up when REPU bit is set. AD10(1) x O DIG External memory interface, Address/Data Bit 10 output.(2) x I TTL External memory interface, Data Bit 10 input.(2) CS(6) 1 I TTL Parallel Slave Port chip select control input. P2B 0 O DIG ECCP2 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE3/AD11/ RE3 0 O DIG LATE<3> data output. P3C 1 I ST PORTE<3> data input; weak pull-up when REPU bit is set. AD11(1) x O DIG External memory interface, Address/Data Bit 11 output.(2) x I TTL External memory interface, Data Bit 11 input.(2) P3C(3) 0 O DIG ECCP3 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE4/AD12/ RE4 0 O DIG LATE<4> data output. P3B 1 I ST PORTE<4> data input; weak pull-up when REPU bit is set. AD12(1) x O DIG External memory interface, Address/Data Bit 12 output.(2) x I TTL External memory interface, Data Bit 12 input.(2) P3B(3) 0 O DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: EMB functions are implemented on 100-pin devices only. 2: External memory interface I/O takes priority over all other digital and PSP I/O. 3: Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin and 100-pin devices). 4: Unimplemented on 64-pin devices. 5: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (80-pin and 100-pin devices in Microcontroller mode). 6: Unimplemented on 64-pin and 80-pin devices. DS39762F-page 158  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 11-11: PORTE FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RE5/AD13/ RE5 0 O DIG LATE<5> data output. P1C 1 I ST PORTE<5> data input; weak pull-up when REPU bit is set. AD13(1) x O DIG External memory interface, Address/Data Bit 13 output.(2) x I TTL External memory interface, Data Bit 13 input.(2) P1C(3) 0 O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE6/AD14/ RE6 0 O DIG LATE<6> data output. P1B(4) 1 I ST PORTE<6> data input; weak pull-up when REPU bit is set. AD14(1) x O DIG External memory interface, Address/Data Bit 14 output.(2) x I TTL External memory interface, Data Bit 14 input.(2) P1B(3) 0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE7/AD15/ RE7 0 O DIG LATE<7> data output. ECCP2/P2A(4) 1 I ST PORTE<7> data input; weak pull-up when REPU bit is set. AD15(1) x O DIG External memory interface, Address/Data Bit 15 output.(2) x I TTL External memory interface, Data Bit 15 input.(2) ECCP2(5) 0 O DIG ECCP2 compare output and PWM output; takes priority over port data. 1 I ST ECCP2 capture input. P2A(5) 0 O DIG ECCP2 Enhanced PWM output, Channel A; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: EMB functions are implemented on 100-pin devices only. 2: External memory interface I/O takes priority over all other digital and PSP I/O. 3: Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin and 100-pin devices). 4: Unimplemented on 64-pin devices. 5: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (80-pin and 100-pin devices in Microcontroller mode). 6: Unimplemented on 64-pin and 80-pin devices. TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTE RE7(1) RE6(1) RE5 RE4 RE3 RE2 RE1 RE0 72 LATE LATE7(1) LATE6(1) LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 72 TRISE TRISE7(1) TRISE6(1) TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 71 LATA RDPU REPU LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices; read as ‘0’.  2011 Microchip Technology Inc. DS39762F-page 159

PIC18F97J60 FAMILY 11.7 PORTF, LATF and TRISF Registers Note1: On device Resets, pins, RF<6:1>, are PORTF is implemented as a bidirectional port in two configured as analog inputs and are read different ways: as ‘0’. • 64-pin and 80-pin devices: 7 bits wide (RF<7:1>) 2: To configure PORTF as digital I/O, turn off the comparators and set the ADCON1 • 100-pin devices: 8 bits wide (RF<7:0>) value. The corresponding Data Direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISF EXAMPLE 11-6: INITIALIZING PORTF bit (= 0) will make the corresponding PORTF pin an CLRF PORTF ; Initialize PORTF by output (i.e., put the contents of the output latch on the ; clearing output selected pin). Only Pin 7 of PORTF has no analog ; data latches input; it is the only pin that can tolerate voltages up to CLRF LATF ; Alternate method 5.5V. ; to clear output ; data latches The Output Latch register (LATF) is also memory MOVLW 07h ; mapped. Read-modify-write operations on the LATF MOVWF CMCON ; Turn off comparators register read and write the latched output value for MOVLW 0Fh ; PORTF. MOVWF ADCON1 ; Set PORTF as digital I/O All pins on PORTF are implemented with Schmitt MOVLW 0CEh ; Value used to ; initialize data Trigger input buffers. Each pin is individually ; direction configurable as an input or output. MOVWF TRISF ; Set RF3:RF1 as inputs PORTF is multiplexed with several analog peripheral ; RF5:RF4 as outputs functions, including the A/D Converter and comparator ; RF7:RF6 as inputs inputs, as well as the comparator outputs. Pins, RF1 through RF6, may be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register. To use RF<6:1> as digital inputs, it is also necessary to turn off the comparators. DS39762F-page 160  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 11-13: PORTF FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RF0/AN5(1) RF0(1) 0 O DIG LATF<0> data output; not affected by analog input. 1 I ST PORTF<0> data input; disabled when analog input is enabled. AN5(1) 1 I ANA A/D Input Channel 5. Default configuration on POR. RF1/AN6/ RF1 0 O DIG LATF<1> data output; not affected by analog input. C2OUT 1 I ST PORTF<1> data input; disabled when analog input is enabled. AN6 1 I ANA A/D Input Channel 6. Default configuration on POR. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. RF2/AN7/ RF2 0 O DIG LATF<2> data output; not affected by analog input. C1OUT 1 I ST PORTF<2> data input; disabled when analog input is enabled. AN7 1 I ANA A/D Input Channel 7. Default configuration on POR. C1OUT 0 O TTL Comparator 1 output; takes priority over port data. RF3/AN8 RF3 0 O DIG LATF<3> data output; not affected by analog input. 1 I ST PORTF<3> data input; disabled when analog input is enabled. AN8 1 I ANA A/D Input Channel 8 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. RF4/AN9 RF4 0 O DIG LATF<4> data output; not affected by analog input. 1 I ST PORTF<4> data input; disabled when analog input is enabled. AN9 1 I ANA A/D Input Channel 9 and Comparator C2- input. Default input configuration on POR; does not affect digital output. RF5/AN10/ RF5 0 O DIG LATF<5> data output; not affected by analog input. Disabled when CVREF CVREF output is enabled. 1 I ST PORTF<5> data input; disabled when analog input is enabled. Disabled when CVREF output is enabled. AN10 1 I ANA A/D Input Channel 10 and Comparator C1+ input. Default input configuration on POR. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RF6/AN11 RF6 0 O DIG LATF<6> data output; not affected by analog input. 1 I ST PORTF<6> data input; disabled when analog input is enabled. AN11 1 I ANA A/D Input Channel 11 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RF7/SS1 RF7 0 O DIG LATF<7> data output. 1 I ST PORTF<7> data input. SS1 1 I TTL Slave select input for MSSP1 module. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Implemented on 100-pin devices only. TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0(1) 72 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0(1) 72 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0(1) 71 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 70 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 70 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 70 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. Note 1: Implemented on 100-pin devices only.  2011 Microchip Technology Inc. DS39762F-page 161

PIC18F97J60 FAMILY 11.8 PORTG, TRISG and When enabling peripheral functions, care should be LATG Registers taken in defining TRIS bits for each PORTG pin. Some peripherals override the TRIS bit to make a pin an Depending on the particular device, PORTG is output, while other peripherals override the TRIS bit to implemented as a bidirectional port in one of three make a pin an input. The user should refer to the ways: corresponding peripheral section for the correct TRIS • 64-pin devices: 1 bit wide (RG<4>) bit settings. The pin override value is not loaded into the TRIS register. This allows read-modify-write of the • 80-pin devices: 5 bits wide (RG<4:0>) TRIS register without concern due to peripheral • 100-pin devices: 8 bits wide (RG<7:0>) overrides. The corresponding Data Direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding EXAMPLE 11-7: INITIALIZING PORTG PORTG pin an input (i.e., put the corresponding output CLRF PORTG ; Initialize PORTG by driver in a High-Impedance mode). Clearing a TRISG ; clearing output bit (= 0) will make the corresponding PORTG pin an ; data latches output (i.e., put the contents of the output latch on the CLRF LATG ; Alternate method selected pin). All pins on PORTG are digital only and ; to clear output tolerate voltages up to 5.5V. ; data latches The Output Latch register (LATG) is also memory MOVLW 04h ; Value used to ; initialize data mapped. Read-modify-write operations on the LATG ; direction register read and write the latched output value for MOVWF TRISG ; Set RG1:RG0 as outputs PORTG. ; RG2 as input PORTG is multiplexed with EUSART2 functions on ; RG4:RG3 as inputs 80-pin and 100-pin devices (Table11-15). PORTG pins have Schmitt Trigger input buffers. DS39762F-page 162  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 11-15: PORTG FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RG0/ECCP3/ RG0(1) 0 O DIG LATG<0> data output. P3A(1) 1 I ST PORTG<0> data input. ECCP3(1) 0 O DIG ECCP3 compare and PWM output; takes priority over port data. 1 I ST ECCP3 capture input. P3A(1) 0 O DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RG1/TX2/ RG1(1) 0 O DIG LATG<1> data output. CK2(1) 1 I ST PORTG<1> data input. TX2(1) 1 O DIG Synchronous serial data output (EUSART2 module); takes priority over port data. CK2(1) 1 O DIG Synchronous serial data input (EUSART2 module). User must configure as an input. 1 I ST Synchronous serial clock input (EUSART2 module). RG2/RX2/ RG2(1) 0 O DIG LATG<2> data output. DT2(1) 1 I ST PORTG<2> data input. RX2(1) 1 I ST Asynchronous serial receive data input (EUSART2 module). DT2(1) 1 O DIG Synchronous serial data output (EUSART2 module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART2 module). User must configure as an input. RG3/CCP4/ RG3(1) 0 O DIG LATG<3> data output. P3D(1) 1 I ST PORTG<3> data input. CCP4(1) 0 O DIG CCP4 compare output and PWM output; takes priority over port data. 1 I ST CCP4 capture input. P3D(1) 0 O DIG ECCP3 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RG4/CCP5/ RG4 0 O DIG LATG<4> data output. P1D 1 I ST PORTG<4> data input. CCP5 0 O DIG CCP5 compare output and PWM output; takes priority over port data. 1 I ST CCP5 capture input. P1D 0 O DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RG5(2) RG5(2) 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. RG6(2) RG6(2) 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. RG7(2) RG7(2) 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Implemented on 80-pin and 100-pin devices only. 2: Implemented on 100-pin devices only. TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTG RG7(1) RG6(1) RG5(1) RG4 RG3(2) RG2(2) RG1(2) RG0(2) 72 LATG LATG7(1) LATG6(1) LATG5(1) LATG4 LATG3(2) LATG2(2) LATG1(2) LATG0(2) 72 TRISG TRISG7(1) TRISG6(1) TRISG5(1) TRISG4 TRISG3(2) TRISG2(2) TRISG1(2) TRISG0(2) 71 Note 1: Implemented on 100-pin devices only. 2: Implemented on 80-pin and 100-pin devices only.  2011 Microchip Technology Inc. DS39762F-page 163

PIC18F97J60 FAMILY 11.9 PORTH, LATH and When the external memory interface is enabled, four of TRISH Registers the PORTH pins function as the high-order address lines for the interface. The address output from the Note: PORTH is available only on 80-pin and interface takes priority over other digital I/O. The 100-pin devices. corresponding TRISH bits are also overridden. PORTH pins, RH4 through RH7, are multiplexed with PORTH is an 8-bit wide, bidirectional I/O port; it is fully analog converter inputs. The operation of these pins as implemented on 80-pin and 100-pin devices. The analog inputs is selected by clearing or setting the corresponding Data Direction register is TRISH. Set- PCFG<3:0> control bits in the ADCON1 register. ting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output PORTH can also be configured as the alternate driver in a High-Impedance mode). Clearing a TRISH Enhanced PWM Output Channels B and C for the bit (= 0) will make the corresponding PORTH pin an ECCP1 and ECCP3 modules. This is done by clearing output (i.e., put the contents of the output latch on the the ECCPMX Configuration bit. selected pin). PORTH<3:0> pins are digital only and tolerate voltages up to 5.5V. EXAMPLE 11-8: INITIALIZING PORTH The Output Latch register (LATH) is also memory CLRF PORTH ; Initialize PORTH by mapped. Read-modify-write operations on the LATH ; clearing output register, read and write the latched output value for ; data latches PORTH. CLRF LATH ; Alternate method ; to clear output All pins on PORTH are implemented with Schmitt ; data latches Trigger input buffers. Each pin is individually MOVLW 0Fh ; Configure PORTH as configurable as an input or output. MOVWF ADCON1 ; digital I/O MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISH ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs ; RH7:RH6 as inputs DS39762F-page 164  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 11-17: PORTH FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RH0/A16 RH0 0 O DIG LATH<0> data output. 1 I ST PORTH<0> data input. A16(1) x O DIG External memory interface, Address Line 16. Takes priority over port data. RH1/A17 RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. A17(1) x O DIG External memory interface, Address Line 17. Takes priority over port data. RH2/A18 RH2 0 O DIG LATH<2> data output. 1 I ST PORTH<2> data input. A18(1) x O DIG External memory interface, Address Line 18. Takes priority over port data. RH3/A19 RH3 0 O DIG LATH<3> data output. 1 I ST PORTH<3> data input. A19(1) x O DIG External memory interface, Address Line 19. Takes priority over port data. RH4/AN12/P3C RH4 0 O DIG LATH<4> data output. 1 I ST PORTH<4> data input. AN12 I ANA A/D Input Channel 12. Default input configuration on POR; does not affect digital output. P3C(2) 0 O DIG ECCP3 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RH5/AN13/P3B RH5 0 O DIG LATH<5> data output. 1 I ST PORTH<5> data input. AN13 I ANA A/D Input Channel 13. Default input configuration on POR; does not affect digital output. P3B(2) 0 O DIG ECCP3 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RH6/AN14/P1C RH6 0 O DIG LATH<6> data output. 1 I ST PORTH<6> data input. AN14 I ANA A/D Input Channel 14. Default input configuration on POR; does not affect digital output. P1C(2) 0 O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RH7/AN15/P1B RH7 0 O DIG LATH<7> data output. 1 I ST PORTH<7> data input. AN15 I ANA A/D Input Channel 15. Default input configuration on POR; does not affect digital output. P1B(2) 0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Unimplemented on 80-pin devices. 2: Alternate assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is cleared (80-pin and 100-pin devices only). Default assignments are PORTE<6:3>. TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTH RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 72 LATH LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 71 TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 71  2011 Microchip Technology Inc. DS39762F-page 165

PIC18F97J60 FAMILY 11.10 PORTJ, TRISJ and When the external memory interface is enabled, all of LATJ Registers the PORTJ pins function as control outputs for the interface. This occurs automatically when the interface Note: PORTJ is available only on 80-pin and is enabled by clearing the EBDIS control bit 100-pin devices. (MEMCON<7>). The TRISJ bits are also overridden. Each of the PORTJ pins has a weak internal pull-up. A PORTJ is implemented as a bidirectional port in two single control bit can turn on all the pull-ups. This is different ways: performed by setting bit, RJPU (PORTA<7>). The • 80-pin devices: 2 bits wide (RJ<5:4>) weak pull-up is automatically turned off when the port • 100-pin devices: 8 bits wide (RJ<7:0>) pin is configured as an output. The pull-ups are disabled on all device Resets. The corresponding Data Direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding EXAMPLE 11-9: INITIALIZING PORTJ PORTJ pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISJ CLRF PORTJ ; Initialize PORTG by bit (= 0) will make the corresponding PORTJ pin an out- ; clearing output put (i.e., put the contents of the output latch on the ; data latches selected pin). All pins on PORTJ are digital only and CLRF LATJ ; Alternate method tolerate voltages up to 5.5V. ; to clear output ; data latches The Output Latch register (LATJ) is also memory MOVLW 0CFh ; Value used to mapped. Read-modify-write operations on the LATJ ; initialize data register read and write the latched output value for ; direction PORTJ. MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output All pins on PORTJ are implemented with Schmitt ; RJ7:RJ6 as inputs Trigger input buffers. Each pin is individually configurable as an input or output. Note: These pins are configured as digital inputs on any device Reset. DS39762F-page 166  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 11-19: PORTJ FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RJ0/ALE(1) RJ0(1) 0 O DIG LATJ<0> data output. 1 I ST PORTJ<0> data input; weak pull-up when RJPU bit is set. ALE(1) x O DIG External memory interface address latch enable control output; takes priority over digital I/O. RJ1/OE(1) RJ1(1) 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input; weak pull-up when RJPU bit is set. OE(1) x O DIG External memory interface output enable control output; takes priority over digital I/O. RJ2/WRL(1) RJ2(1) 0 O DIG LATJ<2> data output. 1 I ST PORTJ<2> data input; weak pull-up when RJPU bit is set. WRL(1) x O DIG External memory bus write low byte control; takes priority over digital I/O. RJ3/WRH(1) RJ3(1) 0 O DIG LATJ<3> data output. 1 I ST PORTJ<3> data input; weak pull-up when RJPU bit is set. WRH(1) x O DIG External memory interface write high byte control output; takes priority over digital I/O. RJ4/BA0 RJ4 0 O DIG LATJ<4> data output. 1 I ST PORTJ<4> data input; weak pull-up when RJPU bit is set. BA0(2) x O DIG External Memory Interface Byte Address 0 control output; takes priority over digital I/O. RJ5/CE RJ5 0 O DIG LATJ<5> data output. 1 I ST PORTJ<5> data input; weak pull-up when RJPU bit is set. CE(2) x O DIG External memory interface chip enable control output; takes priority over digital I/O. RJ6/LB(1) RJ6(1) 0 O DIG LATJ<6> data output. 1 I ST PORTJ<6> data input; weak pull-up when RJPU bit is set. LB(1) x O DIG External memory interface lower byte enable control output; takes priority over digital I/O. RJ7/UB(1) RJ7(1) 0 O DIG LATJ<7> data output. 1 I ST PORTJ<7> data input; weak pull-up when RJPU bit is set. UB(1) x O DIG External memory interface upper byte enable control output; takes priority over digital I/O. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Implemented on 100-pin devices only. 2: EMB functions are implemented on 100-pin devices only. TABLE 11-20: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTJ RJ7(1) RJ6(1) RJ5 RJ4 RJ3(1) RJ2(1) RJ1(1) RJ0(1) 72 LATJ LATJ7(1) LATJ6(1) LATJ5 LATJ4 LATJ3(1) LATJ2(1) LATJ1(1) LATJ0(1) 71 TRISJ TRISJ7(1) TRISJ6(1) TRISJ5 TRISJ4 TRISJ3(1) TRISJ2(1) TRISJ1(1) TRISJ0(1) 71 PORTA RJPU — RA5 RA4 RA3 RA2 RA1 RA0 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTJ. Note 1: Implemented on 100-pin devices only.  2011 Microchip Technology Inc. DS39762F-page 167

PIC18F97J60 FAMILY 11.11 Parallel Slave Port (PSP) FIGURE 11-2: PORTD AND PORTE BLOCK DIAGRAM Note: The Parallel Slave Port is only implemented (PARALLEL SLAVE PORT) on 100-pin devices. PORTD can also function as an 8-bit wide, Parallel Slave Port, or microprocessor port, when control bit, Data Bus D Q PSPMODE (PSPCON<4>), is set. It is asynchronously RDx readable and writable by the external world through the WR LATD Pin CK RD control input pin, RE0/AD8/RD/P2D and WR or PORTD control input pin, RE1/AD9//WR/P2C. Data Latch TTL Note: The Parallel Slave Port is available only in Q D Microcontroller mode. RD PORTD ENEN The PSP can directly interface to an 8-bit micro- TRIS Latch processor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit, PSPMODE, enables port pin, RE0/AD8/RD/P2D, to RD LATD be the RD input, RE1/AD9//WR/P2C to be the WR input and RE2/AD10//CS/P2B to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) One bit of PORTD must be configured as inputs (set). Set Interrupt Flag A write to the PSP occurs when both the CS and WR PSPIF (PIR1<7>) lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set when the write ends. A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit is set. If the user writes new data Read TTL RD to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. Chip Select TTL CS When either the CS or RD lines is detected high, the PORTD pins return to the input state and the PSPIF bit Write TTL WR is set. User applications should wait for PSPIF to be set before servicing the PSP. When this happens, the IBF and OBF bits can be polled and the appropriate action taken. The timing for the control signals in Write and Read modes is shown in Figure11-3 and Figure11-4, respectively. DS39762F-page 168  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 11-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF  2011 Microchip Technology Inc. DS39762F-page 169

PIC18F97J60 FAMILY FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 72 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 72 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 71 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 72 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 72 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 71 PSPCON IBF OBF IBOV PSPMODE — — — — 71 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. DS39762F-page 170  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 12.0 TIMER0 MODULE The T0CON register (Register12-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or A simplified block diagram of the Timer0 module in 8-bit counter in both 8-bit or 16-bit modes mode is shown in Figure12-1. Figure12-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated, 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt on overflow REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned; Timer0 clock input bypasses prescaler 0 = Timer0 prescaler is assigned; Timer0 clock input comes from prescaler output bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value  2011 Microchip Technology Inc. DS39762F-page 171

PIC18F97J60 FAMILY 12.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter; the timer/counter. mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on 12.2 Timer0 Reads and Writes in every clock by default unless a different prescaler value 16-Bit Mode is selected (see Section12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited TMR0H is not the actual high byte of Timer0 in 16-bit for the following two instruction cycles. The user can mode. It is actually a buffered version of the real high work around this by writing an adjusted value to the byte of Timer0 which is not directly readable nor writ- TMR0 register. able (refer to Figure12-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of The Counter mode is selected by setting the T0CS bit TMR0L. This provides the ability to read all 16 bits of (= 1). In this mode, Timer0 increments either on every Timer0 without having to verify that the read of the high rising or falling edge of pin, RA4/T0CKI. The increment- and low byte was valid, due to a rollover between ing edge is determined by the Timer0 Source Edge successive reads of the high and low byte. Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input Similarly, a write to the high byte of Timer0 must also are discussed below. take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a An external clock source can be used to drive Timer0; write occurs to TMR0L. This allows all 16 bits of Timer0 however, it must meet certain requirements to ensure to be updated at once. that the external clock can be synchronized with the FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) T0CS 3 8 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L HiTgMh RB0yte TMR0IF T0CKI pin ProPgrreasmcamlearble 0 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39762F-page 172  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 12.3 Prescaler 12.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable The prescaler assignment is fully under software or writable. Its value is set by the PSA and T0PS<2:0> control and can be changed “on-the-fly” during program bits (T0CON<3:0>) which determine the prescaler execution. assignment and prescale ratio. 12.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0 from 1:2 through 1:256, in power-of-2 increments, are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before TMR0, BSF TMR0, etc.) clear the prescaler count. re-enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: TMR0L Timer0 Register Low Byte 70 TMR0H Timer0 Register High Byte 70 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 69 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 70 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 71 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.  2011 Microchip Technology Inc. DS39762F-page 173

PIC18F97J60 FAMILY NOTES: DS39762F-page 174  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 13.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is shown in Figure13-1. A block diagram of the module’s The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure13-2. features: The module incorporates its own low-power oscillator • Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1 counter oscillator can also be used as a low-power clock source • Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation. and TMR1L) Timer1 can also be used to provide Real-Time Clock • Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal device clock or Timer1 oscillator internal options addition of external components and code overhead. • Interrupt on overflow Timer1 is controlled through the T1CON Control • Reset on ECCP Special Event Trigger register (Register13-1). It also contains the Timer1 • Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 =Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from RC0/T1OSO/T13CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1  2011 Microchip Technology Inc. DS39762F-page 175

PIC18F97J60 FAMILY 13.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled. • Timer When Timer1 is enabled, the RC1/T1OSI and • Synchronous Counter RC0/T1OSO/T13CKI pins become inputs. This means • Asynchronous Counter the values of TRISC<1:0> are ignored and the pins are read as ‘0’. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input On/Off 1 T1OSO/T13CKI 1 Prescaler Synchronize 0 FOSC/4 1, 2, 4, 8 Detect Internal 0 T1OSI Clock 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Set Clear TMR1 TMR1L HTigMh RB1yte TMR1IF (ECCPx Special Event Trigger) on Overflow Note 1:When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize 0 FOSC/4 1, 2, 4, 8 Detect Internal 0 T1OSI Clock 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 T1CKPS<1:0> On/Off T1SYNC TMR1ON Set Clear TMR1 TMR1L HiTgMh RB1yte TMR1IF (ECCPx Special Event Trigger) on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39762F-page 176  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 13.2 Timer1 16-Bit Read/Write Mode TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER1 Timer1 can be configured for 16-bit reads and writes OSCILLATOR(2,3,4) (see Figure13-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped Oscillator Freq. C1 C2 to a buffer register for the high byte of Timer1. A read Type from TMR1L will load the contents of the high byte of LP 32kHz 27pF(1) 27pF(1) Timer1 into the Timer1 High Byte Buffer register. This provides the user with the ability to accurately read all Note1: Microchip suggests these values as a 16 bits of Timer1 without having to determine whether starting point in validating the oscillator a read of the high byte, followed by a read of the low circuit. byte, has become invalid due to a rollover between 2: Higher capacitance increases the stabil- reads. ity of the oscillator but also increases the A write to the high byte of Timer1 must also take place start-up time. through the TMR1H Buffer register. The Timer1 high 3: Since each resonator/crystal has its own byte is updated with the contents of TMR1H when a characteristics, the user should consult write occurs to TMR1L. This allows a user to write all the resonator/crystal manufacturer for 16 bits to both the high and low bytes of Timer1 at once. appropriate values of external The high byte of Timer1 is not directly readable or components. writable in this mode. All reads and writes must take 4: Capacitor values are for design guidance place through the Timer1 High Byte Buffer register. only. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. 13.3.1 USING TIMER1 AS A 13.3 Timer1 Oscillator CLOCK SOURCE The Timer1 oscillator is also available as a clock source An on-chip crystal oscillator circuit is incorporated in power-managed modes. By setting the Clock Select between pins, T1OSI (input) and T1OSO (amplifier bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device output). It is enabled by setting the Timer1 Oscillator switches to SEC_RUN mode. Both the CPU and Enable bit, T1OSCEN (T1CON<3>). The oscillator is a peripherals are clocked from the Timer1 oscillator. If the low-power circuit rated for 32kHz crystals. It will IDLEN bit (OSCCON<7>) is cleared and a SLEEP continue to run during all power-managed modes. The instruction is executed, the device enters SEC_IDLE circuit for a typical LP oscillator is shown in Figure13-3. mode. Additional details are available in Section4.0 Table13-1 shows the capacitor selection for the Timer1 “Power-Managed Modes”. oscillator. Whenever the Timer1 oscillator is providing the clock The user must provide a software time delay to ensure source, the Timer1 system clock status flag, T1RUN proper start-up of the Timer1 oscillator. (T1CON<6>), is set. This can be used to determine the controller’s current clocking mode. It can also indicate FIGURE 13-3: EXTERNAL the clock source being currently used by the Fail-Safe COMPONENTS FOR THE Clock Monitor. If the Clock Monitor is enabled and the TIMER1 OSCILLATOR Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is being C1 PIC18F97J60 provided by the Timer1 oscillator or another source. 27 pF T1OSI 13.3.2 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS XTAL 32.768 kHz The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the T1OSO oscillator, it may also be sensitive to rapidly changing C2 signals in close proximity. 27 pF The oscillator circuit, shown in Figure13-3, should be Note: See the Notes with Table13-1 for additional located as close as possible to the microcontroller. information about capacitor selection. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD.  2011 Microchip Technology Inc. DS39762F-page 177

PIC18F97J60 FAMILY If a high-speed circuit must be located near the oscilla- 13.6 Using Timer1 as a Real-Time Clock tor (such as the ECCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a Adding an external LP oscillator to Timer1 (such as the grounded guard ring around the oscillator circuit, as one described in Section13.3 “Timer1 Oscillator”) shown in Figure13-4, may be helpful when used on a gives users the option to include RTC functionality to single-sided PCB or in addition to a ground plane. their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time FIGURE 13-4: OSCILLATOR CIRCUIT base and several lines of application code to calculate WITH GROUNDED the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can GUARD RING completely eliminate the need for a separate RTC VDD device and battery backup. VSS The application code routine, RTCisr, shown in Example13-1, demonstrates a simple method to OSC1 increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 OSC2 register pair to overflow, triggers the interrupt and calls the routine, which increments the seconds counter by one. Additional counters for minutes and hours are incremented as the previous counter overflows. RC0 Since the register pair is 16 bits wide, counting up to RC1 overflow the register directly from a 32.768kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to pre- RC2 load it. The simplest method is to set the MSb of Note: Not drawn to scale. TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may 13.4 Timer1 Interrupt introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in The TMR1 register pair (TMR1H:TMR1L) increments Asynchronous mode and the Timer1 overflow interrupt from 0000h to FFFFh and rolls over to 0000h. The must be enabled (PIE1<0> = 1), as shown in the Timer1 interrupt, if enabled, is generated on overflow routine, RTCinit. The Timer1 oscillator must also be which is latched in interrupt flag bit, TMR1IF enabled and running at all times. (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, 13.7 Considerations in Asynchronous TMR1IE (PIE1<0>). Counter Mode 13.5 Resetting Timer1 Using the Following a Timer1 interrupt and an update to the ECCPx Special Event Trigger TMR1 registers, the Timer1 module uses a falling edge on its clock source to trigger the next register update on If ECCP1 or ECCP2 is configured to use Timer1 and to the rising edge. If the update is completed after the generate a Special Event Trigger in Compare mode clock input has fallen, the next rising edge will not be (CCPxM<3:0>=1011), this signal will reset Timer3. counted. The trigger from ECCP2 will also start an A/D conver- sion if the A/D module is enabled (see Section18.2.1 If the application can reliably update TMR1 before the “Special Event Trigger” for more information). timer input goes low, no additional action is needed. Otherwise, an adjusted update can be performed The module must be configured as either a timer or a following a later Timer1 increment. This can be done by synchronous counter to take advantage of this feature. monitoring TMR1L within the interrupt routine until it When used this way, the CCPRxH:CCPRxL register increments, and then updating the TMR1H:TMR1L reg- pair effectively becomes a period register for Timer1. ister pair while the clock is low, or one-half of the period If Timer1 is running in Asynchronous Counter mode, of the clock source. Assuming that Timer1 is being this Reset operation may not work. used as a Real-Time Clock, the clock source is a 32.768 kHz crystal oscillator. In this case, one-half In the event that a write to Timer1 coincides with a Special period of the clock is 15.25s. Event Trigger, the write operation will take precedence. The Real-Time Clock application code in Example13-1 Note: The Special Event Triggers from the shows a typical ISR for Timer1, as well as the optional ECCPx module will not set the TMR1IF code required if the update cannot be done reliably interrupt flag bit (PIR1<0>). within the required interval. DS39762F-page 178  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE; Enable Timer1 interrupt RETURN RTCisr ; Insert the next 4 lines of code when TMR1 ; can not be reliably updated before clock pulse goes low BTFSC TMR1L,0 ; wait for TMR1L to become clear BRA $-2 ; (may already be clear) BTFSS TMR1L,0 ; wait for TMR1L to become set BRA $-2 ; TMR1 has just incremented ; If TMR1 update can be completed before clock pulse goes low ; Start ISR here BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done CLRF hours ; Reset hours RETURN ; Done TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 TMR1L Timer1 Register Low Byte 70 TMR1H Timer1 Register High Byte 70 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 70 Legend: Shaded cells are not used by the Timer1 module.  2011 Microchip Technology Inc. DS39762F-page 179

PIC18F97J60 FAMILY 14.0 TIMER2 MODULE 14.1 Timer2 Operation The Timer2 timer module incorporates the following In normal operation, TMR2 is incremented from 00h on features: each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and • 8-Bit Timer and Period registers (TMR2 and PR2, divide-by-16 prescale options. These options are respectively) selected by the prescaler control bits, T2CKPS<1:0> • Readable and writable (both registers) (T2CON<1:0>). The value of TMR2 is compared to that • Software programmable prescaler (1:1, 1:4 and of the Period register, PR2, on each clock cycle. When 1:16) the two values match, the comparator generates a • Software programmable postscaler (1:1 through match signal as the timer output. This signal also resets 1:16) the value of TMR2 to 00h on the next cycle and drives • Interrupt on TMR2 to PR2 match the output counter/postscaler (see Section14.2 “Timer2 Interrupt”). • Optional use as the shift clock for the MSSPx modules The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any This module is controlled through the T2CON register device Reset, while the PR2 register initializes at FFh. (Register14-1) which enables or disables the timer and Both the prescaler and postscaler counters are cleared configures the prescaler and postscaler. Timer2 can be on the following events: shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. • A write to the TMR2 register A simplified block diagram of the module is shown in • A write to the T2CON register Figure14-1. • Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 DS39762F-page 180  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 Output Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2 to PR2 match) pro- the CCP modules, where it is used as a time base for vides the input for the 4-bit output counter/postscaler. operations in PWM mode. This counter generates the TMR2 match interrupt flag Timer2 can be optionally used as the shift clock source which is latched in TMR2IF (PIR1<1>). The interrupt is for the MSSPx modules operating in SPI mode. enabled by setting the TMR2 Match Interrupt Enable Additional information is provided in Section20.0 bit, TMR2IE (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set TMR2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSPx) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 TMR2 Timer2 Register 70 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 70 PR2 Timer2 Period Register 70 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.  2011 Microchip Technology Inc. DS39762F-page 181

PIC18F97J60 FAMILY NOTES: DS39762F-page 182  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 15.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure15-1. A block diagram of the module’s The Timer3 timer/counter module incorporates these operation in Read/Write mode is shown in Figure15-2. features: The Timer3 module is controlled through the T3CON • Software selectable operation as a 16-bit timer or register (Register15-1). It also selects the clock source counter options for the CCPx and ECCPx modules; see • Readable and writable 8-bit registers (TMR3H Section17.1.1 “CCPx/ECCPx Modules and Timer and TMR3L) Resources” for more information. • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt on overflow • Module Reset on CCPx/ECCPx Special Event Trigger REGISTER 15-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3CCP<2:1>: Timer3 and Timer1 to CCPx/ECCPx Enable bits 11 = Timer3 and Timer4 are the clock sources for all CCPx/ECCPx modules 10 = Timer3 and Timer4 are the clock sources for ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 and ECCP2 01 = Timer3 and Timer4 are the clock sources for ECCP2, ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 00 = Timer1 and Timer2 are the clock sources for all CCPx/ECCPx modules bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Select bit (not usable if the device clock comes from Timer1/Timer3) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3  2011 Microchip Technology Inc. DS39762F-page 183

PIC18F97J60 FAMILY 15.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared Timer3 can operate in one of three modes: (= 0), Timer3 increments on every internal instruction • Timer cycle (FOSC/4). When the bit is set, Timer3 increments • Synchronous Counter on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. • Asynchronous Counter As with Timer1, the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. FIGURE 15-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize 0 1, 2, 4, 8 Detect FOSC/4 Internal 0 T1OSI Clock 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 On/Off T3CKPS<1:0> T3SYNC TMR3ON ECCEPCxC SPexle Scpt efrcoimal ET3veCnOt NTr<ig6g,3e>r Clear TMR3 TMR3L HiTgMh RB3yte STonMe tOR v3eIFrflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 15-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize 0 1, 2, 4, 8 Detect FOSC/4 Internal 0 T1OSI Clock 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 T3CKPS<1:0> On/Off T3SYNC TMR3ON ECCPx Special Event Trigger Clear TMR3 TMR3 Set ECCPx Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39762F-page 184  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes The TMR3 register pair (TMR3H:TMR3L) increments (see Figure15-2). When the RD16 control bit from 0000h to FFFFh, and overflows to 0000h. The (T3CON<7>) is set, the address for TMR3H is mapped Timer3 interrupt, if enabled, is generated on overflow to a buffer register for the high byte of Timer3. A read and is latched in interrupt flag bit, TMR3IF (PIR2<1>). from TMR3L will load the contents of the high byte of This interrupt can be enabled or disabled by setting or Timer3 into the Timer3 High Byte Buffer register. This clearing the Timer3 Interrupt Enable bit, TMR3IE provides the user with the ability to accurately read all (PIE2<1>). 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low 15.5 Resetting Timer3 Using the byte, has become invalid due to a rollover between ECCPx Special Event Trigger reads. If ECCP1 or ECCP2 is configured to use Timer3 and to A write to the high byte of Timer3 must also take place generate a Special Event Trigger in Compare mode through the TMR3H Buffer register. The Timer3 high (CCPxM<3:0>=1011), this signal will reset Timer3. byte is updated with the contents of TMR3H when a The trigger from ECCP2 will also start an A/D conver- write occurs to TMR3L. This allows a user to write all sion if the A/D module is enabled (see Section18.2.1 16 bits to both the high and low bytes of Timer3 at once. “Special Event Trigger” for more information). The high byte of Timer3 is not directly readable or The module must be configured as either a timer or writable in this mode. All reads and writes must take synchronous counter to take advantage of this feature. place through the Timer3 High Byte Buffer register. When used this way, the CCPRxH:CCPRxL register Writes to TMR3H do not clear the Timer3 prescaler. pair effectively becomes a Period register for Timer3. The prescaler is only cleared on writes to TMR3L. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. 15.3 Using the Timer1 Oscillator as the Timer3 Clock Source In the event that a write to Timer3 coincides with a Special Event Trigger from an ECCPx module, the The Timer1 internal oscillator may be used as the clock write will take precedence. source for Timer3. The Timer1 oscillator is enabled by Note: The Special Event Triggers from the setting the T1OSCEN (T1CON<3>) bit. To use it as the ECCPx module will not set the TMR3IF Timer3 clock source, the TMR3CS bit must also be set. interrupt flag bit (PIR2<1>). As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section13.0 “Timer1 Module”. TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR2 OSCFIF CMIF ETHIF r BCL1IF — TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE — TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP — TMR3IP CCP2IP 71 TMR3L Timer3 Register Low Byte 70 TMR3H Timer3 Register High Byte 70 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 70 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 71 Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used by the Timer3 module.  2011 Microchip Technology Inc. DS39762F-page 185

PIC18F97J60 FAMILY NOTES: DS39762F-page 186  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 16.0 TIMER4 MODULE 16.1 Timer4 Operation The Timer4 module has the following features: Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is • 8-Bit Timer register (TMR4) readable and writable, and is cleared on any device • 8-Bit Period register (PR4) Reset. The input clock (FOSC/4) has a prescale option • Readable and writable (both registers) of 1:1, 1:4 or 1:16, selected by control bits, • Software programmable prescaler (1:1, 1:4, 1:16) T4CKPS<1:0> (T4CON<1:0>). The match output of • Software programmable postscaler (1:1 to 1:16) TMR4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR4 • Interrupt on TMR4 match of PR4 interrupt, latched in flag bit, TMR4IF (PIR3<3>). Timer4 has a control register, shown in Register16-1. The prescaler and postscaler counters are cleared Timer4 can be shut off by clearing control bit, TMR4ON when any of the following occurs: (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 is also • A write to the TMR4 register controlled by this register. Figure16-1 is a simplified • A write to the T4CON register block diagram of the Timer4 module. • Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR4 is not cleared when T4CON is written. REGISTER 16-1: T4CON: TIMER4 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T4OUTPS<3:0>: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off bit 1-0 T4CKPS<1:0>: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16  2011 Microchip Technology Inc. DS39762F-page 187

PIC18F97J60 FAMILY 16.2 Timer4 Interrupt 16.3 Output of TMR4 The Timer4 module has an 8-Bit Period register, PR4, The output of TMR4 (before the postscaler) is used which is both readable and writable. Timer4 increments only as a PWM time base for the CCPx/ECCPx mod- from 00h until it matches PR4 and then resets to 00h on ules. It is not used as a baud rate clock for the MSSPx the next increment cycle. The PR4 register is initialized modules as is the Timer2 output. to FFh upon Reset. FIGURE 16-1: TIMER4 BLOCK DIAGRAM 4 1:1 to 1:16 T4OUTPS<3:0> Set TMR4IF Postscaler 2 T4CKPS<1:0> TMR4 Output (to PWM) TMR4/PR4 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR4 Comparator PR4 Prescaler 8 8 8 Internal Data Bus TABLE 16-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 TMR4 Timer4 Register 72 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 72 PR4 Timer4 Period Register 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module. DS39762F-page 188  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 17.0 CAPTURE/COMPARE/PWM register. For the sake of clarity, all CCPx module oper- (CCP) MODULES ation in the following sections is described with respect to CCP4, but is equally applicable to CCP5. Members of the PIC18F97J60 family of devices all have Capture and Compare operations described in this chap- a total of five CCP (Capture/Compare/PWM) modules. ter apply to all standard and Enhanced CCPx modules. Two of these (CCP4 and CCP5) implement standard The operations of PWM mode, described in Section17.4 Capture, Compare and Pulse-Width Modulation (PWM) “PWM Mode”, apply to CCP4 and CCP5 only. modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ECCP3) implement Note: Throughout this section and Section18.0 standard Capture and Compare modes, as well as “Enhanced Capture/Compare/PWM (ECCP) Enhanced PWM modes. These are discussed in Modules”, references to register and bit Section18.0 “Enhanced Capture/Compare/PWM names that may be associated with a specific (ECCP) Modules”. CCP module are referred to generically by the use of ‘x’ or ‘y’ in place of the specific module Each CCPx/ECCPx module contains a 16-bit register number. Thus, “CCPxCON” might refer to the which can operate as a 16-Bit Capture register, a 16-Bit control register for ECCP1, ECCP2, ECCP3, Compare register or a PWM Master/Slave Duty Cycle CCP4 or CCP5. REGISTER 17-1: CCPxCON: CCPx CONTROL REGISTER (CCP4 AND CCP5) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: CCPx Module PWM Duty Cycle Bit 1 and Bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCxB<9:2>) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Module Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode; toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode; every falling edge 0101 = Capture mode; every rising edge 0110 = Capture mode; every 4th rising edge 0111 = Capture mode; every 16th rising edge 1000 = Compare mode; initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode; initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Reserved 11xx = PWM mode  2011 Microchip Technology Inc. DS39762F-page 189

PIC18F97J60 FAMILY 17.1 CCPx Module Configuration The assignment of a particular timer to a module is determined by the timer to CCPx enable bits in the Each Capture/Compare/PWM module is associated T3CON register (Register15-1, page183). Depending with a control register (generically, CCPxCON) and a on the configuration selected, up to four timers may be data register (CCPRx). The data register, in turn, is active at once, with modules in the same configuration comprised of two 8-bit registers: CCPRxL (low byte) (Capture/Compare or PWM) sharing timer resources. and CCPRxH (high byte). All registers are both The possible configurations are shown in Figure17-1. readable and writable. 17.1.2 ECCP2 PIN ASSIGNMENT 17.1.1 CCPx/ECCPx MODULES AND The pin assignment for ECCP2 (Capture input, TIMER RESOURCES Compare and PWM output) can change based on The CCPx/ECCPx modules utilize Timers 1, 2, 3 or 4, device configuration. The CCP2MX Configuration bit depending on the mode selected. Timer1 and Timer3 determines which pin ECCP2 is multiplexed to. By are available to modules in Capture or Compare default, it is assigned to RC1 (CCP2MX = 1). If the modes, while Timer2 and Timer4 are available for Configuration bit is cleared, ECCP2 is multiplexed with modules in PWM mode. RE7 on 80-pin and 100-pin devices in Microcontroller mode and RB3 on 100-pin devices in Extended TABLE 17-1: CCPx/ECCPx MODE – TIMER Microcontroller mode. RESOURCE Changing the pin assignment of ECCP2 does not auto- CCPx/ECCPx Mode Timer Resource matically change any requirements for configuring the port pin. Users must always verify that the appropriate Capture Timer1 or Timer3 TRIS register is configured correctly for ECCP2 Compare Timer1 or Timer3 operation, regardless of where it is located. PWM Timer2 or Timer4 FIGURE 17-1: CCPx/ECCPx AND TIMER INTERCONNECT CONFIGURATIONS T3CCP<2:1> = 00 T3CCP<2:1> = 01 T3CCP<2:1> = 10 T3CCP<2:1> = 11 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 ECCP1 ECCP1 ECCP1 ECCP1 ECCP2 ECCP2 ECCP2 ECCP2 ECCP3 ECCP3 ECCP3 ECCP3 CCP4 CCP4 CCP4 CCP4 CCP5 CCP5 CCP5 CCP5 TMR2 TMR4 TMR2 TMR4 TMR2 TMR4 TMR2 TMR4 Timer1 is used for all Capture Timer1 and Timer2 are used Timer1 and Timer2 are used Timer3 is used for all Capture and Compare operations for for Capture and Compare or for Capture and Compare or and Compare operations for all CCPx modules. Timer2 is PWM operations for ECCP1 PWM operations for ECCP1 all CCPx modules. Timer4 is used for PWM operations for only (depending on selected and ECCP2 only (depending used for PWM operations for all CCPx modules. Modules mode). on the mode selected for each all CCPx modules. Modules may share either timer module). Both modules may may share either timer All other modules use either resource as a common time use a timer as a common time resource as a common time Timer3 or Timer4. Modules base. may share either timer base if they are both in base. Capture/Compare or PWM Timer3 and Timer4 are not resource as a common time Timer1 and Timer2 are not modes. available. base if they are in available. Capture/Compare or PWM The other modules use either modes. Timer3 or Timer4. Modules may share either timer resource as a common time base if they are in Capture/Compare or PWM modes. DS39762F-page 190  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 17.2 Capture Mode 17.2.3 SOFTWARE INTERRUPT In Capture mode, the CCPRxH:CCPRxL register pair When the Capture mode is changed, a false capture captures the 16-bit value of the TMR1 or TMR3 interrupt may be generated. The user should keep the registers when an event occurs on the corresponding CCPxIE interrupt enable bit clear to avoid false CCPx pin. An event is defined as one of the following: interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. • Every falling edge • Every rising edge 17.2.4 CCPx PRESCALER • Every 4th rising edge There are four prescaler settings in Capture mode. • Every 16th rising edge They are specified as part of the operating mode The event is selected by the mode select bits, selected by the mode select bits (CCPxM<3:0>). Whenever the CCPx module is turned off or Capture CCPxM<3:0> (CCPxCON<3:0>). When a capture is mode is disabled, the prescaler counter is cleared. This made, the interrupt request flag bit, CCPxIF, is set; it means that any Reset will clear the prescaler counter. must be cleared in software. If another capture occurs before the value in register, CCPRx, is read, the old Switching from one capture prescaler to another may captured value is overwritten by the new captured value. generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from 17.2.1 CCPx PIN CONFIGURATION a non-zero prescaler. Example17-1 shows the In Capture mode, the appropriate CCPx pin should be recommended method for switching between capture configured as an input by setting the corresponding prescalers. This example also clears the prescaler TRIS direction bit. counter and will not generate the “false” interrupt. Note: If RG4/CCP5/P1D is configured as an EXAMPLE 17-1: CHANGING BETWEEN output, a write to the port can cause a CAPTURE PRESCALERS capture condition. (CCP5 SHOWN) 17.2.2 TIMER1/TIMER3 MODE SELECTION CLRF CCP5CON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load WREG with the The timers that are to be used with the capture feature ; new prescaler mode (Timer1 and/or Timer3) must be running in Timer mode or ; value and CCP ON Synchronized Counter mode. In Asynchronous Counter MOVWF CCP5CON ; Load CCP5CON with mode, the capture operation will not work. The timer to be ; this value used with each CCPx module is selected in the T3CON register (see Section17.1.1 “CCPx/ECCPx Modules and Timer Resources”). FIGURE 17-2: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP4IF T3CCP2 TMR3 Enable CCP4 Pin Prescaler and CCPR4H CCPR4L  1, 4, 16 Edge Detect TMR1 T3CCP2 Enable 4 TMR1H TMR1L CCP4CON<3:0> Set CCP5IF 4 Q1:Q4 4 CCP5CON<3:0> T3CCP1 TMR3H TMR3L T3CCP2 TMR3 Enable CCP5 Pin Prescaler and CCPR5H CCPR5L  1, 4, 16 Edge Detect TMR1 Enable T3CCP2 T3CCP1 TMR1H TMR1L  2011 Microchip Technology Inc. DS39762F-page 191

PIC18F97J60 FAMILY 17.3 Compare Mode Note: Clearing the CCP5CON register will force the RG4 compare output latch (depend- In Compare mode, the 16-bit CCPRx register value is ing on device configuration) to the default constantly compared against either the TMR1 or TMR3 low level. This is not the PORTB or register pair value. When a match occurs, the CCPx PORTC I/O data latch. pin: • Can be driven high 17.3.2 TIMER1/TIMER3 MODE SELECTION • Can be driven low Timer1 and/or Timer3 must be running in Timer mode • Can be toggled (high-to-low or low-to-high) or Synchronized Counter mode if the CCPx module is • Remains unchanged (that is, reflects the state of using the compare feature. In Asynchronous Counter the I/O latch) mode, the compare operation may not work. The action on the pin is based on the value of the mode 17.3.3 SOFTWARE INTERRUPT MODE select bits (CCPxM<3:0>). At the same time, the interrupt flag bit, CCPxIF, is set. When the Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the corresponding CCPx pin is 17.3.1 CCPx PIN CONFIGURATION not affected. Only a CCPx interrupt is generated, if The user must configure the CCPx pin as an output by enabled, and the CCPxIE bit is set. clearing the appropriate TRIS bit. FIGURE 17-3: COMPARE MODE OPERATION BLOCK DIAGRAM Set CCP4IF CCPR4H CCPR4L CCP4 Pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCP4CON<3:0> TMR1H TMR1L 0 0 1 TMR3H TMR3L 1 T3CCP1 T3CCP2 Set CCP5IF CCP5 Pin Comparator Compare Output S Q Match Logic R TRIS 4 Output Enable CCPR5H CCPR5L CCP5CON<3:0> DS39762F-page 192  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 17-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 RCON IPEN — CM RI TO PD POR BOR 70 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR2 OSCFIF CMIF ETHIF r BCL1IF — TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE — TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP — TMR3IP CCP2IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 TRISG TRISG7 TRISG6 TRISG5 TRISG4 TRISG3(1) TRISG2 TRISG1 TRISG0 71 TMR1L Timer1 Register Low Byte 70 TMR1H Timer1 Register High Byte 70 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 70 TMR3H Timer3 Register High Byte 70 TMR3L Timer3 Register Low Byte 70 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 71 CCPR4L Capture/Compare/PWM Register 4 Low Byte 72 CCPR4H Capture/Compare/PWM Register 4 High Byte 72 CCPR5L Capture/Compare/PWM Register 5 Low Byte 73 CCPR5H Capture/Compare/PWM Register 5 High Byte 73 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 73 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 73 Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: This bit is only available in 80-pin and 100-pin devices; otherwise, it is unimplemented and reads as ‘0’.  2011 Microchip Technology Inc. DS39762F-page 193

PIC18F97J60 FAMILY 17.4 PWM Mode 17.4.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCPx pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since (PR4) register. The PWM period can be calculated the CCP4 and CCP5 pins are multiplexed with a using Equation17-1: PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. EQUATION 17-1: Note: Clearing the CCP4CON or CCP5CON PWM Period = [(PR2) + 1] • 4 • TOSC • register will force the RG3 or RG4 output (TMR2 Prescale Value) latch (depending on device configuration) to the default low level. This is not the PWM frequency is defined as 1/[PWM period]. PORTG I/O data latch. When TMR2 (TMR4) is equal to PR2 (PR4), the Figure17-4 shows a simplified block diagram of the following three events occur on the next increment CCPx module in PWM mode. cycle: For a step-by-step procedure on how to set up a CCPx • TMR2 (TMR4) is cleared module for PWM operation, see Section17.4.3 • The CCPx pin is set (exception: if PWM duty “Setup for PWM Operation”. cycle=0%, the CCPx pin will not be set) • The PWM duty cycle is latched from CCPRxL into FIGURE 17-4: SIMPLIFIED PWM BLOCK CCPRxH DIAGRAM Note: The Timer2 and Timer4 postscalers (see Duty Cycle Register Section14.0 “Timer2 Module” and 9 0 Section16.0 “Timer4 Module”) are not CCPRxL CCPxCON<5:4> used in the determination of the PWM frequency. The postscaler could be used Latch Duty Cycle to have a servo update rate at a different frequency than the PWM output. CCPRxH (1) 17.4.2 PWM DUTY CYCLE Comparator S Q R CCPx The PWM duty cycle is specified by writing to the Reset TMRx Pin CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available. The CCPRxL contains TMRx = PRx Match 2 LSbs Latched the eight MSbs and the CCPxCON<5:4> contains the Comparator From Q clocks two LSbs. This 10-bit value is represented by CCPRxL:CCPxCON<5:4>. Equation17-2 is used to PRx calculate the PWM duty cycle in time. TRIS Set CCPx pin Output Enable EQUATION 17-2: Note1: The two LSbs of the Duty Cycle register are held by a 2-bit latch that is part of the module’s hardware. It is physically separate from the CCPRx registers. PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) • TOSC • (TMRx Prescale Value) A PWM output (Figure17-5) has a time base (period) and a time that the output stays high (duty cycle). CCPRxL and CCPxCON<5:4> can be written to at any The frequency of the PWM is the inverse of the time, but the duty cycle value is not latched into period (1/period). CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. FIGURE 17-5: PWM OUTPUT Period Duty Cycle TMR2 (TMR4) = PR2 (PR4) TMR2 (TMR4) = Duty Cycle TMR2 (TMR4) = PR2 (TMR4) DS39762F-page 194  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY The CCPRxH register and a 2-bit internal latch are 17.4.3 SETUP FOR PWM OPERATION used to double-buffer the PWM duty cycle. This The following steps should be taken when configuring double-buffering is essential for glitchless PWM the CCPx module for PWM operation: operation. 1. Set the PWM period by writing to the PR2 (PR4) When the CCPRxH and 2-bit latch match TMR2 register. (TMR4), concatenated with an internal 2-bit Q clock or 2. Set the PWM duty cycle by writing to the 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is CCPRxL register and CCPxCON<5:4> bits. cleared. 3. Make the CCPx pin an output by clearing the The maximum PWM resolution (bits) for a given PWM appropriate TRIS bit. frequency is given by Equation17-3: 4. Set the TMR2 (TMR4) prescale value, then enable Timer2 (Timer4) by writing to T2CON EQUATION 17-3: (T4CON). (FOSC ) log 5. Configure the CCPx module for PWM operation. FPWM PWM Resolution (max) = bits log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58  2011 Microchip Technology Inc. DS39762F-page 195

PIC18F97J60 FAMILY TABLE 17-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 RCON IPEN — CM RI TO PD POR BOR 70 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 TRISG TRISG7 TRISG6 TRISG5 TRISG4 TRISG3(1) TRISG2 TRISG1 TRISG0 71 TMR2 Timer2 Register 70 PR2 Timer2 Period Register 70 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 70 TMR4 Timer4 Register 72 PR4 Timer4 Period Register 72 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 72 CCPR4L Capture/Compare/PWM Register 4 Low Byte 72 CCPR4H Capture/Compare/PWM Register 4 High Byte 72 CCPR5L Capture/Compare/PWM Register 5 Low Byte 73 CCPR5H Capture/Compare/PWM Register 5 High Byte 73 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 73 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 73 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4. Note 1: This bit is only available in 80-pin and 100-pin devices; otherwise, it is unimplemented and reads as ‘0’. DS39762F-page 196  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 18.0 ENHANCED The control register for the Enhanced CCPx module is CAPTURE/COMPARE/PWM shown in Register18-1. It differs from the CCP4CON/CCP5CON registers in that the two Most (ECCP) MODULES Significant bits are implemented to control PWM In the PIC18F97J60 family of devices, three of the CCP functionality. modules are implemented as standard CCP modules In addition to the expanded range of modes available with Enhanced PWM capabilities. These include the through the Enhanced CCPxCON register, the ECCPx provision for 2 or 4 output channels, user-selectable modules each have two additional registers associated polarity, dead-band control and automatic shutdown with Enhanced PWM operation and auto-shutdown and restart. The Enhanced features are discussed in features. They are: detail in Section18.4 “Enhanced PWM Mode”. • ECCPxDEL (Dead-Band Delay) Capture, Compare and single output PWM functions of the ECCPx modules are the same as described for the • ECCPxAS (Auto-Shutdown Configuration) standard CCPx modules.  2011 Microchip Technology Inc. DS39762F-page 197

PIC18F97J60 FAMILY REGISTER 18-1: CCPxCON: ENHANCED CCPx CONTROL REGISTER (ECCP1/ECCP2/ECCP3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as Capture/Compare input/output; PxB, PxC, PxD assigned as port pins If CCPxM<3:2> = 11: 00 = Single output: PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DCxB<1:0>: ECCPx Module PWM Duty Cycle Bit 1 and Bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the 2 LSbs of the 10-bit PWM duty cycle. The 8 MSbs of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: ECCPx Module Mode Select bits 0000 = Capture/Compare/PWM disabled (resets ECCPx module) 0001 = Reserved 0010 = Compare mode; toggle output on match 0011 = Capture mode 0100 = Capture mode; every falling edge 0101 = Capture mode; every rising edge 0110 = Capture mode; every 4th rising edge 0111 = Capture mode; every 16th rising edge 1000 = Compare mode; initialize ECCPx pin low; set output on compare match (set CCPxIF) 1001 = Compare mode; initialize ECCPx pin high; clear output on compare match (set CCPxIF) 1010 = Compare mode; generate software interrupt only, ECCPx pin reverts to I/O state) 1011 = Compare mode; trigger special event (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCPx trigger also starts A/D conversion if A/D module is enabled)(1) 1100 = PWM mode; PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode; PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode; PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode; PxA, PxC active-low; PxB, PxD active-low Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3. DS39762F-page 198  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 18.1 ECCPx Outputs and Configuration 18.1.2 ECCP2 OUTPUTS AND PROGRAM MEMORY MODES Each of the Enhanced CCPx modules may have up to four PWM outputs, depending on the selected For 100-pin devices, the Program Memory mode of the operating mode. These outputs, designated PxA device (Section6.1.3 “PIC18F9XJ60/9XJ65 Program through PxD, are multiplexed with various I/O pins. Memory Modes”) also impacts pin multiplexing for the Some ECCPx pin assignments are constant, while module. others change based on device configuration. For The ECCP2 input/output (ECCP2/P2A) can be multi- those pins that do change, the controlling bits are: plexed to one of three pins. The default assignment • CCP2MX Configuration bit (80-pin and 100-pin (CCP2MX Configuration bit is set) for all devices is devices only) RC1. Clearing CCP2MX reassigns ECCP2/P2A to RE7 in 80-pin and 100-pin devices. • ECCPMX Configuration bit (80-pin and 100-pin devices only) An additional option exists for 100-pin devices. When • Program memory operating mode set by the EMB these devices are operating in Microcontroller mode, Configuration bits (100-pin devices only) the multiplexing options described above still apply. In Extended Microcontroller mode, clearing CCP2MX The pin assignments for the Enhanced CCPx modules reassigns ECCP2/P2A to RB3. are summarized in Table18-1, Table18-2 and Table18-3. To configure the I/O pins as PWM outputs, 18.1.3 USE OF CCP4 AND CCP5 WITH the proper PWM mode must be selected by setting the ECCP1 AND ECCP3 PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>, respectively). The appropriate TRIS direction bits for Only the ECCP2 module has four dedicated, output the corresponding port pins must also be set as pins that are available for use. Assuming that the I/O outputs. ports or other multiplexed functions on those pins are not needed, they may be used without interfering with 18.1.1 ECCP1/ECCP3 OUTPUTS AND any other CCPx module. PROGRAM MEMORY MODE ECCP1 and ECCP3, on the other hand, only have In 100-pin devices, the use of Extended Microcontroller three dedicated output pins: ECCPx/PxA, PxB and mode has an indirect effect on the ECCP1 and ECCP3 PxC. Whenever these modules are configured for pins in Enhanced PWM modes. By default, PWM Quad PWM mode, the pin normally used for CCP4 or outputs, P1B/P1C and P3B/P3C, are multiplexed to CCP5 becomes the PxD output pin for ECCP3 and PORTE pins, along with the high-order byte of the ECCP1, respectively. The CCP4 and CCP5 modules external memory bus. When the bus is active in remain functional but their outputs are overridden. Extended Microcontroller mode, it overrides the Enhanced CCPx outputs and makes them unavailable. 18.1.4 ECCPx MODULES AND TIMER Because of this, ECCP1 and ECCP3 can only be used RESOURCES in compatible (single output) PWM modes when the Like the standard CCPx modules, the ECCPx modules device is in Extended Microcontroller mode with default can utilize Timers 1, 2, 3 or 4, depending on the mode pin configuration. selected. Timer1 and Timer3 are available for modules An exception to this configuration is when a 12-bit in Capture or Compare modes, while Timer2 and address width is selected for the external bus Timer4 are available for modules in PWM mode. (EMB<1:0> Configuration bits = 10). In this case, the Additional details on timer resources are provided in upper pins of PORTE continue to operate as digital I/O, Section17.1.1 “CCPx/ECCPx Modules and Timer even when the external bus is active. P1B/P1C and Resources”. P3B/P3C remain available for use as Enhanced PWM outputs. If an application requires the use of additional PWM outputs during Extended Microcontroller mode, the P1B/P1C and P3B/P3C outputs can be reassigned to the upper bits of PORTH. This is done by clearing the ECCPMX Configuration bit.  2011 Microchip Technology Inc. DS39762F-page 199

PIC18F97J60 FAMILY TABLE 18-1: PIN CONFIGURATIONS FOR ECCP1 CCP1CON RD0 or ECCP Mode RC2 RE5 RG4 RH7(2) RH6(2) Configuration RE6(1) 64-Pin Devices; 80-Pin Devices, ECCPMX = 1; 100-Pin Devices, ECCPMX = 1, Microcontroller mode or Extended Microcontroller mode with 12-Bit Address Width: Compatible CCP 00xx 11xx ECCP1 RD0/RE6 RE5 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A P1B RE5 RG4/CCP5 RH7/AN15 RH6/AN14 Quad PWM x1xx 11xx P1A P1B P1C P1D RH7/AN15 RH6/AN14 80-Pin Devices, ECCPMX = 0; 100-Pin Devices, ECCPMX = 0, All Program Memory modes: Compatible CCP 00xx 11xx ECCP1 RD0/RE6 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A RD0/RE6 RE5/AD13 RG4/CCP5 P1B RH6/AN14 Quad PWM(3) x1xx 11xx P1A RD0/RE6 RE5/AD13 P1D P1B P1C 100-Pin Devices, ECCPMX = 1, Extended Microcontroller mode with 16-Bit or 20-Bit Address Width: Compatible CCP 00xx 11xx ECCP1 RD0/RE6 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. Note 1: P1B is multiplexed with RD0 in 64-pin devices, and RE6 on 80-pin and 100-pin devices. 2: These pin options are not available in 64-pin devices. 3: With ECCP1 in Quad PWM mode, the CCP5 pin’s output is overridden by P1D; otherwise, CCP5 is fully operational. TABLE 18-2: PIN CONFIGURATIONS FOR ECCP2 CCP2CON ECCP Mode RB3 RC1 RE7 RE2 RE1 RE0 Configuration All Devices, CCP2MX = 1, All Program Memory modes: Compatible CCP 00xx 11xx RB3/INT3 ECCP2 RE7 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 P2A RE7 P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 P2A RE7 P2B P2C P2D 80-Pin and 100-Pin Devices, CCP2MX = 0, Microcontroller mode: Compatible CCP 00xx 11xx RB3/INT3 RC1/T1OS1 ECCP2 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 RC1/T1OS1 P2A P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 RC1/T1OS1 P2A P2B P2C P2D 100-Pin Devices, CCP2MX = 0, Extended Microcontroller mode: Compatible CCP 00xx 11xx ECCP2 RC1/T1OS1 RE7/AD15 RE2/CS RE1/WR RE0/RD Dual PWM 10xx 11xx P2A RC1/T1OS1 RE7/AD15 P2B RE1/WR RE0/RD Quad PWM x1xx 11xx P2A RC1/T1OS1 RE7/AD15 P2B P2C P2D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. DS39762F-page 200  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 18-3: PIN CONFIGURATIONS FOR ECCP3 CCP3CON RD1 or RD2 or ECCP Mode RE4 RE3 RH5(2) RH4(2) Configuration RG0(1) RG3(1) 64-Pin Devices; 80-Pin Devices, ECCPMX = 1; 100-Pin Devices, ECCPMX = 1, Microcontroller mode: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RD2/RG3 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A P3B RE3 RD2/RG3 RH5/AN13 RH4/AN12 Quad PWM x1xx 11xx P3A P3B P3C P3D RH5/AN13 RH4/AN12 80-Pin Devices, ECCPMX = 0; 100-Pin Devices, ECCPMX = 0, All Program Memory modes: Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RD2/RG3 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A RE6/AD14 RE5/AD13 RD2/RG3 P3B RH4/AN12 Quad PWM(3) x1xx 11xx P3A RE6/AD14 RE5/AD13 P3D P3B P3C 100-Pin Devices, ECCPMX = 1, Extended Microcontroller with 12-Bit Address Width: Compatible CCP 00xx 11xx ECCP3 RE4/AD12 RE3/AD11 RD2/RG3 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A P3B RE3/AD11 RD2/RG3 RH5/AN13 RH4/AN12 100-Pin Devices, ECCPMX = 1, Extended Microcontroller mode with 16-Bit or 20-Bit Address Width: Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RD2/RG3 RH5/AN13 RH4/AN12 Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP3 in a given mode. Note 1: ECCP3/P3A and CCP4/P3D are multiplexed with RD1 and RD2 in 64-pin devices, and RG0 and RG3 in 80-pin and 100-pin devices. 2: These pin options are not available in 64-pin devices. 3: With ECCP3 in Quad PWM mode, the CCP4 pin’s output is overridden by P3D; otherwise, CCP4 is fully operational.  2011 Microchip Technology Inc. DS39762F-page 201

PIC18F97J60 FAMILY 18.2 Capture and Compare Modes Special Event Triggers are not implemented for ECCP3, CCP4 or CCP5. Selecting the Special Event Except for the operation of the Special Event Trigger Trigger mode for these modules has the same effect as discussed below, the Capture and Compare modes of selecting the Compare with Software Interrupt mode the ECCPx modules are identical in operation to that of (CCPxM<3:0> = 1010). CCP4. These are discussed in detail in Section17.2 “Capture Mode” and Section17.3 “Compare Note: The Special Event Trigger from ECCP2 Mode”. will not set the Timer1 or Timer3 interrupt flag bits. 18.2.1 SPECIAL EVENT TRIGGER ECCP1 and ECCP2 incorporate an internal hardware 18.3 Standard PWM Mode trigger that is generated in Compare mode on a match When configured in Single Output mode, the ECCPx between the CCPRx register pair and the selected modules function identically to the standard CCPx timer. This can be used, in turn, to initiate an action. modules in PWM mode, as described in Section17.4 This mode is selected by setting CCPxCON<3:0> to “PWM Mode”. Sometimes this is also referred to as ‘1011’. “Compatible CCP” mode, as in Tables18-1 The Special Event Trigger output of either ECCP1 or through18-3. ECCP2 resets the TMR1 or TMR3 register pair, depending on which timer resource is currently Note: When setting up single output PWM selected. This allows the CCPRx register to effectively operations, users are free to use either of be a 16-Bit Programmable Period register for Timer1 or the processes described in Section17.4.3 Timer3. In addition, the ECCP2 Special Event Trigger “Setup for PWM Operation” or will also start an A/D conversion if the A/D module is Section18.4.9 “Setup for PWM Opera- enabled. tion”. The latter is more generic but will work for either single or multi-output PWM. DS39762F-page 202  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 18.4 Enhanced PWM Mode Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead, offset by The Enhanced PWM mode provides additional PWM one full instruction cycle (4 TOSC). output options for a broader range of control applica- As before, the user must manually configure the tions. The module is a backward compatible version of appropriate TRIS bits for output. the standard CCPx modules and offers up to four out- puts, designated PxA through PxD. Users are also able 18.4.1 PWM PERIOD to select the polarity of the signal (either active-high or active-low). The module’s output mode and polarity are The PWM period is specified by writing to the PR2 configured by setting the PxM<1:0> and CCPxM<3:0> register. The PWM period can be calculated using the bits of the CCPxCON register (CCPxCON<7:6> and following equation: <3:0>, respectively). EQUATION 18-1: For the sake of clarity, Enhanced PWM mode operation is described generically throughout this section with PWM Period = [(PR2) + 1] • 4 • TOSC • respect to ECCP1 and TMR2 modules. Control register (TMR2 Prescale Value) names are presented in terms of ECCP1. All three Enhanced modules, as well as the two timer resources, PWM frequency is defined as 1/[PWM period]. When can be used interchangeably and function identically. TMR2 is equal to PR2, the following three events occur TMR2 or TMR4 can be selected for PWM operation by on the next increment cycle: selecting the proper bits in T3CON. • TMR2 is cleared Figure18-1 shows a simplified block diagram of PWM • The ECCP1 pin is set (if PWM duty cycle=0%, operation. All control registers are double-buffered and the ECCP1 pin will not be set) are loaded at the beginning of a new PWM cycle (the • The PWM duty cycle is copied from CCPR1L into period boundary when Timer2 resets) in order to pre- CCPR1H vent glitches on any of the outputs. The exception is the ECCP1 Dead-Band Delay register, ECCP1DEL, which Note: The Timer2 postscaler (see Section14.0 is loaded at either the duty cycle boundary or the “Timer2 Module”) is not used in the boundary period (whichever comes first). Because of determination of the PWM frequency. The the buffering, the module waits until the assigned timer postscaler could be used to have a servo resets instead of starting immediately. This means that update rate at a different frequency than the PWM output. FIGURE 18-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> P1M1<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L ECCP1/P1A ECCP1/P1A TRISx<x> CCPR1H (Slave) P1B P1B Output TRISx<x> Comparator R Q Controller P1C P1C TMR2 (Note 1) S TRISx<x> Comparator P1D P1D Clear Timer, TRISx<x> set ECCP1 pin and PR2 latch D.C. ECCP1DEL Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.  2011 Microchip Technology Inc. DS39762F-page 203

PIC18F97J60 FAMILY 18.4.2 PWM DUTY CYCLE Note: If the PWM duty cycle value is longer than The PWM duty cycle is specified by writing to the the PWM period, the ECCP1 pin will not CCPR1L register and to the CCP1CON<5:4> bits. Up be cleared. to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> bits contain 18.4.3 PWM OUTPUT CONFIGURATIONS the two LSbs. This 10-bit value is represented by The P1M<1:0> bits in the CCP1CON register allow one CCPR1L:CCP1CON<5:4>. The PWM duty cycle is of four configurations: calculated by the equation: • Single Output EQUATION 18-2: • Half-Bridge Output PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • • Full-Bridge Output, Forward mode TOSC • (TMR2 Prescale Value) • Full-Bridge Output, Reverse mode The Single Output mode is the standard PWM mode CCPR1L and CCP1CON<5:4> can be written to at any discussed in Section18.4 “Enhanced PWM Mode”. time, but the duty cycle value is not copied into The Half-Bridge and Full-Bridge Output modes are CCPR1H until a match between PR2 and TMR2 occurs covered in detail in the sections that follow. (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The general relationship of the outputs in all configurations is summarized in Figure18-2. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM opera- tion. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the ECCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation: EQUATION 18-3: log(FOSC) FPWM PWM Resolution (max) = bits log(2) TABLE 18-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 DS39762F-page 204  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 18-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 PR2 + 1 Duty CCP1CON<7:6> SIGNAL Cycle Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section18.4.6 “Programmable Dead-Band Delay”).  2011 Microchip Technology Inc. DS39762F-page 205

PIC18F97J60 FAMILY FIGURE 18-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) CCP1CON<7:6> SIGNAL 0 Duty PR2 + 1 Cycle Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive P1B Modulated (Full-Bridge, 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section18.4.6 “Programmable Dead-Band Delay”). DS39762F-page 206  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 18.4.4 HALF-BRIDGE MODE FIGURE 18-4: HALF-BRIDGE PWM OUTPUT In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output Period Period signal is output on the P1A pin, while the complemen- tary PWM output signal is output on the P1B pin Duty Cycle (Figure18-4). This mode can be used for half-bridge P1A(2) applications, as shown in Figure18-5, or for full-bridge td applications, where four power switches are being td modulated with two PWM signals. P1B(2) In Half-Bridge Output mode, the programmable dead-band delay can be used to prevent shoot-through (1) (1) (1) current in half-bridge power devices. The value of bits, P1DC<6:0>, sets the number of instruction cycles td = Dead Band Delay before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains Note 1: At this time, the TMR2 register is equal to the inactive during the entire cycle. See Section18.4.6 PR2 register. “Programmable Dead-Band Delay” for more details 2: Output signals are shown as active-high. on dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTE<6> data latches, the TRISC<2> and TRISE<6> bits must be cleared to configure P1A and P1B as outputs. FIGURE 18-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) PIC18F97J60 FET Driver + P1A V - Load FET Driver + P1B V - V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F97J60 FET FET Driver Driver P1A Load FET FET Driver Driver P1B V-  2011 Microchip Technology Inc. DS39762F-page 207

PIC18F97J60 FAMILY 18.4.5 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the data latches of the port pins listed in Table18-1 and In Full-Bridge Output mode, four pins are used as Table18-3. The corresponding TRIS bits must be outputs; however, only two outputs are active at a time. cleared to make the P1A, P1B, P1C and P1D pins In the Forward mode, pin, P1A, is continuously active outputs. and pin, P1D, is modulated. In the Reverse mode, pin, P1C, is continuously active and pin, P1B, is modulated. These are illustrated in Figure18-6. FIGURE 18-6: FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. DS39762F-page 208  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 18-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F97J60 FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D 18.4.5.1 Direction Change in Full-Bridge Mode 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the 2. The turn-off time of the power switch, including forward/reverse direction. When the application firm- the power device and driver circuit, is greater ware changes this direction control bit, the module will than the turn-on time. assume the new direction on the next PWM cycle. Figure18-9 shows an example where the PWM direc- Just before the end of the current PWM period, the tion changes from forward to reverse at a near 100% modulated outputs (P1B and P1D) are placed in their duty cycle. At time, t1, the outputs, P1A and P1D, inactive state, while the unmodulated outputs (P1A and become inactive, while output, P1C, becomes active. In P1C) are switched to drive in the opposite direction. this example, since the turn-off time of the power This occurs in a time interval of (4 TOSC * (Timer2 devices is longer than the turn-on time, a shoot-through Prescale Value) before the next PWM period begins. current may flow through power devices, QC and QD The Timer2 prescaler will be either 1, 4 or 16, depend- (see Figure18-7), for the duration of ‘t’. The same ing on the value of the T2CKPS bits (T2CON<1:0>). phenomenon will occur to power devices, QA and QB, During the interval from the switch of the unmodulated for PWM direction change from reverse to forward. outputs to the beginning of the next period, the If changing PWM direction at high duty cycle is required modulated outputs (P1B and P1D) remain inactive. for an application, one of the following requirements This relationship is shown in Figure18-8. must be met: Note that in Full-Bridge Output mode, the ECCP1 mod- 1. Reduce PWM for a PWM period before ule does not provide any dead-band delay. In general, changing directions. since only one output is modulated at all times, 2. Use switch drivers that can drive the switches off dead-band delay is not required. However, there is a faster than they can drive them on. situation where a dead-band delay might be required. Other options to prevent shoot-through current may This situation occurs when both of the following exist. conditions are true:  2011 Microchip Technology Inc. DS39762F-page 209

PIC18F97J60 FAMILY FIGURE 18-8: PWM DIRECTION CHANGE Period(1) Period SIGNAL P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written at any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 18-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A(1) P1B(1) DC P1C(1) P1D(1) DC t (2) ON External Switch C(1) t (3) OFF External Switch D(1) Potential t = t – t (2,3) OFF ON Shoot-Through Current(1) Note 1: All signals are shown as active-high. 2: t is the turn-on delay of power switch, QC, and its driver. ON 3: t is the turn-off delay of power switch, QD, and its driver. OFF DS39762F-page 210  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 18.4.6 PROGRAMMABLE DEAD-BAND A shutdown event can be caused by either of the two DELAY comparator modules or the FLT0 pin (or any combina- tion of these three sources). The comparators may be In half-bridge applications, where all power switches used to monitor a voltage input proportional to a current are modulated at the PWM frequency at all times, the being monitored in the bridge circuit. If the voltage power switches normally require more time to turn off exceeds a threshold, the comparator switches state and than to turn on. If both the upper and lower power triggers a shutdown. Alternatively, a low-level digital switches are switched at the same time (one turned on signal on the FLT0 pin can also trigger a shutdown. The and the other turned off), both switches may be on for auto-shutdown feature can be disabled by not selecting a short period of time until one switch completely turns any auto-shutdown sources. The auto-shutdown sources off. During this brief interval, a very high current to be used are selected using the ECCP1AS<2:0> bits (shoot-through current) may flow through both power (ECCP1AS<6:4>). switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flow- When a shutdown occurs, the output pins are ing during switching, turning on either of the power asynchronously placed in their shutdown states, switches is normally delayed to allow the other switch specified by the PSS1AC<1:0> and PSS1BD<1:0> bits to completely turn off. (ECCP1AS<3:0>). Each pin pair (P1A/P1C and P1B/P1D) may be set to drive high, drive low or be In the Half-Bridge Output mode, a digitally program- tri-stated (not driving). The ECCP1ASE bit mable dead-band delay is available to avoid (ECCP1AS<7>) is also set to hold the Enhanced PWM shoot-through current from destroying the bridge outputs in their shutdown states. power switches. The delay occurs at the signal transition from the non-active state to the active state. The ECCP1ASE bit is set by hardware when a shutdown See Figure18-4 for the illustration. The lower seven event occurs. If automatic restarts are not enabled, the bits of the ECCP1DEL register (Register18-2) set the ECCP1ASE bit is cleared by firmware when the cause of delay period in terms of microcontroller instruction the shutdown clears. If automatic restarts are enabled, cycles (TCY or 4 TOSC). the ECC1PASE bit is automatically cleared when the cause of the auto-shutdown has cleared. 18.4.7 ENHANCED PWM If the ECCP1ASE bit is set when a PWM period begins, AUTO-SHUTDOWN the PWM outputs remain in their shutdown state for that When the ECCP1 is programmed for any of the entire PWM period. When the ECCP1ASE bit is cleared, Enhanced PWM modes, the active output pins may be the PWM outputs will return to normal operation at the configured for auto-shutdown. Auto-shutdown immedi- beginning of the next PWM period. ately places the Enhanced PWM output pins into a Note: Writing to the ECCP1ASE bit is disabled defined shutdown state when a shutdown event while a shutdown condition is active. occurs. REGISTER 18-2: ECCP1DEL: ECCP1 DEAD-BAND DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 P1RSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCP1ASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCP1ASE must be cleared in software to restart the PWM bit 6-0 P1DC<6:0>: PWM Delay Count bits Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled time and actual time for a PWM signal to transition to active.  2011 Microchip Technology Inc. DS39762F-page 211

PIC18F97J60 FAMILY R EGISTER 18-3: ECCP1AS: ECCP1 AUTO-SHUTDOWN CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCP1ASE: ECCP1 Auto-Shutdown Event Status bit 0 = ECCP1 outputs are operating 1 = A shutdown event has occurred; ECCP1 outputs are in shutdown state bit 6-4 ECCP1AS<2:0>: ECCP1 Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator 1 output 010 = Comparator 2 output 011 = Either Comparator 1 or 2 100 = FLT0 101 = FLT0 or Comparator 1 110 = FLT0 or Comparator 2 111 = FLT0 or Comparator 1 or Comparator 2 bit 3-2 PSS1AC<1:0>: A and C Pins Shutdown State Control bits 00 = Drive A and C pins to ‘0’ 01 = Drive A and C pins to ‘1’ 1x = A and C pins tri-state bit 1-0 PSS1BD<1:0>: B and D Pins Shutdown State Control bits 00 = Drive B and D pins to ‘0’ 01 = Drive B and D pins to ‘1’ 1x = B and D pins tri-state DS39762F-page 212  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 18.4.7.1 Auto-Shutdown and Automatic 18.4.8 START-UP CONSIDERATIONS Restart When the ECCP1 module is used in the PWM mode, the The auto-shutdown feature can be configured to allow application hardware must use the proper external pull-up automatic restarts of the module following a shutdown and/or pull-down resistors on the PWM output pins. When event. This is enabled by setting the P1RSEN bit of the the microcontroller is released from Reset, all of the I/O ECCP1DEL register (ECCP1DEL<7>). pins are in the high-impedance state. The external circuits must keep the power switch devices in the OFF state until In Shutdown mode with P1RSEN = 1 (Figure18-10), the microcontroller drives the I/O pins with the proper the ECCP1ASE bit will remain set for as long as the signal levels, or activates the PWM output(s). cause of the shutdown continues. When the shutdown condition clears, the ECCP1ASE bit is cleared. If The CCP1M<1:0> bits (CCP1CON<1:0>) allow the P1RSEN =0 (Figure18-11), once a shutdown condi- user to choose whether the PWM output signals are tion occurs, the ECCP1ASE bit will remain set until it is active-high or active-low for each pair of PWM output cleared by firmware. Once ECCP1ASE is cleared, the pins (P1A/P1C and P1B/P1D). The PWM output Enhanced PWM will resume at the beginning of the polarities must be selected before the PWM pins are next PWM period. configured as outputs. Changing the polarity configura- tion while the PWM pins are configured as outputs is Note: Writing to the ECCP1ASE bit is disabled not recommended since it may result in damage to the while a shutdown condition is active. application circuits. Independent of the P1RSEN bit setting, if the The P1A, P1B, P1C and P1D output latches may not be auto-shutdown source is one of the comparators, the in the proper states when the PWM module is initialized. shutdown condition is a level. The ECCP1ASE bit Enabling the PWM pins for output at the same time as cannot be cleared as long as the cause of the shutdown the ECCP1 module may cause damage to the applica- persists. tion circuit. The ECCP1 module must be enabled in the The Auto-Shutdown mode can be forced by writing a ‘1’ proper Output mode and complete a full PWM cycle to the ECCP1ASE bit. before configuring the PWM pins as outputs. The com- pletion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. FIGURE 18-10: PWM AUTO-SHUTDOWN (P1RSEN = 1, AUTO-RESTART ENABLED) PWM Period ShutdownEvent ECCP1ASE bit PWM Activity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes FIGURE 18-11: PWM AUTO-SHUTDOWN (P1RSEN = 0, AUTO-RESTART DISABLED) PWM Period ShutdownEvent ECCP1ASE bit PWM Activity Normal PWM ECCP1ASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes  2011 Microchip Technology Inc. DS39762F-page 213

PIC18F97J60 FAMILY 18.4.9 SETUP FOR PWM OPERATION 8. If auto-restart operation is required, set the P1RSEN bit (ECCP1DEL<7>). The following steps should be taken when configuring the ECCP1 module for PWM operation: 9. Configure and start TMR2 (TMR4): • Clear the TMRx interrupt flag bit by clearing 1. Configure the PWM pins, P1A and P1B (and the TMRxIF bit (PIR1<1> for Timer2 or P1C and P1D, if used), as inputs by setting the PIR3<3> for Timer4). corresponding TRIS bits. • Set the TMRx prescale value by loading the 2. Set the PWM period by loading the PR2 (PR4) TxCKPS bits (T2CON<1:0> for Timer2 or register. T4CON<1:0> for Timer4). 3. Configure the ECCP1 module for the desired • Enable Timer2 (or Timer4) by setting the PWM mode and configuration by loading the TMRxON bit (T2CON<2> for Timer2 or CCP1CON register with the appropriate values: T4CON<2> for Timer4). • Select one of the available output 10. Enable PWM outputs after a new PWM cycle configurations and direction with the has started: P1M<1:0> bits. • Wait until TMR2 (TMR4) overflows (TMRxIF • Select the polarities of the PWM output bit is set). signals with the CCP1M<3:0> bits. • Enable the ECCP1/P1A, P1B, P1C and/or 4. Set the PWM duty cycle by loading the CCPR1L P1D pin outputs by clearing the respective register and the CCP1CON<5:4> bits. TRIS bits. 5. For auto-shutdown: • Clear the ECCP1ASE bit (ECCP1AS<7>). • Disable auto-shutdown; ECCP1ASE = 0 • Configure auto-shutdown source 18.4.10 EFFECTS OF A RESET • Wait for Run condition Both Power-on Reset and subsequent Resets will force 6. For Half-Bridge Output mode, set the all ports to Input mode and the CCPx/ECCPx registers dead-band delay by loading ECCP1DEL<6:0> to their Reset states. with the appropriate value. This forces the Enhanced CCPx modules to reset to a 7. If auto-shutdown operation is required, load the state compatible with the standard CCPx modules. ECCP1AS register: • Select the auto-shutdown sources using the ECCP1AS<2:0> bits. • Select the shutdown states of the PWM output pins using PSS1AC<1:0> and PSS1BD<1:0> bits. • Set the ECCP1ASE bit (ECCP1AS<7>). DS39762F-page 214  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 18-5: REGISTERS ASSOCIATED WITH ECCPx MODULES AND TIMER1 TO TIMER4 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 RCON IPEN — CM RI TO PD POR BOR 70 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR2 OSCFIF CMIF ETHIF r BCL1IF — TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE — TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP — TMR3IP CCP2IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 71 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 71 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 71 TRISE TRISE7(2) TRISE6(2) TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 71 TRISG TRISG7 TRISG6 TRISG5 TRISG4 TRISG3(2) TRISG2 TRISG1 TRISG0(2) 71 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 71 TMR1L Timer1 Register Low Byte 70 TMR1H Timer1 Register High Byte 70 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 70 TMR2 Timer2 Register 70 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 70 PR2 Timer2 Period Register 70 TMR3L Timer3 Register Low Byte 70 TMR3H Timer3 Register High Byte 70 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 71 TMR4 Timer4 Register 72 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 72 PR4 Timer4 Period Register 72 CCPRxL(3) Capture/Compare/PWM Register x Low Byte 70 CCPRxH(3) Capture/Compare/PWM Register x High Byte 70 CCPxCON(3) PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 70 ECCPxAS(3) ECCPXASE ECCPXAS2 ECCPXAS1 ECCPXAS0 PSSXAC1 PSSXAC0 PSSXBD1 PSSXBD0 70, 73 ECCPxDEL(3) PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 73 Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used during ECCPx operation. Note 1: Applicable in 64-pin devices only. 2: Registers and/or specific bits are unimplemented in 64-pin devices. 3: Generic term for all of the identical registers of this name for all Enhanced CCPx modules, where ‘x’ identifies the individual module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same generic name are identical.  2011 Microchip Technology Inc. DS39762F-page 215

PIC18F97J60 FAMILY NOTES: DS39762F-page 216  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.0 ETHERNET MODULE The Ethernet module consists of five major functional blocks: All members of the PIC18F97J60 family of devices 1. The PHY transceiver module that encodes and feature an embedded Ethernet controller module. This decodes the analog data that is present on the is a complete connectivity solution, including full imple- twisted-pair interface and sends or receives it mentations of both Media Access Control (MAC) and over the network. Physical Layer (PHY) transceiver modules. Two pulse transformers and a few passive components are all that 2. The MAC module that implements IEEE 802.3 are required to connect the microcontroller directly to compliant MAC logic and provides Media an Ethernet network. Independent Interface Management (MIIM) to control the PHY. The Ethernet module meets all of the IEEE 802.3™ 3. An independent, 8-Kbyte RAM buffer for storing specifications for 10-BaseT connectivity to a twisted-pair packets that have been received and packets network. It incorporates a number of packet filtering that are to be transmitted. schemes to limit incoming packets. It also provides an internal DMA module for fast data throughput and hard- 4. An arbiter to control access to the RAM buffer ware assisted IP checksum calculations. Provisions are when requests are made from the microcontroller also made for two LED outputs to indicate link and core, DMA, transmit and receive blocks. network activity. 5. The register interface that functions as an inter- preter of commands and internal status signals A simple block diagram of the module is shown in between the module and the microcontroller’s Figure19-1. SFRs. FIGURE 19-1: ETHERNET MODULE BLOCK DIAGRAM RX MAC RXBM PHY Arbiter TPOUT+ 8-Kbyte ch0 RXF (Filter) Ethernet RAM MII TX TPOUT- Buffer ch1 Interface DMA and ch0 ch2 IP Checksum TPIN+ TX ch1 RX TPIN- TXBM Flow Control Ethernet Ethernet MIIM RBIAS Buffer Data Interface Addresses Host Interface Ethernet EDATA Ethernet Buffer Pointers Control PHY Register Data MIRD/MIWR PHY Register Addresses MIREGADR Microcontroller SFRs LEDA/LEDBControl 8 Microcontroller Data Bus  2011 Microchip Technology Inc. DS39762F-page 217

PIC18F97J60 FAMILY 19.1 Physical Interfaces and External The LEDs can be individually configured to Connections automatically display link status, RX/TX activity, etc. A configurable stretch capability prolongs the LED blink 19.1.1 SIGNAL AND POWER INTERFACES duration for short events, such as a single packet transmit, allowing human perception. The options are PIC18F97J60 family devices all provide a dedicated controlled by the PHLCON register (Register19-13). 4-pin signal interface for the Ethernet module. No other Typical values for blink stretch are listed in Table19-1. microcontroller or peripheral functions are multiplexed with these pins, so potential device configuration TABLE 19-1: LED BLINK STRETCH conflicts do not need to be considered. The pins are: LENGTH • TPIN+: Differential plus twisted-pair input Stretch Length Typical Stretch (ms) • TPIN-: Differential minus twisted-pair input • TPOUT+: Differential plus twisted-pair output TNSTRCH (normal) 40 • TPOUT-: Differential minus twisted-pair output TMSTRCH (medium) 70 No provisions are made for providing or receiving TLSTRCH (long) 140 digital Ethernet data from an external Ethernet PHY. 19.1.3 OSCILLATOR REQUIREMENTS In addition to the signal connections, the Ethernet mod- ule has its own independent voltage source and ground The Ethernet module is designed to operate at 25 MHz. connections for the PHY module. Separate connections This is provided by the primary microcontroller clock, are provided for the receiver (VDDRX and VSSRX), the either with a 25MHz crystal connected to the OSC1 transmitter (VDDTX and VSSTX) and the transmitter’s and OSC2 pins or an external clock source connected internal PLL (VDDPLL and VSSPLL). Although the voltage to the OSC1 pin. No provision is made to clock the requirements are the same as VDD and VSS for the module from a different source. microcontroller, the pins are not internally connected. To maintain the required clock frequency, the microcon- For the Ethernet module to operate properly, supply troller can operate only from the primary oscillator voltage and ground must be connected to these pins. All source (PRI_RUN or PRI_IDLE modes) while the of the microcontroller’s power and ground supply pins Ethernet module is enabled. Using any other should be externally connected to the same power power-managed mode will require that the Ethernet source or ground node, with no inductors or other filter module be disabled. components between the microcontroller and Ethernet module’s VDD pins. 19.1.3.1 Start-up Timer Besides the independent voltage connections, the PHY The Ethernet module contains a start-up timer, module has a separate bias current input pin, RBIAS. A independent of the microcontroller’s OST, to ensure bias current, derived from an external resistor, must be that the PHY module’s PLL has stabilized before applied to RBIAS for proper transceiver operation. operation. Clearing the module enable bit, ETHEN (ECON2<5>), clears the PHYRDY status bit 19.1.2 LED CONFIGURATION (ESTAT<0>). Setting the ETHEN bit causes this The PHY module provides separate outputs to drive the start-up timer to start counting. When the timer expires, standard Ethernet indicators, LEDA and LEDB. The LED after 1ms, the PHYRDY bit will be automatically set. outputs are multiplexed with PORTA pins, RA0 and RA1. After enabling the module by setting the ETHEN bit, the Their use as LED outputs is enabled by setting the Con- application software should always poll PHYRDY to figuration bit, ETHLED (Register25-6, CONFIG3H<2>). determine when normal Ethernet operation can begin. When configured as LED outputs, RA0/LEDA and RA1/LEDB have sufficient drive capacity (up to 25mA) to directly power the LEDs. The pins must always be configured to supply (source) current to the LEDs. Users must also configure the pins as outputs by clearing TRISA<1:0>. DS39762F-page 218  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.1.4 MAGNETICS, TERMINATION AND common-mode choke is used to reduce EMI emissions, OTHER EXTERNAL COMPONENTS it should be placed between the Ethernet transformer and Pins 1 and 2, of the RJ-45 connector. Many Ethernet To complete the Ethernet interface, the Ethernet transformer modules include common-mode chokes module requires several standard components to be inside the same device package. The transformers installed externally. These components should be should have at least the isolation rating specified in connected, as shown in Figure19-2. Table28-28 to protect against static voltages and meet The internal analog circuitry in the PHY module requires IEEE 802.3 isolation requirements (see Section28.5 that an external resistor (2.26k) be attached from “Ethernet Specifications and Requirements” for RBIAS to ground. The resistor influences the TPOUT+/- specific transformer requirements). Both transmit and signal amplitude. It should be placed as close as possible receive interfaces additionally require two resistors and to the chip with no immediately adjacent signal traces to a capacitor to properly terminate the transmission line, prevent noise capacitively coupling into the pin and minimizing signal reflections. affecting the transmit behavior. It is recommended that All power supply pins must be externally connected to the resistor be a surface mount type. the same power source. Similarly, all ground refer- On the TPIN+/TPIN- and TPOUT+/TPOUT- pins, ences must be externally connected to the same 1:1center-tapped pulse transformers, rated for Ethernet ground node. Each VDD and VSS pin pair should have operations (10/100 or 10/100/1000), are required. When a 0.1F ceramic bypass capacitor placed as close to the Ethernet module is enabled, current is continually the pins as possible. sunk through both TPOUT pins. When the PHY is Since relatively high currents are necessary to operate actively transmitting, a differential voltage is created on the twisted-pair interface, all wires should be kept as the Ethernet cable by varying the relative current sunk short as possible. Reasonable wire widths should be by TPOUT+ compared to TPOUT-. used on power wires to reduce resistive loss. If the A common-mode choke on the PHY side of the interface differential data lines cannot be kept short, they should (i.e., between the microcontrollers’s TPOUT pins and be routed in such a way as to have a 100 characteristic the Ethernet transformer) is not recommend. If a impedance. FIGURE 19-2: EXTERNAL COMPONENTS REQUIRED FOR ETHERNET OPERATION 1 PIC18FXXJ6X 3.3V RJ-45 120(1) CMC(2) TPOUT+ 56pF(1) 49.9, 1% 1 ±5% C1(3) 2 OSC1 0.1 F(1) 49.9, 1% 25 MHz TPOUT- 120(1) 1:1 CT 3 TPIN+ CMC(2) 56pF(1) 4 C2(3) ±5% 49.9, 1% OSC2 5 49.9, 1% 0.1 F 1:1 CT 6 TPIN- 7 1,4) 1,4) 1, 4) 1,4) LEDA LEDB RBIAS ( ( ( ( 8 5 5 5 5 7 7 7 7 2.26 k, 1% 1 nF, 2 kV(1) Note 1: These components are installed for EMI reduction purposes. See Section19.1.5 for more information. 2: Recommended insertion point for Common-Mode Chokes (CMCs) if required for EMI reduction. 3: See Section3.3 “Crystal Oscillator/Ceramic Resonators (HS Modes)” for recommended values. 4: Power over Ethernet applications require capacitors in series with these resistors.  2011 Microchip Technology Inc. DS39762F-page 219

PIC18F97J60 FAMILY 19.1.5 EMI EMISSIONS CONSIDERATIONS Often, the use of “5-core” magnetics, or magnetics involv- ing a center tapped inductor or auto-transformer on the Most locales have limits on unintentional EMI or EMC TX path, is also desirable for EMI emissions reasons. emissions that govern the amount of electromagnetic energy that may be radiated into the environment 19.1.6 AUTOMATIC RX POLARITY across a range of test frequencies. Ethernet applica- DETECTION AND CORRECTION tions normally do not include intentional radio frequency emissions sources. They may experience 10Base-T Ethernet signaling is performed on the Ether- occasional regulatory failures though, due to the rela- net cable as a differentially encoded Manchester data tive ease at which high-frequency noise may radiate stream. This signaling is polarized; therefore, it is out of a long attached Ethernet cable. Long cables can required that the RX+ Ethernet signal on the Ethernet act as unintentional antennas. cable reach the TPIN+ pin, and the RX- Ethernet signal reach the TPIN- pin. Connecting RX+ to TPIN- and RX- The PIC18F97J60 family Ethernet module transmit to TPIN+ (by way of Ethernet isolation transformers) engine internally operates by stepping the 25MHz will cause the PIC18F97J60 family Ethernet module to base Ethernet clock up to a high frequency via a PLL successfully link with the remote partner. However, all embedded in the PHY module. Then, the high receive data will be corrupted by the polarity mismatch frequency is used to turn on/turn off small current sinks and will be internally discarded by the PHY as if it were on the TPOUT+ and TPOUT- pins. This current-mode noise on the wire. drive technique allows the PHY to generate an Ether- net TX waveform that resembles an analog signal, with Higher speed 100Base-TX and 1000Base-T Ethernet most spectral energy at or below 20MHz. technologies uses different signaling schemes. They use Multi-Level Transition 3 (MLT3) and Five-Level However, while low in amplitude, the high frequency Pulse Amplitude Modulation (PAM5) encoding on the used to synthesize the waveform can, in some applica- wire, respectively. These encodings are non-polarized. tion circuits, radiate out of the circuit and result in Therefore, swapping the differential wires will have no regulatory emissions compliance failures. Such failures impact on the Ethernet controller's ability to caused by the Ethernet module will normally be exhib- communicate with the remote node. ited as excess emissions at 200MHz and occasionally 400MHz. A limited number of modern 3rd party 10/100 and 10/100/1000 rated Ethernet devices (switches, routers To minimize the chance of failure, the use of the LC and end devices) connect their TX+ and TX- signals to the low-pass filter is recommended on the TPOUT+ and incorrect pins on their RJ-45 Ethernet jack. These devices TPOUT- pins, as shown Figure19-2. are not IEEE Standard 802.3 compliant. However, In this circuit, 120 ohm ferrite beads are used along because 100Base-TX and 1000Base-T communications with 56pF±5% capacitors to form a low-pass filter with continue to work without correct polarization, some 3rd a -3dB breakpoint that is above 20 MHz, but below party vendors mistakenly release their products to 200MHz. 10Base-T Ethernet signaling requires only production without catching these polarization errors. about 20MHz of spectral bandwidth, so minimal distor- Due to these circumstances, current revisions of the tion is done to the Ethernet signal by using these filters. Ethernet controller in the PIC18F97J60 family of However, noise at 200MHz or 400MHz, generated by devices are not compatible with a limited number of 3rd the PHY, is reduced by several decibels before having party Ethernet devices. The PIC18FXXJXX devices will a chance to radiate out of the application and cause a link up with the partner and the PHY RX activity LED (if regulatory failure. In this circuit, the ferrite beads must enabled) will blink whenever a packet is transmitted to have a saturation current rating of at least 100mA. the PIC18FXXJXX device. However, no packets will be If EMI emissions regulations are stringent in your successfully received and written in the Ethernet locale, additional care should be taken when selecting SRAM buffer when the polarity is incorrect. To eliminate the Ethernet magnetics to further minimize unintention- this problem, and obtain maximum interoperability with ally radiating common-mode signals out of the Ethernet 3rd party devices, it is possible to externally add an RX cable. Ethernet magnetics with a high differential to polarity swapping circuit to PIC18F97J60 family common-mode rejection ratio should be used. applications. Figure19-3 demonstrates the use of bus The differential to common-mode rejection parameter switches to facilitate the swapping of the RX signals. is normally expressed in magnetics manufacturers’ In Figure19-3, a general purpose output pin is used to data sheets, in units of negative decibels across a test select the polarity of the RX signals. When the select line frequency range. In the absence of test data indicating is held low, the A ports of the switches will connect with otherwise, a more negative specification at higher the B0 ports, leaving the B1 ports disconnected. This will frequencies is recommended for the PIC18F97J60 allow the TPIN+ pin to be connected to Pin 3 of the family Ethernet module. For example, a device rated RJ-45 jack while TPIN- is connected to Pin 6. These for -40dB @ 100MHz is likely preferable to -33dB @ connections accommodate the IEEE Standard 802.3 100MHz, even if the performance at 30MHz is similar specified polarity. or better on the -33dB @ 100MHz magnetics. DS39762F-page 220  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY When the select line is raised high, the A ports of the immediate response. This method requires the use of switches will connect with the B1 ports, leaving the B0 a protocol that results in a response packet from the ports disconnected. This will swap the RX polarity and network. In many networks, Dynamic Host Configura- route the TPIN+ pin to the signal on RJ-45 Jack Pin 6. tion Protocol (DHCP) discovery packets may be used TPIN- will connect to RJ-45 Pin 3. This swapped polar- to resolve the correct TPIN polarity quickly. ity can correct an incorrectly wired signal generated at Care should be taken when selecting the bus switches the remote link partner or in the intermediate cabling. to ensure that they are capable of passing the Ethernet In the MCU, software must be written to toggle the signals without distortion. The TPIN± pins will weakly select line state to the correct level based on the con- bias the RX common-mode voltage to approximately nected link partner. This is best achieved by VDD/2, and the Ethernet RX waveform will add up to periodically toggling the select line at low frequency ±1.4V onto this common-mode voltage. Therefore, the (<5Hz), while watching for a successful packet recep- switches must be capable of passing signals of at least tion event. When the correct polarity is found, the select 3.05V. line should stop toggling and remain static until the Additionally, the bus switches should have low Ethernet link is removed. capacitance to minimize the signal loss and impedance In some cases, rather than periodically toggling the discontinuity that may affect the RX signal. The polarity select at a low frequency to receive a packet, switches, rated -3dB bandwidth, must be well above faster determination of the correct polarity may be 20MHz. determined by transmitting a packet and looking for an FIGURE 19-3: RX POLARITY CORRECTION CIRCUIT (TX CONNECTIONS NOT SHOWN) PIC18FXXJ6X GPIO RJ-45 and Magnetics 1 6 +3.3V TX 2 5 TPIN+ 3 4 RX 9 NC7SB3157 9. 4 4x 75 ohm F  9.9 0.1 1 6 +3.3V 1000 pF 2kV 4 2 5 TPIN- 3 4 NC7SB3157 100K  2011 Microchip Technology Inc. DS39762F-page 221

PIC18F97J60 FAMILY 19.2 Ethernet Buffer and Register The Ethernet buffer and PHY Control registers are Spaces contained entirely within the Ethernet module and can- not be accessed directly by the microcontroller. Data is The Ethernet module uses three independent memory transferred between the Ethernet and microcontroller spaces for its operations: by using buffer and pointer registers mapped in the • An Ethernet RAM buffer which stores packet data microcontroller’s SFR space. The relationships as it is received and being prepared for between the SFRs and the Ethernet module’s memory transmission. spaces are shown in Figure19-4. • A set of 8-bit Special Function Registers (SFRs), used to control the module, and pass data back and forth between the module and microcontroller core. • A separate set of 16-bit PHY registers used specifically for PHY control and status reporting. FIGURE 19-4: RELATIONSHIP BETWEEN MICROCONTROLLER AND ETHERNET MEMORY SPACES Microcontroller SFRs Ethernet Module Ethernet Buffer 0000h Ethernet Data EDATA ERDPT(H:L) EWRPT(H:L) 1FFFh ETXST(H:L) ETXND(H:L) Buffer Address ERXST(H:L) ERXND(H:L) ERXRDPT(H:L) ERXWRPT(H:L) PHY Registers 00h PHY Register Data (In/Out) MIRD(H:L) MIWR(H:L) 1Fh PHY Register Address MIREGADR Note: Microcontroller SFRs are not shown in the order of their placement in the data memory space. Memory areas are not shown to scale. DS39762F-page 222  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.2.1 ETHERNET BUFFER AND BUFFER into the ERXND Pointers, will cause the ERDPT POINTER REGISTERS registers to be incremented to the value contained in the ERXST Pointers. Writing to the buffer, on the other The Ethernet buffer contains the transmit and receive hand, does not result in automatic wrapping. memory used by the Ethernet controller. The entire buffer is 8Kbytes, divided into separate receive and By design, the Ethernet memory buffer is unable to transmit buffer spaces. The sizes and locations of support a set of operations where EDATA is used as transmit and receive memory are fully definable using both an operand and a data destination. Failure to the pointers in the Ethernet SFR space. The organiza- observe these restrictions will result in a corrupted read tion of the memory space and the relationships of the or write. Also, due to the read-modify-write architecture pointers are shown in Figure19-5. of the processor core, single-cycle instructions, which write to the EDATA register, will have a side effect of The buffer is always accessible through the EDATA and automatically incrementing the ERDPT registers when Ethernet Pointer SFRs, regardless of whether or not the AUTOINC is set. Using double-cycle MOVFF, MOVSF Ethernet module is enabled. This makes the buffer and MOVSS instructions to write to EDATA will not affect potentially useful for applications requiring large amounts the Read Pointer. See the following note for examples. of RAM and that do not require Ethernet communication. In these instances, disabling the Ethernet module Note: Any single instruction that performs both a reduces overall power usage but does not prevent buffer read and write to the EDATA SFR register access. will result in a corrupted operation. Unsupported examples: 19.2.1.1 Reading and Writing to the Buffer INCF EDATA, F The Ethernet buffer contents are accessed through the XORWF EDATA, F EDATA register, which acts as a window from the MOVFF EDATA, EDATA microcontroller data bus into the buffer. The location of MOVFF INDF0, EDATA; (FSR0 = F61h) that window is determined by either the ERDPT or Instructions that only perform one read or EWRPT Pointers, depending on the operation being one write are permitted. performed. For example, writing to EDATA causes a Supported examples: write to the Ethernet buffer at the address currently INCF EDATA, W indicated by the EWRPT register pair. Similarly, moving MOVF EDATA, W the contents of EDATA to another register actually MOVFF INDF0, EDATA; (FSR0 != F61h) moves the buffer contents at the address indicated by Single-cycle, write-only instructions, while the ERDPT Pointer. valid, will have a side effect of also incre- When the AUTOINC bit (ECON2<7>) is set, the asso- menting the ERDPT registers when ciated Read or Write Pointer increments by one AUTOINC is enabled. address following each read or write operation. This Examples incrementing both ERDPT and eliminates the need to constantly update a pointer after EWRPT: each read or write, simplifying multiple sequential CLRF EDATA operations. By default, the AUTOINC bit is set. SETF EDATA While sequentially reading from the receive buffer, a MOVWF EDATA wrapping condition will occur at the end of the receive buffer. A read of EDATA, from the address programmed  2011 Microchip Technology Inc. DS39762F-page 223

PIC18F97J60 FAMILY FIGURE 19-5: ETHERNET BUFFER ORGANIZATION Transmit Buffer Start 0000h (ETXSTH:ETXSTL) Buffer Write Pointer AAh Write Buffer Data (EWRPTH:EWRPTL) (data AAh moved to EDATA) Transmit Transmit Buffer End Buffer (ETXNDH:ETXNDL) Receive Buffer Start (ERXSTH:ERXSTL) Receive Buffer (Circular FIFO) Buffer Read Pointer 55h Read Buffer Data (ERDPTH:ERDPTL) (data 55h moved out of EDATA) Receive Buffer End 1FFFh (ERXNDH:ERXNDL) DS39762F-page 224  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.2.1.2 Receive Buffer the read-only ERXWRPTH:ERXWRPTL registers are updated with the Internal Pointer’s value. Thus, the The receive buffer constitutes a circular FIFO buffer ERXWRPT registers define the general area in the managed by hardware. The register pairs, receive buffer where data is currently being written. This ERXSTH:ERXSTL and ERXNDH:ERXNDL, serve as makes it useful for determining how much free space is pointers to define the buffer’s size and location within available within the FIFO. the memory. The byte pointed to by the ERXST pair and the byte pointed to by the ERXND pair are both The ERXRDPT registers define a location within the included in the FIFO buffer. FIFO where the receive hardware is forbidden to write to. In normal operation, the receive hardware will write data As bytes of data are received from the Ethernet up to, but not including, the memory pointed to by the interface, they are written into the receive buffer ERXRDPT registers. If the FIFO fills up with data and sequentially. However, after the memory pointed to by new data continues to arrive, the hardware will not over- the ERXND Pointers is written to, the hardware will write the previously received data. Instead, the incoming automatically write the next byte of received data to the data will be thrown away and the old data will be memory pointed to by the ERXST pair. As a result, the preserved. In order to continuously receive new data, the receive hardware will never write outside the application must periodically advance this pointer when- boundaries of the FIFO. ever it finishes processing some, or all, of the old The user may program the ERXST and ERXND received data. Pointers while the receive logic is disabled. The point- An example of how the Receive Buffer Pointers and ers must not be modified while the receive logic is packet data are related in the circular buffer scheme is enabled (ERXEN (ECON1<2>) is set). shown in Figure19-6. Note that while four packets are The buffer hardware uses an Internal Pointer (not shown in this example, the actual number of packets mapped to any user-accessible registers) to determine may be greater or lesser. where unvalidated incoming data is to be written. When a packet has been completely received and validated, FIGURE 19-6: CIRCULAR FIFO BUFFER AND THE RELATIONSHIPS OF THE POINTERS ERXST ERXND ERXRDPT: Sets boundary that Internal PB Write Pointer cannot advance beyond. Prevents Internal Write Pointer from moving into Packet 1’s data space. Internal Write Hardware Pointer points to the buffer location being written ERDPT: Unused Buffer (packet data is still (may contain old data) being received). Data being read Packet 1 out to application. (being processed by application) PB Packet 4 (currently being Packet 2 received) ERXWRPT: Shows the end of the last complete Packet 3 received packet. PB PB Direction of reading and writing data (lower to higher buffer addresses). PB: Packet Boundary, as defined by the Next Packet Pointers that precede each packet.  2011 Microchip Technology Inc. DS39762F-page 225

PIC18F97J60 FAMILY 19.2.1.3 Transmit Buffer ing EDATA). The arbiter gives the EDATA register accesses first priority, while all remaining bandwidth is Any space within the 8-Kbyte memory which is not shared between the RX and TX/DMA blocks. programmed as part of the receive FIFO buffer is consid- ered to be the transmit buffer. The responsibility of With arbitration, bandwidth limitations require that managing where packets are located in the transmit buf- some care be taken in balancing the needs of the mod- fer belongs to the application. Whenever the application ule’s hardware with that of the application. Accessing decides to transmit a packet, the ETXST and ETXND the EDATA register too often may result in the RX or TX Pointers are programmed with addresses specifying blocks causing a buffer overrun or underrun, respec- where, within the transmit buffer, the particular packet to tively. If such a memory access failure occurs, the transmit is located. The hardware does not check that the BUFER bit (ESTAT<6>), and either the TXERIF or start and end addresses do not overlap with the receive RXERIF interrupt flag, becomes set, and a TX or RX buffer. To prevent buffer corruption, the firmware must not interrupt occurs (if enabled). In either case, the current transmit a packet while the ETXST and ETXND Pointers packet will be lost or aborted. are overlapping the receive buffer, or while the ETXND To eliminate the risk of lost packets, run the microcon- Pointers are too close to the receive buffer. See troller core at higher speeds. Following the arbitration Section19.5.2 “Transmitting Packets” for more restrictions, shown in Table19-2, will prevent memory information. access failures from occurring. Also, avoid using seg- ments of application code which perform back-to-back 19.2.1.4 Buffer Arbiter and Access Arbitration accesses of the EDATA register. Instead, insert one or The Ethernet buffer is clocked at one-half of the micro- more instructions (including NOP instructions) between controller clock rate. Varying amounts of memory each read or write to EDATA. access bandwidth are available depending on the clock speed. The total bandwidth available, in bytes per sec- 19.2.1.5 DMA Access to the Buffer ond, is equal to twice the instruction rate (2 * FCY or The integrated DMA controller must read from the FOSC/2). For example, at a system clock speed of buffer when calculating a checksum, and it must read 41.667MHz, the total available memory bandwidth that and write to the buffer when copying memory. The DMA is available is 20.834Mbyte/s. At an Ethernet signaling follows the same wrapping rules as previously rate of 10Mbit/s, the Ethernet RX engine requires described for the receive buffer. While it sequentially 1.25Mbyte/s of buffer memory bandwidth to operate reads, it will be subject to a wrapping condition at the without causing an overrun. If Full-Duplex mode is end of the receive buffer. All writes it does will not be used, an additional 1.25Mbyte/s is required to allow for subject to any wrapping conditions. See Section19.9 simultaneous RX and TX activity. “Direct Memory Access Controller” for more Because of the finite available memory bandwidth, a information. three-channel arbiter is used to allocate bandwidth between the RX engine, the TX and DMA engines, and the microcontroller’s CPU (i.e., the application access- TABLE 19-2: BUFFER ARBITRATION RESTRICTIONS VS. CLOCK SPEED Available Bandwidth (Mbyte/s) FOSC FCY Application Restrictions (MHz) (MHz) to Prevent Underrun/Overrun Total After RX After TX 41.667 10.42 20.83 19.58 18.33 Access EDATA no more than once every 2 TCY 31.250 7.81 15.63 14.38 13.13 Access EDATA no more than once every 2 TCY 25.000 6.25 12.50 11.25 10.00 Access EDATA no more than once every 2 TCY 20.833 5.21 10.42 9.17 7.92 Access EDATA no more than once every 2 TCY 13.889 3.47 6.94 5.69 4.44 Access EDATA no more than once every 2 TCY 12.500 3.13 6.25 5.00 3.75 Access EDATA no more than once every 2 TCY 8.333 2.08 4.17 2.92 1.67 Access EDATA no more than once every 3 TCY 6.250 1.56 3.13 1.88 0.63 Access EDATA no more than once every 5 TCY 4.167 1.04 2.08 0.83 < 0 Do not use DMA, do not use full duplex, access EDATA no more than once every 3 TCY 2.778 0.69 1.39 0.14 < 0 Do not use DMA, do not use full duplex, access EDATA no more than once every 10 TCY DS39762F-page 226  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.2.2 SFRs AND THE ETHERNET MODULE Many of the Ethernet SFRs in Bank 14 serve as pointer registers to indicate addresses within the dedicated Like other peripherals, direct control of the Ethernet Ethernet buffer for storage and retrieval of packet data. module is accomplished through a set of SFRs. Others store information for packet pattern masks or Because of their large number, the majority of these checksum operations. Several are used for controlling registers is located in the bottom half of Bank 14 of the overall module operations, as well as specific MAC and microcontroller’s data memory space. PHY functions. Five key SFRs for the Ethernet module are located in the microcontroller’s regular SFR area in Bank 15, 19.2.3 ETHERNET CONTROL REGISTERS where fast access is possible. They are: The ECON1 register (Register19-1) is used to control • ECON1 the main functions of the module. Receive enable, trans- • EDATA mit request and DMA control bits are all located here. The ECON2 register (Register19-2) is used to control • EIR other top level functions of the module. The ESTAT • The Ethernet Buffer Read Pointer Pair (ERDPTH register (Register19-3) is used to report the high-level and ERDPTL) status of the module and Ethernet communications. ECON1 is described along with other Ethernet control The Ethernet SFRs with the ‘E’ prefix are always registers in the following section. EDATA and accessible, regardless of whether or not the module is ERDPTH:ERDPTL are the Ethernet Data Buffer enabled. registers and its pointers during read operations (see Section19.2.1 “Ethernet Buffer and Buffer Pointer Registers”). EIR is part of the Ethernet interrupt structure and is described in Section19.3 “Ethernet Interrupts”. REGISTER 19-1: ECON1: ETHERNET CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 TXRST RXRST DMAST CSUMEN TXRTS RXEN — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TXRST: Transmit Logic Reset bit 1 = Transmit logic is held in Reset 0 = Normal operation bit 6 RXRST: Receive Logic Reset bit 1 = Receive logic is held in Reset 0 = Normal operation bit 5 DMAST: DMA Start and Busy Status bit 1 = DMA copy or checksum operation is in progress (set by software, cleared by hardware or software) 0 = DMA hardware is Idle bit 4 CSUMEN: DMA Checksum Enable bit 1 = DMA hardware calculates checksums 0 = DMA hardware copies buffer memory bit 3 TXRTS: Transmit Request to Send bit 1 = The transmit logic is attempting to transmit a packet (set by software, cleared by hardware or software) 0 = The transmit logic is Idle bit 2 RXEN: Receive Enable bit 1 = Packets which pass the current filter configuration will be written into the receive buffer 0 = All packets received will be discarded by hardware bit 1-0 Unimplemented: Read as ‘0’  2011 Microchip Technology Inc. DS39762F-page 227

PIC18F97J60 FAMILY REGISTER 19-2: ECON2: ETHERNET CONTROL REGISTER 2 R/W-1 R/W-0(1) R/W-0 U-0 U-0 U-0 U-0 U-0 AUTOINC PKTDEC ETHEN — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 AUTOINC: Automatic Buffer Pointer Increment Enable bit 1 = Automatically increment ERDPT or EWRPT registers on reading from, or writing to, EDATA 0 = Do not automatically change ERDPT and EWRPT registers after EDATA is accessed bit 6 PKTDEC: Packet Decrement bit(1) 1 = Decrement the EPKTCNT register by one 0 = Leave EPKTCNT unchanged bit 5 ETHEN: Ethernet Module Enable bit 1 = Ethernet module is enabled 0 = Ethernet module is disabled bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared once it is set. REGISTER 19-3: ESTAT: ETHERNET STATUS REGISTER U-0 R/C-0 U-0 R/C-0 U-0 R-0 R/C-0 R-0 — BUFER — r — RXBUSY TXABRT PHYRDY bit 7 bit 0 Legend: r = Reserved bit R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 BUFER: Ethernet Buffer Error Status bit 1 = An Ethernet read or write has generated a buffer error (overrun or underrun) 0 = No buffer error has occurred bit 5 Unimplemented: Read as ‘0’ bit 4 Reserved: Write as ‘0’ bit 3 Unimplemented: Read as ‘0’ bit 2 RXBUSY: Receive Busy bit 1 = Receive logic is receiving a data packet 0 = Receive logic is Idle bit 1 TXABRT: Transmit Abort Error bit 1 = The transmit request was aborted 0 = No transmit abort error bit 0 PHYRDY: Ethernet PHY Clock Ready bit 1 = Ethernet PHY start-up timer has expired; PHY is ready 0 = Ethernet PHY start-up timer is still counting; PHY is not ready DS39762F-page 228  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.2.4 MAC AND MII REGISTERS Note1: Do not access the MAC and MII SFRs These SFRs are used to control the operations of the unless the Ethernet module is enabled MAC, and through the MIIM, the PHY. The MAC and (ETHEN = 1). MII registers occupy data addresses, E80h-E85h, 2: Back-to-back accesses of MAC or MII E8Ah and EA0h through EB9h. registers are not supported. Between any Although MAC and MII registers appear in the general instruction which addresses a MAC or MII memory map of the microcontroller, these registers are register, at least one NOP or other embedded inside the MAC module. Host interface logic instruction must be executed. translates the microcontroller data/address bus data to The three MACON registers control specific MAC oper- be able to access these registers. The host interface ations and packet configuration operations. They are logic imposes restrictions on how firmware is able to shown in Register19-4 through Register19-6. access the MAC and MII SFRs. See the following notes. The MII registers are used to control the MIIM interface and serve as the communication channel with the PHY registers. They are shown in Register19-7 and Register19-8. REGISTER 19-4: MACON1: MAC CONTROL REGISTER 1 U-0 U-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — r TXPAUS RXPAUS PASSALL MARXEN bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 Reserved: Do not use bit 3 TXPAUS: Pause Control Frame Transmission Enable bit 1 = Allow the MAC to transmit pause control frames (needed for flow control in full duplex) 0 = Disallow pause frame transmissions bit 2 RXPAUS: Pause Control Frame Reception Enable bit 1 = Inhibit transmissions when pause control frames are received (normal operation) 0 = Ignore pause control frames which are received bit 1 PASSALL: Pass All Received Frames Enable bit 1 = Control frames received by the MAC will be written into the receive buffer if not filtered out 0 = Control frames will be discarded after being processed by the MAC (normal operation) bit 0 MARXEN: MAC Receive Enable bit 1 = Enable packets to be received by the MAC 0 = Disable packet reception  2011 Microchip Technology Inc. DS39762F-page 229

PIC18F97J60 FAMILY REGISTER 19-5: MACON3: MAC CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 PADCFG<2:0>: Automatic Pad and CRC Configuration bits 111 = All short frames are zero-padded to 64 bytes and a valid CRC will then be appended 110 = No automatic padding of short frames 101 = MAC automatically detects VLAN protocol frames which have a 8100h type field and auto- matically pad to 64 bytes. If the frame is not a VLAN frame, it is padded to 60 bytes. After padding, a valid CRC is appended. 100 = No automatic padding of short frames 011 = All short frames are zero-padded to 64 bytes and a valid CRC is appended 010 = No automatic padding of short frames 001 = All short frames are zero-padded to 60 bytes and a valid CRC is appended 000 = No automatic padding of short frames bit 4 TXCRCEN: Transmit CRC Enable bit 1 = MAC appends a valid CRC to all frames transmitted, regardless of the PADCFG<2:0> bits. TXCRCEN must be set if the PADCFG bits specify that a valid CRC is appended. 0 = MAC does not append a CRC. The last 4 bytes are checked and if it is an invalid CRC, it is reported in the transmit status vector. bit 3 PHDREN: Proprietary Header Enable bit 1 = Frames presented to the MAC contain a 4-byte proprietary header which is not used when calculating the CRC 0 = No proprietary header is present; the CRC covers all data (normal operation) bit 2 HFRMEN: Huge Frame Enable bit 1 = Jumbo frames and frames of any illegal size are allowed to be transmitted and received 0 = Frames bigger than MAMXFL are truncated when transmitted or received bit 1 FRMLNEN: Frame Length Checking Enable bit 1 = The type/length field of transmitted and received frames is checked. If it represents a length, the frame size is compared and mismatches are reported in the transmit/receive status vector. 0 = Frame lengths are not compared with the type/length field bit 0 FULDPX: MAC Full-Duplex Enable bit 1 = MAC operates in Full-Duplex mode; application must also set PDPXMD (PHCON1<8>) 0 = MAC operates in Half-Duplex mode; application must also clear PDPXMD DS39762F-page 230  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 19-6: MACON4: MAC CONTROL REGISTER 4 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R-0 R-0 — DEFER r r — — r r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 DEFER: Defer Transmission Enable bit (applies to half duplex only) 1 = When the medium is occupied, the MAC waits indefinitely for it to become free when attempting to transmit (use this setting for IEE 802.3 compliance) 0 = When the medium is occupied, the MAC aborts the transmission after the excessive deferral limit is reached bit 5-4 Reserved: Maintain as ‘0’ bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 Reserved: Maintain as ‘0’ REGISTER 19-7: MICMD: MII COMMAND REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — MIISCAN MIIRD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 MIISCAN: MII Scan Enable bit 1 = PHY register at MIREGADR is continuously read and the data is placed in the MIRD registers 0 = No MII Management scan operation is in progress bit 0 MIIRD: MII Read Enable bit 1 = PHY register at MIREGADR is read once and the data is placed in the MIRD registers 0 = No MII Management read operation is in progress  2011 Microchip Technology Inc. DS39762F-page 231

PIC18F97J60 FAMILY REGISTER 19-8: MISTAT: MII STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — r NVALID SCAN BUSY bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 Reserved: Do not use bit 2 NVALID: MII Management Read Data Not Valid bit 1 = The contents of the MIRD registers are not valid yet 0 = The MII Management read cycle has completed and the MIRD registers have been updated bit 1 SCAN: MII Management Scan Operation bit 1 = MII Management scan operation is in progress 0 = No MII Management scan operation is in progress bit 0 BUSY: MII Management Busy bit 1 = A PHY register is currently being read, or written to. For internal synchronization, the hardware will delay setting this bit for two TCY following a firmware command, which sets the MIISCAN or MIIRD bits, or writes to the MIWRH register. 0 = The MII Management interface is Idle 19.2.5 PHY REGISTERS The PHSTAT1 register (Register19-10) contains the LLSTAT bit. The bit clears and latches low if the physical The PHY registers provide configuration and control of layer link has gone down since the last read of the the PHY module, as well as status information about its register. The application can periodically poll LLSTAT to operation. All PHY registers are 16 bits in width. determine exactly when the link fails. It may be PHY registers are accessed with a 5-bit address, for a particularly useful if the link change interrupt is not used. total of 32 possible registers; of these, only 7 addresses The PHSTAT2 register (Register19-12) contains status are implemented. The implemented registers are listed bits which report if the PHY module is linked to the in Table19-3. The main PHY Control registers are network and whether or not it is transmitting or receiving. described in Register19-9 through Register19-13. The other PHY Control and Status registers are described 19.2.5.2 Accessing PHY Registers later in this chapter. As already mentioned, the PHY registers exist in a Unimplemented registers must never be written to. different memory space and are not directly accessible Reading these locations will return indeterminate data. by the microcontroller. Instead, they are addressed Within implemented registers, all reserved bit locations through a special set of MII registers in the Ethernet that are listed as writable must always be written with SFR bank that implement a Media Independent the value provided in the register description. When Interface Management (MIIM). read, these reserved bits can be ignored. Access is similar to that of the Ethernet buffer, but uses Thy PHY registers are only accessible through the MII separate read and write buffers (MIRDH:MIRDL and Management interface. They must not be read or MIWRH:MIWRL) and a 5-bit address register written to until the PHY start-up timer has expired and (MIREGADR). In addition, the MICMD and MISTAT the PHYRDY bit (ESTAT<0>) is set. registers are used to control read and write operations. 19.2.5.1 PHSTAT Registers The PHSTAT1 and PHSTAT2 registers contain read-only bits that show the current status of the PHY module’s operations, particularly the conditions of the communications link to the rest of the network. DS39762F-page 232  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY To read from a PHY register: The MAC can also be configured to perform automatic back-to-back read operations on a PHY register. To 1. Write the address of the PHY register to be read perform this scan operation: into the MIREGADR register. 2. Set the MIIRD bit (MICMD<0>). The read 1. Write the address of the PHY register to be operation begins and the BUSY bit (MISTAT<0>) scanned into the MIREGADR register. is set after two TCY. 2. Set the MIISCAN bit (MICMD<1>). The scan 3. Wait 10.24 s, then poll the BUSY bit to be operation begins and the BUSY bit is set after certain that the operation is complete. When the two TCY. MAC has obtained the register contents, the After MIISCAN is set, the NVALID (MISTAT<2>), SCAN BUSY bit will clear itself. While BUSY is set, the and BUSY bits are also set. The first read operation will user application should not start any MIISCAN complete after 10.24 s. Subsequent reads will be operations or write to the MIWRH register. done and the MIRDL and MIRDH registers will be con- 4. Clear the MIIRD bit. tinuously updated automatically at the same interval 5. Read the entire 16 bits of the PHY register from until the operation is cancelled. The NVALID bit may be the MIRDL and MIRDH registers. polled to determine when the first read operation is complete. To write to a PHY register: There is no status information which can be used to 1. Write the address of the PHY register to be determine when the MIRD registers are updated. Since written into the MIREGADR register. only one MII register can be read at a time, it must not 2. Write the lower 8 bits of data to write into the be assumed that the values of MIRDL and MIRDH MIWRL register. were read from the PHY at exactly the same time 3. Write the upper 8 bits of data to write into the during a scan operation. MIWRH register. Writing to this register auto- MIISCAN should remain set as long as the scan matically begins the MII transaction, so it must operation is desired. The BUSY and SCAN bits are be written to after MIWRL. The BUSY bit is set automatically cleared after MIISCAN is set to ‘0’ and automatically after two TCY. the last read sequence is completed. MIREGADR The PHY register is written after the MII operation should not be updated while MIISCAN is set. completes, which takes 10.24 s. When the write Starting new PHY operations, such as a read operation operation has completed, the BUSY bit will clear itself. or writing to the MIWRH register, must not be done The application should not start any MII scan or read while a scan is underway. The operation can be operations while busy. cancelled by clearing the MIISCAN bit and then polling When a PHY register is written to, the entire 16 bits are the BUSY bit. New operations may be started after the written at once; selective bit and/or byte writes are not BUSY bit is cleared. implemented. If it is necessary to reprogram only select bits in the register, the controller must first read the PHY register, modify the resulting data and then write the data back to the PHY register.  2011 Microchip Technology Inc. DS39762F-page 233

D TABLE 19-3: PIC18F97J60 FAMILY PHY REGISTER SUMMARY P S 3 9 Addr Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values I 7 C 6 2F 00h PHCON1 r r — — r r — PDPXMD r — — — — — — — 00-- 00-0 0--- ---- -pa 01h PHSTAT1 — — — r r — — — — — — — — LLSTAT r — ---1 1--- ---- -00- 1 g 8 e 2 10h PHCON2 — FRCLNK r r r r r HDLDIS r r r RXAPDIS r r r r -000 0000 0000 0000 F 34 11h PHSTAT2 — — TXSTAT RXSTAT COLSTAT LSTAT r — — — r — — — — — --00 00x- --0- ---- 9 12h PHIE r r r r r r r r r r r PLNKIE r r PGEIE r xxxx xxxx xx00 xx00 7 13h PHIR r r r r r r r r r r r PLNKIF r PGIF r r xxxx xxxx xx00 00x0 J 14h PHLCON r r r r LACFG3 LACFG2 LACFG1 LACFG0 LBCFG3 LBCFG2 LBCFG1 LBCFG0 LFRQ1 LFRQ0 STRCH r 0011 0100 0010 001x 6 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’, r = reserved, do not modify. Shaded cells are unimplemented, read as ‘0’. 0 F A M I L Y  2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

PIC18F97J60 FAMILY REGISTER 19-9: PHCON1: PHY CONTROL REGISTER 1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 r r — — r r — PDPXMD bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 r — — — — — — — bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Reserved: Write as ‘0’ bit 13-12 Unimplemented: Read as ‘0’ bit 11-10 Reserved: Write as ‘0’ bit 9 Unimplemented: Read as ‘0’ bit 8 PDPXMD: PHY Duplex Mode bit 1 = PHY operates in Full-Duplex mode; application must also set FULDPX (MACON3<0>) 0 = PHY operates in Half-Duplex mode, application must also clear FULDP bit 7 Reserved: Maintain as ‘0’ bit 6-0 Unimplemented: Read as ‘0’ REGISTER 19-10: PHSTAT1: PHYSICAL LAYER STATUS REGISTER 1 U-0 U-0 U-0 R-1 R-1 U-0 U-0 U-0 — — — r r — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/LL-0 R/LH-0 U-0 — — — — — LLSTAT r — bit 7 bit 0 Legend: ‘1’ = Bit is set r = Reserved bit R = Read-only bit ‘0’ = Bit is cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR R/L = Read-Only Latch bit LL = Latches Low bit LH = Latches High bit bit 15-13 Unimplemented: Read as ‘0’ bit 12-11 Reserved: Read as ‘1’ bit 10-3 Unimplemented: Read as ‘0’ bit 2 LLSTAT: PHY Latching Link Status bit 1 = Link is up and has been up continously since PHSTAT1 was last read 0 = Link is down or was down for a period since PHSTAT1 was last read bit 1 Reserved: Ignore on read bit 0 Unimplemented: Read as ‘0’  2011 Microchip Technology Inc. DS39762F-page 235

PIC18F97J60 FAMILY REGISTER 19-11: PHCON2: PHY CONTROL REGISTER 2 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FRCLNK r r r r r HDLDIS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r r RXAPDIS r r r r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 FRCLNK: PHY Force Linkup bit 1 = Force linkup even when no link partner is detected (transmission is always allowed) 0 = Normal operation (PHY blocks transmission attempts unless a link partner is attached) bit 13-9 Reserved: Write as ‘0’ bit 8 HDLDIS: PHY Half-Duplex Loopback Disable bit 1 = Normal PHY operation 0 = Reserved bit 7-5 Reserved: Write as ‘0’ bit 4 RXAPDIS: RX+/RX- Operating mode bit 1 = Normal operation 0 = Reserved bit 3-0 Reserved: Write as ‘0’ Note: Improper Ethernet operation may result if HDLDIS or RXAPDIS is cleared, which is the Reset default. Always initialize these bits set before using the Ethernet module. DS39762F-page 236  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY R EGISTER 19-12: PHSTAT2: PHYSICAL LAYER STATUS REGISTER 2 U-0 U-0 R-0 R-0 R-0 R-0 R-x U-0 — — TXSTAT RXSTAT COLSTAT LSTAT r — bit 15 bit 8 U-0 U-0 R-0 U-0 U-0 U-0 U-0 U-0 — — r — — — — — bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 TXSTAT: PHY Transmit Status bit 1 = PHY is transmitting data 0 = PHY is not transmitting data bit 12 RXSTAT: PHY Receive Status bit 1 = PHY is receiving data 0 = PHY is not receiving data bit 11 COLSTAT: PHY Collision Status bit 1 = A collision is occuring (PHY is both transmitting and receiving while in Half-Duplex mode) 0 = A collision is not occuring bit 10 LSTAT: PHY Collision Status bit 1 = Link is up 0 = Link is down bit 9 Reserved: Ignore on read bit 8-6 Unimplemented: Read as ‘0’ bit 5 Reserved: Ignore on read bit 4-0 Unimplemented: Read as ‘0’  2011 Microchip Technology Inc. DS39762F-page 237

PIC18F97J60 FAMILY REGISTER 19-13: PHLCON: PHY MODULE LED CONTROL REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 r r r r LACFG3 LACFG2 LACFG1 LACFG0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-x LBCFG3 LBCFG2 LBCFG1 LBCFG0 LFRQ1 LFRQ0 STRCH r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Reserved: Write as ‘0’ bit 13-12 Reserved: Write as ‘1’ bit 11-8 LACFG<3:0>: LEDA Configuration bits 0000 = Reserved 0001 = Display transmit activity (stretchable) 0010 = Display receive activity (stretchable) 0011 = Display collision activity (stretchable) 0100 = Display link status 0101 = Display duplex status 0110 = Reserved 0111 = Display transmit and receive activity (stretchable) 1000 = On 1001 = Off 1010 = Blink fast 1011 = Blink slow 1100 = Display link status and receive activity (always stretched) 1101 = Display link status and transmit/receive activity (always stretched) 111x = Reserved bit 7-4 LBCFG<3:0>: LEDB Configuration bits 0000 = Reserved 0001 = Display transmit activity (stretchable) 0010 = Display receive activity (stretchable) 0011 = Display collision activity (stretchable) 0100 = Display link status 0101 = Display duplex status 0110 = Reserved 0111 = Display transmit and receive activity (stretchable) 1000 = On 1001 = Off 1010 = Blink fast 1011 = Blink slow 1100 = Display link status and receive activity (always stretched) 1101 = Display link status and transmit/receive activity (always stretched) 111x = Reserved bit 3-2 LFRQ<1:0>: LED Pulse Stretch Time Configuration bits (see Table19-1) 11 = Reserved 10 = Stretch LED events by TLSTRCH 01 = Stretch LED events by TMSTRCH 00 = Stretch LED events by TNSTRCH bit 1 STRCH: LED Pulse Stretching Enable bit 1 = Stretchable LED events will cause lengthened LED pulses based on LFRQ<1:0> configuration 0 = Stretchable LED events will only be displayed while they are occurring bit 0 Reserved: Write as ‘0’ DS39762F-page 238  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.3 Ethernet Interrupts Note: Except for the LINKIF interrupt flag, The Ethernet module can generate multiple interrupt interrupt flag bits are set when an interrupt conditions. To accommodate all of these sources, the condition occurs, regardless of the state of module has its own interrupt logic structure, similar to its corresponding enable bit or the associ- that of the microcontroller. Separate sets of registers ated global enable bit. User software are used to enable and flag different interrupt should ensure the appropriate interrupt conditions. flag bits are clear prior to enabling an interrupt. This feature allows for software The EIE register contains the individual interrupt polling. enable bits for each source, while the EIR register con- tains the corresponding interrupt flag bits. When an 19.3.1 CONTROL INTERRUPT (ETHIE) interrupt occurs, the interrupt flag is set. If the interrupt is enabled in the EIE register, and the corresponding The four registers associated with the control interrupts ETHIE Global Interrupt Enable bit is set, the micro- are shown in Register19-14 through Register19-17. controller’s master Ethernet Interrupt Flag (ETHIF) is set, as appropriate (see Figure19-7). FIGURE 19-7: ETHERNET MODULE INTERRUPT LOGIC PKTIF PKTIE DMAIF PLNKIF PGIF DMAIE LINKIF PLNKIE PGEIE LINKIE Set ETHIF TXIF TXIE ETHIE TXERIF TXERIE RXERIF RXERIE  2011 Microchip Technology Inc. DS39762F-page 239

PIC18F97J60 FAMILY REGISTER 19-14: EIE: ETHERNET INTERRUPT ENABLE REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — PKTIE DMAIE LINKIE TXIE — TXERIE RXERIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PKTIE: Receive Packet Pending Interrupt Enable bit 1 = Enable receive packet pending interrupt 0 = Disable receive packet pending interrupt bit 5 DMAIE: DMA Interrupt Enable bit 1 = Enable DMA interrupt 0 = Disable DMA interrupt bit 4 LINKIE: Link Status Change Interrupt Enable bit 1 = Enable link change interrupt from the PHY 0 = Disable link change interrupt bit 3 TXIE: Transmit Enable bit 1 = Enable transmit interrupt 0 = Disable transmit interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 TXERIE: Transmit Error Interrupt Enable bit 1 = Enable transmit error interrupt 0 = Disable transmit error interrupt bit 0 RXERIE: Receive Error Interrupt Enable bit 1 = Enable receive error interrupt 0 = Disable receive error interrupt DS39762F-page 240  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 19-15: EIR: ETHERNET INTERRUPT REQUEST (FLAG) REGISTER U-0 R-0 R/C-0 R-0 R/C-0 U-0 R/C-0 R/C-0 — PKTIF DMAIF LINKIF TXIF — TXERIF RXERIF bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PKTIF: Receive Packet Pending Interrupt Flag bit 1 = Receive buffer contains one or more unprocessed packets; cleared only when EPKTCNT is decremented to 0 by setting PKTDEC (ECON2<6>) 0 = Receive buffer is empty bit 5 DMAIF: DMA Interrupt Flag bit 1 = DMA copy or checksum calculation has completed 0 = No DMA interrupt is pending bit 4 LINKIF: Link Change Interrupt Flag bit 1 = PHY reports that the link status has changed; read PHIR register to clear 0 = Link status has not changed bit 3 TXIF: Transmit Interrupt Flag bit 1 = Transmit request has ended 0 = No transmit interrupt is pending bit 2 Unimplemented: Read as ‘0’ bit 1 TXERIF: Transmit Error Interrupt Flag bit 1 = A transmit error has occurred 0 = No transmit error has occurred bit 0 RXERIF: Receive Error Interrupt Flag bit 1 = A packet was aborted because there is insufficient buffer space, or a buffer overrun has occurred 0 = No receive error interrupt is pending  2011 Microchip Technology Inc. DS39762F-page 241

PIC18F97J60 FAMILY R EGISTER 19-16: PHIE: PHY INTERRUPT ENABLE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 r r r r r r r r bit 15 bit 8 R-0 R-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 r r r PLNKIE r r PGEIE r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Reserved: Write as ‘0’, ignore on read bit 5 Reserved: Maintain as ‘0’ bit 4 PLNKIE: PHY Link Change Interrupt Enable bit 1 = PHY link change interrupt is enabled 0 = PHY link change interrupt is disabled bit 3-2 Reserved: Write as ‘0’, ignore on read bit 1 PGEIE: PHY Global Interrupt Enable bit 1 = PHY interrupts are enabled 0 = PHY interrupts are disabled bit 0 Reserved: Maintain as ‘0’ REGISTER 19-17: PHIR: PHY INTERRUPT REQUEST (FLAG) REGISTER R-x R-x R-x R-x R-x R-x R-x R-x r r r r r r r r bit 15 bit 8 R-x R-x R-0 R/SC-0 R-0 R/SC-0 R-x R-0 r r r PLNKIF r PGIF r r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit SC = Self-Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Reserved: Ignore on read bit 5 Reserved: Read as ‘0’ bit 4 PLNKIF: PHY Link Change Interrupt Flag bit 1 = PHY link status has changed since PHIR was last read; resets to ‘0’ when read 0 = PHY link status has not changed since PHIR was last read bit 3 Reserved: Read as ‘0’ bit 2 PGIF: PHY Global Interrupt Flag bit 1 = One or more enabled PHY interrupts have occurred since PHIR was last read; resets to ‘0’ when read 0 = No PHY interrupts have occurred bit 1 Reserved: Ignore on read bit 0 Reserved: Read as ‘0’ DS39762F-page 242  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.3.1.1 Receive Error Interrupt (RXERIF) 4. An attempt to transmit a packet larger than the maximum frame length, defined by the The receive error interrupt is used to indicate that a MAMXFL registers, was made without setting packet being received was aborted due to an error the HFRMEN bit (MACON3<2>) or per-packet condition. Three errors are possible: POVERRIDE and PHUGEEN bits. 1. No buffer space is available to store the 5. The Ethernet buffer did not have enough mem- incoming packet (buffer overflow); ory bandwidth to maintain the required 10Mbit/s 2. Receiving another packet would cause the transfer rate (buffer underrun). EPKTCNT counter to overflow, because it Upon any of these conditions, the TXERIF flag is set to already contains the value, 255; or ‘1’. Once set, it can only be cleared by firmware or by a 3. The Ethernet RX hardware was not allocated Reset condition. If the transmit error interrupt is enough memory bandwidth to write the enabled (TXERIE and ETHIE are both set), an Ethernet incoming data to the buffer. interrupt is generated. If the transmit error interrupt is When a packet is being received and the receive error not enabled (either TXERIE or ETHIE is cleared), the occurs, the packet being received will be aborted (per- application may poll TXERIF and take appropriate manently lost) and the RXERIF bit will be set to ‘1’. action. Once the interrupt is processed, the flag bit Once set, RXERIF can only be cleared by firmware or should be cleared. by a Reset condition. If the receive error interrupt and After a transmit abort, the TXRTS bit (ECON1<3>) will Ethernet interrupt are enabled (both RXERIE and be cleared, the TXABRT bit (ESTAT<1>) becomes set ETHIE are set), an Ethernet interrupt is generated. If and the transmit status vector will be written at the the receive error interrupt is not enabled (either ETXND registers + 1. The MAC will not automatically RXERIE or ETHIE is cleared), the application may poll attempt to retransmit the packet. The application may RXERIF and take appropriate action. wish to read the transmit status vector and BUFER bit Normally, upon the first two receive error conditions to determine the cause of the abort. After determining (buffer overflow or potential EPKTCNT overflow), the the problem and solution, the application should clear application would process any packets pending from the BUFER (if set) and TXABRT bits so that future the receive buffer, and then make additional room for aborts can be detected accurately. future packets by advancing the ERXRDPT registers In Full-Duplex mode, Conditions 4 and 5 are the only (low byte first) and decrementing the EPKTCNT regis- ones that should cause this interrupt. Condition 5 can ter. See Section19.5.3.3 “Freeing Receive Buffer be further distinguished as it also sets the BUFER bit. Space” for more information on processing packets. Collisions and other problems related to sharing the Once processed, the application should clear the network are not possible on full-duplex networks. The RXERIF bit. conditions, which cause the transmit error interrupt, The third condition (insufficient RX memory bandwidth) meet the requirements of the transmit interrupt. As a can be identified by checking if the BUFER bit result, when this interrupt occurs, TXIF will also be (ESTAT<6>) has been set. Memory access errors that simultaneously set. set BUFER are generally transient in nature, and do not require run-time resolution. Adjustments to the applica- 19.3.1.3 Transmit Interrupt (TXIF) tion and its allocation of buffer memory bandwidth may The transmit interrupt is used to indicate that the be necessary if BUFER errors are frequent or requested packet transmission has ended (the TXRTS persistent. bit has transitioned from ‘1’ to ‘0’). Upon transmission completion, abort, or transmission cancellation by the 19.3.1.2 Transmit Error Interrupt (TXERIF) application, the TXIF flag will be set to ‘1’. If the The transmit error interrupt is used to indicate that a application did not clear the TXRTS bit, and the transmit abort has occurred. An abort can occur TXABRT bit is not set, the packet was successfully because of any of the following conditions: transmitted. Once TXIF is set, it can only be cleared in software or by a Reset condition. If the transmit 1. More than 15 collisions occurred while attempting interrupt is enabled (TXIE and ETHIE are both set), an to transmit a given packet. interrupt is generated. If the transmit interrupt is not 2. A late collision (collision after 64 bytes of a enabled (either TXIE or ETHIE is cleared), the packet had been transmitted) has occurred. application may poll the TXIF bit and take appropriate 3. The transmission was unable to gain an oppor- action. tunity to transmit the packet because the medium was constantly occupied for too long. The deferral limit was reached and the DEFER bit (MACON4<6>) was clear.  2011 Microchip Technology Inc. DS39762F-page 243

PIC18F97J60 FAMILY 19.3.1.4 Link Change Interrupt (LINKIF) When the receive packet pending interrupt is enabled (both PKTIE and ETHIE are set), an Ethernet interrupt The LINKIF indicates that the link status has changed. is generated whenever a new packet is successfully The actual current link status can be obtained from the received and written into the receive buffer. If the LLSTAT (PHSTAT1<2>) or LSTAT (PHSTAT2<10>) bits receive packet pending interrupt is not enabled (either (see Register19-10 and Register19-12). Unlike other PKTIE or ETHIE is cleared), the user application may interrupt sources, the link status change interrupt is poll the PKTIF bit and take appropriate action. created in the integrated PHY module; additional steps must be taken to enable it. The PKTIF bit can only be cleared indirectly in software, by decrementing the EPKTCNT register to ‘0’, or by a By Reset default, LINKIF is never set for any reason. To Reset condition. See Section19.5.3 “Receiving Pack- receive it, both the PLNKIE and PGEIE bits must be ets” for more information about clearing the EPKTCNT set. When the interrupt is enabled, the LINKIF bit will register. When the last data packet in the receive buffer shadow the contents of the PGIF bit. The PHY only is processed, EPKTCNT becomes zero and the PKTIF supports one interrupt, so the PGIF bit will always be bit is automatically cleared. the same as the PLNKIF bit (when both PHY enable bits are set). 19.3.2 ETHERNET INTERRUPTS AND Once LINKIF is set, it can only be cleared in software WAKE-ON-LAN or by a Reset. If the link change interrupt is enabled The Ethernet interrupt structure implements a version (LINKIE, PLNKIE, PGEIE and ETHIE are all set), an of Wake-on-LAN, also called Remote Wake-up, using a interrupt is generated. If the link change interrupt is not Magic Packet data packet. This allows the application enabled (LINKIE, PLNKIE, PGEIE or ETHIE are to conserve power in Idle mode, and then return to cleared), the user application may poll the PLNKIF flag full-power operation only when a specific wake-up and take appropriate action. packet is received. The LINKIF bit is read-only. Because reading PHY For Remote Wake-up to work, the Ethernet module registers requires a non-negligible period of time, the must remain enabled at all times. It is also necessary to application may instead set PLNKIE and PGEIE, then configure the receive filters to select for Magic Packets. poll the LINKIF flag bit. Performing an MII read on the For more information on filter configuration, see PHIR register will clear the LINKIF, PGIF and PLNKIF Section19.8 “Receive Filters”. bits automatically, and allow for future link status change interrupts. See Section19.2.5 “PHY Registers” for To configure the microcontroller for Remote Wake-up: information on accessing the PHY registers. 1. With the Ethernet module enabled and in normal operating configuration, enable the CRC 19.3.1.5 DMA Interrupt (DMAIF) post-filter and Magic Packets filter The DMA interrupt indicates that the DMA module has (ERXFCON<5,3> = 1). completed its memory copy or checksum calculation 2. Finish processing any pending packets in the (the DMAST bit has transitioned from ‘1’ to ‘0’). Addi- Ethernet buffer. tionally, this interrupt will be caused if the application 3. Enable Ethernet interrupts at the micro- cancels a DMA operation by manually clearing the controller level (PIE2<5> = 1) and the receive DMAST bit. Once set, DMAIF can only be cleared by packet pending interrupt at the module level the firmware or by a Reset condition. If the DMA inter- (EIE<6> = 1). rupt is enabled, an Ethernet interrupt is generated. If 4. Place the microcontroller in PRI_IDLE mode (with the DMA interrupt is not enabled, the user application the primary clock source selected and may poll the DMAIF flag status and take appropriate OSCCON<7> = 1, execute the SLEEP instruction). action. Once processed, the flag bit should be cleared. In this configuration, the receipt of a Magic Packet data 19.3.1.6 Receive Packet Pending Interrupt packet will cause a receive packet pending interrupt. (PKTIF) This, in turn, will cause the microcontroller to wake-up from the interrupt. The receive packet pending interrupt is used to indicate the presence of one or more data packets in the receive buffer and to provide a notification means for the arrival of new packets. When the receive buffer has at least one packet in it, the PKTIF flag bit is set. In other words, this interrupt flag will be set any time the Ethernet Packet Count register (EPKTCNT) is non-zero. DS39762F-page 244  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.4 Module Initialization 19.4.4 WAITING FOR THE PHY START-UP TIMER Before the Ethernet module can be used to transmit and receive packets, certain device settings must be If the initialization procedure is being executed immedi- initialized. Depending on the application, some config- ately after enabling the module (setting the ETHEN bit uration options may need to be changed. Normally, to ‘1’), the PHYRDY bit should be polled to make these tasks may be accomplished once after Reset and certain that enough time (1ms) has elapsed before do not need to be changed thereafter. proceeding to modify the PHY registers. For more information on the PHY start-up timer, see Before any other configuration actions are taken, it is Section19.1.3.1 “Start-up Timer”. recommended that the module be enabled by setting the ETHEN bit (ECON2<5>). This reduces the Idle time 19.4.5 MAC INITIALIZATION SETTINGS that might otherwise result while waiting for the PHYRDY flag to become set. Several of the MAC registers require configuration during initialization. This only needs to be done once during 19.4.1 RECEIVE BUFFER initialization; the order of programming is unimportant. Before receiving any packets, the receive buffer must 1. Set the MARXEN bit (MACON1<0>) to enable be initialized by setting the ERXST and ERXND Point- the MAC to receive frames. If using full duplex, ers. All memory between and including the ERXST and most applications should also set TXPAUS and ERXND addresses will be dedicated to the receive RXPAUS to allow IEEE defined flow control to hardware. The ERXST Pointers must be programmed function. with an even address while the ERXND Pointers must 2. Configure the PADCFG<2:0>, TXCRCEN and be programmed with an odd address. FULDPX bits in the MACON3 register. Most applications should enable automatic padding to Applications expecting large amounts of data and at least 60 bytes and always append a valid frequent packet delivery may wish to allocate most of CRC. For convenience, many applications may the memory as the receive buffer. Applications that wish to set the FRMLNEN bit as well to enable may need to save older packets, or have several frame length status reporting. The FULDPX bit packets ready for transmission, should allocate less should be set if the application will be connected memory. to a full-duplex configured remote node; When programming the ERXST or ERXND Pointers, the otherwise leave it clear. ERXWRPT Pointer registers will automatically be 3. Configure the bits in MACON4. For maintaining updated with the value in the ERXST registers. The compliance with IEEE 802.3, be certain to set address in the ERXWRPT registers will be used as the the DEFER bit (MACON4<6>). starting location when the receive hardware begins 4. Program the MAMXFL registers with the maxi- writing received data. When the ERXST and ERXND mum frame length to be permitted to be received Pointers are initialized, the ERXRDPT registers should or transmitted. Normal network nodes are additionally be programmed with the value of the designed to handle packets that are 1518 bytes ERXND registers. To program the ERXRDPT registers, or less; larger packets are not supported by write to ERXRDPTL first, followed by ERXRDPTH. See IEEE 802.3. Section19.5.3.3 “Freeing Receive Buffer Space” for 5. Configure the MAC Back-to-Back Inter-Packet more information. Gap register, MABBIPG, with 15h (when Full-Duplex mode is used) or 12h (when 19.4.2 TRANSMISSION BUFFER Half-Duplex mode is used). Refer to All memory which is not used by the receive buffer is Register19-18 for a more detailed description of considered to be the transmission buffer. Data which is configuring the inter-packet gap. to be transmitted should be written into any unused 6. Configure the MAC Non Back-to-Back space. After a packet is transmitted, however, the hard- Inter-Packet Gap Low Byte register, MAIPGL, ware will write a 7-byte status vector into memory after with 12h. the last byte in the packet. Therefore, the application 7. If half duplex is used, configure the MAC Non should leave at least 7 bytes between each packet and Back-to-Back Inter-Packet Gap High Byte the beginning of the receive buffer. register, MAIPGH, with 0Ch. 8. Program the local MAC address into the 19.4.3 RECEIVE FILTERS MAADR1:MAADR6 registers. The appropriate receive filters should be enabled or disabled by writing to the ERXFCON register. See Section19.8 “Receive Filters” for information on how to configure it.  2011 Microchip Technology Inc. DS39762F-page 245

PIC18F97J60 FAMILY REGISTER 19-18: MABBIPG: MAC BACK-TO-BACK INTER-PACKET GAP REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-0 BBIPG<6:0>: Back-to-Back Inter-Packet Gap Delay Time bits When FULDPX (MACON3<0>) = 1: Nibble time offset delay between the end of one transmission and the beginning of the next in a back-to-back sequence. The register value should be programmed to the desired period in nibble times minus 3. The recommended setting is 15h which represents the minimum IEEE specified Inter-Packet Gap (IPG) of 9.6s. When FULDPX (MACON3<0>) = 0: Nibble time offset delay between the end of one transmission and the beginning of the next in a back-to-back sequence. The register value should be programmed to the desired period in nibble times minus 6. The recommended setting is 12h which represents the minimum IEEE specified Inter-Packet Gap (IPG) of 9.6s. 19.4.6 PHY INITIALIZATION SETTINGS 19.4.7 DISABLING THE ETHERNET MODULE Depending on the application, bits in three of the PHY module’s registers may also require configuration. There may be circumstances during which the Ethernet The PDPXMD bit (PHCON1<8>) controls the PHY module is not needed for prolonged periods. For half/full-duplex configuration. The application must example, in situations where the application only needs program the bit properly, along with the FULDPX bit to transmit or receive Ethernet packets on the occur- rence of a particular event. In these cases, the module (MACON3<0>). can be selectively powered down. The HDLDIS bit (PHCON2<8>) disables automatic To selectively disable the module: loopback of data. For proper operation, always set both HDLDIS and RXAPDIS (PHCON2<4>). 1. Turn off packet reception by clearing the RXEN The PHY register, PHLCON (Register19-13), controls bit. the outputs of LEDA and LEDB. If an application 2. Wait for any in-progress packets to finish being requires a LED configuration other than the default, received by polling the RXBUSY bit alter this register to match the new requirements. The (ESTAT<2>). This bit should be clear before settings for LED operation are discussed in proceeding. Section19.1.2 “LED Configuration”. 3. Wait for any current transmissions to end by confirming that the TXRTS bit (ECON1<3>) is clear. 4. Clear the ETHEN bit. This removes power and clock sources from the module, and makes the PHY registers inaccessible. The PHYRDY bit is also cleared automatically. DS39762F-page 246  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.5 Transmitting and Receiving Data Ethernet medium, a 7-byte preamble field and Start-of-Frame (SOF) delimiter byte are appended to The Ethernet protocol (IEEE Standard 802.3) provides the beginning of the Ethernet packet. Thus, traffic seen an extremely detailed description of the 10 Mbps, on the twisted-pair cabling will appear as shown in frame-based serial communications system. Before Figure19-8. discussing the actual use of the Ethernet module, a brief review of the structure of a typical Ethernet data 19.5.1.1 Preamble/Start-of-Frame Delimiter frame may be appropriate. It is assumed that users When transmitting and receiving data with the Ethernet already have some familiarity with IEEE 802.3. Those module, the preamble and Start-of-Frame delimiter requiring more information should refer to the official bytes are automatically generated, or stripped from the standard, or other Ethernet reference texts, for a more packets, when they are transmitted or received. It can comprehensive explanation. also automatically generate CRC fields and padding as 19.5.1 PACKET FORMAT needed on transmission, and verify CRC data on reception. The user application does not need to create Normal IEEE 802.3 compliant Ethernet frames are or process these fields, or manually verify CRC data. between 64 and 1518 bytes long. They are made up of However, the padding and CRC fields are written into five or six different fields: a destination MAC address, a the receive buffer when packets arrive, so they may be source MAC address, a type/length field, data payload, evaluated by the user application as needed. an optional padding field and a Cyclic Redundancy Check (CRC). Additionally, when transmitted on the FIGURE 19-8: ETHERNET PACKET FORMAT Number Field Comments of Bytes 7 Preamble Filtered Out by the Module Start-of-Frame Delimiter 1 SFD (filtered out by the module) Destination Address, 6 DA such as Multicast, Broadcast or Unicast 6 SA Source Address 2 Type/Length Type of Packet or the Length of the Packet Used in the Calculation of the FCS Data Packet Payload 46-1500 (with optional padding) Padding 4 FCS(1) Frame Check Sequence – CRC Note 1: The FCS is transmitted starting with bit 31 and ending with bit 0.  2011 Microchip Technology Inc. DS39762F-page 247

PIC18F97J60 FAMILY 19.5.1.2 Destination Address 19.5.1.5 Data The destination address field is a 6-byte field filled with The data field is a variable length field anywhere from the MAC address of the device that the packet is 0to 1500 bytes. Larger data packets will violate Ethernet directed to. If the Least Significant bit in the first byte of standards and will be dropped by most Ethernet nodes. the MAC address is set, the address is a Multicast The Ethernet module, however, is capable of transmit- destination. For example, 01-00-00-00-F0-00 and ting and receiving larger packets when the Huge Frame 33-45-67-89-AB-CD are Multicast addresses, while Enable bit, HFRMEN, is set (MACON3<2> = 1). 00-00-00-00-F0-00 and 32-45-67-89-AB-CD are not. 19.5.1.6 Padding Packets with Multicast destination addresses are designed to arrive and be important to a selected group The padding field is a variable length field added to of Ethernet nodes. If the destination address field is the meet IEEE 802.3 specification requirements when reserved Multicast address, FF-FF-FF-FF-FF-FF, the small data payloads are used. The destination, source, packet is a Broadcast packet and it will be directed to type, data and padding of an Ethernet packet must be everyone sharing the network. If the Least Significant no smaller than 60 bytes. Adding the required 4-byte bit in the first byte of the MAC address is clear, the CRC field, packets must be no smaller than 64 bytes. If address is a Unicast address and will be designed for the data field is less than 46 bytes long, a padding field usage by only the addressed node. is required. The Ethernet module incorporates receive filters which When transmitting packets, the Ethernet module auto- can be used to discard or accept packets with matically generates zero-padding if the PADCFG<2:0> Multicast, Broadcast and/or Unicast destination bits (MACON3<7:5>) are configured for this. Otherwise, addresses. When transmitting packets, the application the user application will need to add any padding to the is responsible for writing the desired destination packet before transmitting it. The module will not prevent address into the transmit buffer. the transmission of undersized packets should the application command such an action. 19.5.1.3 Source Address When receiving packets, the module automatically The source address field is a 6-byte field filled with the rejects packets which are less than 18 bytes. All pack- MAC address of the node which created the Ethernet ets, 18 bytes and larger, will be subject to the standard packet. Users of the Ethernet module must generate a receive filtering criteria and may be accepted as normal unique MAC address for each and every traffic. Since the module only rejects packets smaller microcontroller used. than 18 bytes, it is important that the firmware check the length of every received packet and reject packets MAC addresses consist of two portions. The first three which are smaller than 64 bytes to meet IEEE 802.3 bytes are known as the Organizationally Unique Identi- specification requirements. fier (OUI). OUIs are distributed by the IEEE. The last three bytes are address bytes at the discretion of the 19.5.1.7 CRC company that purchased the OUI. The CRC field is a 4-byte field which contains an industry When transmitting packets, the assigned source MAC standard, 32-bit CRC, calculated with the data from the address must be written into the transmit buffer by the destination, source, type, data and padding fields. It pro- application. The module will not automatically transmit vides a way of detecting corrupted Ethernet frames, as the contents of the MAADR registers which are used well as junk data fragments resulting from packet for the Unicast receive filter. collisions or another host’s aborted transmissions. 19.5.1.4 Type/Length When receiving packets, the Ethernet module will check the CRC of each incoming packet. If the CRCEN bit is The type/length field is a 2-byte field which defines set, packets with invalid CRCs will automatically be dis- which protocol the following packet data belongs to. carded. If CRCEN is clear and the packet meets all other Alternately, if the field is filled with the contents of receive filtering criteria, the packet will be written into the 05DCh (1500) or any smaller number, the field is receive buffer and the application will be able to deter- considered a length field, and it specifies the amount of mine if the CRC was valid by reading the receive status non-padding data which follows in the data field. Users vector (see Section19.5.3 “Receiving Packets”). implementing proprietary networks may choose to treat this field as a length field, while applications When transmitting packets, the module automatically implementing protocols, such as the Internet Protocol generates a valid CRC and transmits it if the (IP) or Address Resolution Protocol (ARP), should PADCFG<2:0> bits are configured for this. Otherwise, program this field with the appropriate type defined by the user application must generate the CRC and place the protocol’s specification when transmitting packets. it in the transmit buffer. Given the complexity of calcu- lating a CRC, it is highly recommended to allow the module to automatically calculate and include the CRC. DS39762F-page 248  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.5.2 TRANSMITTING PACKETS In addition, the Ethernet module requires a single per-packet control byte to precede the packet for trans- The Ethernet module’s MAC will automatically mission. The control byte is organized as shown in generate the preamble and Start-of-Frame (SOF) Figure19-9. Before transmitting packets, the MAC delimiter fields when transmitting. Additionally, the registers, which alter the transmission characteristics, MAC can generate any padding (if needed) and the should be initialized as documented in Section19.4 CRC if configured to do so. The application must “Module Initialization”. generate and write all other frame fields into the buffer memory for transmission. FIGURE 19-9: FORMAT FOR PER-PACKET CONTROL BYTES — — — — PHUGEEN PPADN PCRCEN POVERRIDE bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 PHUGEEN: Per-Packet Huge Frame Enable bit When POVERRIDE = 1: 1 = The packet will be transmitted in whole 0 = The MAC will transmit up to the number of bytes specified by the MAMXFL registers. If the packet is larger than the bytes specified, it will be aborted after the MAMXFL registers specification is reached. When POVERRIDE = 0: This bit is ignored. bit 2 PPADN: Per-Packet Padding Enable bit When POVERRIDE = 1: 1 = The packet will be zero-padded to 60 bytes if it is less than 60 bytes 0 = The packet will be transmitted without adding any padding bytes When POVERRIDE = 0: This bit is ignored. bit 1 PCRCEN: Per-Packet CRC Enable bit When POVERRIDE = 1: 1 = A valid CRC will be calculated and attached to the frame 0 = No CRC will be appended. The last 4 bytes of the frame will be checked for validity as a CRC. When POVERRIDE = 0: This bit is ignored. bit 0 POVERRIDE: Per-Packet Override bit 1 = The values of PCRCEN, PPADN and PHUGEEN will override the configuration defined by MACON3 0 = The values in MACON3 will be used to determine how the packet will be transmitted  2011 Microchip Technology Inc. DS39762F-page 249

PIC18F97J60 FAMILY An example of how the entire assembled transmit transmission engine share the same memory arbiter packet looks in memory is shown in Figure19-10. To channel. Similarly, if the DMAST bit is set after TXRTS construct and transmit a packet in this fashion: is already set, the DMA will wait until the TXRTS bit becomes clear before doing anything. 1. Set the ETXST Pointers to an appropriate unused location in the buffer. This will be the While the transmission is in progress, the ETXST and location of the per-packet control byte. In the ETXND Pointers should not be modified. If it is example, it would be 0120h. It is recommended necessary to cancel the transmission, clear the TXRTS that an even address be used for the ETXST bit. Pointers. When the packet is finished transmitting, or was 2. Using EDATA and the EWRPT registers, aborted due to an error/cancellation, several things sequentially write the packet data to the Ether- occur: net buffer. In order, write the data for the • The TXRTS bit is cleared. per-packet control byte, the destination address, the source MAC address, the type/length and • A 7-byte transmit status vector is written to the the data payload. buffer at the location pointed to by the ETXND Pointers + 1. 3. Set the ETXND Pointers to point to the last byte in the data payload. In the example, it would be • The TXIF flag is set. programmed to 0156h. • An interrupt will be generated (if enabled). 4. Clear the TXIF flag bit (EIR<3>), and set the • The ETXST and ETXND Pointers will not be TXIE (EIE<3>) and ETHIE bits to enable an modified. interrupt when done (if desired). To check if the packet was successfully transmitted, 5. Start the transmission process by setting the read the TXABRT bit. If it has been set, poll the BUFER TXRTS bit (ECON1<3>). bit in addition to the various fields in the transmit status If a DMA operation was in progress while the TXRTS bit vector to determine the cause. The transmit status was set, the module will wait until the DMA operation is vector is organized as shown in Table19-4. Multi-byte complete before attempting to transmit the packet. This fields are written in little-endian format. possible delay is required because the DMA and FIGURE 19-10: SAMPLE TRANSMIT PACKET LAYOUT Buffer Pointers Address Memory Description PHUGEEN, PPADN, ETXST = 0120h 0120h 0Eh Control PCRCEN and POVERRIDE 0121h data[1] 0122h data[2] Destination Address, Data Packet Source Address, Type/Length and Data ETXND = 0156h 0156h data[m] 0157h tsv[7:0] 0158h tsv[15:8] 0159h tsv[23:16] Status Vector 015Ah tsv[31:24] Status Vector Written by the Hardware 015Bh tsv[39:32] 015Ch tsv[47:40] 015Dh tsv[55:48] 015Eh Start of the Next Packet DS39762F-page 250  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 19-4: TRANSMIT STATUS VECTORS Bit Field Description 55-52 Zero 0 51 Transmit VLAN Tagged Frame Frame’s length/type field contained 8100h which is the VLAN protocol identifier. 50 Backpressure Applied Reserved, do not use. 49 Transmit Pause Control Frame The frame transmitted was a control frame with a valid pause opcode. 48 Transmit Control Frame The frame transmitted was a control frame. 47-32 Total Bytes Transmitted on Wire Total bytes transmitted on the wire for the current packet, including all bytes from collided attempts. 31 Transmit Underrun The transmission was aborted due to insufficient buffer memory bandwidth to sustain the 10 Mbit/s transmit rate. 30 Transmit Giant Byte count for frame was greater than the MAMXFL registers. 29 Transmit Late Collision Collision occurred after 64 bytes had already been transmitted. 28 Transmit Excessive Collision Packet was aborted after the number of collisions exceeded 15, the retransmission maximum. 27 Transmit Excessive Defer Packet was deferred in excess of 24,287 bit times (2.4287ms), due to a continuously occupied medium. 26 Transmit Packet Defer Packet was deferred for at least one attempt, but less than an excessive defer. 25 Transmit Broadcast Packet’s destination address was a Broadcast address. 24 Transmit Multicast Packet’s destination address was a Multicast address. 23 Transmit Done Transmission of the packet was completed successfully. 22 Transmit Length Out of Range Indicates that frame type/length field was larger than 1500 bytes (type field). 21 Transmit Length Check Error Indicates that the frame length field value in the packet does not match the actual data byte length and is not a type field. The FRMLNEN bit (MACON3<1>) must be set to get this error. 20 Transmit CRC Error The attached CRC in the packet did not match the internally generated CRC. 19-16 Transmit Collision Count Number of collisions the current packet incurred during transmission attempts. It applies to successfully transmitted packets, and as such, will not show the possible maximum count of 16 collisions. 15-0 Transmit Byte Count Total bytes in frame, not counting collided bytes.  2011 Microchip Technology Inc. DS39762F-page 251

PIC18F97J60 FAMILY 19.5.3 RECEIVING PACKETS criteria will be discarded and the application will not have any means of identifying that a packet was thrown Assuming that the receive buffer has been initialized, away. When a packet is accepted and completely the MAC has been properly configured and the receive written into the buffer: filters have been configured, the application should perform these steps to receive Ethernet packets: • The EPKTCNT register is incremented 1. Set the PKTIE and ETHIE bits to generate an • The PKTIF bit is set Ethernet interrupt whenever a packet is received • An interrupt is generated (if enabled) (if desired). • The Hardware Write Pointers, ERXWRPT, are 2. Clear the RXERIF flag and set both RXERIE automatically advanced and ETHIE to generate an interrupt whenever a 19.5.3.1 Receive Packet Layout packet is dropped, due to insufficient buffer space or memory access bandwidth (if desired). Figure19-11 shows the layout of a received packet. 3. Enable reception by setting the RXEN bit The packets are preceded by a 6-byte header which (ECON1<2>). contains a Next Packet Pointer in addition to a receive status vector which contains receive statistics, After setting RXEN, the Duplex mode and the Receive including the packet’s size. The receive status vectors Buffer Start and End Pointers should not be modified. are shown in Table19-5. Additionally, to prevent unexpected packets from arriv- ing, it is recommended that RXEN be cleared before If the last byte in the packet ends on an odd value altering the receive filter configuration (ERXFCON) and address, the hardware will automatically add a padding MAC address. byte when advancing the Hardware Write Pointer. As such, all packets will start on an even boundary. After reception is enabled, packets which are not filtered out will be written into the circular receive buffer. Any packet which does not meet the necessary filter FIGURE 19-11: SAMPLE RECEIVE PACKET LAYOUT Address Memory Description Packet N – 1 End of the Previous Packet 101Fh 1020h 5Eh Low Byte Next Packet Pointer 1021h 10h High Byte 1022h rsv[7:0] status[7:0] 1023h rsv[15:8] status[15:8] Receive Status Vector 1024h rsv[23:16] status[23:16] 1025h rsv[30:24] status[31:24] 1026h data[1] 1027h data[2] Packet N Packet Data: Destination Address, Source Address, Type/Length, Data, Padding, CRC 1059h data[m-3] crc[31:24] 105Ah data[m-2] crc[23:16] 105Bh data[m-1] crc[15:8] 105Ch data[m] crc[7:0] Byte Skipped to Ensure 105Dh Even Buffer Address 105Eh Packet N + 1 Start of the Next Packet DS39762F-page 252  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 19-5: RECEIVE STATUS VECTORS Bit Field Description 31 Zero ‘0’ 30 Receive VLAN Type Detected Current frame was recognized as a VLAN tagged frame. 29 Receive Unknown Opcode Current frame was recognized as a control frame, but it contained an unknown opcode. 28 Receive Pause Control Frame Current frame was recognized as a control frame containing a valid pause frame opcode and a valid destination address. 27 Receive Control Frame Current frame was recognized as a control frame for having a valid type/length designating it as a control frame. 26 Dribble Nibble Indicates that after the end of this packet, an additional 1 to 7 bits were received. The extra bits were thrown away. 25 Receive Broadcast Packet Indicates packet received had a valid Broadcast address. 24 Receive Multicast Packet Indicates packet received had a valid Multicast address. 23 Received OK Indicates that the packet had a valid CRC and no symbol errors. 22 Length Out of Range Indicates that frame type/length field was larger than 1500 bytes (type field). 21 Length Check Error Indicates that frame length field value in the packet does not match the actual data byte length. 20 CRC Error Indicates that the frame CRC field value does not match the CRC calculated by the MAC. 19 Reserved 18 Carrier Event Previously Seen Indicates that at some time since the last receive, a carrier event was detected. The carrier event is not associated with this packet. A carrier event is activity on the receive channel that does not result in a packet receive attempt being made. 17 Reserved 16 Long Event/Drop Event Indicates a packet over 50,000 bit times occurred or that a packet was dropped since the last receive. 15-0 Received Byte Count Indicates length of the received frame. This includes the destination address, source address, type/length, data, padding and CRC fields. This field is stored in little-endian format. 19.5.3.2 Reading Received Packets In the event that the application needed to randomly access the packet, it would be necessary to manually To process the packet, an application will normally start calculate the proper ERDPT registers, taking care to reading from the beginning of the Next Packet Pointer. not exceed the end of the receive buffer if the packet The application will save the Next Packet Pointer, any spans the ERXND to ERXST buffer boundary. In other necessary bytes from the receive status vector, and words, given the packet start address and a desired then proceed to read the actual packet contents. If the offset, the application should follow the logic shown in AUTOINC bit is set, it will be able to sequentially read Equation19-1. the entire packet without ever modifying the ERDPT registers. The Read Pointer would automatically wrap at the end of the circular receive buffer to the beginning. EQUATION 19-1: RANDOM ACCESS ADDRESS CALCULATION If Packet Start Address + Offset > ERXND, then ERDPT = Packet Start Address + Offset – (ERXND – ERXST + 1) else: ERDPT = Packet Start Address + Offset  2011 Microchip Technology Inc. DS39762F-page 253

PIC18F97J60 FAMILY 19.5.3.3 Freeing Receive Buffer Space Because only one pointer is available to control buffer area ownership, the application must process packets in After the user application has processed a packet (or the order they are received. If a packet is to be saved part of the packet) and needs to free the occupied buf- and processed later, the application should copy the fer space used by the processed data, it must advance packet to an unused location in memory. This can be the Receive Buffer Read Pointer pair, ERXRDPT. The done efficiently using the integrated DMA controller (see module always writes up to, but not over, the memory Section19.9 “Direct Memory Access Controller”). pointed to by the ERXRDPT registers. If an attempt to overwrite the Receive Buffer Read Pointer location 19.5.3.4 Receive Buffer Free Space occurs, the packet in progress is aborted, the RXERIF flag is set and an interrupt is generated (if enabled). In At any time the application needs to know how much this manner, the hardware will never overwrite receive buffer space is remaining, it should read the unprocessed packets. Normally, the ERXRDPT pair is Hardware Write Pointers (ERXWRPT registers) and advanced close to a value pointed to by the Next compare it with the ERXRDPT registers. Combined Packet Pointer, which precedes the receive status with the known size of the receive buffer, the free space vector for the current packet. can be derived. The Receive Buffer Read Pointer Low Byte Note: The ERXWRPT registers only update (ERXRDPTL register) is internally buffered to prevent when a packet has been successfully the pointer from moving when only one byte is updated. received. If the application reads it just To move the ERXRDPT pair, the application must write before another packet is to be success- to ERXRDPTL first. The write will update the internal fully completed, the value returned could buffer but will not affect the register. When the applica- be stale and off by the maximum frame tion writes to ERXRDPTH, the internally buffered low length permitted (MAMXFLH:MAMXFLL) byte will be loaded into the ERXRDPTL register at the plus 8. Furthermore, as the application same time. The ERXRDPT bytes can be read in any reads one byte of the ERXWRPT regis- order. When they are read, the actual value of the ters, a new packet may arrive and update registers will be returned. As a result, the buffered low the 13-bit pointer before the application byte is not readable. has an opportunity to read the other byte of the ERXWRPT registers. In addition to advancing the Receive Buffer Read Pointer, after each packet is fully processed, the appli- When reading the ERXWRPT registers with the receive cation must set the PKTDEC bit (ECON2<6>). This hardware enabled, special care must be taken to ensure causes the EPKTCNT register to decrement by 1. After the low and high bytes are read as a matching set. decrementing, if EPKTCNT is ‘0’, the PKTIF flag bit is To be assured that a matching set is obtained: automatically cleared. Otherwise, it remains set, indi- cating that additional packets are in the receive buffer 1. Read the EPKTCNT register and save its and are waiting to be processed. Attempting to decre- contents. ment EPKTCNT below 0 does not cause an underflow 2. Read ERXWRPTL and ERXWRPTH. to 255, but may cause an unintentional interrupt. The 3. Read the EPKTCNT register again. application should avoid decrementing EPKTCNT in 4. Compare the two packet counts. If they are not this situation. the same, go back to Step 2. Additionally, if the EPKTCNT register ever maximizes With the Hardware Write Pointers obtained, the free at 255, all new packets which are received will be space can be calculated as shown in Equation19-2. aborted, even if buffer space is available. To indicate The hardware prohibits moving the Write Pointer to the the error, the RXERIF is set and an interrupt is same value occupied by the ERXRDPT registers, so at generated (if enabled). To prevent this condition, the least one byte will always go unused in the buffer. The user application must properly decrement the counter Equation19-2 calculation reflects the lost byte. whenever a packet is processed. EQUATION 19-2: RECEIVE BUFFER FREE SPACE CALCULATION If ERXWRPT > ERXRDPT, then Free Space = (ERXND – ERXST) – (ERXWRPT – ERXRDPT) else: if ERXWRPT = ERXRDPT, then Free Space = (ERXND – ERXST) else: Free Space = ERXRDPT – ERXWRPT – 1 DS39762F-page 254  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 19-6: SUMMARY OF REGISTERS ASSOCIATED WITH PACKET TRANSMISSION Reset Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Name Page: EIE — PKTIE DMAIE LINKIE TXIE — TXERIE RXERIE 73 EIR — PKTIF DMAIF LINKIF TXIF — TXERIF RXERIF 73 ESTAT — BUFER — r — RXBUSY TXABRT PHYRDY 73 ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN — — 70 ETXSTL Transmit Start Register Low Byte (ETXST<7:0>) 74 ETXSTH — — — Transmit Start Register High Byte (ETXST<12:8>) 74 ETXNDL Transmit End Register Low Byte (ETXND<7:0>) 74 ETXNDH — — — Transmit End Register High Byte (ETXND<12:8>) 74 MACON1 — — — r TXPAUS RXPAUS PASSALL MARXEN 75 MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX 75 MACON4 — DEFER r r — — r r 75 MABBIPG — BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 75 MAIPGL — MAC Non Back-to-Back Inter-Packet Gap Register Low Byte (MAIPGL<6:0>) 75 MAIPGH — MAC Non Back-to-Back Inter-Packet Gap Register High Byte (MAIPGH<6:0>) 75 MAMXFLL Maximum Frame Length Register Low Byte (MAMXFL<7:0>) 74 MAMXFLH Maximum Frame Length Register High Byte (MAMXFL<15:8>) 74 Legend: — = unimplemented, r = reserved bit. Shaded cells are not used. TABLE 19-7: SUMMARY OF REGISTERS ASSOCIATED WITH PACKET RECEPTION Reset Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Name Page: EIE — PKTIE DMAIE LINKIE TXIE — TXERIE RXERIE 73 EIR — PKTIF DMAIF LINKIF TXIF — TXERIF RXERIF 73 ESTAT — BUFER — r — RXBUSY TXABRT PHYRDY 73 ECON2 AUTOINC PKTDEC ETHEN — — — — — 73 ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN — — 70 ERXSTL Receive Start Register Low Byte (ERXST<7:0>) 74 ERXSTH — — — Receive Start Register High Byte (ERXST<12:8>) 74 ERXNDL Receive End Register Low Byte (ERXND<7:0>) 74 ERXNDH — — — Receive End Register High Byte (ERXND<12:8>) 74 ERXRDPTL Receive Buffer Read Pointer Low Byte (ERXRDPT<7:0>) 73 ERXRDPTH — — — Receive Buffer Read Pointer High Byte (ERXRDPT<12:8>) 73 ERXFCON UCEN ANDOR CRCEN PMEN MPEN HTEN MCEN BCEN 74 EPKTCNT Ethernet Packet Count Register 74 MACON1 — — — r TXPAUS RXPAUS PASSALL MARXEN 75 MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX 75 MAMXFLL Maximum Frame Length Register Low Byte (MAMXFL<7:0>) 74 MAMXFLH Maximum Frame Length Register High Byte (MAMXFL<15:8>) 74 Legend: — = unimplemented, r = reserved bit. Shaded cells are not used.  2011 Microchip Technology Inc. DS39762F-page 255

PIC18F97J60 FAMILY 19.6 Duplex Mode Configuration and If the number of retransmission attempts reaches 15 and Negotiation another collision occurs, the packet is aborted and the TXRTS bit is cleared. The application will then be The Ethernet module does not support Automatic responsible for taking appropriate action. The applica- Duplex mode negotiation. If it is connected to an auto- tion will be able to determine that the packet was aborted matic duplex negotiation-enabled network switch or instead of being successfully transmitted by reading the Ethernet controller, the module will be detected as a TXABRT flag. For more information, see Section19.5.2 half-duplex device. To communicate in full duplex, the “Transmitting Packets”. module and the remote node (switch, router or Ethernet If the collision occurs after 64 bytes have already been controller) must be manually configured for full-duplex transmitted, the packet is immediately aborted without operation. any retransmission attempts. Ordinarily, in IEEE 802.3 compliant networks which are properly configured, this 19.6.1 HALF-DUPLEX OPERATION late collision will not occur. User intervention may be The Ethernet module operates in Half-Duplex mode required to correct the issue. This problem may occur when the FULDPX (MACON3<0>) and PDPXMD as a result of a full-duplex node attempting to transmit (PHCON1<8>) bits are cleared (= 0). If only one of on the half-duplex medium. Alternately, the module these two bits is set, the module will be in an indetermi- may be attempting to operate in Half-Duplex mode nate state and not function correctly. Since switching while it may be connected to a full-duplex network. between Full and Half-Duplex modes may result in this Excessively long cabling and network size may also be indeterminate state, it is recommended that the appli- a possible cause of late collisions. cation not transmit any packets (maintain the TXRTS bit clear), and disable packet reception (maintain the 19.6.2 FULL-DUPLEX OPERATION RXEN bit clear) during this period. The Ethernet module operates in Full-Duplex mode In Half-Duplex mode, only one Ethernet controller may when the FULDPX (MACON3<0>) and PDPXMD be transmitting on the physical medium at any time. If (PHCON1<8>) bits are both set (=1). If only one of the application requests a packet to be transmitted by these two bits is clear, the module will be in an indeter- setting the TXRTS bit while another Ethernet controller minate state and not function correctly. Again, since is already transmitting, the Ethernet module will delay, switching between Full and Half-Duplex modes may waiting for the remote transmitter to stop. When it result in this indeterminate state, it is recommended stops, the module will attempt to transmit its packet. that the application not transmit any packets and Should another Ethernet controller start transmitting at should disable packet reception during this period. approximately the same time, the data on the wire will In Full-Duplex mode, packets will be transmitted while become corrupt and a collision will occur. simultaneously packets may be received. Given this, it The hardware will handle this condition in one of two is impossible to cause any collisions when transmitting ways. If the collision occurs before 64 bytes have been packets. transmitted, the following events occur: 1. The TXRTS bit remains set 2. The transmit error interrupt does not occur 3. A random exponential backoff delay elapses, as defined by the IEEE 802.3 specification 4. A new attempt to transmit the packet from the beginning occurs. The application does not need to intervene. DS39762F-page 256  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.7 Flow Control used to initialize an internal timer. The timer will auto- matically decrement every 512 bit times, or 51.2 s. The Ethernet module implements hardware flow con- While the timer is counting down, reception of packets trol for both Full and Half-Duplex modes. The operation is still enabled. If new pause frames arrive, the timer will of this feature differs depending on which mode is be re-initialized with the new pause timer value. When being used. the timer reaches zero, or was sent a frame with a zero pause timer value, the MAC that received the pause 19.7.1 HALF-DUPLEX MODE frame will resume transmitting any pending packets. To In Half-Duplex mode, setting the FCEN0 bit prevent a pause frame from stopping all traffic on the (EFLOCON<0>) causes flow control to be enabled. entire network, Ethernet switches and routers do not When FCEN0 is set, a continuous preamble pattern of propagate pause control frames in Full-Duplex mode. alternating ‘1’s and ‘0’s (55h) will automatically be The pause operation only applies to the direct recipient. transmitted on the Ethernet medium. Any connected A sample network is shown in Figure19-12. If nodes will see the transmission and either not transmit Computer A were to be transmitting too much data to anything, waiting for the transmission to end, or will the microcontroller-based application in Full-Duplex attempt to transmit and immediately cause a collision. mode, the Ethernet module could transmit a pause Because a collision will always occur, no nodes on the control frame to stop the data which is being sent to it. network will be able to communicate with each other The Ethernet switch would take the pause frame and and no new packets will arrive. stop sending data to the application. If Computer A When the application causes the module to transmit a continues to send data, the Ethernet switch will buffer packet by setting the TXRTS bit, the preamble pattern the data so it can be transmitted later when its pause will stop being transmitted. An inter-packet delay will timer expires. If the Ethernet switch begins to run out of pass as configured by register, MABBIPG, and then the buffer space, it will likely transmit a pause control frame module will attempt to transmit its packet. After the of its own to Computer A. inter-packet delay, other nodes may begin to transmit. If, for some reason the Ethernet switch does not gener- Because all traffic was jammed previously, several ate a pause control frame of its own, or one of the nodes may begin transmitting and a series of collisions nodes does not properly handle the pause frame it may occur. When the module successfully finishes receives, then packets will inevitably be dropped. In transmitting its packet or aborts it, the transmission of any event, any communication between Computer A the preamble pattern will automatically restart. When and Computer B will always be completely unaffected. the application wishes to no longer jam the network, it should clear the FCEN0 bit. The preamble transmis- FIGURE 19-12: SAMPLE FULL-DUPLEX sion will cease and normal network operation will NETWORK resume. Given the detrimental network effects that are possible and lack of effectiveness, it is not recommended that half-duplex flow control be used unless the application will be in a closed network environment with proper testing. 19.7.2 FULL-DUPLEX MODE In Full-Duplex mode (MACON3<0> = 1), hardware flow control is implemented by means of transmitting pause control frames, as defined by the IEEE 802.3 specifica- tion. Pause control frames are 64-byte frames consisting of the reserved Multicast destination address of 01-80-C2-00-00-01, the source address of the sender, a special pause opcode, a 2-byte pause timer value and padding/CRC. Normally, when a pause control frame is received by a MAC, the MAC will finish the packet it is transmitting and then stop transmitting any new frames. The pause timer value will be extracted from the control frame and  2011 Microchip Technology Inc. DS39762F-page 257

PIC18F97J60 FAMILY To enable flow control in Full-Duplex mode, set the When the RXPAUS bit is set and a valid pause frame TXPAUS and RXPAUS bits in the MACON1 register. arrives with a non-zero pause timer value, the module Then, at any time that the receiver buffer is running out will automatically inhibit transmissions. If the TXRTS bit of space, set the Flow Control Enable bits, FCEN<1:0> becomes set to send a packet, the hardware will simply (EFLOCON<1:0>). The module will automatically finish wait until the pause timer expires before attempting to transmitting anything that was in progress and then send the packet and subsequently, clearing the TXRTS send a valid pause frame, loaded with the selected bit. Normally, this is transparent to the microcontroller, pause timer value. Depending on the mode selected, and it will never know that a pause frame had been the application may need to eventually clear Flow received. Should it be desirable to know when the MAC Control mode by again writing to the FCEN bits. is paused or not, the user should set the PASSALL bit (MACON1<1>), then manually interpret the pause control frames which may arrive. REGISTER 19-19: EFLOCON: ETHERNET FLOW CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R-0 R/W-0 R/W-0 — — — — — r FCEN1 FCEN0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 Reserved: Do not use bit 1-0 FCEN<1:0>: Flow Control Enable bits When FULDPX (MACON3<0>) = 1: 11 = Send one pause frame with a ‘0’ timer value and then turn flow control off 10 = Send pause frames periodically 01 = Send one pause frame then turn flow control off 00 = Flow control off When FULDPX (MACON3<0>) = 0: x1 = Flow control on x0 = Flow control off TABLE 19-8: SUMMARY OF REGISTERS USED WITH FLOW CONTROL Reset Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Name Page: ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN — — 70 MACON1 — — — r TXPAUS RXPAUS PASSALL MARXEN 75 MABBIPG — BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 75 EFLOCON — — — — — r FCEN1 FCEN0 75 EPAUSL Pause Timer Value Register Low Byte (EPAUS<7:0>) 75 EPAUSH Pause Timer Value Register High Byte (EPAUS<15:8>) 75 Legend: — = unimplemented, r = reserved bit. Shaded cells are not used. DS39762F-page 258  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.8 Receive Filters 19.8.4 HASH TABLE FILTER To minimize microcontroller processing overhead, the The Hash Table receive filter is typically used to receive Ethernet module incorporates a range of different traffic sent to a specific Multicast group address. receive filters which can automatically reject packets Because it checks the specific destination address of which are not needed. Six different types of packet packets, it is capable of filtering out more unwanted filters are implemented: packets than the Multicast filter. • Unicast The filter performs a 32-bit CRC over the six destination address bytes in the packet, using the polynomial, • Multicast 4C11DB7h. From the resulting 32-bit binary number, a • Broadcast 6-bit value is derived from bits<28:23>. This value, in • Pattern Match turn, points to a location in a table formed by the Ether- • Magic Packet™ net Hash Table registers, ETH0 through ETH7. If the bit • Hash Table in that location is set, the packet meets the Hash Table filter criteria and is accepted. The specific pointer values The individual filters are all configured by the ERXFCON for each bit location in the table are shown in Table19-9. register (Register19-20). More than one filter can be active at any given time. Additionally, the filters can be An example of the Hash Table operation is shown in configured by the ANDOR bit to either logically AND or Example19-1. In this case, the destination address, logically OR the tests of several filters. In other words, 01-00-00-00-01-2C, produces a Table Pointer value of the filters may be set so that only packets accepted by 34h, which points to bit 4 of ETH6. If this bit is ‘1’, the all active filters are accepted, or a packet accepted by packet will be accepted. any one filter is accepted. The flowcharts in Figure19-13 By extension, clearing every bit in the Hash Table and Figure19-14 show the effect that each of the filters registers means that the filter criteria will never be met. will have, depending on the setting of ANDOR. Similarly, if every bit in the Hash Table is set, the filter The device can enter Promiscuous mode and receive criteria will always be met. all legal packets by setting the ERXFCON register to 20h (enabling only the CRC filter for valid packets). The TABLE 19-9: BIT ASSIGNMENTS IN HASH proper setting of the register will depend on the TABLE REGISTERS application requirements. Bit Number in Hash Table Register 19.8.1 UNICAST FILTER 7 6 5 4 3 2 1 0 EHT0 07 06 05 04 03 02 01 00 The Unicast receive filter checks the destination address of all incoming packets. If the destination EHT1 0F 0E 0D 0C 0B 0A 09 08 address exactly matches the contents of the MAADR EHT2 17 16 15 14 13 12 11 10 registers, the packet meets the Unicast filter criteria. EHT3 1F 1E 1D 1C 1B 1A 19 18 EHT4 27 26 25 24 23 22 21 20 19.8.2 MULTICAST FILTER EHT5 2F 2E 2D 2C 2B 2A 29 28 The Multicast receive filter checks the destination EHT6 37 36 35 34 33 32 31 30 address of all incoming packets. If the Least Significant EHT7 3F 3E 3D 3C 3B 3A 39 38 bit of the first byte of the destination address is set, the packet meets the Multicast filter criteria. EXAMPLE 19-1: DERIVING A HASH TABLE 19.8.3 BROADCAST FILTER LOCATION The Broadcast receive filter checks the destination Packet Destination Address: address of all incoming packets. If the destination 01-00-00-00-01-2C (hex) address is FF-FF-FF-FF-FF-FF, the packet meets the Result of CRC-32 with 4C11DB7h: Broadcast filter criteria. 1101 1010 0000 1011 0100 0101 0111 0101 (binary) Pointer Derived from bits<28:23> of CRC Result: 110100 (binary) or 34 (hex) Corresponding Hash Table Location: ETH6<4>  2011 Microchip Technology Inc. DS39762F-page 259

PIC18F97J60 FAMILY REGISTER 19-20: ERXFCON: ETHERNET RECEIVE FILTER CONTROL REGISTER R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 UCEN ANDOR CRCEN PMEN MPEN HTEN MCEN BCEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UCEN: Unicast Filter Enable bit When ANDOR = 1: 1 = Packets not having a destination address matching the local MAC address will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Packets with a destination address matching the local MAC address will be accepted 0 = Filter is disabled bit 6 ANDOR: AND/OR Filter Select bit 1 = AND: Packets will be rejected unless all enabled filters accept the packet 0 = OR: Packets will be accepted unless all enabled filters reject the packet bit 5 CRCEN: Post-Filter CRC Check Enable bit 1 = All packets with an invalid CRC will be discarded 0 = The CRC validity will be ignored bit 4 PMEN: Pattern Match Filter Enable bit When ANDOR = 1: 1 = Packets must meet the Pattern Match criteria or they will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Packets which meet the Pattern Match criteria will be accepted 0 = Filter is disabled bit 3 MPEN: Magic Packet Filter Enable bit When ANDOR = 1: 1 = Packets must be Magic Packets for the local MAC address or they will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Magic Packets for the local MAC address will be accepted 0 = Filter is disabled bit 2 HTEN: Hash Table Filter Enable bit When ANDOR = 1: 1 = Packets must meet the Hash Table criteria or they will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Packets which meet the Hash Table criteria will be accepted 0 = Filter is disabled bit 1 MCEN: Multicast Filter Enable bit When ANDOR = 1: 1 = The LSb of the first byte of the packet’s destination address must be set or it will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Packets which have the LSb of the first byte in the destination address set will be accepted 0 = Filter is disabled bit 0 BCEN: Broadcast Filter Enable bit When ANDOR = 1: 1 = Packets must have a destination address of FF-FF-FF-FF-FF-FF or they will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Packets which have a destination address of FF-FF-FF-FF-FF-FF will be accepted 0 = Filter is disabled DS39762F-page 260  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 19-13: RECEIVE FILTERING USING OR LOGIC Packet Detected on Wire, ANDOR = 0 (OR) UCEN, PMEN, Yes MPEN, HTEN, MCEN and BCEN all clear? No UCENset? Yes Unicast Yes CRCENset? No packet? Yes No No Yes CRCENvalid? Accept Packet PMENset? Yes Pattern Yes matches? No No No Reject Packet Yes Yes MPENset? MagicPacket™ for us? No No Yes Yes HTEN set? Hash table bit set? No No MCEN set? Yes Multicast Yes destination? No No Yes Broadcast Yes BCEN set? destination? No No  2011 Microchip Technology Inc. DS39762F-page 261

PIC18F97J60 FAMILY FIGURE 19-14: RECEIVE FILTERING USING AND LOGIC Packet Detected on Wire, ANDOR = 1 (AND) Yes Unicast No UCEN set? packet? No Yes Yes Pattern No PMEN set? Matches? No Yes Yes No MPEN set? Magic Packet™ for us? No Yes HTEN set? Yes Hash Table No bit set? No Yes Yes No MCEN set? Multicast destination? No Yes Yes Broadcast No BCEN set? destination? No Yes No CRCEN set? Yes No CRC valid? Yes Accept Packet Reject Packet DS39762F-page 262  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.8.5 PATTERN MATCH FILTER The Pattern Match Checksum registers should be programmed to the checksum which is expected for the The Pattern Match filter selects up to 64 bytes from the selected bytes. The checksum is calculated in the incoming packet and calculates an IP checksum of the same manner that the DMA module calculates bytes. The checksum is then compared to the EPMCS checksums (see Section19.9.2 “Checksum Calcula- registers. The packet meets the Pattern Match filter cri- tions”). Data bytes which have corresponding mask teria if the calculated checksum matches the EPMCS bits programmed to ‘0’ are completely removed for registers. The Pattern Match filter may be useful for purposes of calculating the checksum, as opposed to filtering packets which have expected data inside them. treating the data bytes as zero. To use the Pattern Match filter, the application must As an example, if the application wished to filter all program the Pattern Match offset (EPMOH:EPMOL), packets having a particular source MAC address of all of the Pattern Match mask bytes (EPMM0:EPMM7) 00-04-A3-FF-FF-FF, it could program the Pattern and the Pattern Match Checksum register pair Match offset to 0000h and then set bits 6 and 7 of (EPMCSH:EPMCSL). The Pattern Match offset should EPMM0 and bits 0, 1, 2 and 3 of EPMM1 (assuming all be loaded with the offset from the beginning of the des- other mask bits are ‘0’). The proper checksum to pro- tination address field to the 64-byte window which will gram into the EPMCS registers would be 5BFCh. As an be used for the checksum computation. Within the alternative configuration, it could program the offset to 64-byte window, each individual byte can be selectively 0006h and set bits 0, 1, 2, 3, 4 and 5 of EPMM0. The included or excluded from the checksum computation checksum would still be 5BFCh. However, the second by setting or clearing the respective bit in the Pattern case would be less desirable as packets less than Match mask. If a packet is received which would cause 70bytes long could never meet the Pattern Match cri- the 64-byte window to extend past the end of the CRC, teria, even if they would generate the proper checksum the filter criteria will immediately not be met, even if the given the mask configuration. corresponding mask bits are all ‘0’. Another example of a Pattern Match filter is illustrated Note: In all cases, the value of the Pattern Match in Figure19-15. offset must be even for proper operation. Programming the EMPO register pair with an odd value will cause unpredictable results. FIGURE 19-15: SAMPLE PATTERN MATCH FORMAT Input Configuration: EMPOH:EPMOL = 0006h EPMM7:EPMM0 = 0000000000001F0Ah EPMCSH:EPMCSL = 563Fh Field DA SA Type/Length Data FCS Received Data 11 22 33 44 55 66 77 88 99 AA BB CC 00 5A 09 0A 0B 0C 0D . . . 40 . . . FE 45 23 01 Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 . . . 70 . . . Bytes Used for Checksum Computation 64-Byte Window Used for Pattern Match Values Used for Checksum Computation = {88h, AAh, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 00h} (00h padding byte added by hardware) Note: Received data is shown in hexadecimal. Byte numbers are shown in decimal format.  2011 Microchip Technology Inc. DS39762F-page 263

PIC18F97J60 FAMILY 19.8.6 MAGIC PACKET FILTER The Magic Packet pattern consists of a sync pattern of 6FFh bytes, followed by 16 repeats of the destination address (Figure19-16). The Magic Packet filter checks the destination address and data fields of all incoming packets. If the destination address matches the MAADR registers and the data field holds a valid Magic Packet pattern someplace within it, then the packet will meet the Magic Packet filter criteria. FIGURE 19-16: SAMPLE MAGIC PACKET™ FORMAT Received Data Field Comments 00 11 22 33 44 55 DA Destination MAC Address 77 88 99 AA BB CC SA Source MAC Address 00 FE Type/Length Optional Application Data 09 0A 0B 0C 0D 0E Header or Protocol Header FF FF FF FF FF 00 FF FF FF FF FF FF Sync Pattern 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 Magic 00 11 22 33 44 55 Packet 16 Repeats of the 00 11 22 33 44 55 Pattern Destination MAC Address 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 19 1A 1B 1C 1D 1E Footer Optional Application Data or Protocol Footer EF 54 32 10 FCS DS39762F-page 264  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.9 Direct Memory Access Controller • After termination of a DMA operation (DMAST is cleared by hardware or firmware), the application The Ethernet module incorporates a dual purpose DMA must not set DMAST again within 4 instruction controller, which can be used to copy data between loca- cycles. tions within the 8-Kbyte memory buffer. It can also be • To ensure reliable operation, avoid having the used to calculate a 16-bit checksum which is compatible application access EDATA during a DMA copy with various industry standard communication protocols, operation. EDATA may be safely accessed during including TCP, UDP, IP, ICMP, etc. DMA checksum operations. The DMA is controlled using three pointers and several status/control bits: 19.9.1 COPYING MEMORY • EDMASTH:EDMASTL: Source Start Address To copy memory within the buffer: • EDMANDH:EDMANDL: Source End Address 1. Program the EDMAST, EDMAND and EDMADST register pairs with the appropriate start, end and • EDMADSTH:EDMADSTL: Destination Start destination addresses. The EDMAST registers Address should point to the first byte to copy from, the • DMAST and CSUMEN (ECON1<5,4>): DMA EDMAND registers should point to the last byte to Start/Busy and Checksum Enable bits copy and the EDMADST registers should point to • DMAIE and DMAIF (EIE<5> and EIR<5>): DMA the first byte in the destination range. The destina- Interrupt Enable and Flag bits tion range will always be linear, never wrapping at The Source and End Pointers define what data will be any values except from 8191 to 0 (the 8-Kbyte copied or checksumed. The Destination Pointer, used memory boundary). Extreme care should be only when copying data, defines where copied data will taken when calculating the End Pointer to prevent be placed. All three pointers are with respect to the a never ending DMA operation which would 8-Kbyte Ethernet memory and cannot be used to overwrite the entire 8-Kbyte buffer. access memory in the PIC® microcontroller data 2. If desired, set the DMAIE (EIE<5>) and ETHIE memory space. (PIE2<5>) bits, and clear the DMAIF (EIR<5>) When a DMA operation begins, the EDMAST register flag bit to enable an interrupt at the end of the pair is copied into an Internal Source Pointer. The DMA copy process. will execute on one byte at a time and then increment the 3. Clear the CSUMEN (ECON1<4>) bit. Internal Source Pointer. However, if a byte is processed 4. Start the DMA copy by setting the DMAST and the Internal Source Pointer is equal to the Receive (ECON1<5>) bit. Buffer End Pointer pair, ERXND, the Source Pointer will If a transmit operation is in progress (TXRTS bit is set) not be incremented. Instead, the Internal Source Pointer while the DMAST bit is set, the module will wait until the will be loaded with the Receive Buffer Start Pointer pair, transmit operation is complete before attempting to do ERXST. In this way, the DMA will follow the circular FIFO the DMA copy. This possible delay is required because structure of the receive buffer and received packets can the DMA and transmission engine are unable to access be processed using one operation. The DMA operation the buffer at the same time. will end when the Internal Source Pointer matches the EDMAND Pointers. When the copy is complete, the DMA hardware will clear the DMAST bit, set the DMAIF bit and generate While any DMA operation is in progress, the DMA Point- an interrupt (if enabled). The pointers and the ers and the CSUMEN bit (ECON1<4>) should not be EDMACS registers will not be modified. modified. The DMA operation can be canceled at any time by clearing the DMAST bit (ECON1<5>). No regis- After the DMA module has been initialized and has ters will change; however, some memory bytes may begun its copy, one instruction cycle (TCY) will be already have been copied if a DMA copy was in progress. required for each byte copied. However, if the Ethernet receive hardware accumulates one byte of data, the Some operational requirements must always be kept in DMA will stall that cycle, yielding to the higher priority mind when using the DMA. Failure to observe these operation. If a maximum size, 1518-byte packet was requirements may result in a loss of Ethernet buffer copied while no other memory bandwidth was being data, or even complete failure of Ethernet operation: used, the DMA module would require slightly more than • If the EDMAND Pointers cannot be reached 145.7 s to complete at a core frequency of 41.667 because of the receive buffer wrapping behavior, MHz. The time required to copy a minimum size packet the DMA operation will never end. of 64 bytes would be approximately 6.2 s (at • By design, the DMA module cannot be used to 41.667MHz), plus register configuration time. copy or calculate a checksum over only one byte (EDMAST=EDMAND). An attempt to do so may overwrite all memory in the buffer and never end.  2011 Microchip Technology Inc. DS39762F-page 265

PIC18F97J60 FAMILY 19.9.2 CHECKSUM CALCULATIONS When the checksum is finished being calculated, the hardware will clear the DMAST bit, set the DMAIF bit The checksum calculation logic treats the source data and an interrupt will be generated, if enabled. The DMA as a series of 16-bit big-endian integers. If the source Pointers will not be modified and no memory will be range contains an odd number of bytes, a padding byte written to. The EDMACSH and EDMACSL registers will of 00h is effectively added to the end of the series for contain the calculated checksum. The application may purposes of calculating the checksum. write this value into a packet, compare this value with The calculated checksum is the 16-bit, one’s zero (to validate a received block of data containing a complement of the one’s complement sum of all 16-bit checksum field in it), or compare it with some other integers. For example, if the bytes included in the checksum, such as a pseudo header checksum used in checksum were {89h, ABh, CDh}, the checksum would various protocols (TCP, UDP, etc.). begin by computing: 89ABh + CD00h. A carry out of the When operating the DMA in Checksum mode, it takes 16th bit would occur in the example, so in 16-bit one’s one instruction cycle (TCY) for every byte included in complement arithmetic, it would be added back to the the checksum. As a result, if a checksum over first bit. The resulting value of 56ACh would finally be 1446bytes was performed, the DMA module would complemented to achieve a checksum of A953h. require slightly more than 138.8 s to complete the To calculate a checksum: operation at 41.667 MHz. 1. Set the EDMAST and EDMAND register pairs to At the same frequency, a small 20-byte header field point to the first and last bytes of buffer data to would take approximately 1.9s plus DMA setup time be included in the checksum. Care should be to calculate a sum. These estimated times assume that taken when programming these pointers to the Ethernet receive hardware does not need memory prevent a never-ending checksum calculation access bandwidth and the CPU does not issue any due to receive buffer wrapping. reads or writes to the EDATA register while the DMA is 2. To generate an optional interrupt when the computing. checksum calculation is done, set the DMAIE Like the DMA Copy mode, the checksum operation will (EIE<5>) and ETHIE (PIE2<5>) bits and clear not start until the TXRTS bit (ECON1<3>) is clear. This the DMAIF (EIR<5>) bit. may considerably increase the checksum calculation 3. Start the calculation by setting the CSUMEN time if the application transmits a large packet and (ECON1<4>) and DMAST (ECON1<5>) bits. immediately attempts to validate a checksum on a received packet. TABLE 19-10: SUMMARY OF REGISTERS ASSOCIATED WITH THE DMA CONTROLLER Reset Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Name Page EIE — PKTIE DMAIE LINKIE TXIE — TXERIE RXERIE 73 EIR — PKTIF DMAIF LINKIF TXIF — TXERIF RXERIF 73 ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN — — 70 ERXNDL Receive End Register Low Byte (ERXND<7:0>) 73 ERXNDH — — — Receive End Register High Byte (ERXND<12:8>) 73 EDMASTL DMA Start Register Low Byte (EDMAST<7:0>) 73 EDMASTH — — — DMA Start Register High Byte (EDMAST<12:8>) 73 EDMANDL DMA End Register Low Byte (EDMAND<7:0>) 73 EDMANDH — — — DMA End Register High Byte (EDMAND<12:8>) 73 EDMADSTL DMA Destination Register Low Byte (EDMADST<7:0>) 73 EDMADSTH — — — DMA Destination Register High Byte (EDMADST<12:8>) 73 EDMACSL DMA Checksum Register Low Byte (EDMACS<7:0>) 73 EDMACSH DMA Checksum Register High Byte (EDMACS<15:8>) 73 Legend: — = unimplemented. Shaded cells are not used. DS39762F-page 266  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 19.10 Module Resets 19.10.2 TRANSMIT ONLY RESET The Ethernet module provides selective module The Transmit Only Reset is performed by writing a ‘1’ Resets: to the TXRST bit (ECON1<7>). This resets the transmit logic only. Other register and control blocks, such as • Transmit Only Reset buffer management and host interface, are not affected • Receive Only Reset by a Transmit Only Reset event. To return to normal operation, the TXRST bit must be cleared in software. 19.10.1 MICROCONTROLLER RESETS After clearing TXRST, firmware must not write to any Following any standard Reset event, the Ethernet Ethernet module SFRs for at least 1.6 s. After the module returns to a known state. The contents of the delay, normal operation can resume. Ethernet buffer memory are unknown. All SFR and 19.10.3 RECEIVE ONLY RESET PHY registers are loaded with their specified Reset val- ues, depending on the type of Reset event. However, The Receive Only Reset is performed by writing a ‘1’ to the PHY registers must not be accessed until the PHY the RXRST bit (ECON1<6>). This action resets receive start-up timer has expired and the PHYRDY bit logic only. Other register and control blocks, such as the (ESTAT<0>) becomes set, or at least 1ms has passed buffer management and host interface blocks, are not since the ETHEN bit was set. For more details, see affected by a Receive Only Reset event. To return to Section19.1.3.1 “Start-up Timer”. normal operation, the RXRST bit is cleared in software. After clearing RXRST, firmware must not write to any Ethernet module SFRs for at least 1.6 s. After the delay, normal operation can resume.  2011 Microchip Technology Inc. DS39762F-page 267

PIC18F97J60 FAMILY NOTES: DS39762F-page 268  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.0 MASTER SYNCHRONOUS 20.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four modes of SPI are supported. To accomplish 20.1 Master SSP (MSSP) Module communication, typically three pins are used: Overview • Serial Data Out (SDOx) – RC5/SDO1 (or RD4/SDO2 for 100-pin devices) The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other • Serial Data In (SDIx) – RC4/SDI1/SDA1 (or peripheral or microcontroller devices. These peripheral RD5/SDI2/SDA2 for 100-pin devices) devices may be serial EEPROMs, shift registers, • Serial Clock (SCKx) – RC3/SCK1/SCL1 (or display drivers, A/D Converters, etc. The MSSP mod- RD6/SCK2/SCL2 for 100-pin devices) ule can operate in one of two modes: Additionally, a fourth pin may be used when in a Slave • Serial Peripheral Interface (SPI) mode of operation: • Inter-Integrated Circuit (I2C™) • Slave Select (SSx) – RF7/SS1 (or RD7/SS2 for - Full Master mode 100-pin devices) - Slave mode (with general address call) Figure20-1 shows the block diagram of the MSSP The I2C interface supports the following modes in module when operating in SPI mode. hardware: FIGURE 20-1: MSSP BLOCK DIAGRAM • Master mode (SPIMODE) • Multi-Master mode • Slave mode Internal The 64-pin and 80-pin devices of the PIC18F97J60 Data Bus family have one MSSP module, designated as MSSP1. Read Write The 100-pin devices have two MSSP modules, desig- nated as MSSP1 and MSSP2. Each module operates independently of the other. SSPxBUF reg Note: Throughout this section, generic refer- ences to an MSSP module in any of its SDIx operating modes may be interpreted as SSPxSR reg being equally applicable to MSSP1 or SDOx bit 0 Shift MSSP2. Register names and module I/O Clock signals use the generic designator, ‘x’, to indicate the use of a numeral to distin- guish a particular module when required. Control bit names are not individuated. SSx SSx Control Enable 20.2 Control Registers Each MSSP module has three associated control Edge Select registers. These include a status register (SSPxSTAT) and two control registers (SSPxCON1 and SSPxCON2). 2 The use of these registers and their individual configura- Clock Select tion bits differ significantly depending on whether the MSSP module is operating in SPI or I2C mode. SSPM<3:0> ( ) Additional details are provided under the individual SMP:CKE 4 TMR2 Output sections. SCKx 2 2 Edge Note: In devices with more than one MSSP Select Prescaler TOSC module, it is very important to pay close 4, 16, 64 attention to the SSPxCON register names. SSP1CON1 and SSP1CON2 Data to TXx/RXx in SSPxSR TRIS bit control different operational aspects of the same module, while SSP1CON1 and SSP2CON1 control the same features for two different modules.  2011 Microchip Technology Inc. DS39762F-page 269

PIC18F97J60 FAMILY 20.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data Each MSSP module has four registers for SPI mode bytes are written to or read from. operation. These are: In receive operations, SSPxSR and SSPxBUF • MSSPx Control Register 1 (SSPxCON1) together create a double-buffered receiver. When • MSSPx Status Register (SSPxSTAT) SSPxSR receives a complete byte, it is transferred to • Serial Receive/Transmit Buffer Register SSPxBUF and the SSPxIF interrupt is set. (SSPxBUF) During transmission, the SSPxBUF is not • MSSPx Shift Register (SSPxSR) – Not directly double-buffered. A write to SSPxBUF will write to both accessible SSPxBUF and SSPxSR. SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. REGISTER 20-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE(1) D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>). DS39762F-page 270  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 20-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, Clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0100 = SPI Slave mode, Clock = SCKx pin, SSx pin control enabled 0011 = SPI Master mode, Clock = TMR2 output/2 0010 = SPI Master mode, Clock = FOSC/64 0001 = SPI Master mode, Clock = FOSC/16 0000 = SPI Master mode, Clock = FOSC/4 Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When this bit is enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.  2011 Microchip Technology Inc. DS39762F-page 271

PIC18F97J60 FAMILY 20.3.2 OPERATION received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the When initializing the SPI, several options need to be Write Collision detect bit, WCOL (SSPxCON1<7>), will specified. This is done by programming the appropriate be set. User software must clear the WCOL bit so that control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). it can be determined if the following write(s) to the These control bits allow the following to be specified: SSPxBUF register completed successfully. • Master mode (SCKx is the clock output) When the application software is expecting to receive • Slave mode (SCKx is the clock input) valid data, the SSPxBUF should be read before the next • Clock Polarity (Idle state of SCKx) byte of data to transfer is written to the SSPxBUF. The • Data Input Sample Phase (middle or end of data Buffer Full bit, BF (SSPxSTAT<0>), indicates when output time) SSPxBUF has been loaded with the received data • Clock Edge (output data on rising/falling edge of (transmission is complete). When the SSPxBUF is read, SCKx) the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt • Clock Rate (Master mode only) is used to determine when the transmission/reception • Slave Select mode (Slave mode only) has completed. The SSPxBUF must be read and/or Each MSSP module consists of a transmit/receive shift written. If the interrupt method is not going to be used, register (SSPxSR) and a buffer register (SSPxBUF). then software polling can be done to ensure that a write The SSPxSR shifts the data in and out of the device, collision does not occur. Example20-1 shows the MSb first. The SSPxBUF holds the data that was loading of the SSP1BUF (SSP1SR) for data written to the SSPxSR until the received data is ready. transmission. Once the 8 bits of data have been received, that byte is The SSPxSR is not directly readable or writable and moved to the SSPxBUF register. Then, the Buffer Full can only be accessed by addressing the SSPxBUF detect bit, BF (SSPxSTAT<0>), and the interrupt flag register. Additionally, the SSPxSTAT register indicates bit, SSPxIF, are set. This double-buffering of the the various status conditions. received data (SSPxBUF) allows the next byte to start reception before reading the data that was just EXAMPLE 20-1: LOADING THE SSP1BUF (SSP1SR) REGISTER LOOP BTFSS SSP1STAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSP1BUF, W ;WREG reg = contents of SSP1BUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSP1BUF ;New data to xmit DS39762F-page 272  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.3.3 ENABLING SPI I/O Any serial port function that is not desired may be overridden by programming the corresponding data To enable the serial port, MSSP Enable bit, SSPEN direction (TRIS) register to the opposite value. (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the 20.3.4 TYPICAL CONNECTION SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as Figure20-2 shows a typical connection between two serial port pins. For the pins to behave as the serial port microcontrollers. The master controller (Processor 1) function, some must have their data direction bits (in initiates the data transfer by sending the SCKx signal. the TRIS register) appropriately programmed as Data is shifted out of both shift registers on their follows: programmed clock edge and latched on the opposite edge of the clock. Both processors should be • SDIx is automatically controlled by the SPI module programmed to the same Clock Polarity (CKP), then • SDOx must have TRISC<5> (or TRISD<4>) bit both controllers would send and receive data at the cleared same time. Whether the data is meaningful (or dummy • SCKx (Master mode) must have TRISC<3> (or data) depends on the application software. This leads TRISD<6>) bit cleared to three scenarios for data transmission: • SCKx (Slave mode) must have TRISC<3> (or • Master sends data–Slave sends dummy data TRISD<6>) bit set • Master sends data–Slave sends data • SSx must have TRISF<7> (or TRISD<7>) bit set • Master sends dummy data–Slave sends data FIGURE 20-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDOx SDIx Serial Input Buffer Serial Input Buffer (SSPxBUF) (SSPxBUF) SDIx SDOx Shift Register Shift Register (SSPxSR) (SSPxSR) MSb LSb MSb LSb Serial Clock SCKx SCKx PROCESSOR 1 PROCESSOR 2  2011 Microchip Technology Inc. DS39762F-page 273

PIC18F97J60 FAMILY 20.3.5 MASTER MODE The clock polarity is selected by appropriately programming the CKP bit (SSPxCON1<4>). This then, The master can initiate the data transfer at any time would give waveforms for SPI communication as because it controls the SCKx. The master determines shown in Figure20-3, Figure20-5 and Figure20-6, when the slave (Processor 2, Figure20-2) will where the MSB is transmitted first. In Master mode, the broadcast data by the software protocol. SPI clock rate (bit rate) is user-programmable to be one In Master mode, the data is transmitted/received as of the following: soon as the SSPxBUF register is written to. If the SPI • FOSC/4 (or TCY) is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR • FOSC/16 (or 4 • TCY) register will continue to shift in the signal present on the • FOSC/64 (or 16 • TCY) SDIx pin at the programmed clock rate. As each byte is • Timer2 output/2 received, it will be loaded into the SSPxBUF register as This allows a maximum data rate (at 40MHz) of if a normal received byte (interrupts and status bits 10.00Mbps. appropriately set). This could be useful in receiver applications as a “Line Activity Monitor” mode. Figure20-3 shows the waveforms for Master mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. FIGURE 20-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDIx (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF Next Q4 Cycle SSPxSR to after Q2 SSPxBUF DS39762F-page 274  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.3.6 SLAVE MODE SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a In Slave mode, the data is transmitted and received as transmitted byte, and becomes a floating output. the external clock pulses appear on SCKx. When the External pull-up/pull-down resistors may be desirable last bit is latched, the SSPxIF interrupt flag bit is set. depending on the application. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock Note 1: When the SPI is in Slave mode with SSx pin line can be observed by reading the SCKx pin. The Idle control enabled (SSPxCON1<3:0>=0100), state is determined by the CKP bit (SSPxCON1<4>). the SPI module will reset if the SSx pin is set to VDD. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This 2: If the SPI is used in Slave mode with CKE external clock must meet the minimum high and low set, then the SSx pin control must be times as specified in the electrical specifications. enabled. While in Sleep mode, the slave can transmit/receive When the SPI module resets, the bit counter is forced data. When a byte is received, the device will wake-up to ‘0’. This can be done by either forcing the SSx pin to from Sleep. a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDOx pin can 20.3.7 SLAVE SELECT be connected to the SDIx pin. When the SPI needs to SYNCHRONIZATION operate as a receiver, the SDOx pin can be configured The SSx pin allows a Synchronous Slave mode. The as an input. This disables transmissions from the SPI must be in Slave mode with SSx pin control SDOx. The SDIx can always be left as an input (SDIx enabled (SSPxCON1<3:0> = 04h). When the SSx pin function) since it cannot create a bus conflict. is low, transmission and reception are enabled and the FIGURE 20-4: SLAVE SYNCHRONIZATION WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 7 bit 0 SDIx bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2 SSPxBUF  2011 Microchip Technology Inc. DS39762F-page 275

PIC18F97J60 FAMILY FIGURE 20-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2 SSPxBUF FIGURE 20-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2 SSPxSR to SSPxBUF DS39762F-page 276  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.3.8 OPERATION IN POWER-MANAGED 20.3.10 BUS MODE COMPATIBILITY MODES Table20-1 shows the compatibility between the In SPI Master mode, module clocks may be operating standard SPI modes and the states of the CKP and at a different speed than when in full-power mode. In CKE control bits. the case of Sleep mode, all clocks are halted. TABLE 20-1: SPI BUS MODES In Idle modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the Control Bits State Standard SPI Mode secondary clock (Timer1 oscillator at 32.768 kHz) or Terminology CKP CKE the INTRC source. See Section3.7 “Clock Sources and Oscillator Switching” for additional information. 0, 0 0 1 In most cases, the speed that the master clocks SPI 0, 1 0 0 data is not important; however, this should be 1, 0 1 1 evaluated for each system. 1, 1 1 0 If MSSP interrupts are enabled, they can wake the There is also an SMP bit which controls when the data controller from Sleep mode, or one of the Idle modes, is sampled. when the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP 20.3.11 SPI CLOCK SPEED AND MODULE interrupts should be disabled. INTERACTIONS If the Sleep mode is selected, all module clocks are Because MSSP1 and MSSP2 are independent halted and the transmission/reception will remain in modules, they can operate simultaneously at different that state until the devices wakes. After the device data rates. Setting the SSPM<3:0> bits of the returns to Run mode, the module will resume SSPxCON1 register determines the rate for the transmitting and receiving data. corresponding module. In SPI Slave mode, the SPI Transmit/Receive Shift An exception is when both modules use Timer2 as a register operates asynchronously to the device. This time base in Master mode. In this instance, any allows the device to be placed in any power-managed changes to the Timer2 operation will affect both MSSP mode and data to be shifted into the SPI modules equally. If different bit rates are required for Transmit/Receive Shift register. When all 8 bits have each module, the user should select one of the other been received, the MSSP interrupt flag bit will be set, three time base options for one of the modules. and if enabled, will wake the device. 20.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer.  2011 Microchip Technology Inc. DS39762F-page 277

PIC18F97J60 FAMILY TABLE 20-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF(1) BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE(1) BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP(1) BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 71 TRISD TRISD7(1) TRISD6(1) TRISD5(1) TRISD4(1) TRISD3 TRISD2 TRISD1 TRISD0 71 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 71 SSP1BUF MSSP1 Receive Buffer/Transmit Register 70 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 70 SSP1STAT SMP CKE D/A P S R/W UA BF 70 SSP2BUF MSSP2 Receive Buffer/Transmit Register 73 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 73 SSP2STAT SMP CKE D/A P S R/W UA BF 73 Legend: Shaded cells are not used by the MSSP module in SPI mode. Note 1: These bits are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. DS39762F-page 278  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.4 I2C Mode 20.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call These are: support) and provides interrupts on Start and Stop bits • MSSPx Control Register 1 (SSPxCON1) in hardware to determine a free bus (multi-master • MSSPx Control Register 2 (SSPxCON2) function). The MSSP module implements the standard • MSSPx Status Register (SSPxSTAT) mode specifications, as well as 7-bit and 10-bit • MSSPx Receive Buffer/Transmit Register addressing. (SSPxBUF) Two pins are used for data transfer: • MSSPx Shift Register (SSPxSR) – Not directly • Serial clock (SCLx) – RC3/SCK1/SCL1 accessible (or RD6/SCK2/SCL2 for 100-pin devices) • MSSPx Address Register (SSPxADD) • Serial data (SDAx) – RC4/SDI1/SDA1 SSPxCON1, SSPxCON2 and SSPxSTAT are the (or RD5/SDI2/SDA2 for 100-pin devices) control and status registers in I2C mode operation. The The user must configure these pins as inputs by setting SSPxCON1 and SSPxCON2 registers are readable the TRISC<4:3> or TRISD<5:4> bits. and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are FIGURE 20-7: MSSP BLOCK DIAGRAM read/write. (I2C™ MODE) Many of the bits in SSPxCON2 assume different functions, depending on whether the module is operat- Internal ing in Master or Slave mode. SSPxCON2<5:1> also Data Bus assume different names in Slave mode. The different Read Write aspects of SSPxCON2 are shown in Register20-5 (for Master mode) and Register20-6 (Slave mode). SCLx SSPxBUF reg SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes Shift are written to or read from. SDAx Clock The SSPxADD register holds the slave device address SSPxSR reg when the MSSP is configured in I2C Slave mode. When MSb LSb the MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator reload Match Detect Addr Match value. Address Mask In receive operations, SSPxSR and SSPxBUF together, create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF SSPxADD reg and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not Set, Reset double-buffered. A write to SSPxBUF will write to both Start and Stop bit Detect S, P bits SSPxBUF and SSPxSR. (SSPxSTAT reg)  2011 Microchip Technology Inc. DS39762F-page 279

PIC18F97J60 FAMILY REGISTER 20-3: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control is enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus-specific inputs 0 = Disable SMBus-specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit (I2C mode only)(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. DS39762F-page 280  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 20-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins(1) 0 = Disables serial port and configures these pins as I/O port pins(1) bit 4 CKP: SCKx Release Control bit In Slave mode: 1 = Releases clock 0 = Holds clock low (clock stretch); used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit addressing with Start and Stop bit interrupts enabled(2) 1110 = I2C Slave mode, 7-bit addressing with Start and Stop bit interrupts enabled(2) 1011 = I2C Firmware Controlled Master mode (slave Idle)(2) 1000 = I2C Master mode, Clock = FOSC/(4 * (SSPADD + 1))(2) 0111 = I2C Slave mode, 10-bit addressing(2) 0110 = I2C Slave mode, 7-bit addressing(2) Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs. 2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.  2011 Microchip Technology Inc. DS39762F-page 281

PIC18F97J60 FAMILY REGISTER 20-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) Unused in Master mode. bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledged 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit(2) 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit(2) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit(2) 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). DS39762F-page 282  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 20-6: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit Unused in Slave mode. bit 5-2 ADMSK5:ADMSK2: Slave Address Mask Select bits 1 = Masking of corresponding bits of SSPxADD is enabled 0 = Masking of corresponding bits of SSPxADD is disabled bit 1 ADMSK1: Slave Address Least Significant Mask Select bit In 7-Bit Addressing mode: 1 = Masking of SSPxADD<1> is only enabled 0 = Masking of SSPxADD<1> is only disabled In 10-Bit Addressing mode: 1 = Masking of SSPxADD<1:0> is enabled 0 = Masking of SSPxADD<1:0> is disabled bit 0 SEN: Stretch Enable bit(1) 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).  2011 Microchip Technology Inc. DS39762F-page 283

PIC18F97J60 FAMILY 20.4.2 OPERATION The SCLx clock input must have a minimum high and low for proper operation. The high and low times of the The MSSP module functions are enabled by setting the I2C specification, as well as the requirement of the MSSP Enable bit, SSPEN (SSPxCON1<5>). MSSP module, are shown in timing Parameter 100 and The SSPxCON1 register allows control of the I2C oper- Parameter 101. ation. Four mode selection bits (SSPxCON1<3:0>) allow one of the following I2C modes to be selected: 20.4.3.1 Addressing • I2C Master mode, Once the MSSP module has been enabled, it waits for clock = (FOSC/4) x (SSPxADD+1) a Start condition to occur. Following the Start condition, • I2C Slave mode (7-bit addressing) the 8 bits are shifted into the SSPxSR register. All • I2C Slave mode (10-bit addressing) incoming bits are sampled with the rising edge of the clock (SCLx) line. The value of register SSPxSR<7:1> • I2C Slave mode (7-bit addressing) with Start and is compared to the value of the SSPxADD register. The Stop bit interrupts enabled address is compared on the falling edge of the eighth • I2C Slave mode (10-bit addressing) with Start and clock (SCLx) pulse. If the addresses match and the BF Stop bit interrupts enabled and SSPOV bits are clear, the following events occur: • I2C Firmware Controlled Master mode, 1. The SSPxSR register value is loaded into the slave is Idle SSPxBUF register. Selection of any I2C mode, with the SSPEN bit set, 2. The Buffer Full bit, BF, is set. forces the SCLx and SDAx pins to be open-drain, 3. An ACK pulse is generated. provided these pins are programmed to inputs by 4. The MSSP Interrupt Flag bit, SSPxIF, is set (and setting the appropriate TRISC or TRISD bits. To ensure the interrupt is generated, if enabled) on the proper operation of the module, pull-up resistors must falling edge of the ninth SCLx pulse. be provided externally to the SCLx and SDAx pins. In 10-Bit Addressing mode, two address bytes need to 20.4.3 SLAVE MODE be received by the slave. The five Most Significant bits In Slave mode, the SCLx and SDAx pins must be (MSbs) of the first address byte specify if this is a 10-bit configured as inputs (TRISC<4:3> or TRISD<5:4> are address. Bit, R/W (SSPxSTAT<2>), must specify a write so the slave device will receive the second set). The MSSP module will override the input state with the output data when required (slave-transmitter). address byte. For a 10-bit address, the first byte would equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the The I2C Slave mode hardware will always generate an two MSbs of the address. The sequence of events for interrupt on an exact address match. In addition, 10-bit addressing is as follows, with Steps 7 through 9 address masking will also allow the hardware to gener- for the slave-transmitter: ate an interrupt for more than one address (up to 31 in 7-bit addressing and up to 63 in 10-bit addressing). 1. Receive first (high) byte of address (bits, Through the mode select bits, the user can also choose SSPxIF, BF and UA, are set). to interrupt on Start and Stop bits. 2. Update the SSPxADD register with second (low) byte of address (clears bit, UA, and releases the When an address is matched, or the data transfer after SCLx line). an address match is received, the hardware auto- matically will generate the Acknowledge (ACK) pulse 3. Read the SSPxBUF register (clears bit, BF) and and load the SSPxBUF register with the received value clear flag bit, SSPxIF. currently in the SSPxSR register. 4. Receive second (low) byte of address (bits, SSPxIF, BF and UA, are set). Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: 5. Update the SSPxADD register with the first (high) byte of address. If match releases SCLx • The Buffer Full bit, BF (SSPxSTAT<0>), was set line, this will clear bit, UA. before the transfer was received. 6. Read the SSPxBUF register (clears bit, BF) and • The MSSP Overflow bit, SSPOV (SSPxCON1<6>), clear flag bit, SSPxIF. was set before the transfer was received. 7. Receive Repeated Start condition. In this case, the SSPxSR register value is not loaded 8. Receive first (high) byte of address (bits, into the SSPxBUF, but bit, SSPxIF, is set. The BF bit is SSPxIF and BF, are set). cleared by reading the SSPxBUF register, while bit, 9. Read the SSPxBUF register (clears bit, BF) and SSPOV, is cleared through software. clear flag bit, SSPxIF. DS39762F-page 284  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.4.3.2 Address Masking In 10-Bit Addressing mode, bits, ADMSK<5:2>, mask the corresponding address bits in the SSPxADD regis- Masking an address bit causes that bit to become a ter. In addition, ADMSK1 simultaneously masks the two “don’t care”. When one address bit is masked, two LSbs of the address (SSPxADD<1:0>). For any addresses will be Acknowledged and cause an ADMSK bits that are active (ADMSK<n>=1), the cor- interrupt. It is possible to mask more than one address responding address bit is ignored (SSPxADD<n>=x). bit at a time, which makes it possible to Acknowledge Also note, that although in 10-Bit Addressing mode, the up to 31 addresses in 7-bit mode, and up to upper address bits re-use part of the SSPxADD regis- 63addresses in 10-bit mode (see Example20-2). ter bits. The address mask bits do not interact with The I2C Slave behaves the same way whether address those bits; they only affect the lower address bits. masking is used or not. However, when address masking is used, the I2C slave can Acknowledge Note1: ADMSK1 masks the two Least multiple addresses and cause interrupts. When this Significant bits of the address. occurs, it is necessary to determine which address 2: The two Most Significant bits of the caused the interrupt by checking SSPxBUF. address are not affected by address In 7-Bit Addressing mode, address mask bits, masking. ADMSK<5:1> (SSPxCON2<5:1>), mask the corre- sponding address bits in the SSPxADD register. For any ADMSK bits that are set (ADMSK<n>=1), the corre- sponding address bit is ignored (SSPxADD<n>=x). For the module to issue an address Acknowledge, it is sufficient to match only on addresses that do not have an active address mask. EXAMPLE 20-2: ADDRESS MASKING EXAMPLES 7-Bit Addressing: SSPxADD<7:1> = A0h (1010000) (SSPxADD<0> is assumed to be ‘0’) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh 10-Bit Addressing: SSPxADD<7:0> = A0h (10100000) (the two MSb of the address are ignored in this example since they are not affected by masking) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh  2011 Microchip Technology Inc. DS39762F-page 285

PIC18F97J60 FAMILY 20.4.3.3 Reception 20.4.3.4 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set and address match occurs, the R/W bit of the SSPxSTAT an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into register is set. The received address is loaded into the the SSPxBUF register and the SDAx line is held low SSPxBUF register. The ACK pulse will be sent on the (ACK). ninth bit and pin RC3 or RD6 is held low, regardless of SEN (see Section20.4.4 “Clock Stretching” for more When the address byte overflow condition exists, then details). By stretching the clock, the master will be unable the no Acknowledge (ACK) pulse is given. An overflow to assert another clock pulse until the slave is done condition is defined as either bit, BF (SSPxSTAT<0>), preparing the transmit data. The transmit data must be is set, or bit, SSPOV (SSPxCON1<6>), is set. loaded into the SSPxBUF register which also loads the An MSSP interrupt is generated for each data transfer SSPxSR register. Then, pin, RC3 or RD6, should be byte. The interrupt flag bit, SSPxIF, must be cleared in enabled by setting bit, CKP (SSPxCON1<4>). The eight software. The SSPxSTAT register is used to determine data bits are shifted out on the falling edge of the SCLx the status of the byte. input. This ensures that the SDAx signal is valid during If SEN is enabled (SSPxCON2<0> = 1), SCKx/SCLx the SCLx high time (Figure20-10). (RC3 or RD6) will be held low (clock stretch) following The ACK pulse from the master-receiver is latched on each data transfer. The clock must be released by the rising edge of the ninth SCLx input pulse. If the SDAx setting bit, CKP (SSPxCON1<4>). See Section20.4.4 line is high (not ACK), then the data transfer is complete. “Clock Stretching” for more details. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPxSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, pin, RC3 or RD6, must be enabled by setting bit, CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. DS39762F-page 286  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 2 FIGURE 20-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R D5 3 D6 2 D7 1 K C A 9 0 D 8 1 D 7 D2 6 ata D3 5 D e eceiving D4 4 n softwarF is read R D6D5 23 Cleared iSSPxBU 7 D 1 = 0 ACK 9 W 8 R/ A1 7 A2 6 = )0 ddress A3 5 n SEN A e Receiving A5A4 34 set to ‘’ wh0 e A7A6DAx CLx12S SPxIF (PIR1<3> or PIR3<7>) F (SSPxSTAT<0>) SPOV (SSPxCON1<6>) KP(CKP does not r S S S B S C  2011 Microchip Technology Inc. DS39762F-page 287

PIC18F97J60 FAMILY 2 FIGURE 20-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 2 D 6 ata D3 5 D g eivin D4 4 c e R D5 3 D6 2 7 D 1 K C A 9 D0 8 pt. u D1 7 err nt D2 6 e an i s ata D3 5 cau Receiving D D6D5D4 234 Cleared in softwareSSPxBUF is read cknowledged and A e D7 1 ’).0 X will b R/W = 0 ACK 89 a ‘’ or a ‘1 5.X.A3.X. Receiving Address A7A6A5XA3XXSDAx SCLx1234567S SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP(CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can be either x 2:In this example, an address equal to A7.A6.A DS39762F-page 288  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 2 FIGURE 20-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S K F I AC 9 PxI S D0 8 m S o Data D1 7 Fr Transmitting D5D4D3D2 3456 eared in software UF is written in software et in software D6 2 Cl SSPxB KP is s C D7 1 R S CK F I A 9 PxI S S D0 8 m o Fr D1 7 Transmitting Data D6D5D4D3D2 23456 F Cleared in software SSPxBUF is written in software CKP is set in software D7 1 PxI S w S SCLx held lowhile CPUresponds to K C A 9 0 = W 8 R/ 1 A 7 2 ess A 6 Addr A3 5 g n eivi A4 4 ec R A5 3 >) 7 A6A7 12 Data in sampled > or PIR3< 0>) 3 < < T 1 A R T DAx CLx S SPxIF (PI F (SSPxS KP S S S B C  2011 Microchip Technology Inc. DS39762F-page 289

PIC18F97J60 FAMILY FIGURE 20-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 e a Byte D3D2 56 n softwar eceive Dat D5D4 34 Cleared i R D6 2 7 D 1 K AC 9 0 D 8 untilDD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPxADD is updated with highbyte of address d low SPxA D7 1 Clock is helupdate of Staken place ACK0 89 Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACK11110A9A8A7A6A5A4A3A2A1ADAx CLx1234567891234567S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPxADD needs to bewhen SSPxADD is updatedupdatedwith low byte of address UA is set indicating thatSSPxADD needs to beupdated KP(CKP does not reset to ‘’ when SEN = )00 S S S B S U C DS39762F-page 290  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 20-12: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. 0 D 8 1 D 7 e Byte 3D2 6 softwar a D 5 n eceive Dat D5D4 34 Cleared i R D6 2 7 D 1 K AC 9 D0 8 Clock is held low untilClock is held low untilupdate of SSPxADD has update of SSPxADD has taken placetaken place Receive First Byte of AddressReceive Second Byte of AddressReceive Data ByteR/W = 0 ACKACK11110A9A8A7A6A5XA3A2XXD7D6D5D4D3D1D2SDAx SCLx1234567891234567891234576S SSPxIF (PIR1<3> or PIR3<7>) Cleared in software Cleared in softwareCleared in software BF (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SSPOV (SSPxCON1<6>) UA (SSPxSTAT<1>) UA is set indicating thatCleared by hardware whenCleared by hardwarethe SSPxADD needs to beSSPxADD is updated with highwhen SSPxADD is updatedupdatedbyte of addresswith low byte of address UA is set indicating thatSSPxADD needs to beupdated CKP(CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can be either a ‘’ or a ‘’).x10 2:In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt. 3:Note that the Most Significant bits of the address are not affected by the bit masking.  2011 Microchip Technology Inc. DS39762F-page 291

PIC18F97J60 FAMILY 2 FIGURE 20-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCLx low w Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressR/W = Transmitting Data Byte1 11110A8A9ACKD7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPxBUFWrite of SSPxBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPxADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPxADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with lowbyte of address UA is set indicating thatSSPxADD needs to beupdated R/ 8 h be Receive First Byte of Address 11110A9A8DAx CLx1234567S SPxIF (PIR1<3> or PIR3<7>) F (SSPxSTAT<0>) SSPxBUF is written witcontents of SSPxSR A (SSPxSTAT<1>) UA is set indicating thatthe SSPxADD needs to updated KP (SSPxCON1<4>) S S S B U C DS39762F-page 292  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.4.4 CLOCK STRETCHING 20.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The 7-Bit Slave Transmit mode implements clock The SEN bit (SSPxCON2<0>) allows clock stretching stretching by clearing the CKP bit after the falling edge of the ninth clock, if the BF bit is clear. This occurs to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data regardless of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmission is allowed to continue. By holding the 20.4.4.1 Clock Stretching for 7-Bit Slave SCLx line low, the user has time to service the ISR Receive Mode (SEN = 1) and load the contents of the SSPxBUF before the In 7-Bit Slave Receive mode, on the falling edge of the master device can initiate another transmit sequence ninth clock at the end of the ACK sequence, if the BF (see Figure20-10). bit is set, the CKP bit in the SSPxCON1 register is Note1: If the user loads the contents of automatically cleared, forcing the SCLx output to be SSPxBUF, setting the BF bit before the held low. The CKP being cleared to ‘0’ will assert the falling edge of the ninth clock, the CKP bit SCLx line low. The CKP bit must be set in the user’s will not be cleared and clock stretching ISR before reception is allowed to continue. By holding will not occur. the SCLx line low, the user has time to service the ISR 2: The CKP bit can be set in software and read the contents of the SSPxBUF before the regardless of the state of the BF bit. master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure20-15). 20.4.4.4 Clock Stretching for 10-Bit Slave Transmit Mode Note1: If the user reads the contents of the SSPxBUF before the falling edge of the In 10-Bit Slave Transmit mode, clock stretching is ninth clock, thus clearing the BF bit, the controlled during the first two address sequences by CKP bit will not be cleared and clock the state of the UA bit, just as it is in 10-Bit Slave stretching will not occur. Receive mode. The first two addresses are followed by a third address sequence which contains the 2: The CKP bit can be set in software regard- high-order bits of the 10-bit address and the R/W bit less of the state of the BF bit. The user set to ‘1’. After the third address sequence is should be careful to clear the BF bit in the performed, the UA bit is not set, the module is now ISR before the next receive sequence in configured in Transmit mode and clock stretching is order to prevent an overflow condition. controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure20-13). 20.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPxADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPxADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence.  2011 Microchip Technology Inc. DS39762F-page 293

PIC18F97J60 FAMILY 20.4.4.5 Clock Synchronization and already asserted the SCLx line. The SCLx output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx. This When the CKP bit is cleared, the SCLx output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, clearing the CKP bit will not assert the minimum high time requirement for SCLx (see SCLx output low until the SCLx output is already Figure20-14). sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 20-14: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX DX – 1 SCLx Master device asserts clock CKP Master device deasserts clock WR SSPxCON1 DS39762F-page 294  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 2 FIGURE 20-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R D5 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPxBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 ess ddr A3 5 A g eivin A4 4 c e R A5 3 >) A6 2 R3<7 >) A7 1 > or PI 0>) ON1<6 DAx CLxS SPxIF (PIR1<3 F (SSPxSTAT< SPOV (SSPxC KP S S S B S C  2011 Microchip Technology Inc. DS39762F-page 295

PIC18F97J60 FAMILY FIGURE 20-16: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) Clock is not held lowbecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D 8 1 D 7 e Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared in softwareCleared in softwar Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPxADD register before thefalling edge of the ninth clock will have no effecton UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPxADD has taken place Receive Second Byte of Address= 0 A7A6A5A4A3A2A1A0CK 912345678 Cleared in software Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with lowbyte of address after falling edgeof ninth clock UA is set indicating thatSSPxADD needs to beupdated Note:An update of the SSPxADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. Receive First Byte of AddressR/W DAx11110A9A8A CLx12345678S SPxIF (PIR1<3> or PIR3<7>) Cleared in software F (SSPxSTAT<0>) SSPxBUF is written withcontents of SSPxSR SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatthe SSPxADD needs to beupdated KP S S S B S U C DS39762F-page 296  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPxSR is SUPPORT transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK The addressing procedure for the I2C bus is such that bit), the SSPxIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the the master. The exception is the general call address, interrupt can be checked by reading the contents of the which can address all devices. When this address is SSPxBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device-specific or a general call address. Acknowledge. In 10-Bit Addressing mode, the SSPxADD is required The general call address is one of eight addresses to be updated for the second half of the address to reserved for specific purposes by the I2C protocol. It match, and the UA bit is set (SSPxSTAT<1>). If the consists of all ‘0’s with R/W = 0. general call address is sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing The general call address is recognized when the mode, then the second half of the address is not nec- General Call Enable bit, GCEN, is enabled essary, the UA bit will not be set and the slave will begin (SSPxCON2<7> set). Following a Start bit detect, 8 bits receiving data after the Acknowledge (Figure20-17). are shifted into the SSPxSR and the address is compared against the SSPxADD. It is also compared to the general call address and fixed in hardware. FIGURE 20-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK General Call Address SDAx ACK D7 D6 D5 D4 D3 D2 D1 D0 SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPxIF BF (SSPxSTAT<0>) Cleared in software SSPxBUF is read SSPOV (SSPxCON1<6>) ‘0’ GCEN (SSPxCON2<7>) ‘1’  2011 Microchip Technology Inc. DS39762F-page 297

PIC18F97J60 FAMILY 20.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPxCON1 and by setting of events. For instance, the user is not the SSPEN bit. In Master mode, the SCLx and SDAx allowed to initiate a Start condition and lines are manipulated by the MSSP hardware. immediately write the SSPxBUF register to initiate transmission before the Start Master mode of operation is supported by interrupt condition is complete. In this case, the generation on the detection of the Start and Stop con- SSPxBUF will not be written to and the ditions. The Stop (P) and Start (S) bits are cleared from WCOL bit will be set, indicating that a write a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the to the SSPxBUF did not occur. bus is Idle, with both the S and P bits clear. The following events will cause the MSSP Interrupt In Firmware Controlled Master mode, user code Flag bit, SSPxIF, to be set (and MSSP interrupt, if conducts all I2C bus operations based on Start and enabled): Stop bit conditions. • Start Condition Once Master mode is enabled, the user has six • Stop Condition options. • Data Transfer Byte Transmitted/Received 1. Assert a Start condition on SDAx and SCLx. • Acknowledge Transmit 2. Assert a Repeated Start condition on SDAx and • Repeated Start SCLx. 3. Write to the SSPxBUF register, initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDAx and SCLx. 2 FIGURE 20-18: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM<3:0> Data Bus SSPxADD<6:0> Read Write SSPxBUF Baud Rate Generator SDAx Shift SDAx In Clock ct e SSPxSR Detce) MSb LSb L ur e Oo abl WCk s SCLx Receive En StAarcGtk bneiont,we Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCLx In Write Collision Detect Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1) Clock Arbitration Set SSPxIF, BCLxIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPxCON2) End of XMIT/RCV DS39762F-page 298  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPxCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPxIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPxBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDAx, while SCLx outputs the serial clock. The 4. Address is shifted out on the SDAx pin until all first byte transmitted contains the slave address of the 8bits are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPxCON2 register (SSPxCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the end of a serial transfer. SSPxIF bit. In Master Receive mode, the first byte transmitted 7. The user loads the SSPxBUF with eight bits of contains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out on the SDAx pin until all 8 bits logic ‘1’. Thus, the first byte transmitted is a 7-bit slave are transmitted. address followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDAx, while SCLx outputs slave device and writes its value into the the serial clock. Serial data is received, 8 bits at a time. SSPxCON2 register (SSPxCON2<6>). After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the 10. The MSSP module generates an interrupt at the beginning and end of transmission. end of the ninth clock cycle by setting the SSPxIF bit. The Baud Rate Generator used for the SPI mode 11. The user generates a Stop condition by setting operation is used to set the SCLx clock frequency for either 100kHz, 400kHz or 1MHz I2C operation. See the Stop Enable bit, PEN (SSPxCON2<2>). Section20.4.7 “Baud Rate” for more detail. 12. Interrupt is generated once the Stop condition is complete.  2011 Microchip Technology Inc. DS39762F-page 299

PIC18F97J60 FAMILY 20.4.7 BAUD RATE 20.4.7.1 Baud Rate and Module In I2C Master mode, the Baud Rate Generator (BRG) Interdependence reload value is placed in the lower 7 bits of the Because MSSP1 and MSSP2 are independent, they SSPxADD register (Figure20-19). When a write can operate simultaneously in I2C Master mode at occurs to SSPxBUF, the Baud Rate Generator will different baud rates. This is done by using different automatically begin counting. The BRG counts down to BRG reload values for each module. 0 and stops until another reload has taken place. The Because this mode derives its basic clock source from BRG count is decremented twice per instruction cycle the system clock, any changes to the clock will affect (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the both modules in the same proportion. It may be BRG is reloaded automatically. possible to change one or both baud rates back to a Once the given operation is complete (i.e., transmis- previous value by changing the BRG reload value. sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCLx pin will remain in its last state. Table20-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. FIGURE 20-19: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPxADD<6:0> SSPM<3:0> Reload Reload SCLx Control CLKO BRG Down Counter FOSC/4 TABLE 20-3: I2C™ CLOCK RATE w/BRG FSCL FOSC BRG Value (2 Rollovers of BRG) 41.667MHz 19h 400kHz(1) 41.667MHz 67h 100kHz 31.25MHz 13h 400kHz(1) 31.25MHz 4Dh 100kHz 20.833MHz 09h 400kHz(1) 20.833MHz 33h 100kHz Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. DS39762F-page 300  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.4.7.2 Clock Arbitration SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCLx high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCLx pin (SCLx allowed to float high). event that the clock is held low by an external device When the SCLx pin is allowed to float high, the Baud (Figure20-20). Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 20-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX DX – 1 SCLx deasserted but slave holds SCLx allowed to transition high SCLx low (clock arbitration) SCLx BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCLx is sampled high, reload takes place and BRG starts its count BRG Reload  2011 Microchip Technology Inc. DS39762F-page 301

PIC18F97J60 FAMILY 20.4.8 I2C MASTER MODE START Note: If, at the beginning of the Start condition, CONDITION TIMING the SDAx and SCLx pins are already sam- To initiate a Start condition, the user sets the Start pled low, or if during the Start condition, Enable bit, SEN (SSPxCON2<0>). If the SDAx and the SCLx line is sampled low before the SCLx pins are sampled high, the Baud Rate Generator SDAx line is driven low, a bus collision is reloaded with the contents of SSPxADD<6:0> and occurs. The Bus Collision Interrupt Flag, starts its count. If SCLx and SDAx are both sampled BCLxIF, is set, the Start condition is high when the Baud Rate Generator times out (TBRG), aborted and the I2C module is reset into its the SDAx pin is driven low. The action of the SDAx Idle state. being driven low while SCLx is high is the Start condi- 20.4.8.1 WCOL Status Flag tion and causes the S bit (SSPxSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded If the user writes the SSPxBUF when a Start sequence with the contents of SSPxADD<6:0> and resumes its is in progress, the WCOL is set and the contents of the count. When the Baud Rate Generator times out buffer are unchanged (the write doesn’t occur). (TBRG), the SEN bit (SSPxCON2<0>) will be auto- Note: Because queueing of events is not matically cleared by hardware. The Baud Rate allowed, writing to the lower 5 bits of Generator is suspended, leaving the SDAx line held SSPxCON2 is disabled until the Start low and the Start condition is complete. condition is complete. FIGURE 20-21: FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here SDAx = 1, At completion of Start bit, SCLx = 1 hardware clears SEN bit and sets SSPxIF bit TBRG TBRG Write to SSPxBUF occurs here 1st bit 2nd bit SDAx TBRG SCLx TBRG S DS39762F-page 302  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPxCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDAx is sampled low when SCLx the SCLx pin is asserted low. When the SCLx pin is goes from low-to-high. sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<6:0> and begins counting. • SCLx goes low before SDAx is The SDAx pin is released (brought high) for one Baud asserted low. This may indicate that Rate Generator count (TBRG). When the Baud Rate another master is attempting to Generator times out, if SDAx is sampled high, the SCLx transmit a data ‘1’. pin will be deasserted (brought high). When SCLx is Immediately following the SSPxIF bit getting set, the user sampled high, the Baud Rate Generator is reloaded may write the SSPxBUF with the 7-bit address in 7-bit with the contents of SSPxADD<6:0> and begins count- mode or the default first address in 10-bit mode. After the ing. SDAx and SCLx must be sampled high for one first eight bits are transmitted and an ACK is received, the TBRG. This action is then followed by assertion of the user may then transmit an additional eight bits of address SDAx pin (SDAx = 0) for one TBRG while SCLx is high. (10-bit mode) or eight bits of data (7-bit mode). Following this, the RSEN bit (SSPxCON2<1>) will be automatically cleared and the Baud Rate Generator will 20.4.9.1 WCOL Status Flag not be reloaded, leaving the SDAx pin held low. As If the user writes the SSPxBUF when a Repeated Start soon as a Start condition is detected on the SDAx and sequence is in progress, the WCOL is set and the SCLx pins, the S bit (SSPxSTAT<3>) will be set. The contents of the buffer are unchanged (the write doesn’t SSPxIF bit will not be set until the Baud Rate Generator occur). has timed out. Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPxCON2 is disabled until the Repeated Start condition is complete. FIGURE 20-22: REPEATED START CONDITION WAVEFORM S bit set by hardware SDAx = 1, At completion of Start bit, Write to SSPxCON2 occurs here:SDAx = 1, SCLx = 1 hardware clears RSEN bit SCLx (no change) and sets SSPxIF TBRG TBRG TBRG SDAx 1st bit RSEN bit set by hardware on falling edge of ninth clock, Write to SSPxBUF occurs here end of Xmit TBRG SCLx TBRG Sr = Repeated Start  2011 Microchip Technology Inc. DS39762F-page 303

PIC18F97J60 FAMILY 20.4.10 I2C MASTER MODE The user should verify that the WCOL is clear after TRANSMISSION each write to SSPxBUF to ensure the transfer is correct. In all cases, WCOL must be cleared in Transmission of a data byte, a 7-bit address or the software. other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will 20.4.10.3 ACKSTAT Status Flag set the Buffer Full flag bit, BF, and allow the Baud Rate In Transmit mode, the ACKSTAT bit (SSPxCON2<6>) Generator to begin counting and start the next trans- is cleared when the slave has sent an Acknowledge mission. Each bit of address/data will be shifted out (ACK=0) and is set when the slave does not Acknowl- onto the SDAx pin after the falling edge of SCLx is edge (ACK = 1). A slave sends an Acknowledge when asserted (see data hold time specification it has recognized its address (including a general call), Parameter106). SCLx is held low for one Baud Rate or when the slave has properly received its data. Generator rollover count (TBRG). Data should be valid before SCLx is released high (see data setup time 20.4.11 I2C MASTER MODE RECEPTION specification Parameter107). When the SCLx pin is released high, it is held that way for TBRG. The data on Master mode reception is enabled by programming the the SDAx pin must remain stable for that duration and Receive Enable bit, RCEN (SSPxCON2<3>). some hold time after the next falling edge of SCLx. Note: The MSSP module must be in an Idle After the eighth bit is shifted out (the falling edge of the state before the RCEN bit is set or the eighth clock), the BF flag is cleared and the master RCEN bit will be disregarded. releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth The Baud Rate Generator begins counting and on each bit time if an address match occurred, or if data was rollover. The state of the SCLx pin changes received properly. The status of ACK is written into the (high-to-low/low-to-high) and data is shifted into the ACKDT bit on the falling edge of the ninth clock. If the SSPxSR. After the falling edge of the eighth clock, the master receives an Acknowledge, the Acknowledge receive enable flag is automatically cleared, the con- Status bit, ACKSTAT, is cleared; if not, the bit is set. tents of the SSPxSR are loaded into the SSPxBUF, the After the ninth clock, the SSPxIF bit is set and the BF flag bit is set, the SSPxIF flag bit is set and the Baud master clock (Baud Rate Generator) is suspended until Rate Generator is suspended from counting, holding the next data byte is loaded into the SSPxBUF, leaving SCLx low. The MSSP is now in Idle state awaiting the SCLx low and SDAx unchanged (Figure20-23). next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can After the write to the SSPxBUF, each bit of the address then send an Acknowledge bit at the end of reception will be shifted out on the falling edge of SCLx until all by setting the Acknowledge Sequence Enable bit, seven address bits and the R/W bit are completed. On ACKEN (SSPxCON2<4>). the falling edge of the eighth clock, the master will deassert the SDAx pin, allowing the slave to respond 20.4.11.1 BF Status Flag with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the In receive operation, the BF bit is set when an address address was recognized by a slave. The status of the or data byte is loaded into SSPxBUF from SSPxSR. It ACK bit is loaded into the ACKSTAT status bit is cleared when the SSPxBUF register is read. (SSPxCON2<6>). Following the falling edge of the 20.4.11.2 SSPOV Status Flag ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator In receive operation, the SSPOV bit is set when 8 bits is turned off until another write to the SSPxBUF takes are received into the SSPxSR and the BF flag bit is place, holding SCLx low and allowing SDAx to float. already set from a previous reception. 20.4.10.1 BF Status Flag 20.4.11.3 WCOL Status Flag In Transmit mode, the BF bit (SSPxSTAT<0>) is set If the user writes the SSPxBUF when a receive is when the CPU writes to SSPxBUF, and is cleared when already in progress (i.e., SSPxSR is still shifting in a all 8 bits are shifted out. data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). 20.4.10.2 WCOL Status Flag If the user writes to the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL is set and the contents of the buf- fer are unchanged (the write doesn’t occur) after 2TCY after the SSPxBUF write. If SSPxBUF is rewritten within 2 TCY, the WCOL bit is set and SSPxBUF is updated. This may result in a corrupted transfer. DS39762F-page 304  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 20-23: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 AT in ON2 = oftware STxC P n s ACKSSP ared i K e >) AC 9 Cl 6 N2< D0 8 e slave, clear ACKSTAT bit (SSPxCO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared in software service routinfrom MSSP interrupt SSPxBUF is written in software om D7 1 xIF Fr ow SP = 0 SCLx held lwhile CPUsponds to S CK re = 0 A W 9 are R/W A1 ess and R/ 78 d by hardw ave A2 addr 6 eare PxCON2<0> (SEN = ),1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPxBUF written with 7-bit start transmit 12345 Cleared in software SSPxBUF written After Start condition, SEN cl Sn Write SStart co S T<0>) A T S x F SP SDAx SCLx SSPxI BF (S SEN PEN R/W  2011 Microchip Technology Inc. DS39762F-page 305

PIC18F97J60 FAMILY FIGURE 20-24: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) pt Write to SSPxCON2<4>to start Acknowledge sequenceSDAx = ACKDT (SSPxCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from Master,er configured as a receiverSDAx = ACKDT = SDAx = ACKDT = 10ogramming SSPxCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK Bus masterACK is not sentterminatestransfer967895876512343124PSet SSPxIF at endData shifted in on falling edge of CLKof receiveSet SSPxIF interruat end of Acknow-Set SSPxIF interruptSet SSPxIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPxSTAT<4>)Cleared insoftwareand SSPxIF Last bit is shifted into SSPxSR andcontents are unloaded into SSPxBUF SSPOV is set becauseSSPxBUF is still full stpr Maby ACK from Slave R/W = 1A1ACK 798 e, Write to SSPxCON2<0> (SEN = ),1begin Start condition SEN = 0Write to SSPxBUF occurs herstart XMIT Transmit Address to Slave A7A6A5A4A3A2SDAx 631245SCLxS SSPxIF Cleared in softwareSDAx = , SCLx = 01while CPU responds to SSPxIF BF (SSPxSTAT<0>) SSPOV ACKEN DS39762F-page 306  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.4.12 ACKNOWLEDGE SEQUENCE 20.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDAx pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPxCON2<2>). At the end of a (SSPxCON2<4>). When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the fall- pulled low and the contents of the Acknowledge data bit ing edge of the ninth clock. When the PEN bit is set, the are presented on the SDAx pin. If the user wishes to master will assert the SDAx line low. When the SDAx generate an Acknowledge, then the ACKDT bit should line is sampled low, the Baud Rate Generator is be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate before starting an Acknowledge sequence. The Baud Generator times out, the SCLx pin will be brought high Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count) (TBRG) and the SCLx pin is deasserted (pulled high). later, the SDAx pin will be deasserted. When the SDAx When the SCLx pin is sampled high (clock arbitration), pin is sampled high while SCLx is high, the P bit the Baud Rate Generator counts for TBRG. The SCLx pin (SSPxSTAT<4>) is set. A TBRG later, the PEN bit is is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure20-26). matically cleared, the Baud Rate Generator is turned off 20.4.13.1 WCOL Status Flag and the MSSP module then goes into Idle mode (Figure20-25). If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the 20.4.12.1 WCOL Status Flag contents of the buffer are unchanged (the write doesn’t If the user writes the SSPxBUF when an Acknowledge occur). sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 20-25: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPxCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDAx D0 ACK SCLx 8 9 SSPxIF Cleared in Cleared in software SSPxIF set at software SSPxIF set at the end the end of receive of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 20-26: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPxCON2, SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG set PEN after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Falling edge of PEN bit (SSPxCON2<2>) is cleared by 9th clock hardware and the SSPxIF bit is set TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period.  2011 Microchip Technology Inc. DS39762F-page 307

PIC18F97J60 FAMILY 20.4.14 SLEEP OPERATION 20.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master 20.4.15 EFFECTS OF A RESET outputs a ‘1’ on SDAx, by letting SDAx float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCLx pin floats current transfer. high, data should be stable. If the expected data on SDAx is a ‘1’ and the data sampled on the SDAx 20.4.16 MULTI-MASTER MODE pin=0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF In Multi-Master mode, the interrupt generation on the and reset the I2C port to its Idle state (Figure20-27). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDAx and SCLx lines are deasserted and be taken when the P bit (SSPxSTAT<4>) is set, or the the SSPxBUF can be written to. When the user services bus is Idle, with both the S and P bits clear. When the the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the MSSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDAx line must be If a Start, Repeated Start, Stop or Acknowledge condition monitored for arbitration to see if the signal level is the was in progress when the bus collision occurred, the expected output level. This check is performed in condition is aborted, the SDAx and SCLx lines are hardware with the result placed in the BCLxIF bit. deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services The states where arbitration can be lost are: the bus collision Interrupt Service Routine and if the I2C • Address Transfer bus is free, the user can resume communication by • Data Transfer asserting a Start condition. • A Start Condition The master will continue to monitor the SDAx and SCLx • A Repeated Start Condition pins. If a Stop condition occurs, the SSPxIF bit will be set. • An Acknowledge Condition A write to the SSPxBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 20-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDAx. While SCLx is high, Data changes SDAx line pulled low data doesn’t match what is driven while SCLx = 0 by another source by the master. Bus collision has occurred. SDAx released by master SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF DS39762F-page 308  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.4.17.1 Bus Collision During a Start If the SDAx pin is sampled low during this count, the Condition BRG is reset and the SDAx line is asserted early (Figure20-30). If, however, a ‘1’ is sampled on the During a Start condition, a bus collision occurs if: SDAx pin, the SDAx pin is asserted low at the end of a) SDAx or SCLx are sampled low at the beginning the BRG count. The Baud Rate Generator is then of the Start condition (Figure20-28). reloaded and counts down to 0. If the SCLx pin is b) SCLx is sampled low before SDAx is asserted sampled as ‘0’ during this time, a bus collision does not low (Figure20-29). occur. At the end of the BRG count, the SCLx pin is asserted low. During a Start condition, both the SDAx and the SCLx pins are monitored. Note: The reason that bus collision is not a fac- tor during a Start condition is that no two If the SDAx pin is already low, or the SCLx pin is bus masters can assert a Start condition already low, then all of the following occur: at the exact same time. Therefore, one • the Start condition is aborted; master will always assert SDAx before the • the BCLxIF flag is set; and other. This condition does not cause a bus • the MSSP module is reset to its Idle state collision because the two masters must be (Figure20-28). allowed to arbitrate the first address The Start condition begins with the SDAx and SCLx following the Start condition. If the address pins deasserted. When the SDAx pin is sampled high, is the same, arbitration must be allowed to the Baud Rate Generator is loaded from continue into the data portion, Repeated SSPxADD<6:0> and counts down to 0. If the SCLx pin Start or Stop conditions. is sampled low while SDAx is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 20-28: BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDAx = 1, SCLx = 1 MSSP module reset into Idle state. SEN SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because BCLxIF SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared in software S SSPxIF SSPxIF and BCLxIF are cleared in software  2011 Microchip Technology Inc. DS39762F-page 309

PIC18F97J60 FAMILY FIGURE 20-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start SCLx sequence if SDAx = 1, SCLx = 1 SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared in software S ‘0’ ‘0’ SSPxIF ‘0’ ‘0’ FIGURE 20-30: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Set SSPxIF Less than TBRG TBRG SDAx SDAx pulled low by other master. Reset BRG and assert SDAx. SCLx S SCLx pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 BCLxIF ‘0’ S SSPxIF SDAx = 0, SCLx = 1, Interrupts cleared set SSPxIF in software DS39762F-page 310  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 20.4.17.2 Bus Collision During a Repeated reloaded and begins counting. If SDAx goes from Start Condition high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at During a Repeated Start condition, a bus collision exactly the same time. occurs if: If SCLx goes from high-to-low before the BRG times a) A low level is sampled on SDAx when SCLx out and SDAx has not already been asserted, a bus goes from low level to high level. collision occurs. In this case, another master is b) SCLx goes low before SDAx is asserted low, attempting to transmit a data ‘1’ during the Repeated indicating that another master is attempting to Start condition (see Figure20-32). transmit a data ‘1’. If, at the end of the BRG time-out, both SCLx and SDAx When the user deasserts SDAx and the pin is allowed are still high, the SDAx pin is driven low and the BRG to float high, the BRG is loaded with SSPxADD<6:0> is reloaded and begins counting. At the end of the and counts down to 0. The SCLx pin is then deasserted count, regardless of the status of the SCLx pin, the and when sampled high, the SDAx pin is sampled. SCLx pin is driven low and the Repeated Start If SDAx is low, a bus collision has occurred (i.e., another condition is complete. master is attempting to transmit a data ‘0’, see Figure20-31). If SDAx is sampled high, the BRG is FIGURE 20-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared in software S ‘0’ SSPxIF ‘0’ FIGURE 20-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx SCLx goes low before SDAx, set BCLxIF. Release SDAx and SCLx. BCLxIF Interrupt cleared in software RSEN S ‘0’ SSPxIF  2011 Microchip Technology Inc. DS39762F-page 311

PIC18F97J60 FAMILY 20.4.17.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low. Condition When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with a) After the SDAx pin has been deasserted and SSPxADD<6:0> and counts down to 0. After the BRG allowed to float high, SDAx is sampled low after times out, SDAx is sampled. If SDAx is sampled low, a the BRG has timed out. bus collision has occurred. This is due to another b) After the SCLx pin is deasserted, SCLx is master attempting to drive a data ‘0’ (Figure20-33). If sampled low before SDAx goes high. the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure20-34). FIGURE 20-33: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDAx sampled low after TBRG, set BCLxIF SDAx SDAx asserted low SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ FIGURE 20-34: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes low before SDAx goes high, Assert SDAx set BCLxIF SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ DS39762F-page 312  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 20-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR2 OSCFIF CMIF ETHIF r BCL1IF — TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE — TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP — TMR3IP CCP2IP 71 PIR3 SSP2IF(1) BCL2IF(1) RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE(1) BCL2IE(1) RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP(1) BCL2IP(1) RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 71 TRISD TRISD7 TRISD6(1) TRISD5(1) TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 71 SSP1BUF MSSP1 Receive Buffer/Transmit Register 70 SSP1ADD MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) 73 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 70 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 70 GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN 70 SSP1STAT SMP CKE D/A P S R/W UA BF 70 SSP2BUF MSSP2 Receive Buffer/Transmit Register 70 SSP2ADD MSSP2 Address Register (I2C Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) 73 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 73 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 73 GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN 73 SSP2STAT SMP CKE D/A P S R/W UA BF 73 Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used by the MSSP module in I2C™ mode. Note 1: These bits are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. 2: Alternate bit definitions in I2C™ Slave mode.  2011 Microchip Technology Inc. DS39762F-page 313

PIC18F97J60 FAMILY NOTES: DS39762F-page 314  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 21.0 ENHANCED UNIVERSAL The pins of EUSART1 and EUSART2 are multiplexed SYNCHRONOUS with the functions of PORTC (RC6/TX1/CK1 and RC7/RX1/DT1) and PORTG (RG1/TX2/CK2 and ASYNCHRONOUS RECEIVER RG2/RX2/DT2), respectively. In order to configure TRANSMITTER (EUSART) these pins as an EUSART: The Enhanced Universal Synchronous Asynchronous • For EUSART1: Receiver Transmitter (EUSART) module is one of two - SPEN bit (RCSTA1<7>) must be set (= 1) serial I/O modules. (Generically, the EUSART is also - TRISC<7> bit must be set (= 1) known as a Serial Communications Interface or SCI.) - TRISC<6> bit must be cleared (= 0) for The EUSART can be configured as a full-duplex Asynchronous and Synchronous Master asynchronous system that can communicate with modes peripheral devices, such as CRT terminals and - TRISC<6> bit must be set (= 1) for personal computers. It can also be configured as a Synchronous Slave mode half-duplex synchronous system that can communicate • For EUSART2: with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. - SPEN bit (RCSTA2<7>) must be set (= 1) - TRISG<2> bit must be set (= 1) The Enhanced USART module implements additional features, including automatic baud rate detection and - TRISG<1> bit must be cleared (= 0) for calibration, automatic wake-up on Sync Break reception Asynchronous and Synchronous Master and 12-bit Break character transmit. These features modes make it ideally suited for use in Local Interconnect - TRISG<1> bit must be set (= 1) for Network bus (LIN/J2602 bus) systems. Synchronous Slave mode The 64-pin devices of the PIC18F97J60 family are Note: The EUSARTx control will automatically equipped with one EUSART module, referred to as reconfigure the pin from input to output as EUSART1. The 80-pin and 100-pin devices each have needed. two independent EUSART modules, referred to as The operation of each Enhanced USART module is EUSART1 and EUSART2. They can be configured in controlled through three registers: the following modes: • Transmit Status and Control (TXSTAx) • Asynchronous (full-duplex) with: • Receive Status and Control (RCSTAx) - Auto-Wake-up on Character Reception • Baud Rate Control (BAUDCONx) - Auto-Baud Calibration - 12-Bit Break Character Transmission These are detailed on the following pages in Register21-1, Register21-2 and Register21-3, • Synchronous – Master (half-duplex) with respectively. Selectable Clock Polarity • Synchronous – Slave (half-duplex) with Note: Throughout this section, references to Selectable Clock Polarity register and bit names that may be asso- ciated with a specific EUSART module are referred to generically by the use of ‘x’ in place of the specific module number. Thus, “RCSTAx” might refer to the Receive Status register for either EUSART1 or EUSART2.  2011 Microchip Technology Inc. DS39762F-page 315

PIC18F97J60 FAMILY REGISTER 21-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit is enabled 0 = Transmit is disabled bit 4 SYNC: EUSARTx Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission is completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR is empty 0 = TSR is full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39762F-page 316  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 21-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port is disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit 9-Bit Asynchronous mode (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit 9-Bit Asynchronous mode (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREGx register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be an address/data bit or a parity bit and must be calculated by user firmware.  2011 Microchip Technology Inc. DS39762F-page 317

PIC18F97J60 FAMILY REGISTER 21-3: BAUDCONx: BAUD RATE CONTROL REGISTER x R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 RXDTP: Received Data Polarity Select bit Asynchronous mode: 1 = Receive data (RXx) is inverted. Idle state is a low level. 0 = No inversion of receive data (RXx). Idle state is a high level. Synchronous modes: 1 = Data (DTx) is inverted; Idle state is a low level 0 = No inversion of data (DTx); Idle state is a high level bit 4 TXCKP: Clock and Data Polarity Select bit Asynchronous mode: 1 = Transmit data (TXx) is inverted; Idle state is a low level 0 = No inversion of transmit data (TXx); Idle state is a high level Synchronous modes: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator – SPBRGx only, SPBRGHx value ignored (Compatible mode) bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSARTx will continue to sample the RXx pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39762F-page 318  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 21.1 Baud Rate Generator (BRG) the high baud rate (BRGH = 1), or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate The BRG is a dedicated, 8-bit or 16-bit generator that for a fast oscillator frequency. supports both the Asynchronous and Synchronous Writing a new value to the SPBRGHx:SPBRGx regis- modes of the EUSARTx. By default, the BRG operates ters causes the BRG timer to be reset (or cleared). This in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) ensures that the BRG does not wait for a timer overflow selects 16-bit mode. before outputting the new baud rate. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits 21.1.1 OPERATION IN POWER-MANAGED BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also MODES control the baud rate. In Synchronous mode, BRGH is The device clock is used to generate the desired baud ignored. Table21-1 shows the formula for computation of rate. When one of the power-managed modes is the baud rate for different EUSARTx modes which only entered, the new clock source may be operating at a apply in Master mode (internally generated clock). different frequency. This may require an adjustment to Given the desired baud rate and FOSC, the nearest the value in the SPBRGx register pair. integer value for the SPBRGHx:SPBRGx registers can be calculated using the formulas in Table21-1. From this, 21.1.2 SAMPLING the error in baud rate can be determined. An example The data on the RXx pin (either RC7/RX1/DT1 or calculation is shown in Example21-1. Typical baud rates RG2/RX2/DT2) is sampled three times by a majority and error values for the various Asynchronous modes detect circuit to determine if a high or a low level is are shown in Table21-2. It may be advantageous to use present at the RXx pin. TABLE 21-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSARTx Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair  2011 Microchip Technology Inc. DS39762F-page 319

PIC18F97J60 FAMILY EQUATION 21-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate=16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 21-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page: TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39762F-page 320  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 21-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRG16 = 0, BRGH = 0 BAUD FOSC = 41.667 MHz FOSC = 31.25 MHz FOSC = 25.000 MHz FOSC = 20.833 MHz RATE SPBRG SPBRG SPBRG SPBRG (K) Actual % Actual % Actual % Actual % Value Value Value Value Rate (K) Error Rate (K) Error Rate (K) Error Rate (K) Error (decimal) (decimal) (decimal) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — 1.271 5.96 255 2.4 2.543 5.96 255 2.405 0.22 202 2.396 -0.15 162 2.393 -0.27 135 9.6 9.574 -0.27 67 9.574 -0.27 50 9.527 -0.76 40 9.574 -0.27 33 19.2 19.148 -0.27 33 19.531 1.73 24 19.531 1.73 19 19.147 -0.27 16 57.6 59.186 2.75 10 61.035 5.96 7 55.804 -3.12 6 54.253 -5.81 5 115.2 108.508 -5.81 5 122.070 5.96 3 130.208 13.03 2 108.505 -5.81 2 SYNC = 0, BRG16 = 0, BRGH = 0 BAUD FOSC = 13.889 MHz FOSC = 6.250 MHz FOSC = 4.167 MHz RATE SPBRG SPBRG SPBRG (K) Actual % Actual % Actual % Value Value Value Rate (K) Error Rate (K) Error Rate (K) Error (decimal) (decimal) (decimal) 0.3 — — — — — — 0.300 0.01 216 1.2 1.198 -0.08 180 1.206 0.47 80 1.206 0.48 53 2.4 2.411 0.47 89 2.382 -0.76 40 2.411 0.48 26 9.6 9.435 -1.71 22 9.766 1.73 9 9.301 -3.11 6 19.2 19.279 2.75 10 19.531 1.73 4 21.703 13.04 2 57.6 54.254 -5.81 3 48.828 -15.23 1 65.109 13.04 0 115.2 108.508 -5.81 1 97.656 -15.23 0 65.109 -43.48 0 SYNC = 0, BRG16 = 0, BRGH = 1 BAUD FOSC = 41.667 MHz FOSC = 31.25 MHz FOSC = 25.000 MHz FOSC = 20.833 MHz RATE SPBRG SPBRG SPBRG SPBRG (K) Actual % Actual % Actual % Actual % Value Value Value Value Rate (K) Error Rate (K) Error Rate (K) Error Rate (K) Error (decimal) (decimal) (decimal) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — — — — — — — 9.6 10.172 5.96 255 9.621 0.22 202 9.586 -0.15 162 9.573 -0.27 135 19.2 19.148 -0.27 135 19.148 -0.27 101 19.290 0.47 80 19.147 -0.27 67 57.6 57.871 0.47 44 57.445 -0.27 33 57.870 0.47 26 56.611 -1.72 22 115.2 113.226 -1.71 22 114.890 -0.27 16 111.607 -3.12 13 118.369 2.75 10 SYNC = 0, BRG16 = 0, BRGH = 1 BAUD FOSC = 13.889 MHz FOSC = 6.250 MHz FOSC = 4.167 MHz RATE SPBRG SPBRG SPBRG (K) Actual % Actual % Actual % Value Value Value Rate (K) Error Rate (K) Error Rate (K) Error (decimal) (decimal) (decimal) 0.3 — — — — — — — — — 1.2 — — — — — — 1.200 0.01 216 2.4 — — — 2.396 -0.15 162 2.389 -0.44 108 9.6 9.645 0.47 89 9.527 -0.76 40 9.645 0.48 26 19.2 19.290 0.47 44 19.531 1.73 19 18.603 -3.11 13 57.6 57.871 0.47 14 55.804 -3.12 6 52.088 -9.57 4 115.2 108.508 -5.81 7 130.208. 13.03 2 130.219 13.04 1  2011 Microchip Technology Inc. DS39762F-page 321

PIC18F97J60 FAMILY TABLE 21-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRG16 = 1, BRGH = 0 BAUD FOSC = 41.667 MHz FOSC = 31.25 MHz FOSC = 25.000 MHz FOSC = 20.833 MHz RATE SPBRG SPBRG SPBRG SPBRG (K) Actual % Actual % Actual % Actual % Value Value Value Value Rate (K) Error Rate (K) Error Rate (K) Error Rate (K) Error (decimal) (decimal) (decimal) (decimal) 0.3 0.300 0.00 8680 0.300 0.00 6509 0.300 0.01 5207 0.300 0.00 4339 1.2 1.200 0.01 2169 1.200 -0.02 1627 1.200 0.01 1301 1.200 0.00 1084 2.4 2.400 0.01 1084 2.399 -0.02 813 2.400 0.01 650 2.398 -0.09 542 9.6 9.609 0.10 270 9.621 0.22 202 9.586 -0.15 162 9.574 -0.27 135 19.2 19.148 -0.27 135 19.148 -0.27 101 19.290 0.47 80 19.148 -0.27 67 57.6 57.871 0.47 44 57.444 -0.27 33 57.870 0.47 26 56.611 -1.72 22 115.2 113.226 -1.71 22 114.890 -0.27 16 111.607 -3.12 13 118.369 2.75 10 SYNC = 0, BRG16 = 1, BRGH = 0 BAUD FOSC = 13.889 MHz FOSC = 6.250 MHz FOSC = 4.167 MHz RATE SPBRG SPBRG SPBRG (K) Actual % Actual % Actual % Value Value Value Rate (K) Error Rate (K) Error Rate (K) Error (decimal) (decimal) (decimal) 0.3 0.300 -0.02 2893 0.300 0.01 1301 0.300 0.01 867 1.2 1.201 0.05 722 1.198 -0.15 325 1.200 0.01 216 2.4 2.398 -0.08 361 2.396 -0.15 162 2.389 -0.44 108 9.6 9.645 0.47 89 9.527 -0.76 40 9.646 0.48 26 19.2 19.290 0.47 44 19.531 1.73 19 18.603 -3.11 13 57.6 57.871 0.47 14 55.804 -3.12 6 52.088 -9.57 4 115.2 108.508 -5.81 7 130.208 13.03 2 130.218 13.04 1 SYNC = 0, BRG16 = 1, BRGH = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 41.667 MHz FOSC = 31.25 MHz FOSC = 25.000 MHz FOSC = 20.833 MHz RATE SPBRG SPBRG SPBRG SPBRG (K) Actual % Actual % Actual % Actual % Value Value Value Value Rate (K) Error Rate (K) Error Rate (K) Error Rate (K) Error (decimal) (decimal) (decimal) (decimal) 0.3 0.300 0.00 34722 0.300 0.00 26041 0.300 0.00 20832 0.300 0.00 17360 1.2 1.200 0.00 8680 1.200 0.01 6509 1.200 0.01 5207 1.200 0.00 4339 2.4 2.400 0.01 4339 2.400 0.01 3254 2.400 0.01 2603 2.400 0.00 2169 9.6 9.601 0.01 1084 9.598 -0.02 813 9.601 0.01 650 9.592 -0.09 542 19.2 19.184 -0.08 542 19.195 -0.02 406 19.172 -0.15 325 19.219 0.10 270 57.6 57.551 -0.08 180 57.445 -0.27 135 57.339 -0.45 108 57.869 0.47 89 115.2 115.742 0.47 89 114.890 -0.27 67 115.741 0.47 53 115.739 0.47 44 SYNC = 0, BRG16 = 1, BRGH = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 13.889 MHz FOSC = 6.250 MHz FOSC = 4.167 MHz RATE SPBRG SPBRG SPBRG (K) Actual % Actual % Actual % Value Value Value Rate (K) Error Rate (K) Error Rate (K) Error (decimal) (decimal) (decimal) 0.3 0.300 0.00 11573 0.300 0.01 5207 0.300 -0.01 3472 1.2 1.200 -0.02 2893 1.200 0.01 1301 1.200 0.01 867 2.4 2.400 -0.02 1446 2.400 0.01 650 2.400 0.01 433 9.6 9.592 -0.08 361 9.586 -0.15 162 9.557 -0.44 108 19.2 19.184 -0.08 180 19.290 0.47 80 19.292 0.48 53 57.6 57.870 0.47 59 57.870 0.47 26 57.875 0.48 17 115.2 115.742 0.47 29 111.607 -3.12 13 115.750 0.48 8 DS39762F-page 322  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 21.1.3 AUTO-BAUD RATE DETECT While the ABD sequence takes place, the EUSARTx state machine is held in Idle. The RCxIF interrupt is set The Enhanced USARTx module supports the once the fifth rising edge on RXx is detected. The value automatic detection and calibration of baud rate. This in the RCREGx needs to be read to clear the RCxIF feature is active only in Asynchronous mode and while interrupt. The contents of RCREGx should be the WUE bit is clear. discarded. The automatic baud rate measurement sequence (Figure21-1) begins whenever a Start bit is received Note1: If the WUE bit is set with the ABDEN bit, and the ABDEN bit is set. The calculation is Auto-Baud Rate Detection will occur on self-averaging. the byte following the Break character. In the Auto-Baud Rate Detect (ABD) mode, the clock to 2: It is up to the user to determine that the the BRG is reversed. Rather than the BRG clocking the incoming character baud rate is within the range of the selected BRG clock source. incoming RXx signal, the RXx signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is Some combinations of oscillator frequency and EUSARTx baud rates are used as a counter to time the bit period of the incoming serial byte stream. not possible due to bit error rates. Overall system timing and communication baud Once the ABDEN bit is set, the state machine will clear rates must be taken into consideration the BRG and look for a Start bit. The Auto-Baud Rate when using the Auto-Baud Rate Detection Detect must receive a byte with the value 55h (ASCII feature. “U”, which is also the LIN/J2602 bus Sync character) in order to calculate the proper bit rate. The measurement is taken over both a low and high bit time in order to min- TABLE 21-4: BRG COUNTER imize any effects caused by asymmetry of the incoming CLOCK RATES signal. After a Start bit, the SPBRGx begins counting up, BRG16 BRGH BRG Counter Clock using the preselected clock source on the first rising edge of RXx. After eight bits on the RXx pin or the fifth 0 0 FOSC/512 rising edge, an accumulated value totalling the proper 0 1 FOSC/128 BRG period is left in the SPBRGHx:SPBRGx register pair. Once the 5th edge is seen (this should correspond 1 0 FOSC/128 to the Stop bit), the ABDEN bit is automatically cleared. 1 1 FOSC/32 If a rollover of the BRG occurs (an overflow from FFFFh Note: During the ABD sequence, SPBRGx and to 0000h), the event is trapped by the ABDOVF status SPBRGHx are both used as a 16-bit counter, bit (BAUDCONx<7>). It is set in hardware by BRG roll- independent of the BRG16 setting. overs and can be set or cleared by the user in software. ABD mode remains active after rollover events and the 21.1.3.1 ABD and EUSARTx Transmission ABDEN bit remains set (Figure21-2). Since the BRG clock is reversed during ABD acquisition, While calibrating the baud rate period, the BRG registers the EUSARTx transmitter cannot be used during ABD. are clocked at 1/8th the preconfigured clock rate. Note This means that whenever the ABDEN bit is set, that the BRG clock will be configured by the BRG16 and TXREGx cannot be written to. Users should also ensure BRGH bits. Independent of the BRG16 bit setting, both that ABDEN does not become set during a transmit the SPBRGx and SPBRGHx will be used as a 16-bit sequence. Failing to do this may result in unpredictable counter. This allows the user to verify that no carry EUSARTx operation. occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table21-4 for counter clock rates to the BRG.  2011 Microchip Technology Inc. DS39762F-page 323

PIC18F97J60 FAMILY FIGURE 21-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RXx pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSARTx module to be configured in Asynchronous mode and WUE=0. FIGURE 21-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RXx pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h DS39762F-page 324  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 21.2 EUSARTx Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register The Asynchronous mode of operation is selected by is empty and the TXxIF flag bit is set. This interrupt can clearing the SYNC bit (TXSTAx<4>). In this mode, the be enabled or disabled by setting or clearing the inter- EUSARTx uses standard Non-Return-to-Zero (NRZ) rupt enable bit, TXxIE. TXxIF will be set regardless of format (one Start bit, eight or nine data bits and one the state of TXxIE; it cannot be cleared in software. Stop bit). The most common data format is 8 bits. An TXxIF is also not cleared immediately upon loading on-chip, dedicated 8-bit/16-bit Baud Rate Generator TXREGx, but becomes valid in the second instruction can be used to derive standard baud rate frequencies cycle following the load instruction. Polling TXxIF, from the oscillator. immediately following a load of TXREGx, will return The EUSARTx transmits and receives the LSb first. invalid results. The EUSARTx module’s transmitter and receiver are While TXxIF indicates the status of the TXREGx regis- functionally independent but use the same data format ter, another bit, TRMT (TXSTAx<1>), shows the status and baud rate. The Baud Rate Generator produces a of the TSR register. TRMT is a read-only bit which is set clock, either x16 or x64 of the bit shift rate, depending when the TSR register is empty. No interrupt logic is on the BRGH and BRG16 bits (TXSTAx<2> and tied to this bit so the user has to poll this bit in order to BAUDCONx<3>). Parity is not supported by the determine if the TSR register is empty. hardware but can be implemented in software and stored as the 9th data bit. Note1: The TSR register is not mapped in data memory, so it is not available to the user. The TXCKP (BAUDCONx<4>) and RXDTP (BAUDCONx<5>) bits allow the TXx and RXx signals 2: Flag bit, TXxIF, is set when enable bit to be inverted (polarity reversed). Devices that buffer TXEN is set. signals between TTL and RS-232 levels also invert the To set up an Asynchronous Transmission: signal. Setting the TXCKP and RXDTP bits allows for the use of circuits that provide buffering without 1. Initialize the SPBRGHx:SPBRGx registers for inverting the signal. the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve When operating in Asynchronous mode, the EUSARTx the desired baud rate. module consists of the following important elements: 2. Enable the asynchronous serial port by clearing • Baud Rate Generator the SYNC bit and setting bit, SPEN. • Sampling Circuit 3. If the signal from the TXx pin is to be inverted, • Asynchronous Transmitter set the TXCKP bit. • Asynchronous Receiver 4. If interrupts are desired, set enable bit, TXxIE. • Auto-Wake-up on Sync Break Character 5. If 9-bit transmission is desired, set transmit bit, • 12-Bit Break Character Transmit TX9. Can be used as address/data bit. • Auto-Baud Rate Detection 6. Enable the transmission by setting the TXEN bit which will also set bit, TXxIF. 21.2.1 EUSARTx ASYNCHRONOUS 7. If 9-bit transmission is selected, the ninth bit TRANSMITTER should be loaded in bit, TX9D. The EUSARTx transmitter block diagram is shown in 8. Load data to the TXREGx register (starts Figure21-3. The heart of the transmitter is the Transmit transmission). (Serial) Shift Register (TSR). The Shift register obtains 9. If using interrupts, ensure that the GIE and PEIE its data from the Read/Write Transmit Buffer register, bits in the INTCON register (INTCON<7:6>) are TXREGx. The TXREGx register is loaded with data in set. software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREGx register (if available).  2011 Microchip Technology Inc. DS39762F-page 325

PIC18F97J60 FAMILY FIGURE 21-3: EUSARTx TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb LSb (8)  0 Pin Buffer and Control TSR Register TXx pin Interrupt TXEN Baud Rate CLK TRMT SPEN TXCKP BRG16 SPBRGHx SPBRGx TX9 Baud Rate Generator TX9D FIGURE 21-4: ASYNCHRONOUS TRANSMISSION, TXCKP = 0 (TXx NOT INVERTED) Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 21-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK), TXCKP = 0 (TXx NOT INVERTED) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 1 TCY Word 1 Word 2 TXxIF bit (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. DS39762F-page 326  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 21-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF(1) TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE(1) TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP TX2IP(1) TMR4IP CCP5IP CCP4IP CCP3IP 71 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 TXREGx EUSARTx Transmit Register 71 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’.  2011 Microchip Technology Inc. DS39762F-page 327

PIC18F97J60 FAMILY 21.2.2 EUSARTx ASYNCHRONOUS 21.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure21-6. This mode would typically be used in RS-485 systems. The data is received on the RXx pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGHx:SPBRGx registers for whereas the main receive serial shifter operates at the the appropriate baud rate. Set or clear the bit rate or at FOSC. This mode would typically be used BRGH and BRG16 bits, as required, to achieve in RS-232 systems. the desired baud rate. The RXDTP bit (BAUDCON<5>) allows the RXx signal 2. Enable the asynchronous serial port by clearing to be inverted (polarity reversed). Devices that buffer the SYNC bit and setting the SPEN bit. signals from RS-232 to TTL levels also perform an inver- 3. If the signal at the RXx pin is to be inverted, set sion of the signal (when RS-232 = positive, TTL = 0). the RXDTP bit. If the signal from the TXx pin is Inverting the polarity of the RXx pin data by setting the to be inverted, set the TXCKP bit. RXDTP bit allows for the use of circuits that provide 4. If interrupts are required, set the RCEN bit and buffering without inverting the signal. select the desired priority level with the RCxIP bit. To set up an Asynchronous Reception: 5. Set the RX9 bit to enable 9-bit reception. 1. Initialize the SPBRGHx:SPBRGx registers for 6. Set the ADDEN bit to enable address detect. the appropriate baud rate. Set or clear the 7. Enable reception by setting the CREN bit. BRGH and BRG16 bits, as required, to achieve 8. The RCxIF bit will be set when reception is the desired baud rate. complete. The interrupt will be Acknowledged if 2. Enable the asynchronous serial port by clearing the RCxIE and GIE bits are set. the SYNC bit and setting bit, SPEN. 9. Read the RCSTAx register to determine if any 3. If the signal at the RXx pin is to be inverted, set error occurred during reception, as well as read the RXDTP bit. Bit 9 of data (if applicable). 4. If interrupts are desired, set enable bit, RCxIE. 10. Read RCREGx to determine if the device is 5. If 9-bit reception is desired, set bit, RX9. being addressed. 6. Enable the reception by setting bit, CREN. 11. If any error occurred, clear the CREN bit. 7. Flag bit, RCxIF, will be set when reception is 12. If the device has been addressed, clear the complete and an interrupt will be generated if ADDEN bit to allow all received data into the enable bit, RCxIE, was set. receive buffer and interrupt the CPU. 8. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREGx register. 10. If any error occurred, clear the error by clearing enable bit, CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. DS39762F-page 328  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 21-6: EUSARTx RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGHx SPBRGx o 6r4 MSb RSR Register LSb  16 or Stop (8) 7  1 0 Start Baud Rate Generator  4 RX9 Pin Buffer Data and Control Recovery RXx RX9D RCREGx Register FIFO RXDTP SPEN 8 Interrupt RCxIF Data Bus RCxIE FIGURE 21-7: ASYNCHRONOUS RECEPTION, RXDTP = 0 (RXx NOT INVERTED) Start Start Start RXx (pin) bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREGx RCREGx Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word, causing the OERR (Overrun Error) bit to be set. TABLE 21-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF(1) TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE(1) TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP(1) TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 RCREGx EUSARTx Receive Register 71 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’.  2011 Microchip Technology Inc. DS39762F-page 329

PIC18F97J60 FAMILY 21.2.4 AUTO-WAKE-UP ON SYNC BREAK Oscillator start-up time must also be considered, CHARACTER especially in applications using oscillators with longer start-up intervals (i.e., HS or HSPLL mode). The Sync During Sleep mode, all clocks to the EUSARTx are Break (or Wake-up Signal) character must be of suspended. Because of this, the Baud Rate Generator sufficient length and be followed by a sufficient interval is inactive and a proper byte reception cannot be per- to allow enough time for the selected oscillator to start formed. The auto-wake-up feature allows the controller and provide proper initialization of the EUSARTx. to wake-up due to activity on the RXx/DTx line while the EUSARTx is operating in Asynchronous mode. 21.2.4.2 Special Considerations Using The auto-wake-up feature is enabled by setting the WUE the WUE Bit bit (BAUDCONx<1>). Once set, the typical receive The timing of WUE and RCxIF events may cause some sequence on RXx/DTx is disabled and the EUSARTx confusion when it comes to determining the validity of remains in an Idle state, monitoring for a wake-up event received data. As noted, setting the WUE bit places the independent of the CPU mode. A wake-up event consists EUSARTx in an Idle mode. The wake-up event causes of a high-to-low transition on the RXx/DTx line. (This a receive interrupt by setting the RCxIF bit. The WUE bit coincides with the start of a Sync Break or a Wake-up is cleared after this when a rising edge is seen on Signal character for the LIN/J2602 protocol.) RXx/DTx. The interrupt condition is then cleared by Following a wake-up event, the module generates an reading the RCREGx register. Ordinarily, the data in RCxIF interrupt. The interrupt is generated synchro- RCREGx will be dummy data and should be discarded. nously to the Q clocks in normal operating modes The fact that the WUE bit has been cleared (or is still (Figure21-8) and asynchronously if the device is in set), and the RCxIF flag is set, should not be used as Sleep mode (Figure21-9). The interrupt condition is an indicator of the integrity of the data in RCREGx. cleared by reading the RCREGx register. Users should consider implementing a parallel method The WUE bit is automatically cleared once a low-to-high in firmware to verify received data integrity. transition is observed on the RXx line following the To assure that no actual data is lost, check the RCIDL wake-up event. At this point, the EUSARTx module is in bit to verify that a receive operation is not in process. If Idle mode and returns to normal operation. This signals a receive operation is not occurring, the WUE bit may to the user that the Sync Break event is over. then be set just prior to entering the Sleep mode. 21.2.4.1 Special Considerations Using Auto-Wake-up Since auto-wake-up functions by sensing rising edge transitions on RXx/DTx, information with any state changes before the Stop bit may signal a false End-of-Character (EOC) and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all ‘0’s. This can be 00h (8bytes) for standard RS-232 devices or 000h (12 bits) for LIN/J2602 bus. DS39762F-page 330  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 21-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RXx/DTx Line RCxIF Cleared due to user read of RCREGx Note1: The EUSARTx remains in Idle while the WUE bit is set. FIGURE 21-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RXx/DTx Line Note 1 RCxIF Cleared due to user read of RCREGx SLEEP Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSARTx remains in Idle while the WUE bit is set.  2011 Microchip Technology Inc. DS39762F-page 331

PIC18F97J60 FAMILY 21.2.5 BREAK CHARACTER SEQUENCE 1. Configure the EUSARTx for the desired mode. The EUSARTx module has the capability of sending 2. Set the TXEN and SENDB bits to set up the the special Break character sequences that are Break character. required by the LIN/J2602 bus standard. The Break 3. Load the TXREGx with a dummy character to character transmit consists of a Start bit, followed by initiate transmission (the value is ignored). twelve ‘0’ bits and a Stop bit. The Frame Break charac- 4. Write ‘55h’ to TXREGx to load the Sync ter is sent whenever the SENDB and TXEN bits character into the transmit FIFO buffer. (TXSTAx<3> and TXSTAx<5>) are set while the Trans- 5. After the Break has been sent, the SENDB bit is mit Shift Register (TSR) is loaded with data. Note that reset by hardware. The Sync character now the value of data written to TXREGx will be ignored and transmits in the preconfigured mode. all ‘0’s will be transmitted. When the TXREGx becomes empty, as indicated by The SENDB bit is automatically reset by hardware after the TXxIF, the next data byte can be written to the corresponding Stop bit is sent. This allows the user TXREGx. to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync 21.2.6 RECEIVING A BREAK CHARACTER character in the LIN/J2602 support specification). The Enhanced USARTx module can receive a Break Note that the data value written to the TXREGx for the character in two ways. Break character is ignored. The write simply serves the The first method forces configuration of the baud rate purpose of initiating the proper sequence. at a frequency of 9/13 the typical speed. This allows for The TRMT bit indicates when the transmit operation is the Stop bit transition to be at the correct sampling active or Idle, just as it does during normal transmis- location (13 bits for Break versus Start bit, and 8 data sion. See Figure21-10 for the timing of the Break bits for typical data). character sequence. The second method uses the auto-wake-up feature 21.2.5.1 Break and Sync Transmit Sequence described in Section21.2.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the The following sequence will send a message frame EUSARTx will sample the next two transitions on header made up of a Break, followed by an Auto-Baud RXx/DTx, cause an RCxIF interrupt and receive the Sync byte. This sequence is typical of a LIN/J2602 bus next data byte followed by another interrupt. master. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABDEN bit once the TXxIF interrupt is observed. FIGURE 21-10: SEND BREAK CHARACTER SEQUENCE Write to TXREGx Dummy Write BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here Auto-Cleared SENDB bit (Transmit Shift Reg. Empty Flag) DS39762F-page 332  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 21.3 EUSARTx Synchronous Once the TXREGx register transfers the data to the Master Mode TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be The Synchronous Master mode is entered by setting enabled or disabled by setting or clearing the interrupt the CSRC bit (TXSTAx<7>). In this mode, the data is enable bit, TXxIE. TXxIF is set regardless of the state transmitted in a half-duplex manner (i.e., transmission of enable bit, TXxIE; it cannot be cleared in software. It and reception do not occur at the same time). When will reset only when new data is loaded into the transmitting data, the reception is inhibited and vice TXREGx register. versa. Synchronous mode is entered by setting bit, While flag bit, TXxIF, indicates the status of the TXREGx SYNC (TXSTAx<4>). In addition, enable bit, SPEN register, another bit, TRMT (TXSTAx<1>), shows the (RCSTAx<7>), is set in order to configure the TXx and status of the TSR register. TRMT is a read-only bit which RXx pins to CKx (clock) and DTx (data) lines, is set when the TSR is empty. No interrupt logic is tied to respectively. this bit, so the user must poll this bit in order to determine Clock polarity (CKx) is selected with the TXCKP bit if the TSR register is empty. The TSR is not mapped in (BAUDCON<4>). Setting TXCKP sets the Idle state on data memory so it is not available to the user. CKx as high, while clearing the bit sets the Idle state as To set up a Synchronous Master Transmission: low. Data polarity (DTx) is selected with the RXDTP bit (BAUDCONx<5>). Setting RXDTP sets the Idle state 1. Initialize the SPBRGHx:SPBRGx registers for the on DTx as high, while clearing the bit sets the Idle state appropriate baud rate. Set or clear the BRG16 as low. DTx is sampled when CKx returns to its Idle bit, as required, to achieve the desired baud rate. state. This option is provided to support Microwire 2. Enable the synchronous master serial port by devices with this module. setting bits, SYNC, SPEN and CSRC. 3. If interrupts are desired, set enable bit, TXxIE. 21.3.1 EUSARTx SYNCHRONOUS 4. If 9-bit transmission is desired, set bit, TX9. MASTER TRANSMISSION 5. Enable the transmission by setting bit, TXEN. The EUSARTx transmitter block diagram is shown in 6. If 9-bit transmission is selected, the ninth bit Figure21-3. The heart of the transmitter is the Transmit should be loaded in bit, TX9D. (Serial) Shift Register (TSR). The Transmit Shift regis- 7. Start transmission by loading data to the ter obtains its data from the Read/Write Transmit Buffer TXREGx register. register, TXREGx. The TXREGx register is loaded with data in software. The TSR register is not loaded until 8. If using interrupts, ensure that the GIE and PEIE the last bit has been transmitted from the previous load. bits in the INTCON register (INTCON<7:6>) are As soon as the last bit is transmitted, the TSR is loaded set. with new data from the TXREGx (if available). FIGURE 21-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX1/CK1 pin (TXCKP = 0) RC6/TX1/CK1 pin (TXCKP = 1) Write to TXREG1 Reg Write Word 1 Write Word 2 TX1IF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRG1 = 0; continuous transmission of two 8-bit words. This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2).  2011 Microchip Technology Inc. DS39762F-page 333

PIC18F97J60 FAMILY FIGURE 21-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2). TABLE 21-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF(1) TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE(1) TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP TX2IP(1) TMR4IP CCP5IP CCP4IP CCP3IP 71 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 TXREGx EUSARTx Transmit Register 71 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’. DS39762F-page 334  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 21.3.2 EUSARTx SYNCHRONOUS 4. If the signal from the CKx pin is to be inverted, MASTER RECEPTION set the TXCKP bit. If the signal from the DTx pin is to be inverted, set the RXDTP bit. Once Synchronous mode is selected, reception is 5. If interrupts are desired, set enable bit, RCxIE. enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>), or the Continuous Receive 6. If 9-bit reception is desired, set bit, RX9. Enable bit, CREN (RCSTAx<4>). Data is sampled on 7. If a single reception is required, set bit, SREN. the RXx pin on the falling edge of the clock. For continuous reception, set bit, CREN. 8. Interrupt flag bit, RCxIF, will be set when recep- If enable bit, SREN, is set, only a single word is tion is complete and an interrupt will be generated received. If enable bit, CREN, is set, the reception is if the enable bit, RCxIE, was set. continuous until CREN is cleared. If both bits are set, 9. Read the RCSTAx register to get the 9th bit (if then CREN takes precedence. enabled) and determine if any error occurred To set up a Synchronous Master Reception: during reception. 1. Initialize the SPBRGHx:SPBRGx registers for the 10. Read the 8-bit received data by reading the appropriate baud rate. Set or clear the BRG16 RCREGx register. bit, as required, to achieve the desired baud rate. 11. If any error occurred, clear the error by clearing 2. Enable the synchronous master serial port by bit, CREN. setting bits, SYNC, SPEN and CSRC. 12. If using interrupts, ensure that the GIE and PEIE 3. Ensure bits, CREN and SREN, are clear. bits in the INTCON register (INTCON<7:6>) are set. FIGURE 21-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX1/CK1 pin (TXCKP = 0) RC6/TX1/CK1 pin (TXCKP = 1) Write to SREN bit SREN bit CREN bit ‘0’ ‘0’ RC1IF bit (Interrupt) Read RCREG1 Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2).  2011 Microchip Technology Inc. DS39762F-page 335

PIC18F97J60 FAMILY TABLE 21-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF(1) TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE(1) TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP(1) TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 RCREGx EUSARTx Receive Register 71 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’. DS39762F-page 336  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 21.4 EUSARTx Synchronous To set up a Synchronous Slave Transmission: Slave Mode 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, Synchronous Slave mode is entered by clearing bit, CSRC. CSRC (TXSTAx<7>). This mode differs from the 2. Clear bits, CREN and SREN. Synchronous Master mode in that the shift clock is sup- plied externally at the CKx pin (instead of being supplied 3. If the signal from the CKx pin is to be inverted, internally in Master mode). This allows the device to set the TXCKP bit. If the signal from the DTx pin transfer or receive data while in any low-power mode. is to be inverted, set the RXDTP bit. 4. If interrupts are desired, set enable bit, TXxIE. 21.4.1 EUSARTx SYNCHRONOUS 5. If 9-bit transmission is desired, set bit, TX9. SLAVE TRANSMISSION 6. Enable the transmission by setting enable bit, The operation of the Synchronous Master and Slave TXEN. modes is identical, except in the case of Sleep mode. 7. If 9-bit transmission is selected, the ninth bit If two words are written to the TXREGx and then the should be loaded in bit, TX9D. SLEEP instruction is executed, the following will occur: 8. Start transmission by loading data to the TXREGx register. a) The first word will immediately transfer to the TSR register and transmit. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are b) The second word will remain in the TXREGx set. register. c) Flag bit, TXxIF, will not be set. d) When the first word has been shifted out of TSR, the TXREGx register will transfer the second word to the TSR and flag bit, TXxIF, will now be set. e) If enable bit, TXxIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 21-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF(1) TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE(1) TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP TX2IP(1) TMR4IP CCP5IP CCP4IP CCP3IP 71 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 TXREGx EUSARTx Transmit Register 71 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’.  2011 Microchip Technology Inc. DS39762F-page 337

PIC18F97J60 FAMILY 21.4.2 EUSARTx SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical, except in the case of Sleep or any CSRC. Idle mode, and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCxIE. Slave mode. 3. If the signal from the CKx pin is to be inverted, If receive is enabled by setting the CREN bit prior to set the TXCKP bit. If the signal from the DTx pin entering Sleep or any Idle mode, then a word may be is to be inverted, set the RXDTP bit. received while in this low-power mode. Once the word 4. If 9-bit reception is desired, set bit, RX9. is received, the RSR register will transfer the data to the 5. To enable reception, set enable bit, CREN. RCREGx register. If the RCxIE enable bit is set, the 6. Flag bit, RCxIF, will be set when reception is interrupt generated will wake the chip from the complete. An interrupt will be generated if low-power mode. If the global interrupt is enabled, the enable bit, RCxIE, was set. program will branch to the interrupt vector. 7. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREGx register. 9. If any error occurred, clear the error by clearing bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 21-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF(1) TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE(1) TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP(1) TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 RCREGx EUSARTx Receive Register 71 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’. DS39762F-page 338  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 22.0 10-BIT ANALOG-TO-DIGITAL The module has five registers: CONVERTER (A/D) MODULE • A/D Result Register High Byte (ADRESH) • A/D Result Register Low Byte (ADRESL) The Analog-to-Digital (A/D) Converter module has • A/D Control Register 0 (ADCON0) 11inputs for the 64-pin devices, 15 inputs for the 80-pin devices and 16 inputs for the 100-pin devices. This • A/D Control Register 1 (ADCON1) module allows conversion of an analog input signal to • A/D Control Register 2 (ADCON2) a corresponding 10-bit digital number. The ADCON0 register, shown in Register22-1, controls the operation of the A/D module. The ADCON1 register, shown in Register22-2, configures the functions of the port pins. The ADCON2 register, shown in Register22-3, configures the A/D clock source, programmed acquisition time and justification. REGISTER 22-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADCAL: A/D Calibration bit 1 = Calibration is performed on next A/D conversion 0 = Normal A/D Converter operation (no calibration is performed) bit 6 Unimplemented: Read as ‘0’ bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,3) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12)(2,3) 1101 = Channel 13 (AN13)(2,3) 1110 = Channel 14 (AN14)(2,3) 1111 = Channel 15 (AN15)(2,3) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion is in progress 0 = A/D is Idle bit 0 ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled Note 1: This channel is implemented on 100-pin devices only. 2: These channels are implemented on 80-pin and 100-pin devices only. 3: Performing a conversion on unimplemented channels will return random values.  2011 Microchip Technology Inc. DS39762F-page 339

PIC18F97J60 FAMILY REGISTER 22-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = AVSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = AVDD bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits: PCFG<3:0> (1)15 (1)14 (1)13 (1)12 11 10 9 8 7 6 (2)5 4 3 2 (3)1 (3)0 N N N N N N N N N N N N N N N N A A A A A A A A A A A A A A A A 0000 A A A A A A A A A A A A A A A A 0001 D D A A A A A A A A A A A A A A 0010 D D D A A A A A A A A A A A A A 0011 D D D D A A A A A A A A A A A A 0100 D D D D D A A A A A A A A A A A 0101 D D D D D D A A A A A A A A A A 0110 D D D D D D D A A A A A A A A A 0111 D D D D D D D D A A A A A A A A 1000 D D D D D D D D D A A A A A A A 1001 D D D D D D D D D D A A A A A A 1010 D D D D D D D D D D D A A A A A 1011 D D D D D D D D D D D D A A A A 1100 D D D D D D D D D D D D D A A A 1101 D D D D D D D D D D D D D D A A 1110 D D D D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D D D D A = Analog input D = Digital I/O Note 1: AN12 through AN15 are available in 80-pin and 100-pin devices only. 2: AN5 is available in 100-pin devices only. 3: AN0 and AN1 can also operate as Ethernet LED outputs in either Analog or Digital I/O modes. DS39762F-page 340  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 22-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion.  2011 Microchip Technology Inc. DS39762F-page 341

PIC18F97J60 FAMILY The analog reference voltage is software selectable to the A/D conversion. When the A/D conversion is com- either the device’s positive and negative supply voltage plete, the result is loaded into the ADRESH:ADRESL (AVDD and AVSS), or the voltage level on the register pair, the GO/DONE bit (ADCON0<1>) is RA3/AN3/VREF+ and RA2/AN2/VREF- pins. cleared and the A/D Interrupt Flag bit, ADIF, is set. The A/D Converter has a unique feature of being able A device Reset forces all registers to their Reset state. to operate while the device is in Sleep mode. To This forces the A/D module to be turned off and any operate in Sleep, the A/D conversion clock must be conversion in progress is aborted. The value in the derived from the A/D Converter’s internal RC oscillator. ADRESH:ADRESL register pair is not modified for a Power-on Reset. These registers will contain unknown The output of the sample and hold is the input into the data after a Power-on Reset. converter, which generates the result via successive approximation. The block diagram of the A/D module is shown in Figure22-1. Each port pin associated with the A/D Converter can be configured as an analog input or as a digital I/O. The ADRESH and ADRESL registers contain the result of FIGURE 22-1: A/D BLOCK DIAGRAM CHS<3:0> 1111 AN15(1) 1110 AN14(1) 1101 AN13(1) 1100 AN12(1) 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7 0110 AN6 0101 AN5(2) 0100 AN4 VAIN 10-Bit (Input Voltage) 0011 AN3 A/D Converter 0010 AN2 0001 VCFG<1:0> AN1 0000 AN0 VDD VREF+ Reference Voltage VREF- VSS Note 1: Channels AN15 through AN12 are not available in 64-pin devices. 2: Channel AN5 is implemented in 100-pin devices only. DS39762F-page 342  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY After the A/D module has been configured as desired, 2. Configure A/D interrupt (if desired): the selected channel must be acquired before the • Clear ADIF bit conversion is started. The analog input channels must • Set ADIE bit have their corresponding TRIS bits selected as inputs. • Set GIE bit To determine acquisition time, see Section22.1 “A/D Acquisition Requirements”. After this acquisition 3. Wait the required acquisition time (if required). time has elapsed, the A/D conversion can be started. 4. Start conversion: An acquisition time can be programmed to occur • Set GO/DONE bit (ADCON0<1>) between setting the GO/DONE bit and the actual start 5. Wait for A/D conversion to complete, by either: of the conversion. • Polling for the GO/DONE bit to be cleared The following steps should be followed to do an A/D OR conversion: • Waiting for the A/D interrupt 1. Configure the A/D module: 6. Read A/D Result registers (ADRESH:ADRESL); • Configure analog pins, voltage reference and clear bit, ADIF, if required. digital I/O (ADCON1) 7. For the next conversion, go to Step 1 or Step 2, • Select A/D input channel (ADCON0) as required. The A/D conversion time per bit is • Select A/D acquisition time (ADCON2) defined as TAD. A minimum wait of 2 TAD is • Select A/D conversion clock (ADCON2) required before next acquisition starts. • Turn on A/D module (ADCON0) FIGURE 22-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to VDD various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) RSS = Sampling Switch Resistance 1 2 3 4 Sampling Switch (k  2011 Microchip Technology Inc. DS39762F-page 343

PIC18F97J60 FAMILY 22.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation22-1 may be used. This equation assumes For the A/D Converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. Analog Input model is shown in Figure22-2. The Equation22-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time, TACQ. This calculation is based on the following application system required to charge the capacitor, CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 25 pF at the analog input (due to pin leakage current). The Rs = 2.5 k maximum recommended impedance for analog Conversion Error  1/2 LSb sources is 2.5k. After the analog input channel is VDD = 3V  Rss = 2 k selected (changed), the channel must be sampled for Temperature = 85C (system max.) at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 22-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 22-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 22-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 s TCOFF = (Temp – 25C)(0.02 s/C) (85C – 25C)(0.02 s/C) 1.2 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) s -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s 1.05 s TACQ = 0.2 s + 1 s + 1.2 s 2.4 s DS39762F-page 344  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 22.2 Selecting and Configuring Table22-1 shows the resultant TAD times derived from Automatic Acquisition Time the device operating frequencies and the A/D clock source selected. The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE TABLE 22-1: TAD vs. DEVICE OPERATING bit is set. FREQUENCIES When the GO/DONE bit is set, sampling is stopped and AD Clock Source (TAD) Maximum a conversion begins. The user is responsible for ensur- Device ing the required acquisition time has passed between Operation ADCS<2:0> Frequency selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT<2:0> bits 2 TOSC 000 2.86MHz (ADCON2<5:3>) remain in their Reset state (‘000’) and 4 TOSC 100 5.71MHz is compatible with devices that do not offer 8 TOSC 001 11.43MHz programmable acquisition times. 16 TOSC 101 22.86MHz If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. 32 TOSC 010 41.67MHz When the GO/DONE bit is set, the A/D module continues 64 TOSC 110 41.67MHz to sample the input for the selected acquisition time, then RC(2) x11 1.00 MHz(1) automatically begins a conversion. Since the acquisition Note 1: The RC source has a typical TAD time of time is programmed, there may be no need to wait for an 4ms. acquisition time between selecting a channel and setting the GO/DONE bit. 2: See Parameter 130 in Table28-27 for A/D RC clock specifications. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the 22.4 Configuring Analog Port Pins A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is The ADCON1, TRISA, TRISF and TRISH registers nothing to indicate if the acquisition time has ended or control the operation of the A/D port pins. The port pins if the conversion has begun. needed as analog inputs must have their correspond- ing TRIS bits set (input). If the TRIS bit is cleared 22.3 Selecting the A/D Conversion (output), the digital output level (VOH or VOL) will be Clock converted. The A/D conversion time per bit is defined as TAD. The The A/D operation is independent of the state of the A/D conversion requires 11 TAD per 10-bit conversion. CHS<3:0> bits and the TRIS bits. The source of the A/D conversion clock is software Note1: When reading the PORT register, all pins selectable. configured as analog input channels will There are seven possible options for TAD: read as cleared (a low level). Pins config- • 2 TOSC ured as digital inputs will convert an • 4 TOSC analog input. Analog levels on a digitally configured input will be accurately • 8 TOSC converted. • 16 TOSC 2: Analog levels on any pin defined as a • 32 TOSC digital input may cause the digital input • 64 TOSC buffer to consume current out of the • Internal RC Oscillator device’s specification limits. For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD. See Section28.0 “Electrical Characteristics”, A/D Parameter 130 in Table28-27 for more information.  2011 Microchip Technology Inc. DS39762F-page 345

PIC18F97J60 FAMILY 22.5 A/D Conversions 22.6 Use of the ECCP2 Trigger Figure22-3 shows the operation of the A/D Converter An A/D conversion can be started by the “Special Event after the GO/DONE bit has been set and the Trigger” of the ECCP2 module. This requires that the ACQT<2:0> bits are cleared. A conversion is started CCP2M<3:0> bits (CCP2CON<3:0>) be programmed after the following instruction to allow entry into Sleep as ‘1011’ and that the A/D module is enabled (ADON mode before the conversion begins. bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion Figure22-4 shows the operation of the A/D Converter and the Timer1 (or Timer3) counter will be reset to zero. after the GO/DONE bit has been set, the ACQT<2:0> bits Timer1 (or Timer3) is reset to automatically repeat the are set to ‘010’ and a 4TAD acquisition time has been A/D acquisition period with minimal software overhead selected before the conversion starts. (moving ADRESH/ADRESL to the desired location). Clearing the GO/DONE bit during a conversion will The appropriate analog input channel must be selected abort the current conversion. The A/D Result register and the minimum acquisition period is either timed by pair will NOT be updated with the partially completed the user, or an appropriate TACQ time is selected before A/D conversion sample. This means the the Special Event Trigger sets the GO/DONE bit (starts ADRESH:ADRESL registers will continue to contain a conversion). the value of the last completed conversion (or the last If the A/D module is not enabled (ADON is cleared), the value written to the ADRESH:ADRESL registers). Special Event Trigger will be ignored by the A/D module After the A/D conversion is completed or aborted, a but will still reset the Timer1 (or Timer3) counter. 2TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 22-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY – TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 22-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Time Conversion starts (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. DS39762F-page 346  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 22.7 A/D Converter Calibration If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and The A/D Converter in the PIC18F97J60 family of ADCS<2:0> bits in ADCON2 should be updated in devices includes a self-calibration feature which com- accordance with the power-managed mode clock that pensates for any offset generated within the module. will be used. After the power-managed mode is entered The calibration process is automated and is initiated by (either of the power-managed Run modes), an A/D setting the ADCAL bit (ADCON0<7>). The next time acquisition or conversion may be started. Once an the GO/DONE bit is set, the module will perform a acquisition or conversion is started, the device should “dummy” conversion (that is, with reading none of the continue to be clocked by the same power-managed input channels) and store the resulting value internally mode clock source until the conversion has been to compensate for offset. Thus, subsequent offsets will completed. If desired, the device may be placed into be compensated. the corresponding power-managed Idle mode during The calibration process assumes that the device is in a the conversion. relatively steady-state operating condition. If A/D If the power-managed mode clock frequency is less calibration is used, it should be performed after each than 1MHz, the A/D RC clock source should be device Reset, or if there are other major changes in selected. operating conditions. Operation in Sleep mode requires the A/D RC clock to 22.8 Operation in Power-Managed be selected. If bits, ACQT<2:0>, are set to ‘000’ and a conversion is started, the conversion will be delayed Modes one instruction cycle to allow execution of the SLEEP The selection of the automatic acquisition time and A/D instruction and entry to Sleep mode. The IDLEN and conversion clock is determined in part by the clock SCS bits in the OSCCON register must have already source and frequency while in a power-managed been cleared prior to starting the conversion. mode. TABLE 22-2: SUMMARY OF A/D REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR2 OSCFIF CMIF ETHIF r BCL1IF — TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE — TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP — TMR3IP CCP2IP 71 ADRESH A/D Result Register High Byte 70 ADRESL A/D Result Register Low Byte 70 ADCON0 ADCAL — CHS3 CHS3 CHS1 CHS0 GO/DONE ADON 70 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 70 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 70 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 70 PORTA RJPU — RA5 RA4 RA3 RA2 RA1 RA0 72 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 71 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0(1) 72 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0(1) 71 PORTH(2) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 72 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 71 Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used for A/D conversion. Note 1: Implemented in 100-pin devices only. 2: This register is not implemented in 64-pin devices.  2011 Microchip Technology Inc. DS39762F-page 347

PIC18F97J60 FAMILY NOTES: DS39762F-page 348  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 23.0 COMPARATOR MODULE The CMCON register (Register23-1) selects the comparator input and output configuration. Block The analog comparator module contains two diagrams of the various comparator configurations are comparators that can be configured in a variety of shown in Figure23-1. ways. The inputs can be selected from the analog inputs, multiplexed with pins, RF1 through RF6, as well as the on-chip voltage reference (see Section24.0 “Comparator Voltage Reference Module”). The digi- tal outputs (normal or inverted) are available at the pin level and can also be read through the control register. REGISTER 23-1: CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output is inverted 0 = C2 output is not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output is inverted 0 = C1 output is not inverted bit 3 CIS: Comparator Input Switch bit When CM<2:0> = 110: 1 = C1 VIN- connects to RF5/AN10/CVREF C2 VIN- connects to RF3/AN8 0 = C1 VIN- connects to RF6/AN11 C2 VIN- connects to RA4/AN9 bit 2-0 CM<2:0>: Comparator Mode bits Figure23-1 shows the Comparator modes and the CM<2:0> bit settings.  2011 Microchip Technology Inc. DS39762F-page 349

PIC18F97J60 FAMILY 23.1 Comparator Configuration mode is changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Section28.0 “Electrical Characteristics”. tors, shown in Figure23-1. Bits CM<2:0> of the CMCON register are used to select these modes. The Note: Comparator interrupts should be disabled TRISF register controls the data direction of the during a Comparator mode change; comparator pins for each mode. If the Comparator otherwise, a false interrupt may occur. FIGURE 23-1: COMPARATOR I/O OPERATING MODES Comparator Outputs Disabled Comparators Off (POR Default Value) CM<2:0> = 000 CM<2:0> = 111 RF6/AN11 A VIN- RF6/AN11 D VIN- RF5/AN10/ A VIN+ C1 Off (Read as ‘0’) RF5/AN10/ D VIN+ C1 Off (Read as ‘0’) CVREF CVREF RF4/AN9 A VIN- RF4/AN9 D VIN- RF3/AN8 A VIN+ C2 Off (Read as ‘0’) RF3/AN8 D VIN+ C2 Off (Read as ‘0’) Two Independent Comparators Two Independent Comparators with Outputs CM<2:0> = 010 CM<2:0> = 011 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10/ A VIN+ C1 C1OUT RF5/AN10/ A VIN+ C1 C1OUT CVREF CVREF RF2/AN7/C1OUT* RF4/AN9 A VIN- RF4/AN9 A VIN- RF3/AN8 A VIN+ C2 C2OUT RF3/AN8 A VIN+ C2 C2OUT RF1/AN6/C2OUT* Two Common Reference Comparators Two Common Reference Comparators with Outputs CM<2:0> = 100 CM<2:0> = 101 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10/ A VIN+ C1 C1OUT RF5/AN10/ A VIN+ C1 C1OUT CVREF CVREF RF2/AN7/C1OUT* RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF1/AN6/C2OUT* One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM<2:0> = 001 CM<2:0> = 110 RF6/AN11 A VIN- RF6/AN11 A CIS = 0 VIN- RF5/AN10/ A VIN+ C1 C1OUT RCFV5R/EAFN10/ A CIS = 1 VIN+ C1 C1OUT CVREF RF2/AN7/C1OUT* RF4/AN9 A CIS = 0 VIN- RF4/AN9 D VIN- RF3/AN8 A CIS = 1 VIN+ C2 C2OUT RF3/AN8 D VIN+ C2 Off (Read as ‘0’) CVREF From VREF module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs. DS39762F-page 350  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 23.2 Comparator Operation 23.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure23-2, along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference from the the digital output. When the analog input at VIN+ is less comparator voltage reference module. This module is than the analog input VIN-, the output of the comparator described in more detail in Section24.0 “Comparator is a digital low level. When the analog input at VIN+ is Voltage Reference Module”. greater than the analog input, VIN-, the output of the The internal reference is only available in the mode comparator is a digital high level. The shaded areas of where four inputs are multiplexed to two comparators the output of the comparator in Figure23-2 represent (CM<2:0>=110). In this mode, the internal voltage the uncertainty due to input offsets and response time. reference is applied to the VIN+ pin of both comparators. 23.3 Comparator Reference 23.4 Comparator Response Time Depending on the comparator operating mode, either an external or internal voltage reference may be used. Response time is the minimum time, after selecting a The analog signal present at VIN- is compared to the new reference voltage or input source, before the signal at VIN+ and the digital output of the comparator comparator output has a valid level. If the internal ref- is adjusted accordingly (Figure23-2). erence is changed, the maximum delay of the internal voltage reference must be considered when using the FIGURE 23-2: SINGLE COMPARATOR comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section28.0 “Electrical Characteristics”). VIN+ + 23.5 Comparator Outputs Output VIN- – The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RF1 and RF2 I/O pins. When enabled, multiplexors in the output path of the RF1 and RF2 pins will switch and the output of each pin will be the unsynchronized output of the VIN- comparator. The uncertainty of each of the comparators is related to the input offset voltage and VIN+ the response time given in the specifications. Figure23-3 shows the comparator output block diagram. Output The TRISF bits will still function as an output enable/disable for the RF1 and RF2 pins while in this mode. 23.3.1 EXTERNAL REFERENCE SIGNAL The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<5:4>). When external voltage references are used, the comparator module can be configured to have the com- Note1: When reading the PORT register, all pins parators operate from the same or different reference configured as analog inputs will read as sources. However, threshold detector applications may ‘0’. Pins configured as digital inputs will require the same reference. The reference signal must convert an analog input according to the be between VSS and VDD and can be applied to either Schmitt Trigger input specification. pin of the comparator(s). 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified.  2011 Microchip Technology Inc. DS39762F-page 351

PIC18F97J60 FAMILY FIGURE 23-3: COMPARATOR OUTPUT BLOCK DIAGRAM X E L + Port Pins TIP To CxOUT UL - pin M D Q Bus Data CxINV Read CMCON EN Set D Q CMIF bit EN CL From Other Reset Comparator 23.6 Comparator Interrupts 23.7 Comparator Operation During Sleep The comparator interrupt flag is set whenever there is a change in the output value of either comparator. When a comparator is active and the device is placed Software will need to maintain information about the in Sleep mode, the comparator remains active and the status of the output bits, as read from CMCON<7:6>, to interrupt is functional, if enabled. This interrupt will determine the actual change that occurred. The CMIF wake-up the device from Sleep mode, when enabled. bit (PIR2<6>) is the Comparator Interrupt Flag. The Each operational comparator will consume additional CMIF bit must be reset by clearing it. Since it is also current, as shown in the comparator specifications. To possible to write a ‘1’ to this register, a simulated minimize power consumption while in Sleep mode, turn interrupt may be initiated. off the comparators (CM<2:0>=111) before entering Both the CMIE bit (PIE2<6>) and the PEIE bit Sleep. If the device wakes up from Sleep, the contents (INTCON<6>) must be set to enable the interrupt. In of the CMCON register are not affected. addition, the GIE bit (INTCON<7>) must also be set. If 23.8 Effects of a Reset any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt A device Reset forces the CMCON register to its Reset condition occurs. state, causing the comparator modules to be turned off Note: If a change in the CMCON register (CM<2:0>=111). However, the input pins (RF3 (C1OUT or C2OUT) should occur when a through RF6) are configured as analog inputs by read operation is being executed (start of default on device Reset. The I/O configuration for these the Q2 cycle), then the CMIF (PIR2 pins is determined by the setting of the PCFG<3:0> bits register) interrupt flag may not get set. (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at Reset The user, in the Interrupt Service Routine, can clear the time. interrupt in the following manner: a) Any read or write of CMCON will end the mismatch condition. b) Clear flag bit, CMIF. A mismatch condition will continue to set flag bit, CMIF. Reading CMCON will end the mismatch condition and allow flag bit, CMIF, to be cleared. DS39762F-page 352  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 23.9 Analog Input Connection range by more than 0.6V in either direction, one of the Considerations diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10k is A simplified circuit for an analog input is shown in recommended for the analog sources. Any external Figure23-4. Since the analog pins are connected to a component connected to an analog input pin, such as digital output, they have reverse biased diodes to VDD a capacitor or a Zener diode, should have very little and VSS. The analog input, therefore, must be between leakage current. VSS and VDD. If the input voltage deviates from this FIGURE 23-4: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator Input AIN VA C5 PpIFN VT = 0.6V I±L5E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR2 OSCFIF CMIF ETHIF r BCL1IF — TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE — TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP — TMR3IP CCP2IP 71 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 70 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 70 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 72 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 71 Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used by the comparator module.  2011 Microchip Technology Inc. DS39762F-page 353

PIC18F97J60 FAMILY NOTES: DS39762F-page 354  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 24.0 COMPARATOR VOLTAGE is selected by the CVRR bit (CVRCON<5>). The REFERENCE MODULE primary difference between the ranges is the size of the steps selected by the CVREF selection bits The comparator voltage reference is a 16-tap resistor (CVR<3:0>), with one range offering finer resolution. ladder network that provides a selectable reference The equations used to calculate the output of the voltage. Although its primary purpose is to provide a comparator voltage reference are as follows: reference for the analog comparators, it may also be If CVRR = 1: used independently of them. CVREF = ((CVR<3:0>)/24) x (CVRSRC) A block diagram of the module is shown in Figure24-1. If CVRR = 0: The resistor ladder is segmented to provide two ranges CVREF=(CVRSRC/4)+((CVR<3:0>)/32)x of CVREF values and has a power-down function to (CVRSRC) conserve power when the reference is not being used. The comparator reference supply voltage can come The module’s supply reference can be provided from either device VDD/VSS or an external voltage reference. from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit 24.1 Configuring the Comparator (CVRCON<4>). Voltage Reference The settling time of the comparator voltage reference The voltage reference module is controlled through the must be considered when changing the CVREF CVRCON register (Register24-1). The comparator output (see Table28-3 in Section28.0 “Electrical voltage reference provides two ranges of output volt- Characteristics”). age, each with 16 distinct levels. The range to be used REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = VDD – VSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0  (CVR<3:0>)  15) When CVRR = 1: CVREF = ((CVR<3:0>)/24)  (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32)  (CVRSRC) Note 1: CVROE overrides the TRISF<5> bit setting.  2011 Microchip Technology Inc. DS39762F-page 355

PIC18F97J60 FAMILY FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ VDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U 16 Steps M 1 CVREF o- 6-t R 1 R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 24.2 Comparator Voltage Reference 24.4 Effects of a Reset Accuracy/Error A device Reset disables the voltage reference by The full range of voltage reference cannot be realized clearing bit, CVREN (CVRCON<7>). This Reset also due to the construction of the module. The transistors disconnects the reference from the RA2 pin by clearing on the top and bottom of the resistor ladder network bit, CVROE (CVRCON<6>), and selects the (Figure24-1) keep CVREF from approaching the refer- high-voltage range by clearing bit, CVRR ence source rails. The voltage reference is derived (CVRCON<5>). The CVR value select bits are also from the reference source; therefore, the CVREF output cleared. changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be 24.5 Connection Considerations found in Section28.0 “Electrical Characteristics”. The voltage reference module operates independently of the comparator module. The output of the reference 24.3 Operation During Sleep generator may be connected to the RF5 pin if the When the device wakes up from Sleep through an CVROE bit is set. Enabling the voltage reference out- interrupt, or a Watchdog Timer time-out, the contents of put onto RA2, when it is configured as a digital input, the CVRCON register are not affected. To minimize will increase current consumption. Connecting RF5 as current consumption in Sleep mode, the voltage a digital output with CVRSS enabled will also increase reference should be disabled. current consumption. The RF5 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure24-2 shows an example buffering technique. DS39762F-page 356  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 24-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXJ6X R(1) CVREF + Module Voltage RF5 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the comparator voltage reference configuration bits, CVRCON<5> and CVRCON<3:0>. TABLE 24-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 70 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 70 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 71 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference module.  2011 Microchip Technology Inc. DS39762F-page 357

PIC18F97J60 FAMILY NOTES: DS39762F-page 358  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 25.0 SPECIAL FEATURES OF THE 25.1.1 CONSIDERATIONS FOR CPU CONFIGURING THE PIC18F97J60 FAMILY DEVICES PIC18F97J60 family devices include several features Devices of the PIC18F97J60 family do not use persis- intended to maximize reliability and minimize cost tent memory registers to store configuration information. through elimination of external components. These are: The configuration bytes are implemented as volatile • Oscillator Selection memory which means that configuration data must be • Resets: programmed each time the device is powered up. - Power-on Reset (POR) Configuration data is stored in the four words at the top - Power-up Timer (PWRT) of the on-chip program memory space, known as the - Oscillator Start-up Timer (OST) Flash Configuration Words, which are located in the - Brown-out Reset (BOR) program memory space, as shown in Table6-1. The Configuration Words are stored in the same order • Interrupts shown in Table25-1, with CONFIG1L at the lowest • Watchdog Timer (WDT) address and CONFIG3H at the highest. The data is • Fail-Safe Clock Monitor automatically loaded in the proper Configuration • Two-Speed Start-up registers during device power-up. • Code Protection When creating applications for these devices, users • In-Circuit Serial Programming should always specifically allocate the location of the The oscillator can be configured for the application Flash Configuration Word for configuration data. This is depending on frequency, power, accuracy and cost. All to make certain that program code is not stored in this of the options are discussed in detail in Section3.0 address when the code is compiled. “Oscillator Configurations”. The volatile memory cells used for the Configuration A complete discussion of device Resets and interrupts bits always reset to ‘1’ on Power-on Resets. For all is available in previous sections of this data sheet. other types of Reset events, the previously pro- grammed values are maintained and used without In addition to their Power-up and Oscillator Start-up reloading from program memory. Timers provided for Resets, the PIC18F97J60 family of devices has a configurable Watchdog Timer which is The four Most Significant bits of CONFIG1H, controlled in software. CONFIG2H and CONFIG3H, in program memory, The inclusion of an internal RC oscillator also provides should also be ‘1111’. This makes these Configuration the additional benefits of a Fail-Safe Clock Monitor Words appear to be NOP instructions in the remote event that their locations are ever executed by (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and accident. Since Configuration bits are not implemented automatic switchover in the event of its failure. in the corresponding locations, writing ‘1’s to these Two-Speed Start-up enables code to be executed locations has no effect on device operation. almost immediately on start-up while the primary clock To prevent inadvertent configuration changes during source completes its start-up delays. code execution, all programmable Configuration bits All of these features are enabled and configured by are write-once. After a bit is initially programmed during setting the appropriate Configuration register bits. a power cycle, it cannot be written to again. Changing a device configuration requires that power to the device 25.1 Configuration Bits be cycled. The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various device configurations. These bits are mapped starting at program memory location, 300000h. A complete list is shown in Table25-1. A detailed explanation of the various bit functions is provided in Register25-1 through Register25-8.  2011 Microchip Technology Inc. DS39762F-page 359

PIC18F97J60 FAMILY TABLE 25-1: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value(1) 300000h CONFIG1L DEBUG XINST STVREN — — — — WDTEN 110- ---1 300001h CONFIG1H —(2) —(2) —(2) —(2) —(3) CP0 — — ---- 01-- 300002h CONFIG2L IESO FCMEN — — — FOSC2 FOSC1 FOSC0 11-- -111 300003h CONFIG2H —(2) —(2) —(2) —(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111 300004h CONFIG3L WAIT(4) BW(4) EMB1(4) EMB0(4) EASHFT(4) — — — 1111 1--- 300005h CONFIG3H —(2) —(2) —(2) —(2) — ETHLED ECCPMX(5) CCP2MX(5) ---- -111 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(6) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx(6) Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’. Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the configuration bytes maintain their previously programmed states. 2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed. 3: This bit should always be maintained as ‘0’. 4: Implemented in 100-pin devices only. 5: Implemented in 80-pin and 100-pin devices only. 6: See Register25-7 and Register25-8 for DEVID values. These registers are read-only and cannot be programmed by the user. DS39762F-page 360  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 25-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-0 U-0 U-0 U-0 U-0 R/WO-1 DEBUG XINST STVREN — — — — WDTEN bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled; RB6 and RB7 are configured as general purpose I/O pins 0 = Background debugger is enabled; RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode are enabled 0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode) bit 5 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow is enabled 0 = Reset on stack overflow/underflow is disabled bit 4-1 Unimplemented: Read as ‘0’ bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT is enabled 0 = WDT is disabled (control is placed on SWDTEN bit) REGISTER 25-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-0 U-0 U-0 U-0 U-0(1) R/WO-1 U-0 U-0 —(2) —(2) —(2) —(2) — CP0 — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 CP0: Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is code-protected bit 1-0 Unimplemented: Read as ‘0’ Note 1: This bit should always be maintained as ‘0’. 2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed.  2011 Microchip Technology Inc. DS39762F-page 361

PIC18F97J60 FAMILY REGISTER 25-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/WO-1 R/WO-1 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 IESO FCMEN — — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up is enabled 0 = Two-Speed Start-up is disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 5-3 Unimplemented: Read as ‘0’ bit 2 FOSC2: Default/Reset System Clock Select bit 1 = Clock selected by FOSC<1:0> as system clock is enabled when OSCCON<1:0> = 00 0 = INTRC enabled as system clock when OSCCON<1:0> = 00 bit 1-0 FOSC<1:0>: Oscillator Selection bits 11 = EC oscillator, PLL is enabled and under software control, CLKO function on OSC2 10 = EC oscillator, CLKO function on OSC2 01 = HS oscillator, PLL is enabled and under software control 00 = HS oscillator DS39762F-page 362  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 25-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1 —(1) —(1) —(1) —(1) WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed.  2011 Microchip Technology Inc. DS39762F-page 363

PIC18F97J60 FAMILY REGISTER 25-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 WAIT(1) BW(1) EMB1(1) EMB0(1) EASHFT(1) — — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states for operations on external memory bus is disabled 0 = Wait states for operations on external memory bus is enabled and selected by MEMCON<5:4> bit 6 BW: Data Bus Width Select bit(1) 1 = 16-Bit Data Width mode 0 = 8-Bit Data Width mode bit 5-4 EMB<1:0>: External Memory Bus Configuration bits(1) 11 = Microcontroller mode, external bus disabled 10 = Extended Microcontroller mode,12-Bit Addressing mode 01 = Extended Microcontroller mode,16-Bit Addressing mode 00 = Extended Microcontroller mode, 20-Bit Addressing mode bit 3 EASHFT: External Address Bus Shift Enable bit(1) 1 = Address shifting is enabled; address on external bus is offset to start at 000000h 0 = Address shifting is disabled; address on external bus reflects the PC value bit 2-0 Unimplemented: Read as ‘0’ Note 1: Implemented on 100-pin devices only. DS39762F-page 364  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY REGISTER 25-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-0 U-0 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 —(1) —(1) —(1) —(1) — ETHLED ECCPMX(2) CCP2MX(2) bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 ETHLED: Ethernet LED Enable bit 1 = RA0/RA1 are multiplexed with LEDA/LEDB when the Ethernet module is enabled and function as I/O when the Ethernet is disabled 0 = RA0/RA1 function as I/O regardless of Ethernet module status bit 1 ECCPMX: ECCP MUX bit(2) 1 = ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 0 = ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 bit 0 CCP2MX: ECCP2 MUX bit(2) 1 = ECCP2/P2A is multiplexed with RC1 0 = ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (80-pin and 100-pin devices) or with RB3 in Extended Microcontroller mode (100-pin devices only) Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed. 2: Implemented in 80-pin and 100-pin devices only.  2011 Microchip Technology Inc. DS39762F-page 365

PIC18F97J60 FAMILY REGISTER 25-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F97J60 FAMILY DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 DEV<2:0>: Device ID bits See Register25-8 for a complete listing. bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. REGISTER 25-8: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F97J60 FAMILY DEVICES R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-0 DEV<10:3>: Device ID bits: DEV<10:3> DEV<2:0> Device (DEVID2<7:0>) (DEVID1<7:5>) 0001 1000 000 PIC18F66J60 0001 1111 000 PIC18F66J65 0001 1111 001 PIC18F67J60 0001 1000 001 PIC18F86J60 0001 1111 010 PIC18F86J65 0001 1111 011 PIC18F87J60 0001 1000 010 PIC18F96J60 0001 1111 100 PIC18F96J65 0001 1111 101 PIC18F97J60 DS39762F-page 366  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 25.2 Watchdog Timer (WDT) Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts For PIC18F97J60 family devices, the WDT is driven by when executed. the INTRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT period 2: When a CLRWDT instruction is executed, is 4ms and has the same stability as the INTRC the postscaler count will be cleared. oscillator. The 4ms period of the WDT is multiplied by a 16-bit 25.2.1 CONTROL REGISTER postscaler. Any output of the WDT postscaler is The WDTCON register (Register25-9) is a readable selected by a multiplexor, controlled by the WDTPS bits and writable register. The SWDTEN bit enables or dis- in Configuration Register 2H. Available periods range ables WDT operation. This allows software to override from 4ms to 131.072seconds (2.18 minutes). The the WDTEN Configuration bit and enable the WDT only WDT and postscaler are cleared whenever a SLEEP or if it has been disabled by the Configuration bit. CLRWDT instruction is executed, or a clock failure (primary or Timer1 oscillator) has occurred. FIGURE 25-1: WDT BLOCK DIAGRAM Enable WDT SWDTEN INTRC Control WDT Counter Wake-up from INTRC Oscillator 128 Power-Managed Modes CLRWDT Programmable Postscaler Reset WDT All Device Resets 1:1 to 1:32,768 Reset WDT 4 WDTPS<3:0> Sleep  2011 Microchip Technology Inc. DS39762F-page 367

PIC18F97J60 FAMILY REGISTER 25-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled. TABLE 25-2: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page: RCON IPEN — CM RI TO PD POR BOR 70 WDTCON — — — — — — — SWDTEN 70 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer. DS39762F-page 368  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 25.3 On-Chip Voltage Regulator FIGURE 25-2: CONNECTIONS FOR THE ON-CHIP REGULATOR All of the PIC18F97J60 family devices power their core digital logic at a nominal 2.5V. This may create an issue Regulator Enabled (ENVREG tied to VDD): for designs that are required to operate at a higher 3.3V typical voltage, such as 3.3V. To simplify system design, all devices in the PIC18F97J60 family incor- PIC18FXXJ6X porate an on-chip regulator that allows the device to VDD run its core logic from VDD. ENVREG The regulator is controlled by the ENVREG pin. Tying VDDCORE/VCAP VDD to the pin enables the regulator, which in turn, CF provides power to the core from the other VDD pins. VSS When the regulator is enabled, a low-ESR filter capacitor must be connected to the VDDCORE/VCAP pin (Figure25-2). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Section28.3 “DC Characteristics: Regulator Disabled (ENVREG tied to ground): PIC18F97J60 Family (Industrial)”. If ENVREG is tied to VSS, the regulator is disabled. In (VDD > VDDCORE) this case, separate power for the core logic, at a nomi- 2.5V(1) 3.3V(1) nal 2.5V, must be supplied to the device on the VDDCORE/VCAP pin to run the I/O pins at higher voltage PIC18FXXJ6X levels, typically 3.3V. Alternatively, the VDDCORE/VCAP VDD and VDD pins can be tied together to operate at a lower ENVREG nominal voltage. Refer to Figure25-2 for possible configurations. VDDCORE/VCAP VSS 25.3.1 ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC18F97J60 family devices also have a simple brown-out capability. (VDD = VDDCORE) If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry 2.5V(1) will generate a Brown-out Reset. This event is captured PIC18FXXJ6X by the BOR flag bit (RCON<0>). VDD The operation of the BOR is described in more detail in ENVREG Section5.4 “Brown-out Reset (BOR)” and Section5.4.1 “Detecting BOR”. The Brown-out VDDCORE/VCAP Reset voltage levels are specific in Section28.1 “DC VSS Characteristics: Supply Voltage, PIC18F97J60 Family (Industrial)” 25.3.2 POWER-UP REQUIREMENTS Note 1: These are typical operating voltages. Refer to Section28.1 “DC Characteristics: The on-chip regulator is designed to meet the power-up Supply Voltage” for the full operating requirements for the device. If the application does not ranges of VDD and VDDCORE. use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts.  2011 Microchip Technology Inc. DS39762F-page 369

PIC18F97J60 FAMILY 25.4 Two-Speed Start-up In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the The Two-Speed Start-up feature helps to minimize the currently selected clock source until the primary clock latency period, from oscillator start-up to code execu- source becomes available. The setting of the IESO bit tion, by allowing the microcontroller to use the INTRC is ignored. oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO 25.4.1 SPECIAL CONSIDERATIONS FOR Configuration bit. USING TWO-SPEED START-UP Two-Speed Start-up should be enabled only if the While using the INTRC oscillator in Two-Speed primary oscillator mode is HS or HSPLL Start-up, the device still obeys the normal command (Crystal-Based) modes. Since the EC and ECPLL sequences for entering power-managed modes, modes do not require an Oscillator Start-up Timer including serial SLEEP instructions (refer to delay, Two-Speed Start-up should be disabled. Section4.1.4 “Multiple Sleep Commands”). In prac- When enabled, Resets and wake-ups from Sleep mode tice, this means that user code can change the cause the device to configure itself to run from the SCS<1:0> bit settings, or issue SLEEP instructions, internal oscillator block as the clock source, following before the OST times out. This would allow an applica- the time-out of the Power-up Timer after a Power-on tion to briefly wake-up, perform routine “housekeeping” Reset is enabled. This allows almost immediate code tasks and return to Sleep before the device starts to execution while the primary oscillator starts and the operate from the primary oscillator. OST is running. Once the OST times out, the device User code can also check if the primary clock source is automatically switches to PRI_RUN mode. currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. FIGURE 25-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake from Interrupt Event OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS39762F-page 370  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 25.5 Fail-Safe Clock Monitor During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable The Fail-Safe Clock Monitor (FSCM) allows the for timing-sensitive applications. In these cases, it may microcontroller to continue operation in the event of an be desirable to select another clock configuration and external oscillator failure by automatically switching the enter an alternate power-managed mode. This can be device clock to the internal oscillator block. The FSCM done to attempt a partial recovery or execute a function is enabled by setting the FCMEN controlled shutdown. See Section4.1.4 “Multiple Configuration bit. Sleep Commands” and Section25.4.1 “Special When FSCM is enabled, the INTRC oscillator runs at Considerations for Using Two-Speed Start-up” for all times to monitor clocks to peripherals and provide a more details. backup clock in the event of a clock failure. Clock The FSCM will detect failures of the primary or second- monitoring (shown in Figure25-4) is accomplished by ary clock sources only. If the internal oscillator block creating a sample clock signal which is the INTRC out- fails, no failure would be detected, nor would any action put, divided by 64. This allows ample time between be possible. FSCM sample clocks for a peripheral clock edge to occur. The peripheral device clock and the sample 25.5.1 FSCM AND THE WATCHDOG TIMER clock are presented as inputs to the Clock Monitor Both the FSCM and the WDT are clocked by the (CM) latch. The CM is set on the falling edge of the INTRC oscillator. Since the WDT operates with a device clock source but cleared on the rising edge of separate divider and counter, disabling the WDT has the sample clock. no effect on the operation of the INTRC oscillator when the FSCM is enabled. FIGURE 25-4: FSCM BLOCK DIAGRAM As already noted, the clock source is switched to the Clock Monitor INTRC clock when a clock failure is detected. This may Latch (CM) (edge-triggered) mean a substantial change in the speed of code execu- Peripheral tion. If the WDT is enabled with a small prescale value, S Q Clock a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, Fail-Safe Clock events also reset the WDT and post- INTRC scaler, allowing it to start timing from when execution ÷ 64 C Q Source speed was changed, and decreasing the likelihood of an erroneous time-out. (32 s) 488 Hz (2.048 ms) 25.5.2 EXITING FAIL-SAFE OPERATION Clock The fail-safe condition is terminated by either a device Failure Reset or by entering a power-managed mode. On Detected Reset, the controller starts the primary clock source specified in Configuration Register 2H (with any Clock failure is tested for on the falling edge of the required start-up delays that are required for the oscil- sample clock. If a sample clock falling edge occurs lator mode, such as OST or PLL timer). The INTRC while CM is still set, a clock failure has been detected oscillator provides the device clock until the primary (Figure25-5). This causes the following: clock source becomes ready (similar to a Two-Speed • The FSCM generates an oscillator fail interrupt by Start-up). The clock source is then switched to the setting bit, OSCFIF (PIR2<7>) primary clock (indicated by the OSTS bit in the • The device clock source is switched to the internal OSCCON register becoming set). The Fail-Safe Clock oscillator block (OSCCON is not updated to show Monitor then resumes monitoring the peripheral clock. the current clock source – this is the fail-safe The primary clock source may never become ready condition) during start-up. In this case, operation is clocked by the • The WDT is reset INTRC oscillator. The OSCCON register will remain in its Reset state until a power-managed mode is entered.  2011 Microchip Technology Inc. DS39762F-page 371

PIC18F97J60 FAMILY FIGURE 25-5: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 25.5.3 FSCM INTERRUPTS IN For HS or HSPLL modes, the situation is somewhat POWER-MANAGED MODES different. Since the oscillator may require a start-up time considerably longer than the FSCM sample clock By entering a power-managed mode, the clock time, a false clock failure may be detected. To prevent multiplexor selects the clock source selected by the this, the internal oscillator block is automatically config- OSCCON register. Fail-Safe Monitoring of the ured as the device clock and functions until the primary power-managed clock source resumes in the clock is stable (the OST and PLL timers have timed power-managed mode. out). This is identical to Two-Speed Start-up mode. If an oscillator failure occurs during power-managed Once the primary clock is stable, the INTRC returns to operation, the subsequent events depend on whether its role as the FSCM source. or not the oscillator failure interrupt is enabled. If Note: The same logic that prevents false oscilla- enabled (OSCFIF=1), code execution will be clocked tor failure interrupts on POR, or wake from by the INTRC multiplexor. An automatic transition back Sleep, will also prevent the detection of to the failed clock source will not occur. the oscillator’s failure to start at all follow- If the interrupt is disabled, subsequent interrupts while ing these events. This can be avoided by in Idle mode will cause the CPU to begin executing monitoring the OSTS bit and using a instructions while being clocked by the INTRC source. timing routine to determine if the oscillator is taking too long to start. Even so, no 25.5.4 POR OR WAKE-UP FROM SLEEP oscillator failure interrupt will be flagged. The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset As noted in Section25.4.1 “Special Considerations (POR) or low-power Sleep mode. When the primary for Using Two-Speed Start-up”, it is also possible to device clock is either EC or INTRC, monitoring can select another clock configuration and enter an alternate begin immediately following these events. power-managed mode while waiting for the primary clock to become stable. When the new power-managed mode is selected, the primary clock is disabled. DS39762F-page 372  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 25.6 Program Verification and 25.7 In-Circuit Serial Programming Code Protection PIC18F97J60 family microcontrollers can be serially For all devices in the PIC18F97J60 family, the on-chip programmed while in the end application circuit. This is program memory space is treated as a single block. simply done with two lines for clock and data and three Code protection for this block is controlled by one other lines for power, ground and the programming Configuration bit, CP0. This bit inhibits external reads voltage. This allows customers to manufacture boards and writes to the program memory space. It has no with unprogrammed devices and then program the direct effect in normal execution mode. microcontroller just before shipping the product. This also allows the most recent firmware or a custom 25.6.1 CONFIGURATION REGISTER firmware to be programmed. PROTECTION 25.8 In-Circuit Debugger The Configuration registers are protected against untoward changes or reads in two ways. The primary When the DEBUG Configuration bit is programmed to protection is the write-once feature of the Configuration a ‘0’, the In-Circuit Debugger functionality is enabled. bits which prevents reconfiguration once the bit has This function allows simple debugging functions when been programmed during a power cycle. To safeguard used with MPLAB® IDE. When the microcontroller has against unpredictable events, Configuration bit this feature enabled, some resources are not available changes resulting from individual cell level disruptions for general use. Table25-3 shows which resources are (such as ESD events) will cause a parity error and required by the background debugger. trigger a device Reset. The data for the Configuration registers is derived from TABLE 25-3: DEBUGGER RESOURCES the Flash Configuration Words in program memory. I/O pins: RB6, RB7 When the CP0 bit is programmed (cleared), the source Stack: 2 levels data for device configuration is also protected as a consequence. Program Memory: 512 bytes Data Memory: 10 bytes  2011 Microchip Technology Inc. DS39762F-page 373

PIC18F97J60 FAMILY NOTES: DS39762F-page 374  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 26.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: The PIC18F97J60 family of devices incorporates the • A literal value to be loaded into a file register standard set of 75 PIC18 core instructions, as well as (specified by ‘k’) an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software • The desired FSR register to load the literal value stack. The extended set is discussed later in this into (specified by ‘f’) section. • No operand required (specified by ‘—’) 26.1 Standard Instruction Set The control instructions may use some of the following operands: The standard PIC18 instruction set adds many enhancements to the previous PIC® MCU instruction • A program memory address (specified by ‘n’) sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions PIC MCU instruction sets. Most instructions are a (specified by ‘s’) single program memory word (16 bits), but there are • The mode of the table read and table write four instructions that require two program memory instructions (specified by ‘m’) locations. • No operand required Each single-word instruction is a 16-bit word divided (specified by ‘—’) into an opcode, which specifies the instruction type and All instructions are a single word, except for four one or more operands, which further specify the double-word instructions. These instructions were operation of the instruction. made double-word to contain the required information The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If into four basic categories: this second word is executed as an instruction (by itself), it will execute as a NOP. • Byte-oriented operations • Bit-oriented operations All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the • Literal operations program counter is changed as a result of the instruc- • Control operations tion. In these cases, the execution takes two instruction The PIC18 instruction set summary in Table26-2 lists cycles with the additional instruction cycle(s) executed byte-oriented, bit-oriented, literal and control as a NOP. operations. Table26-1 shows the opcode field The double-word instructions execute in two instruction descriptions. cycles. Most byte-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. 1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4MHz, the normal 2. The destination of the result (specified by ‘d’) instruction execution time is 1s. If a conditional test is true, or the program counter is changed as a result of 3. The accessed memory (specified by ‘a’) an instruction, the instruction execution time is 2 s. The file register designator ‘f’ specifies which file regis- Two-word branch instructions (if true) would take 3 s. ter is to be used by the instruction. The destination Figure26-1 shows the general formats that the instruc- designator ‘d’ specifies where the result of the tions can have. All examples use the convention ‘nnh’ operation is to be placed. If ‘d’ is zero, the result is to represent a hexadecimal number. placed in the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction. The Instruction Set Summary, shown in Table26-2, lists the standard instructions recognized by the All bit-oriented instructions have three operands: Microchip MPASMTM Assembler. 1. The file register (specified by ‘f’) Section26.1.1 “Standard Instruction Set” provides 2. The bit in the file register (specified by ‘b’) a description of each instruction. 3. The accessed memory (specified by ‘a’) The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register desig- nator ‘f’ represents the number of the file in which the bit is located.  2011 Microchip Technology Inc. DS39762F-page 375

PIC18F97J60 FAMILY TABLE 26-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh), or 2-bit FSR designator (0h to 3h). f 12-bit Register file address (000h to FFFh). This is the source address. s f 12-bit Register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No Change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-Down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a program memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or Unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for indirect addressing of register files (source). s z 7-bit offset value for indirect addressing of register files (destination). d { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr.  Assigned to. < > Register bit field.  In the set of. italics User-defined term (font is Courier New). DS39762F-page 376  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC  2011 Microchip Technology Inc. DS39762F-page 377

PIC18F97J60 FAMILY TABLE 26-2: PIC18F97J60 FAMILY INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39762F-page 378  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 26-2: PIC18F97J60 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call Subroutine1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.  2011 Microchip Technology Inc. DS39762F-page 379

PIC18F97J60 FAMILY TABLE 26-2: PIC18F97J60 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move Literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY  PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39762F-page 380  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 26.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) + k  W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f)  dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ADDLW 15h mode whenever f 95 (5Fh). See Before Instruction Section26.2.3 “Byte-Oriented and W = 10h Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = 25h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).  2011 Microchip Technology Inc. DS39762F-page 381

PIC18F97J60 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0  f  255 Operands: 0  k  255 d [0,1] Operation: (W) .AND. k  W a [0,1] Status Affected: N, Z Operation: (W) + (f) + (C)  dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read literal Process Write to GPR bank (default). ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: ANDLW 05Fh in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Before Instruction Section26.2.3 “Byte-Oriented and W = A3h Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = 03h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS39762F-page 382  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0  f  255 Operands: -128  n  127 d [0,1] Operation: if Carry bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: (W) .AND. (f)  dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ’1’, then the program Description: The contents of W are ANDed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’ (default). incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a GPR bank (default). two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates Cycles: 1(2) in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Q Cycle Activity: Section26.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to Words: 1 ‘n’ Data PC No No No No Cycles: 1 operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If Carry = 1; W = 02h PC = address (HERE + 12) REG = C2h If Carry = 0; PC = address (HERE + 2)  2011 Microchip Technology Inc. DS39762F-page 383

PIC18F97J60 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0  f  255 Operands: -128  n  127 0  b  7 Operation: if Negative bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: 0  f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank (default). incremented to fetch the next instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Words: 1 Section26.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to Q Cycle Activity: ‘n’ Data PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No ‘n’ Data operation Before Instruction FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS39762F-page 384  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128  n  127 Operands: -128  n  127 Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’, (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2)  2011 Microchip Technology Inc. DS39762F-page 385

PIC18F97J60 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128  n  127 Operands: -128  n  127 Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’, (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS39762F-page 386  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024  n  1023 Operands: 0  f  255 0  b  7 Operation: (PC) + 2 + 2n  PC a [0,1] Status Affected: None Operation: 1  f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected. PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the two-cycle instruction. GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section26.2.3 “Byte-Oriented and Decode Read literal Process Write to Bit-Oriented Instructions in Indexed ‘n’ Data PC Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah  2011 Microchip Technology Inc. DS39762F-page 387

PIC18F97J60 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0  f  255 Operands: 0  f  255 0  b  7 0  b < 7 a [0,1] a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set If ‘a’ is ‘0’ and the extended instruction is enabled, this instruction operates in set is enabled, this instruction operates in Indexed Literal Offset Addressing mode Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See whenever f 95 (5Fh). See Section26.2.3 “Byte-Oriented and Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39762F-page 388  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0  f  255 Operands: -128  n  127 0  b < 7 Operation: if Overflow bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: (f<b>)  f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank (default). instruction, the new address will be PC + 2 + 2n. This instruction is then a If ‘a’ is ‘0’ and the extended instruction two-cycle instruction. set is enabled, this instruction operates in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Cycles: 1(2) Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Q1 Q2 Q3 Q4 Words: 1 Decode Read literal Process Write to PC Cycles: 1 ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: Before Instruction PORTC = 0110 0101 [65h] PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2)  2011 Microchip Technology Inc. DS39762F-page 389

PIC18F97J60 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128  n  127 Operands: 0  k  1048575 s [0,1] Operation: if Zero bit is ‘1’, (PC) + 2 + 2n  PC Operation: (PC) + 4  TOS, k  PC<20:1>; Status Affected: None if s = 1, Encoding: 1110 0000 nnnn nnnn (W)  WS, Description: If the Zero bit is ‘1’, then the program (STATUS)  STATUSS, will branch. (BSR)  BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will have Encoding: incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk 7 0 instruction, the new address will be 2nd word(k<19:8>) 1111 k kkk kkkk kkkk 19 8 PC + 2 + 2n. This instruction is then a Description: Subroutine call of entire 2-Mbyte two-cycle instruction. memory range. First, return address Words: 1 (PC+ 4) is pushed onto the return stack. Cycles: 1(2) If ‘s’ = 1, the W, STATUS and BSR registers are also pushed into their Q Cycle Activity: respective shadow registers, WS, If Jump: STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs (default). Then, the Decode Read literal Process Write to 20-bit value ‘k’ is loaded into PC<20:1>. ‘n’ Data PC CALL is a two-cycle instruction. No No No No Words: 2 operation operation operation operation Cycles: 2 If No Jump: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No ‘n’ Data operation Decode Read literal Push PC to Read literal ‘k’<7:0>, stack ’k’<19:8>, Write to PC Example: HERE BZ Jump No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction Example: HERE CALL THERE,1 If Zero = 1; PC = address (Jump) Before Instruction If Zero = 0; PC = address (HERE) PC = address (HERE + 2) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39762F-page 390  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0  f  255 Operands: None a [0,1] Operation: 000h  WDT, Operation: 000h  f, 000h  WDT postscaler, 1  Z 1  TO, 1  PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the Watchdog Timer. It also resets the post- If ‘a’ is ‘0’, the Access Bank is selected. scaler of the WDT. Status bits, TO and If ‘a’ is ‘1’, the BSR is used to select the PD, are set. GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Cycles: 1 in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Decode No Process No Literal Offset Mode” for details. operation Data operation Words: 1 Example: CLRWDT Cycles: 1 Before Instruction Q Cycle Activity: WDT Counter = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write WDT Counter = 00h register ‘f’ Data register ‘f’ WDT Postscaler = 0 TO = 1 PD = 1 Example: CLRF FLAG_REG,1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h  2011 Microchip Technology Inc. DS39762F-page 391

PIC18F97J60 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: (f)  dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank (default). instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank (default). mode whenever f 95 (5Fh). See Section26.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Words: 1 Section26.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Cycles: 1(2) register ‘f’ Data destination Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h W = ECh Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG  W; PC = Address (NEQUAL) DS39762F-page 392  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0  f  255 Operands: 0  f  255 a  [0,1] a  [0,1] Operation: (f) –W), Operation: (f) –W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of the W by Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the If the contents of ‘f’ are less than the contents of WREG, then the fetched contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Note: 3 cycles if skip and followed Section26.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 Words: 1 Decode Read Process No Cycles: 1(2) register ‘f’ Data operation Note: 3 cycles if skip and followed If skip: by a 2-word instruction. Q1 Q2 Q3 Q4 Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process No If skip and followed by 2-word instruction: register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; PC = Address (LESS) Before Instruction If REG  W; PC = Address (HERE) PC = Address (NLESS) W = ? After Instruction If REG  W; PC = Address (GREATER) If REG  W; PC = Address (NGREATER)  2011 Microchip Technology Inc. DS39762F-page 393

PIC18F97J60 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0  f  255 d  [0,1] Operation: If [W<3:0> > 9] or [DC = 1], then a  [0,1] (W<3:0>) + 6  W<3:0>; else Operation: (f) – 1  dest (W<3:0>)  W<3:0> Status Affected: C, DC, N, OV, Z If [W<7:4> > 9] or [C = 1], then Encoding: 0000 01da ffff ffff (W<7:4>) + 6  W<7:4>, Description: Decrement register ‘f’. If ‘d’ is ‘0’, the C =1; result is stored in W. If ‘d’ is ‘1’, the else result is stored back in register ‘f’ (W<7:4>)  W<7:4> (default). Status Affected: C If ‘a’ is ‘0’, the Access Bank is selected. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Description: DAW adjusts the eight-bit value in W, resulting from the earlier addition of two If ‘a’ is ‘0’ and the extended instruction variables (each in packed BCD format) set is enabled, this instruction operates and produces a correct packed BCD in Indexed Literal Offset Addressing result. mode whenever f 95 (5Fh). See Section26.2.3 “Byte-Oriented and Words: 1 Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write Q Cycle Activity: register W Data W Q1 Q2 Q3 Q4 Decode Read Process Write to Example 1: DAW register ‘f’ Data destination Before Instruction W = A5h C = 0 Example: DECF CNT, 1, 0 DC = 0 Before Instruction After Instruction CNT = 01h W = 05h Z = 0 C = 1 DC = 0 After Instruction CNT = 00h Example 2: Z = 1 Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS39762F-page 394  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – 1  dest, Operation: (f) – 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is ‘0’, the next instruction If the result is not ‘0’, the next which is already fetched is discarded instruction which is already fetched is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing Section26.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See Bit-Oriented Instructions in Indexed Section26.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT  0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP  0; PC = Address (NZERO)  2011 Microchip Technology Inc. DS39762F-page 395

PIC18F97J60 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0  k  1048575 Operands: 0  f  255 d  [0,1] Operation: k  PC<20:1> a  [0,1] Status Affected: None Operation: (f) + 1  dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire 2-Mbyte memory incremented. If ‘d’ is ‘0’, the result is range. The 20-bit value ‘k’ is loaded into placed in W. If ‘d’ is ‘1’, the result is PC<20:1>. GOTO is always a two-cycle placed back in register ‘f’ (default). instruction. If ‘a’ is ‘0’, the Access Bank is selected. Words: 2 If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Cycles: 2 If ‘a’ is ‘0’ and the extended instruction Q Cycle Activity: set is enabled, this instruction operates Q1 Q2 Q3 Q4 in Indexed Literal Offset Addressing Decode Read literal No Read literal mode whenever f 95 (5Fh). See ‘k’<7:0>, operation ‘k’<19:8>, Section26.2.3 “Byte-Oriented and Write to PC Bit-Oriented Instructions in Indexed No No No No Literal Offset Mode” for details. operation operation operation operation Words: 1 Cycles: 1 Example: GOTO THERE Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 PC = Address (THERE) Decode Read Process Write to register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS39762F-page 396  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) + 1  dest, Operation: (f) + 1  dest, skip if result  0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’. (default) If the result is not ‘0’, the next If the result is ‘0’, the next instruction instruction which is already fetched is which is already fetched is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section26.2.3 “Byte-Oriented and Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG  0; PC = Address (ZERO) PC = Address (NZERO) If CNT  0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO)  2011 Microchip Technology Inc. DS39762F-page 397

PIC18F97J60 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) .OR. k  W a  [0,1] Status Affected: N, Z Operation: (W) .OR. (f)  dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: IORLW 35h in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Before Instruction Section26.2.3 “Byte-Oriented and W = 9Ah Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = BFh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS39762F-page 398  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0  f  2 Operands: 0  f  255 0  k  4095 d  [0,1] a  [0,1] Operation: k  FSRf Operation: f  dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to File Select Register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’ (default). Q Cycle Activity: Location ‘f’ can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 Decode Read literal Process Write If ‘a’ is ‘0’, the Access Bank is selected. ‘k’ MSB Data literal ‘k’ If ‘a’ is ‘1’, the BSR is used to select the MSB to GPR bank (default). FSRfH If ‘a’ is ‘0’ and the extended instruction Decode Read literal Process Write literal set is enabled, this instruction operates ‘k’ LSB Data ‘k’ to FSRfL in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section26.2.3 “Byte-Oriented and Example: LFSR 2, 3ABh Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. FSR2H = 03h FSR2L = ABh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data W Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h  2011 Microchip Technology Inc. DS39762F-page 399

PIC18F97J60 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0  f  4095 Operands: 0  k  255 s 0  f  4095 d Operation: k  BSR Operation: (f )  f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffff s Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffff d of BSR<7:4> always remains ‘0’ Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Decode Read Process Write literal Either source or destination can be W literal ‘k’ Data ‘k’ to BSR (a useful special situation). MOVFF is particularly useful for Example: MOVLB 5 transferring a data memory location to a peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h After Instruction The MOVFF instruction cannot use the BSR Register = 05h PCL, TOSU, TOSH or TOSL as the destination register Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS39762F-page 400  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: k  W Operation: (W)  f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: MOVLW 5Ah in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See After Instruction Section26.2.3 “Byte-Oriented and W = 5Ah Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh  2011 Microchip Technology Inc. DS39762F-page 401

PIC18F97J60 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: (W) x k  PRODH:PRODL Operation: (W) x (f)  PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried out 8-bit literal ‘k’. The 16-bit result is between the contents of W and the placed in PRODH:PRODL register pair. register file location ‘f’. The 16-bit result is PRODH contains the high byte. stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W is unchanged. W and ‘f’ are unchanged. None of the Status flags are affected. None of the Status flags are affected. Note that neither Overflow nor Carry is Note that neither Overflow nor Carry is possible in this operation. A Zero result possible in this operation. A Zero result is is possible but not detected. possible but not detected. Words: 1 If ‘a’ is ‘0’, the Access Bank is selected. If Cycles: 1 ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set Decode Read Process Write is enabled, this instruction operates in literal ‘k’ Data registers Indexed Literal Offset Addressing mode PRODH: whenever f 95 (5Fh). See PRODL Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: MULLW 0C4h Words: 1 Before Instruction W = E2h Cycles: 1 PRODH = ? Q Cycle Activity: PRODL = ? Q1 Q2 Q3 Q4 After Instruction W = E2h Decode Read Process Write PRODH = ADh register ‘f’ Data registers PRODL = 08h PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS39762F-page 402  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0  f  255 Operands: None a  [0,1] Operation: No operation Operation: (f) + 1  f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h]  2011 Microchip Technology Inc. DS39762F-page 403

PIC18F97J60 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC + 2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS39762F-page 404  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n  PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC + 2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC + 2 + 2n. This instruction is a Decode Start No No two-cycle instruction. reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Flags* = Reset Value Decode Read literal Process Write to PC ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2)  2011 Microchip Technology Inc. DS39762F-page 405

PIC18F97J60 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, Operation: k  W, 1  GIE/GIEH or PEIE/GIEL; (TOS)  PC, if s = 1, PCLATU, PCLATH are unchanged (WS)  W, Status Affected: None (STATUSS)  STATUS, (BSRS)  BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 Global Interrupt Enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers WS, Q1 Q2 Q3 Q4 STATUSS and BSRS are loaded into Decode Read Process POP PC their corresponding registers W, literal ‘k’ Data from stack, STATUS and BSR. If ‘s’ = 0, no update write to W of these registers occurs (default). No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS RETLW kn ; End of table W = WS BSR = BSRS STATUS = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn DS39762F-page 406  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s  [0,1] Operands: 0  f  255 d  [0,1] Operation: (TOS)  PC; a  [0,1] if s = 1, (WS)  W, Operation: (f<n>)  dest<n + 1>, (STATUSS)  STATUS, (f<7>)  C, (BSRS)  BSR, (C)  dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry flag. popped and the top of the stack (TOS) If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is loaded into the program counter. If is ‘1’, the result is stored back in register ‘s’= 1, the contents of the shadow ‘f’ (default). registers WS, STATUSS and BSRS are If ‘a’ is ‘0’, the Access Bank is selected. loaded into their corresponding If ‘a’ is ‘1’, the BSR is used to select the registers W, STATUS and BSR. If GPR bank (default). ‘s’ = 0, no update of these registers occurs (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 2 mode whenever f 95 (5Fh). See Section26.2.3 “Byte-Oriented and Q Cycle Activity: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1  2011 Microchip Technology Inc. DS39762F-page 407

PIC18F97J60 FAMILY RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f<n>)  dest<n + 1>, Operation: (f<n>)  dest<n – 1>, (f<7>)  dest<0> (f<0>)  C, (C)  dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘0’, the Access Bank is selected. register ‘f’ (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank (default). set is enabled, this instruction operates in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f 95 (5Fh). See set is enabled, this instruction operates Section26.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f 95 (5Fh). See Literal Offset Mode” for details. Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39762F-page 408  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY RRNCF Rotate Right f (no carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a [0,1] a  [0,1] Operation: FFh  f Operation: (f<n>)  dest<n – 1>, Status Affected: None (f<0>)  dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank (default). placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f 95 (5Fh). See per the BSR value (default). Section26.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Section26.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111  2011 Microchip Technology Inc. DS39762F-page 409

PIC18F97J60 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 f 255 d  [0,1] Operation: 00h  WDT, a  [0,1] 0  WDT postscaler, 1  TO, Operation: (W) – (f) – (C) dest 0  PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored in is set. The Watchdog Timer and its W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’ (default). The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is selected. If with the oscillator stopped. ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction operates in Q Cycle Activity: Indexed Literal Offset Addressing mode Q1 Q2 Q3 Q4 whenever f 95 (5Fh). See Decode No Process Go to Section26.2.3 “Byte-Oriented and operation Data Sleep Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to TO = 1 † register ‘f’ Data destination PD = 0 Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39762F-page 410  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 k 255 Operands: 0 f 255 d  [0,1] Operation: k – (W) W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the result Q Cycle Activity: is stored back in register ‘f’ (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read Process Write to If ‘a’ is ‘1’, the BSR is used to select the literal ‘k’ Data W GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction operates Before Instruction in Indexed Literal Offset Addressing W = 01h mode whenever f 95 (5Fh). See C = ? Section26.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 01h Literal Offset Mode” for details. C = 1 ; result is positive Z = 0 Words: 1 N = 0 Cycles: 1 Example 2: SUBLW 02h Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 W = 02h C = ? Decode Read Process Write to After Instruction register ‘f’ Data destination W = 00h C = 1 ; result is zero Example 1: SUBWF REG, 1, 0 Z = 1 Before Instruction N = 0 REG = 3 W = 2 Example 3: SUBLW 02h C = ? Before Instruction After Instruction W = 03h REG = 1 C = ? W = 2 After Instruction C = 1 ; result is positive W = FFh ; (2’s complement) Z = 0 C = 0 ; result is negative N = 0 Z = 0 Example 2: SUBWF REG, 0, 0 N = 1 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1  2011 Microchip Technology Inc. DS39762F-page 411

PIC18F97J60 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: (f<3:0>)  dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>)  dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored Description: The upper and lower nibbles of register in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing Section26.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) REG = 35h C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39762F-page 412  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD*, TBLPTR = 00A356h (Prog Mem (TBLPTR))  TABLAT; MEMORY(00A356h) = 34h TBLPTR – No Change After Instruction if TBLRD*+, TABLAT = 34h (Prog Mem (TBLPTR))  TABLAT; TBLPTR = 00A357h (TBLPTR) + 1  TBLPTR Example 2: TBLRD +* ; if TBLRD*-, (Prog Mem (TBLPTR))  TABLAT; Before Instruction (TBLPTR) – 1  TBLPTR TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY(01A357h) = 12h (TBLPTR) + 1  TBLPTR; MEMORY(01A358h) = 34h (Prog Mem (TBLPTR))  TABLAT After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write Memory) TABLAT)  2011 Microchip Technology Inc. DS39762F-page 413

PIC18F97J60 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT*+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT)  Holding Register; TBLPTR = 00A356h HOLDING REGISTER TBLPTR – No Change (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT)  Holding Register; TABLAT = 55h (TBLPTR) + 1  TBLPTR TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT)  Holding Register; (00A356h) = 55h (TBLPTR) – 1  TBLPTR Example 2: TBLWT +*; if TBLWT+*, Before Instruction (TBLPTR) + 1  TBLPTR; TABLAT = 34h (TABLAT)  Holding Register TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER 8 holding registers the TABLAT is written (01389Bh) = 34h to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section6.0 “Memory Organization” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register) DS39762F-page 414  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0  f  255 Operands: 0 k 255 a  [0,1] Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to set is enabled, this instruction operates literal ‘k’ Data W in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: XORLW 0AFh Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Before Instruction Literal Offset Mode” for details. W = B5h After Instruction Words: 1 W = 1Ah Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT  00h, PC = Address (NZERO)  2011 Microchip Technology Inc. DS39762F-page 415

PIC18F97J60 FAMILY XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS39762F-page 416  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 26.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table26-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section26.2.2 “Extended Instruction instruction set, the PIC18F97J60 family of devices also Set”. The opcode field descriptions in Table26-1 (page provide an optional extension to the core CPU function- 376) apply to both the standard and extended PIC18 ality. The added features include eight additional instruction sets. instructions that augment Indirect and Indexed Addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction set these instructions directly in assembler. are enabled by default on unprogrammed devices. The syntax for these commands is Users must properly set or clear the XINST Configura- provided as a reference for users who tion bit during programming to enable or disable these may be reviewing code that has been features. generated by a compiler. The instructions in the extended set can all be classified as literal operations, which either manipulate 26.2.1 EXTENDED INSTRUCTION SYNTAX the File Select Registers, or use them for Indexed Most of the extended instructions use indexed argu- Addressing. Two of the instructions, ADDFSR and ments, using one of the File Select Registers and some SUBFSR, each have an additional special instantiation offset to specify a source or destination register. When for using FSR2. These versions (ADDULNK and an argument for an instruction serves as part of SUBULNK) allow for automatic return after execution. Indexed Addressing, it is enclosed in square brackets The extended instructions are specifically implemented (“[ ]”). This is done to indicate that the argument is used to optimize reentrant program code (that is, code that is as an index or offset. The MPASM™ Assembler will recursive or that uses a software stack) written in flag an error if it determines that an index or offset value high-level languages, particularly C. Among other is not bracketed. things, they allow users working in high-level When the extended instruction set is enabled, brackets languages to perform certain operations on data are also used to indicate index arguments in structures more efficiently. These include: byte-oriented and bit-oriented instructions. This is in • Dynamic allocation and deallocation of software addition to other changes in their syntax. For more stack space when entering and leaving details, see Section26.2.3.1 “Extended Instruction subroutines Syntax with Standard PIC18 Commands”. • Function Pointer invocation Note: In the past, square brackets have been • Software Stack Pointer manipulation used to denote optional arguments in the • Manipulation of variables located in a software PIC18 and earlier instruction sets. In this stack text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 26-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None Decrement FSR2 SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None Return  2011 Microchip Technology Inc. DS39762F-page 417

PIC18F97J60 FAMILY 26.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 + k  FSR2, Operation: FSR(f) + k  FSR(f) (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. Q Cycle Activity: The instruction takes two cycles to Q1 Q2 Q3 Q4 execute; a NOP is performed during the second cycle. Decode Read Process Write to literal ‘k’ Data FSR This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates Example: ADDFSR 2, 23h only on FSR2. Before Instruction Words: 1 FSR2 = 03FFh Cycles: 2 After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS39762F-page 418  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY CALLW Subroutine Call using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0  z  127 s 0  f  4095 Operation: (PC + 2)  TOS, d (W)  PCL, Operation: ((FSR2) + z )  f s d (PCLATH)  PCH, Status Affected: None (PCLATU)  PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffff d Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’, in the first word, to the value s latched into PCH and PCU, of FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘fd’ in the second word. Both addresses new next instruction is fetched. can be anywhere in the 4096-byte data space (000h to FFFh). Unlike CALL, there is no option to update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an indirect addressing register, the Q1 Q2 Q3 Q4 value returned will be 00h. Decode Read Push PC to No Words: 2 WREG stack operation Cycles: 2 No No No No operation operation operation operation Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Before Instruction Decode No No Write PC = address (HERE) operation operation register ‘f’ PCLATH = 10h No dummy (dest) PCLATU = 00h W = 06h read After Instruction PC = 001006h TOS = address (HERE + 2) Example: MOVSF [05h], REG2 PCLATH = 10h PCLATU = 00h Before Instruction W = 06h FSR2 = 80h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h  2011 Microchip Technology Inc. DS39762F-page 419

PIC18F97J60 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0  zs  127 Operands: 0k  255 0  z  127 d Operation: k  (FSR2), Operation: ((FSR2) + zs)  ((FSR2) + zd) FSR2 – 1  FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1110 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. Description The contents of the source register are FSR2 is decremented by 1 after the moved to the destination register. The operation. addresses of the source and destination registers are determined by adding the This instruction allows users to push 7-bit literal offsets ‘z ’ or ‘z ’, values onto a software stack. s d respectively, to the value of FSR2. Both Words: 1 registers can be located anywhere in the 4096-byte data memory space Cycles: 1 (000h to FFFh). Q Cycle Activity: The MOVSS instruction cannot use the Q1 Q2 Q3 Q4 PCL, TOSU, TOSH or TOSL as the Decode Read ‘k’ Process Write to destination register. data destination If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the Example: PUSHL 08h resultant destination address points to Before Instruction an indirect addressing register, the FSR2H:FSR2L = 01ECh instruction will execute as a NOP. Memory (01ECh) = 00h Words: 2 After Instruction Cycles: 2 FSR2H:FSR2L = 01EBh Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS39762F-page 420  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 – k  FSR2, Operation: FSRf – k  FSRf (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified contents of the FSR2. A RETURN is then by ‘f’. executed by loading the PC with the TOS. Words: 1 Cycles: 1 The instruction takes two cycles to execute; a NOP is performed during the Q Cycle Activity: second cycle. Q1 Q2 Q3 Q4 This may be thought of as a special case Decode Read Process Write to of the SUBFSR instruction, where f = 3 register ‘f’ Data destination (binary ‘11’); it operates only on FSR2. Words: 1 Example: SUBFSR 2, 23h Cycles: 2 Before Instruction Q Cycle Activity: FSR2 = 03FFh Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to FSR2 = 03DCh register ‘f’ Data destination No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS)  2011 Microchip Technology Inc. DS39762F-page 421

PIC18F97J60 FAMILY 26.2.3 BYTE-ORIENTED AND 26.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file register argument ‘f’ in the standard byte-oriented and Note: Enabling the PIC18 instruction set exten- bit-oriented commands is replaced with the literal offset sion may cause legacy applications to value ‘k’. As already noted, this occurs only when ‘f’ is behave erratically or fail entirely. less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing (Section6.6.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within the brackets, will the standard PIC18 instruction set are interpreted. generate an error in the MPASM Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is either as a location in the Access Bank (a = 0) or in a never specified; it will automatically be assumed to be GPR bank designated by the BSR (a = 1). When the ‘0’. This is in contrast to standard operation (extended extended instruction set is enabled and a = 0, however, instruction set disabled), when ‘a’ is set on the basis of a file register argument of 5Fh or less is interpreted as the target address. Declaring the Access RAM bit in an offset from the pointer value in FSR2 and not as a this mode will also generate an error in the MPASM literal address. For practical purposes, this means that Assembler. all instructions that use the Access RAM bit as an The destination argument ‘d’ functions as before. argument – that is, all byte-oriented and bit-oriented instructions, or almost half of the core PIC18 instruc- In the latest versions of the MPASM Assembler, tions – may behave differently when the extended language support for the extended instruction set must instruction set is enabled. be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the When the content of FSR2 is 00h, the boundaries of the source listing. Access RAM are essentially remapped to their original values. This may be useful in creating 26.2.4 CONSIDERATIONS WHEN backward-compatible code. If this technique is used, it ENABLING THE EXTENDED may be necessary to save the value of FSR2 and INSTRUCTION SET restore it when moving back and forth between C and assembly routines in order to preserve the Stack It is important to note that the extensions to the instruc- Pointer. Users must also keep in mind the syntax tion set may not be beneficial to all users. In particular, requirements of the extended instruction set (see users who are not writing code that uses a software Section26.2.3.1 “Extended Instruction Syntax with stack may not benefit from using the extensions to the Standard PIC18 Commands”). instruction set. Although the Indexed Literal Offset mode can be very Additionally, the Indexed Literal Offset Addressing useful for dynamic stack and pointer manipulation, it mode may create issues with legacy applications can also be very annoying if a simple arithmetic opera- written to the PIC18 assembler. This is because tion is carried out on the wrong register. Users who are instructions in the legacy code may attempt to address accustomed to the PIC18 programming must keep in registers in the Access Bank below 5Fh. Since these mind that, when the extended instruction set is addresses are interpreted as literal offsets to FSR2 enabled, register addresses of 5Fh or less are used for when the instruction set extension is enabled, the Indexed Literal Offset Addressing. application may read or write to the wrong data addresses. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset When porting an application to the PIC18F97J60 fam- mode are provided on the following page to show how ily, it is very important to consider the type of code. A execution is affected. The operand conditions shown in large, reentrant application that is written in C and the examples are applicable to all instructions of these would benefit from efficient compilation will do well types. when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39762F-page 422  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0  k  95 Operands: 0  f  95 d  [0,1] 0  b  7 Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ Cycles: 1 is ‘1’, the result is stored back in register ‘f’ (default). Q Cycle Activity: Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1 register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Contents Example: ADDWF [OFST],0 of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction Set Indexed SETF W = 37h (Indexed Literal Offset mode) Contents of 0A2Ch = 20h Syntax: SETF [k] Operands: 0  k  95 Operation: FFh  ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh  2011 Microchip Technology Inc. DS39762F-page 423

PIC18F97J60 FAMILY 26.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set for the PIC18F97J60 family. This includes the • A menu option or dialog box within the MPLAB C18 C Compiler, MPASM assembly language environment that allows the user to configure the and MPLAB Integrated Development Environment language tool and its settings for the project (IDE). • A command line option When selecting a target device for software • A directive in the source code development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for These options vary between different compilers, the XINST Configuration bit is ‘0’, disabling the assemblers and development environments. Users are extended instruction set and Indexed Literal Offset encouraged to review the documentation accompany- Addressing. For proper execution of applications ing their development systems for the appropriate developed to take advantage of the extended information. instruction set, XINST must be set during programming. DS39762F-page 424  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 27.0 DEVELOPMENT SUPPORT 27.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2011 Microchip Technology Inc. DS39762F-page 425

PIC18F97J60 FAMILY 27.2 MPLAB C Compilers for Various 27.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 27.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 27.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 27.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS39762F-page 426  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 27.7 MPLAB SIM Software Simulator 27.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 27.10 PICkit 3 In-Circuit Debugger/ Programmer and 27.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2011 Microchip Technology Inc. DS39762F-page 427

PIC18F97J60 FAMILY 27.11 PICkit 2 Development 27.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 27.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39762F-page 428  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 28.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any digital only input pin or MCLR with respect to VSS (except VDD)........................................-0.3V to 6.0V Voltage on any combined digital and analog pin with respect to VSS.............................................-0.3V to (VDD + 0.3V) Voltage on VDDCORE with respect to VSS...................................................................................................-0.3V to 2.75V Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD) (Note 2)0mA Output clamp current, IOK (VO < 0 or VO > VDD) (Note 2)0mA Maximum output current sunk by any PORTB and PORTC I/O pins......................................................................25mA Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins..........................................................8mA Maximum output current sunk by any PORTA, PORTF, PORTG and PORTH I/O pins (Note 3).............................2mA Maximum output current sourced by any PORTB and PORTC I/O pins.................................................................25mA Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins.....................................................8mA Maximum output current sourced by any PORTA, PORTF, PORTG and PORTH I/O pins (Note 3)........................2mA Maximum current sunk byall ports combined.......................................................................................................200mA Maximum current sourced by all ports combined..................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) + (VTPOUT x ITPOUT) 2: No clamping diodes are present. 3: Exceptions are RA<1> and RA<0>, which are capable of directly driving LEDs up to 25mA. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2011 Microchip Technology Inc. DS39762F-page 429

PIC18F97J60 FAMILY FIGURE 28-1: PIC18F97J60 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (ENVREG TIED TO VDD) 4.0V 3.6V 3.5V PIC18F6XJ6X/8XJ6X/9XJ6X 1) 3.0V () D D 2.7V V 2.5V ( e g a t 2.0V ol V 0 Frequency 41.6667 MHz Note 1: When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset before VDD reaches a level at which full-speed operation is not possible. FIGURE 28-2: PIC18F97J60 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (ENVREG TIED TO VSS) 3.00V 2.75V 2.7V 1) ()E 2.50V PIC18F6XJ6X/8XJ6X/9XJ6X R O 2.35V C D 2.25V D V ( e 2.00V g a t ol V 4 MHz 41.6667 MHz Frequency For frequencies between 4 MHz and 41.6667 MHz, FMAX = (107.619 MHz/V) * (VDDCORE – 2V) + 4 MHz. Note 1: When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCOREVDD3.6V. DS39762F-page 430  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 28.1 DC Characteristics: Supply Voltage, PIC18F97J60 Family (Industrial) PIC18F97J60 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage VDDCORE — 3.6 V ENVREG tied to VSS 2.7 — 3.6 V ENVREG tied to VDD 3.1 — 3.6 V Ethernet module enabled (ECON2<5> = 1) D001B VDDCORE External Supply for 2.0 — 2.7 V Microcontroller Core D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Power-on Reset — — 0.7 V See Section5.3 “Power-on Voltage Reset (POR)” for details D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section5.3 “Power-on to Ensure Internal Reset (POR)” for details Power-on Reset D005 BOR Brown-out Reset 2.35 2.4 2.7 V Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.  2011 Microchip Technology Inc. DS39762F-page 431

PIC18F97J60 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F97J60 Family (Industrial) PIC18F97J60 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) All devices 19.0 69.0 A -40°C VDD = 2.0V, 21.0 69.0 A +25°C VDDCORE = 2.0V(4) 45.0 149.0 A +85°C (Sleep mode) All devices 26.0 104.0 A -40°C VDD = 2.5V, 29.0 104.0 A +25°C VDDCORE = 2.5V(4) 60.0 184.0 A +85°C (Sleep mode) All devices 40.0 203.0 A -40°C VDD = 3.3V(5) 44.0 203.0 A +25°C (Sleep mode) 105.0 209.0 A +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD). 6: For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing. DS39762F-page 432  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) PIC18F97J60 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) All devices 12.0 34.0 A -40°C VDD = 2.0V, 12.0 34.0 A +25°C VDDCORE = 2.0V(4) 74.0 108.0 A +85°C All devices 20.0 45.0 A -40°C FOSC = 31kHz VDD = 2.5V, 20.0 45.0 A +25°C VDDCORE = 2.5V(4) (RC_RUN mode, 82.0 126.0 A +85°C Internal Oscillator Source) All devices 105.0 168.0 A -40°C 105.0 168.0 A +25°C VDD = 3.3V(5) 182.0 246.0 A +85°C All devices 8.0 32.0 A -40°C VDD = 2.0V, 8.0 32.0 A +25°C VDDCORE = 2.0V(4) 62.0 98.0 A +85°C All devices 12.0 35.0 A -40°C FOSC = 31kHz VDD = 2.5V, 12.0 35.0 A +25°C VDDCORE = 2.5V(4) (RC_IDLE mode, 70.0 95.0 A +85°C Internal Oscillator Source) All devices 90.0 152.0 A -40°C 90.0 152.0 A +25°C VDD = 3.3V(5) 170.0 225.0 A +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD). 6: For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing.  2011 Microchip Technology Inc. DS39762F-page 433

PIC18F97J60 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) PIC18F97J60 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 0.8 1.5 mA -40°C VDD = 2.0V, 0.8 1.5 mA +25°C VDDCORE = 2.0V(4) 0.9 1.7 mA +85°C All devices 1.1 1.8 mA -40°C FOSC = 1MHZ VDD = 2.5V, 1.1 1.8 mA +25°C (PRI_RUN mode, VDDCORE = 2.5V(4) 1.2 2.0 mA +85°C EC oscillator) All devices 2.1 3.4 mA -40°C 2.0 3.4 mA +25°C VDD = 3.3V(5) 2.1 3.4 mA +85°C All devices 9.2 14.5 mA -40°C VDD = 2.5V, 9.0 14.5 mA +25°C VDDCORE = 2.5V(4) 9.2 14.5 mA +85°C FOSC = 25MHz (PRI_RUN mode, All devices 13.0 18.4 mA -40°C EC oscillator) 12.4 18.4 mA +25°C VDD = 3.3V(5) 13.0 18.4 mA +85°C All devices 13.4 19.8 mA -40°C VDD = 2.5V, 13.0 19.8 mA +25°C VDDCORE = 2.5V(4) 13.4 19.8 mA +85°C FOSC = 41.6667MHZ (PRI_RUN mode, All devices 14.5 21.6 mA -40°C EC oscillator) 14.4 21.6 mA +25°C VDD = 3.3V(5) 14.5 21.6 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD). 6: For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing. DS39762F-page 434  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) PIC18F97J60 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 2.8 5.2 mA -40°C VDD = 2.5V, 2.5 5.2 mA +25°C VDDCORE = 2.5V(4) 2.8 5.2 mA +85°C FOSC = 25MHZ, 2.7778 MHz internal All devices 3.6 6.4 mA -40°C (PRI_RUN HS mode) 3.3 6.4 mA +25°C VDD = 3.3V(5) 3.6 6.4 mA +85°C All devices 6.4 11.0 mA -40°C VDD = 2.5V, 6.0 11.0 mA +25°C VDDCORE = 2.5V(4) 6.4 11.0 mA +85°C FOSC = 25MHZ, 13.8889 MHz internal All devices 7.8 12.5 mA -40°C (PRI_RUN HSPLL mode) 7.4 12.5 mA +25°C VDD = 3.3V(5) 7.8 12.5 mA +85°C All devices 9.2 14.5 mA -40°C VDD = 2.5V, 9.0 14.5 mA +25°C VDDCORE = 2.5V(4) 9.2 14.5 mA +85°C FOSC = 25MHZ, 25 MHz internal All devices 13.0 18.4 mA -40°C (PRI_RUN HS mode) 12.4 18.4 mA +25°C VDD = 3.3V(5) 13.0 18.4 mA +85°C All devices 13.4 19.8 mA -40°C VDD = 2.5V, 13.0 19.8 mA +25°C VDDCORE = 2.5V(4) 13.4 19.8 mA +85°C FOSC = 25MHZ, 41.6667 MHz internal All devices 14.5 21.6 mA -40°C (PRI_RUN HSPLL mode) 14.4 21.6 mA +25°C VDD = 3.3V(5) 14.5 21.6 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD). 6: For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing.  2011 Microchip Technology Inc. DS39762F-page 435

PIC18F97J60 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) PIC18F97J60 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 0.5 1.1 mA -40°C VDD = 2.0V, 0.5 1.1 mA +25°C VDDCORE = 2.0V(4) 0.6 1.2 mA +85°C All devices 0.9 1.4 mA -40°C FOSC = 1MHz VDD = 2.5V, 0.9 1.4 mA +25°C (PRI_IDLE mode, VDDCORE = 2.5V(4) 1.0 1.5 mA +85°C EC oscillator) All devices 1.9 2.6 mA -40°C 1.8 2.6 mA +25°C VDD = 3.3V(5) 1.9 2.6 mA +85°C All devices 5.9 9.5 mA -40°C VDD = 2.5V, 5.6 9.5 mA +25°C VDDCORE = 2.5V(4) 5.9 9.5 mA +85°C FOSC = 25MHZ (PRI_IDLE mode, All devices 7.5 13.2 mA -40°C EC oscillator) 7.2 13.2 mA +25°C VDD = 3.3V(5) 7.5 13.2 mA +85°C All devices 8.6 14.0 mA -40°C VDD = 2.5V, 8.0 14.0 mA +25°C VDDCORE = 2.5V(4) 8.6 14.0 mA +85°C FOSC = 41.6667MHz (PRI_IDLE mode, All devices 9.8 16.0 mA -40°C EC oscillator) 9.4 16.0 mA +25°C VDD = 3.3V(5) 9.8 16.0 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD). 6: For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing. DS39762F-page 436  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) PIC18F97J60 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 22.0 45.0 A -10°C VDD = 2.0V, 22.0 45.0 A +25°C VDDCORE = 2.0V(4) 78.0 114.0 A +70°C All devices 27.0 52.0 A -10°C FOSC = 32kHz(3) VDD = 2.5V, 27.0 52.0 A +25°C VDDCORE = 2.5V(4) (SEC_RUN mode, 92.0 135.0 A +70°C Timer1 as clock) All devices 106.0 168.0 A -10°C 106.0 168.0 A +25°C VDD = 3.3V(5) 188.0 246.0 A +70°C All devices 18.0 37.0 A -10°C VDD = 2.0V, 18.0 37.0 A +25°C VDDCORE = 2.0V(4) 75.0 105.0 A +70°C All devices 21.0 40.0 A -10°C FOSC = 32kHz(3) VDD = 2.5V, 21.0 40.0 A +25°C VDDCORE = 2.5V(4) (SEC_IDLE mode, 84.0 98.0 A +70°C Timer1 as clock) All devices 94.0 152.0 A -10°C 94.0 152.0 A +25°C VDD = 3.3V(5) 182.0 225.0 A +70°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD). 6: For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing.  2011 Microchip Technology Inc. DS39762F-page 437

PIC18F97J60 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) PIC18F97J60 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Module Differential Currents (IWDT, IOSCB, IAD, IETH) D022 Watchdog Timer 2.4 7.0 A -40°C (IWDT) 2.4 7.0 A +25°C VDDVCDODR E= =2 .20.V0,V (4) 12.0 19.0 A +85°C 3.0 8.0 A -40°C VDD = 2.5V, 3.0 8.0 A +25°C VDDCORE = 2.5V(4) 14.0 22.0 A +85°C 5.0 12.0 A -40°C 5.0 12.0 A +25°C VDD = 3.3V(5) 19.0 30.0 A +85°C D025 Timer1 Oscillator 12.0 20.0 A -40°C (IOSCB) 12.0 20.0 A +25°C VDDVCDODR E= =2 .20.V0,V (4) 32kHz on Timer1(3) 24.0 36.0 A +85°C 13.0 21.0 A -40°C 13.0 21.0 A +25°C VDDVCDODR E= =2 .25.V5,V (4) 32kHz on Timer1(3) 26.0 38.0 A +85°C 14.0 25.0 A -40°C 14.0 25.0 A +25°C VDD = 3.3V(5) 32kHz on Timer1(3) 29.0 40.0 A +85°C D026 A/D Converter VDD = 2.0V, (IAD) 1.2 10.0 A -40°C to +85°C VDDCORE = 2.0V(4) VDD = 2.5V, A/D on, not converting 1.2 10.0 A -40°C to +85°C VDDCORE = 2.5V(4) 1.2 11.0 A -40°C to +85°C VDD = 3.3V(5) D027 Ethernet Module 130.0 156.0 mA -40°C to +85°C No transmit activity IETH(6) 180.0 214.0 mA -40°C to +85°C VDD = 3.3V(5) Transmission in progress Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD). 6: For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing. DS39762F-page 438  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 28.3 DC Characteristics: PIC18F97J60 Family (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage All I/O Ports: D030 with TTL Buffer VSS 0.15VDD V VDD<2.7V VSS 0.8 V 2.7V VDD 3.6V D031 with Schmitt Trigger Buffer VSS 0.2 VDD V D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V EC mode D034 T13CKI VSS 0.3 V VIH Input High Voltage I/O Ports, with Analog Functions: D040 with TTL Buffer 0.25 VDD + 0.8V VDD V D041 with Schmitt Trigger Buffer 0.8 VDD VDD V I/O Ports, Digital Only: with TTL Buffer 0.25 VDD + 0.8V 5.5 V with Schmitt Trigger Buffer 0.8 VDD 5.5 V D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC mode D044 T13CKI 1.6 VDD V IIL Input Leakage Current(1) D060 I/O Ports — 1 A VSS VPIN VDD, Pin at high-impedance D061 MCLR — 1 A Vss VPIN VDD D063 OSC1 — 1 A Vss VPIN VDD IPU Weak Pull-up Current D070 IPURB PORTB, PORTD, PORTE, PORTJ 80 400 A VDD = 3.3V, VPIN = VSS Note 1: Negative current is defined as current sourced by the pin.  2011 Microchip Technology Inc. DS39762F-page 439

PIC18F97J60 FAMILY 28.3 DC Characteristics: PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O Ports: PORTD, PORTE, — 0.4 V IOL = 4 mA, VDD = 3.3V, PORTJ -40C to +85C PORTA<5:2>, PORTF, — 0.4 V IOL = 2 mA, VDD = 3.3V, PORTG, PORTH -40C to +85C PORTA<1:0>, PORTB, — 0.4 V IOL = 8 mA, VDD = 3.3V, PORTC -40C to +85C D083 OSC2/CLKO — 0.4 V IOL = 2 mA, VDD = 3.3V, (EC, ECPLL modes) -40C to +85C VOH Output High Voltage(1) D090 I/O Ports: V PORTD, PORTE, 2.4 — V IOH = -4 mA, VDD = 3.3V, PORTJ -40C to +85C PORTA<5:2>, PORTF, 2.4 — V IOH = -2 mA, VDD = 3.3V, PORTG, PORTH -40C to +85C PORTA<1:0>, PORTB, 2.4 — V IOH = -8 mA, VDD = 3.3V, PORTC -40C to +85C D092 OSC2/CLKO 2.4 — V IOH = -1.0 mA, VDD = 3.3V, (EC, ECPLL modes) -40C to +85C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — 15 pF In HS mode when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 — 50 pF To meet the AC timing (in Internal RC mode, EC, ECPLL) specifications D102 CB SCLx, SDAx — 400 pF I2C™ specification Note 1: Negative current is defined as current sourced by the pin. DS39762F-page 440  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial Param Sym Characteristic Min Typ† Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 100 1K — E/W -40C to +85C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW Voltage for Self-Timed Erase or Write VDD 2.70 — 3.6 V ENVREG tied to VDD VDDCORE 2.35 — 2.7 V ENVREG tied to VSS D133A TIW Self-Timed Write Cycle Time — 2.8 — ms D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D135 IDDP Supply Current during — 10 — mA Ethernet module disabled Programming † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2011 Microchip Technology Inc. DS39762F-page 441

PIC18F97J60 FAMILY TABLE 28-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V  VDD  3.6V, -40°C  TA  +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage* — ±5.0 ±25 mV D301 VICM Input Common-Mode Voltage* 0 — AVDD – 1.5 V D302 CMRR Common-Mode Rejection Ratio* 55 — — dB 300 TRESP Response Time(1)* — 150 400 ns 301 TMC2OV Comparator Mode Change to — — 10 s Output Valid* * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (AVDD – 1.5)/2, while the other input transitions from VSS to AVDD. TABLE 28-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V  VDD  3.6V, -40°C  TA  +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb D312 VRUR Unit Resistor Value (R) — 2k —  310 TSET Settling Time(1) — — 10 s Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. TABLE 28-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C  TA  +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. VRGOUT Regulator Output Voltage — 2.5 — V CF External Filter Capacitor 1 10 — F Capacitor must be low Value series resistance DS39762F-page 442  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 28.4 AC (Timing) Characteristics 28.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc ECCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDIx sc SCKx do SDOx ss SSx dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-Impedance) V Valid L Low Z High-Impedance I2C only AA Output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition  2011 Microchip Technology Inc. DS39762F-page 443

PIC18F97J60 FAMILY 28.4.2 TIMING CONDITIONS The temperature and voltages specified in Table28-5 apply to all timing specifications unless otherwise noted. Figure28-3 specifies the load conditions for the timing specifications. TABLE 28-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA +85°C for industrial AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section28.1 “DC Characteristics: Supply Voltage, PIC18F97J60 Family (Industrial)” and Section28.3 “DC Characteristics: PIC18F97J60 Family (Industrial)”. FIGURE 28-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports CL = 15 pF for OSC2/CLKO DS39762F-page 444  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 28-4: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 28-6: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 41.6667 MHz EC Oscillator mode Oscillator Frequency(1) 6 25 MHz HS Oscillator mode 1 TOSC External CLKI Period(1) 24 — ns EC Oscillator mode Oscillator Period(1) 40 167 ns HS Oscillator mode 2 TCY Instruction Cycle Time(1) 96 — ns TCY = 4/FOSC, Industrial 3 TOSL, External Clock in (OSC1) 10 — ns EC Oscillator mode TOSH High or Low Time 4 TOSR, External Clock in (OSC1) — 7.5 ns EC Oscillator mode TOSF Rise or Fall Time 5 Clock Frequency Tolerance — ±50 ppm Ethernet module enabled Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.  2011 Microchip Technology Inc. DS39762F-page 445

PIC18F97J60 FAMILY TABLE 28-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.6V TO 3.6V) Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FOSC Oscillator Frequency Range 8 — 25 MHz HSPLL mode 8 — 37.5 MHz ECPLL mode F11 FSYS On-Chip VCO System Frequency 20 — 62.5 MHz F12 t PLL Start-up Time (Lock Time) — — 2 ms rc F13 CLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 3.3V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 28-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F97J60 FAMILY (INDUSTRIAL) Param Characteristic Min Typ Max Units Conditions No. INTRC Accuracy @ Freq = 31 kHz(1) 21.7 — 40.3 kHz Note 1: INTRC frequency changes as VDDCORE changes. DS39762F-page 446  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 28-5: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 12 13 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure28-3 for load conditions. TABLE 28-9: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1  to CLKO  — 75 200 ns 11 TOSH2CKH OSC1  to CLKO  — 75 200 ns 12 TCKR CLKO Rise Time — 15 30 ns 13 TCKF CLKO Fall Time — 15 30 ns 14 TCKL2IOV CLKO  to Port Out Valid — — 0.5 TCY + 20 ns 15 TIOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns 16 TCKH2IOI Port In Hold after CLKO  0 — — ns 17 TOSH2IOV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1  (Q2 cycle) to Port Input Invalid 100 — — ns (I/O in hold time) 19 TIOV2OSH Port Input Valid to OSC1  0 — — ns (I/O in setup time) 20 TIOR Port Output Rise Time — — 6 ns 21 TIOF Port Output Fall Time — — 5 ns 22† TINP INTx pin High or Low Time TCY — — ns 23† TRBP RB<7:4> Change INTx High or Low Time TCY — — ns † These parameters are asynchronous events not related to any internal clock edges.  2011 Microchip Technology Inc. DS39762F-page 447

PIC18F97J60 FAMILY FIGURE 28-6: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 AD<15:0> Address Data from External Address 150 160 163 151 162 161 155 166 167 168 ALE 164 169 171 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C, unless otherwise stated. TABLE 28-10: CLKO AND I/O TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE  0.25 TCY – 10 — — ns (address setup time) 151 TalL2adl ALE  to Address Out Invalid 5 — — ns (address hold time) 155 TalL2oeL ALE to OE  10 0.125 TCY — ns 160 TadZ2oeL AD high-Z to OE (bus release to OE) 0 — — ns 161 ToeH2adD OE  to AD Driven 0.125 TCY – 5 — — ns 162 TadV2oeH Least Significant Data Valid before OE  20 — — ns (data setup time) 163 ToeH2adl OE  to Data In Invalid (data hold time) 0 — — ns 164 TalH2alL ALE Pulse Width — TCY — ns 165 ToeL2oeH OE Pulse Width 0.5 TCY – 5 0.5 TCY — ns 166 TalH2alH ALE  to ALE  (cycle time) — 0.25 TCY — ns 167 Tacc Address Valid to Data Valid 0.75 TCY – 25 — — ns 168 Toe OE  to Data Valid — 0.5 TCY – 25 ns 169 TalL2oeH ALE to OE  0.625 TCY – 10 — 0.625 TCY + 10 ns 171 TalH2csL Chip Enable Active to ALE  0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns DS39762F-page 448  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 28-7: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 166 AD<15:0> Address Data Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157 157A UB or LB Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C, unless otherwise stated. TABLE 28-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE (address setup time) 0.25 TCY – 10 — — ns 151 TalL2adl ALE  to Address Out Invalid (address hold time) 5 — — ns 153 TwrH2adl WRn  to Data Out Invalid (data hold time) 5 — — ns 154 TwrL WRn Pulse Width 0.5 TCY – 5 0.5 TCY — ns 156 TadV2wrH Data Valid before WRn (data setup time) 0.5 TCY – 10 — — ns 157 TbsV2wrL Byte Select Valid before WRn  0.25 TCY — — ns (byte select setup time) 157A TwrH2bsI WRn  to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 — — ns 166 TalH2alH ALE  to ALE  (cycle time) — 0.25 TCY — ns 171 TalH2csL Chip Enable Active to ALE  0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns  2011 Microchip Technology Inc. DS39762F-page 449

PIC18F97J60 FAMILY FIGURE 28-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure28-3 for load conditions. TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDT Watchdog Timer Time-out Period 2.8 4.1 5.4 ms (no postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 46.2 66 85.8 ms 34 TIOZ I/O High-Impedance from MCLR — — 3TCY + 2 s System clock available Low or Watchdog Timer Reset — — 415 s System clock unavailable (Sleep mode or primary oscillator off) 38 TCSD CPU Start-up Time — 200 — s DS39762F-page 450  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 28-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure28-3 for load conditions. TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 TT1H T13CKI High Synchronous, no prescaler 0.5 TCY + 20 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 46 TT1L T13CKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 47 TT1P T13CKI Input Synchronous Greater of: — ns N = prescale Period 20ns or value (TCY + 40)/N (1, 2, 4, 8) Asynchronous 60 — ns FT1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 TCKE2TMRI Delay from External T13CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment  2011 Microchip Technology Inc. DS39762F-page 451

PIC18F97J60 FAMILY FIGURE 28-10: CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCPx MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure28-3 for load conditions. TABLE 28-14: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCPx MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With prescaler 10 — ns 51 TCCH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With prescaler 10 — ns 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TCCR CCPx Output Fall Time — 25 ns 54 TCCF CCPx Output Fall Time — 25 ns TABLE 28-15: PARALLEL SLAVE PORT REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 62 TdtV2wrH Data In Valid before WR  or CS  (setup time) 20 — ns 63 TwrH2dtI WR  or CS  to Data–In Invalid (hold time) 20 — ns 64 TrdL2dtV RD  and CS  to Data–Out Valid — 80 ns 65 TrdH2dtI RD  or CS  to Data–Out Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being Cleared from — 3 TCY WR  or CS  DS39762F-page 452  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 28-11: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SCKx (CKP = 0) 78 79 SCKx (CKP = 1) 79 78 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure28-3 for load conditions. TABLE 28-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 100 — ns TDIV2SCL 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 100 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time — 25 ns 79 TSCF SCKx Output Fall Time — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV  2011 Microchip Technology Inc. DS39762F-page 453

PIC18F97J60 FAMILY FIGURE 28-12: EXAMPLE SPI MASTER MODE TIMING (CKE=1) 81 SCKx (CKP = 0) 79 73 SCKx (CKP = 1) 80 78 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure28-3 for load conditions. TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 100 — ns TDIV2SCL 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 100 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time — 25 ns 79 TSCF SCKx Output Fall Time — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TCY — ns TDOV2SCL DS39762F-page 454  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 28-13: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SSx 70 SCKx (CKP = 0) 83 71 72 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure28-3 for load conditions. TABLE 28-18: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx  to SCKx  or SCKx  Input TCY — ns TSSL2SCL 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 100 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 100 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx  to SDOx Output High-impedance 10 50 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 83 TSCH2SSH, SSx  after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used.  2011 Microchip Technology Inc. DS39762F-page 455

PIC18F97J60 FAMILY FIGURE 28-14: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SSx 70 SCKx 83 (CKP = 0) 71 72 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure28-3 for load conditions. TABLE 28-19: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx  to SCKx  or SCKx  Input TCY — ns TSSL2SCL 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 100 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx  to SDOx Output High-Impedance 10 50 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 82 TSSL2DOV SDOx Data Output Valid after SSx  Edge — 50 ns 83 TSCH2SSH, SSx  after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39762F-page 456  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 28-15: I2C™ BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure28-3 for load conditions. TABLE 28-20: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 28-16: I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure28-3 for load conditions.  2011 Microchip Technology Inc. DS39762F-page 457

PIC18F97J60 FAMILY TABLE 28-21: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s PIC18F97J60 family must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s PIC18F97J60 family must operate at a minimum of 10 MHz MSSP module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — s PIC18F97J60 family must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s PIC18F97J60 family must operate at a minimum of 10 MHz MSSP module 1.5 TCY — 102 TR SDAx and SCLx Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDAx and SCLx Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup 100 kHz mode 4.7 — s Only relevant for Repeated Time 400 kHz mode 0.6 — s Start condition 91 THD:STA Start Condition Hold 100 kHz mode 4.0 — s After this period, the first Time 400 kHz mode 0.6 — s clock pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup 100 kHz mode 4.7 — s Time 400 kHz mode 0.6 — s 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS39762F-page 458  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 28-17: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure28-3 for load conditions. TABLE 28-22: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. FIGURE 28-18: MASTER SSP I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 91 107 92 SDAx In 109 109 110 SDAx Out Note: Refer to Figure28-3 for load conditions.  2011 Microchip Technology Inc. DS39762F-page 459

PIC18F97J60 FAMILY TABLE 28-23: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 1 MHz mode(1) TBD — ns 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) TBD — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free 400 kHz mode 1.3 — ms before a new transmission can start 1 MHz mode(1) TBD — ms D102 CB Bus Capacitive Loading — 400 pF Legend: TBD = To Be Determined Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but Parameter #107250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, Parameter #102 + Parameter #107=1000+250=1250ns (for 100 kHz mode), before the SCLx line is released. DS39762F-page 460  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY FIGURE 28-19: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 122 Note: Refer to Figure28-3 for load conditions. TABLE 28-24: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid — 40 ns 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns 122 TDTRF Data Out Rise Time and Fall Time — 20 ns FIGURE 28-20: EUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TXx/CKx pin 125 RXx/DTx pin 126 Note: Refer to Figure28-3 for load conditions. TABLE 28-25: EUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CKx  (DTx hold time) 10 — ns 126 TCKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns  2011 Microchip Technology Inc. DS39762F-page 461

PIC18F97J60 FAMILY TABLE 28-26: A/D CONVERTER CHARACTERISTICS: PIC18F97J60 FAMILY (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit VREF  2.0V A03 EIL Integral Linearity Error — — <±1 LSb VREF  2.0V A04 EDL Differential Linearity Error — — <±1 LSb VREF  2.0V A06 EOFF Offset Error — — <±3 LSb VREF  2.0V A07 EGN Gain Error — — <±3 LSb VREF  2.0V A10 — Monotonicity Guaranteed(1) — VSS VAIN VREF A20 VREF Reference Voltage Range 1.8 — — V VDD  3.0V (VREFH – VREFL) 3 — — V VDD  3.0V VREFSUM Reference Voltage Sum — — AVDD + 0.5 V (VREFH + VREFL) A21 VREFH Reference Voltage High VREFL — AVDD V A22 VREFL Reference Voltage Low AVSS — VREFH V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 2.5 k Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 A During VAIN acquisition. — — 1000 A During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source. FIGURE 28-21: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK(1) 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. DS39762F-page 462  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY TABLE 28-27: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period 0.7 25.0(1) s TOSC based, VREF  2.0V TBD 1 s A/D RC mode 131 TCNV Conversion Time 11 12 TAD (not including acquisition time) (Note 2) 132 TACQ Acquisition Time (Note 3) 1.4 — s -40C to +85C 135 TSWC Switching Time from Convert  Sample — (Note 4) TBD TDIS Discharge Time 0.2 — s Legend: TBD = To Be Determined Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. 4: On the following cycle of the device clock. 28.5 Ethernet Specifications and Requirements TABLE 28-28: REQUIREMENTS FOR ETHERNET TRANSCEIVER EXTERNAL MAGNETICS Parameter Min Norm Max Units Conditions RX Turns Ratio — 1:1 — — TX Turns Ratio — 1:1 — — Transformer Center Tap = 3.3V Insertion Loss — — -1.1 dB Primary Inductance 350 — — H 8mA bias Transformer Isolation 1.5 — — kVrms Required to meet IEEE 802.3™ requirements Differential to Common-Mode 40 — — dB 0.1 to 10MHz Rejection Return Loss -16 — — dB  2011 Microchip Technology Inc. DS39762F-page 463

PIC18F97J60 FAMILY NOTES: DS39762F-page 464  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX 18F67J60- XXXXXXXXXX I/PTe3 XXXXXXXXXX 1110017 YYWWNNN 80-Lead TQFP Example XXXXXXXXXXXX PIC18F87J60- XXXXXXXXXXXX I/PTe3 YYWWNNN 1110017 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX PIC18F97J60- XXXXXXXXXXXX I/PTe3 YYWWNNN 1110017 100-Lead TQFP (14x14x1 mm) Example XXXXXXXXXXXX PIC18F97J60- XXXXXXXXXXXX I/PFe3 YYWWNNN 1110017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011 Microchip Technology Inc. DS39762F-page 465

PIC18F97J60 FAMILY 29.2 Package Details The following sections give the technical details of the packages. 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(cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)@/1 DS39762F-page 466  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:27)(cid:28)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)  2011 Microchip Technology Inc. DS39762F-page 467

PIC18F97J60 FAMILY )(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 E e E1 b N NOTE1 123 NOTE2 α A c φ β A1 A2 L L1 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 @(cid:4) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)/(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)(cid:6)(cid:17)1 DS39762F-page 468  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY )(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)  2011 Microchip Technology Inc. DS39762F-page 469

PIC18F97J60 FAMILY (cid:27)(cid:28)(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 e E E1 N b NOTE1 123 NOTE2 α c A φ A1 β L L1 A2 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 (cid:15)(cid:4)(cid:4) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)(cid:5)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:16) (cid:4)(cid:30)(cid:15)@ (cid:4)(cid:30)(cid:17)(cid:16) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:15)(cid:4)(cid:4)1 DS39762F-page 470  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY (cid:27)(cid:28)(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)  2011 Microchip Technology Inc. DS39762F-page 471

PIC18F97J60 FAMILY (cid:27)(cid:28)(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:21)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:3)(cid:29)(cid:27)(cid:3)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 e E1 E b N α NOTE1 123 NOTE2 A c φ A2 β L A1 L1 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 (cid:15)(cid:4)(cid:4) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)/(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15);(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15);(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:15)(cid:15)(cid:4)1 DS39762F-page 472  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY (cid:27)(cid:28)(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:21)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:3)(cid:29)(cid:27)(cid:3)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)  2011 Microchip Technology Inc. DS39762F-page 473

PIC18F97J60 FAMILY NOTES: DS39762F-page 474  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY APPENDIX A: REVISION HISTORY Revision A (March 2006) Original data sheet for the PIC18F97J60 family of devices. Revision B (October 2006) First revision. Includes preliminary electrical specifica- tions; revised and updated material on the Ethernet module; updated material on Reset integration; and updates to the device memory map. Revision C (June 2007) Corrected Table 10.2: Input Voltage Levels; added con- tent on Ethernet module’s reading and writing to the buffer; added new, 100-lead PT 12x12x1 mm TQFP package to “Package Marking Information” and “Pack- age Details” sections; updated other package details drawings; changed Product Identification System examples. Revision D (January 2008) Added one line to “Ethernet Features” description. Added land pattern schematics for each package. Revision E (October 2009) Updated to remove Preliminary status. Revision F (April 2011) Added Brown-out Reset (BOR) specs, added Ethernet RX Auto-Polarity circuit section, added EMI filter section, added Section2.0 “Guidelines for Getting Started with PIC18FJ Microcontrollers”, changed the opcode encoding of the PUSHL instruction to 1110 1010 kkk kkkk and changed the 2 TOSC Maximum Device Frequency in Table22-1 from 2.68MHz to the correct value of 2.86 MHz. Updated comparator input offset voltage maximum to the correct value of 25 mV.  2011 Microchip Technology Inc. DS39762F-page 475

PIC18F97J60 FAMILY APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in TableB-1. TABLE B-1: DEVICE DIFFERENCES BETWEEN PIC18F97J60 FAMILY MEMBERS 0 5 0 0 5 0 0 5 0 6 6 6 6 6 6 6 6 6 J J J J J J J J J 6 6 7 6 6 7 6 6 7 6 6 6 8 8 8 9 9 9 Features F F F F F F F F F 8 8 8 8 8 8 8 8 8 1 1 1 1 1 1 1 1 1 C C C C C C C C C PI PI PI PI PI PI PI PI PI Program Memory (Bytes) 64K 96K 128K 64K 96K 128K 64K 96K 128K Program Memory 32764 49148 65532 32764 49148 65532 32764 49148 65532 (Instructions) Interrupt Sources 26 27 29 I/O Ports (Pins) Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G, H, J Ports A, B, C, D, E, F, G, H, J (39) (55) (70) Enhanced USART Modules 1 2 MSSP Modules 1 2 Parallel Slave Port No Yes Communications (PSP) External Memory Bus No Yes 10-Bit Analog-to-Digital 11 input channels 15 input channels 16 input channels Module Packages 64-pin TQFP 80-pin TQFP 100-pin TQFP DS39762F-page 476  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY INDEX Analog Input Model ..................................................343 Baud Rate Generator ..............................................300 A Capture Mode Operation .........................................191 Comparator Analog Input Model ..............................353 A/D ...................................................................................339 Comparator I/O Operating Modes ...........................350 Acquisition Requirements ........................................344 Comparator Output ..................................................352 ADCAL Bit ................................................................347 Comparator Voltage Reference ...............................356 ADCON0 Register ....................................................339 Comparator Voltage Reference Output ADCON1 Register ....................................................339 Buffer Example ................................................357 ADCON2 Register ....................................................339 Compare Mode Operation .......................................192 ADRESH Register ............................................339, 342 Connections for On-Chip Voltage Regulator ...........369 ADRESL Register ....................................................339 Crystal Oscillator Operation (HS, HSPLL) .................50 Analog Port Pins, Configuring ..................................345 Device Clock ..............................................................49 Associated Registers ...............................................347 Enhanced PWM .......................................................203 Automatic Acquisition Time, Selecting and Ethernet Interrupt Logic ...........................................239 Configuring ......................................................345 Ethernet Module ......................................................217 Configuring the Module ............................................343 EUSARTx Receive ..................................................329 Conversion Clock (TAD) ...........................................345 EUSARTx Transmit .................................................326 Conversion Requirements .......................................463 External Clock Input Operation (EC) .........................50 Conversion Status (GO/DONE Bit) ..........................342 External Clock Input Operation (HS) .........................50 Conversions .............................................................346 External Power-on Reset Circuit (Slow Converter Calibration ...............................................347 Converter Characteristics ........................................462 VDD Power-up) ..................................................65 Fail-Safe Clock Monitor ...........................................371 Converter Interrupt, Configuring ..............................343 Full-Bridge Application Example ..............................209 Operation in Power-Managed Modes ......................347 Generic I/O Port Operation ......................................145 Special Event Trigger (ECCP) .........................202, 346 Half-Bridge Output Mode Applications ....................207 Use of the ECCP2 Trigger .......................................346 Interrupt Logic ..........................................................130 Absolute Maximum Ratings .............................................429 MSSP (I2C Master Mode) ........................................298 AC (Timing) Characteristics .............................................443 MSSP (I2C Mode) ....................................................279 Load Conditions for Device Timing MSSP (SPI Mode) ...................................................269 Specifications ...................................................444 On-Chip Reset Circuit ................................................63 Parameter Symbology .............................................443 PIC18F66J60/66J65/67J60 .......................................15 Temperature and Voltage Specifications .................444 PIC18F86J60/86J65/87J60 .......................................16 Timing Conditions ....................................................444 PIC18F96J60/96J65/97J60 .......................................17 ACKSTAT ........................................................................304 PORTD and PORTE (Parallel Slave Port) ...............168 ACKSTAT Status Flag .....................................................304 PWM Operation (Simplified) ....................................194 ADCAL Bit ........................................................................347 Reads from Flash Program Memory .......................109 ADCON0 Register ............................................................339 Required External Components for Ethernet ...........219 GO/DONE Bit ...........................................................342 RX Polarity Correction Circuit (TX not Shown) ........221 ADCON1 Register ............................................................339 Single Comparator ...................................................351 ADCON2 Register ............................................................339 Table Read Operation .............................................105 ADDFSR ..........................................................................418 Table Write Operation .............................................106 ADDLW ............................................................................381 Table Writes to Flash Program Memory ..................111 ADDULNK ........................................................................418 Timer0 in 16-Bit Mode .............................................172 ADDWF ............................................................................381 Timer0 in 8-Bit Mode ...............................................172 ADDWFC .........................................................................382 Timer1 .....................................................................176 ADRESH Register ............................................................339 Timer1 (16-Bit Read/Write Mode) ............................176 ADRESL Register ....................................................339, 342 Timer2 .....................................................................181 Analog-to-Digital Converter. See A/D. Timer3 .....................................................................184 ANDLW ............................................................................382 Timer3 (16-Bit Read/Write Mode) ............................184 ANDWF ............................................................................383 Timer4 .....................................................................188 Assembler Watchdog Timer ......................................................367 MPASM Assembler ..................................................426 BN ....................................................................................384 B BNC .................................................................................385 Baud Rate Generator .......................................................300 BNN .................................................................................385 BC ....................................................................................383 BNOV ..............................................................................386 BCF ..................................................................................384 BNZ .................................................................................386 BF ....................................................................................304 BOR. See Brown-out Reset. BF Status Flag .................................................................304 BOV .................................................................................389 Block Diagrams BRA .................................................................................387 16-Bit Byte Select Mode ..........................................121 BRG. See Baud Rate Generator. 16-Bit Byte Write Mode ............................................119 Brown-out Reset (BOR) .....................................................65 16-Bit Word Write Mode ...........................................120 and On-Chip Voltage Regulator ..............................369 8-Bit Multiplexed Mode ............................................123 Detecting ...................................................................65 A/D ...........................................................................342  2011 Microchip Technology Inc. DS39762F-page 477

PIC18F97J60 FAMILY BSF ..................................................................................387 Comparator ......................................................................349 BTFSC .............................................................................388 Analog Input Connection Considerations ................353 BTFSS ..............................................................................388 Associated Registers ...............................................353 BTG ..................................................................................389 Configuration ...........................................................350 BZ .....................................................................................390 Effects of a Reset ....................................................352 Interrupts .................................................................352 C Operation .................................................................351 C Compilers Operation During Sleep ...........................................352 MPLAB C18 .............................................................426 Outputs ....................................................................351 CALL ................................................................................390 Reference ................................................................351 CALLW .............................................................................419 External Signal ................................................351 Capture (CCP Module) .....................................................191 Internal Signal ..................................................351 Associated Registers ...............................................193 Response Time ........................................................351 CCPRxH:CCPRxL Registers ...................................191 Comparator Specifications ...............................................442 CCPx Pin Configuration ...........................................191 Comparator Voltage Reference .......................................355 Prescaler ..................................................................191 Accuracy and Error ..................................................356 Software Interrupt ....................................................191 Associated Registers ...............................................357 Timer1/Timer3 Mode Selection ................................191 Configuring ..............................................................355 Capture (ECCP Module) ..................................................202 Connection Considerations ......................................356 Capture/Compare/PWM (CCP) ........................................189 Effects of a Reset ....................................................356 Capture Mode. See Capture. Operation During Sleep ...........................................356 CCPRxH Register ....................................................190 Compare (CCP Module) ..................................................192 CCPRxL Register .....................................................190 Associated Registers ...............................................193 CCPx/ECCPx Interconnect Configurations ..............190 CCPRx Register ......................................................192 CCPx/ECCPx Mode and Timer Resources .............190 CCPx Pin Configuration ...........................................192 Compare Mode. See Compare. Software Interrupt Mode ..........................................192 Module Configuration ...............................................190 Timer1/Timer3 Mode Selection ................................192 Clock Sources Compare (ECCP Module) ................................................202 Default System Clock on Reset .................................54 Special Event Trigger ......................................202, 346 Effects of Power-Managed Modes .............................54 Computed GOTO ...............................................................83 Oscillator Switching ....................................................52 Configuration Bits ............................................................359 CLRF ................................................................................391 Configuration Mismatch (CM) Reset ..................................65 CLRWDT ..........................................................................391 Configuration Register Protection ....................................373 Code Examples Core Features 16 x 16 Signed Multiply Routine ..............................128 Easy Migration ...........................................................11 16 x 16 Unsigned Multiply Routine ..........................128 Expanded Memory .....................................................11 8 x 8 Signed Multiply Routine ..................................127 Extended Instruction Set ...........................................11 8 x 8 Unsigned Multiply Routine ..............................127 External Memory Bus ................................................11 Changing Between Capture Prescalers ...................191 Oscillator Options ......................................................11 Computed GOTO Using an Offset Value ...................83 CPFSEQ ..........................................................................392 Erasing a Flash Program Memory Row ...................110 CPFSGT ..........................................................................393 Fast Register Stack ....................................................83 CPFSLT ...........................................................................393 How to Clear RAM (Bank 1) Using Indirect Crystal Oscillator/Ceramic Resonators (HS Modes) ..........50 Addressing .........................................................98 Customer Change Notification Service ............................488 Implementing a Real-Time Clock Using a Customer Notification Service .........................................488 Timer1 Interrupt Service ..................................179 Customer Support ............................................................488 Initializing PORTA ....................................................146 D Initializing PORTB ....................................................148 Initializing PORTC ....................................................151 Data Addressing Modes ....................................................98 Initializing PORTD ....................................................154 Comparing Addressing Modes with the Initializing PORTE ....................................................157 Extended Instruction Set Enabled ...................102 Initializing PORTF ....................................................160 Direct .........................................................................98 Initializing PORTG ...................................................162 Indexed Literal Offset ..............................................101 Initializing PORTH ....................................................164 Affected Instructions ........................................101 Initializing PORTJ ....................................................166 BSR .................................................................103 Loading the SSP1BUF (SSP1SR) Register .............272 Mapping Access Bank .....................................103 Reading a Flash Program Memory Word ................109 Indirect .......................................................................98 Saving STATUS, WREG and BSR Inherent and Literal ....................................................98 Registers in RAM .............................................144 Data Memory .....................................................................86 Writing to Flash Program Memory ...........................112 Access Bank ..............................................................88 Code Protection ...............................................................359 Bank Select Register (BSR) ......................................86 COMF ...............................................................................392 Ethernet SFRs ...........................................................90 Extended Instruction Set .........................................100 General Purpose Register File ..................................88 DS39762F-page 478  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY Memory Maps Ethernet Module ..............................................................217 Ethernet Special Function Registers .................90 Associated Registers, Direct Memory Access PIC18F97J60 Family .........................................87 Controller .........................................................266 Special Function Registers ................................89 Associated Registers, Flow Control .........................258 Special Function Registers ........................................89 Associated Registers, Reception .............................255 DAW .................................................................................394 Associated Registers, Transmission .......................255 DC Characteristics ...........................................................439 Automatic RX Polarity Detection, Correction ...........220 Power-Down and Supply Current ............................432 Buffer and Buffer Pointers .......................................223 Supply Voltage .........................................................431 Buffer Arbiter ...................................................226 DCFSNZ ..........................................................................395 DMA Access ....................................................226 DECF ...............................................................................394 Receive Buffer .................................................225 DECFSZ ...........................................................................395 Transmit Buffer ................................................226 Default System Clock .........................................................54 Buffer and Register Spaces .....................................222 Development Support ......................................................425 Buffer Organization ..................................................224 Device Differences ...........................................................476 CRC .........................................................................248 Device Overview ................................................................11 Direct Memory Access (DMA) Controller .................265 Details on Individual Family Members .......................12 Direct Memory Access Controller Features (100-Pin Devices) .......................................14 Checksum Calculations ...................................266 Features (64-Pin Devices) .........................................13 Copying Memory .............................................265 Features (80-Pin Devices) .........................................13 Disabling ..................................................................246 Direct Addressing ...............................................................99 Duplex Mode Configuration and Negotiation ...........256 EMI Emissions Considerations ................................220 E Ethernet and Microcontroller Memory ECCP2 Relationship .....................................................222 Pin Assignment ........................................................190 Ethernet Control Registers ......................................227 Effect on Standard PIC Instructions .................................422 Flow Control ............................................................257 Electrical Characteristics ..................................................429 Initializing .................................................................245 Requirements for Ethernet Transceiver Interrupts .................................................................239 External Magnetics ..........................................463 Interrupts and Wake-on-LAN ...................................244 Enhanced Capture/Compare/PWM (ECCP) ....................197 LED Configuration ...................................................218 Capture and Compare Modes ..................................202 MAC and MII Registers ...........................................229 Capture Mode. See Capture (ECCP Module). MAC Initialization Settings .......................................245 ECCP1/ECCP3 Outputs and Program Magnetics, Termination and Other External Memory Mode ..................................................199 Components ....................................................219 ECCP2 Outputs and Program Memory Modes ........199 Memory Maps ..........................................................234 Enhanced PWM Mode .............................................203 Oscillator Requirements ..........................................218 Outputs and Configuration .......................................199 Packet Format .........................................................247 Pin Configurations for ECCP1 .................................200 Per-Packet Control Bytes ........................................249 Pin Configurations for ECCP2 .................................200 PHSTAT Registers ..................................................232 Pin Configurations for ECCP3 .................................201 PHY Initialization Settings .......................................246 PWM Mode. See PWM (ECCP Module). PHY Registers .........................................................232 Standard PWM Mode ...............................................202 PHY Start-up Timer .................................................218 Timer Resources ......................................................199 Reading from a PHY Register .................................233 Use of CCP4/CCP5 with ECCP1/ECCP3 ................199 Receive Filters .........................................................259 Enhanced Capture/Compare/PWM (ECCPx) Broadcast ........................................................259 Associated Registers ...............................................215 Hash Table ......................................................259 Enhanced Universal Synchronous Asynchronous Magic Packet ...................................................259 Receiver Transmitter (EUSART). See EUSART. Multicast ..........................................................259 ENVREG pin ....................................................................369 Pattern Match ..................................................259 Equations Unicast ............................................................259 16 x 16 Signed Multiplication Algorithm ...................128 Resets .....................................................................267 16 x 16 Unsigned Multiplication Algorithm ...............128 Microcontroller Reset .......................................267 A/D Acquisition Time ................................................344 Receive Only ...................................................267 A/D Minimum Charging Time ...................................344 Transmit Only ..................................................267 Calculating Baud Rate Error ....................................320 Signal and Power Interfaces ....................................218 Calculating the A/D Minimum Required Special Function Registers (SFRs) .........................227 Acquisition Time ..............................................344 Random Access Address Calculation ......................253 Receive Buffer Free Space Calculation ...................254 Errata ...................................................................................9  2011 Microchip Technology Inc. DS39762F-page 479

PIC18F97J60 FAMILY Transmitting and Receiving Data .............................247 Extended Microcontroller .................................118 Packet Field Definitions ...........................247–248 Microcontroller .................................................118 Reading Received Packets ..............................253 Wait States ..............................................................118 Receive Buffer Space ......................................254 Weak Pull-ups on Port Pins .....................................118 Receive Packet Layout ....................................252 F Receive Status Vectors ....................................253 Receiving Packets ...........................................252 Fail-Safe Clock Monitor ...........................................359, 371 Transmit Packet Layout ...................................250 and the Watchdog Timer .........................................371 Transmit Status Vectors ...................................251 Exiting Operation .....................................................371 Transmitting Packets .......................................249 Interrupts in Power-Managed Modes .......................372 Ethernet Operation, Microcontroller Clock .........................51 POR or Wake-up From Sleep ..................................372 EUSARTx Fast Register Stack ...........................................................83 Asynchronous Mode ................................................325 Firmware Instructions ......................................................375 Associated Registers, Receive ........................329 Flash Configuration Words ........................................78, 359 Associated Registers, Transmit .......................327 Flash Program Memory ...................................................105 Auto-Wake-up on Sync Break Character .........330 Associated Registers ...............................................113 Break Character Sequence ..............................332 Control Registers .....................................................106 Receiving .................................................332 EECON1 and EECON2 ...................................106 Receiver ...........................................................328 TABLAT (Table Latch) .....................................108 Setting Up 9-Bit Mode with Address Detect .....328 TBLPTR (Table Pointer) ..................................108 Transmitter .......................................................325 Erase Sequence ......................................................110 Baud Rate Generator Erasing ....................................................................110 Operation in Power-Managed Modes ..............319 Operation During Code-Protect ...............................113 Baud Rate Generator (BRG) ....................................319 Reading ...................................................................109 Associated Registers .......................................320 Table Pointer Auto-Baud Rate Detect ....................................323 Boundaries Based on Operation .....................108 Baud Rates, Asynchronous Modes ..................321 Table Pointer Boundaries ........................................108 High Baud Rate Select (BRGH Bit) ..................319 Table Reads and Table Writes ................................105 Sampling ..........................................................319 Write Sequence .......................................................111 Synchronous Master Mode ......................................333 Writing .....................................................................111 Associated Registers, Receive ........................336 Protection Against Spurious Writes .................113 Associated Registers, Transmit .......................334 Unexpected Termination .................................113 Reception .........................................................335 Write Verify ......................................................113 Transmission ....................................................333 FSCM. See Fail-Safe Clock Monitor. Synchronous Slave Mode ........................................337 G Associated Registers, Receive ........................338 Associated Registers, Transmit .......................337 GOTO ..............................................................................396 Reception .........................................................338 H Transmission ....................................................337 Hardware Multiplier ..........................................................127 Extended Instruction Set Introduction ..............................................................127 ADDFSR ..................................................................418 Operation .................................................................127 ADDULNK ................................................................418 Performance Comparison ........................................127 CALLW .....................................................................419 MOVSF ....................................................................419 I MOVSS ....................................................................420 I/O Ports ...........................................................................145 PUSHL .....................................................................420 Pin Capabilities ........................................................145 SUBFSR ..................................................................421 I2C Mode (MSSP) ............................................................279 SUBULNK ................................................................421 Acknowledge Sequence Timing ..............................307 External Clock Input (EC Modes) .......................................50 Associated Registers ...............................................313 External Memory Bus .......................................................115 Baud Rate Generator ..............................................300 16-Bit Byte Select Mode ..........................................121 Bus Collision 16-Bit Byte Write Mode ............................................119 During a Repeated Start Condition ..................311 16-Bit Data Width Modes .........................................118 During a Start Condition ..................................309 16-Bit Mode Timing ..................................................122 During a Stop Condition ..................................312 16-Bit Word Write Mode ...........................................120 Clock Arbitration ......................................................301 21-Bit Addressing .....................................................117 Clock Rate w/BRG ...................................................300 8-Bit Data Width Mode .............................................123 Clock Stretching .......................................................293 8-Bit Mode Timing ....................................................124 10-Bit Slave Receive Mode (SEN = 1) ............293 Address and Data Line Usage (table) ......................117 10-Bit Slave Transmit Mode ............................293 Address and Data Width ..........................................117 7-Bit Slave Receive Mode (SEN = 1) ..............293 Address Shifting .......................................................117 7-Bit Slave Transmit Mode ..............................293 Control .....................................................................116 Clock Synchronization and the CKP Bit ...................294 I/O Port Functions ....................................................115 Effects of a Reset ....................................................308 Operation in Power-Managed Modes ......................125 General Call Address Support .................................297 Program Memory Modes .........................................118 DS39762F-page 480  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY Master Mode ............................................................298 DECF .......................................................................394 Baud Rate Generator .......................................300 DECFSZ ..................................................................395 Operation .........................................................299 Extended Instructions ..............................................417 Reception .........................................................304 Considerations when Enabling ........................422 Repeated Start Condition Timing .....................303 Syntax .............................................................417 Start Condition Timing .....................................302 Use with MPLAB IDE Tools .............................424 Transmission ...................................................304 General Format .......................................................377 Multi-Master Communication, Bus Collision GOTO ......................................................................396 and Arbitration .................................................308 INCF ........................................................................396 Multi-Master Mode ...................................................308 INCFSZ ....................................................................397 Operation .................................................................284 INFSNZ ....................................................................397 Read/Write Bit Information (R/W Bit) ...............284, 286 IORLW .....................................................................398 Registers ..................................................................279 IORWF .....................................................................398 Serial Clock (SCKx/SCLx) .......................................286 LFSR .......................................................................399 Slave Mode ..............................................................284 MOVF ......................................................................399 Address Masking .............................................285 MOVFF ....................................................................400 Addressing .......................................................284 MOVLB ....................................................................400 Reception .........................................................286 MOVLW ...................................................................401 Transmission ...................................................286 MOVWF ...................................................................401 Sleep Operation .......................................................308 MULLW ....................................................................402 Stop Condition Timing ..............................................307 MULWF ...................................................................402 INCF .................................................................................396 NEGF .......................................................................403 INCFSZ ............................................................................397 NOP .........................................................................403 In-Circuit Debugger ..........................................................373 POP .........................................................................404 In-Circuit Serial Programming (ICSP) ......................359, 373 PUSH .......................................................................404 Indexed Literal Offset Addressing RCALL .....................................................................405 and Standard PIC18 Instructions .............................422 RESET .....................................................................405 Indexed Literal Offset Mode .............................................422 RETFIE ....................................................................406 Indirect Addressing ............................................................99 RETLW ....................................................................406 INFSNZ ............................................................................397 RETURN ..................................................................407 Initialization Conditions for All Registers ......................69–75 RLCF .......................................................................407 Instruction Cycle ................................................................84 RLNCF .....................................................................408 Clocking Scheme .......................................................84 RRCF .......................................................................408 Flow/Pipelining ...........................................................84 RRNCF ....................................................................409 Instruction Set ..................................................................375 SETF .......................................................................409 ADDLW ....................................................................381 SETF (Indexed Literal Offset Mode) ........................423 ADDWF ....................................................................381 SLEEP .....................................................................410 ADDWF (Indexed Literal Offset Mode) ....................423 Standard Instructions ...............................................375 ADDWFC .................................................................382 SUBFWB .................................................................410 ANDLW ....................................................................382 SUBLW ....................................................................411 ANDWF ....................................................................383 SUBWF ....................................................................411 BC ............................................................................383 SUBWFB .................................................................412 BCF ..........................................................................384 SWAPF ....................................................................412 BN ............................................................................384 TBLRD .....................................................................413 BNC .........................................................................385 TBLWT ....................................................................414 BNN .........................................................................385 TSTFSZ ...................................................................415 BNOV .......................................................................386 XORLW ...................................................................415 BNZ ..........................................................................386 XORWF ...................................................................416 BOV .........................................................................389 INTCON Register BRA ..........................................................................387 RBIF Bit ...................................................................148 BSF ..........................................................................387 INTCON Registers ...........................................................131 BSF (Indexed Literal Offset Mode) ..........................423 Inter-Integrated Circuit. See I2C Mode. BTFSC .....................................................................388 Internal Oscillator Block .....................................................51 BTFSS .....................................................................388 Internal RC Oscillator BTG ..........................................................................389 Use with WDT ..........................................................367 BZ ............................................................................390 Internal Voltage Regulator Specifications ........................442 CALL ........................................................................390 Internet Address ..............................................................488 CLRF ........................................................................391 CLRWDT ..................................................................391 COMF ......................................................................392 CPFSEQ ..................................................................392 CPFSGT ..................................................................393 CPFSLT ...................................................................393 DAW .........................................................................394 DCFSNZ ..................................................................395  2011 Microchip Technology Inc. DS39762F-page 481

PIC18F97J60 FAMILY Interrupt Sources ..............................................................359 Oscillator Configuration .....................................................49 Interrupt-on-Change (RB7:RB4) ..............................148 EC ..............................................................................49 INTx Pin ...................................................................144 ECPLL .......................................................................49 PORTB, Interrupt-on-Change ..................................144 HS ..............................................................................49 TMR0 .......................................................................144 HSPLL .......................................................................49 TMR0 Overflow ........................................................173 Internal Oscillator Block .............................................51 TMR1 Overflow ........................................................175 INTRC ........................................................................49 TMR2 to PR2 Match (PWM) ....................................203 Oscillator Selection ..........................................................359 TMR3 Overflow ................................................183, 185 Oscillator Start-up Timer (OST) .........................................54 TMR4 to PR4 Match ................................................188 Oscillator Transitions .........................................................54 TMR4 to PR4 Match (PWM) ....................................187 Oscillator, Timer1 .....................................................175, 185 Interrupts ..........................................................................129 Oscillator, Timer3 .............................................................183 Context Saving .........................................................144 OUI. See Organizationally Unique Identifier. Interrupts, Flag Bits P Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) .........................................................148 Packaging ........................................................................465 INTRC. See Internal Oscillator Block. Details ......................................................................466 IORLW .............................................................................398 Marking ....................................................................465 IORWF .............................................................................398 Parallel Slave Port (PSP) .................................................168 IPR Registers ...................................................................140 Associated Registers ...............................................170 PORTD ....................................................................168 L Select (PSPMODE Bit) ............................................168 LFSR ................................................................................399 PIE Registers ...................................................................137 Pin Functions M AVDD ..............................................................32, 42, 24 Master Clear (MCLR) .........................................................65 AVSS ..............................................................42, 32, 24 Master Synchronous Serial Port (MSSP). See MSSP. ENVREG .......................................................24, 32, 42 Memory Organization .........................................................77 MCLR ............................................................25, 33, 18 Data Memory .............................................................86 OSC1/CLKI ....................................................18, 25, 33 Program Memory .......................................................77 OSC2/CLKO ..................................................18, 25, 33 Memory Programming Requirements ..............................441 RA0/LEDA/AN0 .............................................18, 25, 33 Microchip Internet Web Site .............................................488 RA1/LEDB/AN1 .............................................18, 25, 33 MOVF ...............................................................................399 RA2/AN2/VREF- .............................................18, 25, 33 MOVFF .............................................................................400 RA3/AN3/VREF+ ............................................18, 25, 33 MOVLB .............................................................................400 RA4/T0CKI ....................................................18, 25, 33 MOVLW ............................................................................401 RA5/AN4 ........................................................18, 25, 33 MOVSF ............................................................................419 RB0/INT0/FLT0 ..............................................19, 26, 34 MOVSS ............................................................................420 RB1/INT1 .......................................................19, 26, 34 MOVWF ...........................................................................401 RB2/INT2 .......................................................19, 26, 34 MPLAB ASM30 Assembler, Linker, Librarian ..................426 RB3/INT3 .............................................................19, 26 MPLAB Integrated Development Environment RB3/INT3/ECCP2/P2A ..............................................34 Software ...................................................................425 RB4/KBI0 .......................................................19, 26, 34 MPLAB PM3 Device Programmer ....................................428 RB5/KBI1 .......................................................19, 26, 34 MPLAB REAL ICE In-Circuit Emulator System ................427 RB6/KBI2/PGC ..............................................19, 26, 34 MPLINK Object Linker/MPLIB Object Librarian ...............426 RB7/KBI3/PGD ..............................................19, 26, 34 MSSP RBIAS ............................................................24, 32, 42 ACK Pulse ........................................................284, 286 RC0/T1OSO/T13CKI .....................................20, 27, 35 Control Registers (general) ......................................269 RC1/T1OSI/ECCP2/P2A ...............................20, 27, 35 Module Overview .....................................................269 RC2/ECCP1/P1A ...........................................20, 27, 35 SPI Master/Slave Connection ..................................273 RC3/SCK1/SCL1 ...........................................20, 27, 35 SSPxBUF Register ..................................................274 RC4/SDI1/SDA1 ............................................20, 27, 35 SSPxSR Register .....................................................274 RC5/SDO1 .....................................................20, 27, 35 MULLW ............................................................................402 RC6/TX1/CK1 ................................................20, 27, 35 MULWF ............................................................................402 RC7/RX1/DT1 ................................................20, 27, 35 RD0 ...........................................................................28 N RD0/AD0/PSP0 .........................................................36 NEGF ...............................................................................403 RD0/P1B ....................................................................21 NOP .................................................................................403 RD1 ...........................................................................28 O RD1/AD1/PSP1 .........................................................36 RD1/ECCP3/P3A .......................................................21 Opcode Field Descriptions ...............................................376 RD2 ...........................................................................28 Organizationally Unique Identifier (OUI) ..........................248 RD2/AD2/PSP2 .........................................................36 DS39762F-page 482  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY RD2/CCP4/P3D .........................................................21 VDD ................................................................24, 42, 32 RD3/AD3/PSP3 ..........................................................36 VDDCORE/VCAP ..............................................42, 24, 32 RD4/AD4/PSP4/SDO2 ...............................................36 VDDPLL ...........................................................32, 42, 24 RD5/AD5/PSP5/SDI2/SDA2 ......................................36 VDDRX ............................................................32, 42, 24 RD6/AD6/PSP6/SCK2/SCL2 .....................................36 VDDTX ............................................................24, 32, 42 RD7/AD7/PSP7/SS2 ..................................................36 VSS ................................................................42, 32, 24 RE0/AD8/RD/P2D ......................................................37 VSSPLL ...........................................................24, 42, 32 RE0/P2D ..............................................................22, 28 VSSRX ............................................................32, 24, 42 RE1/AD9/WR/P2C .....................................................37 VSSTX .............................................................32, 42, 24 RE1/P2C ..............................................................22, 28 Pinout I/O Descriptions RE2/AD10/CS/P2B ....................................................37 PIC18F66J60/66J65/67J60 .......................................18 RE2/P2B ..............................................................22, 28 PIC18F86J60/86J65/87J60 .......................................25 RE3/AD11/P3C ..........................................................37 PIC18F96J60/96J65/97J60 .......................................33 RE3/P3C ..............................................................22, 28 PIR Registers ...................................................................134 RE4/AD12/P3B ..........................................................37 PLL Block ..........................................................................51 RE4/P3B ..............................................................22, 28 Clock Speeds for Various Configurations ..................52 RE5/AD13/P1C ..........................................................37 POP .................................................................................404 RE5/P1C ..............................................................22, 28 POR. See Power-on Reset. RE6/AD14/P1B ..........................................................37 PORTA RE6/P1B ....................................................................28 Associated Registers ...............................................147 RE7/AD15/ECCP2/P2A .............................................37 LATA Register .........................................................146 RE7/ECCP2/P2A .......................................................28 PORTA Register ......................................................146 RF0/AN5 ....................................................................38 TRISA Register ........................................................146 RF1/AN6/C2OUT ...........................................23, 29, 38 PORTB RF2/AN7/C1OUT ...........................................23, 29, 38 Associated Registers ...............................................150 RF3/AN8 ........................................................23, 29, 38 LATB Register .........................................................148 RF4/AN9 ........................................................23, 29, 38 PORTB Register ......................................................148 RF5/AN10/CVREF ..........................................23, 38, 29 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) .......148 RF6/AN11 ......................................................23, 29, 38 TRISB Register ........................................................148 RF7/SS1 ........................................................23, 38, 29 PORTC RG0/ECCP3/P3A .................................................30, 39 Associated Registers ...............................................153 RG1/TX2/CK2 ......................................................30, 39 LATC Register .........................................................151 RG2/RX2/DT2 ......................................................30, 39 PORTC Register ......................................................151 RG3/CCP4/P3D ...................................................30, 39 RC3/SCK1/SCL1 Pin ...............................................286 RG4/CCP5/P1D .............................................24, 30, 39 TRISC Register .......................................................151 RG5 ............................................................................39 PORTD RG6 ............................................................................39 Associated Registers ...............................................156 RG7 ............................................................................39 LATD Register .........................................................154 RH0 ............................................................................31 PORTD Register ......................................................154 RH0/A16 ....................................................................40 TRISD Register .......................................................154 RH1 ............................................................................31 PORTE RH1/A17 ....................................................................40 Associated Registers ...............................................159 RH2 ............................................................................31 LATE Register .........................................................157 RH2/A18 ....................................................................40 PORTE Register ......................................................157 RH3 ............................................................................31 PSP Mode Select (PSPMODE Bit) ..........................168 RH3/A19 ....................................................................40 RE0/AD8/RD/P2D Pin .............................................168 RH4/AN12/P3C ....................................................31, 40 RE1/AD9/WR/P2C Pin ............................................168 RH5/AN13/P3B ....................................................31, 40 RE2/AD10/CS/P2B Pin ............................................168 RH6/AN14/P1C ....................................................31, 40 TRISE Register ........................................................157 RH7/AN15/P1B ....................................................31, 40 PORTF RJ0/ALE .....................................................................41 Associated Registers ...............................................161 RJ1/OE ......................................................................41 LATF Register .........................................................160 RJ2/WRL ....................................................................41 PORTF Register ......................................................160 RJ3/WRH ...................................................................41 TRISF Register ........................................................160 RJ4 .............................................................................32 PORTG RJ4/BA0 .....................................................................41 Associated Registers ...............................................163 RJ5 .............................................................................32 LATG Register .........................................................162 RJ5/CE .......................................................................41 PORTG Register .....................................................162 RJ6/LB .......................................................................41 TRISG Register .......................................................162 RJ7/UB .......................................................................41 PORTH TPIN- ..............................................................24, 32, 42 Associated Registers ...............................................165 TPIN+ .............................................................24, 32, 42 LATH Register .........................................................164 TPOUT- ..........................................................24, 32, 42 PORTH Register ......................................................164 TPOUT+ .........................................................24, 32, 42 TRISH Register .......................................................164  2011 Microchip Technology Inc. DS39762F-page 483

PIC18F97J60 FAMILY PORTJ PWM (CCP Module) Associated Registers ...............................................167 Associated Registers ...............................................196 LATJ Register ..........................................................166 Duty Cycle ...............................................................194 PORTJ Register .......................................................166 Example Frequencies/Resolutions ..........................195 TRISJ Register .........................................................166 Operation Setup ......................................................195 Power-Managed Modes .....................................................55 Period ......................................................................194 and SPI Operation ...................................................277 TMR2 to PR2 Match ................................................203 Clock Sources ............................................................55 TMR4 to PR4 Match ................................................187 Clock Transitions and Status Indicators .....................56 PWM (ECCP Module) ......................................................203 Entering ......................................................................55 CCPR1H:CCPR1L Registers ...................................203 Exiting Idle and Sleep Modes ....................................61 Direction Change in Full-Bridge Output Mode .........209 By Interrupt ........................................................61 Duty Cycle ...............................................................204 By Reset ............................................................61 Effects of a Reset ....................................................214 By WDT Time-out ..............................................61 Enhanced PWM Auto-Shutdown .............................211 Without an Oscillator Start-up Timer Delay ........61 Example Frequencies/Resolutions ..........................204 Idle Modes .................................................................59 Full-Bridge Mode .....................................................208 PRI_IDLE ...........................................................60 Half-Bridge Mode .....................................................207 RC_IDLE ............................................................61 Output Configurations ..............................................204 SEC_IDLE ..........................................................60 Output Relationships (Active-High) ..........................205 Multiple Sleep Commands .........................................56 Output Relationships (Active-Low) ..........................206 Run Modes .................................................................56 Period ......................................................................203 PRI_RUN ...........................................................56 Programmable Dead-Band Delay ............................211 RC_RUN ............................................................58 Setup for PWM Operation ........................................214 SEC_RUN ..........................................................56 Start-up Considerations ...........................................213 Selection ....................................................................55 Q Sleep Mode ................................................................59 Summary (table) ........................................................55 Q Clock ....................................................................195, 204 Power-on Reset (POR) ......................................................65 R Power-up Timer (PWRT) ...........................................66 Time-out Sequence ....................................................66 RAM. See Data Memory. Power-up Delays ................................................................54 RC_IDLE Mode ..................................................................61 Power-up Timer (PWRT) ..............................................54, 66 RC_RUN Mode ..................................................................58 Prescaler RCALL .............................................................................405 Timer2 ......................................................................204 RCON Register Prescaler, Timer0 .............................................................173 Bit Status During Initialization ....................................68 Prescaler, Timer2 .............................................................195 Reader Response ............................................................489 PRI_IDLE Mode .................................................................60 Receive Filters PRI_RUN Mode .................................................................56 AND Logic Flow .......................................................262 Program Counter ................................................................81 Magic Packet Format ...............................................264 PCL, PCH and PCU Registers ...................................81 OR Logic Flow .........................................................261 PCLATH and PCLATU Registers ..............................81 Pattern Match Filter Format .....................................263 Program Memory Register File Summary ................................................91–96 Extended Instruction Set ..........................................100 Registers Instructions .................................................................85 ADCON0 (A/D Control 0) .........................................339 Two-Word ..........................................................85 ADCON1 (A/D Control 1) .........................................340 Interrupt Vector ..........................................................78 ADCON2 (A/D Control 2) .........................................341 Look-up Tables ..........................................................83 BAUDCONx (Baud Rate Control x) .........................318 Memory Maps ............................................................77 CCPxCON (Capture/Compare/PWM Control, Hard Vectors and Configuration Words .............78 CCP4 and CCP5) ............................................189 Memory Maps, Modes ...............................................80 CCPxCON (Enhanced CCPx Control, Modes ECCP1/ECCP2/ECCP3) .................................198 Memory Access (table) ......................................80 CMCON (Comparator Control) ................................349 Reset Vector ..............................................................78 CONFIG1H (Configuration 1 High) ..........................361 Program Memory Modes ....................................................79 CONFIG1L (Configuration 1 Low) ...........................361 Address Shifting (Extended Microcontroller) ..............80 CONFIG2H (Configuration 2 High) ..........................363 Extended Microcontroller ...........................................79 CONFIG2L (Configuration 2 Low) ...........................362 Microcontroller ...........................................................79 CONFIG3H (Configuration 3 High) ..........................365 Program Verification and Code Protection .......................373 CONFIG3L (Configuration 3 Low) .....................79, 364 Programming, Device Instructions ...................................375 CVRCON (Comparator Voltage PSP. See Parallel Slave Port. Reference Control) ..........................................355 Pulse-Width Modulation. See PWM (CCP Module) DEVID1 (Device ID 1) ..............................................366 and PWM (ECCP Module). DEVID2 (Device ID 2) ..............................................366 PUSH ...............................................................................404 ECCP1AS (ECCP1 Auto-Shutdown PUSH and POP Instructions ..............................................82 Configuration) ..................................................212 PUSHL .............................................................................420 ECCP1DEL (ECCP1 Dead-Band Delay) .................211 DS39762F-page 484  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY ECON1 (Ethernet Control 1) ....................................227 Reset .................................................................................63 ECON2 (Ethernet Control 2) ....................................228 Brown-out Reset (BOR) .............................................63 EECON1 (EEPROM Control 1) ................................107 Configuration Mismatch (CM) ....................................63 EFLOCON (Ethernet Flow Control) .........................258 MCLR Reset, During Power-Managed Modes ..........63 EIE (Ethernet Interrupt Enable) ................................240 MCLR Reset, Normal Operation ................................63 EIR (Ethernet Interrupt Request, Flag) ....................241 Power-on Reset (POR) ..............................................63 ERXFCON (Ethernet Receive Filter Control) ...........260 RESET Instruction .....................................................63 ESTAT (Ethernet Status) .........................................228 Stack Full Reset ........................................................63 INTCON (Interrupt Control) ......................................131 Stack Underflow Reset ..............................................63 INTCON2 (Interrupt Control 2) .................................132 State of Registers ......................................................68 INTCON3 (Interrupt Control 3) .................................133 Watchdog Timer (WDT) Reset IPR1 (Peripheral Interrupt Priority 1) ........................140 During Execution ...............................................63 IPR2 (Peripheral Interrupt Priority 2) ........................141 Resets .............................................................................359 IPR3 (Peripheral Interrupt Priority 3) ........................142 Brown-out Reset (BOR) ...........................................359 MABBIPG (MAC Back-to-Back Oscillator Start-up Timer (OST) ...............................359 Inter-Packet Gap) ............................................246 Power-on Reset (POR) ............................................359 MACON1 (MAC Control 1) .......................................229 Power-up Timer (PWRT) .........................................359 MACON3 (MAC Control 3) .......................................230 Stack Full/Underflow ..................................................83 MACON4 (MAC Control 4) .......................................231 RETFIE ............................................................................406 MEMCON (External Memory Bus Control) ..............116 RETLW ............................................................................406 MICMD (MII Command) ...........................................231 RETURN ..........................................................................407 MISTAT (MII Status) ................................................232 Return Address Stack ........................................................81 OSCCON (Oscillator Control) ....................................53 Return Stack Pointer (STKPTR) ........................................82 OSCTUNE (PLL Block Control) .................................51 Revision History ...............................................................475 PHCON1 (PHY Control 1) ........................................235 RLCF ...............................................................................407 PHCON2 (PHY Control 2) ........................................236 RLNCF .............................................................................408 PHIE (PHY Interrupt Enable) ...................................242 RRCF ...............................................................................408 PHIR (PHY Interrupt Request, Flag) ........................242 RRNCF ............................................................................409 PHLCON (PHY Module LED Control) ......................238 S PHSTAT1 (Physical Layer Status 1) ........................235 PHSTAT2 (Physical Layer Status 2) ........................237 SCKx ...............................................................................269 PIE1 (Peripheral Interrupt Enable 1) ........................137 SDIx .................................................................................269 PIE2 (Peripheral Interrupt Enable 2) ........................138 SDOx ...............................................................................269 PIE3 (Peripheral Interrupt Enable 3) ........................139 SEC_IDLE Mode ...............................................................60 PIR1 (Peripheral Interrupt Request (Flag) 1) ...........134 SEC_RUN Mode ................................................................56 PIR2 (Peripheral Interrupt Request (Flag) 2) ...........135 Serial Clock, SCKx ..........................................................269 PIR3 (Peripheral Interrupt Request (Flag) 3) ...........136 Serial Data In (SDIx) ........................................................269 PSPCON (Parallel Slave Port Control) ....................169 Serial Data Out (SDOx) ...................................................269 RCON (Reset Control) .......................................64, 143 Serial Peripheral Interface. See SPI Mode. RCSTAx (Receive Status and Control x) .................317 SETF ...............................................................................409 SSPxCON1 (MSSPx Control 1, I2C Mode) ..............281 Slave Select (SSx) ...........................................................269 SSPxCON1 (MSSPx Control 1, SPI Mode) .............271 SLEEP .............................................................................410 SSPxCON2 (MSSPx Control 2, Sleep I2C Master Mode) ............................................282 OSC1 and OSC2 Pin States ......................................54 SSPxCON2 (MSSPx Control 2, Software Simulator (MPLAB SIM) ...................................427 I2C Slave Mode) ..............................................283 Special Event Trigger. See Compare (ECCP Module). SSPxSTAT (MSSPx Status, I2C Mode) ...................280 Special Features of the CPU ...........................................359 SSPxSTAT (MSSPx Status, SPI Mode) ..................270 Special Function Registers STATUS .....................................................................97 Ethernet SFRs ...........................................................90 STKPTR (Stack Pointer) ............................................82 SPI Mode (MSSP) T0CON (Timer0 Control) ..........................................171 Associated Registers ...............................................278 T1CON (Timer1 Control) ..........................................175 Bus Mode Compatibility ...........................................277 T2CON (Timer2 Control) ..........................................180 Clock Speed and Module Interactions .....................277 T3CON (Timer3 Control) ..........................................183 Effects of a Reset ....................................................277 T4CON (Timer4 Control) ..........................................187 Enabling SPI I/O ......................................................273 TXSTAx (Transmit Status and Control x) .................316 Master Mode ............................................................274 WDTCON (Watchdog Timer Control) ......................368 Master/Slave Connection ........................................273 RESET .............................................................................405 Operation .................................................................272 Operation in Power-Managed Modes ......................277  2011 Microchip Technology Inc. DS39762F-page 485

PIC18F97J60 FAMILY Serial Clock ..............................................................269 Timer3 ..............................................................................183 Serial Data In ...........................................................269 16-Bit Read/Write Mode ..........................................185 Serial Data Out ........................................................269 Associated Registers ...............................................185 Slave Mode ..............................................................275 Operation .................................................................184 Slave Select .............................................................269 Oscillator ..........................................................183, 185 Slave Select Synchronization ..................................275 Overflow Interrupt ............................................183, 185 SPI Clock .................................................................274 Resetting Using the ECCPx Special Typical Connection ..................................................273 Event Trigger ...................................................185 SSPOV .............................................................................304 TMR3H Register ......................................................183 SSPOV Status Flag ..........................................................304 TMR3L Register .......................................................183 SSPSTAT Register Timer4 ..............................................................................187 R/W Bit .....................................................................286 Associated Registers ...............................................188 SSPxSTAT Register Operation .................................................................187 R/W Bit .....................................................................284 Output, PWM Time Base .........................................188 .........................................................................................269 Postscaler. See Postscaler, Timer4. SUBFSR ...........................................................................421 PR4 Register ...................................................187, 194 SUBFWB ..........................................................................410 Prescaler. See Prescaler, Timer4. SUBLW ............................................................................411 TMR4 Register .........................................................187 SUBULNK ........................................................................421 TMR4 to PR4 Match Interrupt ..........................187, 188 SUBWF ............................................................................411 Timing Diagrams SUBWFB ..........................................................................412 A/D Conversion ........................................................462 SWAPF ............................................................................412 Asynchronous Reception, RXDTP = 0 (RXx Not Inverted) ...........................................329 T Asynchronous Transmission (Back-to-Back), Table Pointer Operations (table) ......................................108 TXCKP = 0 (TXx Not Inverted) ........................326 Table Reads/Table Writes ..................................................83 Asynchronous Transmission, TXCKP = 0 TBLRD .............................................................................413 (TXx Not Inverted) ...........................................326 TBLWT .............................................................................414 Automatic Baud Rate Calculation ............................324 Timer0 ..............................................................................171 Auto-Wake-up Bit (WUE) During Normal Associated Registers ...............................................173 Operation .........................................................331 Clock Source Select (T0CS Bit) ...............................172 Auto-Wake-up Bit (WUE) During Sleep ...................331 Operation .................................................................172 Baud Rate Generator with Clock Arbitration ............301 Overflow Interrupt ....................................................173 BRG Overflow Sequence .........................................324 Prescaler ..................................................................173 BRG Reset Due to SDAx Arbitration During Prescaler Assignment (PSA Bit) ..............................173 Start Condition .................................................310 Prescaler Select (T0PS2:T0PS0 Bits) .....................173 Capture/Compare/PWM (Including Prescaler, Switching Assignment .............................173 ECCPx Modules) .............................................452 Prescaler. See Prescaler, Timer0. CLKO and I/O ..........................................................447 Reads and Writes in 16-Bit Mode ............................172 Clock Synchronization .............................................294 Source Edge Select (T0SE Bit) ................................172 Clock/Instruction Cycle ..............................................84 Timer1 ..............................................................................175 EUSARTx Synchronous Receive 16-Bit Read/Write Mode ...........................................177 (Master/Slave) .................................................461 Associated Registers ...............................................179 EUSARTx Synchronous Transmission Considerations in Asynchronous Counter Mode ......178 (Master/Slave) .................................................461 Interrupt ....................................................................178 Example SPI Master Mode (CKE = 0) .....................453 Operation .................................................................176 Example SPI Master Mode (CKE = 1) .....................454 Oscillator ..........................................................175, 177 Example SPI Slave Mode (CKE = 0) .......................455 Layout Considerations .....................................177 Example SPI Slave Mode (CKE = 1) .......................456 Overflow Interrupt ....................................................175 External Clock (All Modes Except PLL) ...................445 Resetting, Using the ECCPx Special External Memory Bus for Sleep (Extended Event Trigger ...................................................178 Microcontroller Mode) ..............................122, 124 Special Event Trigger (ECCP) .................................202 External Memory Bus for TBLRD (Extended TMR1H Register ......................................................175 Microcontroller Mode) ..............................122, 124 TMR1L Register .......................................................175 Fail-Safe Clock Monitor ...........................................372 Use as a Clock Source ............................................177 First Start Bit ............................................................302 Use as a Real-Time Clock .......................................178 Full-Bridge PWM Output ..........................................208 Timer2 ..............................................................................180 Half-Bridge PWM Output .........................................207 Associated Registers ...............................................181 I2C Acknowledge Sequence ....................................307 Interrupt ....................................................................181 I2C Bus Collision During a Repeated Operation .................................................................180 Start Condition (Case 1) ..................................311 Output ......................................................................181 I2C Bus Collision During a Repeated PR2 Register ....................................................194, 203 Start Condition (Case 2) ..................................311 TMR2 to PR2 Match Interrupt ..................................203 I2C Bus Collision During a Stop Condition (Case 1) 312 DS39762F-page 486  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY I2C Bus Collision During a Stop Transition From RC_RUN Mode to Condition (Case 2) ...........................................312 PRI_RUN Mode .................................................58 I2C Bus Collision During Start Transition From SEC_RUN Mode to Condition (SCLx = 0) .......................................310 PRI_RUN Mode (HSPLL) ..................................57 I2C Bus Collision During Start Transition to RC_RUN Mode .....................................58 Condition (SDAx Only) .....................................309 Timing Diagrams and Specifications I2C Bus Collision for Transmit and Acknowledge ....308 AC Characteristics I2C Bus Data ............................................................457 Internal RC Accuracy .......................................446 I2C Bus Start/Stop Bits .............................................457 Capture/Compare/PWM Requirements I2C Master Mode (7 or 10-Bit Transmission) ...........305 (Including ECCPx Modules) ............................452 I2C Master Mode (7-Bit Reception) ..........................306 CLKO and I/O Requirements ...........................447, 448 I2C Slave Mode (10-Bit Reception, SEN = 0, EUSARTx Synchronous Receive Requirements .....461 ADMSK = 01001) .............................................291 EUSARTx Synchronous Transmission I2C Slave Mode (10-Bit Reception, SEN = 0) ..........290 Requirements ..................................................461 I2C Slave Mode (10-Bit Reception, SEN = 1) ..........296 Example SPI Mode Requirements I2C Slave Mode (10-Bit Transmission) .....................292 (Master Mode, CKE = 0) ..................................453 I2C Slave Mode (7-Bit Reception, SEN = 0, Example SPI Mode Requirements ADMSK = 01011) .............................................288 (Master Mode, CKE = 1) ..................................454 I2C Slave Mode (7-Bit Reception, SEN = 0) ............287 Example SPI Mode Requirements I2C Slave Mode (7-Bit Reception, SEN = 1) ............295 (Slave Mode, CKE = 0) ....................................455 I2C Slave Mode (7-Bit Transmission) .......................289 Example SPI Slave Mode Requirements (CKE = 1) 456 I2C Slave Mode General Call Address External Clock Requirements ..................................445 Sequence (7 or 10-Bit Addressing Mode) ........297 I2C Bus Data Requirements (Slave Mode) ..............458 I2C Stop Condition Receive or Transmit Mode ........307 I2C Bus Start/Stop Bits Requirements Master SSP I2C Bus Data ........................................459 (Slave Mode) ...................................................457 Master SSP I2C Bus Start/Stop Bits ........................459 Master SSP I2C Bus Data Requirements ................460 Parallel Slave Port (PSP) Read ...............................170 Master SSP I2C Bus Start/Stop Bits Parallel Slave Port (PSP) Write ...............................169 Requirements ..................................................459 Program Memory Read ............................................448 Parallel Slave Port Requirements ............................452 Program Memory Write ............................................449 PLL Clock ................................................................446 PWM Auto-Shutdown (P1RSEN = 0, Program Memory Write Requirements ....................449 Auto-Restart Disabled) ....................................213 Reset, Watchdog Timer, Oscillator Start-up PWM Auto-Shutdown (P1RSEN = 1, Timer, Power-up Timer and Brown-out Auto-Restart Enabled) .....................................213 Reset Requirements ........................................450 PWM Direction Change ...........................................210 Timer0 and Timer1 External Clock PWM Direction Change at Near Requirements ..................................................451 100% Duty Cycle .............................................210 Top-of-Stack Access ..........................................................81 PWM Output ............................................................194 TRISE Register Repeated Start Condition .........................................303 PSPMODE Bit .........................................................168 Reset, Watchdog Timer (WDT), Oscillator Start-up TSTFSZ ...........................................................................415 Timer (OST) and Power-up Timer (PWRT) .....450 Two-Speed Start-up .................................................359, 370 Send Break Character Sequence ............................332 Two-Word Instructions Slave Synchronization .............................................275 Example Cases .........................................................85 Slow Rise Time (MCLR Tied to VDD, TXSTAx Register VDD Rise > TPWRT) ............................................67 BRGH Bit .................................................................319 SPI Mode (Master Mode) .........................................274 V SPI Mode (Slave Mode, CKE = 0) ...........................276 SPI Mode (Slave Mode, CKE = 1) ...........................276 VDDCORE/VCAP Pin ..........................................369, 442, 369 Synchronous Reception (Master Mode, SREN) ......335 W Synchronous Transmission ......................................333 Synchronous Transmission (Through TXEN) ..........334 Watchdog Timer (WDT) ...........................................359, 367 Time-out Sequence on Power-up (MCLR Associated Registers ...............................................368 Not Tied to VDD), Case 1 ...................................66 Control Register .......................................................367 Time-out Sequence on Power-up (MCLR Programming Considerations ..................................367 Not Tied to VDD), Case 2 ...................................67 WCOL ......................................................302, 303, 304, 307 Time-out Sequence on Power-up (MCLR Tied WCOL Status Flag ...................................302, 303, 304, 307 to VDD, VDD Rise < TPWRT) ................................66 WWW Address ................................................................488 Timer0 and Timer1 External Clock ..........................451 WWW, On-Line Support ......................................................9 Transition for Entry to Idle Mode ................................60 X Transition for Entry to SEC_RUN Mode ....................57 Transition for Entry to Sleep Mode ............................59 XORLW ...........................................................................415 Transition for Two-Speed Start-up XORWF ...........................................................................416 (INTRC to HSPLL) ...........................................370 Transition for Wake From Idle to Run Mode ..............60 Transition for Wake From Sleep Mode (HSPLL) .......59  2011 Microchip Technology Inc. DS39762F-page 487

PIC18F97J60 FAMILY NOTES: DS39762F-page 488  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011 Microchip Technology Inc. DS39762F-page 489

PIC18F97J60 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F97J60 Family Literature Number: DS39762F Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39762F-page 490  2011 Microchip Technology Inc.

PIC18F97J60 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18F67J60-I/PT 301 = Industrial temp., Range TQFP package, QTP pattern #301. b) PIC18F67J60T-I/PT = Tape and reel, Industrial temp., TQFP package. Device PIC18F66J60/66J65/67J60, PIC18F86J60/86J65/87J60, PIC18F96J60/96J65/97J60, PIC18F66J60/66J65/67J60T(1), PIC18F86J60/86J65/87J60T(1), PIC18F96J60/96J65/97J60T(1) Temperature Range I = -40C to +85C (Industrial) Package PT = 64, 80 and 100-Lead, 12x12x1mm TQFP (Thin Quad Flatpack) PF = 100-Lead, 14x14x1mm TQFP Note1: T = in tape and reel Pattern QTP, SQTP, Code or Special Requirements (blank otherwise)  2011 Microchip Technology Inc. DS39762F-page 491

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