PIC18F87J50 Family Data Sheet 64/80-Pin High-Performance, 1-Mbit Flash USB Microcontrollers with nanoWatt Technology © 2009 Microchip Technology Inc. DS39775C

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of Microchip MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries. WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard, arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39775C-page 2 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 64/80-Pin High-Performance, 1-Mbit Flash USB Microcontrollers with nanoWatt Technology Universal Serial Bus Features: Peripheral Highlights (continued): • USB V2.0 Compliant SIE • 10-Bit, up to 12-Channel Analog-to-Digital (A/D) • Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s) Converter module: • Supports Control, Interrupt, Isochronous and - Auto-acquisition capability Bulk Transfers - Conversion available during Sleep • Supports up to 32 Endpoints (16 bidirectional) • Two Enhanced USART modules: • 3.9-Kbyte Dual Access RAM for USB - Supports RS-485, RS-232 and LIN 1.2 • On-Chip USB Transceiver - Auto-wake-up on Start bit - Auto-Baud Detect Flexible Oscillator Structure: External Memory Bus • High-Precision PLL for USB (80-pin devices only): • Two External Clock modes, up to 48 MHz • Internal 31 kHz Oscillator, Tunable Internal • Address Capability of up to 2 Mbytes Oscillator, 31 kHz to 8 MHz • 8-Bit or 16-Bit Interface • Secondary Oscillator using Timer1 @ 32 kHz • 12-Bit, 16-Bit and 20-Bit Addressing modes • Fail-Safe Clock Monitor: Special Microcontroller Features: - Allows for safe shutdown if any clock stops • 5.5V Tolerant Inputs (digital-only pins) Peripheral Highlights: • Low-Power, High-Speed CMOS Flash Technology • High-Current Sink/Source 25 mA/25mA • C Compiler Optimized Architecture for (PORTB and PORTC) Re-Entrant Code • Four Programmable External Interrupts • Power Management Features: • Four Input Change Interrupts - Run: CPU on, peripherals on • Two Capture/Compare/PWM (CCP) modules - Idle: CPU off, peripherals on • Three Enhanced Capture/Compare/PWM (ECCP) - Sleep: CPU off, peripherals off modules: • Priority Levels for Interrupts - One, two or four PWM outputs • Self-Programmable under Software Control - Selectable polarity • 8 x 8 Single-Cycle Hardware Multiplier - Programmable dead time • Extended Watchdog Timer (WDT): - Auto-shutdown and auto-restart - Programmable period from 4 ms to 131s • Two Master Synchronous Serial Port (MSSP) • Single-Supply In-Circuit Serial Programming™ modules supporting 3-Wire SPI (all 4 modes) and (ICSP™) via Two Pins I2C™ Master and Slave modes • In-Circuit Debug (ICD) with 3 Breakpoints via • 8-Bit Parallel Master Port/Enhanced Parallel Two Pins Slave Port with 16 Address Lines • Operating Voltage Range of 2.0V to 3.6V • Dual Analog Comparators with Input Multiplexing • On-Chip 2.5V Regulator • Flash Program Memory of 10000 Erase/Write Cycles and 20-Year Data Retention © 2009 Microchip Technology Inc. DS39775C-page 3

PIC18F87J50 FAMILY Device MFleamsho rPyr (obgyrtaems) SRM(bAeyMmte oDsra)yta I/O A1/D0- B(ciht) (EPCCWCCPMP/) SMPSISPMI2aCs™ter EUSART omparators Timers8/16-Bit xternal Bus PMP/PSP C E PIC18F65J50 32K 3904* 49 8 2/3 2 Y Y 2 2 2/3 N Y PIC18F66J50 64K 3904* 49 8 2/3 2 Y Y 2 2 2/3 N Y PIC18F66J55 96K 3904* 49 8 2/3 2 Y Y 2 2 2/3 N Y PIC18F67J50 128K 3904* 49 8 2/3 2 Y Y 2 2 2/3 N Y PIC18F85J50 32K 3904* 65 12 2/3 2 Y Y 2 2 2/3 Y Y PIC18F86J50 64K 3904* 65 12 2/3 2 Y Y 2 2 2/3 Y Y PIC18F86J55 96K 3904* 65 12 2/3 2 Y Y 2 2 2/3 Y Y PIC18F87J50 128K 3904* 65 12 2/3 2 Y Y 2 2 2/3 Y Y * Includes the dual access RAM used by the USB module which is shared with data memory. Pin Diagrams 1) (A 64-Pin TQFP E/P2B13/P3C/REFO12/P3B11/P1C10/P1B(1)9/ECCP2/P20 123 4/SDO25/SDI2/SDA26/SCK2/SCL27/SS2 BAAAAAD DDD DDDD MMMMMMM MMM MMMM PPPPPPP PPP PPPP E2/E3/E4/E5/E6/E7/D0/ DD SS D1/D2/D3/ D4/D5/D6/D7/ RRRRRRRVVRRR RRRR 4321 098765 4321 09 6666 655555 5555 54 RE1/PMWR/P2C 1 48 RB0/FLT0/INT0 RE0/PMRD/P2D 2 47 RB1/INT1/PMA4 RG0/PMA8/ECCP3/P3A 3 46 RB2/INT2/PMA3 RG1/PMA7/TX2/CK2 4 45 RB3/INT3/PMA2 RG2/PMA6/RX2/DT2 5 44 RB4/KBI0/PMA1 RG3/PMCS1/CCP4/P3D 6 43 RB5/KBI1/PMA0 MCLR 7 42 RB6/KBI2/PGC PIC18F6XJ5X RG4/PMCS2/CCP5/P1D 8 41 VSS VSS 9 40 OSC2/CLKO/RA6 VDDCORE/VCAP 10 39 OSC1/CLKI/RA7 RF7/SS1/C1OUT 11 38 VDD RF6/AN11/C1INA 12 37 RB7/KBI3/PGD RF5/AN10/C1INB/CVREF 13 36 RC5/SDO1/C2OUT RF4/D+ 14 35 RC4/SDI1/SDA1 RF3/D- 15 34 RC3/SCK1/SCL1 RF2/PMA5/AN7/C2INB 16 33 RC2/ECCP1/P1A 7890123456789012 1112222222222333 VUSB ENVREGAVDD AVSSRA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1RA0/AN0VSS VDD RA5/AN4/C2INARA4/T0CKI(1)(1)SI/ECCP2/P2AC0/T1OSO/T13CKIRC6/TX1/CK1RC7/RX1/DT1 OR 1 T 1/ C R Note 1: The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit. DS39775C-page 4 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY Pin Diagrams (Continued) 1) O (A 80-Pin TQFP A17 A16(3)AD10/PMBE/P2B(2)AD11/PMA13/P3C/REF(2)AD12/PMA12/P3B(2)AD13/PMA11/P1C(2)AD14/PMA10/P1B(1)AD15/PMA9/ECCP2/P2 AD0/PMD0 (3)AD1/PMD1(3)AD2/PMD2(3)AD3/PMD3(3)AD4/PMD4/SDO2(3)AD5/PMD5/SDI2/SDA2(3)AD6/PMD6/SCK2/SCL2(3)AD7/PMD7/SS2 ALE OE H1/ H0/ E2/ E3/ E4/ E5/ E6/ E7/ D0/ DD SS D1/ D2/ D3/ D4/ D5/ D6/ D7/ J0/ J1/ R R R R R R R R R V V R R R R R R R R R 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 RH2/A18/PMD7(4) 1 60 RJ2/WRL RH3/A19/PMD6(4) 2 59 RJ3/WRH RE1/AD9/PMWR(3)/P2C 3 58 RB0/FLT0/INT0 RE0/AD8/PMRD(3)/P2D 4 57 RB1/INT1/PMA4 RG0/PMA8/ECCP3/P3A 5 56 RB2/INT2/PMA3 RG1/PMA7/TX2/CK2 6 55 RP2BA3(/1IN)/PTM3/AE2CCP2(1)/ RG2/PMA6/RX2/DT2 7 54 RB4/KBI0/PMA1 RG3/PMCS1/CCP4/P3D 8 53 RB5/KBI1/PMA0 MCLR 9 52 RB6/KBI2/PGC RG4/PMCS2/CCP5/P1D 10 PIC18F8XJ5X 51 VSS VSS 11 50 OSC2/CLKO/RA6 VDDCORE/VCAP 12 49 OSC1/CLKI/RA7 RF7/PMD0(4)/SS1/C1OUT 13 48 VDD RF6/PMD1(4)/AN11/C1INA 14 47 RB7/KBI3/PGD RF5/PCM1DIN2(B4)//CAVNR1E0F/ 15 46 RC5/SDO1/C2OUT RF4/D+ 16 45 RC4/SDI1/SDA1 RF3/D- 17 44 RC3/SCK1/SCL1 RF2/PMA5/AN7/C2INB 18 43 RC2/ECCP1/P1A RH7/PMWR(4)/AN15/P1B(2) 19 42 RJ7/UB RH6/PMRD(4)/AN14/ 20 41 RJ6/LB P1C(2)/C1INC 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 (4)(2)BE/AN13/P3B/C2IND(4)(2)D3/AN12/P3C/C2INC VUSB ENVREG AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0 VSS VDD(4)RA5/PMD4/AN4/C2INA(4)RA4/PMD5/T0CKI(1)(1)1/T1OSI/ECCP2/P2A RC0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 RJ4/BA0 RJ5/CE M M C P P R 5/ 4/ H H R R Note 1: The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit and the program memory mode. 2: P1B, P1C, P3B and P3C pin placement depends on the setting of the ECCPMX Configuration bit. 3: PMP pin placement when PMPMX = 1. 4: PMP pin placement when PMPMX = 0. © 2009 Microchip Technology Inc. DS39775C-page 5

PIC18F87J50 FAMILY Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Oscillator Configurations............................................................................................................................................................35 3.0 Power-Managed Modes.............................................................................................................................................................47 4.0 Reset..........................................................................................................................................................................................55 5.0 Memory Organization.................................................................................................................................................................69 6.0 Flash Program Memory..............................................................................................................................................................97 7.0 External Memory Bus...............................................................................................................................................................107 8.0 8 x 8 Hardware Multiplier..........................................................................................................................................................119 9.0 Interrupts..................................................................................................................................................................................121 10.0 I/O Ports...................................................................................................................................................................................137 11.0 Parallel Master Port..................................................................................................................................................................167 12.0 Timer0 Module.........................................................................................................................................................................191 13.0 Timer1 Module.........................................................................................................................................................................195 14.0 Timer2 Module.........................................................................................................................................................................201 15.0 Timer3 Module.........................................................................................................................................................................203 16.0 Timer4 Module.........................................................................................................................................................................207 17.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................209 18.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................217 19.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................233 20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................279 21.0 10-bit Analog-to-Digital Converter (A/D) Module......................................................................................................................301 22.0 Universal Serial Bus (USB)......................................................................................................................................................311 23.0 Comparator Module..................................................................................................................................................................337 24.0 Comparator Voltage Reference Module...................................................................................................................................345 25.0 Special Features of the CPU....................................................................................................................................................349 26.0 Instruction Set Summary..........................................................................................................................................................365 27.0 Development Support...............................................................................................................................................................415 28.0 Electrical Characteristics..........................................................................................................................................................419 29.0 Packaging Information..............................................................................................................................................................459 Appendix A: Revision History.............................................................................................................................................................463 Appendix B: Device Differences.........................................................................................................................................................463 The Microchip Web Site.....................................................................................................................................................................477 Customer Change Notification Service..............................................................................................................................................477 Customer Support..............................................................................................................................................................................477 Reader Response..............................................................................................................................................................................478 Product Identification System.............................................................................................................................................................479 DS39775C-page 6 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. DS39775C-page 7

PIC18F87J50 FAMILY NOTES: DS39775C-page 8 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 1.0 DEVICE OVERVIEW 1.1.3 OSCILLATOR OPTIONS AND FEATURES This document contains device-specific information for the following devices: All of the devices in the PIC18F87J10 family offer five different oscillator options, allowing users a range of • PIC18F65J50 • PIC18F85J50 choices in developing application hardware. These • PIC18F66J50 • PIC18F86J50 include: • PIC18F66J55 • PIC18F86J55 • Two Crystal modes, using crystals or ceramic resonators. • PIC18F67J50 • PIC18F87J50 • Two External Clock modes, offering the option of This family introduces a new line of low-voltage USB a divide-by-4 clock output. microcontrollers with the main traditional advantage of • An internal oscillator block which provides an all PIC18 microcontrollers – namely, high computa- 8MHz clock and an INTRC source (approxi- tional performance and a rich feature set – at an mately 31 kHz, stable over temperature and VDD), extremely competitive price point. These features as well as a range of 6 user-selectable clock make the PIC18F87J10 family a logical choice for frequencies, between 125 kHz to 4 MHz, for a many high-performance applications, where cost is a total of 8 clock frequencies. This option frees an primary consideration. oscillator pin for use as an additional general purpose I/O. 1.1 Core Features • A Phase Lock Loop (PLL) frequency multiplier, available to the high-speed crystal, external 1.1.1 nanoWatt TECHNOLOGY oscillator and internal oscillator, providing a clock All of the devices in the PIC18F87J10 family incorporate speed up to 48 MHz. a range of features that can significantly reduce power • Dual clock operation, allowing the USB module to consumption during operation. Key items include: run from a high-frequency oscillator while the rest • Alternate Run Modes: By clocking the controller of the microcontroller is clocked at a different from the Timer1 source or the internal RC oscilla- frequency. tor, power consumption during code execution The internal oscillator block provides a stable reference can be reduced by as much as 90%. source that gives the family additional features for • Multiple Idle Modes: The controller can also run robust operation: with its CPU core disabled but the peripherals still • Fail-Safe Clock Monitor: This option constantly active. In these states, power consumption can be monitors the main clock source against a reference reduced even further, to as little as 4% of normal signal provided by the internal oscillator. If a clock operation requirements. failure occurs, the controller is switched to the • On-the-Fly Mode Switching: The internal oscillator, allowing for continued low-speed power-managed modes are invoked by user code operation or a safe application shutdown. during operation, allowing the user to incorporate • Two-Speed Start-up: This option allows the power-saving ideas into their application’s internal oscillator to serve as the clock source software design. from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. 1.1.2 UNIVERSAL SERIAL BUS (USB) 1.1.4 EXPANDED MEMORY Devices in the PIC18F87J10 family incorporate a fully-featured Universal Serial Bus communications The PIC18F87J10 family provides ample room for module with a built-in transceiver that is compliant with application code, from 32Kbytes to 128Kbytes of code the USB Specification Revision 2.0. The module space. The Flash cells for program memory are rated supports both low-speed and full-speed communication to last in excess of 10000 erase/write cycles. Data for all supported data transfer types. retention without refresh is conservatively estimated to be greater than 20 years. The Flash program memory is readable and writable during normal operation. The PIC18F87J10 family also provides plenty of room for dynamic application data with up to 3904bytes of data RAM. © 2009 Microchip Technology Inc. DS39775C-page 9

PIC18F87J50 FAMILY 1.1.5 EXTERNAL MEMORY BUS • CCP Modules: All devices in the family incorporate two Capture/Compare/PWM (CCP) modules and In the event that 128Kbytes of memory are inadequate three Enhanced CCP modules to maximize for an application, the 80-pin members of the flexibility in control applications. Up to four different PIC18F87J10 family also implement an External Mem- time bases may be used to perform several ory Bus (EMB). This allows the controller’s internal different operations at once. Each of the three program counter to address a memory space of up to ECCPs offers up to four PWM outputs, allowing for 2Mbytes, permitting a level of data access that few a total of 12 PWMs. The ECCPs also offer many 8-bit devices can claim. This allows additional memory beneficial features, including polarity selection, options, including: programmable dead time, auto-shutdown and • Using combinations of on-chip and external restart and Half-Bridge and Full-Bridge Output memory up to the 2-Mbyte limit modes. • Using external Flash memory for reprogrammable • 10-Bit A/D Converter: This module incorporates application code or large data tables programmable acquisition time, allowing for a • Using external RAM devices for storing large channel to be selected and a conversion to be amounts of variable data initiated without waiting for a sampling period, and thus, reducing code overhead. 1.1.6 EXTENDED INSTRUCTION SET • Extended Watchdog Timer (WDT): This The PIC18F87J10 family implements the optional enhanced version incorporates a 16-bit prescaler, extension to the PIC18 instruction set, adding 8 new allowing an extended time-out range that is stable instructions and an Indexed Addressing mode. across operating voltage and temperature. See Enabled as a device configuration option, the extension Section28.0 “Electrical Characteristics” for has been specifically designed to optimize re-entrant time-out periods. application code originally developed in high-level languages, such as ‘C’. 1.3 Details on Individual Family 1.1.7 EASY MIGRATION Members Regardless of the memory size, all devices share the Devices in the PIC18F87J10 family are available in same rich set of peripherals, allowing for a smooth 64-pin and 80-pin packages. Block diagrams for the migration path as applications grow and evolve. two groups are shown in Figure1-1 and Figure1-2. The consistent pinout scheme used throughout the The devices are differentiated from each other in two entire family also aids in migrating to the next larger ways: device. This is true when moving between the 64-pin 1. Flash program memory (six sizes, ranging from members, between the 80-pin members, or even 32Kbytes for PIC18FX5J50 devices to jumping from 64-pin to 80-pin devices. 128Kbytes for PIC18FX7J50). The PIC18F87J10 family is also pin compatible with 2. I/O ports (7 bidirectional ports on 64-pin devices, other PIC18 families, such as the PIC18F87J10, 9 bidirectional ports on 80-pin devices). PIC18F87J11, PIC18F8720 and PIC18F8722. This All other features for devices in this family are identical. allows a new dimension to the evolution of applications, These are summarized in Table1-1 and Table1-2. allowing developers to select different price points The pinouts for all devices are listed in Table1-3 and within Microchip’s PIC18 portfolio, while maintaining Table1-4. the same feature set. 1.2 Other Special Features • Communications: The PIC18F87J10 family incorporates a range of serial and parallel com- munication peripherals, including a fully featured Universal Serial Bus communications module that is compliant with the USB Specification Revision2.0. This device also includes 2 indepen- dent Enhanced USARTs and 2 Master SSP modules, capable of both SPI and I2C™ (Master and Slave) modes of operation. The device also has a parallel port and can be configured to serve as either a Parallel Master Port or as a Parallel Slave Port. DS39775C-page 10 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F6XJ5X (64-PIN DEVICES) Features PIC18F65J50 PIC18F66J50 PIC18F66J55 PIC18F67J50 Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz Program Memory (Bytes) 32K 64K 96K 128K Program Memory (Instructions) 16384 32768 49152 65536 Data Memory (Bytes) 3904 3904 3904 3904 Interrupt Sources 30 I/O Ports Ports A, B, C, D, E, F, G Timers 5 Capture/Compare/PWM Modules 2 Enhanced Capture/ 3 Compare/PWM Modules Serial Communications MSSP (2), Enhanced USART (2), USB Parallel Communications (PMP) Yes 10-Bit Analog-to-Digital Module 8 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 64-Pin TQFP TABLE 1-2: DEVICE FEATURES FOR THE PIC18F8XJ5X (80-PIN DEVICES) Features PIC18F85J50 PIC18F86J50 PIC18F86J55 PIC18F87J50 Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz Program Memory (Bytes) 32K 64K 96K 128K Program Memory (Instructions) 16384 32768 49152 65536 Data Memory (Bytes) 3904 3904 3904 3904 Interrupt Sources 30 I/O Ports Ports A, B, C, D, E, F, G, H, J Timers 5 Capture/Compare/PWM Modules 2 Enhanced Capture/ 3 Compare/PWM Modules Serial Communications MSSP (2), Enhanced USART (2), USB Parallel Communications (PMP) Yes 10-Bit Analog-to-Digital Module 12 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 80-Pin TQFP © 2009 Microchip Technology Inc. DS39775C-page 11

PIC18F87J50 FAMILY FIGURE 1-1: PIC18F6XJ5X (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch inc/dec logic 8 8 RA0:RA5(1) Data Memory (3.9 Kbytes) 21 PCLAT U PCLATH 20 Address Latch PCU PCH PCL Program Counter 12 PORTB Data Address<12> RB0:RB7(1) 31 Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (32-128Kbytes) FSR1 Data Latch FSR2 12 PORTC inc/dec RC0:RC7(1) 8 logic Table Latch Address ROM Latch Instruction Bus <16> Decode PORTD IR RD0:RD7(1) 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL PORTE RE0:RE7(1) 8 x 8 Multiply OSC2/CLKO GeTnimeriantgion Power-up 3 8 OSC1/CLKI IN8T MOHSzC Timer BITO8P W8 8 Oscillator OIsNcTilRlaCtor Start-up Timer 8 8 PORTF VUSB Power-on RF2:RF7(1) USB ALU<8> Reset Module 8 Precision Watchdog Band Gap Timer Reference ENVREG Brown-out PORTG Voltage Reset(2) Regulator RG0:RG4(1) VDDCORE/VCAP VDD,VSS MCLR ADC 10-Bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators PMP ECCP1 ECCP2 ECCP3 CCP4 CCP5 EUSART1 EUSART2 MSSP1 MSSP2 USB Note 1: See Table1-3 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. DS39775C-page 12 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 1-2: PIC18F8XJ5X (80-PIN) BLOCK DIAGRAM Data Bus<8> PORTA Table Pointer<21> 8 8 Data Latch RA0:RA5(1) Data Memory inc/dec logic PCLAT U PCLATH (3.9 Kbytes) 21 20 Address Latch PCU PCH PCL PORTB Program Counter 12 RB0:RB7(1) Data Address<12> 31 Level Stack e Address Latch 4 12 4 nterfac P(r3o2g-r1a2m8 KMbeymteosr)y STKPTR BSR FFSSRR01 ABccaensks RCP0O:RRCTC7(1) us I Data Latch FSR2 12 B m ste 8 inloc/gdiecc PORTD Sy Table Latch RD0:RD7(1) Address ROM Latch Decode Instruction Bus <16> PORTE IR RE0:RE7(1) AD15:AD0, A19:A16 (Multiplexed with PORTD, 8 PORTE and PORTH) PORTF PRODH PRODL State Machine IDnestcroudcteio &n RF2:RF7(1) Control Signals Control 8 x 8 Multiply 3 8 BITOP W OOSSCC21//CCLLKKOI GeTnimeriantgion PoTwimere-rup 8 8 8 RGP0O:RRTGG4(1) 8 MHz INTOSC 8 8 Oscillator INTRC Start-up Timer ALU<8> Oscillator PORTH VUSB USB Power-on 8 RH0:RH7(1) Reset Module Precision Watchdog Band Gap Timer Reference PORTJ ENVREG Brown-out Voltage Reset(2) RJ0:RJ7(1) Regulator VDDCORE/VCAP VDD,VSS MCLR ADC 10-Bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators PMP ECCP1 ECCP2 ECCP3 CCP4 CCP5 EUSART1 EUSART2 MSSP1 MSSP2 USB Note 1: See Table1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. DS39775C-page 13

PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type 64-TQFP MCLR 7 I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OSC1/CLKI/RA7 39 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CLKI I CMOS Main oscillator input connection. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7(3) I/O TTL Main clock input connection. General purpose I/O pin. OSC2/CLKO/RA6 40 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — Main oscillator feedback output connection. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6(3) I/O TTL System cycle clock output (FOSC/4). General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39775C-page 14 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 64-TQFP PORTA is a bidirectional I/O port. RA0/AN0 24 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 23 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF- 22 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 21 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 28 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4/C2INA 27 RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. C2INA — Analog Comparator 2 input A RA6 — — — See the OSC2/CLKO/RA6 pin. RA7 — — — See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. DS39775C-page 15

PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 64-TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/FLT0/INT0 48 RB0 I/O TTL Digital I/O. FLT0 I ST ECCP1/2/3 Fault input. INT0 I ST External interrupt 0. RB1/INT1/PMA4 47 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. PMA4 O — Parallel Master Port address. RB2/INT2/PMA3 46 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. PMA3 O — Parallel Master Port address. RB3/INT3/PMA2 45 RB3 I/O TTL Digital I/O. INT3 I ST External interrupt 3. PMA2 O — Parallel Master Port address. RB4/KBI0/PMA1 44 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. PMA1 I/O — Parallel Master Port address. RB5/KBI1/PMA0 43 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PMA0 I/O — Parallel Master Port address. RB6/KBI2/PGC 42 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 37 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39775C-page 16 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 64-TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 30 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/ECCP2/P2A 29 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. ECCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A(1) O — ECCP2 PWM output A. RC2/ECCP1/P1A 33 RC2 I/O ST Digital I/O. ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O — ECCP1 PWM output A. RC3/SCK1/SCL1 34 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI1/SDA1 35 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O ST I2C data I/O. RC5/SDO1/C2OUT 36 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. C2OUT O TTL Comparator 2 output. RC6/TX1/CK1 31 RC6 I/O ST Digital I/O. TX1 O — EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1). RC7/RX1/DT1 32 RC7 I/O ST Digital I/O. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. DS39775C-page 17

PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 64-TQFP PORTD is a bidirectional I/O port. RD0/PMD0 58 RD0 I/O ST Digital I/O. PMD0 I/O TTL Parallel Master Port data. RD1/PMD1 55 RD1 I/O ST Digital I/O. PMD1 I/O TTL Parallel Master Port data. RD2/PMD2 54 RD2 I/O ST Digital I/O. PMD2 I/O TTL Parallel Master Port data. RD3/PMD3 53 RD3 I/O ST Digital I/O. PMD3 I/O TTL Parallel Master Port data. RD4/PMD4/SDO2 52 RD4 I/O ST Digital I/O. PMD4 I/O TTL Parallel Master Port data. SDO2 O — SPI data out. RD5/PMD5/SDI2/SDA2 51 RD5 I/O ST Digital I/O. PMD5 I/O TTL Parallel Master Port data. SDI2 I ST SPI data in. SDA2 I/O ST I2C™ data I/O. RD6/PMD6/SCK2/SCL2 50 RD6 I/O ST Digital I/O. PMD6 I/O TTL Parallel Master Port data. SCK2 I/O ST Synchronous serial clock input/output for SPI mode. SCL2 I/O ST Synchronous serial clock input/output for I2C mode. RD7/PMD7/SS2 49 RD7 I/O ST Digital I/O. PMD7 I/O TTL Parallel Master Port data. SS2 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39775C-page 18 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 64-TQFP PORTE is a bidirectional I/O port. RE0/PMRD/P2D 2 RE0 I/O ST Digital I/O. PMRD I/O — Parallel Master Port read strobe. P2D O — ECCP2 PWM output D. RE1/PMWR/P2C 1 RE1 I/O ST Digital I/O. PMWR I/O — Parallel Master Port write strobe. P2C O — ECCP2 PWM output C. RE2/PMBE/P2B 64 RE2 I/O ST Digital I/O. PMBE O — Parallel Master Port byte enable P2B O — ECCP2 PWM output B. RE3/PMA13/P3C/REFO 63 RE3 I/O ST Digital I/O. PMA13 O — Parallel Master Port address. P3C O — ECCP3 PWM output C. REFO O — Reference clock out. RE4/PMA12/P3B 62 RE4 I/O ST Digital I/O. PMA12 O — Parallel Master Port address. P3B O — ECCP3 PWM output B. RE5/PMA11/P1C 61 RE5 I/O ST Digital I/O. PMA11 O — Parallel Master Port address. P1C O — ECCP1 PWM output C. RE6/PMA10/P1B 60 RE6 I/O ST Digital I/O. PMA10 O — Parallel Master Port address. P1B O — ECCP1 PWM output B. RE7/PMA9/ECCP2/P2A 59 RE7 I/O ST Digital I/O. PMA9 O — Parallel Master Port address. ECCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A(2) O — ECCP2 PWM output A. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. DS39775C-page 19

PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 64-TQFP PORTF is a bidirectional I/O port. RF2/PMA5/AN7/C2INB 16 RF2 I/O ST Digital I/O. PMA5 O — Parallel Master Port address. AN7 I Analog Analog input 7. C2INB I Analog Comparator 2 input B. RF3/D- 15 RF3 I ST Digital input. D- I/O — USB differential minus line (input/output). RF4/D+ 14 RF4 I ST Digital input. D+ I/O — USB differential plus line (input/output). RF5/AN10/C1INB/CVREF 13 RF5 I ST Digital input. AN10 I Analog Analog input 10. C1INB I Analog Comparator 1 input B. CVREF O Analog Comparator reference voltage output. RF6/AN11/C1INA 12 RF6 I/O ST Digital I/O. AN11 I Analog Analog input 11. C1INA I Analog Comparator 1 input A. RF7/SS1/C1OUT 11 RF7 I/O ST Digital I/O. SS1 I TTL SPI slave select input. C1OUT O TTL Comparator 1 output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39775C-page 20 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 64-TQFP PORTG is a bidirectional I/O port. RG0/PMA8/ECCP3/P3A 3 RG0 I/O ST Digital I/O. PMA8 O — Parallel Master Port address. ECCP3 I/O — Capture 3 input/Compare 3 output/PWM3 output. P3A O — ECCP3 PWM output A. RG1/PMA7/TX2/CK2 4 RG1 I/O ST Digital I/O. PMA7 O — Parallel Master Port address. TX2 O — EUSART2 asynchronous transmit. CK2 I/O ST EUSART2 synchronous clock (see related RX2/DT2). RG2/PMA6/RX2/DT2 5 RG2 I/O ST Digital I/O. PMA6 O — Parallel Master Port address. RX2 I ST EUSART2 asynchronous receive. DT2 I/O ST EUSART2 synchronous data (see related TX2/CK2). RG3/PMCS1/CCP4/P3D 6 RG3 I/O ST Digital I/O. PMCS1 O — Parallel Master Port chip select 1. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM4 output. P3D O — ECCP3 PWM output D. RG4/PMCS2/CCP5/P1D 8 RG4 I/O ST Digital I/O. PMCS2 O — Parallel Master Port chip select 2. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM5 output. P1D O — ECCP1 PWM output D. VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins. VDD 26, 38, 57 P — Positive supply for peripheral digital logic and I/O pins. AVSS 20 P — Ground reference for analog modules. AVDD 19 P — Positive supply for analog modules. ENVREG 18 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP 10 Core logic power or external filter capacitor connection. VDDCORE P — Positive supply for microcontroller core logic (regulator disabled). VCAP P — External filter capacitor connection (regulator enabled). VUSB 17 P — USB voltage input pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. DS39775C-page 21

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP MCLR 9 I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OSC1/CLKI/RA7 49 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CLKI I CMOS Main oscillator input connection. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7(8) I/O TTL Main clock input connection. General purpose I/O pin. OSC2/CLKO/RA6 50 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — Main oscillator feedback output connection. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6(8) I/O TTL System cycle clock output (FOSC/4). General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39775C-page 22 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTA is a bidirectional I/O port. RA0/AN0 30 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 29 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF- 28 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 27 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/PMD5/T0CKI 34 RA4 I/O ST Digital I/O. PMD5(7) I/O TTL Parallel Master Port data. T0CKI I ST Timer0 external clock input. RA5/PMD4/AN4/C2INA 33 RA5 I/O TTL Digital I/O. PMD4(7) I/O TTL Parallel Master Port data. AN4 I Analog Analog input 4. C2INA I Analog Comparator 2 input A. RA6 — — — See the OSC2/CLKO/RA6 pin. RA7 — — — See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. DS39775C-page 23

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/FLT0/INT0 58 RB0 I/O TTL Digital I/O. FLT0 I ST ECCP1/2/3 Fault input. INT0 I ST External interrupt 0. RB1/INT1/PMA4 57 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. PMA4 O — Parallel Master Port address. RB2/INT2/PMA3 56 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. PMA3 O — Parallel Master Port address. RB3/INT3/ECCP2/ 55 P2A/PMA2 RB3 I/O TTL Digital I/O. INT3 I ST External interrupt 3. ECCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A(1) O — ECCP2 PWM output A. PMA2 O — Parallel Master Port address. RB4/KBI0/PMA1 54 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. PMA1 I/O — Parallel Master Port address. RB5/KBI1/PMA0 53 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PMA0 I/O — Parallel Master Port address. RB6/KBI2/PGC 52 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 47 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39775C-page 24 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 36 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/ECCP2/P2A 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. ECCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A(2) O — ECCP2 PWM output A. RC2/ECCP1/P1A 43 RC2 I/O ST Digital I/O. ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O — ECCP1 PWM output A. RC3/SCK1/SCL1 44 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI1/SDA1 45 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O ST I2C data I/O. RC5/SDO1/C2OUT 46 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. C2OUT O TTL Comparator 2 output. RC6/TX1/CK1 37 RC6 I/O ST Digital I/O. TX1 O — EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1). RC7/RX1/DT1 38 RC7 I/O ST Digital I/O. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. DS39775C-page 25

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTD is a bidirectional I/O port. RD0/AD0/PMD0 72 RD0 I/O ST Digital I/O. AD0 I/O TTL External memory address/data 0. PMD0(6) I/O TTL Parallel Master Port data. RD1/AD1/PMD1 69 RD1 I/O ST Digital I/O. AD1 I/O TTL External memory address/data 1. PMD1(6) I/O TTL Parallel Master Port data. RD2/AD2/PMD2 68 RD2 I/O ST Digital I/O. AD2 I/O TTL External memory address/data 2. PMD2(6) I/O TTL Parallel Master Port data. RD3/AD3/PMD3 67 RD3 I/O ST Digital I/O. AD3 I/O TTL External memory address/data 3. PMD3(6) I/O TTL Parallel Master Port data. RD4/AD4/PMD4/ 66 SDO2 RD4 I/O ST Digital I/O. AD4 I/O TTL External memory address/data 4. PMD4(6) I/O TTL Parallel Master Port data. SDO2 O — SPI data out. RD5/AD5/PMD5/ 65 SDI2/SDA2 RD5 I/O ST Digital I/O. AD5 I/O TTL External memory address/data 5. PMD5(6) I/O TTL Parallel Master Port data. SDI2 I ST SPI data in. SDA2 I/O ST I2C™ data I/O. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39775C-page 26 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTD is a bidirectional I/O port (continued). RD6/AD6/PMD6/ 64 SCK2/SCL2 RD6 I/O ST Digital I/O. AD6 I/O TTL External memory address/data 6. PMD6(6) I/O TTL Parallel Master Port data. SCK2 I/O ST Synchronous serial clock input/output for SPI mode. SCL2 I/O ST Synchronous serial clock input/output for I2C™ mode. RD7/AD7/PMD7/SS2 63 RD7 I/O ST Digital I/O. AD7 I/O TTL External memory address/data 7. PMD7(6) I/O TTL Parallel Master Port data. SS2 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. DS39775C-page 27

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTE is a bidirectional I/O port. RE0/AD8/PMRD/P2D 4 RE0 I/O ST Digital I/O. AD8 I/O TTL External memory address/data 8. PMRD(6) I/O — Parallel Master Port read strobe. P2D O — ECCP2 PWM output D. RE1/AD9/PMWR/P2C 3 RE1 I/O ST Digital I/O. AD9 I/O TTL External memory address/data 9. PMWR(6) I/O — Parallel Master Port write strobe. P2C O — ECCP2 PWM output C. RE2/AD10/PMBE/P2B 78 RE2 I/O ST Digital I/O. AD10 I/O TTL External memory address/data 10. PMBE(6) O — Parallel Master Port byte enable. P2B O — ECCP2 PWM output B. RE3/AD11/PMA13/ 77 P3C/REFO RE3 I/O ST Digital I/O. AD11 I/O TTL External memory address/data 11. PMA13 O — Parallel Master Port address. P3C(3) O — ECCP3 PWM output C. REFO O — Reference Clock out. RE4/AD12/PMA12/P3B 76 RE4 I/O ST Digital I/O. AD12 I/O TTL External memory address/data 12. PMA12 O — Parallel Master Port address. P3B(3) O — ECCP3 PWM output B. RE5/AD13/PMA11/P1C 75 RE5 I/O ST Digital I/O. AD13 I/O TTL External memory address/data 13. PMA11 O — Parallel Master Port address. P1C(3) O — ECCP1 PWM output C. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39775C-page 28 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTE is a bidirectional I/O port (continued). RE6/AD14/PMA10/P1B 74 RE6 I/O ST Digital I/O. AD14 I/O TTL External memory address/data 14. PMA10 O — Parallel Master Port address. P1B(3) O — ECCP1 PWM output B. RE7/AD15/PMA9/ 73 ECCP2/P2A RE7 I/O ST Digital I/O. AD15 I/O TTL External memory address/data 15. PMA9 O — Parallel Master Port address. ECCP2(4) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A(4) O — ECCP2 PWM output A. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. DS39775C-page 29

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTF is a bidirectional I/O port. RF2/PMA5/AN7/C2INB 18 RF2 I/O ST Digital I/O. PMA5 O — Parallel Master Port address. AN7 I Analog Analog input 7. C2INB I Analog Comparator 2 input B. RF3/D- 17 RF3 I/O ST Digital I/O. D- I/O — Analog input 8. RF4/D+ 16 RF4 I/O ST Digital I/O. D+ I/O — Analog input 9. RF5/PMD2/AN10/ 15 C1INB/CVREF RF5 I/O ST Digital I/O. PMD2(7) I/O TTL Parallel Master Port address. AN10 I Analog Analog input 10. C1INB I Analog Comparator 1 input B. CVREF O Analog Comparator reference voltage output. RF6/PMD1/AN11/C1INA 14 RF6 I/O ST Digital I/O. PMD1(7) I/O TTL Parallel Master Port address. AN11 I Analog Analog input 11. C1INA I Analog Comparator 1 input A. RF7/PMD0/SS1/C1OUT 13 RF7 I/O ST Digital I/O. PMD0(7) I/O TTL Parallel Master Port address. SS1 I TTL SPI slave select input. C1OUT O — Comparator 1 output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39775C-page 30 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTG is a bidirectional I/O port. RG0/PMA8/ECCP3/P3A 5 RG0 I/O ST Digital I/O. PMA8 O — Parallel Master Port address. ECCP3 I/O ST Capture 3 input/Compare 3 output/PWM3 output. P3A O — ECCP3 PWM output A. RG1/PMA7/TX2/CK2 6 RG1 I/O ST Digital I/O. PMA7 O — Parallel Master Port address. TX2 O — EUSART2 asynchronous transmit. CK2 I/O ST EUSART2 synchronous clock (see related RX2/DT2). RG2/PMA6/RX2/DT2 7 RG2 I/O ST Digital I/O. PMA6 I/O — Parallel Master Port address. RX2 I ST EUSART2 asynchronous receive. DT2 I/O ST EUSART2 synchronous data (see related TX2/CK2). RG3/PMCS1/CCP4/P3D 8 RG3 I/O ST Digital I/O. PMCS1 I/O — Parallel Master Port chip select 1. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM4 output. P3D O — ECCP3 PWM output D. RG4/PMCS2/CCP5/P1D 10 RG4 I/O ST Digital I/O. PMCS2 O — Parallel Master Port chip select 2. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM5 output. P1D O — ECCP1 PWM output D. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. DS39775C-page 31

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTH is a bidirectional I/O port. RH0/A16 79 RH0 I/O ST Digital I/O. A16 O TTL External memory address/data 16. RH1/A17 80 RH1 I/O ST Digital I/O. A17 O TTL External memory address/data 17. RH2/A18/PMD7 1 RH2 I/O ST Digital I/O. A18 O TTL External memory address/data 18. PMD7(7) I/O TTL Parallel Master Port data. RH3/A19/PMD6 2 RH3 I/O ST Digital I/O. A19 O TTL External memory address/data 19. PMD6(7) I/O TTL Parallel Master Port data. RH4/PMD3/AN12/ 22 P3C/C2INC RH4 I/O ST Digital I/O. PMD3(7) I/O TTL Parallel Master Port address. AN12 I Analog Analog input 12. P3C(5) O — ECCP3 PWM output C. C2INC I Analog Comparator 2 input C. RH5/PMBE/AN13/ 21 P3B/C2IND RH5 I/O ST Digital I/O. PMBE(7) O — Parallel Master Port byte enable. AN13 I Analog Analog input 13. P3B(5) O — ECCP3 PWM output B. C2IND I Analog Comparator 2 input D. RH6/PMRD/AN14/ 20 P1C/C1INC RH6 I/O ST Digital I/O. PMRD(7) I/O — Parallel Master Port read strobe. AN14 I Analog Analog input 14. P1C(5) O — ECCP1 PWM output C. C1INC I Analog Comparator 1 input C. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39775C-page 32 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTH is a bidirectional I/O port (continued). RH7/PMWR/AN15/P1B 19 RH7 I/O ST Digital I/O. PMWR(7) I/O — Parallel Master Port write strobe. AN15 I Analog Analog input 15. P1B(5) O — ECCP1 PWM output B. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. DS39775C-page 33

PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type 80-TQFP PORTJ is a bidirectional I/O port. RJ0/ALE 62 RJ0 I/O ST Digital I/O. ALE O — External memory address latch enable. RJ1/OE 61 RJ1 I/O ST Digital I/O. OE O — External memory output enable. RJ2/WRL 60 RJ2 I/O ST Digital I/O. WRL O — External memory write low control. RJ3/WRH 59 RJ3 I/O ST Digital I/O. WRH O — External memory write high control. RJ4/BA0 39 RJ4 I/O ST Digital I/O. BA0 O — External memory byte address 0 control. RJ5/CE 40 RJ5 I/O ST Digital I/O CE O — External memory chip enable control. RJ6/LB 41 RJ6 I/O ST Digital I/O. LB O — External memory low byte control. RJ7/UB 42 RJ7 I/O ST Digital I/O. UB O — External memory high byte control. VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins. VDD 32, 48, 71 P — Positive supply for peripheral digital logic and I/O pins. AVSS 26 P — Ground reference for analog modules. AVDD 25 P — Positive supply for analog modules. ENVREG 24 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP 12 Core logic power or external filter capacitor connection. VDDCORE P — Positive supply for microcontroller core logic (regulator disabled). VCAP P — External filter capacitor connection (regulator enabled). VUSB 23 P — USB voltage input pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39775C-page 34 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 2.0 OSCILLATOR TABLE 2-1: OSCILLATOR MODES CONFIGURATIONS Mode Description ECPLL External Clock Input mode, the PLL can 2.1 Overview be enabled or disabled, CLKO on RA6, apply external clock signal to RA7 Devices in the PIC18F87J10 family incorporate a EC External Clock Input mode, the PLL is different oscillator and microcontroller clock system always disabled, CLKO on RA6, apply than general purpose PIC18F devices. The addition of external clock signal to RA7 the USB module, with its unique requirements for a stable clock source, make it necessary to provide a HSPLL High-Speed Crystal/Resonator mode, separate clock source that is compliant with both USB PLL can be enabled or disabled, crystal/ resonator connected between RA6 and low-speed and full-speed specifications. RA7 The PIC18F87J50 family has additional prescalers and HS High-Speed Crystal/Resonator mode, postscalers which have been added to accommodate a PLL always disabled, crystal/resonator wide range of oscillator frequencies. An overview of the connected between RA6 and RA7 oscillator structure is shown in Figure2-1. INTOSCPLLO Internal Oscillator mode, PLL can be Other oscillator features used in PIC18 enhanced enabled or disabled, CLKO on RA6, port microcontrollers, such as the internal oscillator block function on RA7, the internal oscillator and clock switching, remain the same. They are block is used to derive both the primary discussed later in this chapter. clock source and the postscaled internal clock 2.1.1 OSCILLATOR CONTROL INTOSCPLL Internal Oscillator mode, PLL can be The operation of the oscillator in PIC18F87J10 family enabled or disabled, port function on devices is controlled through three Configuration regis- RA6 and RA7, the internal oscillator ters and two control registers. Configuration registers, block is used to derive both the primary CONFIG1L, CONFIG1H and CONFIG2L, select the clock source and the postscaled internal oscillator mode, PLL prescaler and CPU divider options. clock As Configuration bits, these are set when the device is INTOSCO Internal Oscillator mode, PLL is always programmed and left in that configuration until the disabled, CLKO on RA6, port function on device is reprogrammed. RA7, the output of the INTOSC postscaler serves as both the postscaled The OSCCON register (Register2-2) selects the Active internal clock and the primary clock Clock mode; it is primarily used in controlling clock source switching in power-managed modes. Its use is INTOSC Internal Oscillator mode, PLL is always discussed in Section2.4.1 “Oscillator Control disabled, port function on RA6 and RA7, Register”. the output of the INTOSC postscaler The OSCTUNE register (Register2-1) is used to trim serves as both the postscaled internal the INTOSC frequency source, as well as select the clock and the primary clock source low-frequency clock source that drives several special features. The OSCTUNE register is also used to activate or disable the PLL. Its use is described in Section2.2.5.1 “OSCTUNE Register”. 2.2 Oscillator Types PIC18F87J10 family devices can be operated in eight distinct oscillator modes. Users can program the FOSC2:FOSC0 Configuration bits to select one of the modes listed in Table2-1. For oscillator modes which produce a clock output, “CLKO”, on pin RA6, the output frequency will be one fourth of the peripheral clock frequency. The clock output will stop when in Sleep mode, but will continue during Idle mode (see Figure2-1). © 2009 Microchip Technology Inc. DS39775C-page 35

PIC18F87J50 FAMILY 2.2.1 OSCILLATOR MODES AND A network of MUXes, clock dividers and a fixed 96 MHz USB OPERATION output PLL have been provided which can be used to derive various microcontroller core and USB module Because of the unique requirements of the USB module, frequencies. The oscillator structure of the a different approach to clock operation is necessary. In PIC18F87J50 family of devices is best understood by order to use the USB module, a fixed 6MHz or 48 MHz referring to Figure2-1. clock must be internally provided to the USB module for operation in either Low-Speed or Full-Speed mode, respectively. The microcontroller core need not be clocked at the same frequency as the USB module. FIGURE 2-1: PIC18F87J50 FAMILY CLOCK DIAGRAM PLLDIV2:PLLDIV0 ÷ 12 000 er ÷ 10 001 Primary Oscillator PLL Prescal ÷÷÷÷÷÷ 654321 001111110011010101 4 MHz 9P6L ML(H1)z ÷ 2 48 MHz FSEN OSC2 FOSC2 1 USB Module Clock 1 1 OSC1 (Note 2) ÷ 8 10 Needs 48 MHz for FS Needs 6 MHz for LS 0 0 0 CPDIV1:CPDIV0 ÷ 4 11 PLLEN ÷ 6 er 00 CPDIV1:CPDIV0 d ÷ 3 vi 01 Di ÷ 2 U 10 P ÷ 1 C 11 FOSC2:FOSC1 Other PSroimuracrey( 4C)lock IDLE CPU 00 Secondary Oscillator 00 Timer1 Clock(3) Peripherals T1OSO 01 11 RA6 T1OSCEN Postscaled Internal Clock ÷ 4 T1OSI OSCCON<1:0> CLKO OSCCON<6:4> Enabled Modes 8 MHz 111 4 MHz OIsnBctleiolrlcnaktaolr caler 2 MHz 111001 8 MHz osts 1 MHz 100 P 500 kHz 8 MHz C 011 INTRC OS 250 kHz 010 31 kHz NT 125 kHz I 001 1 31 kHz 000 0 WDT, PWRT, FSCM OSCTUNE<7> and Two-Speed Start-up Note 1: The PLL requires a 4 MHz input and it produces a 96 MHz output. The PLL will not be available until the PLLEN bit in the OSCTUNE register is set. Once the PLLEN bit is set, the PLL requires up to 2 ms to lock. 2: In order to use the USB module in Full-Speed mode, this node must be run at 48 MHz. For Low-Speed mode, this node may be run at either 48 MHz or 24 MHz, but the CPDIV bits must be set such that the USB module is clocked at 6 MHz. 3: Selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the reference clock of Section2.5 “Reference Clock Output”) and PLL. 4: The USB module cannot be used to communicate unless the primary clock source is selected. DS39775C-page 36 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 2.2.2 CRYSTAL OSCILLATOR/CERAMIC TABLE 2-3: CAPACITOR SELECTION FOR RESONATORS CRYSTAL OSCILLATOR In HS and HSPLL Oscillator modes, a crystal or Typical Capacitor Values ceramic resonator is connected to the OSC1 and Crystal Tested: Osc Type OSC2 pins to establish oscillation. Figure2-2 shows Freq C1 C2 the pin connections. The oscillator design requires the use of a parallel cut HS 4 MHz 27 pF 27 pF crystal. 8 MHz 22 pF 22 pF Note: Use of a series cut crystal may give a fre- 20 MHz 15 pF 15 pF quency out of the crystal manufacturer’s Capacitor values are for design guidance only. specifications. These capacitors were tested with the crystals listed below for basic start-up and operation. These values FIGURE 2-2: CRYSTAL/CERAMIC are not optimized. RESONATOR OPERATION Different capacitor values may be required to produce (XT, HS OR HSPLL acceptable oscillator operation. The user should test CONFIGURATION) the performance of the oscillator over the expected C1(1) OSC1 VDD and temperature range for the application. See the notes following this table for additional To information. Internal XTAL RF(3) Logic Crystals Used: Sleep 4 MHz RS(2) C2(1) OSC2 PIC18F87J50 8 MHz 20 MHz Note 1: See Table2-2 and Table2-3 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT Note1: Higher capacitance increases the stability strip cut crystals. of oscillator but also increases the 3: RF varies with the oscillator mode chosen. start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any TABLE 2-2: CAPACITOR SELECTION FOR voltage, it may be necessary to use the CERAMIC RESONATORS HS mode or switch to a crystal oscillator. Typical Capacitor Values Used: 3: Since each resonator/crystal has its own characteristics, the user should consult Mode Freq OSC1 OSC2 the resonator/crystal manufacturer for HS 8.0 MHz 27 pF 27 pF appropriate values of external 16.0 MHz 22 pF 22 pF components. Capacitor values are for design guidance only. 4: Rs may be required to avoid overdriving These capacitors were tested with the resonators crystals with low drive level specification. listed below for basic start-up and operation. These 5: Always verify oscillator performance over values are not optimized. the VDD and temperature range that is Different capacitor values may be required to produce expected for the application. acceptable oscillator operation. The user should test An internal postscaler allows users to select a clock the performance of the oscillator over the expected frequency other than that of the crystal or resonator. VDD and temperature range for the application. Frequency division is determined by the CPDIV See the notes following Table2-3 for additional Configuration bits. Users may select a clock frequency information. of the oscillator frequency, or 1/2, 1/3 or 1/6 of the frequency. Resonators Used: An external clock may also be used when the micro- 4.0 MHz controller is in HS Oscillator mode. In this case, the 8.0 MHz OSC2/CLKO pin is left open (Figure2-3). 16.0 MHz © 2009 Microchip Technology Inc. DS39775C-page 37

PIC18F87J50 FAMILY FIGURE 2-3: EXTERNAL CLOCK INPUT There is also a CPU divider which can be used to derive OPERATION (HS OSC the microcontroller clock from the PLL. This allows the CONFIGURATION) USB peripheral and microcontroller to use the same oscillator input and still operate at different clock speeds. The CPU divider can reduce the incoming frequency by Clock from OSC1 a factor of 1, 2, 3 or 6. Ext. System PIC18F87J50 Open OSC2 (HS Mode) 2.2.5 INTERNAL OSCILLATOR BLOCK The PIC18F87J10 family devices include an internal oscillator block which generates two different clock sig- 2.2.3 EXTERNAL CLOCK INPUT nals; either can be used as the microcontroller’s clock source. The internal oscillator may eliminate the need The EC and ECPLL Oscillator modes require an exter- for external oscillator circuits on the OSC1 and/or nal clock source to be connected to the OSC1 pin. OSC2 pins. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. The main output (INTOSC) is an 8 MHz clock source which can be used to directly drive the device clock. It In the EC and ECPLL Oscillator modes, the oscillator also drives the INTOSC postscaler which can provide a frequency divided by 4 is available on the OSC2 pin. range of clock frequencies from 31 kHz to 8 MHz. This signal may be used for test purposes or to Additionally, the INTOSC may be used in conjunction synchronize other logic. Figure2-4 shows the pin with the PLL to generate clock frequencies up to connections for the EC Oscillator mode. 48MHz. FIGURE 2-4: EXTERNAL CLOCK INPUT The other clock source is the internal RC oscillator (INTRC) which provides a nominal 31 kHz output. OPERATION (EC AND INTRC is enabled if it is selected as the device clock ECPLL CONFIGURATION) source. It is also enabled automatically when any of the following are enabled: Clock from OSC1/CLKI • Power-up Timer Ext. System PIC18F87J50 • Fail-Safe Clock Monitor FOSC/4 OSC2/CLKO • Watchdog Timer • Two-Speed Start-up 2.2.4 PLL FREQUENCY MULTIPLIER These features are discussed in greater detail in Section25.0 “Special Features of the CPU”. PIC18F87J10 family devices include a Phase Locked Loop (PLL) circuit. This is provided specifically for USB The clock source frequency (INTOSC direct, INTRC applications with lower speed oscillators and can also direct or INTOSC postscaler) is selected by configuring be used as a microcontroller clock source. the IRCF bits of the OSCCON register (page44). The PLL can be enabled in HSPLL, ECPLL, INTOSCPLL and INTOSCPLLO Oscillator modes by setting the PLLEN bit (OSCTUNE<6>). It is designed to produce a fixed 96MHz reference clock from a fixed 4MHz input. The output can then be divided and used for both the USB and the microcontroller core clock. Because the PLL has a fixed frequency input and output, there are eight prescaling options to match the oscillator input frequency to the PLL. This prescaler allows the PLL to be used with crystals, res- onators and external clocks, which are integer multiple frequencies of 4 MHz. For example, a 12 MHz crystal could be used in a prescaler divide by three mode to drive the PLL. DS39775C-page 38 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 2.2.5.1 OSCTUNE Register 2.2.5.3 Compensating for INTOSC Drift The internal oscillator’s output has been calibrated at It is possible to adjust the INTOSC frequency by the factory but can be adjusted in the user’s applica- modifying the value in the OSCTUNE register. This has tion. This is done by writing to the OSCTUNE register no effect on the INTRC clock source frequency. (Register2-1). The tuning sensitivity is constant Tuning the INTOSC source requires knowing when to throughout the tuning range. make the adjustment, in which direction it should be When the OSCTUNE register is modified, the INTOSC made and in some cases, how large a change is and INTRC frequencies will begin shifting to the new needed. When using the EUSART, for example, an frequency. The INTRC clock will reach the new adjustment may be required when it begins to generate frequency within 8 clock cycles (approximately, framing errors or receives data with errors while in 8*32μs=256μs). The INTOSC clock will stabilize Asynchronous mode. Framing errors indicate that the within 1ms. Code execution continues during this shift. device clock frequency is too high; to adjust for this, There is no indication that the shift has occurred. decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may sug- The OSCTUNE register also contains the INTSRC bit. gest that the clock speed is too low; to compensate, The INTSRC bit allows users to select which internal increment OSCTUNE to increase the clock frequency. oscillator provides the clock source when the 31kHz frequency option is selected. This is covered in greater It is also possible to verify device clock speed against detail in Section2.4.1 “Oscillator Control Register”. a reference clock. Two timers may be used: one timer is clocked by the peripheral clock, while the other is The PLLEN bit, contained in the OSCTUNE register, clocked by a fixed reference source, such as the can be used to enable or disable the internal 96 MHz Timer1 oscillator. Both timers are cleared but the timer PLL when running in one of the PLL type oscillator clocked by the reference generates interrupts. When modes (e.g., INTOSCPLL). Oscillator modes that do an interrupt occurs, the internally clocked timer is read not contain “PLL” in their name cannot be used with and both timers are cleared. If the internally clocked the PLL. In these modes, the PLL is always disabled timer value is greater than expected, then the internal regardless of the setting of the PLLEN bit. oscillator block is running too fast. To adjust for this, When configured for one of the PLL enabled modes, decrement the OSCTUNE register. setting the PLLEN bit does not immediately switch the Finally, a CCP module can use free-running Timer1 (or device clock to the PLL output. The PLL requires up to Timer3), clocked by the internal oscillator block and an two milliseconds to start up and lock during which time external event with a known period (i.e., AC power the device continues to be clocked. Once the PLL out- put is ready, the microcontroller core will automatically frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use switch to the PLL derived frequency. later. When the second event causes a capture, the 2.2.5.2 Internal Oscillator Output Frequency time of the first event is subtracted from the time of the and Drift second event. Since the period of the external event is known, the time difference between events can be The internal oscillator block is calibrated at the factory calculated. to produce an INTOSC output frequency of 8.0MHz. However, this frequency may drift as VDD or tempera- If the measured time is much greater than the calcu- ture changes, which can affect the controller operation lated time, the internal oscillator block is running too in a variety of ways. fast; to compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated The low-frequency INTRC oscillator operates indepen- time, the internal oscillator block is running too slow; to dently of the INTOSC source. Any changes in INTOSC compensate, increment the OSCTUNE register. across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. © 2009 Microchip Technology Inc. DS39775C-page 39

PIC18F87J50 FAMILY REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock derived from 8MHz INTOSC source (divide-by-256 enabled) 0 = 31kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN: Frequency Multiplier Enable bit 1 = 96 MHz PLL is enabled 0 = 96 MHz PLL is disabled bit 5-0 TUN5:TUN0: Frequency Tuning bits 011111 = Maximum frequency 011110 • • • • • • 000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 • • • • 100000 = Minimum frequency 2.3 Oscillator Settings for USB way the clock dividers have been implemented in the PIC18F87J50 family, the microcontroller core must run When the PIC18F87J10 family is used for USB at 24 MHz in order for the USB module to get the 6MHz connectivity, a 6 MHz or 48 MHz clock must be clock needed for low-speed USB operation. Several provided to the USB module for operation in either clocking schemes could be used to meet these two Low-Speed or Full-Speed modes, respectively. This required conditions. See Table2-4 and Table2-5 for may require some forethought in selecting an oscillator possible combinations which can be used for frequency and programming the device. low-speed USB operation. The full range of possible oscillator configurations compatible with USB operation is shown in Table2-5. TABLE 2-4: CLOCK FOR LOW-SPEED USB 2.3.1 LOW-SPEED OPERATION Clock CPU The USB clock for Low-Speed mode is derived from the CPDIV<1:0> USB Clock Input Clock primary oscillator or from the 96 MHz PLL. In order to operate the USB module in Low-Speed mode, a 6MHz 48 24 <1, 1> 48/8 = 6 MHz clock must be provided to the USB module. Due to the 24 24 <1, 0> 24/4 = 6 MHz DS39775C-page 40 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 2-5: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION Input Oscillator PLL Division Clock Mode MCU Clock Division Microcontroller Frequency (PLLDIV2:PLLDIV0) (FOSC2:FOSC0) (CPDIV1:CPDIV0) Clock Frequency None (11) 48MHz ÷2 (10) 24MHz 48MHz N/A EC ÷3 (01) 16MHz ÷6 (00) 8MHz None (11) 48MHz ÷2 (10) 24MHz 48MHz ÷12 (000) ECPLL ÷3 (01) 16MHz ÷6 (00) 8MHz None (11) 48MHz ÷2 (10) 24MHz 40MHz ÷10 (001) ECPLL ÷3 (01) 16MHz ÷6 (00) 8MHz None (11) 48MHz ÷2 (10) 24MHz 24MHz ÷6 (010) HSPLL, ECPLL ÷3 (01) 16MHz ÷6 (00) 8MHz None (11) 24MHz ÷2 (10) 12MHz 24MHz N/A(1) EC, HS ÷3 (01) 8MHz ÷6 (00) 4MHz None (11) 48MHz ÷2 (10) 24MHz 20MHz ÷5 (011) HSPLL, ECPLL ÷3 (01) 16MHz ÷6 (00) 8MHz None (11) 48MHz ÷2 (10) 24MHz 16MHz ÷4 (100) HSPLL, ECPLL ÷3 (01) 16MHz ÷6 (00) 8MHz None (11) 48MHz ÷2 (10) 24MHz 12MHz ÷3 (101) HSPLL, ECPLL ÷3 (01) 16MHz ÷6 (00) 8MHz None (11) 48MHz ÷2 (10) 24MHz 8MHz ÷2 (110) HSPLL, ECPLL ÷3 (01) 16MHz ÷6 (00) 8MHz None (11) 48MHz ÷2 (10) 24MHz 4MHz ÷1 (111) HSPLL, ECPLL ÷3 (01) 16MHz ÷6 (00) 8MHz Legend: All clock frequencies, except 24MHz, are exclusively associated with full-speed USB operation (USB clock of 48MHz). Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24MHz, USB clock of 6MHz). Note 1: Only valid for low-speed USB operation. © 2009 Microchip Technology Inc. DS39775C-page 41

PIC18F87J50 FAMILY 2.4 Clock Sources and Oscillator 2.4.1 OSCILLATOR CONTROL REGISTER Switching The OSCCON register (Register2-2) controls several aspects of the device clock’s operation, both in Like previous PIC18 enhanced devices, the full-power operation and in power-managed modes. PIC18F87J10 family includes a feature that allows the device clock source to be switched from the main The System Clock Select bits, SCS1:SCS0, select the oscillator to an alternate, low-frequency clock source. clock source. The available clock sources are the PIC18F87J10 family devices offer two alternate clock primary clock (defined by the FOSC2:FOSC0 Configu- sources. When an alternate clock source is enabled, ration bits), the secondary clock (Timer1 oscillator) and the various power-managed operating modes are the postscaled internal clock.The clock source changes available. immediately, after one or more of the bits is written to, following a brief clock transition interval. The SCS bits Essentially, there are three clock sources for these are cleared on all forms of Reset. devices: The Internal Oscillator Frequency Select bits, • Primary oscillators IRCF2:IRCF0, select the frequency output provided on • Secondary oscillators the postscaled internal clock line. The choices are the • Internal oscillator block INTRC source, the INTOSC source (8MHz) or one of The primary clock sources include the External the frequencies derived from the INTOSC postscaler Crystal and Resonator modes, the External Clock (31kHz to 4MHz). If the postscaled internal clock is modes and the internal oscillator block. The particular supplying the device clock, changing the states of these mode is defined by the FOSC2:FOSC0 Configuration bits will have an immediate change on the internal oscil- bits. The details of these modes are covered earlier in lator’s output. On device Resets, the default output this chapter. frequency of the INTOSC postscaler is set at 4MHz. The secondary oscillators are those external sources When an output frequency of 31kHz is selected not connected to the OSC1 or OSC2 pins. These (IRCF2:IRCF0 = 000), users may choose which inter- sources may continue to operate even after the nal oscillator acts as the source. This is done with the controller is placed in a power-managed mode. INTSRC bit in the OSCTUNE register (OSCTUNE<7>). Setting this bit selects INTOSC as a 31.25kHz clock PIC18F87J10 family devices offer the Timer1 oscillator source by enabling the divide-by-256 output of the as a secondary oscillator. This oscillator, in all INTOSC postscaler. Clearing INTSRC selects INTRC power-managed modes, is often the time base for (nominally 31kHz) as the clock source. functions such as a Real-Time Clock (RTC). Most often, a 32.768kHz watch crystal is connected This option allows users to select the tunable and more between the RC0/T1OSO/T13CKI and RC1/T1OSI/ precise INTOSC as a clock source, while maintaining ECCP2/P2A pins. Like the HS Oscillator mode circuits, power savings with a very low clock speed. Regardless loading capacitors are also connected from each pin to of the setting of INTSRC, INTRC always remains the ground. The Timer1 oscillator is discussed in greater clock source for features such as the Watchdog Timer detail in Section13.3 “Timer1 Oscillator”. and the Fail-Safe Clock Monitor. In addition to being a primary clock source, the The OSTS and T1RUN bits indicate which clock source postscaled internal clock is available as a is currently providing the device clock. The OSTS bit power-managed mode clock source. The INTRC indicates that the Oscillator Start-up Timer (OST) has source is also used as the clock source for several timed out and the primary clock is providing the device special features, such as the WDT and Fail-Safe Clock clock in primary clock modes. The T1RUN bit Monitor. (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. The IDLEN bit determines if the device goes into Sleep mode, or one of the Idle modes, when the SLEEP instruction is executed. DS39775C-page 42 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY The use of the flag and control bits in the OSCCON 2.4.2 OSCILLATOR TRANSITIONS register is discussed in more detail in Section3.0 PIC18F87J10 family devices contain circuitry to “Power-Managed Modes”. prevent clock “glitches” when switching between clock Note 1: The Timer1 oscillator must be enabled to sources. A short pause in the device clock occurs dur- select the Timer1 clock. The Timer1 oscil- ing the clock switch. The length of this pause is the sum lator is enabled by setting the T1OSCEN of two cycles of the old clock source and three to four bit in the Timer1 Control register cycles of the new clock source. This formula assumes (T1CON<3>). If the Timer1 oscillator is not that the new clock source is stable. enabled, then any attempt to select the Clock transitions are discussed in greater detail in Timer1 clock source will be ignored. Section3.1.2 “Entering Power-Managed Modes”. 2: It is recommended that the Timer1 oscillator be operating and stable prior to switching to it as the clock source; other- wise, a very long delay may occur while the Timer1 oscillator starts. © 2009 Microchip Technology Inc. DS39775C-page 43

PIC18F87J50 FAMILY REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER(1) R/W-0 R/W-1 R/W-1 R/W-0 R-1(2) U-1 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS — SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8MHz (INTOSC drives clock directly) 110 = 4MHz(3) 101 = 2MHz 100 = 1MHz 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31kHz (from either INTOSC/256 or INTRC directly)(4) bit 3 OSTS: Oscillator Start-up Time-out Status bit(2) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready bit 2 Unimplemented: Read as ‘1’ bit 1-0 SCS1:SCS0: System Clock Select bits 11 = Postscaled internal clock (INTRC/INTOSC derived) 10 = Reserved 01 = Timer1 oscillator 00 = Primary clock source (INTOSC postscaler output when FOSC2:FOSC0 = 001 or 000) 00 = Primary clock source (CPU divider output for other values of FOSC2:FOSC0) Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 3: Default output frequency of INTOSC on Reset (4 MHz). 4: Source selected by the INTSRC bit (OSCTUNE<7>), see text. DS39775C-page 44 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 2.5 Reference Clock Output OSC1 and OSC2, or the current system clock source, is used for the reference clock output. The ROSSLP bit In addition to the peripheral clock/4 output in certain determines if the reference source is available on RE3 oscillator modes, the device clock in the PIC18F87J10 when the device is in Sleep mode. family can also be configured to provide a reference To use the reference clock output in Sleep mode, both clock output signal to a port pin. This feature is avail- the ROSSLP and ROSEL bits must be set. The device able in all oscillator configurations and allows the user clock must also be configured for an EC or HS mode; to select a greater range of clock submultiples to drive otherwise, the oscillator on OSC1 and OSC2 will be external devices in the application. powered down when the device enters Sleep mode. This reference clock output is controlled by the Clearing the ROSEL bit allows the reference output REFOCON register (Register2-3). Setting the ROON frequency to change as the system clock changes bit (REFOCON<7>) makes the clock signal available during any clock switches. on the REFO (RE3) pin. The RODIV3:RODIV0 bits The REFOCON register is an alternate SFR and enable the selection of 16 different clock divider shares the same memory address as the OSCCON options. register. It is accessed by setting the ADSHR bit The ROSSLP and ROSEL bits (REFOCON<5:4>) con- (WDTCON<4>) in the WDTCON register (see trol the availability of the reference output during Sleep Register25-9). mode. The ROSEL bit determines if the oscillator on REGISTER 2-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator enabled on REFO pin 0 = Reference oscillator disabled bit 6 Unimplemented: Read as ‘0’ bit 5 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 4 ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator used as the base clock. Note that the crystal oscillator must be enabled using the FOSC2:FOSC0 bits; crystal maintains the operation in Sleep mode. 0 = System clock used as the base clock; base clock reflects any clock switching of the device bit 3-0 RODIV3:RODIV0: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value © 2009 Microchip Technology Inc. DS39775C-page 45

PIC18F87J50 FAMILY 2.6 Effects of Power-Managed Modes Sleep mode should not be invoked while the USB mod- on the Various Clock Sources ule is enabled and operating in full-power mode. Before Sleep mode is selected, the USB module should be put When PRI_IDLE mode is selected, the designated in the suspend state. This is accomplished by setting primary oscillator continues to run without interruption. the SUSPND bit in the UCON register. For all other power-managed modes, the oscillator Enabling any on-chip feature that will operate during using the OSC1 pin is disabled. Unless the USB Sleep will increase the current consumed during Sleep. module is enabled, the OSC1 pin (and OSC2 pin if The INTRC is required to support WDT operation. The used by the oscillator) will stop oscillating. Timer1 oscillator may be operating to support a In secondary clock modes (SEC_RUN and Real-Time Clock. Other features may be operating that SEC_IDLE), the Timer1 oscillator is operating and do not require a device clock source (i.e., MSSP slave, providing the device clock. The Timer1 oscillator may PMP, INTx pins and others). Peripherals that may add also run in all power-managed modes if required to significant current consumption are listed in clock Timer1 or Timer3. Section28.2 “DC Characteristics: Power-Down and In internal oscillator modes (RC_RUN and RC_IDLE), Supply Current”. the internal oscillator block provides the device clock source. The 31kHz INTRC output can be used directly 2.7 Power-up Delays to provide the clock and may be enabled to support Power-up delays are controlled by two timers so that no various special features regardless of the external Reset circuitry is required for most applications. power-managed mode (see Section25.2 “Watchdog The delays ensure that the device is kept in Reset until Timer (WDT)”, Section25.4 “Two-Speed Start-up” the device power supply is stable under normal circum- and Section25.5 “Fail-Safe Clock Monitor” for more stances and the primary clock is operating and stable. information on WDT, Fail-Safe Clock Monitor and For additional information on power-up delays, see Two-Speed Start-up). The INTOSC output at 8MHz Section4.6 “Power-up Timer (PWRT)”. may be used directly to clock the device or may be divided down by the postscaler. The INTOSC output is The first timer is the Power-up Timer (PWRT), which disabled if the clock is provided directly from the INTRC provides a fixed delay on power-up (parameter 33, output. Table28-13). If the Sleep mode is selected, all clock sources which The second timer is the Oscillator Start-up Timer are no longer required are stopped. Since all the tran- (OST), intended to keep the chip in Reset until the sistor switching currents have been stopped, Sleep crystal oscillator is stable (HS mode). The OST does mode achieves the lowest current consumption of the this by counting 1024 oscillator cycles before allowing device (only leakage currents). the oscillator to clock the device. There is a delay of interval, TCSD (parameter 38, Table28-13), following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC or internal oscillator modes are used as the primary clock source. DS39775C-page 46 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 3.0 POWER-MANAGED MODES 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three The PIC18F87J10 family devices provide the ability to clock sources for power-managed modes. They are: manage power consumption by simply managing clock- ing to the CPU and the peripherals. In general, a lower • The primary clock source, as defined by the clock frequency and a reduction in the number of circuits FOSC2:FOSC0 Configuration bits being clocked constitutes lower consumed power. For • The Timer1 clock (provided by the secondary the sake of managing power in an application, there are oscillator) three primary modes of operation: • The postscaled internal clock (derived from the • Run mode internal oscillator block) • Idle mode 3.1.2 ENTERING POWER-MANAGED • Sleep mode MODES These modes define which portions of the device are Switching from one power-managed mode to another clocked and at what speed. The Run and Idle modes begins by loading the OSCCON register. The may use any of the three available clock sources SCS1:SCS0 bits select the clock source and determine (primary, secondary or internal oscillator block); the which Run or Idle mode is to be used. Changing these Sleep mode does not use a clock source. bits causes an immediate switch to the new clock The power-managed modes include several source, assuming that it is running. The switch may power-saving features offered on previous PIC® also be subject to clock transition delays. These are devices. One is the clock switching feature, offered in discussed in Section3.1.3 “Clock Transitions and other PIC18 devices, allowing the controller to use the Status Indicators” and subsequent sections. Timer1 oscillator in place of the primary oscillator. Also Entry to the power-managed Idle or Sleep modes is included is the Sleep mode, offered by all PIC devices, triggered by the execution of a SLEEP instruction. The where all device clocks are stopped. actual mode that results depends on the status of the IDLEN bit. 3.1 Selecting Power-Managed Modes Depending on the current mode and the mode being Selecting a power-managed mode requires two switched to, a change to a power-managed mode does decisions: if the CPU is to be clocked or not and which not always require setting all of these bits. Many clock source is to be used. The IDLEN bit transitions may be done by changing the oscillator (OSCCON<7>) controls CPU clocking, while the select bits, or changing the IDLEN bit, prior to issuing a SCS1:SCS0 bits (OSCCON<1:0>) select the clock SLEEP instruction. If the IDLEN bit is already source. The individual modes, bit settings, clock configured correctly, it may only be necessary to sources and affected modules are summarized in perform a SLEEP instruction to switch to the desired Table3-1. mode. TABLE 3-1: POWER-MANAGED MODES OSCCON<7,1:0> Module Clocking Mode Available Clock and Oscillator Source IDLEN(1) SCS1:SCS0 CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary clock source (defined by FOSC2:FOSC0); this is the normal full-power execution mode SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 oscillator RC_RUN N/A 11 Clocked Clocked Postscaled internal clock PRI_IDLE 1 00 Off Clocked Primary clock source (defined by FOSC2:FOSC0) SEC_IDLE 1 01 Off Clocked Secondary – Timer1 oscillator RC_IDLE 1 11 Off Clocked Postscaled internal clock Note 1: IDLEN reflects its value when the SLEEP instruction is executed. © 2009 Microchip Technology Inc. DS39775C-page 47

PIC18F87J50 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS 3.2 Run Modes INDICATORS In the Run modes, clocks to both the core and The length of the transition between clock sources is peripherals are active. The difference between these the sum of two cycles of the old clock source and three modes is the clock source. to four cycles of the new clock source. This formula assumes that the new clock source is stable. 3.2.1 PRI_RUN MODE Two bits indicate the current clock source and its The PRI_RUN mode is the normal, full-power execu- status: OSTS (OSCCON<3>) and T1RUN tion mode of the microcontroller. This is also the default (T1CON<6>). In general, only one of these bits will be mode upon a device Reset unless Two-Speed Start-up set while in a given power-managed mode. When the is enabled (see Section25.4 “Two-Speed Start-up” OSTS bit is set, the primary clock is providing the for details). In this mode, the OSTS bit is set. (see device clock. When the T1RUN bit is set, the Timer1 Section2.4.1 “Oscillator Control Register”). oscillator is providing the clock. If neither of these bits is set, INTRC is clocking the device. 3.2.2 SEC_RUN MODE Note: Executing a SLEEP instruction does not The SEC_RUN mode is the compatible mode to the necessarily place the device into Sleep “clock switching” feature offered in other PIC18 mode. It acts as the trigger to place the devices. In this mode, the CPU and peripherals are controller into either the Sleep mode, or clocked from the Timer1 oscillator. This gives users the one of the Idle modes, depending on the option of lower power consumption while still using a setting of the IDLEN bit. high-accuracy clock source. SEC_RUN mode is entered by setting the SCS1:SCS0 3.1.4 MULTIPLE SLEEP COMMANDS bits to ‘01’. The device clock source is switched to the The power-managed mode that is invoked with the Timer1 oscillator (see Figure3-1), the primary oscilla- SLEEP instruction is determined by the setting of the tor is shut down, the T1RUN bit (T1CON<6>) is set and IDLEN bit at the time the instruction is executed. If the OSTS bit is cleared. another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. DS39775C-page 48 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY On transitions from SEC_RUN mode to PRI_RUN Note: The Timer1 oscillator should already be mode, the peripherals and CPU continue to be clocked running prior to entering SEC_RUN mode. from the Timer1 oscillator while the primary clock is If the T1OSCEN bit is not set when the started. When the primary clock becomes ready, a SCS1:SCS0 bits are set to ‘01’, entry to clock switch back to the primary clock occurs (see SEC_RUN mode will not occur. If the Figure3-2). When the clock switch is complete, the Timer1 oscillator is enabled, but not yet T1RUN bit is cleared, the OSTS bit is set and the running, device clocks will be delayed until primary clock is providing the clock. The IDLEN and the oscillator has started. In such situa- SCS bits are not affected by the wake-up; the Timer1 tions, initial oscillator operation is far from oscillator continues to run. stable and unpredictable operation may result. FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS1:SCS0 Bits Changed OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. © 2009 Microchip Technology Inc. DS39775C-page 49

PIC18F87J50 FAMILY 3.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC In RC_RUN mode, the CPU and peripherals are block while the primary clock is started. When the clocked from the internal oscillator; the primary clock is primary clock becomes ready, a clock switch to the shut down. This mode provides the best power conser- primary clock occurs (see Figure3-4). When the clock vation of all the Run modes while still executing code. switch is complete, the OSTS bit is set and the primary It works well for user applications which are not highly clock is providing the device clock. The IDLEN and timing sensitive or do not require high-speed clocks at SCS bits are not affected by the switch. The INTRC all times. block source will continue to run if either the WDT or the This mode is entered by setting the SCS1:SCS0 bits Fail-Safe Clock Monitor is enabled. (OSCCON<1:0>) to ‘11’. When the clock source is switched to the internal oscillator block (see Figure3-3), the primary oscillator is shut down and the OSTS bit is cleared. FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS1:SCS0 Bits Changed OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS39775C-page 50 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 3.3 Sleep Mode 3.4 Idle Modes The power-managed Sleep mode is identical to the leg- The Idle modes allow the controller’s CPU to be acy Sleep mode offered in all other PIC devices. It is selectively shut down while the peripherals continue to entered by clearing the IDLEN bit (the default state on operate. Selecting a particular Idle mode allows users device Reset) and executing the SLEEP instruction. to further manage power consumption. This shuts down the selected oscillator (Figure3-5). All If the IDLEN bit is set to ‘1’ when a SLEEP instruction is clock source status bits are cleared. executed, the peripherals will be clocked from the clock Entering the Sleep mode from any other mode does not source selected using the SCS1:SCS0 bits; however, the require a clock switch. This is because no clocks are CPU will not be clocked. The clock source status bits are needed once the controller has entered Sleep. If the not affected. Setting IDLEN and executing a SLEEP WDT is selected, the INTRC source will continue to instruction provides a quick method of switching from a operate. If the Timer1 oscillator is enabled, it will also given Run mode to its corresponding Idle mode. continue to run. If the WDT is selected, the INTRC source will continue When a wake event occurs in Sleep mode (by interrupt, to operate. If the Timer1 oscillator is enabled, it will also Reset or WDT time-out), the device will not be clocked continue to run. until the clock source selected by the SCS1:SCS0 bits Since the CPU is not executing instructions, the only becomes ready (see Figure3-6), or it will be clocked exits from any of the Idle modes are by interrupt, WDT from the internal oscillator if either the Two-Speed time-out or a Reset. When a wake event occurs, CPU Start-up or the Fail-Safe Clock Monitor are enabled execution is delayed by an interval of TCSD (see Section25.0 “Special Features of the CPU”). In (parameter38, Table28-13) while it becomes ready to either case, the OSTS bit is set when the primary clock execute code. When the CPU begins executing code, is providing the device clocks. The IDLEN and SCS bits it resumes with the same clock source for the current are not affected by the wake-up. Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits. FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. © 2009 Microchip Technology Inc. DS39775C-page 51

PIC18F87J50 FAMILY 3.4.1 PRI_IDLE MODE 3.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes, in that it does not disable the primary device peripherals continue to be clocked from the Timer1 clock. For timing sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by set- the fastest resumption of device operation with its more ting the IDLEN bit and executing a SLEEP instruction. If accurate primary clock source, since the clock source the device is in another Run mode, set IDLEN first, then does not have to “warm up” or transition from another set SCS1:SCS0 to ‘01’ and execute SLEEP. When the oscillator. clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared PRI_IDLE mode is entered from PRI_RUN mode by and the T1RUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then set the SCS bits to ‘00’ and execute SLEEP. be clocked from the Timer1 oscillator. After an interval Although the CPU is disabled, the peripherals continue of TCSD following the wake event, the CPU begins exe- to be clocked from the primary clock source specified cuting code being clocked by the Timer1 oscillator. The by the FOSC1:FOSC0 Configuration bits. The OSTS IDLEN and SCS bits are not affected by the wake-up; bit remains set (see Figure3-7). the Timer1 oscillator continues to run (see Figure3-8). When a wake event occurs, the CPU is clocked from the Note: The Timer1 oscillator should already be primary clock source. A delay of interval TCSD is running prior to entering SEC_IDLE mode. required between the wake event and when code exe- If the T1OSCEN bit is not set when the cution starts. This is required to allow the CPU to SLEEP instruction is executed, the SLEEP become ready to execute instructions. After the instruction will be ignored and entry to wake-up, the OSTS bit remains set. The IDLEN and SEC_IDLE mode will not occur. If the SCS bits are not affected by the wake-up (see Timer1 oscillator is enabled, but not yet Figure3-8). running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event DS39775C-page 52 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 3.4.3 RC_IDLE MODE 3.5.2 EXIT BY WDT TIME-OUT In RC_IDLE mode, the CPU is disabled but the A WDT time-out will cause different actions depending peripherals continue to be clocked from the internal on which power-managed mode the device is in when oscillator block. This mode allows for controllable the time-out occurs. power conservation during Idle periods. If the device is not executing code (all Idle modes and From RC_RUN, this mode is entered by setting the Sleep mode), the time-out will result in an exit from the IDLEN bit and executing a SLEEP instruction. If the power-managed mode (see Section3.2 “Run device is in another Run mode, first set IDLEN, then Modes” and Section3.3 “Sleep Mode”). If the device clear the SCS bits and execute SLEEP. When the clock is executing code (all Run modes), the time-out will source is switched to the INTOSC block, the primary result in a WDT Reset (see Section25.2 “Watchdog oscillator is shut down and the OSTS bit is cleared. Timer (WDT)”). When a wake event occurs, the peripherals continue to The Watchdog Timer and postscaler are cleared by one be clocked from the internal oscillator block. After a of the following events: delay of TCSD following the wake event, the CPU • Executing a SLEEP or CLRWDT instruction begins executing code being clocked by the INTRC. • The loss of a currently selected clock source (if The IDLEN and SCS bits are not affected by the the Fail-Safe Clock Monitor is enabled) wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is 3.5.3 EXIT BY RESET enabled. Exiting an Idle or Sleep mode by Reset automatically 3.5 Exiting Idle and Sleep Modes forces the device to run from the INTRC. An exit from Sleep mode, or any of the Idle modes, is 3.5.4 EXIT WITHOUT AN OSCILLATOR triggered by an interrupt, a Reset or a WDT time-out. START-UP DELAY This section discusses the triggers that cause exits Certain exits from power-managed modes do not from power-managed modes. The clocking subsystem invoke the OST at all. There are two cases: actions are discussed in each of the power-managed • PRI_IDLE mode, where the primary clock source modes sections (see Section3.2 “Run Modes”, Section3.3 “Sleep Mode” and Section3.4 “Idle is not stopped; and Modes”). • the primary clock source is either the EC or ECPLL mode. 3.5.1 EXIT BY INTERRUPT In these instances, the primary clock source either Any of the available interrupt sources can cause the does not require an oscillator start-up delay, since it is device to exit from an Idle mode, or the Sleep mode, to already running (PRI_IDLE), or normally does not a Run mode. To enable this functionality, an interrupt require an oscillator start-up delay (EC). However, a source must be enabled by setting its enable bit in one fixed delay of interval, TCSD, following the wake event of the INTCON or PIE registers. The exit sequence is is still required when leaving Sleep and Idle modes to initiated when the corresponding interrupt flag bit is set. allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this On all exits from Idle or Sleep modes by interrupt, code delay. execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section9.0 “Interrupts”). A fixed delay of interval, TCSD, following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2009 Microchip Technology Inc. DS39775C-page 53

PIC18F87J50 FAMILY NOTES: DS39775C-page 54 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 4.0 RESET A simplified block diagram of the on-chip Reset circuit is shown in Figure4-1. The PIC18F87J10 family of devices differentiate between various kinds of Reset: 4.1 RCON Register a) Power-on Reset (POR) Device Reset events are tracked through the RCON b) MCLR Reset during normal operation register (Register4-1). The lower five bits of the c) MCLR Reset during power-managed modes register indicate that a specific Reset event has d) Watchdog Timer (WDT) Reset (during occurred. In most cases, these bits can only be set by execution) the event and must be cleared by the application after e) Configuration Mismatch (CM) the event. The state of these flag bits, taken together, f) Brown-out Reset (BOR) can be read to indicate the type of Reset that just occurred. This is described in more detail in g) RESET Instruction Section4.7 “Reset State of Registers”. h) Stack Full Reset The RCON register also has a control bit for setting i) Stack Underflow Reset interrupt priority (IPEN). Interrupt priority is discussed This section discusses Resets generated by MCLR, in Section9.0 “Interrupts”. POR and BOR, and covers the operation of the various start-up timers. Stack Reset events are covered in Section5.1.6.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section25.2 “Watchdog Timer (WDT)”. FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Configuration Word Mismatch Stack Stack Full/Underflow Reset Pointer External Reset MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset(1) S PWRT 32 μs PWRT 66 ms Chip_Reset R Q INTRC 11-Bit Ripple Counter Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to function properly. © 2009 Microchip Technology Inc. DS39775C-page 55

PIC18F87J50 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0’ bit 5 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration Mismatch Reset occurs) bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. 2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section4.4.1 “Detecting BOR” for more information. 3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39775C-page 56 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 4.2 Master Clear (MCLR) FIGURE 4-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering a hard SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path VDD VDD which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, D R R1 including the WDT. MCLR 4.3 Power-on Reset (POR) C PIC18F87J50 A Power-on Reset condition is generated on-chip whenever VDD rises above a certain threshold. This Note 1: External Power-on Reset circuit is required allows the device to start in the initialized state when only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor VDD is adequate for operation. quickly when VDD powers down. To take advantage of the POR circuitry, tie the MCLR 2: R < 40kΩ is recommended to make sure that pin through a resistor (1kΩ to 10kΩ) to VDD. This will the voltage drop across R does not violate eliminate external RC components usually needed to the device’s electrical specification. create a Power-on Reset delay. A minimum rise rate for 3: R1 ≥ 1 kΩ will limit any current flowing into VDD is specified (parameter D004). For a slow rise MCLR from external capacitor C, in the event time, see Figure4-2. of MCLR/VPP pin breakdown, due to When the device starts normal operation (i.e., exits the Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the 4.4.1 DETECTING BOR device must be held in Reset until the operating The BOR bit always resets to ‘0’ on any Brown-out conditions are met. Reset or Power-on Reset event. This makes it difficult POR events are captured by the POR bit (RCON<1>). to determine if a Brown-out Reset event has occurred The state of the bit is set to ‘0’ whenever a Power-on just by reading the state of BOR alone. A more reliable Reset occurs; it does not change for any other Reset method is to simultaneously check the state of both event. POR is not reset to ‘1’ by any hardware event. POR and BOR. This assumes that the POR bit is reset To capture multiple events, the user manually resets to ‘1’ in software immediately after any Power-on Reset the bit to ‘1’ in software following any Power-on Reset. event. If BOR is ‘0’ while POR is ‘1’, it can be reliably assumed that a Brown-out Reset event has occurred. 4.4 Brown-out Reset (BOR) If the voltage regulator is disabled, Brown-out Reset functionality is disabled. In this case, the BOR bit The PIC18F87J10 family of devices incorporates a cannot be used to determine a Brown-out Reset event. simple BOR function when the internal regulator is The BOR bit is still cleared by a Power-on Reset event. enabled (ENVREG pin is tied to VDD). Any drop of VDD below VBOR (parameterD005) for greater than time 4.5 Configuration Mismatch (CM) TBOR (parameter 35) will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than The Configuration Mismatch (CM) Reset is designed to TBOR. The chip will remain in Brown-out Reset until detect and attempt to recover from random, memory VDD rises above VBOR. corrupting events. These include Electrostatic Once a BOR has occurred, the Power-up Timer will Discharge (ESD) events, which can cause widespread keep the chip in Reset for TPWRT (parameter33). If single-bit changes throughout the device, and result in VDD drops below VBOR while the Power-up Timer is catastrophic failure. running, the chip will go back into a Brown-out Reset In PIC18FXXJ Flash devices, the device Configuration and the Power-up Timer will be initialized. Once VDD registers (located in the configuration memory space) rises above VBOR, the Power-up Timer will execute the are continuously monitored during operation by com- additional time delay. paring their values to complimentary shadow registers. If a mismatch is detected between the two sets of registers, a CM Reset automatically occurs. These events are captured by the CM bit (RCON<5>). The state of the bit is set to ‘0’ whenever a CM event occurs; it does not change for any other Reset event. © 2009 Microchip Technology Inc. DS39775C-page 57

PIC18F87J50 FAMILY A CM Reset behaves similarly to a Master Clear Reset, The power-up time delay depends on the INTRC clock RESET instruction, WDT time-out or Stack Event and will vary from chip-to-chip due to temperature and Resets. As with all hard and power Reset events, the process variation. See DC parameter33 for details. device Configuration Words are reloaded from the Flash Configuration Words in program memory as the 4.6.1 TIME-OUT SEQUENCE device restarts. The PWRT time-out is invoked after the POR pulse has cleared. The total time-out will vary based on the status 4.6 Power-up Timer (PWRT) of the PWRT. Figure4-3, Figure4-4, Figure4-5 and Figure4-6 all depict time-out sequences on power-up PIC18F87J10 family devices incorporate an on-chip with the Power-up Timer. Power-up Timer (PWRT) to help regulate the Power-on Reset process. The PWRT is always enabled. The Since the time-outs occur from the POR pulse, if MCLR main function is to ensure that the device voltage is is kept low long enough, the PWRT will expire. Bringing stable before code is executed. MCLR high will begin execution immediately if a clock source is available (Figure4-5). This is useful for The Power-up Timer (PWRT) of the PIC18F87J10 fam- testing purposes, or to synchronize more than one ily devices is an 11-bit counter which uses the INTRC PIC18FXXXX device operating in parallel. source as the clock input. This yields an approximate time interval of 2048x32μs=66ms. While the PWRT is counting, the device is held in Reset. FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET DS39775C-page 58 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. DS39775C-page 59

PIC18F87J50 FAMILY 4.7 Reset State of Registers different Reset situations, as indicated in Table4-1. These bits are used in software to determine the nature Most registers are unaffected by a Reset. Their status of the Reset. is unknown on POR and unchanged by all other Table4-2 describes the Reset states for all of the Resets. The other registers are forced to a “Reset Special Function Registers. These are categorized by state” depending on the type of Reset that occurred. Power-on and Brown-out Resets, Master Clear and Most registers are not affected by a WDT wake-up, WDT Resets and WDT wake-ups. since this is viewed as the resumption of normal operation. Status bits from the RCON register (CM, RI, TO, PD, POR and BOR) are set or cleared differently in TABLE 4-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter(1) CM RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET instruction 0000h u 0 u u u u u u Brown-out Reset 0000h 1 1 1 1 u 0 u u Configuration Mismatch Reset 0000h 0 u u u u u u u MCLR Reset during 0000h u u 1 u u u u u power-managed Run modes MCLR Reset during 0000h u u 1 0 u u u u power-managed Idle modes and Sleep mode MCLR Reset during full-power 0000h u u u u u u u u execution Stack Full Reset (STVREN = 1) 0000h u u u u u u 1 u Stack Underflow Reset 0000h u u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u u u u u u u 1 actual Reset, STVREN = 0) WDT time-out during full-power 0000h u u 0 u u u u u or power-managed Run modes WDT time-out during PC + 2 u u 0 0 u u u u power-managed Idle or Sleep modes Interrupt exit from PC + 2 u u u 0 u u u u power-managed modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). DS39775C-page 60 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets WDT Reset Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Brown-out Reset or Interrupt Stack Resets CM Resets TOSU Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---0 uuuu(1) TOSH Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu(1) TOSL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu(1) STKPTR Feature1 PIC18F8XJ5X 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu PCLATH Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PCL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 PC + 2(2) TBLPTRU Feature1 PIC18F8XJ5X --00 0000 --00 0000 --uu uuuu TBLPTRH Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu TBLPTRL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu TABLAT Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PRODH Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu PRODL Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu INTCON Feature1 PIC18F8XJ5X 0000 000x 0000 000u uuuu uuuu(3) INTCON2 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu(3) INTCON3 Feature1 PIC18F8XJ5X 1100 0000 1100 0000 uuuu uuuu(3) INDF0 Feature1 PIC18F8XJ5X N/A N/A N/A POSTINC0 Feature1 PIC18F8XJ5X N/A N/A N/A POSTDEC0 Feature1 PIC18F8XJ5X N/A N/A N/A PREINC0 Feature1 PIC18F8XJ5X N/A N/A N/A PLUSW0 Feature1 PIC18F8XJ5X N/A N/A N/A FSR0H Feature1 PIC18F8XJ5X ---- xxxx ---- uuuu ---- uuuu FSR0L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu WREG Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu INDF1 Feature1 PIC18F8XJ5X N/A N/A N/A POSTINC1 Feature1 PIC18F8XJ5X N/A N/A N/A POSTDEC1 Feature1 PIC18F8XJ5X N/A N/A N/A PREINC1 Feature1 PIC18F8XJ5X N/A N/A N/A PLUSW1 Feature1 PIC18F8XJ5X N/A N/A N/A FSR1H Feature1 PIC18F8XJ5X ---- xxxx ---- uuuu ---- uuuu FSR1L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu BSR Feature1 PIC18F8XJ5X ---- 0000 ---- 0000 ---- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. DS39775C-page 61

PIC18F87J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets WDT Reset Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Brown-out Reset or Interrupt Stack Resets CM Resets INDF2 Feature1 PIC18F8XJ5X N/A N/A N/A POSTINC2 Feature1 PIC18F8XJ5X N/A N/A N/A POSTDEC2 Feature1 PIC18F8XJ5X N/A N/A N/A PREINC2 Feature1 PIC18F8XJ5X N/A N/A N/A PLUSW2 Feature1 PIC18F8XJ5X N/A N/A N/A FSR2H Feature1 PIC18F8XJ5X ---- xxxx ---- uuuu ---- uuuu FSR2L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu STATUS Feature1 PIC18F8XJ5X ---x xxxx ---u uuuu ---u uuuu TMR0H Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu TMR0L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu T0CON Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu OSCCON Feature1 PIC18F8XJ5X 0110 q100 0110 q100 0110 q10u REFOCON Feature1 PIC18F8XJ5X 0-00 0000 u-uu uuuu u-uu uuuu CM1CON Feature1 PIC18F8XJ5X 0001 1111 uuuu uuuu uuuu uuuu CM2CON Feature1 PIC18F8XJ5X 0001 1111 uuuu uuuu uuuu uuuu RCON(4) Feature1 PIC18F8XJ5X 0-11 1100 0-qq qquu u-qq qquu TMR1H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu ODCON1 Feature1 PIC18F8XJ5X ---0 0000 ---u uuuu ---u uuuu TMR1L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu ODCON2 Feature1 PIC18F8XJ5X ---- --00 ---- --uu ---- --uu T1CON Feature1 PIC18F8XJ5X 0000 0000 u0uu uuuu uuuu uuuu ODCON3 Feature1 PIC18F8XJ5X ---- --00 ---- --uu ---- --uu TMR2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PADCFG1 Feature1 PIC18F8XJ5X ---- ---0 ---- ---u ---- ---u PR2 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 1111 1111 MEMCON Feature1 PIC18F8XJ5X 0-00 --00 0-00 --00 u-uu --uu T2CON Feature1 PIC18F8XJ5X -000 0000 -000 0000 -uuu uuuu SSP1BUF Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu SSP1ADD Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu SSP1MSK Feature1 PIC18F8XJ5X 1111 1111 uuuu uuuu uuuu uuuu SSP1STAT Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu SSP1CON1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu SSP1CON2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table4-1 for Reset value for specific condition. DS39775C-page 62 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets WDT Reset Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Brown-out Reset or Interrupt Stack Resets CM Resets ADRESH Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu ADRESL Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu ADCON1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu ANCON0 Feature1 PIC18F8XJ5X 0--0 0000 u--u uuuu u--u uuuu ANCON1 Feature1 PIC18F8XJ5X 0000 00-- uuuu uu-- uuuu uu-- WDTCON Feature1 PIC18F8XJ5X 0x-0 ---0 0x-u ---0 ux-u ---u ECCP1AS Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu ECCP1DEL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu CCPR1H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu ECCP2AS Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu ECCP2DEL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu CCPR2H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu ECCP3AS Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu ECCP3DEL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu CCPR3H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu CCPR3L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu CCP3CON Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu SPBRG1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu RCREG1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu TXREG1 Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu TXSTA1 Feature1 PIC18F8XJ5X 0000 0010 0000 0010 uuuu uuuu RCSTA1 Feature1 PIC18F8XJ5X 0000 000x 0000 000x uuuu uuuu SPBRG2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu RCREG2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu TXREG2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu TXSTA2 Feature1 PIC18F8XJ5X 0000 0010 0000 0010 uuuu uuuu EECON2 Feature1 PIC18F8XJ5X ---- ---- ---- ---- ---- ---- EECON1 Feature1 PIC18F8XJ5X --00 x00- --00 u00- --00 u00- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. DS39775C-page 63

PIC18F87J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets WDT Reset Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Brown-out Reset or Interrupt Stack Resets CM Resets IPR3 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu PIR3 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu(3) PIE3 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu IPR2 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu PIR2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu(3) PIE2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu IPR1 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu PIR1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu(3) PIE1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu RCSTA2 Feature1 PIC18F8XJ5X 0000 000x 0000 000x uuuu uuuu OSCTUNE Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu TRISJ Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu TRISH Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu TRISG Feature1 PIC18F8XJ5X ---1 1111 ---1 1111 ---u uuuu TRISF Feature1 PIC18F8XJ5X 111- -1-- 111- -1-- uuu- -u-- TRISE Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu TRISD Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu TRISC Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu TRISB Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu TRISA Feature1 PIC18F8XJ5X --11 1111 --11 1111 --uu uuuu LATJ Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu LATH Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu LATG Feature1 PIC18F8XJ5X ---x xxxx ---u uuuu ---u uuuu LATF Feature1 PIC18F8XJ5X xxxx xx-- uuuu uu-- uuuu uu-- LATE Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu LATD Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu LATC Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu LATB Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu LATA Feature1 PIC18F8XJ5X --xx xxxx --uu uuuu --uu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table4-1 for Reset value for specific condition. DS39775C-page 64 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets WDT Reset Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Brown-out Reset or Interrupt Stack Resets CM Resets PORTJ Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu PORTH Feature1 PIC18F8XJ5X 0000 xxxx uuuu uuuu uuuu uuuu PORTG Feature1 PIC18F8XJ5X 000x xxxx 000u uuuu uuuu uuuu PORTF Feature1 PIC18F8XJ5X x00x x0-- u00u u0-- u00u u0-- PORTE Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu PORTD Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu PORTC Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu PORTB Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu PORTA Feature1 PIC18F8XJ5X --0x 0000 --0u 0000 --uu uuuu SPBRGH1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu BAUDCON1 Feature1 PIC18F8XJ5X 0100 0-00 0100 0-00 uuuu u-uu SPBRGH2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu BAUDCON2 Feature1 PIC18F8XJ5X 0100 0-00 0100 0-00 uuuu u-uu TMR3H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu TMR3L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu T3CON Feature1 PIC18F8XJ5X 0000 0000 uuuu uuuu uuuu uuuu TMR4 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PR4 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 1111 1111 CVRCON Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu T4CON Feature1 PIC18F8XJ5X -000 0000 -000 0000 -uuu uuuu CCPR4H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu CCPR4L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu CCP4CON Feature1 PIC18F8XJ5X --00 0000 --00 0000 --uu uuuu CCPR5H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu CCPR5L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu CCP5CON Feature1 PIC18F8XJ5X --00 0000 --00 0000 --uu uuuu SSP2BUF Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu SSP2ADD Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu SSP2MSK Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu SSP2STAT Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu SSP2CON1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu SSP2CON2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu CMSTAT Feature1 PIC18F8XJ5X ---- --11 ---- --11 ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. DS39775C-page 65

PIC18F87J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets WDT Reset Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Brown-out Reset or Interrupt Stack Resets CM Resets PMADDRH Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDOUT1H Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMADDRL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDOUT1L Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDIN1H Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDIN1L Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu UCON Feature1 PIC18F8XJ5X -0x0 000- -0x0 000- -uuu uuu- USTAT Feature1 PIC18F8XJ5X -xxx xxx- -xxx xxx- -uuu uuu- UEIR Feature1 PIC18F8XJ5X 0--0 0000 0--0 0000 u--u uuuu UIR Feature1 PIC18F8XJ5X -000 0000 -000 0000 -uuu uuuu UFRMH Feature1 PIC18F8XJ5X ---- -xxx ---- -xxx ---- -uuu UFRML Feature1 PIC18F8XJ5X xxxx xxxx xxxx xxxx uuuu uuuu UCFG Feature1 PIC18F8XJ5X 00-0 0000 00-0 0000 uu-u uuuu UADDR Feature1 PIC18F8XJ5X -000 0000 -uuu uuuu -uuu uuuu UEIE Feature1 PIC18F8XJ5X 0--0 0000 0--0 0000 u--u uuuu UIE Feature1 PIC18F8XJ5X -000 0000 -000 0000 -uuu uuuu UEP15 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP14 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP13 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP12 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP11 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP10 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP9 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP8 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP7 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP6 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP5 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP4 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP3 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP2 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP1 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu UEP0 Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu PMCONH Feature1 PIC18F8XJ5X 0-00 0000 0-00 0000 u-uu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table4-1 for Reset value for specific condition. DS39775C-page 66 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets WDT Reset Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Brown-out Reset or Interrupt Stack Resets CM Resets PMCONL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMMODEH Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMMODEL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDOUT2H Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDOUT2L Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDIN2H Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDIN2L Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMEH Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMEL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMSTATH Feature1 PIC18F8XJ5X 00-- 0000 00-- 0000 uu-- uuuu PMSTATL Feature1 PIC18F8XJ5X 10-- 1111 10-- 1111 uu-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. DS39775C-page 67

PIC18F87J50 FAMILY NOTES: DS39775C-page 68 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 5.0 MEMORY ORGANIZATION 5.1 Program Memory Organization There are two types of memory in PIC18 Flash PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address will return all ‘0’s (a As Harvard architecture devices, the data and program NOP instruction). memories use separate busses; this allows for The entire PIC18F87J10 family offers a range of concurrent access of the two memory spaces. on-chip Flash program memory sizes, from 64Kbytes Additional detailed information on the operation of the (up to 16,384 single-word instructions) to 128Kbytes Flash program memory is provided in Section6.0 (65,536 single-word instructions). The program “Flash Program Memory”. memory maps for individual family members are shown in Figure5-3. FIGURE 5-1: MEMORY MAPS FOR PIC18F87J50 FAMILY DEVICES PC<20:0> 21 CALL, CALLW, RCALL, RETURN, RETFIE, RETLW, ADDULNK, SUBULNK Stack Level 1 • • • Stack Level 31 PIC18FX5J50 PIC18FX6J50 PIC18FX6J55 PIC18FX7J50 000000h On-Chip On-Chip On-Chip On-Chip Memory Memory Memory Memory Config. Words 007FFFh Config. Words 00FFFFh Config. Words e 017FFFh c a p S y or m e M Config. Words 01FFFFh er s U Unimplemented Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 1FFFFFF Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. © 2009 Microchip Technology Inc. DS39775C-page 69

PIC18F87J50 FAMILY 5.1.1 HARD MEMORY VECTORS 5.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded Because PIC18F87J10 family devices do not have per- return vectors in their program memory space. The sistent configuration memory, the top four words of Reset vector address is the default value to which the on-chip program memory are reserved for configuration program counter returns on all device Resets; it is information. On Reset, the configuration information is located at 0000h. copied into the Configuration registers. PIC18 devices also have two interrupt vector The Configuration Words are stored in their program addresses for the handling of high-priority and memory location in numerical order, starting with the low-priority interrupts. The high-priority interrupt vector lower byte of CONFIG1 at the lowest address and end- is located at 0008h and the low-priority interrupt vector ing with the upper byte of CONFIG4. For these devices, is at 0018h. Their locations in relation to the program only Configuration Words, CONFIG1 through memory map are shown in Figure5-2. CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Word for devices FIGURE 5-2: HARD VECTOR AND in the PIC18F87J10 family are shown in Table5-1. CONFIGURATION WORD Their location in the memory map is shown with the LOCATIONS FOR other memory vectors in Figure5-2. PIC18F87J50 FAMILY Additional details on the device Configuration Words DEVICES are provided in Section25.1 “Configuration Bits”. TABLE 5-1: FLASH CONFIGURATION Reset Vector 0000h WORD FOR PIC18F87J50 High-Priority Interrupt Vector 0008h FAMILY DEVICES Low-Priority Interrupt Vector 0018h Program Configuration Device Memory Word (Kbytes) Addresses PIC18F65J50 On-Chip 32 7FF8h to 7FFFh PIC18F85J50 Program Memory PIC18F66J50 64 FFF8h to FFFFh PIC18F86J50 PIC18F66J55 17FF8h to 96 PIC18F86J55 17FFFh PIC18F67J50 1FFF8h to Flash Configuration Words (Top of Memory-7) 128 (Top of Memory) PIC18F87J50 1FFFFh Read as ‘0’ 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure5-1 for device-specific values). Shaded area represents unimplemented memory. Areas are not shown to scale. DS39775C-page 70 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 5.1.3 PIC18F87J50 FAMILY PROGRAM The Microcontroller mode is also the only operating MEMORY MODES mode available to 64-pin devices. • The Extended Microcontroller Mode allows The 80-pin devices in this family can address up to a access to both internal and external program total of 2Mbytes of program memory. This is achieved memories as a single block. The device can through the External Memory Bus. There are two access its entire on-chip program memory; above distinct operating modes available to the controllers: this, the device accesses external program • Microcontroller (MC) memory up to the 2-Mbyte program space limit. • Extended Microcontroller (EMC) Execution automatically switches between the The program memory mode is determined by setting two memories as required. the EMB Configuration bits (CONFIG3L<5:4>), as The setting of the EMB Configuration bits also controls shown in Register5-1. (See also Section25.1 the address bus width of the External Memory Bus. “Configuration Bits” for additional details on the This is covered in more detail in Section7.0 “External device Configuration bits.) Memory Bus”. The program memory modes operate as follows: In all modes, the microcontroller has complete access • The Microcontroller Mode accesses only on-chip to data RAM. Flash memory. Attempts to read above the top of Figure5-3 compares the memory maps of the different on-chip memory causes a read of all ‘0’s (a NOP program memory modes. The differences between instruction). on-chip and external memory access limitations are more fully explained in Table5-2. REGISTER 5-1: CONFIG3L: CONFIGURATION REGISTER 3 LOW R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 WAIT(1) BW(1) EMB1(1) EMB0(1) EASHFT(1) — — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states on the external bus are disabled 0 = Wait states on the external bus are enabled and selected by MEMCON<5:4> bit 6 BW: Data Bus Width Select bit(1) 1 = 16-Bit Data Width modes 0 = 8-Bit Data Width modes bit 5-4 EMB1:EMB0: External Memory Bus Configuration bits(1) 11 = Microcontroller mode, external bus disabled 10 = Extended Microcontroller mode, 12-bit address width for external bus 01 = Extended Microcontroller mode, 16-bit address width for external bus 00 = Extended Microcontroller mode, 20-bit address width for external bus bit 3 EASHFT: External Address Bus Shift Enable bit(1) 1 = Address shifting enabled – external address bus is shifted to start at 000000h 0 = Address shifting disabled – external address bus reflects the PC value bit 2-0 Unimplemented: Read as ‘0’ Note 1: Implemented only on 80-pin devices. © 2009 Microchip Technology Inc. DS39775C-page 71

PIC18F87J50 FAMILY 5.1.4 EXTENDED MICROCONTROLLER To avoid this, the Extended Microcontroller mode MODE AND ADDRESS SHIFTING implements an address shifting option to enable auto- matic address translation. In this mode, addresses By default, devices in Extended Microcontroller mode presented on the external bus are shifted down by the directly present the program counter value on the size of the on-chip program memory and are remapped external address bus for those addresses in the range to start at 0000h. This allows the complete use of the of the external memory space. In practical terms, this external memory device’s memory space. means addresses in the external memory device below the top of on-chip memory are unavailable. FIGURE 5-3: MEMORY MAPS FOR PIC18F87J50 FAMILY PROGRAM MEMORY MODES Microcontroller Mode(1) Extended Microcontroller Mode(2) Extended Microcontroller Mode with Address Shifting(2) On-Chip External On-Chip External On-Chip Memory Memory Memory Memory Memory Space Space Space Space Space 000000h 000000h 000000h On-Chip On-Chip On-Chip No Program Program Program Access Memory Memory Memory (Top of Memory) (Top of Memory) External (Top of Memory) (Top of Memory) + 1 (Top of Memory) + 1 Memory (Top of Memory) + 1(3) Mapped Reads ‘0’s External Mapped to Memory to External External Memory 1FFFFFh – Memory Space (Top of Memory) Space 1FFFFFh 1FFFFFh 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure5-1 for device-specific values). Shaded areas represent unimplemented, or inaccessible areas, depending on the mode. Note 1: This mode is the only available mode on 64-pin devices and the default on 80-pin devices. 2: These modes are only available on 80-pin devices. 3: Addresses starting at the top of the program memory are translated to start at 0000h of the external device whenever the EASHFT Configuration bit is set. TABLE 5-2: MEMORY ACCESS FOR PIC18F8XJ5X PROGRAM MEMORY MODES Internal Program Memory External Program Memory Operating Mode Execution Table Read Table Write Execution Table Read Table Write From From To From From To Microcontroller Yes Yes Yes No Access No Access No Access Extended Microcontroller Yes Yes Yes Yes Yes Yes DS39775C-page 72 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 5.1.5 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and is contained in three separate 8-bit registers. The the stack is readable and writable through the low byte, known as the PCL register, is both readable Top-of-Stack Special Function Registers. Data can also and writable. The high byte, or PCH register, contains be pushed to, or popped from the stack, using these the PC<15:8> bits; it is not directly readable or writable. registers. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack. register contains the PC<20:16> bits; it is also not The Stack Pointer is first incremented and the location directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the register are performed through the PCLATU register. contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred a pop from the stack. The contents of the location to the program counter by any operation that writes pointed to by the STKPTR are transferred to the PC PCL. Similarly, the upper two bytes of the program and then the Stack Pointer is decremented. counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all offsets to the PC (see Section5.1.8.1 “Computed Resets. There is no RAM associated with the location GOTO”). corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is The PC addresses bytes in the program memory. To full, has overflowed or has underflowed. prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to 5.1.6.1 Top-of-Stack Access a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. Only the top of the return address stack (TOS) is read- able and writable. A set of three registers, The CALL, RCALL, GOTO and program branch TOSU:TOSH:TOSL, hold the contents of the stack instructions write to the program counter directly. For location pointed to by the STKPTR register these instructions, the contents of PCLATH and (Figure5-4). This allows users to implement a software PCLATU are not transferred to the program counter. stack if necessary. After a CALL, RCALL or interrupt (and ADDULNK and SUBULNK instructions if the 5.1.6 RETURN ADDRESS STACK extended instruction set is enabled), the software can The return address stack allows any combination of up read the pushed value by reading the to 31 program calls and interrupts to occur. The PC is TOSU:TOSH:TOSL registers. These values can be pushed onto the stack when a CALL or RCALL instruc- placed on a user-defined software stack. At return time, tion is executed, or an interrupt is Acknowledged. The the software can return these values to PC value is pulled off the stack on a RETURN, RETLW TOSU:TOSH:TOSL and do a return. or a RETFIE instruction (and on ADDULNK and The user must disable the global interrupt enable bits SUBULNK instructions if the extended instruction set is while accessing the stack to prevent inadvertent stack enabled). PCLATU and PCLATH are not affected by corruption. any of the RETURN or CALL instructions. FIGURE 5-4: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> Top-of-Stack Registers Stack Pointer 11111 TOSU TOSH TOSL 11110 STKPTR<4:0> 00h 1Ah 34h 11101 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 © 2009 Microchip Technology Inc. DS39775C-page 73

PIC18F87J50 FAMILY 5.1.6.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The STKPTR register (Register5-2) contains the Stack to the PC and set the STKUNF bit, while the Stack Pointer value, the STKFUL (Stack Full) status bit and Pointer remains at zero. The STKUNF bit will remain the STKUNF (Stack Underflow) status bits. The value set until cleared by software or until a POR occurs. of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System (RTOS) for return stack maintenance. not the same as a Reset, as the contents of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a 5.1.6.3 PUSH and POP Instructions POR. Since the Top-of-Stack is readable and writable, the The action that takes place when the stack becomes ability to push values onto the stack and pull values off full depends on the state of the STVREN (Stack Over- the stack, without disturbing normal program execu- flow Reset Enable) Configuration bit. (Refer to tion, is a desirable feature. The PIC18 instruction set Section25.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control. (default), the 31st push will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data onto the stack, set the STKFUL bit and reset the or a return address on the stack. device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto Pointer will be set to zero. the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st push and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by Any additional pushes will not overwrite the 31st push decrementing the Stack Pointer. The previous value and the STKPTR will remain at 31. pushed onto the stack then becomes the TOS value. REGISTER 5-2: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. DS39775C-page 74 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 5.1.6.4 Stack Full and Underflow Resets 5.1.8 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in There may be programming situations that require the Configuration Register 1L. When STVREN is set, a full creation of data structures, or look-up tables, in or underflow condition will set the appropriate STKFUL program memory. For PIC18 devices, look-up tables or STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit, but not cause • Table Reads a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 5.1.8.1 Computed GOTO 5.1.7 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in A Fast Register Stack is provided for the STATUS, Example5-2. WREG and BSR registers to provide a “fast return” option for interrupts. This stack is only one level deep A look-up table can be formed with an ADDWF PCL and is neither readable nor writable. It is loaded with the instruction and a group of RETLW nn instructions. The current value of the corresponding register when the W register is loaded with an offset into the table before processor vectors for an interrupt. All interrupt sources executing a call to that table. The first instruction of the will push values into the Stack registers. The values in called routine is the ADDWF PCL instruction. The next the registers are then loaded back into the working instruction executed will be one of the RETLW nn registers if the RETFIE, FAST instruction is used to instructions that returns the value ‘nn’ to the calling return from the interrupt. function. If both low and high-priority interrupts are enabled, the The offset value (in WREG) specifies the number of Stack registers cannot be used reliably to return from bytes that the program counter should advance and low-priority interrupts. If a high-priority interrupt occurs should be multiples of 2 (LSb = 0). while servicing a low-priority interrupt, the Stack In this method, only one data byte may be stored in register values stored by the low-priority interrupt will each instruction location and room on the return be overwritten. In these cases, users must save the key address stack is required. registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 5-2: COMPUTED GOTO USING Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE interrupts are used, the Fast Register Stack can be MOVF OFFSET, W used to restore the STATUS, WREG and BSR registers CALL TABLE at the end of a subroutine call. To use the Fast Register ORG nn00h Stack for a subroutine call, a CALL label, FAST TABLE ADDWF PCL instruction must be executed to save the STATUS, RETLW nnh WREG and BSR registers to the Fast Register Stack. A RETLW nnh RETURN, FAST instruction is then executed to restore RETLW nnh these registers from the Fast Register Stack. . . Example5-1 shows a source code example that uses . the Fast Register Stack during a subroutine call and return. 5.1.8.2 Table Reads EXAMPLE 5-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per ;STACK program word while programming. The Table Pointer • (TBLPTR) specifies the byte address and the Table • Latch (TABLAT) contains the data that is read from the program memory. Data is transferred from program SUB1 • memory one byte at a time. • RETURN FAST ;RESTORE VALUES SAVED Table read operation is discussed further in ;IN FAST REGISTER STACK Section6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. DS39775C-page 75

PIC18F87J50 FAMILY 5.2 PIC18 Instruction Cycle 5.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles, Q1 5.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are pipe- The microcontroller clock input, whether from an lined in such a manner that a fetch takes one instruction internal or external source, is internally divided by four cycle, while the decode and execute takes another to generate four non-overlapping quadrature clocks instruction cycle. However, due to the pipelining, each (Q1, Q2, Q3 and Q4). Internally, the program counter is instruction effectively executes in one cycle. If an incremented on every Q1; the instruction is fetched instruction causes the program counter to change (e.g., from the program memory and latched into the Instruc- GOTO), then two cycles are required to complete the tion Register (IR) during Q4. The instruction is decoded instruction (Example5-3). and executed during the following Q1 through Q4. The A fetch cycle begins with the Program Counter (PC) clocks and instruction execution flow are shown in incrementing in Q1. Figure5-5. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 5-5: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Q3 Phase Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS39775C-page 76 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 5.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruc- tion. Since instructions are always stored on word The program memory is addressed in bytes. Instruc- boundaries, the data contained in the instruction is a tions are stored as two bytes or four bytes in program word address. The word address is written to PC<20:1> memory. The Least Significant Byte of an instruction which accesses the desired byte address in program word is always stored in a program memory location memory. Instruction #2 in Figure5-6 shows how the with an even address (LSB = 0). To maintain alignment instruction, GOTO 0006h, is encoded in the program with instruction boundaries, the PC increments in steps memory. Program branch instructions, which encode a of 2 and the LSB will always read ‘0’ (see Section5.1.5 relative address offset, operate in the same manner. The “Program Counter”). offset value stored in a branch instruction represents the Figure5-6 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section26.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 5-6: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0 ↓ Program Memory 000000h Byte Locations → 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 5.2.4 TWO-WORD INSTRUCTIONS and used by the instruction sequence. If the first word is skipped for some reason and the second word is The standard PIC18 instruction set has four two-word executed by itself, a NOP is executed instead. This is instructions: CALL, MOVFF, GOTO and LSFR. In all necessary for cases when the two-word instruction is cases, the second word of the instructions always has preceded by a conditional instruction that changes the ‘1111’ as its four Most Significant bits; the other 12 bits PC. Example5-4 shows how this works. are literal data, usually a data memory address. Note: See Section5.5 “Program Memory and The use of ‘1111’ in the 4 MSbs of an instruction the Extended Instruction Set” for specifies a special form of NOP. If the instruction is information on two-word instructions in the executed in proper sequence – immediately after the extended instruction set. first word – the data in the second word is accessed EXAMPLE 5-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code © 2009 Microchip Technology Inc. DS39775C-page 77

PIC18F87J50 FAMILY 5.3 Data Memory Organization 5.3.2 BANK SELECT REGISTER Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section5.6 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit 12-bit address, allowing up to 4096 bytes of data low-order address and a 4-bit Bank Pointer. memory. The memory space is divided into as many as Most instructions in the PIC18 instruction set make use 16 banks that contain 256 bytes each. The of the Bank Pointer, known as the Bank Select Register PIC18F87J10 family implements all available banks (BSR). This SFR holds the 4 Most Significant bits of a and provides 3904 bytes of data memory available to location’s address; the instruction itself includes the the user. Figure5-7 shows the data memory 8Least Significant bits. Only the four lower bits of the organization for the devices. BSR are implemented (BSR3:BSR0). The upper four The data memory contains Special Function Registers bits are unused; they will always read ‘0’ and cannot be (SFRs) and General Purpose Registers (GPRs). The written to. The BSR can be loaded directly by using the SFRs are used for control and status of the controller MOVLB instruction. and peripheral functions, while GPRs are used for data The value of the BSR indicates the bank in data mem- storage and scratchpad operations in the user’s ory. The 8 bits in the instruction show the location in the application. Any read of an unimplemented location will bank and can be thought of as an offset from the bank’s read as ‘0’s. lower boundary. The relationship between the BSR’s The instruction set and architecture allow operations value and the bank division in data memory is shown in across all banks. The entire data memory may be Figure5-8. accessed by Direct, Indirect or Indexed Addressing Since up to 16 registers may share the same low-order modes. Addressing modes are discussed later in this address, the user must always be careful to ensure that section. the proper bank is selected before performing a data To ensure that commonly used registers (select SFRs read or write. For example, writing what should be and select GPRs) can be accessed in a single cycle, program data to an 8-bit address of F9h while the BSR PIC18 devices implement an Access Bank. This is a is 0Fh, will end up resetting the program counter. 256-byte memory space that provides fast access to While any bank can be selected, only those banks that select SFRs and the lower portion of GPR Bank 0 with- are actually implemented can be read or written to. out using the BSR. Section5.3.3 “Access Bank” Writes to unimplemented banks are ignored, while provides a detailed description of the Access RAM. reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the 5.3.1 USB RAM operation was successful. The data memory map in The entire data memory is actually mapped to a special Figure5-7 indicates which banks are implemented. dual access RAM. When the USB module is disabled, In the core PIC18 instruction set, only the MOVFF the GPRs in these banks are used like any other GPR instruction fully specifies the 12-bit address of the in the data memory space. source and target registers. This instruction ignores the When the USB module is enabled, the memory in these BSR completely when it executes. All other instructions banks is allocated as buffer RAM for USB operation. include only the low-order address as an operand and This area is shared between the microcontroller core must use either the BSR or the Access Bank to locate and the USB Serial Interface Engine (SIE) and is used their target registers. to transfer data directly between the two. It is theoretically possible to use the areas of USB RAM that are not allocated as USB buffers for normal scratchpad memory or other variable storage. In practice, the dynamic nature of buffer allocation makes this risky at best. Additionally, Bank 4 is used for USB buffer management when the module is enabled and should not be used for any other purposes during that time. Additional information on USB RAM and buffer operation is provided in Section22.0 “Universal Serial Bus (USB)” DS39775C-page 78 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 5-7: DATA MEMORY MAP FOR PIC18F87J50 FAMILY DEVICES BSR<3:0> Data Memory Map When a = 0: The BSR is ignored and the 00h 000h Access Bank is used. Access RAM = 0000 Bank 0 GPR(1) 0056F0hh Tpuhrep ofisrest R9A6M b (yfrteosm aBraen kg e0n).e ral FFh 0FFh 00h 100h The remaining 160 bytes are = 0001 Special Function Registers Bank 1 GPR(1) (from Bank 15). FFh 1FFh 00h 200h = 0010 Bank 2 GPR(1) When a = 1: FFh 2FFh The BSR specifies the bank 00h 300h used by the instruction. = 0011 Bank 3 GPR(1) FFh 3FFh 00h 400h = 0100 Bank 4 GPR, BDT(1) FFh 4FFh 00h 500h = 0101 Bank 5 GPR(1) FFh 5FFh 00h 600h = 0110 Bank 6 GPR(1) Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 GPR(1) Access RAM Low 5Fh FFh 7FFh Access RAM High 60h 00h 800h = 1000 Bank 8 GPR(1) (SFRs) FFh FFh 8FFh 00h 900h = 1001 Bank 9 GPR(1) FFh 9FFh 00h A00h = 1010 Bank 10 GPR(1) FFh AFFh 00h B00h = 1011 Bank 11 GPR(1) FFh BFFh 00h C00h = 1100 GPR(1) Bank 12 FFh CFFh 00h D00h = 1101 GPR(1) Bank 13 FFh DFFh 00h E00h = 1110 GPR(1) Bank 14 FFh EFFh = 1111 00h GPR(1) F00h F3Fh Bank 15 40h SFR(2) 60h F5Fh Access RAM FFh FFFh Note 1: These banks also serve as RAM buffers for USB operation. See Section5.3.1 “USB RAM” for more information. 2: Addresses, F40h through F5Fh, are not part of the Access Bank, therefore, specifying a BSR should be used to access these registers. © 2009 Microchip Technology Inc. DS39775C-page 79

PIC18F87J50 FAMILY FIGURE 5-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 7 BSR(1) 0 000h Data Memory 00h 7 From Opcode(2) 0 0 0 0 0 0 0 1 0 Bank 0 11 11 11 11 11 11 11 11 FFh 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 5.3.3 ACCESS BANK Using this “forced” addressing allows the instruction to operate on a data address in a single cycle without While the use of the BSR with an embedded 8-bit updating the BSR first. For 8-bit addresses of 60h and address allows users to address the entire range of above, this means that users can evaluate and operate data memory, it also means that the user must always on SFRs more efficiently. The Access RAM below 60h ensure that the correct bank is selected. Otherwise, is a good place for data values that the user might need data may be read from or written to the wrong location. to access rapidly, such as immediate computational This can be disastrous if a GPR is the intended target results or common program variables. Access RAM of an operation, but an SFR is written to instead. also allows for faster and more code efficient context Verifying and/or changing the BSR for each read or saving and switching of variables. write to data memory can become very inefficient. The mapping of the Access Bank is slightly different To streamline access for the most commonly used data when the extended instruction set is enabled (XINST memory locations, the data memory is configured with Configuration bit = 1). This is discussed in more detail an Access Bank, which allows users to access a in Section5.6.3 “Mapping the Access Bank in mapped block of memory without specifying a BSR. Indexed Literal Offset Mode”. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of 5.3.4 GENERAL PURPOSE memory (60h-FFh) in Bank 15. The lower half is known REGISTER FILE as the “Access RAM” and is composed of GPRs. The upper half is where the device’s SFRs are mapped. PIC18 devices may have banked memory in the GPR These two areas are mapped contiguously in the area. This is data RAM which is available for use by all Access Bank and can be addressed in a linear fashion instructions. GPRs start at the bottom of Bank 0 by an 8-bit address (Figure5-7). (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a The Access Bank is used by core PIC18 instructions Power-on Reset and are unchanged on all other that include the Access RAM bit (the ‘a’ parameter in Resets. the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. DS39775C-page 80 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 5.3.5 SPECIAL FUNCTION REGISTERS ALU’s STATUS register is described later in this section. Registers related to the operation of the The Special Function Registers (SFRs) are registers peripheral features are described in the chapter for that used by the CPU and peripheral modules for controlling peripheral. the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of The SFRs are typically distributed among the data memory (FFFh) and extend downward to occupy peripherals whose functions they control. Unused SFR more than the top half of Bank 15 (F40h to FFFh). A list locations are unimplemented and read as ‘0’s of these registers is given inTable5-3, Table5-4 and Note: Addresses, F40h through F5Fh, are not Table5-5. part of the Access Bank, therefore specify- The SFRs can be classified into two sets: those ing a BSR should be used to access these associated with the “core” device functionality (ALU, registers. Resets and interrupts) and those related to the peripheral functions. The Reset and interrupt registers are described in their respective chapters, while the TABLE 5-3: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J50 FAMILY DEVICES Address Name Address Name Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh ECCP1AS F9Fh IPR1 F7Fh SPBRGH1 F5Fh UCFG FFEh TOSH FDEh POSTINC2(1) FBEh ECCP1DEL F9Eh PIR1 F7Eh BAUDCON1 F5Eh UADDR FFDh TOSL FDDh POSTDEC2(1) FBDh CCPR1H F9Dh PIE1 F7Dh SPBRGH2 F5Dh UEIE FFCh STKPTR FDCh PREINC2(1) FBCh CCPR1L F9Ch RCSTA2 F7Ch BAUDCON2 F5Ch UIE FFBh PCLATU FDBh PLUSW2(1) FBBh CCP1CON F9Bh OSCTUNE F7Bh TMR3H F5Bh UEP15 FFAh PCLATH FDAh FSR2H FBAh ECCP2AS F9Ah TRISJ(2) F7Ah TMR3L F5Ah UEP14 FF9h PCL FD9h FSR2L FB9h ECCP2DEL F99h TRISH(2) F79h T3CON F59h UEP13 FF8h TBLPTRU FD8h STATUS FB8h CCPR2H F98h TRISG F78h TMR4 F58h UEP12 FF7h TBLPTRH FD7h TMR0H FB7h CCPR2L F97h TRISF F77h PR4(3) F57h UEP11 FF6h TBLPTRL FD6h TMR0L FB6h CCP2CON F96h TRISE F76h T4CON F56h UEP10 FF5h TABLAT FD5h T0CON FB5h ECCP3AS F95h TRISD F75h CCPR4H F55h UEP9 FF4h PRODH FD4h FB4h ECCP3DEL F94h TRISC F74h CCPR4L F54h UEP8 FF3h PRODL FD3h OSCCON(3) FB3h CCPR3H F93h TRISB F73h CCP4CON F53h UEP7 FF2h INTCON FD2h CM1CON FB2h CCPR3L F92h TRISA F72h CCPR5H F52h UEP6 FF1h INTCON2 FD1h CM2CON FB1h CCP3CON F91h LATJ(2) F71h CCPR5L F51h UEP5 FF0h INTCON3 FD0h RCON FB0h SPBRG1 F90h LATH(2) F70h CCP5CON F50h UEP4 FEFh INDF0(1) FCFh TMR1H(3) FAFh RCREG1 F8Fh LATG F6Fh SSP2BUF F4Fh UEP3 FEEh POSTINC0(1) FCEh TMR1L(3) FAEh TXREG1 F8Eh LATF F6Eh SSP2ADD F4Eh UEP2 FEDh POSTDEC0(1) FCDh T1CON(3) FADh TXSTA1 F8Dh LATE F6Dh SSP2STAT F4Dh UEP1 FECh PREINC0(1) FCCh TMR2(3) FACh RCSTA1 F8Ch LATD F6Ch SSP2CON1 F4Ch UEP0 FEBh PLUSW0(1) FCBh PR2(3) FABh SPBRG2 F8Bh LATC F6Bh SSP2CON2 F4Bh PMCONH FEAh FSR0H FCAh T2CON FAAh RCREG2 F8Ah LATB F6Ah CMSTAT F4Ah PMCONL FE9h FSR0L FC9h SSP1BUF FA9h TXREG2 F89h LATA F69h PMADDRH(4) F49h PMMODEH FE8h WREG FC8h SSP1ADD FA8h TXSTA2 F88h PORTJ(2) F68h PMADDRL(4) F48h PMMODEL FE7h INDF1(1) FC7h SSP1STAT FA7h EECON2 F87h PORTH(2) F67h PMDIN1H F47h PMDOUT2H FE6h POSTINC1(1) FC6h SSP1CON1 FA6h EECON1 F86h PORTG F66h PMDIN1L F46h PMDOUT2L FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h PORTF F65h UCON F45h PMDIN2H FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h USTAT F44h PMDIN2L FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h UEIR F43h PMEH FE2h FSR1H FC2h ADCON0(3) FA2h IPR2 F82h PORTC F62h UIR F42h PMEL FE1h FSR1L FC1h ADCON1(3) FA1h PIR2 F81h PORTB F61h UFRMH F41h PMSTATH FE0h BSR FC0h WDTCON FA0h PIE2 F80h PORTA F60h UFRML F40h PMSTATL Note 1: This is not a physical register. 2: This register is not available on 64-pin devices. 3: This register shares the same address with another register (see Table5-4 for alternate register). 4: PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address. PMADDRx is used in Master modes and PMDOUTx is used in Slave modes. © 2009 Microchip Technology Inc. DS39775C-page 81

PIC18F87J50 FAMILY 5.3.5.1 Shared Address SFRs 5.3.5.2 Context Defined SFRs In several locations in the SFR bank, a single address In addition to the shared address SFRs, there are sev- is used to access two different hardware registers. In eral registers that share the same address in the SFR these cases, a “legacy” register of the standard PIC18 space, but are not accessed with the ADSHR bit. SFR set (such as OSCCON, T1CON, etc.) shares its Instead, the register’s definition and use depends on address with an alternate register. These alternate reg- the operating mode of its associated peripheral. These isters are associated with enhanced configuration registers are: options for peripherals, or with new device features not • SSPxADD and SSPxMSK: These are two sepa- included in the standard PIC18 SFR map. A complete rate hardware registers, accessed through a list of shared register addresses and the registers single SFR address. The operating mode of the associated with them is provided in Table5-4. MSSP modules determines which register is Access to the alternate registers is enabled in software being accessed. See Section19.4.3.4 “7-Bit by setting the ADSHR bit in the WDTCON register Address Masking Mode” for additional details. (Register5-3). ADSHR must be manually set or • PMADDRH/L and PMDOUT2H/L: In this case, cleared to access the alternate or legacy registers, as these named buffer pairs are actually the same required. Since the bit remains in a given state until physical registers. The PMP module’s operating changed, users should always verify the state of mode determines what function the registers take ADSHR before writing to any of the shared SFR on. See Section11.1.2 “Data Registers” for addresses. additional details. TABLE 5-4: SHARED SFR ADDRESSES FOR PIC18F87J50 FAMILY DEVICES Address Name Address Name Address Name FD3h (D) OSCCON FCDh (D) T1CON FC2h (D) ADCON0 (A) REFOCON (A) ODCON3 (A) ANCON1 FCFh (D) TMR1H FCCh (D) TMR2 FC1h (D) ADCON1 (A) ODCON1 (A) PADCFG1 (A) ANCON0 FCEh (D) TMR1L FCBh (D) PR2 F77h (D) PR4 (A) ODCON2 (A) MEMCON(1) (A) CVRCON Legend: (D) = Default SFR, accessible only when ADSHR = 0; (A) = Alternate SFR, accessible only when ADSHR = 1. Note 1: Implemented in 80-pin devices only. REGISTER 5-3: WDTCON: WATCHDOG TIMER CONTROL REGISTER R/W-0 R-x U-0 R/W-0 U-0 U-0 U-0 U-0 REGSLP LVDSTAT — ADSHR — — — SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 REGSLP: Voltage Regulator Low-Power Operation Enable bit For details of bit operation, see Register25-9 on page 359. bit 6 LVDSTAT: Low-Voltage Detect Status bit 1 = VDDCORE > 2.45V nominal 0 = VDDCORE < 2.45V nominal bit 5 Unimplemented: Read as ‘0’ bit 4 ADSHR: Shared Address SFR Select bit 1 = Alternate SFR is selected 0 = Default (legacy) SFR is selected bit 3-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit For details of bit operation, see Register25-9. DS39775C-page 82 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 61, 73 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 61, 73 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 61, 73 STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 61, 74 PCLATU — — bit 21(1) Holding Register for PC<20:16> ---0 0000 61, 73 PCLATH Holding Register for PC<15:8> 0000 0000 61, 73 PCL PC Low Byte (PC<7:0>) 0000 0000 61, 73 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 61, 106 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 61, 106 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 61, 106 TABLAT Program Memory Table Latch 0000 0000 61, 106 PRODH Product Register High Byte xxxx xxxx 61, 119 PRODL Product Register Low Byte xxxx xxxx 61, 119 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 61, 123 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 61, 123 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 61, 123 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 61, 91 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 61, 92 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 61, 92 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 61, 92 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – N/A 61, 92 value of FSR0 offset by W FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 61, 91 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 61, 91 WREG Working Register xxxx xxxx 61, 75 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 61, 91 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 61, 92 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 61, 92 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 61, 92 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – N/A 61, 92 value of FSR1 offset by W FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 61, 91 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 61, 91 BSR — — — — Bank Select Register ---- 0000 61, 78 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 62, 91 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 62, 92 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 62, 92 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 62, 92 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – N/A 62, 92 value of FSR2 offset by W FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 62, 91 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming modes. 2: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. 4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 6: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.4.3.2 “Address Masking Modes” for details 7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 80-pin devices. 8: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. DS39775C-page 83

PIC18F87J50 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 62, 91 STATUS — — — N OV Z DC C ---x xxxx 62, 89 TMR0H Timer0 Register High Byte 0000 0000 62, 193 TMR0L Timer0 Register Low Byte xxxx xxxx 62, 193 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 62, 192 OSCCON(2)/ IDLEN IRCF2 IRCF1 IRCF0 OSTS(4) — SCS1 SCS0 0110 q100 62, 44 REFOCON(3) ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 0-00 0000 62, 45 CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 62, 345 CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 62, 345 RCON IPEN — CM RI TO PD POR BOR 0-11 1100 60, 62, 135 TMR1H(2)/ Timer1 Register High Byte xxxx xxxx 62, 196 ODCON1(3) — — — CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD ---0 0000 62, 139 TMR1L(2)/ Timer1 Register Low Byte xxxx xxxx 62, 196 ODCON2(3) — — — — — — U2OD U1OD ---- --00 62, 139 T1CON(2)/ RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 62, 196 ODCON3(3) — — — — — — SPI2OD SPI1OD ---- --00 62, 139 TMR2(2)/ Timer2 Register 0000 0000 62, 201 PADCFG1(3) — — — — — — — PMPTTL ---- ---0 62, 140 PR2(2)/ Timer2 Period Register 1111 1111 62, 201 MEMCON(3) EDBIS — WAIT1 WAIT0 — — WM1 WMO 0-00 --00 62, 108 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 62, 201 SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 62, 243, 278 SSP1ADD/ MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C™ Master mode) 0000 0000 62, 248 SSP1MSK(5) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 62, 250 SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 62, 233, 244 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 62, 233, 245 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 62, 233, GCEN ACKSTAT ADMSK5(6) ADMSK4(6) ADMSK3(6) ADMSK2(6) ADMSK1(6) SEN 246 ADRESH A/D Result Register High Byte xxxx xxxx 63, 310 ADRESL A/D Result Register Low Byte xxxx xxxx 63, 310 ADCON0(2)/ VCFG1 VCFG0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 63, 301 ANCON1(3) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 — — 0000 00-- 63, 301 ADCON1(2)/ ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0000 0000 63, 301 ANCON0(3) PCFG7 — — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0--0 0000 63, 301 WDTCON REGSLP LVDSTAT — ADSHR — — — SWDTEN 0x-0 ---0 63, 358 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming modes. 2: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. 4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 6: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.4.3.2 “Address Masking Modes” for details 7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 80-pin devices. 8: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information. DS39775C-page 84 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 63, 232 ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 63, 232 CCPR1H Capture/Compare/PWM Register 1 HIgh Byte xxxx xxxx 63, 232 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 63, 232 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 63, 232 ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 63, 232 ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 63, 232 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 63, 232 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 63, 232 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 63, 232 ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 63, 232 ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 63, 232 CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx 63, 232 CCPR3L Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 63, 232 CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 63, 232 SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 63, 283 RCREG1 EUSART1 Receive Register 0000 0000 63, 291, 292 TXREG1 EUSART1 Transmit Register xxxx xxxx 63, 289, 290 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 63, 289 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 63, 291 SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 63, 283 RCREG2 EUSART2 Receive Register 0000 0000 63, 291, 292 TXREG2 EUSART2 Transmit Register 0000 0000 63, 289, 290 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 63, 289 EECON2 Program Memory Control Register 2 (not a physical register) ---- ---- 63, 98 EECON1 — — WPROG FREE WRERR WREN WR — --00 x00- 63, 98 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 1111 1111 64, 132 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 0000 0000 64, 126 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 0000 0000 64, 129 IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP 1111 1111 64, 132 PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 0000 0000 64, 126 PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE 0000 0000 64, 129 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 64, 132 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 64, 126 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 64, 129 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 64, 291 OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 64, 39 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming modes. 2: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. 4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 6: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.4.3.2 “Address Masking Modes” for details 7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 80-pin devices. 8: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. DS39775C-page 85

PIC18F87J50 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: TRISJ(7) TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111 64, 165 TRISH(7) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111 64, 163 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ---1 1111 64, 160 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 — — 111- -1-- 64, 157 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 64, 154 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 64, 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 64, 148 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 64, 145 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 64, 142 LATJ(7) LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx xxxx 64, 165 LATH(7) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx 64, 163 LATG — — — LATG4 LATG3 LATG2 LATG1 LATG0 ---x xxxx 64, 160 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 — — xxxx xx-- 64, 157 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx 64, 154 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 64, 151 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 64, 148 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 64, 145 LATA — — LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 --xx xxxx 64, 142 PORTJ(7) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx 65, 165 PORTH(7) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 0000 xxxx 65, 163 PORTG RDPU REPU RJPU(7) RG4 RG3 RG2 RG1 RG0 000x xxxx 65, 160 PORTF RF7 RF6 RF5 RF4 RF3 RF2 — — x00x x0-- 65, 157 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 65, 154 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 65, 151 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 65, 148 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 65, 145 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 65, 142 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 65, 283 BAUDCON1 ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN 0100 0-00 65, 283 SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 65, 283 BAUDCON2 ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN 0100 0-00 65, 283 TMR3H Timer3 Register High Byte xxxx xxxx 65, 208 TMR3L Timer3 Register Low Byte xxxx xxxx 65, 208 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 65, 208 TMR4 Timer4 Register 0000 0000 65, 207 PR4(2)/ Timer4 Period Register 1111 1111 65, 208 CVRCON(3) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 65, 346 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 65, 207 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming modes. 2: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. 4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 6: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.4.3.2 “Address Masking Modes” for details 7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 80-pin devices. 8: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information. DS39775C-page 86 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 65, 210 CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 65, 210 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 65, 210 CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 65, 210 CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 65, 210 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 65, 210 SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 65, 243, 278 SSP2ADD/ MSSP2 Address Register (I2C™ Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) 0000 0000 65, 243 SSP2MSK(5) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 0000 0000 65, 250 SSP2STAT SMP CKE D/A P S R/W UA BF 1111 1111 65, 233, 244 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 65, 233, 245 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 65, 233, GCEN ACKSTAT ADMSK5(6) ADMSK4(6) ADMSK3(6) ADMSK2(6) ADMSK1(6) SEN 245 CMSTAT — — — — — — COUT2 COUT1 ---- --11 65, 339 PMADDRH/ CS2 CS1 Parallel Master Port Address High Byte 0000 0000 66, 174 PMDOUT1H(8) Parallel Port Out Data High Byte (Buffer 1) 0000 0000 66, 177 PMADDRL/ Parallel Master Port Address Low Byte 0000 0000 66, 174 PMDOUT1L(8) Parallel Port Out Data Low Byte (Buffer 0) 0000 0000 66, 174 PMDIN1H Parallel Port In Data High Byte (Buffer 1) 0000 0000 66, 174 PMDIN1L Parallel Port In Data Low Byte (Buffer 0) 0000 0000 66, 174 UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 66, 312 USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 66, 316 UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 66, 329 UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 66, 326 UFRMH — — — — — FRM10 FRM9 FRM8 ---- -xxx 66, 318 UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 66, 318 UCFG UTEYE — — UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000 66, 313 UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 66, 318 UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 66, 330 UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 66, 328 UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming modes. 2: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. 4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 6: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.4.3.2 “Address Masking Modes” for details 7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 80-pin devices. 8: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. DS39775C-page 87

PIC18F87J50 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 PMCONH PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 0-00 0000 66, 168 PMCONL CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP 0000 0000 67, 169 PMMODEH BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 0000 0000 67, 170 PMMODEL WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000 0000 67, 171 PMDOUT2H Parallel Port Out Data High Byte (Buffer 3) 0000 0000 67, 174 PMDOUT2L Parallel Port Out Data Low Byte (Buffer 2) 0000 0000 67, 174 PMDIN2H Parallel Port In Data High Byte (Buffer 3) 0000 0000 67, 174 PMDIN2L Parallel Port In Data Low Byte (Buffer 2) 0000 0000 67, 174 PMEH PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 0000 0000 67, 171 PMEL PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000 0000 67, 172 PMSTATH IBF IBOV — — IB3F IB2F IB1F IB0F 00-- 0000 67, 172 PMSTATL OBE OBUF — — OB3E OB2E OB1E OB0E 10-- 1111 67, 173 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming modes. 2: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. 4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 6: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.4.3.2 “Address Masking Modes” for details 7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 80-pin devices. 8: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information. DS39775C-page 88 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 5.3.6 STATUS REGISTER register then reads back as ‘000u u1uu’. It is recom- mended, therefore, that only BCF, BSF, SWAPF, The STATUS register, shown in Register5-4, contains MOVFF and MOVWF instructions are used to alter the the arithmetic status of the ALU. The STATUS register STATUS register because these instructions do not can be the operand for any instruction, as with any affect the Z, C, DC, OV or N bits in the STATUS other register. If the STATUS register is the destination register. for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. For other instructions not affecting any Status bits, see the instruction set summaries in Table26-2 and These bits are set or cleared according to the device Table26-3. logic. Therefore, the result of an instruction with the STATUS register as destination may be different than Note: The C and DC bits operate as a borrow and intended. For example, CLRF STATUS will set the Z bit digit borrow bit respectively, in subtraction. but leave the other bits unchanged. The STATUS REGISTER 5-4: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. 2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. DS39775C-page 89

PIC18F87J50 FAMILY 5.4 Data Addressing Modes Purpose Register File”), or a location in the Access Bank (Section5.3.3 “Access Bank”) as the data Note: The execution of some instructions in the source for the instruction. core PIC18 instruction set are changed The Access RAM bit ‘a’ determines how the address is when the PIC18 extended instruction set is interpreted. When ‘a’ is ‘1’, the contents of the BSR enabled. See Section5.6 “Data Memory (Section5.3.2 “Bank Select Register”) are used with and the Extended Instruction Set” for the address to determine the complete 12-bit address more information. of the register. When ‘a’ is ‘0’, the address is interpreted While the program memory can be addressed in only as being a register in the Access Bank. Addressing that one way – through the program counter – information uses the Access RAM is sometimes also known as in the data memory space can be addressed in several Direct Forced Addressing mode. ways. For most instructions, the addressing mode is A few instructions, such as MOVFF, include the entire fixed. Other instructions may use up to three modes, 12-bit address (either source or destination) in their depending on which operands are used and whether or opcodes. In these cases, the BSR is ignored entirely. not the extended instruction set is enabled. The destination of the operation’s results is determined The addressing modes are: by the destination bit ‘d’. When ‘d’ is ‘1’, the results are • Inherent stored back in the source register, overwriting its origi- nal contents. When ‘d’ is ‘0’, the results are stored in • Literal the W register. Instructions without the ‘d’ argument • Direct have a destination that is implicit in the instruction; their • Indirect destination is either the target register being operated An additional addressing mode, Indexed Literal Offset, on or the W register. is available when the extended instruction set is 5.4.3 INDIRECT ADDRESSING enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section5.6.1 “Indexed Indirect Addressing allows the user to access a location Addressing with Literal Offset”. in data memory without giving a fixed address in the instruction. This is done by using File Select Registers 5.4.1 INHERENT AND LITERAL (FSRs) as pointers to the locations to be read or written ADDRESSING to. Since the FSRs are themselves located in RAM as Many PIC18 control instructions do not need any Special Function Registers, they can also be directly argument at all; they either perform an operation that manipulated under program control. This makes FSRs globally affects the device, or they operate implicitly on very useful in implementing data structures such as one register. This addressing mode is known as tables and arrays in data memory. Inherent Addressing. Examples include SLEEP, RESET The registers for Indirect Addressing are also and DAW. implemented with Indirect File Operands (INDFs) that Other instructions work in a similar way, but require an permit automatic manipulation of the pointer value with additional explicit argument in the opcode. This is auto-incrementing, auto-decrementing or offsetting known as Literal Addressing mode, because they with another value. This allows for efficient code using require some literal value as an argument. Examples loops, such as the example of clearing an entire RAM include ADDLW and MOVLW, which respectively, add or bank in Example5-5. It also enables users to perform move a literal value to the W register. Other examples Indexed Addressing and other Stack Pointer include CALL and GOTO, which include a 20-bit operations for program memory in data memory. program memory address. EXAMPLE 5-5: HOW TO CLEAR RAM 5.4.2 DIRECT ADDRESSING (BANK 1) USING Direct Addressing specifies all or part of the source INDIRECT ADDRESSING and/or destination address of the operation within the LFSR FSR0, 100h ; opcode itself. The options are specified by the NEXT CLRF POSTINC0 ; Clear INDF arguments accompanying the instruction. ; register then ; inc pointer In the core PIC18 instruction set, bit-oriented and BTFSS FSR0H, 1 ; All done with byte-oriented instructions use some version of Direct ; Bank1? Addressing by default. All of these instructions include BRA NEXT ; NO, clear next some 8-bit Literal Address as their Least Significant CONTINUE ; YES, continue Byte. This address specifies either a register address in one of the banks of data RAM (Section5.3.4 “General DS39775C-page 90 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 5.4.3.1 FSR Registers and the mapped in the SFR space but are not physically imple- INDF Operand mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. At the core of Indirect Addressing are three sets of A read from INDF1, for example, reads the data at the registers: FSR0, FSR1 and FSR2. Each represents a address indicated by FSR1H:FSR1L. Instructions that pair of 8-bit registers, FSRnH and FSRnL. The four use the INDF registers as operands actually use the upper bits of the FSRnH register are not used, so each contents of their corresponding FSR as a pointer to the FSR pair holds a 12-bit value. This represents a value instruction’s target. The INDF operand is just a that can address the entire range of the data memory convenient way of using the pointer. in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current Indirect Addressing is accomplished with a set of contents of the BSR and the Access RAM bit have no Indirect File Operands, INDF0 through INDF2. These effect on determining the target address. can be thought of as “virtual” registers: they are FIGURE 5-9: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 Indirect Addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 1 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains E00h FCCh. This means the contents of Bank 14 location FCCh will be added to that F00h of the W register and stored back in Bank 15 FCCh. FFFh Data Memory © 2009 Microchip Technology Inc. DS39775C-page 91

PIC18F87J50 FAMILY 5.4.3.2 FSR Registers and POSTINC, 5.4.3.3 Operations by FSRs on FSRs POSTDEC, PREINC and PLUSW Indirect Addressing operations that target other FSRs In addition to the INDF operand, each FSR register pair or virtual registers represent special cases. For exam- also has four additional indirect operands. Like INDF, ple, using an FSR to point to one of the virtual registers these are “virtual” registers that cannot be indirectly will not result in successful operations. As a specific read or written to. Accessing these registers actually case, assume that FSR0H:FSR0L contains FE7h, the accesses the associated FSR register pair, but also address of INDF1. Attempts to read the value of the performs a specific action on its stored value. They are: INDF1, using INDF0 as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as the • POSTDEC: accesses the FSR value, then operand, will result in a NOP. automatically decrements it by ‘1’ afterwards • POSTINC: accesses the FSR value, then On the other hand, using the virtual registers to write to automatically increments it by ‘1’ afterwards an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any • PREINC: increments the FSR value by ‘1’, then incrementing or decrementing. Thus, writing to INDF2 uses it in the operation or POSTDEC2 will write the same value to the • PLUSW: adds the signed value of the W register FSR2H:FSR2L. (range of -127 to 128) to that of the FSR and uses the new value in the operation Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct In this context, accessing an INDF register uses the operations. Users should proceed cautiously when value in the FSR registers without changing them. working on these registers, particularly if their code Similarly, accessing a PLUSW register gives the FSR uses Indirect Addressing. value offset by the value in the W register; neither value is actually changed in the operation. Accessing the Similarly, operations by Indirect Addressing are gener- other virtual registers changes the value of the FSR ally permitted on all other SFRs. Users should exercise registers. the appropriate caution that they do not inadvertently change settings that might affect the operation of the Operations on the FSRs with POSTDEC, POSTINC device. and PREINC affect the entire register pair; that is, roll- overs of the FSRnL register from FFh to 00h carry over 5.5 Program Memory and the to the FSRnH register. On the other hand, results of Extended Instruction Set these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The operation of program memory is unaffected by the The PLUSW register can be used to implement a form use of the extended instruction set. of Indexed Addressing in the data memory space. By Enabling the extended instruction set adds five manipulating the value in the W register, users can additional two-word commands to the existing PIC18 reach addresses that are fixed offsets from pointer instruction set: ADDFSR, CALLW, MOVSF, MOVSS and addresses. In some applications, this can be used to SUBFSR. These instructions are executed as described implement some powerful program control structure, in Section5.2.4 “Two-Word Instructions”. such as software stacks, inside of data memory. DS39775C-page 92 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 5.6 Data Memory and the Extended Under these conditions, the file address of the Instruction Set instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing) or as Enabling the PIC18 extended instruction set (XINST an 8-bit address in the Access Bank. Instead, the value Configuration bit = 1) significantly changes certain is interpreted as an offset value to an Address Pointer aspects of data memory and its addressing. Specifi- specified by FSR2. The offset and the contents of cally, the use of the Access Bank for many of the core FSR2 are added to obtain the target address of the PIC18 instructions is different. This is due to the intro- operation. duction of a new addressing mode for the data memory space. This mode also alters the behavior of Indirect 5.6.2 INSTRUCTIONS AFFECTED BY Addressing using FSR2 and its associated operands. INDEXED LITERAL OFFSET MODE What does not change is just as important. The size of Any of the core PIC18 instructions that can use Direct the data memory space is unchanged, as well as its Addressing are potentially affected by the Indexed linear addressing. The SFR map remains the same. Literal Offset Addressing mode. This includes all Core PIC18 instructions can still operate in both Direct byte-oriented and bit-oriented instructions, or almost and Indirect Addressing mode; inherent and literal one-half of the standard PIC18 instruction set. Instruc- instructions do not change at all. Indirect Addressing tions that only use Inherent or Literal Addressing with FSR0 and FSR1 also remains unchanged. modes are unaffected. Additionally, byte-oriented and bit-oriented instructions 5.6.1 INDEXED ADDRESSING WITH are not affected if they use the Access Bank (Access LITERAL OFFSET RAM bit is ‘1’) or include a file address of 60h or above. Enabling the PIC18 extended instruction set changes Instructions meeting these criteria will continue to the behavior of Indirect Addressing using the FSR2 execute as before. A comparison of the different possi- register pair and its associated file operands. Under the ble addressing modes when the extended instruction proper conditions, instructions that use the Access set is enabled is shown in Figure5-10. Bank – that is, most bit-oriented and byte-oriented Those who desire to use byte-oriented or bit-oriented instructions – can invoke a form of Indexed Addressing instructions in the Indexed Literal Offset mode should using an offset specified in the instruction. This special note the changes to assembler syntax for this mode. addressing mode is known as Indexed Addressing with This is described in more detail in Section26.2.1 Literal Offset, or Indexed Literal Offset mode. “Extended Instruction Syntax”. When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0); and • The file address argument is less than or equal to 5Fh. © 2009 Microchip Technology Inc. DS39775C-page 93

PIC18F87J50 FAMILY FIGURE 5-10: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When a = 0 and f ≥ 60h: The instruction executes in 060h Direct Forced mode. ‘f’ is Bank 0 interpreted as a location in the 100h Access RAM between 060h 00h and FFFh. This is the same as Bank 1 through 60h locations F60h to FFFh Bank 14 (Bank15) of data memory. Valid range for ‘f’ Locations below 060h are not FFh available in this addressing F00h Access RAM mode. Bank 15 F60h SFRs FFFh Data Memory When a = 0 and f ≤ 5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 060h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F60h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When a = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 060h Direct mode (also known as Direct Long mode). ‘f’ is 100h interpreted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F60h SFRs FFFh Data Memory DS39775C-page 94 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 5.6.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue The use of Indexed Literal Offset Addressing mode to use Direct Addressing as before. Any Indirect or effectively changes how the lower part of Access RAM Indexed Addressing operation that explicitly uses any (00h to 5Fh) is mapped. Rather than containing just the of the indirect file operands (including FSR2) will con- contents of the bottom part of Bank 0, this mode maps tinue to operate as standard Indirect Addressing. Any the contents from Bank 0 and a user-defined “window” instruction that uses the Access Bank, but includes a that can be located anywhere in the data memory register address of greater than 05Fh, will use Direct space. The value of FSR2 establishes the lower bound- Addressing and the normal Access Bank map. ary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). 5.6.4 BSR IN INDEXED LITERAL Addresses in the Access RAM above 5Fh are mapped OFFSET MODE as previously described (see Section5.3.3 “Access Bank”). An example of Access Bank remapping in this Although the Access Bank is remapped when the addressing mode is shown in Figure5-11. extended instruction set is enabled, the operation of the BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. FIGURE 5-11: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a Not Accessible FSR2H:FSR2L = 120h 05Fh Locations in the region Bank 0 from the FSR2 Pointer 100h (120h) to the pointer plus 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Bank 1 “Window” Access RAM (000h-05Fh). 200h 5Fh Special Function Registers 60h at F60h through FFFh are mapped to 60h through Bank 2 FFh, as usual. through SFRs Bank 0 addresses below Bank 14 5Fh are not available in FFh this mode. They can still Access Bank be addressed by using the F00h BSR. Bank 15 F60h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. DS39775C-page 95

PIC18F87J50 FAMILY NOTES: DS39775C-page 96 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte • Table Read (TBLRD) at a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 64 bytes at a time or two bytes at a time. Pro- The program memory space is 16 bits wide, while the gram memory is erased in blocks of 1024 bytes at a data RAM space is 8 bits wide. Table reads and table time. A bulk erase operation may not be issued from writes move data between these two memory spaces user code. through an 8-bit register (TABLAT). Writing or erasing program memory will cease Table read operations retrieve data from program instruction fetches until the operation is complete. The memory and place it into the data RAM space. program memory cannot be accessed during the write Figure6-1 shows the operation of a table read with or erase, therefore, code cannot execute. An internal program memory and data RAM. programming timer terminates program memory writes and erases. Table write operations store data from the data memory space into holding registers in program memory. The A value written to program memory does not need to be procedure to write the contents of the holding registers a valid instruction. Executing a program memory into program memory is detailed in Section6.5 “Writing location that forms an invalid instruction results in a to Flash Program Memory”. Figure6-2 shows the NOP. operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. DS39775C-page 97

PIC18F87J50 FAMILY FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section6.5 “Writing to Flash Program Memory”. 6.2 Control Registers The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase Several control registers are used in conjunction with operation is initiated on the next WR command. When the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled. • EECON1 register The WREN bit, when set, will allow a write operation. • EECON2 register On power-up, the WREN bit is clear. The WRERR bit is • TABLAT register set in hardware when the WR bit is set and cleared • TBLPTR registers when the internal programming timer expires and the write operation is complete. 6.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is The EECON1 register (Register6-1) is the control read as ‘1’. This can indicate that a write register for memory accesses. The EECON2 register is operation was prematurely terminated by not a physical register; it is used exclusively in the a Reset, or a write operation was memory write and erase sequences. Reading attempted improperly. EECON2 will read all ‘0’s. The WR control bit initiates write operations. The bit The WPROG bit, when set, will allow programming cannot be cleared, only set, in software. It is cleared in twobytes per word on the execution of the WR com- hardware at the completion of the write operation. mand. If this bit is cleared, the WR command will result in programming on a block of 64 bytes. DS39775C-page 98 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 6-1: EECON1: EEPROM CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 — — WPROG FREE WRERR(1) WREN WR — bit 7 bit 0 Legend: S = Settable only bit (cannot be cleared in software) R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 WPROG: One Word-Wide Program bit 1 = Program 2 bytes on the next WR command 0 = Program 64 bytes on the next WR command bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program Write Enable bit 1 = Allows write cycles to Flash program memory 0 = Inhibits write cycles to Flash program memory bit 1 WR: Write Control bit 1 = Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is complete bit 0 Unimplemented: Read as ‘0’ Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. DS39775C-page 99

PIC18F87J50 FAMILY 6.2.2 TABLE LATCH REGISTER (TABLAT) 6.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the SFR space. The Table Latch register is used to Flash program memory. hold 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the TBLPTR memory and data RAM. determine which byte is read from program memory into TABLAT. 6.2.3 TABLE POINTER REGISTER (TBLPTR) When a TBLWT is executed, the seven LSbs of the Table Pointer register (TBLPTR<6:0>) determine which The Table Pointer (TBLPTR) register addresses a byte of the 64 program memory holding registers is written within the program memory. The TBLPTR is comprised to. When the timed write to program memory begins of three SFR registers: Table Pointer Upper Byte, Table (via the WR bit), the 12 MSbs of the TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<21:10>) determine which program memory (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- block of 1024 bytes is written to. For more detail, see ters join to form a 22-bit wide pointer. The low-order Section6.5 “Writing to Flash Program Memory”. 21bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to When an erase of program memory is executed, the the device ID, the user ID and the Configuration bits. 12MSbs of the Table Pointer register point to the 1024-byte block that will be erased. The Least The Table Pointer register, TBLPTR, is used by the Significant bits are ignored. TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the Figure6-3 describes the relevant boundaries of table operation. These operations are shown in TBLPTR based on Flash program memory operations. Table6-1. These operations on the TBLPTR only affect the low-order 21bits. TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE: TBLPTR<20:10> TABLE WRITE: TBLPTR<20:6> TABLE READ: TBLPTR<21:0> DS39775C-page 100 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 6.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure6-4 shows the interface between the internal program memory and the TABLAT. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_ODD © 2009 Microchip Technology Inc. DS39775C-page 101

PIC18F87J50 FAMILY 6.4 Erasing Flash Program Memory 6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or The sequence of events for erasing a block of internal through ICSP control, can larger blocks of program program memory location is: memory be bulk erased. Word erase in the Flash array 1. Load Table Pointer register with address of row is not supported. being erased. When initiating an erase sequence from the micro- 2. Set the WREN and FREE bits (EECON1<2,4>) controller itself, a block of 1024 bytes of program to enable the erase operation. memory is erased. The Most Significant 12 bits of the 3. Disable interrupts. TBLPTR<21:10> point to the block being erased. 4. Write 55h to EECON2. TBLPTR<9:0> are ignored. 5. Write 0AAh to EECON2. The EECON1 register commands the erase operation. 6. Set the WR bit. This will begin the row erase The WREN bit must be set to enable write operations. cycle. The FREE bit is set to select an erase operation. For 7. The CPU will stall for duration of the erase for protection, the write initiate sequence for EECON2 TIW (see parameter D133A). must be used. 8. Re-enable interrupts. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS39775C-page 102 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 6.5 Writing to Flash Program Memory The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip The programming block is 32 words or 64 bytes. charge pump, rated to operate over the voltage range Programming one word or two bytes at a time is also of the device. supported. Note1: Unlike previous PIC® devices, members Table writes are used internally to load the holding of the PIC18F87J10 family do not reset registers needed to program the Flash memory. There the holding registers after a write occurs. are 64 holding registers used by the table writes for The holding registers must be cleared or programming. overwritten before a programming Since the Table Latch (TABLAT) is only a single byte, the sequence. TBLWT instruction may need to be executed 64times for 2: To maintain the endurance of the program each programming operation (if WPROG = 0). All of the memory cells, each Flash byte should not table write operations will essentially be short writes be programmed more than one time because only the holding registers are written. At the between erase operations. Before end of updating the 64 holding registers, the EECON1 attempting to modify the contents of the register must be written to in order to start the target cell a second time, a row erase of programming operation with a long write. the target row, or a bulk erase of the entire The long write is necessary for programming the inter- memory, must be performed. nal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxx3F Holding Register Holding Register Holding Register Holding Register Program Memory 6.5.1 FLASH PROGRAM MEMORY WRITE 8. Disable interrupts. SEQUENCE 9. Write 55h to EECON2. The sequence of events for programming an internal 10. Write 0AAh to EECON2. program memory location should be: 11. Set the WR bit. This will begin the write cycle. 1. Read 1024 bytes into RAM. 12. The CPU will stall for duration of the write for TIW (see parameter D133A). 2. Update data values in RAM as necessary. 13. Re-enable interrupts. 3. Load Table Pointer register with address being erased. 14. Repeat steps 6 through 13 until all 1024 bytes are written to program memory. 4. Execute the row erase procedure. 15. Verify the memory (table read). 5. Load Table Pointer register with address of first byte being written, minus 1. An example of the required code is shown in 6. Write the 64 bytes into the holding registers with Example6-3 on the following page. auto-increment. Note: Before setting the WR bit, the Table 7. Set the WREN bit (EECON1<2>) to enable byte Pointer address needs to be within the writes. intended address range of the 64 bytes in the holding register. © 2009 Microchip Technology Inc. DS39775C-page 103

PIC18F87J50 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base address MOVWF TBLPTRU ; of the memory block, minus 1 MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts MOVLW D'16' MOVWF WRITE_COUNTER ; Need to write 16 blocks of 64 to write ; one erase block of 1024 RESTART_BUFFER MOVLW D'64' MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L FILL_BUFFER ... ; read the new data from I2C, SPI, ; PSP, USART, etc. WRITE_BUFFER MOVLW D’64 ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS MOVFF POSTINC0, WREG ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_BYTE_TO_HREGS PROGRAM_MEMORY BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory DECFSZ WRITE_COUNTER ; done with one write cycle BRA RESTART_BUFFER ; if not done replacing the erase block DS39775C-page 104 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 6.5.2 FLASH PROGRAM MEMORY WRITE 3. Set the WREN bit (EECON1<2>) to enable SEQUENCE (WORD PRORAMMING). writes and the WPROG bit (EECON1<5>) to select Word Write mode. The PIC18F87J10 family of devices have a feature that 4. Disable interrupts. allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the 5. Write 55h to EECON2. memory location is already erased, the following 6. Write AAh to EECON2. sequence is required to enable this feature: 7. Set the WR bit. This will begin the write cycle. 1. Load the Table Pointer register with the address 8. The CPU will stall for duration of the write for TIW of the data to be written. (It must be an even (see parameter D133A). address.) 9. Re-enable interrupts. 2. Write the 2 bytes into the holding registers by performing table writes. (Do not post-increment on the second table write.) EXAMPLE 6-4: SINGLE WORD WRITE TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base address MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW ; The table pointer must be loaded with an even address MOVWF TBLPTRL MOVLW DATA0 ; LSB of word to be written MOVWF TABLAT TBLWT*+ MOVLW DATA1 ; MSB of word to be written MOVWF TABLAT TBLWT* ; The last table write must not increment the table pointer! The table pointer needs to point to the MSB before starting the write operation. PROGRAM_MEMORY BSF EECON1, WPROG ; enable single word write BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WPROG ; disable single word write BCF EECON1, WREN ; disable write to memory © 2009 Microchip Technology Inc. DS39775C-page 105

PIC18F87J50 FAMILY 6.5.3 WRITE VERIFY 6.6 Flash Program Operation During Code Protection Depending on the application, good programming practice may dictate that the value written to the See Section25.6 “Program Verification and Code memory should be verified against the original value. Protection” for details on code protection of Flash This should be used in applications where excessive program memory. writes can stress bits near the specification limit. 6.5.4 UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and repro- grammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 61 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 61 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 61 TABLAT Program Memory Table Latch 61 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 EECON2 Program Memory Control Register 2 (not a physical register) 63 EECON1 — — WPROG FREE WRERR WREN WR — 63 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access. DS39775C-page 106 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 7.0 EXTERNAL MEMORY BUS The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE Note: The External Memory Bus is not and PORTH) are multiplexed with the address/data bus implemented on 64-pin devices. for a total of 20 available lines, while PORTJ is multiplexed with the bus control signals. The External Memory Bus (EMB) allows the device to access external memory devices (such as Flash, A list of the pins and their functions is provided in EPROM, SRAM, etc.) as program or data memory. It Table7-1. supports both 8 and 16-Bit Data Width modes and three address widths of up to 20 bits. TABLE 7-1: PIC18F87J50 FAMILY EXTERNAL BUS – I/O PORT FUNCTIONS Name Port Bit External Memory Bus Function RD0/AD0 PORTD 0 Address bit 0 or Data bit 0 RD1/AD1 PORTD 1 Address bit 1 or Data bit 1 RD2/AD2 PORTD 2 Address bit 2 or Data bit 2 RD3/AD3 PORTD 3 Address bit 3 or Data bit 3 RD4/AD4 PORTD 4 Address bit 4 or Data bit 4 RD5/AD5 PORTD 5 Address bit 5 or Data bit 5 RD6/AD6 PORTD 6 Address bit 6 or Data bit 6 RD7/AD7 PORTD 7 Address bit 7 or Data bit 7 RE0/AD8 PORTE 0 Address bit 8 or Data bit 8 RE1/AD9 PORTE 1 Address bit 9 or Data bit 9 RE2/AD10 PORTE 2 Address bit 10 or Data bit 10 RE3/AD11 PORTE 3 Address bit 11 or Data bit 11 RE4/AD12 PORTE 4 Address bit 12 or Data bit 12 RE5/AD13 PORTE 5 Address bit 13 or Data bit 13 RE6/AD14 PORTE 6 Address bit 14 or Data bit 14 RE7/AD15 PORTE 7 Address bit 15 or Data bit 15 RH0/A16 PORTH 0 Address bit 16 RH1/A17 PORTH 1 Address bit 17 RH2/A18 PORTH 2 Address bit 18 RH3/A19 PORTH 3 Address bit 19 RJ0/ALE PORTJ 0 Address Latch Enable (ALE) Control pin RJ1/OE PORTJ 1 Output Enable (OE) Control pin RJ2/WRL PORTJ 2 Write Low (WRL) Control pin RJ3/WRH PORTJ 3 Write High (WRH) Control pin RJ4/BA0 PORTJ 4 Byte Address bit 0 (BA0) RJ5/CE PORTJ 5 Chip Enable (CE) Control pin RJ6/LB PORTJ 6 Lower Byte Enable (LB) Control pin RJ7/UB PORTJ 7 Upper Byte Enable (UB) Control pin Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. © 2009 Microchip Technology Inc. DS39775C-page 107

PIC18F87J50 FAMILY 7.1 External Memory Bus Control The WAIT bits allow for the addition of wait states to external memory operations. The use of these bits is The operation of the interface is controlled by the discussed in Section7.3 “Wait States”. MEMCON register (Register7-1). This register is The WM bits select the particular operating mode used available in all program memory operating modes when the bus is operating in 16-Bit Data Width mode. except Microcontroller mode. In this mode, the register These are discussed in more detail in Section7.6 is disabled and cannot be written to. “16-Bit Data Width Modes”. These bits have no effect The EBDIS bit (MEMCON<7>) controls the operation when an 8-Bit Data Width mode is selected. of the bus and related port functions. Clearing EBDIS The MEMCON register (see Register7-1) shares the enables the interface and disables the I/O functions of same memory space as the PR2 register and can be the ports, as well as any other functions multiplexed to alternately selected based on the designation of the those pins. Setting the bit enables the I/O ports and ADSHR bit in the WDTCON register (see other functions, but allows the interface to override Register25-9). everything else on the pins when an external memory operation is required. By default, the external bus is always enabled and disables all other I/O. The operation of the EBDIS bit is also influenced by the program memory mode being used. This is discussed in more detail in Section7.5 “Program Memory Modes and the External Memory Bus”. REGISTER 7-1: MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EBDIS — WAIT1 WAIT0 — — WM1 WM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EBDIS: External Bus Disable bit 1 = External bus enabled when microcontroller accesses external memory; otherwise, all external bus drivers are mapped as I/O ports 0 = External bus always enabled, I/O ports are disabled bit 6 Unimplemented: Read as ‘0’ bit 5-4 WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 WM1:WM0: TBLWT Operation with 16-Bit Data Bus Width Select bits 1x = Word Write mode: TABLAT word output, WRH active when TABLAT is written 01 = Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB) will activate 00 = Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate DS39775C-page 108 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 7.2 Address and Data Width 7.2.1 ADDRESS SHIFTING ON THE EXTERNAL BUS The PIC18F87J10 family of devices can be indepen- dently configured for different address and data widths By default, the address presented on the external bus on the same memory bus. Both address and data width is the value of the PC. In practical terms, this means are set by Configuration bits in the CONFIG3L register. that addresses in the external memory device below As Configuration bits, this means that these options the top of on-chip memory are unavailable to the micro- can only be configured by programming the device and controller. To access these physical locations, the glue are not controllable in software. logic between the microcontroller and the external memory must somehow translate addresses. The BW bit selects an 8-bit or 16-bit data bus width. Setting this bit (default) selects a data width of 16 bits. To simplify the interface, the external bus offers an extension of Extended Microcontroller mode that The EMB1:EMB0 bits determine both the program automatically performs address shifting. This feature is memory operating mode and the address bus width. controlled by the EASHFT Configuration bit. Setting The available options are 20-bit, 16-bit and 12-bit, as this bit offsets addresses on the bus by the size of the well as Microcontroller mode (external bus disabled). microcontroller’s on-chip program memory and sets Selecting a 16-bit or 12-bit width makes a correspond- the bottom address at 0000h. This allows the device to ing number of high-order lines available for I/O use the entire range of physical addresses of the functions. These pins are no longer affected by the external memory. setting of the EBDIS bit. For example, selecting a 16-Bit Addressing mode (EMB1:EMB0=01) disables 7.2.2 21-BIT ADDRESSING A19:A16 and allows PORTH<3:0> to function without As an extension of 20-bit address width operation, the interruptions from the bus. Using the smaller address External Memory Bus can also fully address a 2-Mbyte widths allows users to tailor the memory bus to the size memory space. This is done by using the Bus Address of the external memory space for a particular design bit 0 (BA0) control line as the Least Significant bit of the while freeing up pins for dedicated I/O operation. address. The UB and LB control signals may also be Because the EMB bits have the effect of disabling pins used with certain memory devices to select the upper for memory bus operations, it is important to always and lower bytes within a 16-bit wide data word. select an address width at least equal to the data width. This addressing mode is available in both 8-Bit and If a 12-bit address width is used with a 16-bit data certain 16-Bit Data Width modes. Additional details are width, the upper four bits of data will not be available on provided in Section7.6.3 “16-Bit Byte Select Mode” the bus. and Section7.7 “8-Bit Data Width Mode”. All combinations of address and data widths require multiplexing of address and data information on the same lines. The address and data multiplexing, as well as I/O ports made available by the use of smaller address widths, are summarized in Table7-2. TABLE 7-2: ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS Multiplexed Data and Address Only Ports Available Data Width Address Width Address Lines (and Lines (and for I/O Corresponding Ports) Corresponding Ports) AD11:AD8 PORTE<7:4>, 12-bit (PORTE<3:0>) All of PORTH AD15:AD8 16-bit AD7:AD0 All of PORTH 8-bit (PORTE<7:0>) (PORTD<7:0>) A19:A16, AD15:AD8 20-bit (PORTH<3:0>, — PORTE<7:0>) 16-bit AD15:AD0 — All of PORTH 16-bit (PORTD<7:0>, A19:A16 20-bit — PORTE<7:0>) (PORTH<3:0>) © 2009 Microchip Technology Inc. DS39775C-page 109

PIC18F87J50 FAMILY 7.3 Wait States functions. When EBDIS = 0, the pins function as the external bus. When EBDIS = 1, the pins function as I/O While it may be assumed that external memory devices ports. will operate at the microcontroller clock rate, this is If the device fetches or accesses external memory often not the case. In fact, many devices require longer while EBDIS = 1, the pins will switch to external bus. If times to write or retrieve data than the time allowed by the EBDIS bit is set by a program executing from exter- the execution of table read or table write operations. nal memory, the action of setting the bit will be delayed To compensate for this, the External Memory Bus can until the program branches into the internal memory. At be configured to add a fixed delay to each table opera- that time, the pins will change from external bus to I/O tion using the bus. Wait states are enabled by setting ports. the WAIT Configuration bit. When enabled, the amount If the device is executing out of internal memory when of delay is set by the WAIT1:WAIT0 bits EBDIS = 0, the memory bus address/data and control (MEMCON<5:4>). The delay is based on multiples of pins will not be active. They will go to a state where the microcontroller instruction cycle time and are added active address/data pins are tri-state; the CE, OE, following the instruction cycle when the table operation WRH, WRL, UB and LB signals are ‘1’ and ALE and is executed. The range is from no delay to 3TCY BA0 are ‘0’. Note that only those pins associated with (default value). the current address width are forced to tri-state; the other pins continue to function as I/O. In the case of 7.4 Port Pin Weak Pull-ups 16-bit address width, for example, only AD<15:0> With the exception of the upper address lines, (PORTD and PORTE) are affected; A19:A16 A19:A16, the pins associated with the External Memory (PORTH<3:0>) continue to function as I/O. Bus are equipped with weak pull-ups. The pull-ups are In all external memory modes, the bus takes priority controlled by the upper three bits of the PORTG over any other peripherals that may share pins with it. register (PORTG<7:5>). They are named RDPU, This includes the Parallel Master Port and serial REPU and RJPU and control pull-ups on PORTD, communication modules which would otherwise take PORTE and PORTJ, respectively. Setting one of these priority over the I/O port. bits enables the corresponding pull-ups for that port. All pull-ups are disabled by default on all device Resets. 7.6 16-Bit Data Width Modes In Extended Microcontroller mode, the port pull-ups In 16-Bit Data Width mode, the external memory can be useful in preserving the memory state on the interface can be connected to external memories in external bus while the bus is temporarily disabled three different configurations: (EBDIS = ‘1’). • 16-Bit Byte Write 7.5 Program Memory Modes and the • 16-Bit Word Write External Memory Bus • 16-Bit Byte Select The PIC18F87J10 family of devices is capable of The configuration to be used is determined by the operating in one of two program memory modes, using WM1:WM0 bits in the MEMCON register combinations of on-chip and external program memory. (MEMCON<1:0>). These three different configurations The functions of the multiplexed port pins depend on allow the designer maximum flexibility in using both the program memory mode selected, as well as the 8-bit and 16-bit devices with 16-bit data. setting of the EBDIS bit. For all 16-bit modes, the Address Latch Enable (ALE) In Microcontroller Mode, the bus is not active and the pin indicates that the address bits, AD<15:0>, are avail- pins have their port functions only. Writes to the able on the external memory interface bus. Following MEMCOM register are not permitted. The Reset value the address latch, the Output Enable signal (OE) will enable both bytes of program memory at once to form of EBDIS (‘0’) is ignored and EMB pins behave as I/O a 16-bit instruction word. The Chip Enable signal (CE) ports. is active at any time that the microcontroller accesses In Extended Microcontroller Mode, the external external memory, whether reading or writing; it is program memory bus shares I/O port functions on the inactive (asserted high) whenever the device is in pins. When the device is fetching or doing table Sleep mode. read/table write operations on the external program In Byte Select mode, JEDEC standard Flash memories memory space, the pins will have the external bus will require BA0 for the byte address line and one I/O function. line to select between Byte and Word mode. The other If the device is fetching and accessing internal program 16-bit modes do not need BA0. JEDEC standard static memory locations only, the EBDIS control bit will RAM memories will use the UB or LB signals for byte change the pins from external memory to I/O port selection. DS39775C-page 110 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 7.6.1 16-BIT BYTE WRITE MODE During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the Figure7-1 shows an example of 16-Bit Byte Write AD15:AD0 bus. The appropriate WRH or WRL control mode for PIC18F87J10 family devices. This mode is line is strobed on the LSb of the TBLPTR. used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. FIGURE 7-1: 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18F87J50 (MSB) (LSB) A<19:0> AD<7:0> 373 A<x:0> A<x:0> D<15:8> D<7:0> D<7:0> D<7:0> CE CE AD<15:8> 373 OE WR(2) OE WR(2) ALE A<19:16>(1) CE OE WRH WRL Address Bus Data Bus Control Lines Note 1: Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. DS39775C-page 111

PIC18F87J50 FAMILY 7.6.2 16-BIT WORD WRITE MODE During a TBLWT cycle to an odd address (TBLPTR<0>= 1), the TABLAT data is presented on Figure7-2 shows an example of 16-Bit Word Write the upper byte of the AD15:AD0 bus. The contents of mode for PIC18F87J10 family devices. This mode is the holding latch are presented on the lower byte of the used for word-wide memories which include some of AD15:AD0 bus. the EPROM and Flash-type memories. This mode allows opcode fetches and table reads from all forms of The WRH signal is strobed for each write cycle; the 16-bit memory and table writes to any type of WRL pin is unused. The signal on the BA0 pin indicates word-wide external memories. This method makes a the LSb of the TBLPTR, but it is left unconnected. distinction between TBLWT cycles to even or odd Instead, the UB and LB signals are active to select both addresses. bytes. The obvious limitation to this method is that the table write must be done in pairs on a specific word During a TBLWT cycle to an even address boundary to correctly write a word location. (TBLPTR<0>= 0), the TABLAT data is transferred to a holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. No write signals are activated. FIGURE 7-2: 16-BIT WORD WRITE MODE EXAMPLE PIC18F87J50 AD<7:0> 373 A<20:1> A<x:0> JEDEC Word EPROM Memory D<15:0> D<15:0> CE OE WR(2) AD<15:8> 373 ALE A<19:16>(1) CE OE WRH Address Bus Data Bus Control Lines Note 1: Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section6.1 “Table Reads and Table Writes”. DS39775C-page 112 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 7.6.3 16-BIT BYTE SELECT MODE Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC Figure7-3 shows an example of 16-Bit Byte Select standard Flash memories require that a controller I/O mode. This mode allows table write operations to port pin be connected to the memory’s BYTE/WORD word-wide external memories with byte selection pin to provide the select signal. They also use the BA0 capability. This generally includes both word-wide signal from the controller as a byte address. JEDEC Flash and SRAM devices. standard static RAM memories, on the other hand, use During a TBLWT cycle, the TABLAT data is presented the UB or LB signals to select the byte. on the upper and lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle; the WRL pin is not used. The BA0 or UB/LB signals are used to select the byte to be written, based on the Least Significant bit of the TBLPTR register. FIGURE 7-3: 16-BIT BYTE SELECT MODE EXAMPLE PIC18F87J50 A<20:1> AD<7:0> 373 A<x:1> JEDEC Word FLASH Memory D<15:0> D<15:0> 138(3) CE AD<15:8> 373 A0 ALE BYTE/WORD OE WR(1) A<19:16>(2) OE WRH WRL A<20:1> A<x:1> JEDEC Word BA0 SRAM Memory I/O D<15:0> CE D<15:0> LB LB UB UB OE WR(1) Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section6.1 “Table Reads and Table Writes”. 2: Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2009 Microchip Technology Inc. DS39775C-page 113

PIC18F87J50 FAMILY 7.6.4 16-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure7-4 and Figure7-5. FIGURE 7-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:0> CF33h 9256h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction Execution INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW FIGURE 7-5: EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:0> 3AAAh 0003h 3AABh 0E55h CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction Execution INST(PC – 2) SLEEP DS39775C-page 114 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 7.7 8-Bit Data Width Mode The Address Latch Enable (ALE) pin indicates that the address bits, AD<15:0>, are available on the external In 8-Bit Data Width mode, the External Memory Bus memory interface bus. The Output Enable signal (OE) operates only in Multiplexed mode; that is, data shares will enable one byte of program memory for a portion of the 8 Least Significant bits of the address bus. the instruction cycle, then BA0 will change and the Figure7-6 shows an example of 8-Bit Multiplexed second byte will be enabled to form the 16-bit instruc- mode for 80-pin devices. This mode is used for a single tion word. The Least Significant bit of the address, BA0, 8-bit memory connected for 16-bit operation. The must be connected to the memory devices in this instructions will be fetched as two 8-bit bytes on a mode. The Chip Enable signal (CE) is active at any shared data/address bus. The two bytes are sequen- time that the microcontroller accesses external tially fetched within one instruction cycle (TCY). memory, whether reading or writing. It is inactive Therefore, the designer must choose external memory (asserted high) whenever the device is in Sleep mode. devices according to timing calculations based on This generally includes basic EPROM and Flash 1/2TCY (2 times the instruction rate). For proper mem- devices. It allows table writes to byte-wide external ory speed selection, glue logic propagation delay times memories. must be considered, along with setup and hold times. FIGURE 7-6: 8-BIT MULTIPLEXED MODE EXAMPLE D<7:0> PIC18F87J50 A<19:0> AD<7:0> 373 A<x:1> ALE D<15:8> A0 D<7:0> AD<15:8>(1) CE A<19:16>(1) OE WR(2) BA0 CE OE WRL Address Bus Data Bus Control Lines Note 1: Upper order address bits are only used for 20-bit address width. The upper AD byte is used for all address widths except 8-bit. 2: This signal only applies to table writes. See Section6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. DS39775C-page 115

PIC18F87J50 FAMILY 7.7.1 8-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure7-7 and Figure7-8. FIGURE 7-7: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:8> CFh AD<7:0> 33h 92h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction Execution INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW FIGURE 7-8: EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:8> 3Ah 3Ah AD<7:0> AAh 00h 03h ABh 0Eh 55h BA0 CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction Execution INST(PC – 2) SLEEP DS39775C-page 116 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 7.8 Operation in Power-Managed In Sleep and Idle modes, the microcontroller core does Modes not need to access data; bus operations are suspended. The state of the external bus is frozen, with In alternate, power-managed Run modes, the external the address/data pins and most of the control pins hold- bus continues to operate normally. If a clock source ing at the same state they were in when the mode was with a lower speed is selected, bus operations will run invoked. The only potential changes are the CE, LB at that speed. In these cases, excessive access times and UB pins, which are held at logic high. for the external memory may result if wait states have been enabled and added to external memory opera- tions. If operations in a lower power Run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. © 2009 Microchip Technology Inc. DS39775C-page 117

PIC18F87J50 FAMILY NOTES: DS39775C-page 118 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 8.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 8-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 8.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY register. ROUTINE Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the MOVF ARG1, W advantages of higher computational throughput and MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit allows the PIC18 devices to be used in many applica- SUBWF PRODH, F ; PRODH = PRODH tions previously reserved for digital signal processors. ; - ARG1 A comparison of various hardware and software MOVF ARG2, W multiply operations, along with the savings in memory BTFSC ARG1, SB ; Test Sign Bit and execution time, is shown in Table8-1. SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 8.2 Operation Example8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example8-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the argu- ments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 48 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 5.7 μs 27.6 μs 69 μs 8 x 8 unsigned Hardware multiply 1 1 83.3 ns 400 ns 1 μs Without hardware multiply 33 91 7.5 μs 36.4 μs 91 μs 8 x 8 signed Hardware multiply 6 6 500 ns 2.4 μs 6 μs Without hardware multiply 21 242 20.1 μs 96.8 μs 242 μs 16 x 16 unsigned Hardware multiply 28 28 2.3 μs 11.2 μs 28 μs Without hardware multiply 52 254 21.6 μs 102.6 μs 254 μs 16 x 16 signed Hardware multiply 35 40 3.3 μs 16.0 μs 40 μs © 2009 Microchip Technology Inc. DS39775C-page 119

PIC18F87J50 FAMILY Example8-3 shows the sequence to do a 16 x 16 EQUATION 8-2: 16 x 16 SIGNED unsigned multiplication. Equation8-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + EQUATION 8-1: 16 x 16 UNSIGNED (ARG1H • ARG2L • 28) + MULTIPLICATION (ARG1L • ARG2H • 28) + ALGORITHM (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L (-1 • ARG1H<7> • ARG2H:ARG2L • 216) = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + EXAMPLE 8-4: 16 x 16 SIGNED (ARG1L • ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 8-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example8-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation8-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers ; (RES3:RES0). To account for the sign bits of the SIGN_ARG1 arguments, the MSb for each argument pair is tested BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? and the appropriate subtractions are done. BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS39775C-page 120 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 9.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are Members of the PIC18F87J10 family of devices have compatible with PIC® mid-range devices. In multiple interrupt sources and an interrupt priority Compatibility mode, the interrupt priority bits for each feature that allows most interrupt sources to be source have no effect. INTCON<6> is the PEIE bit assigned a high-priority level or a low-priority level. The which enables/disables all peripheral interrupt sources. high-priority interrupt vector is at 0008h and the INTCON<7> is the GIE bit which enables/disables all low-priority interrupt vector is at 0018h. High-priority interrupt sources. All interrupts branch to address interrupt events will interrupt any low-priority interrupts 0008h in Compatibility mode. that may be in progress. When an interrupt is responded to, the global interrupt There are thirteen registers which are used to control enable bit is cleared to disable further interrupts. If the interrupt operation. These registers are: IPEN bit is cleared, this is the GIE bit. If interrupt priority • RCON levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a • INTCON low-priority interrupt. Low-priority interrupts are not • INTCON2 processed while high-priority interrupts are in progress. • INTCON3 The return address is pushed onto the stack and the • PIR1, PIR2, PIR3 PC is loaded with the interrupt vector address (0008h • PIE1, PIE2, PIE3 or 0018h). Once in the Interrupt Service Routine, the • IPR1, IPR2, IPR3 source(s) of the interrupt can be determined by polling It is recommended that the Microchip header files the interrupt flag bits. The interrupt flag bits must be supplied with MPLAB® IDE be used for the symbolic bit cleared in software before re-enabling interrupts to names in these registers. This allows the avoid recursive interrupts. assembler/compiler to automatically take care of the The “return from interrupt” instruction, RETFIE, exits placement of these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL In general, interrupt sources have three bits to control if priority levels are used) which re-enables interrupts. their operation. They are: For external interrupt events, such as the INTx pins or • Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. • Enable bit that allows program execution to Individual interrupt flag bits are set regardless of the branch to the interrupt vector address when the status of their corresponding enable bit or the GIE bit. flag bit is set • Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while The interrupt priority feature is enabled by setting the any interrupt is enabled. Doing so may IPEN bit (RCON<7>). When interrupt priority is cause erratic microcontroller behavior. enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. DS39775C-page 121

PIC18F87J50 FAMILY FIGURE 9-1: PIC18F87J50 FAMILY INTERRUPT LOGIC TMR0IF Wake-up if in TMR0IE Idle or Sleep modes TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE Interrupt to CPU INT1IP Vector to Location INT2IF PIR1<7:0> INT2IE 0008h PIE1<7:0> INT2IP IPR1<7:0> INT3IF INT3IE INT3IP GIE/GIEH PIR2<7:0> PIE2<7:0> IPR2<7:0> IPEN PIR3<7:0> IPEN PIE3<7:0> IPR3<7:0> PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> Interrupt to CPU PIR3<7:0> TTMMRR00IIEF IPEN V00e1c8tohr to Location PIE3<7:0> TMR0IP IPR3<7:0> RBIF RBIE RBIP GIE/GIEH PEIE/GIEL INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP DS39775C-page 122 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 9.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers which contain various enable, priority and flag interrupt enable bit. User software should bits. ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. DS39775C-page 123

PIC18F87J50 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39775C-page 124 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. DS39775C-page 125

PIC18F87J50 FAMILY 9.2 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the Global peripheral interrupts. Due to the number of peripheral Interrupt Enable bit, GIE (INTCON<7>). interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PMPIF: Parallel Master Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 =No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART1 receive buffer is empty bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART1 transmit buffer is full bit 3 SSP1IF: Master Synchronous Serial Port Interrupt Flag bit (MSSP1 module) 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow DS39775C-page 126 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6 CM2IF: Comparator 2 Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5 CM1IF: Comparator 1 Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 4 USBIF: USB Interrupt Flag bit 1 = USB has requested an interrupt (must be cleared in software) 0 = No USB interrupt request bit 3 BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = Device VDDCORE voltage is above the regulator low-voltage trip point (above 2.45V) bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. DS39775C-page 127

PIC18F87J50 FAMILY REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 6 BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 5 RC2IF: EUSART2 Receive Interrupt Flag bit 1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The EUSART2 receive buffer is empty bit 4 TX2IF: EUSART2 Transmit Interrupt Flag bit 1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The EUSART2 transmit buffer is full bit 3 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred bit 2 CCP5IF: CCP5 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 1 CCP4IF: CCP4 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 0 CCP3IF: ECCP3 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. DS39775C-page 128 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PMPIE: Parallel Master Port Read/Write Interrupt Enable bit 1 = Enables the PM read/write interrupt 0 = Disables the PM read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enables the EUSART1 receive interrupt 0 = Disables the EUSART1 receive interrupt bit 4 TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enables the EUSART1 transmit interrupt 0 = Disables the EUSART1 transmit interrupt bit 3 SSP1IE: Master Synchronous Serial Port Interrupt Enable bit (MSSP1 module) 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt bit 2 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enables the ECCP1 interrupt 0 = Disables the ECCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2009 Microchip Technology Inc. DS39775C-page 129

PIC18F87J50 FAMILY REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CM2IE: Comparator 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 CM1IE: Comparator 1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 USBIE: USB Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module) 1 = Enabled 0 = Disabled bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39775C-page 130 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module) 1 = Enabled 0 = Disabled bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP5IE: CCP5 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. DS39775C-page 131

PIC18F87J50 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PMPIP: Parallel Master Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSP1IP: Master Synchronous Serial Port Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority bit 2 CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39775C-page 132 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CM2IP: Comparator 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 C12IP: Comparator 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 USBIP: USB Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. DS39775C-page 133

PIC18F87J50 FAMILY REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module) 1 = High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IE: TMR4 to PR4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP5IP: CCP5 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit 1 = High priority 0 = Low priority DS39775C-page 134 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 9-13: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0’ bit 5 CM: Configuration Mismatch Flag bit For details of bit operation, see Register4-1. bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register4-1. bit 3 TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register4-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register4-1. © 2009 Microchip Technology Inc. DS39775C-page 135

PIC18F87J50 FAMILY 9.6 INTx Pin Interrupts 9.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, In 8-bit mode (which is the default), an overflow in the RB2/INT2 and RB3/INT3 pins are edge-triggered. If the TMR0 register (FFh→00h) will set flag bit, TMR0IF. In corresponding INTEDGx bit in the INTCON2 register is 16-bit mode, an overflow in the TMR0H:TMR0L register set (= 1), the interrupt is triggered by a rising edge; if pair (FFFFh→0000h) will set TMR0IF. The interrupt the bit is clear, the trigger is on the falling edge. When can be enabled/disabled by setting/clearing enable bit, a valid edge appears on the RBx/INTx pin, the TMR0IE (INTCON<5>). Interrupt priority for Timer0 is corresponding flag bit, INTxIF, is set. This interrupt can determined by the value contained in the interrupt prior- be disabled by clearing the corresponding enable bit, ity bit, TMR0IP (INTCON2<2>). See Section12.0 INTxIE. Flag bit, INTxIF, must be cleared in software in “Timer0 Module” for further details on the Timer0 the Interrupt Service Routine before re-enabling the module. interrupt. 9.8 PORTB Interrupt-on-Change All external interrupts (INT0, INT1, INT2 and INT3) can wake-up the processor from the power-managed An input change on PORTB<7:4> sets flag bit, RBIF modes if bit INTxIE was set prior to going into the (INTCON<0>). The interrupt can be enabled/disabled power-managed modes. If the Global Interrupt Enable by setting/clearing enable bit, RBIE (INTCON<3>). bit, GIE, is set, the processor will branch to the interrupt Interrupt priority for PORTB interrupt-on-change is vector following wake-up. determined by the value contained in the interrupt Interrupt priority for INT1, INT2 and INT3 is determined priority bit, RBIP (INTCON2<0>). by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and 9.9 Context Saving During Interrupts INT3IP (INTCON2<1>). There is no priority bit associated with INT0. It is always a high-priority During interrupts, the return PC address is saved on interrupt source. the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack. If a fast return from interrupt is not used (see Section5.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS39775C-page 136 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 10.0 I/O PORTS 10.1 I/O Port Pin Capabilities Depending on the device selected and features When developing an application, the capabilities of the enabled, there are up to nine ports available. Some port pins must be considered. Outputs on some pins pins of the I/O ports are multiplexed with an alternate have higher output drive strength than others. Similarly, function from the peripheral features on the device. In some pins can tolerate higher than VDD input levels. general, when a peripheral is enabled, that pin may not 10.1.1 INPUT PINS AND VOLTAGE be used as a general purpose I/O pin. CONSIDERATIONS Each port has three memory-mapped registers for its operation: The voltage tolerance of pins used as device inputs is dependent on the pin’s input function. Pins that are used • TRIS register (Data Direction register) as digital only inputs are able to handle DC voltages up • PORT register (reads the levels on the pins of the to 5.5V, a level typical for digital logic circuits. In contrast, device) pins that also have analog input functions of any kind • LAT register (Output Latch register) (such as A/D and comparator inputs) can only tolerate Reading the PORT register reads the current status of voltages up to VDD. Voltage excursions beyond VDD on the pins, whereas writing to the PORT register writes to these pins should be avoided. the output latch (LAT) register. Table10-1 summarizes the input capabilities. Refer to Setting a TRIS bit (= 1) makes the corresponding Section28.0 “Electrical Characteristics” for more PORT pin an input (i.e., put the corresponding output details. driver in a high-impedance mode). Clearing a TRIS bit (= 0) makes the corresponding PORT pin an output TABLE 10-1: INPUT VOLTAGE LEVELS (i.e., put the contents of the corresponding LAT bit on Tolerated the selected pin). Port or Pin Description Input The Data Latch (LAT register) is useful for read-modify-write operations on the value that the I/O PORTA<5:0> VDD Only VDD input levels tolerated. pins are driving. Read-modify-write operations on the PORTC<1:0> LAT register read and write the latched output value for PORTF<6:1> PORT register. PORTH<7:4>(1) A simplified model of a generic I/O port, without the PORTB<7:0> 5.5V Tolerates input levels interfaces to other peripherals, is shown in Figure10-1. PORTC<7:2> above VDD, useful for most standard logic. FIGURE 10-1: GENERIC I/O PORT PORTD<7:0> OPERATION PORTE<7:0> PORTF<7> PORTG<4:0> RD LAT PORTH<3:0>(1) Data Bus PORTJ<7:0>(1) D Q Note 1: These ports are not available on 64-pin WR LAT I/O pin or PORT devices. CK Data Latch 10.1.2 PIN OUTPUT DRIVE D Q When used as digital I/O, the output pin drive strengths vary for groups of pins intended to meet the needs for WR TRIS CK a variety of applications. In general, there are three TRIS Latch Input classes of output pins in terms of drive capability. Buffer PORTB and PORTC, as well as PORTA<7:6>, are RD TRIS designed to drive higher current loads, such as LEDs. PORTD, PORTE and PORTJ are capable of driving digital circuits associated with external memory Q D devices. They can also drive LEDs, but only those with smaller current requirements. PORTF, PORTG and ENEN PORTH, along with PORTA<5:0>, have the lowest RD PORT drive level, but are capable of driving normal digital circuit loads with a high input impedance. © 2009 Microchip Technology Inc. DS39775C-page 137

PIC18F87J50 FAMILY Table10-2 summarizes the output capabilities of the When the open-drain option is required, the output pin ports. Refer to the “Absolute Maximum Ratings” in must also be tied through an external pull-up resistor Section28.0 “Electrical Characteristics” for more provided by the user to a higher voltage level, up to details. 5.5V (Figure10-2). When a digital logic high signal is output, it is pulled up to the higher voltage level. TABLE 10-2: OUTPUT DRIVE LEVELS FIGURE 10-2: USING THE OPEN-DRAIN Port Drive Description OUTPUT (USART SHOWN PORTA Minimum Intended for indication. AS EXAMPLE) PORTF PORTG 3.3V +5V PORTH(1) PIC18F87J50 PORTD Medium Sufficient drive levels for external memory interfacing PORTE as well as indication. PORTJ(1) VDD TXX 5V (at logic ‘1’) PORTB High Suitable for direct LED drive PORTC levels. Note 1: These ports are not available on 64-pin devices. 10.1.3 PULL-UP CONFIGURATION 10.1.5 TTL INPUT BUFFER OPTION Four of the I/O ports (PORTB, PORTD, PORTE and PORTJ) implement configurable weak pull-ups on all Many of the digital I/O ports use Schmitt Trigger (ST) pins. These are internal pull-ups that allow floating input buffers. While this form of buffering works well digital input signals to be pulled to a consistent level, with many types of input, some applications may without the use of external resistors. require TTL level signals to interface with external logic devices. This is particularly true with the EMB and the The pull-ups are enabled with a single bit for each of the Parallel Master Port (PMP), which are particularly likely ports: RBPU (INTCON2<7>) for PORTB, and RDPU, to be interfaced to TTL level logic or memory devices. REPU and RJPU (PORTG<7:5>) for the other ports. The inputs for the PMP can be optionally configured for Note: RJPU is implemented on 80-pin devices TTL buffers with the PMPTTL bit in the PADCFG1 reg- only. ister (Register10-4). Setting this bit configures all data and control input pins for the PMP to use TTL buffers. 10.1.4 OPEN-DRAIN OUTPUTS By default, these PMP inputs use the port’s ST buffers. The output pins for several peripherals are also As with the ODCON registers, the PADCFG1 register equipped with a configurable open-drain output option. resides in the SFR configuration space; it shares the This allows the peripherals to communicate with same memory address as the TMR2 register. external digital logic operating at a higher voltage level, PADCFG1 is accessed by setting the ADSHR bit without the use of level translators. (WDTCON<4>). The open-drain option is implemented on port pins specifically associated with the data and clock outputs of the EUSARTs, the MSSP modules (in SPI mode) and the CCP and ECCP modules. It is selectively enabled by setting the open-drain control bit for the correspond- ing module in the ODCON registers (Register10-1, Register10-2 and Register10-3). Their configuration is discussed in more detail with the individual port where these peripherals are multiplexed. The ODCON registers all reside in the SFR configuration space, and share the same SFR addresses as the Timer1 registers (see Section5.3.5.1 “Shared Address SFRs” for more details). The ODCON registers are accessed by setting the ADSHR bit (WDTCON<4>). DS39775C-page 138 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 10-1: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 CCP5OD:CCP4OD: CCPx Open-Drain Output Enable bits 1 = Open-drain output on CCPx pin (Capture/PWM modes) enabled 0 = Open-drain output disabled bit 2-0 ECCP3OD:ECCP1OD: ECCPx Open-Drain Output Enable bits 1 = Open-drain output on ECCPx pin (Capture mode) enabled 0 = Open-drain output disabled REGISTER 10-2: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — U2OD U1OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 U2OD:U1OD: EUSARTx Open-Drain Output Enable bits 1 = Open-drain output on TXx/CKx pin enabled 0 = Open-drain output disabled REGISTER 10-3: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SPI2OD SPI1OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 SPI2OD:SPI1OD: SPI Open-Drain Output Enable bits 1 = Open-drain output on SDOx pin enabled 0 = Open-drain output disabled © 2009 Microchip Technology Inc. DS39775C-page 139

PIC18F87J50 FAMILY REGISTER 10-4: PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers 10.2 PORTA, TRISA and For INTOSCx and INTOSCPLLx Oscillator modes LATA Registers (FOSC2 Configuration bit is ‘0’), either RA7, or both RA6 and RA7, automatically become available as digi- PORTA is a 6-bit wide, bidirectional port. The tal I/O, depending on the oscillator mode selected. corresponding Data Direction register is TRISA. The When RA6 is not configured as a digital I/O, in these corresponding Output Latch register is LATA. cases, it provides a clock output at FOSC/4. A list of the possible configurations for RA6 and RA7, based on The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. It is also multi- oscillator mode, is provided in Register10-3. For these pins, the corresponding PORTA, TRISA and LATA bits plexed as the Parallel Master Port Data pin. The other PORTA pins are multiplexed with the analog VREF+ and are only defined when the pins are configured as I/O. VREF- inputs. The operation of pins RA5:RA0 as A/D Converter inputs is selected by clearing or setting the TABLE 10-3: FUNCTION OF RA7:RA6 IN control bits in the ANCON0 register. INTOSC AND INTOSCPLL MODES Note 1: The RA5 (RA5/PMD4/AN4/C2INA) pin is a multiplexed A/D convertor, Parallel Master Oscillator Mode RA6 RA7 Port data and also a Comparator2 input A. (FOSC2:FOSC0 Configuration bits) (PMP pin placement depends on the INTOSCPLLO (011) CLKO I/O PMPMX Configuration bit.) INTOSCPLL (010) I/O I/O 2: RA5 and RA3:RA0 are configured as INTOSCO (001) CLKO I/O analog inputs on any Reset and are read as ‘0’. RA4 is configured as a digital input. INTOSC (000) I/O I/O The RA4/T0CKI pin is a Schmitt Trigger input. All other Legend: CLKO = FOSC/4 clock output; I/O = digital port. PORTA pins have TTL input levels and full CMOS output drivers. EXAMPLE 10-1: INITIALIZING PORTA The TRISA register controls the direction of the PORTA CLRF PORTA ; Initialize PORTA by pins, even when they are being used as analog inputs. ; clearing output The user must ensure the bits in the TRISA register are ; data latches maintained set when using them as analog inputs. CLRF LATA ; Alternate method to OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally ; clear data latches serve as the external circuit connections for the BSF WDTCON,ADSHR; Enable write/read to external (primary) oscillator circuit (HS and HSPLL ; the shared SFR MOVLW 1Fh ; Configure A/D Oscillator modes), or the external clock input (EC and MOVWF ANCON0 ; for digital inputs ECPLL Oscillator modes). In these cases, RA6 and BCF WDTCON,ADSHR; Disable write/read RA7 are not available as digital I/O and their ; to the shared SFR corresponding TRIS and LAT bits are read as ‘0’. MOVLW 0CFh ; Value used to ; initialize ; data direction MOVWF TRISA ; Set RA<3:0> as inputs, ; RA<5:4> as outputs DS39775C-page 140 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 10-4: PORTA FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D input channel 0. Default input configuration on POR; does not affect digital output. RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA A/D input channel 1. Default input configuration on POR; does not affect digital output. RA2/AN2/VREF- RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when CVREF output enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. AN2 1 I ANA A/D input channel 2 . Default input configuration on POR; not affected by analog output. VREF- 1 I ANA A/D low reference voltage input. RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D input channel 3. Default input configuration on POR. VREF+ 1 I ANA A/D high reference voltage input. RA4/T0CKI/ RA4 0 O DIG LATA<4> data output. PMD5 1 I ST PORTA<4> data input; default configuration on POR. T0CKI x I ST Timer0 clock input. PMD5(1,2) x O DIG Parallel Master Port data output. x I TTL Parallel Master Port data output. RA5/PMD4/ RA5 0 O DIG LATA<5> data output; not affected by analog input. AN4/C2INA 1 I TTL PORTA<5> data input; disabled when analog input enabled. PMD4(1,2) x O DIG Parallel Master Port data output. x I TTL Parallel Master Port data output. AN4 1 I ANA A/D input channel 4. Default configuration on POR. C2INA 1 I ANA Comparator2 input A. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: When PMPMX = 0. 2: Available on 80-pin devices only. © 2009 Microchip Technology Inc. DS39775C-page 141

PIC18F87J50 FAMILY TABLE 10-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 65 LATA — — LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 64 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 64 ANCON0(1) PCFG7 — — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 63 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. DS39775C-page 142 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 10.3 PORTB, TRISB and The interrupt-on-change feature is recommended for LATB Registers wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change PORTB is an 8-bit wide, bidirectional port. The corre- feature. Polling of PORTB is not recommended while sponding Data Direction register is TRISB. All pins on using the interrupt-on-change feature. PORTB are digital only and tolerate voltages up to For 80-pin devices, RB3 can be configured as the 5.5V. alternate peripheral pin for the ECCP2 module and Each of the PORTB pins has a weak internal pull-up. A Enhanced PWM output 2A by clearing the CCP2MX single control bit can turn on all the pull-ups. This is Configuration bit. This applies only to 80-pin devices performed by clearing bit, RBPU (INTCON2<7>). The operating in Extended Microcontroller mode. If the weak pull-up is automatically turned off when the port device is in Microcontroller mode, the alternate pin is configured as an output. The pull-ups are assignment for ECCP2 is RE7. As with other ECCP2 disabled on a Power-on Reset. configurations, the user must ensure that the TRISB<3> Four of the PORTB pins (RB7:RB4) have an bit is set appropriately for the intended operation. Ports, interrupt-on-change feature. Only pins configured as RB1, RB2, RB3, RB4 and RB5, are multiplexed with inputs can cause this interrupt to occur (i.e., any the Parallel Master Port address. RB7:RB4 pin configured as an output is excluded from the interrupt-on-change comparison). The input pins EXAMPLE 10-2: INITIALIZING PORTB (of RB7:RB4) are compared with the old value latched CLRF PORTB ; Initialize PORTB by on the last read of PORTB. The “mismatch” outputs of ; clearing output RB7:RB4 are ORed together to generate the RB Port ; data latches Change Interrupt with Flag bit, RBIF (INTCON<0>). CLRF LATB ; Alternate method to clear ; output data latches This interrupt can wake the device from MOVLW 0CFh ; Value used to initialize power-managed modes. The user, in the Interrupt ; data direction Service Routine, can clear the interrupt in the following MOVWF TRISB ; Set RB<3:0> as inputs manner: ; RB<5:4> as outputs ; RB<7:6> as inputs a) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). This will end the mismatch condition. b) Clear flag bit, RBIF. A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared. © 2009 Microchip Technology Inc. DS39775C-page 143

PIC18F87J50 FAMILY TABLE 10-6: PORTB FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RB0/FLT0/INT0 RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software. INT0 1 I ST External interrupt 0 input. RB1/INT1/ RB1 0 O DIG LATB<1> data output. PMA4 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. INT1 1 I ST External interrupt 1 input. PMA4 x O — Parallel Master Port address out. RB2/INT2/ RB2 0 O DIG LATB<2> data output. PMA3 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. INT2 1 I ST External interrupt 2 input. PMA3 x O — Parallel Master Port address out. RB3/INT3/ RB3 0 O DIG LATB<3> data output. ECCP2/P2A/ 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. PMA2 INT3 1 I ST External interrupt 3 input. ECCP2(1) 0 O DIG ECCP2 compare output and ECCP2 PWM output; takes priority over port data. 1 I ST ECCP2 capture input. P2A(1) 0 O DIG ECCP2 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. PMA2 x O — Parallel Master Port address out. RB4/KBI0/ RB4 0 O DIG LATB<4> data output. PMA1 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. KBI0 I TTL Interrupt-on-pin change. PMA1 x O — Parallel Master Port address out. RB5/KBI1/ RB5 0 O DIG LATB<5> data output. PMA0 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 I TTL Interrupt-on-pin change. PMA0 x O — Parallel Master Port address out. RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-pin change. PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(2) RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-pin change. PGD x O DIG Serial execution data output for ICSP and ICD operation.(2) x I ST Serial execution data input for ICSP and ICD operation.(2) Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode, 80-pin devices only). Default assignment is RC1. 2: All other pin functions are disabled when ICSP™ or ICD are enabled. DS39775C-page 144 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 10-7: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 65 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 64 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 64 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 61 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 61 Legend: Shaded cells are not used by PORTB. © 2009 Microchip Technology Inc. DS39775C-page 145

PIC18F87J50 FAMILY 10.4 PORTC, TRISC and Note: These pins are configured as digital inputs LATC Registers on any device Reset. PORTC is an 8-bit wide, bidirectional port. Only The contents of the TRISC register are affected by PORTC pins, RC2 through RC7, are digital only pins peripheral overrides. Reading TRISC always returns and can tolerate input voltages up to 5.5V. the current contents, even though a peripheral device PORTC is multiplexed with CCP, MSSP and EUSART may be overriding one or more of the pins. peripheral functions (Table10-8). The pins have Schmitt Trigger input buffers. The pins for CCP, SPI EXAMPLE 10-3: INITIALIZING PORTC and EUSART are also configurable for open-drain out- CLRF PORTC ; Initialize PORTC by put whenever these functions are active. Open-drain ; clearing output configuration is selected by setting the SPIxOD, ; data latches ECCPxOD and UxOD control bits in the ODCON regis- CLRF LATC ; Alternate method to clear ters (see Section10.1.3 “Pull-up Configuration” for ; output data latches more information). MOVLW 0CFh ; Value used to initialize ; data direction RC1 is normally configured as the default peripheral MOVWF TRISC ; Set RC<3:0> as inputs pin for the ECCP2 module. Assignment of ECCP2 is ; RC<5:4> as outputs controlled by Configuration bit, CCP2MX (default state, ; RC<7:6> as inputs CCP2MX = 1). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. DS39775C-page 146 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 10-8: PORTC FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RC0/T1OSO/ RC0 0 O DIG LATC<0> data output. T13CKI 1 I ST PORTC<0> data input. T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T13CKI 1 I ST Timer1/Timer3 counter input. RC1/T1OSI/ RC1 0 O DIG LATC<1> data output. ECCP2/P2A 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. ECCP2(1) 0 O DIG ECCP2 compare output and ECCP2 PWM output; takes priority over port data. 1 I ST ECCP2 capture input. P2A(1) 0 O DIG ECCP2 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC2/ECCP1/ RC2 0 O DIG LATC<2> data output. P1A 1 I ST PORTC<2> data input. ECCP1 0 O DIG ECCP1 compare output and ECCP1 PWM output; takes priority over port data. 1 I ST ECCP1 capture input. P1A 0 O DIG ECCP1 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC3/SCK1/ RC3 0 O DIG LATC<3> data output. SCL1 1 I ST PORTC<3> data input. SCK1 0 O DIG SPI clock output (MSSP1 module); takes priority over port data. 1 I ST SPI clock input (MSSP1 module). SCL1 0 O DIG I2C™ clock output (MSSP1 module); takes priority over port data. 1 I ST I2C clock input (MSSP1 module); input type depends on module setting. RC4/SDI1/ RC4 0 O DIG LATC<4> data output. SDA1 1 I ST PORTC<4> data input. SDI1 1 I ST SPI data input (MSSP1 module). SDA1 1 O DIG I2C data output (MSSP1 module); takes priority over port data. 1 I ST I2C data input (MSSP1 module); input type depends on module setting. RC5/SDO1/ RC5 0 O DIG LATC<5> data output. C2OUT 1 I ST PORTC<5> data input. SDO1 0 O DIG SPI data output (MSSP1 module); takes priority over port data. C2OUT x O DIG Comparator 2 output. RC6/TX1/CK1 RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX1 1 O DIG Synchronous serial data output (EUSART1 module); takes priority over port data. CK1 1 O DIG Synchronous serial data input (EUSART1 module). User must configure as an input. 1 I ST Synchronous serial clock input (EUSART1 module). Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. © 2009 Microchip Technology Inc. DS39775C-page 147

PIC18F87J50 FAMILY TABLE 10-8: PORTC FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RC7/RX1/DT1 RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX1 1 I ST Asynchronous serial receive data input (EUSART1 module). DT1 1 O DIG Synchronous serial data output (EUSART1 module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART1 module). User must configure as an input. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. TABLE 10-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 65 LATC LATC7 LATBC6 LATC5 LATCB4 LATC3 LATC2 LATC1 LATC0 64 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 64 DS39775C-page 148 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 10.5 PORTD, TRISD and Each of the PORTD pins has a weak internal pull-up. LATD Registers The pull-ups are provided to keep the inputs at a known state for the external memory interface while powering PORTD is an 8-bit wide, bidirectional port. All pins on up. A single control bit can turn off all the pull-ups. This PORTD are digital only and tolerate voltages up to is performed by clearing bit, RDPU (PORTG<7>). The 5.5V. weak pull-up is automatically turned off when the port All pins on PORTD are implemented with Schmitt pin is configured as an output. The pull-ups are Trigger input buffers. Each pin is individually disabled on all device Resets. configurable as an input or output. EXAMPLE 10-4: INITIALIZING PORTD Note: These pins are configured as digital inputs on any device Reset. CLRF PORTD ; Initialize PORTD by ; clearing output On 80-pin devices, PORTD is multiplexed with the ; data latches system bus as part of the external memory interface. CLRF LATD ; Alternate method to clear I/O port and other functions are only available when the ; output data latches interface is disabled by setting the EBDIS bit MOVLW 0CFh ; Value used to initialize (MEMCON<7>). When the interface is enabled, ; data direction PORTD is the low-order byte of the multiplexed MOVWF TRISD ; Set RD<3:0> as inputs address/data bus (AD7:AD0). The TRISD bits are also ; RD<5:4> as outputs ; RD<7:6> as inputs overridden. PORTD can also be configured to function as an 8-bit wide Parallel Master Port data. In this mode, Parallel Master Port takes priority over the other digital I/O (but not the external memory interface). This multiplexing is available when PMPMX = 1. When the Parallel Master Port is active, the input buffers are TTL. For more information, refer to Section11.0 “Parallel Master Port” © 2009 Microchip Technology Inc. DS39775C-page 149

PIC18F87J50 FAMILY TABLE 10-10: PORTD FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RD0/AD0/ RD0 0 O DIG LATD<0> data output. PMD0 1 I ST PORTD<0> data input. AD0(2) x O DIG External memory interface, address/data bit 0 output.(1) x I TTL External memory interface, data bit 0 input.(1) PMD0(3) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. RD1/AD1/ RD1 0 O DIG LATD<1> data output. PMD1 1 I ST PORTD<1> data input. AD1(2) x O DIG External memory interface, address/data bit 1 output.(1) x I TTL External memory interface, data bit 1 input.(1) PMD1(3) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. RD2/AD2/ RD2 0 O DIG LATD<2> data output. PMD2 1 I ST PORTD<2> data input. AD2(2) x O DIG External memory interface, address/data bit 2 output.(1) x I TTL External memory interface, data bit 2 input.(1) PMD2(3) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. RD3/AD3/ RD3 0 O DIG LATD<3> data output. PMD3 1 I ST PORTD<3> data input. AD3(2) x O DIG External memory interface, address/data bit 3 output.(1) x I TTL External memory interface, data bit 3 input.(1) PMD3(3) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. RD4/AD4/ RD4 0 O DIG LATD<4> data output. PMD4/SDO2 1 I ST PORTD<4> data input. AD4(2) x O DIG External memory interface, address/data bit 4 output.(1) x I TTL External memory interface, data bit 4 input.(1) PMD4(3) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. SDO2 0 O DIG SPI data output (MSSP2 module); takes priority over port data. RD5/AD5/ RD5 0 O DIG LATD<5> data output. PMD5/SDI2/ 1 I ST PORTD<5> data input. SDA2 AD5(2) x O DIG External memory interface, address/data bit 5 output.(1) x I TTL External memory interface, data bit 5 input.(1) PMD5(3) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. SDI2 1 I ST SPI data input (MSSP2 module). SDA2 1 O DIG I2C™ data output (MSSP2 module); takes priority over port data. 1 I ST I2C data input (MSSP2 module); input type depends on module setting. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PMP I/O. 2: Available on 80-pin devices only. 3: When PMPMX = 1. DS39775C-page 150 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 10-10: PORTD FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RD6/AD6/ RD6 0 O DIG LATD<6> data output. PMD6/SCK2/ 1 I ST PORTD<6> data input. SCL2 AD6(2) x O DIG-3 External memory interface, address/data bit 6 output.(1) x I TTL External memory interface, data bit 6 input.(1) PMD6(3) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. SCK2 0 O DIG SPI clock output (MSSP2 module); takes priority over port data. 1 I ST SPI clock input (MSSP2 module). SCL2 0 O DIG I2C™ clock output (MSSP2 module); takes priority over port data. 1 I ST I2C clock input (MSSP2 module); input type depends on module setting. RD7/AD7/ RD7 0 O DIG LATD<7> data output. PMD7/SS2 1 I ST PORTD<7> data input. AD7(2) x O DIG External memory interface, address/data bit 7 output.(1) x I TTL External memory interface, data bit 7 input.(1) PMD7(3) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. SS2 x I TTL Slave select input for MSSP (MSSP2 module). Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PMP I/O. 2: Available on 80-pin devices only. 3: When PMPMX = 1. TABLE 10-11: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 65 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 64 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 64 PORTG RDPU REPU RJPU(1) RG4 RG3 RG2 RG1 RG0 65 Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. DS39775C-page 151

PIC18F87J50 FAMILY 10.6 PORTE, TRISE and PORTE is also multiplexed with Enhanced PWM LATE Registers outputs B and C for ECCP1 and ECCP3 and outputs B, C and D for ECCP2. For all devices, their default PORTE is an 8-bit wide, bidirectional port. All pins on assignments are on PORTE<6:3>. On 80-pin devices, PORTE are digital only and tolerate voltages up to the multiplexing for the outputs of ECCP1 and ECCP3 5.5V. is controlled by the ECCPMX Configuration bit. All pins on PORTE are implemented with Schmitt Clearing this bit reassigns the P1B/P1C and P3B/P3C Trigger input buffers. Each pin is individually outputs to PORTH. configurable as an input or output. For devices operating in Microcontroller mode, pin RE7 can be configured as the alternate peripheral pin for the Note: These pins are configured as digital inputs ECCP2 module and Enhanced PWM output 2A. This is on any device Reset. done by clearing the CCP2MX Configuration bit. On 80-pin devices, PORTE is multiplexed with the PORTE is also multiplexed with the Parallel Master system bus as part of the external memory interface. Port address lines. When PMPMX = 0, RE1 and RE0 I/O port and other functions are only available when the are multiplexed with the control signals, PMPWR and interface is disabled, by setting the EBDIS bit PMPRD. (MEMCON<7>). When the interface is enabled, PORTE is the high-order byte of the multiplexed RE3 can also be configured as the Reference Clock address/data bus (AD15:AD8). The TRISE bits are also Output (REFO) from the system clock. for further overridden. details on this, refer to Section2.5 “Reference Clock Output”. Each of the PORTE pins has a weak internal pull-up. A single control bit can turn off all the pull-ups. This is EXAMPLE 10-5: INITIALIZING PORTE performed by clearing bit REPU (PORTG<6>). The CLRF PORTE ; Initialize PORTE by weak pull-up is automatically turned off when the port ; clearing output pin is configured as an output. The pull-ups are ; data latches disabled on any device Reset. CLRF LATE ; Alternate method to clear ; output data latches MOVLW 03h ; Value used to initialize ; data direction MOVWF TRISE ; Set RE<1:0> as inputs ; RE<7:2> as outputs DS39775C-page 152 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 10-12: PORTE FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RE0/AD8/ RE0 0 O DIG LATE<0> data output. PMRD/P2D 1 I ST PORTE<0> data input. AD8(3) x O DIG External memory interface, address/data bit 8 output.(2) x I TTL External memory interface, data bit 8 input.(2) PMRD(5) x O DIG Parallel Master Port read strobe pin. x I TTL Parallel Master Port read pin. P2D 0 O DIG ECCP2 Enhanced PWM output, channel D; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. RE1/AD9/ RE1 0 O DIG LATE<1> data output. PMWR/P2C 1 I ST PORTE<1> data input. AD9(3) x O DIG External memory interface, address/data bit 9 output.(2) x I TTL External memory interface, data bit 9 input.(2) PMWR(5) x O DIG Parallel Master Port write strobe pin. x I TTL Parallel Master Port write pin. P2C 0 O DIG ECCP2 Enhanced PWM output, channel C; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. RE2/AD10/ RE2 0 O DIG LATE<2> data output. PMBE/P2B 1 I ST PORTE<2> data input. AD10(3) x O DIG External memory interface, address/data bit 10 output.(2) x I TTL External memory interface, data bit 10 input.(2) PMBE(5) x O DIG Parallel Master Port byte enable. P2B 0 O DIG ECCP2 Enhanced PWM output, channel B; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. RE3/AD11/ RE3 0 O DIG LATE<3> data output. PMA13/P3C/ 1 I ST PORTE<3> data input. REFO AD11(3) x O DIG External memory interface, address/data bit 11 output.(2) x I TTL External memory interface, data bit 11 input.(2) PMA13 x O DIG Parallel Master Port address. P3C(1) 0 O DIG ECCP3 Enhanced PWM output, channel C; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. REFO x O DIG Reference output clock. RE4/AD12/ RE4 0 O DIG LATE<4> data output. PMA12/P3B 1 I ST PORTE<4> data input. AD12(3) x O DIG External memory interface, address/data bit 12 output.(2) x I TTL External memory interface, data bit 12 input.(2) PMA12 x O DIG Parallel Master Port address. P3B(1) 0 O DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only). 2: External memory interface I/O takes priority over all other digital and PMP I/O. 3: Available on 80-pin devices only. 4: Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller mode). 5: Default configuration for PMP (PMPMX Configuration bit=1). © 2009 Microchip Technology Inc. DS39775C-page 153

PIC18F87J50 FAMILY TABLE 10-12: PORTE FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RE5/AD13/ RE5 0 O DIG LATE<5> data output. PMA11/P1C 1 I ST PORTE<5> data input. AD13(3) x O DIG External memory interface, address/data bit 13 output.(2) x I TTL External memory interface, data bit 13 input.(2) PMA11 x O DIG Parallel Master Port address. P1C(1) 0 O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. RE6/AD14/ RE6 0 O DIG LATE<6> data output. PMA10/P1B 1 I ST PORTE<6> data input. AD14(3) x O DIG External memory interface, address/data bit 14 output.(2) x I TTL External memory interface, data bit 14 input.(2) PMA10 x O DIG Parallel Master Port address. P1B(1) 0 O DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. RE7/AD15/ RE7 0 O DIG LATE<7> data output. PMA9/ECCP2/ 1 I ST PORTE<7> data input. P2A AD15(3) x O DIG External memory interface, address/data bit 15 output.(2) x I TTL External memory interface, data bit 15 input.(2) PMA9 x O DIG Parallel Master Port address. ECCP2(4) 0 O DIG ECCP2 compare output and ECCP2 PWM output; takes priority over port data. 1 I ST ECCP2 capture input. P2A(4) 0 O DIG ECCP2 Enhanced PWM output, channel A; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only). 2: External memory interface I/O takes priority over all other digital and PMP I/O. 3: Available on 80-pin devices only. 4: Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller mode). 5: Default configuration for PMP (PMPMX Configuration bit=1). TABLE 10-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 65 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 64 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 64 PORTG RDPU REPU RJPU(1) RG4 RG3 RG2 RG1 RG0 65 Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices, read as ‘0’. DS39775C-page 154 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 10.7 PORTF, LATF and TRISF Registers When Configuration bit, PMPMX = 0, PORTF is multi- plexed with Parallel Master data port. This multiplexing PORTF is a 6-bit wide, bidirectional port. RF2, RF5 and is available only in 80 pin devices. RF6 are analog inputs. These ports are configured as analog inputs on a device Reset. EXAMPLE 10-6: INITIALIZING PORTF All pins on PORTF are implemented with Schmitt Trig- CLRF PORTF ; Initialize PORTF by ger input buffers. Each pin is individually configurable ; clearing output as an input or output. ; data latches Pins, RF3 and RF4, are multiplexed with the USB mod- CLRF LATF ; Alternate method to ; clear output latches ule. Depending on the configuration of the module, they BSF WDTCON,ADSHR ; Enable write/read to can serve as the differential data lines for the on-chip ; the shared SFR USB transceiver. Both RF3 and RF4 have Schmitt MOVLW 80h ; make RF2 digital Trigger input buffers. As digital ports, they can only MOVWF ANCON0 ; function as digital inputs; the on-chip USB transceiver MOVLW 0Ch ; make RF<6:5> digital must be disabled (UTRDIS (UCFG<3>) bit = 1) to use MOVWF ANCON1 ; the pin as digital inputs. When configured for USB oper- BCF WDTCON,ADSHR ; Disable write/read to ation, the data direction is determined automatically by ; the shared SFR the configuration and status of the USB module at any MOVLW C0h ; given time. MOVWF TRISF ; Set RF5:RF2 as outputs, ; RF<7:6> as inputs Note1: On device Resets, pins RF2, RF5 and RF6 are configured as analog inputs and are read as ‘0’. 2: To configure PORTF as digital I/O, set the corresponding bits in ANCON0 and ANCON1. © 2009 Microchip Technology Inc. DS39775C-page 155

PIC18F87J50 FAMILY TABLE 10-14: PORTF FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RF2/PMA5/ RF2 0 O DIG LATF<2> data output; not affected by analog input. AN7/C2INB 1 I ST PORTF<2> data input; disabled when analog input enabled. PMA5 x O DIG Parallel Master Port address. AN7 1 I ANA A/D input channel 7. Default configuration on POR. C2INB x I ANA Comparator 2 input B. RF3/D- RF3 1 I ST PORTF<3> data input; disabled when analog input enabled. D- O XVCR USB bus differential minus line output (internal transceiver). I XVCR USB bus differential minus line input (internal transceiver). RF4/D+ RF4 1 I ST PORTF<4> data input; disabled when analog input enabled. D+ O XVCR USB bus differential plus line output (internal transceiver). I XVCR USB bus differential plus line input (internal transceiver). RF5/PMD2/ RF5 0 O DIG LATF<5> data output; not affected by analog input. Disabled when AN10/C1INB/ CVREF output enabled. CVREF 1 I ST PORTF<5> data input; disabled when analog input enabled. Disabled when CVREF output enabled. PMD2(1) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. AN10 1 I ANA A/D input channel 10 and Comparator C1+ input. Default input configuration on POR. C1INB x I ANA Comparator 1 input B. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RF6/PMD1/ RF6 0 O DIG LATF<6> data output; not affected by analog input. AN11/C1INA 1 I ST PORTF<6> data input; disabled when analog input enabled. PMD1(1) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. AN11 1 I ANA A/D input channel 11 and Comparator C1- input. Default input configuration on POR; does not affect digital output. C1INA x I ANA Comparator 1 input A. RF7/PMD0/ RF7 0 O DIG LATF<7> data output. SS1/C1OUT 1 I ST PORTF<7> data input. PMD0(1) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. SS1 1 I TTL Slave select input for MSSP1. C1OUT x O DIG Comparator 1 output. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, XVCR = USB Transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only. DS39775C-page 156 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTF RF7 RF6 RF5 RF4 RF3 RF2 — — 65 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 — — 64 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 — — 64 ANCON0(1) PCFG7 — — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 63 ANCON1(1) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 — — 63 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. © 2009 Microchip Technology Inc. DS39775C-page 157

PIC18F87J50 FAMILY 10.8 PORTG, TRISG and Although the port itself is only five bits wide, LATG Registers PORTG<7:5>bits are still implemented. These are used to control the weak pull-ups on the I/O ports PORTG is a 5-bit wide, bidirectional port. The corre- associated with the External Memory Bus (PORTD, sponding Data Direction register is TRISG. All pins on PORTE and PORTJ). Setting these bits enables the PORTG are digital only and tolerate voltages up to pull-ups. Since these are control bits and are not 5.5V. associated with port I/O, the corresponding TRISG and PORTG is multiplexed with EUSART2 functions LATG bits are not implemented. (Table10-16). PORTG pins have Schmitt Trigger input buffers. PORTG has pins multiplexed with the Parallel EXAMPLE 10-7: INITIALIZING PORTG Master Port. CLRF PORTG ; Initialize PORTG by When enabling peripheral functions, care should be ; clearing output taken in defining TRIS bits for each PORTG pin. Some ; data latches peripherals override the TRIS bit to make a pin an CLRF LATG ; Alternate method to clear ; output data latches output, while other peripherals override the TRIS bit to MOVLW 04h ; Value used to initialize make a pin an input. The user should refer to the ; data direction corresponding peripheral section for the correct TRIS MOVWF TRISG ; Set RG1:RG0 as outputs bit settings. The pin override value is not loaded into ; RG2 as input the TRIS register. This allows read-modify-write of the ; RG4:RG3 as outputs TRIS register without concern due to peripheral overrides. DS39775C-page 158 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 10-16: PORTG FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RG0/PMA8/ RG0 0 O DIG LATG<0> data output. ECCP3/P3A 1 I ST PORTG<0> data input. PMA8 x O DIG Parallel Master Port address. ECCP3 O DIG ECCP3 compare and PWM output; takes priority over port data. I ST ECCP3 capture input. P3A 0 O DIG ECCP3 Enhanced PWM output, channel A; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. RG1/PMA7/ RG1 0 O DIG LATG<1> data output. TX2/CK2/ 1 I ST PORTG<1> data input. PMA7 x O DIG Parallel Master Port address. TX2 1 O DIG Synchronous serial data output (EUSART2 module); takes priority over port data. CK2 1 O DIG Synchronous serial data input (EUSART2 module). User must configure as an input. 1 I ST Synchronous serial clock input (EUSART2 module). RG2/PMA6/ RG2 0 O DIG LATG<2> data output. RX2/DT2 1 I ST PORTG<2> data input. PMA6 x O DIG Parallel Master Port address. RX2 1 I ST Asynchronous serial receive data input (EUSART2 module). DT2 1 O DIG Synchronous serial data output (EUSART2 module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART2 module). User must configure as an input. RG3/PMCS1/ RG3 0 O DIG LATG<3> data output. CCP4/P3D 1 I ST PORTG<3> data input. PMCS1 x O DIG Parallel Master Port address chip select 1 x I TTL Parallel Master Port address chip select 1 in. CCP4 0 O DIG CCP4 compare output and CCP4 PWM output; takes priority over port data. 1 I ST CCP4 capture input. P3D 0 O DIG ECCP3 Enhanced PWM output, channel D; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. RG4/PMCS2/ RG4 0 O DIG LATG<4> data output. CCP5/P1D 1 I ST PORTG<4> data input. PMCS2 x O DIG Parallel Master Port address chip select 2 CCP5 0 O DIG CCP5 compare output and CCP5 PWM output; takes priority over port data. 1 I ST CCP5 capture input. P1D 0 O DIG ECCP1 Enhanced PWM output, channel D; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. DS39775C-page 159

PIC18F87J50 FAMILY TABLE 10-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTG RDPU REPU RJPU(1) RG4 RG3 RG2 RG1 RG0 65 LATG — — — LATG4 LATG3 LATG2 LATG1 LATG0 64 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 64 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: Unimplemented on 64-pin devices, read as ‘0’. DS39775C-page 160 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 10.9 PORTH, LATH and PORTH can also be configured as the alternate TRISH Registers Enhanced PWM output channels B and C for the ECCP1 and ECCP3 modules. This is done by clearing Note: PORTH is available only on 80-pin the ECCPMX Configuration bit. devices. EXAMPLE 10-8: INITIALIZING PORTH PORTH is an 8-bit wide, bidirectional I/O port. PORTH pins <3:0> are digital only and tolerate voltages up to CLRF PORTH ; Initialize PORTH by ; clearing output 5.5V. ; data latches All pins on PORTH are implemented with Schmitt CLRF LATH ; Alternate method to Trigger input buffers. Each pin is individually ; clear output latches configurable as an input or output. BSF WDTCON,ADSHR; Enable write/read to ; the shared SFR When the external memory interface is enabled, four of MOVLW F0h ; Configure PORTH as the PORTH pins function as the high-order address MOVWF ANCON1 ; digital I/O lines for the interface. The address output from the BCF WDTCON,ADSHR; Disable write/read to interface takes priority over other digital I/O. The ; the shared SFR corresponding TRISH bits are also overridden. PORTH MOVLW 0CFh ; Value used to initialize pins, RH4 through RH7, are multiplexed with analog ; data direction converter inputs. The operation of these pins as analog MOVWF TRISH ; Set RH3:RH0 as inputs inputs is selected by clearing or setting the ; RH5:RH4 as outputs ; RH7:RH6 as inputs corresponding bits in the ANCON1 register. RH3 to RH6 is multiplexed with Parallel Master Port and RH4 to RH6 are multiplexed as comparator pins. © 2009 Microchip Technology Inc. DS39775C-page 161

PIC18F87J50 FAMILY TABLE 10-18: PORTH FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RH0/A16 RH0 0 O DIG LATH<0> data output. 1 I ST PORTH<0> data input. A16 x O DIG External memory interface, address line 16. Takes priority over port data. RH1/A17 RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. A17 x O DIG External memory interface, address line 17. Takes priority over port data. RH2/A18/ RH2 0 O DIG LATH<2> data output. PMD7 1 I ST PORTH<2> data input. A18 x O DIG External memory interface, address line 18. Takes priority over port data. PMD7(2) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. RH3/A19/ RH3 0 O DIG LATH<3> data output. PMD6 1 I ST PORTH<3> data input. A19 x O DIG External memory interface, address line 19. Takes priority over port data. PMD6(2) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. RH4/PMD3/ RH4 0 O DIG LATH<4> data output. AN12/P3C/ 1 I ST PORTH<4> data input. C2INC PMD3(2) X I TTL Parallel Master Port data out. X O DIG Parallel Master Port data input. AN12 I ANA A/D input channel 12. Default input configuration on POR; does not affect digital output. P3C(1) 0 O DIG ECCP3 Enhanced PWM output, channel C; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. C2INC x I ANA Comparator 2 input C. RH5/PMBE/ RH5 0 O DIG LATH<5> data output. AN13/P3B/ 1 I ST PORTH<5> data input. C2IND PMBE(2) x O DIG Parallel Master Port Data byte enable. AN13 I ANA A/D input channel 13. Default input configuration on POR; does not affect digital output. P3B(1) 0 O DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. C2IND x I ANA Comparator 2 input D. RH6/PMRD/ RH6 0 O DIG LATH<6> data output. AN14/P1C/ 1 I ST PORTH<6> data input. C1INC PMRD(2) x O DIG Parallel Master Port read strobe. x I TTL Parallel Master Port read in. AN14 I ANA A/D input channel 14. Default input configuration on POR; does not affect digital output. P1C(1) 0 O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. C1INC x I ANA Comparator 1 input C. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is cleared. Default assignments are PORTE<6:3>. 2: When PMPMX = 0. DS39775C-page 162 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 10-18: PORTH FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RH7/PMWR/ RH7 0 O DIG LATH<7> data output. AN15/P1B/ 1 I ST PORTH<7> data input. PMWR(2) x O DIG Parallel Master Port write strobe. x I TTL Parallel Master Port write in. AN15 I ANA A/D input channel 15. Default input configuration on POR; does not affect digital output. P1B(1) 0 O DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is cleared. Default assignments are PORTE<6:3>. 2: When PMPMX = 0. TABLE 10-19: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTH(1) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 64 LATH(1) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 65 TRISH(1) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 64 ANCON1(2) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 — — 63 Legend: Shaded cells are not used by PORTH. Note 1: Unimplemented on 64-pin devices, read as ‘0’. 2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. © 2009 Microchip Technology Inc. DS39775C-page 163

PIC18F87J50 FAMILY 10.10 PORTJ, TRISJ and Each of the PORTJ pins has a weak internal pull-up. LATJ Registers The pull-ups are provided to keep the inputs at a known state for the external memory interface while powering Note: PORTJ is available only on 80-pin devices. up. A single control bit can turn off all the pull-ups. This is performed by clearing bit RJPU (PORTG<5>). The PORTJ is an 8-bit wide, bidirectional port. All pins on weak pull-up is automatically turned off when the port PORTJ are digital only and tolerate voltages up to 5.5V. pin is configured as an output. The pull-ups are All pins on PORTJ are implemented with Schmitt disabled on any device Reset. Trigger input buffers. Each pin is individually configurable as an input or output. EXAMPLE 10-9: INITIALIZING PORTJ Note: These pins are configured as digital inputs CLRF PORTJ ; Initialize PORTG by on any device Reset. ; clearing output ; data latches When the external memory interface is enabled, all of CLRF LATJ ; Alternate method to clear the PORTJ pins function as control outputs for the ; output data latches interface. This occurs automatically when the interface MOVLW 0CFh ; Value used to initialize is enabled by clearing the EBDIS control bit ; data direction (MEMCON<7>). The TRISJ bits are also overridden. MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs DS39775C-page 164 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 10-20: PORTJ FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RJ0/ALE RJ0 0 O DIG LATJ<0> data output. 1 I ST PORTJ<0> data input. ALE x O DIG External memory interface address latch enable control output; takes priority over digital I/O. RJ1/OE RJ1 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input. OE x O DIG External memory interface output enable control output; takes priority over digital I/O. RJ2/WRL RJ2 0 O DIG LATJ<2> data output. 1 I ST PORTJ<2> data input. WRL x O DIG External Memory Bus write low byte control; takes priority over digital I/O. RJ3/WRH RJ3 0 O DIG LATJ<3> data output. 1 I ST PORTJ<3> data input. WRH x O DIG External memory interface write high byte control output; takes priority over digital I/O. RJ4/BA0 RJ4 0 O DIG LATJ<4> data output. 1 I ST PORTJ<4> data input. BA0 x O DIG External memory interface byte address 0 control output; takes priority over digital I/O. RJ5/CE RJ5 0 O DIG LATJ<5> data output. 1 I ST PORTJ<5> data input. CE x O DIG External memory interface chip enable control output; takes priority over digital I/O. RJ6/LB RJ6 0 O DIG LATJ<6> data output. 1 I ST PORTJ<6> data input. LB x O DIG External memory interface lower byte enable control output; takes priority over digital I/O. RJ7/UB RJ7 0 O DIG LATJ<7> data output. 1 I ST PORTJ<7> data input. UB x O DIG External memory interface upper byte enable control output; takes priority over digital I/O. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 10-21: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTJ(1) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 65 LATJ(1) LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 64 TRISJ(1) TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 64 PORTG RDPU REPU RJPU(1) RG4 RG3 RG2 RG1 RG0 65 Legend: Shaded cells are not used by PORTJ. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. DS39775C-page 165

PIC18F87J50 FAMILY NOTES: DS39775C-page 166 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 11.0 PARALLEL MASTER PORT Key features of the PMP module include: • Up to 16 Programmable Address Lines The Parallel Master Port module (PMP) is a parallel, 8-bit I/O module, specifically designed to communicate • Up to Two Chip Select Lines with a wide variety of parallel devices, such as commu- • Programmable Strobe Options nication peripherals, LCDs, external memory devices - Individual Read and Write Strobes or; and microcontrollers. Because the interface to parallel - Read/Write Strobe with Enable Strobe peripherals varies significantly, the PMP is highly • Address Auto-Increment/Auto-Decrement configurable. The PMP module can be configured to • Programmable Address/Data Multiplexing serve as either a Parallel Master Port or as a Parallel Slave Port. • Programmable Polarity on Control Signals • Legacy Parallel Slave Port Support • Enhanced Parallel Slave Support - Address Support - 4-Byte Deep, Auto-Incrementing Buffer • Programmable Wait States • Selectable Input Voltage Levels FIGURE 11-1: PMP MODULE OVERVIEW Address Bus Data Bus Control Lines PMA<0> PIC18 PMALL Parallel Master Port PMA<1> PMALH Up to 16-Bit Address PMA<13:2> EEPROM PMA<14> PMCS1 PMA<15> PMCS2 PMBE FIFO Microcontroller LCD PMRD Buffer PMRD/PMWR PMWR PMENB PMD<7:0> PMA<7:0> PMA<15:8> 8-Bit Data © 2009 Microchip Technology Inc. DS39775C-page 167

PIC18F87J50 FAMILY 11.1 Module Registers The PMCON registers (Register11-1 and Register11-2) control basic module operations, includ- The PMP module has a total of 14 Special Function ing turning the module on or off. They also configure Registers for its operation, plus one additional register address multiplexing and control strobe configuration. to set configuration options. Of these, 8 registers are The PMMODE registers (Register11-3 and used for control and 6 are used for PMP data transfer. Register11-4) configure the various Master and Slave 11.1.1 CONTROL REGISTERS operating modes, the data width and interrupt generation. The eight PMP Control registers are: The PMEH and PMEL registers (Register11-5 and • PMCONH and PMCONL Register11-6) configure the module’s operation at the • PMMODEH and PMMODEL hardware (I/O pin) level. • PMSTATL and PMSTATH The PMSTAT registers (Register11-5 and Register11-6) provide status flags for the module’s • PMEH and PMEL input and output buffers, depending on the operating mode. REGISTER 11-1: PMCONH: PARALLEL PORT CONTROL REGISTER HIGH BYTE R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed bit 6 Unimplemented: Read as ‘0’ bit 5 PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 4-3 ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8> 00 = Address and data appear on separate pins bit 2 PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled bit 1 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled bit 0 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled DS39775C-page 168 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 11-2: PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE R/W-0 R/W-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CSF1:CSF0: Chip Select Function bits 11 = Reserved 10 = PMCS1 and PMCS2 function as chip select 01 = PMCS2 functions as chip select, PMCS1 used as address bit 14 (PMADDRH address bit 6) 00 = PMCS2 and PMCS1 used as address bits 15 and 14 (PMADDRH address bits 7 and 6) bit 5 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 CS2P: Chip Select 2 Polarity bit(1) 1 = Active-high (PMCS2) 0 = Active-low (PMCS2) bit 3 CS1P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS1/PMCS) 0 = Active-low (PMCS1/PMCS) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODEH<1:0>=00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master Mode 1 (PMMODEH<1:0>=11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODEH<1:0>=00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master Mode 1 (PMMODEH<1:0>=11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. DS39775C-page 169

PIC18F87J50 FAMILY REGISTER 11-3: PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 6-5 IRQM1:IRQM0: Interrupt Request Mode bits 11 = Interrupt generated when read buffer 3 is read or write buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated bit 4-3 INCM1:INCM0: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR<15,13:0> by 1 every read/write cycle 01 = Increment ADDR<15,13:0> by 1 every read/write cycle 00 = No increment or decrement of address bit 2 MODE16: 8/16-Bit Mode bit 1 = 16-Bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers 0 = 8-Bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer bit 1-0 MODE1:MODE0: Parallel Port Mode Select bits 11 = Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>) 10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>) 01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>) DS39775C-page 170 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 11-4: PMMODEL: PARALLEL PORT MODE REGISTER LOW BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITB1(1) WAITB0(1) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(1) WAITE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits(1) 11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY bit 5-2 WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY ... 0001 = Wait of additional 1 TCY 0000 = No additional wait cycles (operation forced into one TCY) bit 1-0 WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits(1) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000. REGISTER 11-5: PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PTEN15:PTEN14: PMCSx Strobe Enable bits 1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1 0 = PMA15 and PMA14 function as port I/O bit 5-0 PTEN13:PTEN8: PMP Address Port Enable bits 1 = PMA<13:8> function as PMP address lines 0 = PMA<13:8> function as port I/O © 2009 Microchip Technology Inc. DS39775C-page 171

PIC18F87J50 FAMILY REGISTER 11-6: PMEL: PARALLEL PORT ENABLE REGISTER LOW BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 PTEN7:PTEN2: PMP Address Port Enable bits 1 = PMA<7:2> function as PMP address lines 0 = PMA<7:2> function as port I/O bit 1-0 PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O REGISTER 11-7: PMSTATH: PARALLEL PORT STATUS REGISTER HIGH BYTE R-0 R/W-0 U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 6 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 IB3F:IB0F: Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data DS39775C-page 172 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 11-8: PMSTATL: PARALLEL PORT STATUS REGISTER LOW BYTE R-1 R/W-0 U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OB3E:OB0E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted © 2009 Microchip Technology Inc. DS39775C-page 173

PIC18F87J50 FAMILY 11.1.2 DATA REGISTERS upper two bits of the register can be used to determine the operation of chip select signals. If chip select The PMP module uses 6 registers for transferring data signals are not used, PMADDR simply functions to hold into and out of the microcontroller. They are arranged the upper 8 bits of the address. The function of the as three pairs to allow the option of 16-bit data individual bits in PMADDRH is shown in Register11-9. operations: The PMDOUT2H and PMDOUT2L registers are only • PMDIN1H and PMDIN1L used in Buffered Slave modes and serve as a buffer for • PMDIN2H and PMDIN2L outgoing data. • PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L • PMDOUT2H and PMDOUT2L 11.1.3 PAD CONFIGURATION CONTROL REGISTER The PMDIN1 register is used for incoming data in Slave modes, and both input and output data in Master In addition to the module level configuration options, modes. The PMDIN2 register is used for buffering input the PMP module can also be configured at the I/O pin data in select Slave modes. for electrical operation. This option allows users to select either the normal Schmitt Trigger input buffer on The PMADDRx/PMDOUT1x registers are actually a digital I/O pins shared with the PMP, or use TTL level single register pair; the name and function is dictated compatible buffers instead. Buffer configuration is by the module’s operating mode. In Master modes, the controlled by the PMPTTL bit in the PADCFG1 register. registers functions as the PMADDRH and PMADDRL registers, and contain the address of any incoming or The PADCFG1 register is one of the shared address outgoing data. In Slave modes, the registers function SFRs, and has the same address as the TMR2 regis- as PMDOUT1H and PMDOUT1L and are used for ter. PADCFG1 is accessed by setting the ADSHR bit outgoing data. (WDTCON<4>). Refer to Section5.3.5.1 “Shared Address SFRs” for more information. PMADDRH differs from PMADDRL in that it can also have limited PMP control functions. When the module is operating in select Master mode configurations, the REGISTER 11-9: PMADDRH: PARALLEL PORT ADDRESS REGISTER, HIGH BYTE (MASTER MODES ONLY)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS2 CS1 ADDR<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CS2: Chip Select 2 bit If PMCON<7:6> = 10 or 01: 1 = Chip select 2 is active 0 = Chip select 2 is inactive If PMCON<7:6> = 11 or 00: Bit functions as ADDR<15>. bit 6 CS1: Chip Select 1 bit If PMCON<7:6> = 10: 1 = Chip select 1 is active 0 = Chip select 1 is inactive If PMCON<7:6> = 11 or 0x: Bit functions as ADDR<14>. bit 5-0 ADDR5:ADDR0: Parallel Port Destination Address bits Note 1: In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers. DS39775C-page 174 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 11.1.4 PMP MULTIPLEXING 11.2 Slave Port Modes OPTIONS(80-PINS DEVICES) The primary mode of operation for the module is con- By default, the PMP and the External Memory Bus figured using the MODE1:MODE0 bits in the (EMB) multiplex some of their signals to the same I/O PMMODEH register. The setting affects whether the pins on PORTD and PORTE. It is possible that some module acts as a slave or a master and it determines applications may require the use of both modules at the the usage of the control pins. same time. For these instances, the 80-pin devices can be configured to multiplex the PMP to different I/O 11.2.1 LEGACY MODE (PSP) ports. PMP configuration is determined by the PMPMX In Legacy mode (PMMODEH<1:0>=00 and Configuration bit setting; by default, the PMP and EMB PMPEN=1), the module is configured as a Parallel modules share PORTD and PORTE. The optional pin Slave Port with the associated enabled module pins configuration is shown in Table 11-1. dedicated to the module. In this mode, an external device, such as another microcontroller or micro- TABLE 11-1: PMP PIN MULTIPLEXING processor, can asynchronously read and write data 80-PIN DEVICES using the 8-bit data bus (PMD<7:0>), the read (PMRD), Pin Assignment write (PMWR) and chip select (PMCS1) inputs. It acts PMP as a slave on the bus and responds to the read/write Function PMPMX = 1 PMPMX= 0 control signals. PMD0 PORTD<0> PORTF<7> Figure11-2 shows the connection of the Parallel Slave Port. When chip select is active and a write strobe PMD1 PORTD<1> PORTF<6> occurs (PMCS = 1 and PMWR = 1), the data from PMD2 PORTD<2> PORTF<5> PMD<7:0> is captured into the PMDIN1L register. PMD3 PORTD<3> PORTH<4> PMD4 PORTD<4> PORTA<5> PMD5 PORTD<5> PORTA<4> PMD6 PORTD<6> PORTH<3> PMD7 PORTD<7> PORTH<2> PMBE PORTE<2> PORTH<5> PMWR PORTE<1> PORTH<7> PMRD PORTE<0> PORTH<6> FIGURE 11-2: LEGACY PARALLEL SLAVE PORT EXAMPLE Address Bus Master PIC18 Slave Data Bus PMD<7:0> PMD<7:0> Control Lines PMCS PMCS1 PMRD PMRD PMWR PMWR © 2009 Microchip Technology Inc. DS39775C-page 175

PIC18F87J50 FAMILY 11.2.2 WRITE TO SLAVE PORT 11.2.3 READ FROM SLAVE PORT When chip select is active and a write strobe occurs When chip select is active and a read strobe occurs (PMCS=1 and PMWR=1), the data from PMD<7:0> (PMCS=1 and PMRD=1), the data from the is captured into the lower PMDIN1L register. The PMDOUTL1 register (PMDOUTL1<7:0>) is presented PMPIF and IBF flag bits are set when the write onto PMD<7:0>.The timing for the control signals in ends.The timing for the control signals in Write mode is Read mode is shown in Figure11-4. shown in Figure11-3. The polarity of the control signals are configurable. FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS1 PMWR PMRD PMD<7:0> IBF OBE PMPIF FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS1 PMWR PMRD PMD<7:0> IBF OBE PMPIF DS39775C-page 176 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 11.2.4 BUFFERED PARALLEL SLAVE flow is generated, and the Buffer Overflow flag bit PORT MODE OBUF is set. If all four OBxE status bits are set, then the Output Buffer Empty flag (OBE) will also be set. Buffered Parallel Slave Port mode is functionally iden- tical to the legacy Parallel Slave Port mode with one 11.2.4.2 WRITE TO SLAVE PORT exception: the implementation of 4-level read and write buffers. Buffered PSP mode is enabled by setting the For write operations, the data is be stored sequentially, INCM bits in the PMMODEH register. If the INCM<1:0> starting with Buffer 0 (PMDIN1L<7:0>) and ending with Buffer 3 (PMDIN2H<7:0). As with read operations, the bits are set to ‘11’, the PMP module will act as the buffered Parallel Slave Port. module maintains an internal pointer to the buffer that is to be written next. When the Buffered mode is active, the PMDIN1L, PMDIN1H, PMDIN2L and PMDIN2H registers become The input buffers have their own write status bits, IBxF the write buffers and the PMDOUT1L, PMDOUT1H, in the PMSTATH register. The bit is set when the buffer PMDOUT2L and PMDOUT2H registers become the contains unread incoming data, and cleared when the read buffers. Buffers are numbered 0 through 3, start- data has been read. The flag bit is set on the write strobe. If a write occurs on a buffer when its associated ing with the lower byte of PMDIN1L to PMDIN2H as the read buffers and PMDOUT1L to PMDOUT2H as the IBxF bit is set, the Buffer Overflow flag, IBOV, is set; any incoming data in the buffer will be lost. If all four write buffers. IBxF flags are set, the Input Buffer Full Flag (IBF) is set. 11.2.4.1 READ FROM SLAVE PORT In Buffered Slave mode, the module can be configured For read operations, the bytes will be sent out sequen- to generate an interrupt on every read or write strobe tially, starting with Buffer 0 (PMDOUT1L<7:0>) and (IRQM1:IRQM0=01). It can be configured to generate ending with Buffer 3 (PMDOUT2H<7:0>) for every read an interrupt on a read from Read Buffer 3 or a write to strobe. The module maintains an internal pointer to Write Buffer 3, which is essentially an interrupt every keep track of which buffer is to be read. Each of the fourth read or write strobe (RQM1:IRQM0=11). When buffers has a corresponding read status bit, OBxE, in interrupting every fourth byte for input data, all input the PMSTATL register. This bit is cleared when a buffer buffer registers should be read to clear the IBxF flags. contains data that has not been written to the bus, and If these flags are not cleared, then there is a risk of is set when data is written to the bus. If the current hitting an overflow condition. buffer location being read from is empty, a buffer under- FIGURE 11-5: PARALLEL MASTER/SLAVE CONNECTION BUFFERED EXAMPLE Master PIC18 Slave PMD<7:0> Write Read PMD<7:0> Address Address Pointer Pointer PMDOUT1L (0) PMDIN1L (0) PMCS PMCS1 PMDOUT1H (1) PMDIN1H (1) PMRD PMRD PMDOUT2L (2) PMDIN2L (2) PMWR PMWR PMDOUT2H (3) PMDIN2H (3) Data Bus Control Lines © 2009 Microchip Technology Inc. DS39775C-page 177

PIC18F87J50 FAMILY 11.2.5 ADDRESSABLE PARALLEL SLAVE TABLE 11-2: SLAVE MODE BUFFER PORT MODE ADDRESSING In the Addressable Parallel Slave Port mode Output Input Register (PMMODEH<1:0>=01), the module is configured with PMADDR<1:0> Register (Buffer) two extra inputs, PMA<1:0>, which are the address (Buffer) lines 1 and 0. This makes the 4-byte buffer space 00 PMDOUT1L (0) PMDIN1L (0) directly addressable as fixed pairs of read and write buffers. As with legacy Buffered mode, data is output 01 PMDOUT1H (1) PMDIN1H (1) from PMDOUT1L, PMDOUT1H, PMDOUT2L and 10 PMDOUT2L (2) PMDIN2L (2) PMDOUT2H, and is read in PMDIN1L, PMDIN1H, 11 PMDOUT2H((3) PMDIN2H (3) PMDIN2L and PMDIN2H. Table11-2 shows the buffer addressing for the incoming address to the input and output registers. FIGURE 11-6: PARALLEL MASTER/SLAVE CONNECTION ADDRESSED BUFFER EXAMPLE Master PIC18F Slave PMA<1:0> PMA<1:0> PMD<7:0> Write Read PMD<7:0> Address Address Decode Decode PMDOUT1L (0) PMDIN1L (0) PMCS PMCS1 PMDOUT1H (1) PMDIN1H (1) PMRD PMRD PMDOUT2L (2) PMDIN2L (2) PMWR PMWR PMDOUT2H (3) PMDIN2H (3) Address Bus Data Bus Control Lines DS39775C-page 178 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 11.2.5.1 READ FROM SLAVE PORT output registers and their associated address. When an output buffer is read, the corresponding OBxE bit is set. When chip select is active and a read strobe occurs The OBxE flag bit is set when all the buffers are empty. (PMCS = 1 and PMRD = 1), the data from one of the If any buffer is already empty, OBxE = 1, the next read four output bytes is presented onto PMD<7:0>. Which to that buffer will generate an OBUF event. byte is read depends on the 2-bit address placed on ADDR[1:0]. Table11-2 shows the corresponding FIGURE 11-7: PARALLEL SLAVE PORT READ WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD<7:0> PMA<1:0> OBE PMPIF 11.2.5.2 WRITE TO SLAVE PORT When an input buffer is written, the corresponding IBxF bit is set. The IBF flag bit is set when all the buffers are When chip select is active and a write strobe occurs written. If any buffer is already written (IBxF = 1), the (PMCS = 1 and PMWR = 1), the data from PMD<7:0> next write strobe to that buffer will generate an OBUF is captured into one of the four input buffer bytes. event and the byte will be discarded. Which byte is written depends on the 2-bit address placed on ADDRL[1:0]. Table11-2 shows the corre- sponding input registers and their associated address. FIGURE 11-8: PARALLEL SLAVE PORT WRITE WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD<7:0> PMA<1:0> IBF PMPIF © 2009 Microchip Technology Inc. DS39775C-page 179

PIC18F87J50 FAMILY 11.3 MASTER PORT MODES Note that the polarity of control signals that share the same output pin (for example, PMWR and PMENB) are In its Master modes, the PMP module provides an 8-bit controlled by the same bit; the configuration depends data bus, up to 16 bits of address, and all the necessary on which Master Port mode is being used. control signals to operate a variety of external parallel devices, such as memory devices, peripherals and 11.3.3 DATA WIDTH slave microcontrollers. To use the PMP as a master, The PMP supports data widths of both 8 and 16 bits. the module must be enabled (PMPEN = 1) and the The data width is selected by the MODE16 bit mode must be set to one of the two possible Master (PMMODEH<2>). Because the data path into and out modes (PMMODEH<1:0> = 10 or 11). of the module is only 8 bits wide, 16-bit operations are Because there are a number of parallel devices with a always handled in a multiplexed fashion, with the Least variety of control methods, the PMP module is Significant Byte of data being presented first. To differ- designed to be extremely flexible to accommodate a entiate data bytes, the Byte Enable control strobe, range of configurations. Some of these features PMBE, is used to signal when the Most Significant Byte include: of data is being presented on the data lines. • 8 and 16-Bit Data modes on an 8-bit data bus 11.3.4 ADDRESS MULTIPLEXING • Configurable address/data multiplexing • Up to two chip select lines In either of the Master modes (PMMODEH<1:0> = 1x), the user can configure the address bus to be multiplexed • Up to 16 selectable address lines together with the data bus. This is accomplished using • Address auto-increment and auto-decrement the ADRMUX1:ADRMUX0 bits (PMCONH<4:3>). There • Selectable polarity on all control lines are three address multiplexing modes available; typical • Configurable wait states at different stages of the pinout configurations for these modes are shown in read/write cycle Figure11-9, Figure11-10 and Figure11-11. In Demultiplexed mode (PMCONH<4:3> = 00), data 11.3.1 PMP AND I/O PIN CONTROL and address information are completely separated. Multiple control bits are used to configure the presence Data bits are presented on PMD<7:0>, and address or absence of control and address signals in the mod- bits are presented on PMADDRH<7:0> and ule. These bits are PTBEEN, PTWREN, PTRDEN, and PMADDRL<7:0> PTEN<15:0>. They give the user the ability to conserve In Partially Multiplexed mode (PMCONH<4:3> = 01), pins for other functions and allow flexibility to control the lower eight bits of the address are multiplexed with the external address. When any one of these bits is set, the data pins on PMD<7:0>. The upper eight bits of the associated function is present on its associated pin; address are unaffected and are presented on when clear, the associated pin reverts to its defined I/O PMADDRH<7:0>. The PMA0 pin is used as an port function. Address Latch, and presents the Address Latch Low Setting a PTEN bit will enable the associated pin as an enable strobe (PMALL). The read and write sequences address pin and drive the corresponding data con- are extended by a complete CPU cycle during which tained in the PMADDR register. Clearing the PTENx bit the address is presented on the PMD<7:0> pins. will force the pin to revert to its original I/O function. In Fully Multiplexed mode (PMCONH<4:3> = 10), the For the pins configured as chip select (PMCS1 or entire 16 bits of the address are multiplexed with the PMCS2) with the corresponding PTENx bit set. The data pins on PMD<7:0>. The PMA0 and PMA1 pins are PTEN0 and PTEN1 bits also control the PMALL and used to present Address Latch Low enable (PMALL) PMALH signals. When multiplexing is used, the and Address Latch High enable (PMALH) strobes, associated address latch signals should be enabled. respectively. The read and write sequences are extended by two complete CPU cycles. During the first 11.3.2 READ/WRITE CONTROL cycle, the lower eight bits of the address are presented The PMP module supports two distinct read/write on the PMD<7:0> pins with the PMALL strobe active. signaling methods. In Master Mode 1, read and write During the second cycle, the upper eight bits of the strobe are combined into a single control line, address are presented on the PMD<7:0> pins with the PMRD/PMWR. A second control line, PMENB, deter- PMALH strobe active. In the event the upper address mines when a read or write action is to be taken. In bits are configured as chip select pins, the Master Mode 2, separate Read and Write strobes corresponding address bits are automatically forced (PMRD and PMWR) are supplied on separate pins. to‘0’. All control signals (PMRD, PMWR, PMBE, PMENB, PMAL and PMCSx) can be individually configured as either positive or negative polarity. Configuration is controlled by separate bits in the PMCONL register. DS39775C-page 180 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 11-9: DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F PMA<13:0> PMD<7:0> PMCS1 PMCS2 Address Bus PMRD Data Bus PMWR Control Lines FIGURE 11-10: PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F PMA<13:8> PMD<7:0> PMA<7:0> PMCS1 PMCS2 Address Bus PMALL Multiplexed Data and PMRD Address Bus PMWR Control Lines FIGURE 11-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PMD<7:0> PIC18F PMA<13:8> PMCS1 PMCS2 PMALL PMALH Multiplexed Data and PMRD Address Bus PMWR Control Lines © 2009 Microchip Technology Inc. DS39775C-page 181

PIC18F87J50 FAMILY 11.3.5 CHIP SELECT FEATURES If the 16-bit mode is enabled (MODE16 = 1), the read of the low byte of the PMDIN1L register will initiate two Up to two chip select lines, PMCS1 and PMCS2, are bus reads. The first read data byte is placed into the available for the Master modes of the PMP. The two PMDIN1L register, and the second read data is placed chip select lines are multiplexed with the Most Signifi- into the PMDIN1H. cant bits of the address bus (PMADDRH<6> and PMADDRH<7>). When a pin is configured as a chip Note that the read data obtained from the PMDIN1L select, it is not included in any address auto-increment/ register is actually the read value from the previous decrement. The function of the chip select signals is read operation. Hence, the first user read will be a configured using the chip select function bits dummy read to initiate the first bus read and fill the read (PMCONL<7:6>). register. Also, the requested read value will not be ready until after the BUSY bit is observed low. Thus, in 11.3.6 AUTO-INCREMENT/DECREMENT a back-to-back read operation, the data read from the register will be the same for both reads. The next read While the module is operating in one of the Master of the register will yield the new value. modes, the INCM bits (PMMODEH<3:4>) control the behavior of the address value. The address can be 11.3.9 WRITE OPERATION made to automatically increment or decrement after each read and write operation. The address increments To perform a write onto the parallel bus, the user writes once each operation is completed and the BUSY bit to the PMDIN1L register. This causes the module to goes to ‘0’. If the chip select signals are disabled and first output the desired values on the chip select lines configured as address bits, the bits will participate in and the address bus. The write data from the PMDIN1L the increment and decrement operations; otherwise, register is placed onto the PMD<7:0> data bus. Then the CS2 and CS1 bit values will be unaffected. the write line (PMWR) is strobed. If the 16-bit mode is enabled (MODE16 = 1), the write to the PMDIN1L reg- 11.3.7 WAIT STATES ister will initiate two bus writes. First write will consist of the data contained in PMDIN1L and the second write In Master mode, the user has control over the duration will contain the PMDIN1H. of the read, write and address cycles by configuring the module wait states. Three portions of the cycle, the 11.3.10 PARALLEL MASTER PORT STATUS beginning, middle and end, are configured using the corresponding WAITBx, WAITMx and WAITEx bits in 11.3.10.1 The BUSY Bit the PMMODEL register. In addition to the PMP interrupt, a BUSY bit is provided The WAITB bits (PMMODEL<7:6>) set the number of to indicate the status of the module. This bit is only wait cycles for the data setup prior to the PMRD/PMWT used in Master mode. While any read or write operation strobe in Mode 10, or prior to the PMENB strobe in is in progress, the BUSY bit is set for all but the very last Mode 11. The WAITM bits (PMMODEL<5:2>) set the CPU cycle of the operation. In effect, if a single-cycle number of wait cycles for the PMRD/PMWT strobe in read or write operation is requested, the BUSY bit will Mode 10, or for the PMENB strobe in Mode 11. When never be active. This allows back-to-back transfers. this wait state setting is 0 then WAITB and WAITE have While the bit is set, any request by the user to initiate a no effect. The WAITE bits (PMMODEL<1:0>) define new operation will be ignored (i.e., writing or reading the number of wait cycles for the data hold time after the lower byte of the PMDIN1L register will not initiate the PMRD/PMWT strobe in Mode 10, or after the either a read nor a write). PMENB strobe in Mode 11. 11.3.10.2 INTERRUPTS 11.3.8 READ OPERATION When the PMP module interrupt is enabled for Master To perform a read on the Parallel Master Port, the user mode, the module will interrupt on every completed reads the PMDIN1L register. This causes the PMP to read or write cycle; otherwise, the BUSY bit is available output the desired values on the chip select lines and to query the status of the module. the address bus. Then the read line (PMRD) is strobed. The read data is placed into the PMDIN1L register. DS39775C-page 182 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 11.3.11 MASTER MODE TIMING This section contains a number of timing examples that represent the common Master mode configuration options. These options vary from 8-bit to 16-bit data, fully demultiplexed to fully multiplexed address, as well as wait states. FIGURE 11-12: READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> PMA<13:0> PMWR PMRD PMPIF BUSY FIGURE 11-13: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> Address<7:0> Data PMA<13:8> PMWR PMRD PMALL PMPIF BUSY FIGURE 11-14: READ TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - PMCS2 PMCS1 PMD<7:0> Address<7:0> Data PMA<13:8> PMRD PMWR PMALL PMPIF BUSY WAITB<1:0> = 01 WAITE<1:0> = 00 WAITM<3:0> = 0010 © 2009 Microchip Technology Inc. DS39775C-page 183

PIC18F87J50 FAMILY FIGURE 11-15: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> Address<7:0> Data PMA<13:8> PMWR PMRD PMALL PMPIF BUSY FIGURE 11-16: WRITE TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - PMCS2 PMCS1 PMD<7:0> Address<7:0> Data PMA<13:8> PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> = 01 WAITE<1:0> = 00 WAITM<3:0> = 0010 FIGURE 11-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> Address<7:0> Data PMA<13:8> PMRD/PMWR PMENB PMALL PMPIF BUSY DS39775C-page 184 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 11-18: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> Address<7:0> Data PMA<13:8> PMRD/PMWR PMENB PMALL PMPIF BUSY FIGURE 11-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> Address<7:0> Address<15:8> Data PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 11-20: WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> Address<7:0> Address<15:8> Data PMWR PMRD PMALL PMALH PMPIF BUSY © 2009 Microchip Technology Inc. DS39775C-page 185

PIC18F87J50 FAMILY FIGURE 11-21: READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> LSB MSB PMA<13:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-22: WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> LSB MSB PMA<13:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> Address<7:0> LSB MSB PMA<13:8> PMWR PMRD PMBE PMALL PMPIF BUSY DS39775C-page 186 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 11-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> Address<7:0> LSB MSB PMA<13:8> PMWR PMRD PMBE PMALL PMPIF BUSY FIGURE 11-25: READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> Address<7:0> Address<15:8> LSB MSB PMWR PMRD PMBE PMALH PMALL PMPIF BUSY FIGURE 11-26: WRITE TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> Address<7:0> Address<15:8> LSB MSB PMWR PMRD PMBE PMALH PMALL PMPIF BUSY © 2009 Microchip Technology Inc. DS39775C-page 187

PIC18F87J50 FAMILY 11.4 Application Examples 11.4.1 MULTIPLEXED MEMORY OR PERIPHERAL This section introduces some potential applications for the PMP module. Figure11-27 demonstrates the hookup of a memory or another addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective. However, for this configuration, there needs to be some external latches to maintain the address. FIGURE 11-27: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION PIC18F A<7:0> PMD<7:0> 373 A<15:0> PMALL D<7:0> D<7:0> CE A<15:8> 373 OE WR PMALH PMCS Address Bus PMRD Data Bus PMWR Control Lines 11.4.2 PARTIALLY MULTIPLEXED ory or peripheral that is partially multiplexed with an MEMORY OR PERIPHERAL external latch. If the peripheral has internal latches, as shown in Figure11-29, then no extra circuitry is Partial multiplexing implies using more pins; however, required except for the peripheral itself. for a few extra pins, some extra performance can be achieved. Figure11-28 shows an example of a mem- FIGURE 11-28: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC18F A<7:0> PMD<7:0> 373 A<14:0> PMALL D<7:0> D<7:0> A<14:8> PMA<14:7> CE PMCS OE WR Address Bus Data Bus PMRD Control Lines PMWR FIGURE 11-29: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC18F Parallel Peripheral PMD<7:0> AD<7:0> PMALL ALE PMCS CS Address Bus PMRD RD Data Bus PMWR WR Control Lines DS39775C-page 188 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 11.4.3 PARALLEL EEPROM EXAMPLE Figure11-30 shows an example connecting parallel EEPROM to the PMP. Figure11-31 shows a slight variation to this, configuring the connection for 16-bit data from a single EEPROM. FIGURE 11-30: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA) PIC18F Parallel EEPROM PMA<n:0> A<n:0> PMD<7:0> D<7:0> PMCS CE Address Bus PMRD OE Data Bus PMWR WR Control Lines FIGURE 11-31: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA) PIC18F Parallel EEPROM PMA<n:0> A<n:1> PMD<7:0> D<7:0> PMBE A0 PMCS CE Address Bus PMRD OE Data Bus PMWR WR Control Lines 11.4.4 LCD CONTROLLER EXAMPLE The PMP module can be configured to connect to a typical LCD controller interface, as shown in Figure11-32. In this case the PMP module is config- ured for active-high control signals since common LCD displays require active-high control. FIGURE 11-32: LCD CONTROL EXAMPLE (BYTE MODE OPERATION) PIC18F LCD Controller PM<7:0> D<7:0> PMA0 RS PMRD/PMWR R/W Address Bus PMCS E Data Bus Control Lines © 2009 Microchip Technology Inc. DS39775C-page 189

PIC18F87J50 FAMILY TABLE 11-3: REGISTERS ASSOCIATED WITH PMP MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PMCONH PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 66 PMCONL CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP 67 PMADDRH(1)/ CS2 CS1 Parallel Master Port Address, High Byte 66 PMDOUT1H(1) Parallel Port Out Data, High Byte (Buffer 1) 66 PMADDRL(1)/ Parallel Master Port Address, Low Byte 66 PMDOUT1L(1) Parallel Port Out Data, Low Byte (Buffer 0) 66 PMDOUT2H Parallel Port Out Data, High Byte (Buffer 3) 66 PMDOUT2L Parallel Port Out Data, Low Byte (Buffer 2) 66 PMDIN1H Parallel Port In Data, High Byte (Buffer 1) 66 PMDIN1L Parallel Port In Data, Low Byte (Buffer 0) 66 PMDIN2H Parallel Port In Data, High Byte (Buffer 3) 67 PMDIN2L Parallel Port In Data, Low Byte (Buffer 2) 67 PMMODEH BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 67 PMMODEL WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 67 PMEH PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 67 PMEL PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 67 PMSTATH IBF IBOV — — IB3F IB2F IB1F IB0F 67 PMSTATL OBE OBUF — — OB3E OB2E OB1E OB0E 67 PADCFG1(2) — — — — — — — PMPTTL 62 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. 2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. DS39775C-page 190 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 12.0 TIMER0 MODULE The T0CON register (Register12-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or A simplified block diagram of the Timer0 module in 8-bit counter in both 8-bit or 16-bit modes mode is shown in Figure12-1. Figure12-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. DS39775C-page 191

PIC18F87J50 FAMILY 12.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter. The timer/counter. mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on 12.2 Timer0 Reads and Writes in every clock by default unless a different prescaler value 16-Bit Mode is selected (see Section12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited TMR0H is not the actual high byte of Timer0 in 16-bit for the following two instruction cycles. The user can mode. It is actually a buffered version of the real high work around this by writing an adjusted value to the byte of Timer0 which is not directly readable nor writ- TMR0 register. able (refer to Figure12-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of The Counter mode is selected by setting the T0CS bit TMR0L. This provides the ability to read all 16 bits of (= 1). In this mode, Timer0 increments either on every Timer0 without having to verify that the read of the high rising or falling edge of pin RA4/T0CKI. The increment- and low byte were valid, due to a rollover between ing edge is determined by the Timer0 Source Edge successive reads of the high and low byte. Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input Similarly, a write to the high byte of Timer0 must also are discussed below. take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a An external clock source can be used to drive Timer0; write occurs to TMR0L. This allows all 16 bits of Timer0 however, it must meet certain requirements to ensure to be updated at once. that the external clock can be synchronized with the FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) T0CS 3 8 T0PS2:T0PS0 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with TMR0 Set 1 Internal TMR0L High Byte TMR0IF T0CKI pin ProPgrreasmcamlearble 0 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS2:T0PS0 Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39775C-page 192 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 12.3 Prescaler 12.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. The prescaler assignment is fully under software Its value is set by the PSA and T0PS2:T0PS0 bits control and can be changed “on-the-fly” during program (T0CON<3:0>) which determine the prescaler execution. assignment and prescale ratio. 12.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0 from 1:2 through 1:256 in power-of-2 increments are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before TMR0, BSF TMR0, etc.) clear the prescaler count. re-enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: TMR0L Timer0 Register Low Byte 62 TMR0H Timer0 Register High Byte 62 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 62 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 64 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. DS39775C-page 193

PIC18F87J50 FAMILY NOTES: DS39775C-page 194 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 13.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is shown in Figure13-1. A block diagram of the module’s The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure13-2. features: The module incorporates its own low-power oscillator • Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1 counter oscillator can also be used as a low-power clock source • Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation. and TMR1L) Timer1 can also be used to provide Real-Time Clock • Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal device clock or Timer1 oscillator internal options addition of external components and code overhead. • Interrupt on overflow Timer1 is controlled through the T1CON Control • Reset on CCP Special Event Trigger register (Register13-1). It also contains the Timer1 • Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER(1) R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 =Timer1 oscillator is enabled 0 =Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. © 2009 Microchip Technology Inc. DS39775C-page 195

PIC18F87J50 FAMILY 13.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled. • Timer When Timer1 is enabled, the RC1/T1OSI and • Synchronous Counter RC0/T1OSO/T13CKI pins become inputs. This means • Asynchronous Counter the values of TRISC<1:0> are ignored and the pins are read as ‘0’. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input On/Off 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 On/Off T1CKPS1:T1CKPS0 T1SYNC TMR1ON Set Clear TMR1 TMR1L HiTgMh RBy1te TMR1IF (ECCPx Special Event Trigger) on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 T1CKPS1:T1CKPS0 On/Off T1SYNC TMR1ON Clear TMR1 TMR1L HiTgMh RB1yte STMetR 1IF (ECCPx Special Event Trigger) on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39775C-page 196 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 13.2 Timer1 16-Bit Read/Write Mode TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(2,3,4) Timer1 can be configured for 16-bit reads and writes (see Figure13-2). When the RD16 control bit, Oscillator Freq. C1 C2 T1CON<7>, is set, the address for TMR1H is mapped Type to a buffer register for the high byte of Timer1. A read LP 32kHz 27pF(1) 27pF(1) from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register. This Note1: Microchip suggests these values as a provides the user with the ability to accurately read all starting point in validating the oscillator 16 bits of Timer1 without having to determine whether circuit. a read of the high byte, followed by a read of the low 2: Higher capacitance increases the stability byte, has become invalid due to a rollover between of the oscillator but also increases the reads. start-up time. A write to the high byte of Timer1 must also take place 3: Since each resonator/crystal has its own through the TMR1H Buffer register. The Timer1 high characteristics, the user should consult byte is updated with the contents of TMR1H when a the resonator/crystal manufacturer for write occurs to TMR1L. This allows a user to write all appropriate values of external 16 bits to both the high and low bytes of Timer1 at once. components. The high byte of Timer1 is not directly readable or 4: Capacitor values are for design guidance writable in this mode. All reads and writes must take only. place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. 13.3.1 USING TIMER1 AS A The prescaler is only cleared on writes to TMR1L. CLOCK SOURCE 13.3 Timer1 Oscillator The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select An on-chip crystal oscillator circuit is incorporated bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device between pins T1OSI (input) and T1OSO (amplifier switches to SEC_RUN mode; both the CPU and output). It is enabled by setting the Timer1 Oscillator peripherals are clocked from the Timer1 oscillator. If the Enable bit, T1OSCEN (T1CON<3>). The oscillator is a IDLEN bit (OSCCON<7>) is cleared and a SLEEP low-power circuit rated for 32kHz crystals. It will instruction is executed, the device enters SEC_IDLE continue to run during all power-managed modes. The mode. Additional details are available in Section3.0 circuit for a typical LP oscillator is shown in Figure13-3. “Power-Managed Modes”. Table13-1 shows the capacitor selection for the Timer1 Whenever the Timer1 oscillator is providing the clock oscillator. source, the Timer1 system clock status flag, T1RUN The user must provide a software time delay to ensure (T1CON<6>), is set. This can be used to determine the proper start-up of the Timer1 oscillator. controller’s current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe FIGURE 13-3: EXTERNAL Clock Monitor. If the Clock Monitor is enabled and the COMPONENTS FOR THE Timer1 oscillator fails while providing the clock, polling TIMER1 LP OSCILLATOR the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. C1 PIC18F87J50 27 pF 13.3.2 TIMER1 OSCILLATOR LAYOUT T1OSI CONSIDERATIONS XTAL The Timer1 oscillator circuit draws very little power 32.768 kHz during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing T1OSO signals in close proximity. C2 The oscillator circuit, shown in Figure13-3, should be 27 pF located as close as possible to the microcontroller. Note: See the Notes with Table13-1 for additional There should be no circuits passing within the oscillator information about capacitor selection. circuit boundaries other than VSS or VDD. © 2009 Microchip Technology Inc. DS39775C-page 197

PIC18F87J50 FAMILY If a high-speed circuit must be located near the oscilla- tor (such as the ECCP1 pin in Output Compare or PWM Note: The Special Event Triggers from the mode, or the primary oscillator using the OSC2 pin), a ECCPx module will not set the TMR1IF grounded guard ring around the oscillator circuit, as interrupt flag bit (PIR1<0>). shown in Figure13-4, may be helpful when used on a single-sided PCB or in addition to a ground plane. 13.6 Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the FIGURE 13-4: OSCILLATOR CIRCUIT one described in Section13.3 “Timer1 Oscillator”) WITH GROUNDED gives users the option to include RTC functionality to GUARD RING their applications. This is accomplished with an inex- pensive watch crystal to provide an accurate time base VDD and several lines of application code to calculate the VSS time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can OSC1 completely eliminate the need for a separate RTC device and battery backup. OSC2 The application code routine, RTCisr, shown in Example13-1, demonstrates a simple method to increment a counter at one-second intervals using an RC0 Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls RC1 the routine which increments the seconds counter by one. Additional counters for minutes and hours are incremented as the previous counter overflows. RC2 Since the register pair is 16 bits wide, counting up to Note: Not drawn to scale. overflow the register directly from a 32.768kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to pre- 13.4 Timer1 Interrupt load it. The simplest method is to set the MSb of The TMR1 register pair (TMR1H:TMR1L) increments TMR1H with a BSF instruction. Note that the TMR1L from 0000h to FFFFh and rolls over to 0000h. The register is never preloaded or altered; doing so may Timer1 interrupt, if enabled, is generated on overflow introduce cumulative error over many cycles. which is latched in interrupt flag bit, TMR1IF For this method to be accurate, Timer1 must operate in (PIR1<0>). This interrupt can be enabled or disabled Asynchronous mode and the Timer1 overflow interrupt by setting or clearing the Timer1 Interrupt Enable bit, must be enabled (PIE1<0> = 1) as shown in the TMR1IE (PIE1<0>). routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. 13.5 Resetting Timer1 Using the ECCP Special Event Trigger 13.7 Considerations in Asynchronous Counter Mode If ECCP1 or ECCP2 is configured to use Timer1 and to generate a Special Event Trigger in Compare mode Following a Timer1 interrupt and an update to the (CCPxM3:CCPxM0=1011), this signal will reset TMR1 registers, the Timer1 module uses a falling edge Timer3. The trigger from ECCP2 will also start an A/D on its clock source to trigger the next register update on conversion if the A/D module is enabled (see the rising edge. If the update is completed after the Section18.2.1 “Special Event Trigger” for more clock input has fallen, the next rising edge will not be information). counted. The module must be configured as either a timer or a If the application can reliably update TMR1 before the synchronous counter to take advantage of this feature. timer input goes low, no additional action is needed. When used this way, the CCPRxH:CCPRxL register Otherwise, an adjusted update can be performed pair effectively becomes a period register for Timer1. following a later Timer1 increment. This can be done by If Timer1 is running in Asynchronous Counter mode, monitoring TMR1L within the interrupt routine until it this Reset operation may not work. increments, and then updating the TMR1H:TMR1L reg- ister pair while the clock is low, or one-half of the period In the event that a write to Timer1 coincides with a of the clock source. Assuming that Timer1 is being Special Event Trigger, the write operation will take used as a Real-Time Clock, the clock source is a precedence. 32.768 kHz crystal oscillator. In this case, one-half period of the clock is 15.25 μs. DS39775C-page 198 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY The Real-Time Clock application code in Example13-1 shows a typical ISR for Timer1, as well as the optional code required if the update cannot be done reliably within the required interval. EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr ; Insert the next 4 lines of code when TMR1 ; can not be reliably updated before clock pulse goes low BTFSC TMR1L,0 ; wait for TMR1L to become clear BRA $-2 ; (may already be clear) BTFSS TMR1L,0 ; wait for TMR1L to become set BRA $-2 ; TMR1 has just incremented ; If TMR1 update can be completed before clock pulse goes low ; Start ISR here BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done CLRF hours ; Reset hours RETURN ; Done © 2009 Microchip Technology Inc. DS39775C-page 199

PIC18F87J50 FAMILY TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 TMR1L(1) Timer1 Register Low Byte 62 TMR1H(1) Timer1 Register High Byte 62 T1CON(1) RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 62 Legend: Shaded cells are not used by the Timer1 module. Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. DS39775C-page 200 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 14.0 TIMER2 MODULE 14.1 Timer2 Operation The Timer2 module incorporates the following features: In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 4-bit counter/prescaler on the • 8-Bit Timer and Period registers (TMR2 and PR2, clock input gives direct input, divide-by-4 and respectively) divide-by-16 prescale options. These are selected by • Readable and writable (both registers) the prescaler control bits, T2CKPS1:T2CKPS0 • Software programmable prescaler (T2CON<1:0>). The value of TMR2 is compared to that (1:1, 1:4 and 1:16) of the Period register, PR2, on each clock cycle. When • Software programmable postscaler the two values match, the comparator generates a (1:1 through 1:16) match signal as the timer output. This signal also resets • Interrupt on TMR2 to PR2 match the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section14.2 • Optional use as the shift clock for the “Timer2 Interrupt”). MSSP modules The TMR2 and PR2 registers are both directly readable The module is controlled through the T2CON register and writable. The TMR2 register is cleared on any (Register14-1) which enables or disables the timer and device Reset, while the PR2 register initializes at FFh. configures the prescaler and postscaler. Timer2 can be Both the prescaler and postscaler counters are cleared shut off by clearing control bit, TMR2ON (T2CON<2>), on the following events: to minimize power consumption. • a write to the TMR2 register A simplified block diagram of the module is shown in Figure14-1. • a write to the T2CON register • any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 © 2009 Microchip Technology Inc. DS39775C-page 201

PIC18F87J50 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 Output Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2 to PR2 match) pro- the ECCP modules, where it is used as a time base for vides the input for the 4-bit output counter/postscaler. operations in PWM mode. This counter generates the TMR2 match interrupt flag Timer2 can be optionally used as the shift clock source which is latched in TMR2IF (PIR1<1>). The interrupt is for the MSSP modules operating in SPI mode. enabled by setting the TMR2 Match Interrupt Enable Additional information is provided in Section19.0 bit, TMR2IE (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>). FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS3:T2OUTPS0 Set TMR2IF Postscaler 2 T2CKPS1:T2CKPS0 TMR2 Output (to PWM or MSSPx) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 TMR2(1) Timer2 Register 62 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 62 PR2(1) Timer2 Period Register 62 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. DS39775C-page 202 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 15.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure15-1. A block diagram of the module’s The Timer3 timer/counter module incorporates these operation in Read/Write mode is shown in Figure15-2. features: The Timer3 module is controlled through the T3CON • Software selectable operation as a 16-bit timer or register (Register15-1). It also selects the clock source counter options for the CCP and ECCP modules; see • Readable and writable 8-bit registers (TMR3H Section17.1.1 “CCP Modules and Timer and TMR3L) Resources” for more information. • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on ECCP Special Event Trigger REGISTER 15-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to ECCPx/CCPx Enable bits 11 = Timer3 and Timer4 are the clock sources for all ECCP/CCP modules 10 = Timer3 and Timer4 are the clock sources for ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 and ECCP2 01 = Timer3 and Timer4 are the clock sources for ECCP2, ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 00 = Timer1 and Timer2 are the clock sources for all ECCP/CCP modules bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. DS39775C-page 203

PIC18F87J50 FAMILY 15.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared Timer3 can operate in one of three modes: (= 0), Timer3 increments on every internal instruction • Timer cycle (FOSC/4). When the bit is set, Timer3 increments • Synchronous Counter on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. • Asynchronous Counter As with Timer1, the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. FIGURE 15-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 On/Off T3CKPS1:T3CKPS0 T3SYNC TMR3ON ECCPx Special Event Trigger Clear TMR3 TMR3 Set ECCPx Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 15-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T13CKI/T1OSO 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 T3CKPS1:T3CKPS0 On/Off T3SYNC TMR3ON ECCPx Special Event Trigger Clear TMR3 TMR3 Set ECCPx Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39775C-page 204 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes The TMR3 register pair (TMR3H:TMR3L) increments (see Figure15-2). When the RD16 control bit from 0000h to FFFFh and overflows to 0000h. The (T3CON<7>) is set, the address for TMR3H is mapped Timer3 interrupt, if enabled, is generated on overflow to a buffer register for the high byte of Timer3. A read and is latched in interrupt flag bit, TMR3IF (PIR2<1>). from TMR3L will load the contents of the high byte of This interrupt can be enabled or disabled by setting or Timer3 into the Timer3 High Byte Buffer register. This clearing the Timer3 Interrupt Enable bit, TMR3IE provides the user with the ability to accurately read all (PIE2<1>). 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low 15.5 Resetting Timer3 Using the ECCP byte, has become invalid due to a rollover between Special Event Trigger reads. If ECCP1 or ECCP2 is configured to use Timer3 and to A write to the high byte of Timer3 must also take place generate a Special Event Trigger in Compare mode through the TMR3H Buffer register. The Timer3 high (CCPxM3:CCPxM0=1011), this signal will reset byte is updated with the contents of TMR3H when a Timer3. The trigger from ECCP2 will also start an A/D write occurs to TMR3L. This allows a user to write all conversion if the A/D module is enabled (see 16 bits to both the high and low bytes of Timer3 at once. Section18.2.1 “Special Event Trigger” for more The high byte of Timer3 is not directly readable or information). writable in this mode. All reads and writes must take The module must be configured as either a timer or place through the Timer3 High Byte Buffer register. synchronous counter to take advantage of this feature. Writes to TMR3H do not clear the Timer3 prescaler. When used this way, the CCPRxH:CCPRxL register The prescaler is only cleared on writes to TMR3L. pair effectively becomes a period register for Timer3. If Timer3 is running in Asynchronous Counter mode, 15.3 Using the Timer1 Oscillator as the the Reset operation may not work. Timer3 Clock Source In the event that a write to Timer3 coincides with a The Timer1 internal oscillator may be used as the clock Special Event Trigger from an ECCP module, the write source for Timer3. The Timer1 oscillator is enabled by will take precedence. setting the T1OSCEN (T1CON<3>) bit. To use it as the Note: The Special Event Triggers from the Timer3 clock source, the TMR3CS bit must also be set. ECCPx module will not set the TMR3IF As previously noted, this also configures Timer3 to interrupt flag bit (PIR1<0>). increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section13.0 “Timer1 Module”. TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 64 PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE 64 IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP 64 TMR3L Timer3 Register Low Byte 65 TMR3H Timer3 Register High Byte 65 T1CON(1) RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 62 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. © 2009 Microchip Technology Inc. DS39775C-page 205

PIC18F87J50 FAMILY NOTES: DS39775C-page 206 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 16.0 TIMER4 MODULE 16.1 Timer4 Operation The Timer4 timer module has the following features: Timer4 can be used as the PWM time base for the PWM mode of the ECCP/CCP modules. The TMR4 • 8-bit timer register (TMR4) register is readable and writable and is cleared on any • 8-bit period register (PR4) device Reset. The input clock (FOSC/4) has a prescale • Readable and writable (both registers) option of 1:1, 1:4 or 1:16, selected by control bits • Software programmable prescaler (1:1, 1:4, 1:16) T4CKPS1:T4CKPS0 (T4CON<1:0>). The match out- • Software programmable postscaler (1:1 to 1:16) put of TMR4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a • Interrupt on TMR4 match of PR4 TMR4 interrupt, latched in flag bit, TMR4IF (PIR3<3>). Timer4 has a control register shown in Register16-1. The prescaler and postscaler counters are cleared Timer4 can be shut off by clearing control bit, TMR4ON when any of the following occurs: (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 are also • a write to the TMR4 register controlled by this register. Figure16-1 is a simplified • a write to the T4CON register block diagram of the Timer4 module. • any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR4 is not cleared when T4CON is written. REGISTER 16-1: T4CON: TIMER4 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T4OUTPS3:T4OUTPS0: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off bit 1-0 T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 © 2009 Microchip Technology Inc. DS39775C-page 207

PIC18F87J50 FAMILY 16.2 Timer4 Interrupt 16.3 Output of TMR4 The Timer4 module has an 8-bit period register, PR4, The output of TMR4 (before the postscaler) is used which is both readable and writable. Timer4 increments only as a PWM time base for the ECCP/CCP modules. from 00h until it matches PR4 and then resets to 00h on It is not used as a baud rate clock for the MSSP the next increment cycle. The PR4 register is initialized modules as is the Timer2 output. to FFh upon Reset. FIGURE 16-1: TIMER4 BLOCK DIAGRAM 4 1:1 to 1:16 T4OUTPS3:T4OUTPS0 Set TMR4IF Postscaler 2 T4CKPS1:T4CKPS0 TMR4 Output (to PWM) TMR4/PR4 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR4 Comparator PR4 Prescaler 8 8 8 Internal Data Bus TABLE 16-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 TMR4 Timer4 Register 65 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 65 PR4(1) Timer4 Period Register 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module. Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. DS39775C-page 208 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 17.0 CAPTURE/COMPARE/PWM Capture and Compare operations described in this (CCP) MODULES chapter apply to all standard and Enhanced CCP modules. The operations of PWM mode, described in Members of the PIC18F87J10 family of devices all have Section17.4 “PWM Mode”, apply to CCP4 and CCP5 a total of five CCP (Capture/Compare/PWM) modules. only. Two of these (CCP4 and CCP5) implement standard Note: Throughout this section and Section18.0 Capture, Compare and Pulse-Width Modulation (PWM) “Enhanced Capture/Compare/PWM (ECCP) modes and are discussed in this section. The other three Module”, references to register and bit names modules (ECCP1, ECCP2, ECCP3) implement that may be associated with a specific CCP standard Capture and Compare modes, as well as module are referred to generically by the use of Enhanced PWM modes. These are discussed in ‘x’ or ‘y’ in place of the specific module number. Section18.0 “Enhanced Capture/Compare/PWM Thus, “CCPxCON” might refer to the control (ECCP) Module”. register for ECCP1, ECCP2, ECCP3, CCP4 or Each CCP/ECCP module contains a 16-bit register CCP5. which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. For the sake of clarity, all CCP module opera- tion in the following sections is described with respect to CCP4, but is equally applicable to CCP5. REGISTER 17-1: CCPxCON: CCPx CONTROL REGISTER (CCP4 MODULE, CCP5 MODULE) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCPx Module Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCPx Module Mode Select bits 0000 =Capture/Compare/PWM disabled (resets CCPx module) 0001 =Reserved 0010 =Compare mode: toggle output on match (CCPxIF bit is set) 0011 =Reserved 0100 =Capture mode: every falling edge 0101 =Capture mode: every rising edge 0110 =Capture mode: every 4th rising edge 0111 =Capture mode: every 16th rising edge 1000 =Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 =Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 =Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 =Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match (CCPxIF bit is set) 11xx =PWM mode © 2009 Microchip Technology Inc. DS39775C-page 209

PIC18F87J50 FAMILY 17.1 CCP Module Configuration The assignment of a particular timer to a module is determined by the timer to CCP enable bits in the Each Capture/Compare/PWM module is associated T3CON register (Register15-1, page203). Depending with a control register (generically, CCPxCON) and a on the configuration selected, up to four timers may be data register (CCPRx). The data register, in turn, is active at once, with modules in the same configuration comprised of two 8-bit registers: CCPRxL (low byte) (Capture/Compare or PWM) sharing timer resources. and CCPRxH (high byte). All registers are both The possible configurations are shown in Figure17-1. readable and writable. 17.1.2 OPEN-DRAIN OUTPUT OPTION 17.1.1 CCP MODULES AND TIMER When operating in Output mode (i.e., in Compare or RESOURCES PWM modes), the drivers for the CCPx pins can be The ECCP/CCP modules utilize Timers 1, 2, 3 or 4, optionally configured as open-drain outputs. This fea- depending on the mode selected. Timer1 and Timer3 ture allows the voltage level on the pin to be pulled to are available to modules in Capture or Compare a higher level through an external pull-up resistor, and modes, while Timer2 and Timer4 are available for allows the output to communicate with external cir- modules in PWM mode. cuits without the need for additional level shifters. For more information, see Section10.1.4 “Open-Drain TABLE 17-1: CCP MODE – TIMER Outputs”. RESOURCE The open-drain output option is controlled by the bits in CCP Mode Timer Resource the ODCON1 register. Setting the appropriate bit con- figures the pin for the corresponding module for Capture Timer1 or Timer3 open-drain operation. The ODCON1 memory shares Compare Timer1 or Timer3 the same address space as TMR1H. The ODCON1 PWM Timer2 or Timer4 register can be accessed by setting the ADSHR bit in the WDTCON register(WDTCON<4>). FIGURE 17-1: ECCP/CCP AND TIMER INTERCONNECT CONFIGURATIONS T3CCP<2:1> = 00 T3CCP<2:1> = 01 T3CCP<2:1> = 10 T3CCP<2:1> = 11 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 ECCP1 ECCP1 ECCP1 ECCP1 ECCP2 ECCP2 ECCP2 ECCP2 ECCP3 ECCP3 ECCP3 ECCP3 CCP4 CCP4 CCP4 CCP4 CCP5 CCP5 CCP5 CCP5 TMR2 TMR4 TMR2 TMR4 TMR2 TMR4 TMR2 TMR4 Timer1 is used for all Capture Timer1 and Timer2 are used Timer1 and Timer2 are used Timer3 is used for all Capture and Compare operations for for Capture and Compare or for Capture and Compare or and Compare operations for all CCP modules. Timer2 is PWM operations for ECCP1 PWM operations for ECCP1 all CCP modules. Timer4 is used for PWM operations for only (depending on selected and ECCP2 only (depending used for PWM operations for all CCP modules. Modules mode). on the mode selected for each all CCP modules. Modules may share either timer All other modules use either module). Both modules may may share either timer resource as a common time Timer3 or Timer4. Modules use a timer as a common time resource as a common time base. base if they are both in base. may share either timer Capture/Compare or PWM Timer3 and Timer4 are not resource as a common time Timer1 and Timer2 are not available. base if they are in modes. available. Capture/Compare or PWM The other modules use either modes. Timer3 or Timer4. Modules may share either timer resource as a common time base if they are in Capture/Compare or PWM modes. DS39775C-page 210 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 17.2 Capture Mode 17.2.3 SOFTWARE INTERRUPT In Capture mode, the CCPRxH:CCPRxL register pair When the Capture mode is changed, a false capture captures the 16-bit value of the TMR1 or TMR3 interrupt may be generated. The user should keep the registers when an event occurs on the corresponding CCPxIE interrupt enable bit clear to avoid false CCPx pin. An event is defined as one of the following: interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. • every falling edge • every rising edge 17.2.4 CCP PRESCALER • every 4th rising edge There are four prescaler settings in Capture mode. • every 16th rising edge They are specified as part of the operating mode The event is selected by the mode select bits, selected by the mode select bits (CCPxM3:CCPxM0). Whenever the CCPx module is turned off or Capture CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture mode is disabled, the prescaler counter is cleared. This is made, the interrupt request flag bit, CCPxIF, is set; it means that any Reset will clear the prescaler counter. must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old Switching from one capture prescaler to another may captured value is overwritten by the new captured value. generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from 17.2.1 CCPx PIN CONFIGURATION a non-zero prescaler. Example17-1 shows the In Capture mode, the appropriate CCPx pin should be recommended method for switching between capture configured as an input by setting the corresponding prescalers. This example also clears the prescaler TRIS direction bit. counter and will not generate the “false” interrupt. Note: If RG4/CCP5 is configured as an output, a EXAMPLE 17-1: CHANGING BETWEEN write to the port can cause a capture CAPTURE PRESCALERS condition. (CCP5 SHOWN) 17.2.2 TIMER1/TIMER3 MODE SELECTION CLRF CCP5CON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load WREG with the The timers that are to be used with the capture feature ; new prescaler mode (Timer1 and/or Timer3) must be running in Timer mode or ; value and CCP ON Synchronized Counter mode. In Asynchronous Counter MOVWF CCP5CON ; Load CCP5CON with mode, the capture operation will not work. The timer to be ; this value used with each CCP module is selected in the T3CON register (see Section17.1.1 “CCP Modules and Timer Resources”). FIGURE 17-2: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP4IF T3CCP2 TMR3 Enable CCP4 pin Prescaler and CCPR4H CCPR4L ÷ 1, 4, 16 Edge Detect TMR1 T3CCP2 Enable 4 TMR1H TMR1L CCP4CON<3:0> Set CCP5IF 4 Q1:Q4 4 CCP5CON<3:0> T3CCP1 TMR3H TMR3L T3CCP2 TMR3 Enable CCP5 pin Prescaler and CCPR5H CCPR5L ÷ 1, 4, 16 Edge Detect TMR1 Enable T3CCP2 T3CCP1 TMR1H TMR1L © 2009 Microchip Technology Inc. DS39775C-page 211

PIC18F87J50 FAMILY 17.3 Compare Mode Note: Clearing the CCP5CON register will force the RG4 compare output latch (depend- In Compare mode, the 16-bit CCPRx register value is ing on device configuration) to the default constantly compared against either the TMR1 or TMR3 low level. This is not the PORTB or register pair value. When a match occurs, the CCPx pin PORTC I/O data latch. can be: • driven high 17.3.2 TIMER1/TIMER3 MODE SELECTION • driven low Timer1 and/or Timer3 must be running in Timer mode • toggled (high-to-low or low-to-high) or Synchronized Counter mode if the CCPx module is • remains unchanged (that is, reflects the state of using the compare feature. In Asynchronous Counter the I/O latch) mode, the compare operation may not work. The action on the pin is based on the value of the mode 17.3.3 SOFTWARE INTERRUPT MODE select bits (CCPxM3:CCPxM0). At the same time, the interrupt flag bit, CCPxIF, is set. When the Generate Software Interrupt mode is chosen (CCPxM3:CCPxM0 = 1010), the corresponding CCPx 17.3.1 CCPx PIN CONFIGURATION pin is not affected. Only a CCP interrupt is generated, if enabled and the CCPxIE bit is set. The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit. FIGURE 17-3: COMPARE MODE OPERATION BLOCK DIAGRAM Set CCP4IF CCPR4H CCPR4L CCP4 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCP4CON<3:0> 0 TMR1H TMR1L 0 1 TMR3H TMR3L 1 T3CCP1 T3CCP2 Set CCP5IF CCP5 pin Comparator Compare Output S Q Match Logic R TRIS 4 Output Enable CCPR5H CCPR5L CCP5CON<3:0> DS39775C-page 212 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 17-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 RCON IPEN — CM RI TO PD POR BOR 62 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 64 PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE 64 IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 64 TMR1L(1) Timer1 Register Low Byte 62 TMR1H(1) Timer1 Register High Byte 62 ODCON1(2) — — — CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD 62 T1CON(1) RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 62 TMR3H Timer3 Register High Byte 65 TMR3L Timer3 Register Low Byte 65 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 65 CCPR4L Capture/Compare/PWM Register 4 Low Byte 65 CCPR4H Capture/Compare/PWM Register 4 High Byte 65 CCPR5L Capture/Compare/PWM Register 5 Low Byte 65 CCPR5H Capture/Compare/PWM Register 5 High Byte 65 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 65 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. © 2009 Microchip Technology Inc. DS39775C-page 213

PIC18F87J50 FAMILY 17.4 PWM Mode 17.4.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCPx pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since (PR4) register. The PWM period can be calculated the CCP4 and CCP5 pins are multiplexed with a using Equation17-1: PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. EQUATION 17-1: Note: Clearing the CCP4CON or CCP5CON PWM Period = [(PR2) + 1] • 4 • TOSC • register will force the RG3 or RG4 output (TMR2 Prescale Value) latch (depending on device configuration) to the default low level. This is not the PWM frequency is defined as 1/[PWM period]. PORTG I/O data latch. When TMR2 (TMR4) is equal to PR2 (PR4), the Figure17-4 shows a simplified block diagram of the following three events occur on the next increment CCP module in PWM mode. cycle: For a step-by-step procedure on how to set up a CCP • TMR2 (TMR4) is cleared module for PWM operation, see Section17.4.3 • The CCPx pin is set (exception: if PWM duty “Setup for PWM Operation”. cycle=0%, the CCPx pin will not be set) • The PWM duty cycle is latched from CCPRxL into FIGURE 17-4: SIMPLIFIED PWM BLOCK CCPRxH DIAGRAM Note: The Timer2 and Timer 4 postscalers (see Duty Cycle Register Section14.0 “Timer2 Module” and 9 0 Section16.0 “Timer4 Module”) are not CCPRxL CCPxCON<5:4> used in the determination of the PWM frequency. The postscaler could be used Latch Duty Cycle to have a servo update rate at a different CCPRxH (1) frequency than the PWM output. Comparator S Q 17.4.2 PWM DUTY CYCLE R CCPx The PWM duty cycle is specified by writing to the Reset TMRx pin CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available. The CCPRxL contains TMRx = PRx Match 2 LSbs latched the eight MSbs and the CCPxCON<5:4> contains the Comparator from Q clocks two LSbs. This 10-bit value is represented by CCPRxL:CCPxCON<5:4>. Equation17-2 is used to PRx calculate the PWM duty cycle in time. TRIS Set CCPx pin Output Enable EQUATION 17-2: Note1: The two LSbs of the Duty Cycle register are held by a 2-bit latch that is part of the module’s hardware. It is physically separate from the CCPRx registers. PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) • TOSC • (TMR2 Prescale Value) A PWM output (Figure17-5) has a time base (period) and a time that the output stays high (duty cycle). CCPRxL and CCPxCON<5:4> can be written to at any The frequency of the PWM is the inverse of the time, but the duty cycle value is not latched into period (1/period). CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. FIGURE 17-5: PWM OUTPUT Period Duty Cycle TMR2 (TMR4) = PR2 (PR4) TMR2 (TMR4) = Duty Cycle TMR2 (TMR4) = PR2 (TMR4) DS39775C-page 214 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY The CCPRxH register and a 2-bit internal latch are 17.4.3 SETUP FOR PWM OPERATION used to double-buffer the PWM duty cycle. This The following steps should be taken when configuring double-buffering is essential for glitchless PWM the CCP module for PWM operation: operation. 1. Set the PWM period by writing to the PR2 (PR4) When the CCPRxH and 2-bit latch match TMR2 register. (TMR4), concatenated with an internal 2-bit Q clock or 2. Set the PWM duty cycle by writing to the 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is CCPRxL register and CCPxCON<5:4> bits. cleared. 3. Make the CCPx pin an output by clearing the The maximum PWM resolution (bits) for a given PWM appropriate TRIS bit. frequency is given by Equation17-3: 4. Set the TMR2 (TMR4) prescale value, then enable Timer2 (Timer4) by writing to T2CON EQUATION 17-3: (T4CON). (FOSC ) log 5. Configure the CCPx module for PWM operation. FPWM PWM Resolution (max) = bits log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 © 2009 Microchip Technology Inc. DS39775C-page 215

PIC18F87J50 FAMILY TABLE 17-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 RCON IPEN — CM RI TO PD POR BOR 62 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 64 TMR2(1) Timer2 Register 62 PR2(1) Timer2 Period Register 62 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 62 TMR4 Timer4 Register 65 PR4(1) Timer4 Period Register 65 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 65 CCPR4L Capture/Compare/PWM Register 4 Low Byte 65 CCPR4H Capture/Compare/PWM Register 4 High Byte 65 CCPR5L Capture/Compare/PWM Register 5 Low Byte 65 CCPR5H Capture/Compare/PWM Register 5 High Byte 65 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 65 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 65 ODCON1(2) — — — CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD 62 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4. Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. DS39775C-page 216 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 18.0 ENHANCED CAPTURE/ The control register for the Enhanced CCP module is COMPARE/PWM (ECCP) shown in Register18-1. It differs from the CCP4CON/ CCP5CON registers in that the two Most Significant MODULE bits are implemented to control PWM functionality. In the PIC18F87J10 family of devices, three of the CCP In addition to the expanded range of modes available modules are implemented as standard CCP modules through the Enhanced CCPxCON register, the ECCP with Enhanced PWM capabilities. These include the modules each have two additional registers associated provision for 2 or 4 output channels, user-selectable with Enhanced PWM operation and auto-shutdown polarity, dead-band control and automatic shutdown features. They are: and restart. The Enhanced features are discussed in • ECCPxDEL (ECCPx PWM Delay) detail in Section18.4 “Enhanced PWM Mode”. Capture, Compare and single-output PWM functions of • ECCPxAS (ECCPx Auto-Shutdown Control) the ECCP module are the same as described for the standard CCP module. REGISTER 18-1: CCPxCON: ECCPx CONTROL REGISTER (ECCP1/ECCP2/ECCP3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PxM1:PxM0: Enhanced PWM Output Configuration bits If CCPxM3:CCPxM2 = 00, 01, 10: xx = PxA assigned as Capture/Compare input/output; PxB, PxC, PxD assigned as port pins If CCPxM3:CCPxM2 = 11: 00 = Single output: PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: ECCPx Module Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCPx module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Capture mode 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF) 1001 = Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF) 1010 = Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state 1011 = Compare mode: trigger special event (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCP2 trigger also starts A/D conversion if A/D module is enabled)(1) 1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3. © 2009 Microchip Technology Inc. DS39775C-page 217

PIC18F87J50 FAMILY 18.1 ECCP Outputs and Configuration An additional option exists for 80-pin devices. When these devices are operating in Microcontroller mode, Each of the Enhanced CCP modules may have up to the multiplexing options described above still apply. In four PWM outputs, depending on the selected operat- Extended Microcontroller mode, clearing CCP2MX ing mode. These outputs, designated PxA through reassigns ECCP2/P2A to RB3. PxD, are multiplexed with various I/O pins. Some Changing the pin assignment of ECCP2 does not auto- ECCP pin assignments are constant, while others matically change any requirements for configuring the change based on device configuration. For those pins port pin. Users must always verify that the appropriate that do change, the controlling bits are: TRIS register is configured correctly for ECCP2 • CCP2MX Configuration bit operation regardless of where it is located. • ECCPMX Configuration bit (80-pin devices only) 18.1.3 USE OF CCP4 AND CCP5 WITH • Program Memory Operating mode, set by the EMB Configuration bits (80-pin devices only) ECCP1 AND ECCP3 The pin assignments for the Enhanced CCP modules Only the ECCP2 module has four dedicated output pins are summarized in Table18-1, Table18-2 and that are available for use. Assuming that the I/O ports Table18-3. To configure the I/O pins as PWM outputs, or other multiplexed functions on those pins are not the proper PWM mode must be selected by setting the needed, they may be used whenever needed without PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>, interfering with any other CCP module. respectively). The appropriate TRIS direction bits for ECCP1 and ECCP3, on the other hand, only have the corresponding port pins must also be set as three dedicated output pins: ECCPx/PxA, PxB and outputs. PxC. Whenever these modules are configured for Quad PWM mode, the pin normally used for CCP4 or 18.1.1 ECCP1/ECCP3 OUTPUTS AND CCP5 becomes the PxD output pins for ECCP3 and PROGRAM MEMORY MODE ECCP1, respectively. The CCP4 and CCP5 modules In 80-pin devices, the use of Extended Microcontroller remain functional but their outputs are overridden. mode has an indirect effect on the use of ECCP1 and ECCP3 in Enhanced PWM modes. By default, PWM 18.1.4 ECCP MODULES AND TIMER outputs, P1B/P1C and P3B/P3C, are multiplexed to RESOURCES PORTE pins along with the high-order byte of the Like the standard CCP modules, the ECCP modules External Memory Bus. When the bus is active in can utilize Timers 1, 2, 3 or 4, depending on the mode Extended Microcontroller mode, it overrides the selected. Timer1 and Timer3 are available for modules Enhanced CCP outputs and makes them unavailable. in Capture or Compare modes, while Timer2 and Because of this, ECCP1 and ECCP3 can only be used Timer4 are available for modules in PWM mode. in compatible (single output) PWM modes when the Additional details on timer resources are provided in device is in Extended Microcontroller mode and default Section17.1.1 “CCP Modules and Timer pin configuration. Resources”. An exception to this configuration is when a 12-bit address width is selected for the external bus 18.1.5 OPEN-DRAIN OUTPUT OPTION (EMB1:EMB0 Configuration bits = 01). In this case, the When operating in compare or standard PWM modes, upper pins of PORTE continue to operate as digital I/O, the drivers for the ECCPx pins can be optionally config- even when the external bus is active. P1B/P1C and ured as open-drain outputs. This feature allows the P3B/P3C remain available for use as Enhanced PWM voltage level on the pin to be pulled to a higher level outputs. through an external pull-up resistor, and allows the out- If an application requires the use of additional PWM put to communicate with external circuits without the outputs during enhanced microcontroller operation, the need for additional level shifters. For more information, P1B/P1C and P3B/P3C outputs can be reassigned to see Section10.1.4 “Open-Drain Outputs”. the upper bits of PORTH. This is done by clearing the The open-drain output option is controlled by the bits in ECCPMX Configuration bit. the ODCON1 register. Setting the appropriate bit con- figures the pin for the corresponding module for 18.1.2 ECCP2 OUTPUTS AND PROGRAM open-drain operation. The ODCON1 memory shares MEMORY MODES the same address space as of TMR1H. The ODCON1 For 80-pin devices, the program memory mode of the register can be accessed by setting the ADSHR bit in device (Section5.1.3 “PIC18F87J50 Family Program the WDTCON register (WDTCON<4>). Memory Modes”) also impacts pin multiplexing for the module. The ECCP2 input/output (ECCP2/P2A) can be multiplexed to one of three pins. The default assignment (CCP2MX Configuration bit is set) for all devices is RC1. Clearing CCP2MX reassigns ECCP2/P2A to RE7. DS39775C-page 218 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 18-1: PIN CONFIGURATIONS FOR ECCP1 CCP1CON ECCP Mode RC2 RE6 RE5 RG4 RH7 RH6 Configuration All Feature1 Devices: Compatible CCP 00xx 11xx ECCP1 RE6 RE5 RG4/CCP5 N/A N/A Dual PWM 10xx 11xx P1A P1B RE5 RG4/CCP5 N/A N/A Quad PWM(1) x1xx 11xx P1A P1B P1C P1D N/A N/A PIC18F8XJ5X Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A RE6/AD14 RE5/AD13 RG4/CCP5 P1B RH6/AN14 Quad PWM(1) x1xx 11xx P1A RE6/AD14 RE5/AD13 P1D P1B P1C PIC18F8XJ5X Devices, ECCPMX = 1, Extended Microcontroller mode, 16-Bit or 20-Bit Address Width: Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 PIC18F8XJ5X Devices, ECCPMX = 1, Microcontroller mode or Extended Microcontroller mode, 12-Bit Address Width: Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A P1B RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Quad PWM(1) x1xx 11xx P1A P1B P1C P1D RH7/AN15 RH6/AN14 Legend: x = Don’t care, N/A = Not Available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. Note 1: With ECCP1 in Quad PWM mode, CCP5’s output is overridden by P1D; otherwise, CCP5 is fully operational. TABLE 18-2: PIN CONFIGURATIONS FOR ECCP2 CCP2CON ECCP Mode RB3 RC1 RE7 RE2 RE1 RE0 Configuration All Devices, CCP2MX = 1, Either Operating mode: Compatible CCP 00xx 11xx RB3/INT3 ECCP2 RE7 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 P2A RE7 P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 P2A RE7 P2B P2C P2D All Devices, CCP2MX = 0, Microcontroller mode: Compatible CCP 00xx 11xx RB3/INT3 RC1/T1OS1 ECCP2 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 RC1/T1OS1 P2A P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 RC1/T1OS1 P2A P2B P2C P2D PIC18F8XJ5X Devices, CCP2MX = 0, Extended Microcontroller mode: Compatible CCP 00xx 11xx ECCP2 RC1/T1OS1 RE7/AD15 RE2/CS RE1/WR RE0/RD Dual PWM 10xx 11xx P2A RC1/T1OS1 RE7/AD15 P2B RE1/WR RE0/RD Quad PWM x1xx 11xx P2A RC1/T1OS1 RE7/AD15 P2B P2C P2D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. © 2009 Microchip Technology Inc. DS39775C-page 219

PIC18F87J50 FAMILY TABLE 18-3: PIN CONFIGURATIONS FOR ECCP3 CCP3CON ECCP Mode RG0 RE4 RE3 RG3 RH5 RH4 Configuration Feature1 Devices: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RG3/CCP4 N/A N/A Dual PWM 10xx 11xx P3A P3B RE3 RG3/CCP4 N/A N/A Quad PWM(1) x1xx 11xx P3A P3B P3C P3D N/A N/A PIC18F8XJ5X Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P3A RE6/AD14 RE5/AD13 RG3/CCP4 P3B RH6/AN14 Quad PWM(1) x1xx 11xx P3A RE6/AD14 RE5/AD13 P3D P3B P3C PIC18F8XJ5X Devices, ECCPMX = 1, Extended Microcontroller mode, 16-Bit or 20-Bit Address Width: Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14 PIC18F8XJ5X Devices, ECCPMX = 1, Microcontroller mode or Extended Microcontroller mode, 12-Bit Address Width: Compatible CCP 00xx 11xx ECCP3 RE4/AD12 RE3/AD11 RG3/CCP4 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A P3B RE3/AD11 RG3/CCP4 RH5/AN13 RH4/AN12 Quad PWM(1) x1xx 11xx P3A P3B P3C P3D RH5/AN13 RH4/AN12 Legend: x = Don’t care, N/A = Not Available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode. Note 1: With ECCP3 in Quad PWM mode, CCP4’s output is overridden by P1D; otherwise, CCP4 is fully operational. 18.2 Capture and Compare Modes Special Event Triggers are not implemented for ECCP3, CCP4 or CCP5. Selecting the Special Event Except for the operation of the Special Event Trigger Trigger mode for these modules has the same effect as discussed below, the Capture and Compare modes of selecting the Compare with Software Interrupt mode the ECCP module are identical in operation to that of (CCPxM3:CCPxM0 = 1010). CCP4. These are discussed in detail in Section17.2 “Capture Mode” and Section17.3 “Compare Note: The Special Event Trigger from ECCP2 Mode”. will not set the Timer1 or Timer3 interrupt flag bits. 18.2.1 SPECIAL EVENT TRIGGER ECCP1 and ECCP2 incorporate an internal hardware 18.3 Standard PWM Mode trigger that is generated in Compare mode on a match When configured in Single Output mode, the ECCP between the CCPRx register pair and the selected module functions identically to the standard CCP timer. This can be used in turn to initiate an action. This module in PWM mode, as described in Section17.4 mode is selected by setting CCPxCON<3:0> to ‘1011’. “PWM Mode”. This is also sometimes referred to as The Special Event Trigger output of either ECCP1 or “Compatible CCP” mode as in Tables18-1 ECCP2 resets the TMR1 or TMR3 register pair, depend- through18-3. ing on which timer resource is currently selected. This Note: When setting up single output PWM allows the CCPRx register pair to effectively be a 16-bit operations, users are free to use either of programmable period register for Timer1 or Timer3. In the processes described in Section17.4.3 addition, the ECCP2 Special Event Trigger will also start “Setup for PWM Operation” or an A/D conversion if the A/D module is enabled. Section18.4.9 “Setup for PWM Opera- tion”. The latter is more generic but will work for either single or multi-output PWM. DS39775C-page 220 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 18.4 Enhanced PWM Mode Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by The Enhanced PWM mode provides additional PWM one full instruction cycle (4 TOSC). output options for a broader range of control applica- As before, the user must manually configure the tions. The module is a backward compatible version of appropriate TRIS bits for output. the standard CCP module and offers up to four outputs, designated PxA through PxD. Users are also able to 18.4.1 PWM PERIOD select the polarity of the signal (either active-high or active-low). The module’s output mode and polarity The PWM period is specified by writing to the PR2 areconfigured by setting the PxM1:PxM0 and register. The PWM period can be calculated using the CCPxM3CCPxM0 bits of the CCPxCON register equation: (CCPxCON<7:6> and CCPxCON<3:0>, respectively). EQUATION 18-1: For the sake of clarity, Enhanced PWM mode operation is described generically throughout this section with PWM Period = [(PR2) + 1] • 4 • TOSC • respect to the ECCP1 and TMR2 modules. Control reg- (TMR2 Prescale Value) ister names are presented in terms of ECCP1. All three Enhanced modules, as well as the two timer resources, PWM frequency is defined as 1/[PWM period]. When can be used interchangeably and function identically. TMR2 is equal to PR2, the following three events occur TMR2 or TMR4 can be selected for PWM operation by on the next increment cycle: selecting the proper bits in T3CON. • TMR2 is cleared Figure18-1 shows a simplified block diagram of PWM • The ECCP1 pin is set (if PWM duty cycle=0%, operation. All control registers are double-buffered and the ECCP1 pin will not be set) are loaded at the beginning of a new PWM cycle (the • The PWM duty cycle is copied from CCPR1L into period boundary when Timer2 resets) in order to CCPR1H prevent glitches on any of the outputs. The exception is the ECCPx PWM Delay register, ECCPxDEL, which is Note: The Timer2 postscaler (see Section14.0 loaded at either the duty cycle boundary or the bound- “Timer2 Module”) is not used in the ary period (whichever comes first). Because of the determination of the PWM frequency. The buffering, the module waits until the assigned timer postscaler could be used to have a servo resets instead of starting immediately. This means that update rate at a different frequency than the PWM output. FIGURE 18-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> P1M1<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L ECCP1/P1A ECCP1/P1A TRISx<x> CCPR1H (Slave) P1B P1B Output TRISx<x> Comparator R Q Controller P1C P1C TMR2 (Note 1) S TRISx<x> Comparator P1D P1D Clear Timer, TRISx<x> set ECCP1 pin and PR2 latch D.C. ECCP1DEL Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. DS39775C-page 221

PIC18F87J50 FAMILY 18.4.2 PWM DUTY CYCLE Note: If the PWM duty cycle value is longer than The PWM duty cycle is specified by writing to the the PWM period, the ECCP1 pin will not CCPR1L register and to the CCP1CON<5:4> bits. Up be cleared. to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the 18.4.3 PWM OUTPUT CONFIGURATIONS two LSbs. This 10-bit value is represented by The P1M1:P1M0 bits in the CCP1CON register allow CCPR1L:CCP1CON<5:4>. The PWM duty cycle is one of four configurations: calculated by the following equation: • Single Output EQUATION 18-2: • Half-Bridge Output PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • • Full-Bridge Output, Forward mode TOSC • (TMR2 Prescale Value) • Full-Bridge Output, Reverse mode The Single Output mode is the standard PWM mode CCPR1L and CCP1CON<5:4> can be written to at any discussed in Section18.4 “Enhanced PWM Mode”. time but the duty cycle value is not copied into The Half-Bridge and Full-Bridge Output modes are CCPR1H until a match between PR2 and TMR2 occurs covered in detail in the sections that follow. (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The general relationship of the outputs in all configurations is summarized in Figure18-2. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM opera- tion. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the ECCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: EQUATION 18-3: log(FOSC) FPWM PWM Resolution (max) = bits log(2) TABLE 18-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 DS39775C-page 222 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 18-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 PR2 + 1 Duty CCP1CON<7:6> SIGNAL Cycle Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive FIGURE 18-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 Duty PR2 + 1 CCP1CON<7:6> SIGNAL Cycle Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive P1B Modulated (Full-Bridge, 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section18.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. DS39775C-page 223

PIC18F87J50 FAMILY 18.4.4 HALF-BRIDGE MODE FIGURE 18-4: HALF-BRIDGE PWM OUTPUT In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output Period Period signal is output on the P1A pin, while the complemen- tary PWM output signal is output on the P1B pin Duty Cycle (Figure18-4). This mode can be used for half-bridge P1A(2) applications, as shown in Figure18-5, or for full-bridge td applications, where four power switches are being td modulated with two PWM signals. P1B(2) In Half-Bridge Output mode, the programmable dead-band delay can be used to prevent shoot-through (1) (1) (1) current in half-bridge power devices. The value of bits P1DC6:P1DC0 sets the number of instruction cycles td = Dead Band Delay before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains Note 1: At this time, the TMR2 register is equal to the inactive during the entire cycle. See Section18.4.6 PR2 register. “Programmable Dead-Band Delay” for more details 2: Output signals are shown as active-high. on dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTE<6> data latches, the TRISC<2> and TRISE<6> bits must be cleared to configure P1A and P1B as outputs. FIGURE 18-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) PIC18F87J50 FET Driver + P1A V - Load FET Driver + P1B V - V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F87J50 FET FET Driver Driver P1A Load FET FET Driver Driver P1B V- DS39775C-page 224 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 18.4.5 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the port pins as described in Table18-1, Table18-2 In Full-Bridge Output mode, four pins are used as and Table18-3. The corresponding TRIS bits must be outputs; however, only two outputs are active at a time. cleared to make the P1A, P1B, P1C and P1D pins In the Forward mode, pin P1A is continuously active outputs. and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure18-6. FIGURE 18-6: FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. DS39775C-page 225

PIC18F87J50 FAMILY FIGURE 18-7: EXAMPLE OF FULL-BRIDGE OUTPUT APPLICATION V+ PIC18F87J50 FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D 18.4.5.1 Direction Change in Full-Bridge 1. The direction of the PWM output changes when Output Mode the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including In the Full-Bridge Output mode, the P1M1 bit in the the power device and driver circuit, is greater CCP1CON register allows users to control the forward/ than the turn-on time. reverse direction. When the application firmware changes this direction control bit, the module will Figure18-9 shows an example where the PWM direc- assume the new direction on the next PWM cycle. tion changes from forward to reverse at a near 100% duty cycle. At time t1, the outputs, P1A and P1D, Just before the end of the current PWM period, the become inactive, while output, P1C, becomes active. In modulated outputs (P1B and P1D) are placed in their this example, since the turn-off time of the power inactive state, while the unmodulated outputs (P1A and devices is longer than the turn-on time, a shoot-through P1C) are switched to drive in the opposite direction. current may flow through power devices, QC and QD This occurs in a time interval of (4 TOSC * (Timer2 (see Figure18-7), for the duration of ‘t’. The same Prescale Value) before the next PWM period begins. phenomenon will occur to power devices, QA and QB, The Timer2 prescaler will be either 1, 4 or 16, depend- for PWM direction change from reverse to forward. ing on the value of the T2CKPS bits (T2CON<1:0>). During the interval from the switch of the unmodulated If changing PWM direction at high duty cycle is required outputs to the beginning of the next period, the for an application, one of the following requirements modulated outputs (P1B and P1D) remain inactive. must be met: This relationship is shown in Figure18-8. 1. Reduce PWM for a PWM period before Note that in the Full-Bridge Output mode, the ECCP1 changing directions. module does not provide any dead-band delay. In gen- 2. Use switch drivers that can drive the switches off eral, since only one output is modulated at all times, faster than they can drive them on. dead-band delay is not required. However, there is a Other options to prevent shoot-through current may situation where a dead-band delay might be required. exist. This situation occurs when both of the following conditions are true: DS39775C-page 226 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 18-8: PWM DIRECTION CHANGE Period(1) Period SIGNAL P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written at any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 18-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A(1) P1B(1) DC P1C(1) P1D(1) DC t (2) ON External Switch C(1) t (3) OFF External Switch D(1) Potential t = t – t (2,3) OFF ON Shoot-Through Current(1) Note 1: All signals are shown as active-high. 2: t is the turn-on delay of power switch QC and its driver. ON 3: t is the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. DS39775C-page 227

PIC18F87J50 FAMILY 18.4.6 PROGRAMMABLE DEAD-BAND A shutdown event can be caused by either of the two DELAY comparator modules or the FLT0 pin (or any combina- tion of these three sources). The comparators may be In half-bridge applications, where all power switches used to monitor a voltage input proportional to a current are modulated at the PWM frequency at all times, the being monitored in the bridge circuit. If the voltage power switches normally require more time to turn off exceeds a threshold, the comparator switches state and than to turn on. If both the upper and lower power triggers a shutdown. Alternatively, a low-level digital sig- switches are switched at the same time (one turned on nal on the FLT0 pin can also trigger a shutdown. The and the other turned off), both switches may be on for auto-shutdown feature can be disabled by not selecting a short period of time until one switch completely turns any auto-shutdown sources. The auto-shutdown off. During this brief interval, a very high current sources to be used are selected using the (shoot-through current) may flow through both power ECCP1AS2:ECCP1AS0 bits (ECCP1AS<6:4>). switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flow- When a shutdown occurs, the output pins are ing during switching, turning on either of the power asynchronously placed in their shutdown states, switches is normally delayed to allow the other switch specified by the PSS1AC1:PSS1AC0 and to completely turn off. PSS1BD1:PSS1BD0 bits (ECCP1AS3:ECCP1AS0). Each pin pair (P1A/P1C and P1B/P1D) may be set to In the Half-Bridge Output mode, a digitally program- drive high, drive low or be tri-stated (not driving). The mable, dead-band delay is available to avoid ECCP1ASE bit (ECCP1AS<7>) is also set to hold the shoot-through current from destroying the bridge Enhanced PWM outputs in their shutdown states. power switches. The delay occurs at the signal transition from the non-active state to the active state The ECCP1ASE bit is set by hardware when a (see Figure18-4 for illustration). The lower seven bits of shutdown event occurs. If automatic restarts are not the ECCP1DEL register (Register18-2) set the delay enabled, the ECCP1ASE bit is cleared by firmware period in terms of microcontroller instruction cycles when the cause of the shutdown clears. If automatic (TCY or 4 TOSC). restarts are enabled, the ECCP1ASE bit is automati- cally cleared when the cause of the auto-shutdown has 18.4.7 ENHANCED PWM cleared. AUTO-SHUTDOWN If the ECCP1ASE bit is set when a PWM period begins, When the ECCP1 is programmed for any of the the PWM outputs remain in their shutdown state for that Enhanced PWM modes, the active output pins may be entire PWM period. When the ECCP1ASE bit is configured for auto-shutdown. Auto-shutdown immedi- cleared, the PWM outputs will return to normal ately places the Enhanced PWM output pins into a operation at the beginning of the next PWM period. defined shutdown state when a shutdown event Note: Writing to the ECCP1ASE bit is disabled occurs. while a shutdown condition is active. REGISTER 18-2: ECCPxDEL: ECCPx PWM DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPxASE must be cleared in software to restart the PWM bit 6-0 PxDC6:PxDC0: PWM Delay Count bits Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. DS39775C-page 228 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 18-3: ECCPxAS: ECCPx AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPxASE: ECCPx Auto-Shutdown Event Status bit 0 = ECCPx outputs are operating 1 = A shutdown event has occurred; ECCPx outputs are in shutdown state bit 6-4 ECCPxAS2:ECCPxAS0: ECCPx Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator 1 output 010 = Comparator 2 output 011 = Either Comparator 1 or 2 100 = FLT0 101 = FLT0 or Comparator 1 110 = FLT0 or Comparator 2 111 = FLT0 or Comparator 1 or Comparator 2 bit 3-2 PSSxAC1:PSSxAC0: Pins A and C Shutdown State Control bits 00 = Drive Pins A and C to ‘0’ 01 = Drive Pins A and C to ‘1’ 1x = Pins A and C tri-state bit 1-0 PSSxBD1:PSSxBD0: Pins B and D Shutdown State Control bits 00 = Drive Pins B and D to ‘0’ 01 = Drive Pins B and D to ‘1’ 1x = Pins B and D tri-state 18.4.7.1 Auto-Shutdown and Automatic Independent of the P1RSEN bit setting, if the Restart auto-shutdown source is one of the comparators, the shutdown condition is a level. The ECCP1ASE bit The auto-shutdown feature can be configured to allow cannot be cleared as long as the cause of the shutdown automatic restarts of the module following a shutdown persists. event. This is enabled by setting the P1RSEN bit of the ECCP1DEL register (ECCP1DEL<7>). The Auto-Shutdown mode can be forced by writing a ‘1’ to the ECCP1ASE bit. In Shutdown mode with P1RSEN = 1 (Figure18-10), the ECCP1ASE bit will remain set for as long as the 18.4.8 START-UP CONSIDERATIONS cause of the shutdown continues. When the shutdown When the ECCP1 module is used in the PWM mode, condition clears, the ECCP1ASE bit is cleared. If the application hardware must use the proper external P1RSEN =0 (Figure18-11), once a shutdown condi- pull-up and/or pull-down resistors on the PWM output tion occurs, the ECCP1ASE bit will remain set until it is pins. When the microcontroller is released from Reset, cleared by firmware. Once ECCP1ASE is cleared, the all of the I/O pins are in the high-impedance state. The Enhanced PWM will resume at the beginning of the external circuits must keep the power switch devices in next PWM period. the OFF state until the microcontroller drives the I/O Note: Writing to the ECCP1ASE bit is disabled pins with the proper signal levels, or activates the PWM while a shutdown condition is active. output(s). © 2009 Microchip Technology Inc. DS39775C-page 229

PIC18F87J50 FAMILY The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow The P1A, P1B, P1C and P1D output latches may not be the user to choose whether the PWM output signals are in the proper states when the PWM module is initialized. active-high or active-low for each pair of PWM output Enabling the PWM pins for output at the same time as pins (P1A/P1C and P1B/P1D). The PWM output the ECCP1 module may cause damage to the applica- polarities must be selected before the PWM pins are tion circuit. The ECCP1 module must be enabled in the configured as outputs. Changing the polarity configura- proper output mode and complete a full PWM cycle tion while the PWM pins are configured as outputs is before configuring the PWM pins as outputs. The not recommended since it may result in damage to the completion of a full PWM cycle is indicated by the application circuits. TMR2IF bit being set as the second PWM period begins. FIGURE 18-10: PWM AUTO-SHUTDOWN (P1RSEN = 1, AUTO-RESTART ENABLED) PWM Period ShutdownEvent ECCP1ASE bit PWM Activity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes FIGURE 18-11: PWM AUTO-SHUTDOWN (P1RSEN = 0, AUTO-RESTART DISABLED) PWM Period ShutdownEvent ECCP1ASE bit PWM Activity Normal PWM ECCP1ASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes DS39775C-page 230 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 18.4.9 SETUP FOR PWM OPERATION 8. If auto-restart operation is required, set the PxRSEN bit (ECCPxDEL<7>). The following steps should be taken when configuring the ECCPx module for PWM operation: 9. Configure and start TMRn (TMR2 or TMR4): • Clear the TMRn interrupt flag bit by clearing 1. Configure the PWM pins PxA and PxB (and PxC the TMRnIF bit (PIR1<1> for Timer2 or and PxD, if used) as inputs by setting the PIR3<3> for Timer4). corresponding TRIS bits. • Set the TMRn prescale value by loading the 2. Set the PWM period by loading the PR2 (PR4) TnCKPS bits (TnCON<1:0>). register. • Enable Timer2 (or Timer4) by setting the 3. Configure the ECCPx module for the desired TMRnON bit (TnCON<2>). PWM mode and configuration by loading the CCPxCON register with the appropriate values: 10. Enable PWM outputs after a new PWM cycle has started: • Select one of the available output configurations and direction with the • Wait until TMRn overflows (TMRnIF bit is set). PxM1:PxM0 bits. • Enable the ECCPx/PxA, PxB, PxC and/or • Select the polarities of the PWM output PxD pin outputs by clearing the respective signals with the CCPxM3:CCPxM0 bits. TRIS bits. 4. Set the PWM duty cycle by loading the CCPRxL • Clear the ECCPxASE bit (ECCPxAS<7>). register and the CCPxCON<5:4> bits. 18.4.10 EFFECTS OF A RESET 5. For auto-shutdown: Both Power-on Reset and subsequent Resets will force • Disable auto-shutdown; ECCPxASE = 0 all ports to Input mode and the ECCP registers to their • Configure auto-shutdown source Reset states. • Wait for Run condition This forces the Enhanced CCP module to reset to a 6. For Half-Bridge Output mode, set the state compatible with the standard CCP module. dead-band delay by loading ECCPxDEL<6:0> with the appropriate value. 7. If auto-shutdown operation is required, load the ECCPxAS register: • Select the auto-shutdown sources using the ECCPxAS2:ECCPxAS0 bits. • Select the shutdown states of the PWM output pins using the PSSxAC1:PSSxAC0 and PSSxBD1:PSSxBD0 bits. • Set the ECCPxASE bit (ECCPxAS<7>). © 2009 Microchip Technology Inc. DS39775C-page 231

PIC18F87J50 FAMILY TABLE 18-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 RCON IPEN — CM RI TO PD POR BOR 62 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 64 PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE 64 IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 64 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 64 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 64 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 64 TRISH(1) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 64 TMR1L(3) Timer1 Register Low Byte 62 TMR1H(3) Timer1 Register High Byte 62 T1CON(3) RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 62 TMR2(3) Timer2 Register 62 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 62 PR2(3) Timer2 Period Register 62 TMR3L Timer3 Register Low Byte 65 TMR3H Timer3 Register High Byte 65 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 65 TMR4 Timer4 Register 65 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 65 PR4(3) Timer4 Period Register 65 CCPRxL(2) Capture/Compare/PWM Register x Low Byte 63 CCPRxH(2) Capture/Compare/PWM Register x High Byte 63, CCPxCON(2) PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 63 ECCPxAS(2) ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 63, 63, 63 ECCPxDEL(2) PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 63, 63, 63 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: Available on 80-pin devices only. 2: Generic term for all of the identical registers of this name for all Enhanced CCP modules, where ‘x’ identifies the individual module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same generic name are identical. 3: Default (legacy) SFR at this address, available when WDTCON<4> = 0. DS39775C-page 232 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.0 MASTER SYNCHRONOUS 19.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four modes of SPI are supported. To accomplish 19.1 Master SSP (MSSP) Module communication, typically three pins are used: Overview • Serial Data Out (SDOx) – RC5/SDO1 or RD4/SDO2 The Master Synchronous Serial Port (MSSP) module is • Serial Data In (SDIx) – RC4/SDI1/SDA1 or a serial interface, useful for communicating with other RD5/SDI2/SDA2 peripheral or microcontroller devices. These peripheral • Serial Clock (SCKx) – RC3/SCK1/SCL1 or devices may be serial EEPROMs, shift registers, RD6/SCK2/SCL2 display drivers, A/D Converters, etc. The MSSP module can operate in one of two modes: Additionally, a fourth pin may be used when in a Slave mode of operation: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) • Slave Select (SSx) – RF7/SS1 or RD7/SS2 - Full Master mode Figure19-1 shows the block diagram of the MSSP - Slave mode (with general address call) module when operating in SPI mode. The I2C interface supports the following modes in FIGURE 19-1: MSSPx BLOCK DIAGRAM hardware: (SPIMODE) • Master mode Internal • Multi-Master mode Data Bus • Slave mode with 5-bit and 7-bit address masking Read Write (with address masking for both 10-bit and 7-bit addressing) SSPxBUF reg All members of the PIC18F87J10 family have two MSSP modules, designated as MSSP1 and MSSP2. Each module operates independently of the other. SDIx Note: Throughout this section, generic refer- SSPxSR reg ences to an MSSP module in any of its SDOx bit 0 Shift Clock operating modes may be interpreted as being equally applicable to MSSP1 or MSSP2. Register names and module I/O signals use the generic designator ‘x’ to indicate the use of a numeral to distinguish SSx SSxControl a particular module when required. Control Enable bit names are not individuated. Edge Select 19.2 Control Registers Each MSSP module has three associated control regis- 2 ters. These include a status register (SSPxSTAT) and Clock Select two control registers (SSPxCON1 and SSPxCON2). The SSPM3:SSPM0 use of these registers and their individual configuration SMP:CKE ( ) bits differ significantly depending on whether the MSSP 4 TMR2 Output module is operated in SPI or I2C mode. SCKx 2 2 Edge Additional details are provided under the individual Select Prescaler TOSC sections. 4, 16, 64 Note: In devices with more than one MSSP Data to TXx/RXx in SSPxSR module, it is very important to pay close TRIS bit attention to SSPxCON register names. SSP1CON1 and SSP1CON2 control Note: Only port I/O names are used in this diagram for different operational aspects of the same the sake of brevity. Refer to the text for a full list of module, while SSP1CON1 and multiplexed functions. SSP2CON1 control the same features for two different modules. © 2009 Microchip Technology Inc. DS39775C-page 233

PIC18F87J50 FAMILY 19.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data Each MSSP module has four registers for SPI mode bytes are written to or read from. operation. These are: In receive operations, SSPxSR and SSPxBUF • MSSPx Control Register 1 (SSPxCON1) together create a double-buffered receiver. When • MSSPx Status Register (SSPxSTAT) SSPxSR receives a complete byte, it is transferred to • Serial Receive/Transmit Buffer Register SSPxBUF and the SSPxIF interrupt is set. (SSPxBUF) During transmission, the SSPxBUF is not • MSSPx Shift Register (SSPxSR) – Not directly double-buffered. A write to SSPxBUF will write to both accessible SSPxBUF and SSPxSR. SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. REGISTER 19-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE(1) D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>). DS39775C-page 234 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 19-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of over- flow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, this pin must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only. © 2009 Microchip Technology Inc. DS39775C-page 235

PIC18F87J50 FAMILY 19.3.2 OPERATION Buffer Full bit, BF (SSPxSTAT<0>), indicates when SSPxBUF has been loaded with the received data When initializing the SPI, several options need to be (transmission is complete). When the SSPxBUF is read, specified. This is done by programming the appropriate the BF bit is cleared. This data may be irrelevant if the control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). SPI is only a transmitter. Generally, the MSSP interrupt These control bits allow the following to be specified: is used to determine when the transmission/reception • Master mode (SCKx is the clock output) has completed. If the interrupt method is not going to be • Slave mode (SCKx is the clock input) used, then software polling can be done to ensure that a • Clock Polarity (Idle state of SCKx) write collision does not occur. Example19-1 shows the loading of the SSPxBUF (SSPxSR) for data • Data Input Sample Phase (middle or end of data transmission. output time) • Clock Edge (output data on rising/falling edge of The SSPxSR is not directly readable or writable and SCKx) can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates • Clock Rate (Master mode only) the various status conditions. • Slave Select mode (Slave mode only) Each MSSP module consists of a transmit/receive shift 19.3.3 OPEN-DRAIN OUTPUT OPTION register (SSPxSR) and a buffer register (SSPxBUF). The drivers for the SDOx output and SCKx clock pins The SSPxSR shifts the data in and out of the device, can be optionally configured as open-drain outputs. MSb first. The SSPxBUF holds the data that was written This feature allows the voltage level on the pin to be to the SSPxSR until the received data is ready. Once the pulled to a higher level through an external pull-up 8 bits of data have been received, that byte is moved to resistor, and allows the output to communicate with the SSPxBUF register. Then, the Buffer Full detect bit, external circuits without the need for additional level BF (SSPxSTAT<0>) and the interrupt flag bit, SSPxIF, shifters. For more information, see Section10.1.4 are set. This double-buffering of the received data “Open-Drain Outputs”. (SSPxBUF) allows the next byte to start reception before The open-drain output option is controlled by the reading the data that was just received. Any write to the SPI2OD and SPI1OD bits (ODCON3<1:0>. Setting an SSPxBUF register during transmission/reception of data SPIxOD bit configures both SDO and SCK pins for the will be ignored and the Write Collision Detect bit, WCOL corresponding open-drain operation. (SSPxCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following The ODCON3 register shares the same address as the write(s) to the SSPxBUF register completed T1CON register. The ODCON3 register is accessed by successfully. setting the ADSHR bit in the WDTCON register (WDTCON<4>). When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The EXAMPLE 19-1: LOADING THE SSP1BUF (SSP1SR) REGISTER LOOP BTFSS SSP1STAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSP1BUF, W ;WREG reg = contents of SSP1BUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSP1BUF ;New data to xmit DS39775C-page 236 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.3.4 ENABLING SPI I/O Any serial port function that is not desired may be overridden by programming the corresponding Data To enable the serial port, MSSP Enable bit, SSPEN Direction (TRIS) register to the opposite value. (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the 19.3.5 TYPICAL CONNECTION SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as Figure19-2 shows a typical connection between two serial port pins. For the pins to behave as the serial port microcontrollers. The master controller (Processor 1) function, some must have their data direction bits (in initiates the data transfer by sending the SCKx signal. the TRIS register) appropriately programmed as Data is shifted out of both shift registers on their pro- follows: grammed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to • SDIx is automatically controlled by the the same Clock Polarity (CKP), then both controllers SPI module would send and receive data at the same time. • SDOx must have the TRISC<5> or TRISD<4> bit Whether the data is meaningful (or dummy data) cleared depends on the application software. This leads to • SCKx (Master mode) must have the TRISC<3> or three scenarios for data transmission: TRISD<6>bit cleared • Master sends data – Slave sends dummy data • SCKx (Slave mode) must have the TRISC<3> or • Master sends data – Slave sends data TRISD<6> bit set • Master sends dummy data – Slave sends data • SSx must have the TRISF<7> or TRISD<7> bit set FIGURE 19-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDOx SDIx Serial Input Buffer Serial Input Buffer (SSPxBUF) (SSPxBUF) SDIx SDOx Shift Register Shift Register (SSPxSR) (SSPxSR) MSb LSb MSb LSb Serial Clock SCKx SCKx PROCESSOR 1 PROCESSOR 2 © 2009 Microchip Technology Inc. DS39775C-page 237

PIC18F87J50 FAMILY 19.3.6 MASTER MODE shown in Figure19-3, Figure19-5 and Figure19-6, where the MSB is transmitted first. In Master mode, the The master can initiate the data transfer at any time SPI clock rate (bit rate) is user programmable to be one because it controls the SCKx. The master determines of the following: when the slave (Processor 1, Figure19-2) is to broadcast data by the software protocol. • FOSC/4 (or TCY) In Master mode, the data is transmitted/received as • FOSC/16 (or 4 • TCY) soon as the SSPxBUF register is written to. If the SPI • FOSC/64 (or 16 • TCY) is only going to receive, the SDOx output could be dis- • Timer2 output/2 abled (programmed as an input). The SSPxSR register This allows a maximum data rate (at 40MHz) of will continue to shift in the signal present on the SDIx 10.00Mbps. pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as Figure19-3 shows the waveforms for Master mode. if a normal received byte (interrupts and status bits When the CKE bit is set, the SDOx data is valid before appropriately set). This could be useful in receiver there is a clock edge on SCKx. The change of the input applications as a “Line Activity Monitor” mode. sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received The clock polarity is selected by appropriately data is shown. programming the CKP bit (SSPxCON1<4>). This then, would give waveforms for SPI communication as FIGURE 19-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDIx (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF DS39775C-page 238 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.3.7 SLAVE MODE transmitted byte and becomes a floating output. Exter- nal pull-up/pull-down resistors may be desirable In Slave mode, the data is transmitted and received as depending on the application. the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Note1: When the SPI is in Slave mode While in Slave mode, the external clock is supplied by with SSx pin control enabled the external clock source on the SCKx pin. This exter- (SSPxCON1<3:0>=0100), the SPI nal clock must meet the minimum high and low times module will reset if the SSx pin is set to VDD. as specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE While in Sleep mode, the slave can transmit/receive set, then the SSx pin control must be data. When a byte is received, the device can be enabled. configured to wake-up from Sleep. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SSx pin to 19.3.8 SLAVE SELECT a high level or clearing the SSPEN bit. SYNCHRONIZATION To emulate two-wire communication, the SDOx pin can The SSx pin allows a Synchronous Slave mode. The be connected to the SDIx pin. When the SPI needs to SPI must be in Slave mode with the SSx pin control operate as a receiver, the SDOx pin can be configured enabled (SSPxCON1<3:0> = 04h). When the SSx pin as an input. This disables transmissions from the is low, transmission and reception are enabled and the SDOx. The SDIx can always be left as an input (SDIx SDOx pin is driven. When the SSx pin goes high, the function) since it cannot create a bus conflict. SDOx pin is no longer driven, even if in the middle of a FIGURE 19-4: SLAVE SYNCHRONIZATION WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 7 bit 0 SDIx bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF © 2009 Microchip Technology Inc. DS39775C-page 239

PIC18F87J50 FAMILY FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF FIGURE 19-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPxSR to SSPxBUF DS39775C-page 240 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.3.9 OPERATION IN POWER-MANAGED 19.3.11 BUS MODE COMPATIBILITY MODES Table19-1 shows the compatibility between the In SPI Master mode, module clocks may be operating standard SPI modes and the states of the CKP and at a different speed than when in full power mode; in CKE control bits. the case of the Sleep mode, all clocks are halted. TABLE 19-1: SPI BUS MODES In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the Control Bits State Standard SPI Mode secondary clock (Timer1 oscillator) or the INTOSC Terminology CKP CKE source. See Section2.4 “Clock Sources and Oscillator Switching” for additional information. 0, 0 0 1 In most cases, the speed that the master clocks SPI 0, 1 0 0 data is not important; however, this should be 1, 0 1 1 evaluated for each system. 1, 1 1 0 If MSSP interrupts are enabled, they can wake the con- There is also an SMP bit which controls when the data troller from Sleep mode, or one of the Idle modes, when is sampled. the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts 19.3.12 SPI CLOCK SPEED AND MODULE should be disabled. INTERACTIONS If the Sleep mode is selected, all module clocks are Because MSSP1 and MSSP2 are independent halted and the transmission/reception will remain in modules, they can operate simultaneously at different that state until the device wakes. After the device data rates. Setting the SSPM3:SSPM0 bits of the returns to Run mode, the module will resume SSPxCON1 register determines the rate for the transmitting and receiving data. corresponding module. In SPI Slave mode, the SPI Transmit/Receive Shift An exception is when both modules use Timer2 as a register operates asynchronously to the device. This time base in Master mode. In this instance, any allows the device to be placed in any power-managed changes to the Timer2 module’s operation will affect mode and data to be shifted into the SPI Trans- both MSSP modules equally. If different bit rates are mit/Receive Shift register. When all 8 bits have been required for each module, the user should select one of received, the MSSP interrupt flag bit will be set and if the other three time base options for one of the enabled, will wake the device. modules. 19.3.10 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. © 2009 Microchip Technology Inc. DS39775C-page 241

PIC18F87J50 FAMILY TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 64 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 64 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 — — 64 SSP1BUF MSSP1 Receive Buffer/Transmit Register 62 SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 62, 65 SSPxSTAT SMP CKE D/A P S R/W UA BF 62, 65 SSP2BUF MSSP2 Receive Buffer/Transmit Register 65 ODCON3(1) — — — — — — SPI2OD SPI1OD 62 Legend: Shaded cells are not used by the MSSP module in SPI mode. Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. DS39775C-page 242 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.4 I2C Mode 19.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call These are: support), and provides interrupts on Start and Stop bits • MSSPx Control Register 1 (SSPxCON1) in hardware to determine a free bus (multi-master • MSSPx Control Register 2 (SSPxCON2) function). The MSSP module implements the standard • MSSPx Status Register (SSPxSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPxBUF) Two pins are used for data transfer: • MSSPx Shift Register (SSPxSR) – Not directly • Serial Clock (SCLx) – RC3/SCK1/SCL1 or accessible RD6/SCK2/SCL2 • MSSPx Address Register (SSPxADD) • Serial Data (SDAx) – RC4/SDI1/SDA1 or • MSSPx 7-Bit Address Mask Register (SSPxMSK) RD5/SDI2/SDA2 SSPxCON1, SSPxCON2 and SSPxSTAT are the The user must configure these pins as inputs by setting control and status registers in I2C mode operation. The the associated TRIS bits. SSPxCON1 and SSPxCON2 registers are readable and writable. The lower 6 bits of the SSPxSTAT are FIGURE 19-7: MSSPx BLOCK DIAGRAM read-only. The upper two bits of the SSPxSTAT are (I2C™ MODE) read/write. SSPxSR is the shift register used for shifting data in or Internal out. SSPxBUF is the buffer register to which data Data Bus bytes are written to or read from. Read Write SSPxADD contains the slave device address when the MSSP is configured in I2C Slave mode. When the SSPxBUF reg SCLx MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator Shift reload value. Clock SSPxSR reg SSPxMSK holds the slave address mask value when SDAx MSb LSb the module is configured for 7-bit Address Masking mode. While it is a separate register, it shares the same SFR address as SSPxADD; it is only accessible when Match Detect Addr Match the SSPM3:SSPM0 bits are specifically set to permit Address Mask access. Additional details are provided in Section19.4.3.4 “7-Bit Address Masking Mode”. SSPxADD reg In receive operations, SSPxSR and SSPxBUF together, create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. Start and Set, Reset Stop bit Detect S, P bits During transmission, the SSPxBUF is not (SSPxSTAT reg) double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. © 2009 Microchip Technology Inc. DS39775C-page 243

PIC18F87J50 FAMILY REGISTER 19-3: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. DS39775C-page 244 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 19-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: SCKx Release Control bit In Slave mode: 1 = Releases clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(2) 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1001 = Load SSPMSK register at SSPADD SFR address(3,4) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs. 2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. 3: When SSPM3:SSPM0 = 1001, any reads or writes to the SSPxADD SFR address actually accesses the SSPMSK register. 4: This mode is only available when 7-bit Address Masking mode is selected (MSSPMSK Configuration bit is ‘1’). © 2009 Microchip Technology Inc. DS39775C-page 245

PIC18F87J50 FAMILY REGISTER 19-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit(2) 1 = Initiates Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit(2) 1 = Initiates Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable bit(2) 1 = Initiates Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). DS39775C-page 246 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 19-6: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit Unused in Slave mode. bit 5-2 ADMSK5:ADMSK2: Slave Address Mask Select bits (5-Bit Address Masking) 1 = Masking of corresponding bits of SSPxADD enabled 0 = Masking of corresponding bits of SSPxADD disabled bit 1 ADMSK1: Slave Address Least Significant bit(s) Mask Select bit In 7-Bit Addressing mode: 1 = Masking of SSPxADD<1> only enabled 0 = Masking of SSPxADD<1> only disabled In 10-Bit Addressing mode: 1 = Masking of SSPxADD<1:0> enabled 0 = Masking of SSPxADD<1:0> disabled bit 0 SEN: Start Condition Enable/Stretch Enable bit(1) 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). REGISTER 19-7: SSPxMSK: I2C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 MSK7:MSK0: Slave Address Mask Select bit 1 = Masking of corresponding bit of SSPxADD enabled 0 = Masking of corresponding bit of SSPxADD disabled Note 1: This register shares the same SFR address as SSPxADD, and is only addressable in select MSSP operating modes. See Section19.4.3.4 “7-Bit Address Masking Mode” for more details. 2: MSK0 is not used as a mask bit in 7-bit addressing. © 2009 Microchip Technology Inc. DS39775C-page 247

PIC18F87J50 FAMILY 19.4.2 OPERATION 19.4.3.1 Addressing The MSSP module functions are enabled by setting the Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPxCON1<5>). a Start condition to occur. Following the Start condition, The SSPxCON1 register allows control of the I2C the 8 bits are shifted into the SSPxSR register. All incoming bits are sampled with the rising edge of the operation. Four mode selection bits (SSPxCON1<3:0>) allow one of the following I2C modes to be selected: clock (SCLx) line. The value of register, SSPxSR<7:1>, is compared to the value of the SSPxADD register. The • I2C Master mode, clock address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCLx) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) with Start and 1. The SSPxSR register value is loaded into the Stop bit interrupts enabled SSPxBUF register. • I2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is 4. The MSSP Interrupt Flag bit, SSPxIF, is set (and Idle interrupt is generated, if enabled) on the falling Selection of any I2C mode with the SSPEN bit set edge of the ninth SCLx pulse. forces the SCLx and SDAx pins to be open-drain, In 10-Bit Addressing mode, two address bytes need to provided these pins are programmed as inputs by be received by the slave. The five Most Significant bits setting the appropriate TRISC or TRISD bits. To ensure (MSbs) of the first address byte specify if this is a 10-bit proper operation of the module, pull-up resistors must address. Bit R/W (SSPxSTAT<2>) must specify a write be provided externally to the SCLx and SDAx pins. so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal 19.4.3 SLAVE MODE ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two In Slave mode, the SCLx and SDAx pins must be MSbs of the address. The sequence of events for 10-bit configured as inputs (TRISC<4:3> set). The MSSP addressing is as follows, with steps 7 through 9 for the module will override the input state with the output data slave-transmitter: when required (slave-transmitter). 1. Receive first (high) byte of address (bits SSPxIF, The I2C Slave mode hardware will always generate an BF and UA are set on address match). interrupt on an address match. Address masking will 2. Update the SSPxADD register with second (low) allow the hardware to generate an interrupt for more byte of address (clears bit UA and releases the than one address (up to 31 in 7-bit addressing and up SCLx line). to 63 in 10-bit addressing). Through the mode select 3. Read the SSPxBUF register (clears bit, BF) and bits, the user can also choose to interrupt on Start and clear flag bit, SSPxIF. Stop bits. 4. Receive second (low) byte of address (bits When an address is matched, or the data transfer after SSPxIF, BF and UA are set). an address match is received, the hardware auto- 5. Update the SSPxADD register with the first matically will generate the Acknowledge (ACK) pulse (high) byte of address. If match releases SCLx and load the SSPxBUF register with the received value line, this will clear bit UA. currently in the SSPxSR register. 6. Read the SSPxBUF register (clears bit BF) and Any combination of the following conditions will cause clear flag bit SSPxIF. the MSSP module not to give this ACK pulse: 7. Receive Repeated Start condition. • The Buffer Full bit, BF (SSPxSTAT<0>), was set 8. Receive first (high) byte of address (bits SSPxIF before the transfer was received. and BF are set). • The overflow bit, SSPOV (SSPxCON1<6>), was 9. Read the SSPxBUF register (clears bit BF) and set before the transfer was received. clear flag bit, SSPxIF. In this case, the SSPxSR register value is not loaded into the SSPxBUF, but bit SSPxIF is set. The BF bit is cleared by reading the SSPxBUF register, while bit SSPOV is cleared through software. The SCLx clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. DS39775C-page 248 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.4.3.2 Address Masking Modes 1 of the incoming address. This allows the module to Acknowledge up to 31 addresses when using 7-bit Masking an address bit causes that bit to become a addressing, or 63 addresses with 10-bit addressing “don't care”. When one address bit is masked, two (see Example19-2). This Masking mode is selected addresses will be Acknowledged and cause an when the MSSPMSK Configuration bit is programmed interrupt. It is possible to mask more than one address (‘0’). bit at a time, which greatly expands the number of addresses Acknowledged. The address mask in this mode is stored is stored in the The I2C Slave behaves the same way whether address SSPxCON2 register, which stops functioning as a control register in I2C Slave mode (Register19-6). In masking is used or not. However, when address masking is used, the I2C slave can Acknowledge 7-Bit Address Masking mode, address mask bits, ADMSK<5:1> (SSPxCON2<5:1>), mask the multiple addresses and cause interrupts. When this corresponding address bits in the SSPxADD register. occurs, it is necessary to determine which address For any ADMSK bits that are set (ADMSK<n>=1), the caused the interrupt by checking SSPxBUF. corresponding address bit is ignored The PIC18F87J10 family of devices is capable of using (SSPxADD<n>=x). For the module to issue an two different Address Masking modes in I2C Slave address Acknowledge, it is sufficient to match only on operation: 5-Bit Address Masking and 7-Bit Address addresses that do not have an active address mask. Masking. The Masking mode is selected at device In 10-Bit Address Masking mode, bits ADMSK<5:2> configuration using the MSSPMSK Configuration bit. mask the corresponding address bits in the SSPxADD The default device configuration is 7-bit Address register. In addition, ADMSK1 simultaneously masks Masking. the two LSbs of the address (SSPxADD<1:0>). For any Both Masking modes, in turn, support address masking ADMSK bits that are active (ADMSK<n>=1), the cor- of 7-bit and 10-bit addresses. The combination of responding address bit is ignored (SPxADD<n>=x). Masking modes and addresses provide different Also note that although in 10-Bit Address Masking ranges of Acknowledgable addresses for each mode, the upper address bits reuse part of the combination. SSPxADD register bits. The address mask bits do not While both Masking modes function in roughly the interact with those bits; they only affect the lower same manner, the way they use address masks are address bits. different. Note1: ADMSK1 masks the two Least Significant bits of the address. 19.4.3.3 5-Bit Address Masking Mode 2: The two Most Significant bits of the As the name implies, 5-Bit Address Masking mode address are not affected by address uses an address mask of up to 5 bits to create a range masking. of addresses to be Acknowledged, using bits 5 through EXAMPLE 19-2: ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE 7-Bit Addressing: SSPADD<7:1>= A0h (1010000) (SSPADD<0> is assumed to be 0) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh 10-Bit Addressing: SSPADD<7:0> = A0h (10100000) (The two MSb of the address are ignored in this example, since they are not affected by masking) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh © 2009 Microchip Technology Inc. DS39775C-page 249

PIC18F87J50 FAMILY 19.4.3.4 7-Bit Address Masking Mode Setting or clearing mask bits in SSPxMSK behaves in the opposite manner of the ADMSK bits in 5-Bit Unlike 5-Bit Address Masking mode, 7-Bit Address Address Masking mode. That is, clearing a bit in Masking mode uses a mask of up to 8 bits (in 10-bit SSPxMSK causes the corresponding address bit to be addressing) to define a range of addresses than can be masked; setting the bit requires a match in that Acknowledged, using the lowest bits of the incoming position. SSPxMSK resets to all ‘1’s upon any Reset address. This allows the module to Acknowledge up to condition and, therefore, has no effect on the standard 127 different addresses with 7-bit addressing, or 255 MSSP operation until written with a mask value. with 10-bit addressing (see Example19-3). This mode is the default configuration of the module, and is With 7-Bit Address Masking mode, SSPxMSK<7:1> selected when MSSPMSK is unprogrammed (‘1’). bits mask the corresponding address bits in the SSPxADD register. For any SSPxMSK bits that are The address mask for 7-Bit Address Masking mode is active (SSPxMSK<n>=0), the corresponding stored in the SSPxMSK register, instead of the SSPxADD address bit is ignored (SSPxADD<n>=x). SSPxCON2 register. SSPxMSK is a separate hard- For the module to issue an address Acknowledge, it is ware register within the module, but it is not directly sufficient to match only on addresses that do not have addressable. Instead, it shares an address in the SFR an active address mask. space with the SSPxADD register. To access the SSPxMSK register, it is necessary to select MSSP With 10-Bit Address Masking mode, SSPxMSK<7:0> mode, ‘1001’ (SSPCON1<3:0> = 1001), and then read bits mask the corresponding address bits in the or write to the location of SSPxADD. SSPxADD register. For any SSPxMSK bits that are active (=0), the corresponding SSPxADD address bit To use 7-Bit Address Masking mode, it is necessary to is ignored (SSPxADD<n>=x). initialize SSPxMSK with a value before selecting the I2C Slave Addressing mode. Thus, the required Note: The two Most Significant bits of the sequence of events is: address are not affected by address 1. Select SSPxMSK Access mode masking. (SSPxCON2<3:0> = 1001). 2. Write the mask value to the appropriate SSPADD register address (FC8h for MSSP1, F6Eh for MSSP2). 3. Set the appropriate I2C Slave mode (SSPxCON2<3:0> = 0111 for 10-bit addressing, 0110 for 7-bit addressing). EXAMPLE 19-3: ADDRESS MASKING EXAMPLES IN 7-BIT MASKING MODE 7-Bit Addressing: SSPxADD<7:1> = 1010 000 SSPxMSK<7:1> = 1111 001 Addresses Acknowledged = A8h, A6h, A4h, A0h 10-Bit Addressing: SSPxADD<7:0> = 1010 0000 (The two MSb are ignored in this example since they are not affected) SSPxMSK<5:1> = 1111 0 Addresses Acknowledged = A8h, A6h, A4h, A0h DS39775C-page 250 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.4.3.5 Reception 19.4.3.6 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPxSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPxSTAT register is set. The received address is the SSPxBUF register and the SDAx line is held low loaded into the SSPxBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin SCLx is held low regard- less of SEN (see Section19.4.4 “Clock Stretching” When the address byte overflow condition exists, then for more details). By stretching the clock, the master the no Acknowledge (ACK) pulse is given. An overflow will be unable to assert another clock pulse until the condition is defined as either bit, BF (SSPxSTAT<0>), slave is done preparing the transmit data. The transmit is set or bit, SSPOV (SSPxCON1<6>), is set. data must be loaded into the SSPxBUF register which An MSSP interrupt is generated for each data transfer also loads the SSPxSR register. Then, pin SCLx should byte. The interrupt flag bit, SSPxIF, must be cleared in be enabled by setting bit, CKP (SSPxCON1<4>). The software. The SSPxSTAT register is used to determine eight data bits are shifted out on the falling edge of the the status of the byte. SCLx input. This ensures that the SDAx signal is valid If SEN is enabled (SSPxCON2<0> = 1), SCLx will be during the SCLx high time (Figure19-10). held low (clock stretch) following each data transfer. The ACK pulse from the master-receiver is latched on The clock must be released by setting bit, CKP the rising edge of the ninth SCLx input pulse. If the (SSPxCON1<4>). See Section19.4.4 “Clock SDAx line is high (not ACK), then the data transfer is Stretching” for more details. complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets the SSPxSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, pin SCLx must be enabled by setting bit, CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. © 2009 Microchip Technology Inc. DS39775C-page 251

PIC18F87J50 FAMILY 2 FIGURE 19-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e eceiving D4 4 n softwarF is read R D6D5 23 Cleared iSSPxBU 7 D 1 = 0 ACK 9 W 8 R/ A1 7 2 )0 A 6 = ddress A3 5 n SEN A e Receiving A5A4 34 set to ‘’ wh0 e SDAxA7A6 SCLx12S SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP (SSPxCON1<4>) (CKP does not r DS39775C-page 252 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 2 FIGURE 19-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 pt. u D1 7 nterr n i D2 6 e a s u Data D3 5 e d ca Receiving D5D4 34 ared in softwarPxBUF is read owledged an D6 2 CleSS Ackn e D7 1 ’).0 X will b K 9 a ‘ X. R/W = 0 AC 8 a ‘’ or 1 5.X.A3. be 6.A X 7 her 7.A Receiving Address SDAxA7A6A5XA3X SCLx123456S SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP (SSPxCON1<4>) (CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can eitx 2:In this example, an address equal to A © 2009 Microchip Technology Inc. DS39775C-page 253

PIC18F87J50 FAMILY 2 FIGURE 19-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S K F I AC 9 PxI S D0 8 m S o Data D1 7 Fr Transmitting D5D4D3D2 3456 eared in software UF is written in software et in software D6 2 Cl SSPxB KP is s C D7 1 R S ACK 9 PxIF I S S D0 8 m o Fr D1 7 Transmitting Data D6D5D4D3D2 23456 F Cleared in software SSPxBUF is written in software CKP is set in software D7 1 PxI SCLx held lowwhile CPUresponds to SS K C A 9 0 = W 8 R/ 1 A 7 ess A2 6 Addr A3 5 g n eivi A4 4 ec R A5 3 >) 7 A6A7 12 Data in sampled 3> or PIR3< <0>) N1<4>) R1< TAT CO DAx CLx S SPxIF (PI F (SSPxS KP (SSPx S S S B C DS39775C-page 254 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 19-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 untilDD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPxADD is updated with highbyte of address nd cause an interrupt. Clock is held low Clock is held low untilupdate of SSPxAupdate of SSPxADD has taken placetaken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACKACKDAx11110A9A8A7A6A5XA3A2XXD7 CLx1234567891234567891S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPxADD needs to bewhen SSPxADD is updatedupdatedwith low byte of address UA is set indicating thatSSPxADD needs to beupdatedKP (SSPxCON1<4>) (CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can either be a ‘’ or a ‘’).x10 2:In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged a 3:Note that the Most Significant bits of the address are not affected by the bit masking. S S S B S U C © 2009 Microchip Technology Inc. DS39775C-page 255

PIC18F87J50 FAMILY FIGURE 19-12: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 untilDD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPxADD is updated with highbyte of address d low SPxA D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACKDAx11110A9A8A7A6A5A4A3A2A1 CLx1234567891234567S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPxADD needs to bewhen SSPxADD is updatedupdatedwith low byte of address UA is set indicating thatSSPxADD needs to beupdatedKP (SSPxCON1<4>) (CKP does not reset to ‘’ when SEN = )00 S S S B S U C DS39775C-page 256 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 2 FIGURE 19-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCLx low w Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressTransmitting Data ByteR/W = 1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPxBUFWrite of SSPxBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPxADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPxADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with lowbyte of address UA is set indicating thatSSPxADD needs to beupdated R/ 8 h be Receive First Byte of Address DAx11110A9A8 CLx1234567S SPxIF (PIR1<3> or PIR3<7>) F (SSPxSTAT<0>) SSPxBUF is written witcontents of SSPxSR A (SSPxSTAT<1>) UA is set indicating thatthe SSPxADD needs to updated KP (SSPxCON1<4>) S S S B U C © 2009 Microchip Technology Inc. DS39775C-page 257

PIC18F87J50 FAMILY 19.4.4 CLOCK STRETCHING 19.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The 7-Bit Slave Transmit mode implements clock The SEN bit (SSPxCON2<0>) allows clock stretching stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data regardless of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCLx line 19.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPxBUF before the master device In 7-Bit Slave Receive mode, on the falling edge of the can initiate another transmit sequence (see ninth clock at the end of the ACK sequence, if the BF Figure19-10). bit is set, the CKP bit in the SSPxCON1 register is Note1: If the user loads the contents of automatically cleared, forcing the SCLx output to be SSPxBUF, setting the BF bit before the held low. The CKP bit being cleared to ‘0’ will assert falling edge of the ninth clock, the CKP bit the SCLx line low. The CKP bit must be set in the will not be cleared and clock stretching user’s ISR before reception is allowed to continue. By will not occur. holding the SCLx line low, the user has time to service 2: The CKP bit can be set in software the ISR and read the contents of the SSPxBUF before regardless of the state of the BF bit. the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure19-15). 19.4.4.4 Clock Stretching for 10-Bit Slave Transmit Mode Note1: If the user reads the contents of the SSPxBUF before the falling edge of the In 10-Bit Slave Transmit mode, clock stretching is ninth clock, thus clearing the BF bit, the controlled during the first two address sequences by CKP bit will not be cleared and clock the state of the UA bit, just as it is in 10-Bit Slave stretching will not occur. Receive mode. The first two addresses are followed by a third address sequence, which contains the 2: The CKP bit can be set in software high-order bits of the 10-bit address and the R/W bit regardless of the state of the BF bit. The set to ‘1’. After the third address sequence is user should be careful to clear the BF bit performed, the UA bit is not set, the module is now in the ISR before the next receive configured in Transmit mode and clock stretching is sequence in order to prevent an overflow controlled by the BF flag as in 7-Bit Slave Transmit condition. mode (see Figure19-13). 19.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPxADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPxADD register before the falling edge of the ninth clock occurs, and if the user hasn’t cleared the BF bit by reading the SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39775C-page 258 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.4.4.5 Clock Synchronization and already asserted the SCLx line. The SCLx output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx. This When the CKP bit is cleared, the SCLx output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, clearing the CKP bit will not assert the minimum high time requirement for SCLx (see SCLx output low until the SCLx output is already Figure19-14). sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 19-14: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX DX – 1 SCLx Master device CKP asserts clock Master device deasserts clock WR SSPxCON1 © 2009 Microchip Technology Inc. DS39775C-page 259

PIC18F87J50 FAMILY 2 FIGURE 19-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R D5 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPxBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 >) A6 2 R3<7 >) A7 1 > or PI 0>) ON1<6 1<4>) DAx CLxS SPxIF (PIR1<3 F (SSPxSTAT< SPOV (SSPxC KP (SSPxCON S S S B S C DS39775C-page 260 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 19-16: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) Clock is not held lowbecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D 8 1 D 7 e Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared in softwareCleared in softwar Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPxADD register beforethe falling edge of the ninth clock will have noeffect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 DAx11110A9A8A7A6A5A4A3A2A1A0ACK CLx12345678912345678S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardware whenthe SSPxADD needs to beSSPxADD is updated with lowupdatedbyte of address after falling edgeof ninth clock UA is set indicating thatSSPxADD needs to beupdated KP (SSPxCON1<4>)Note:An update of the SSPxADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. S S S B S U C © 2009 Microchip Technology Inc. DS39775C-page 261

PIC18F87J50 FAMILY 19.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPxSR is SUPPORT transferred to the SSPxBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK The addressing procedure for the I2C bus is such that bit), the SSPxIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the the master. The exception is the general call address interrupt can be checked by reading the contents of the which can address all devices. When this address is SSPxBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device-specific or a general call address. Acknowledge. In 10-bit mode, the SSPxADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit is set (SSPxSTAT<1>). If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second The general call address is recognized when the half of the address is not necessary, the UA bit will not General Call Enable bit, GCEN, is enabled be set and the slave will begin receiving data after the (SSPxCON2<7> set). Following a Start bit detect, 8 bits Acknowledge (Figure19-17). are shifted into the SSPxSR and the address is compared against the SSPxADD. It is also compared to the general call address and fixed in hardware. FIGURE 19-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK General Call Address SDAx ACK D7 D6 D5 D4 D3 D2 D1 D0 SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPxIF BF (SSPxSTAT<0>) Cleared in software SSPxBUF is read SSPOV (SSPxCON1<6>) ‘0’ GCEN (SSPxCON2<7>) ‘1’ DS39775C-page 262 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPxCON1 and by setting of events. For instance, the user is not the SSPEN bit. In Master mode, the SCLx and SDAx allowed to initiate a Start condition and lines are manipulated by the MSSP hardware if the immediately write the SSPxBUF register to TRIS bits are set. initiate transmission before the Start condition is complete. In this case, the Master mode of operation is supported by interrupt SSPxBUF will not be written to and the generation on the detection of the Start and Stop con- WCOL bit will be set, indicating that a write ditions. The Stop (P) and Start (S) bits are cleared from to the SSPxBUF did not occur. a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the The following events will cause the MSSP Interrupt bus is Idle, with both the S and P bits clear. Flag bit, SSPxIF, to be set (and MSSP interrupt, if In Firmware Controlled Master mode, user code enabled): conducts all I2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options. • Acknowledge transmitted 1. Assert a Start condition on SDAx and SCLx. • Repeated Start 2. Assert a Repeated Start condition on SDAx and SCLx. 3. Write to the SSPxBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDAx and SCLx. 2 FIGURE 19-18: MSSPx BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM3:SSPM0 Data Bus SSPxADD<6:0> Read Write SSPxBUF Baud Rate Generator SDAx Shift SDAx In Clock ct e SSPxSR Detce) MSb LSb L ur e Oo abl WCk s SCLx Receive En StAarcGtk bneiont,we Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCLx In Write Collision Detect Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1) Clock Arbitration Set SSPxIF, BCLxIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPxCON2) End of XMIT/RCV © 2009 Microchip Technology Inc. DS39775C-page 263

PIC18F87J50 FAMILY 19.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPxCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPxIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPxBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDAx while SCLx outputs the serial clock. The 4. Address is shifted out the SDAx pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPxCON2 register (SSPxCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the end of a serial transfer. SSPxIF bit. In Master Receive mode, the first byte transmitted 7. The user loads the SSPxBUF with eight bits of contains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDAx pin until all 8 bits logic ‘1’. Thus, the first byte transmitted is a 7-bit slave are transmitted. address, followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDAx, while SCLx outputs slave device and writes its value into the the serial clock. Serial data is received 8 bits at a time. SSPxCON2 register (SSPxCON2<6>). After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the 10. The MSSP module generates an interrupt at the beginning and end of transmission. end of the ninth clock cycle by setting the SSPxIF bit. The Baud Rate Generator, used for the SPI mode 11. The user generates a Stop condition by setting operation, is used to set the SCLx clock frequency for either 100kHz, 400kHz or 1MHz I2C operation. See the Stop Enable bit, PEN (SSPxCON2<2>). Section19.4.7 “Baud Rate” for more details. 12. Interrupt is generated once the Stop condition is complete. DS39775C-page 264 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.4.7 BAUD RATE 19.4.7.1 Baud Rate and Module In I2C Master mode, the Baud Rate Generator (BRG) Interdependence reload value is placed in the lower 7 bits of the Because MSSP1 and MSSP2 are independent, they SSPxADD register (Figure19-19). When a write can operate simultaneously in I2C Master mode at occurs to SSPxBUF, the Baud Rate Generator will different baud rates. This is done by using different automatically begin counting. The BRG counts down to BRG reload values for each module. 0 and stops until another reload has taken place. The Because this mode derives its basic clock source from BRG count is decremented twice per instruction cycle the system clock, any changes to the clock will affect (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the both modules in the same proportion. It may be BRG is reloaded automatically. possible to change one or both baud rates back to a Once the given operation is complete (i.e., transmis- previous value by changing the BRG reload value. sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCLx pin will remain in its last state. Table19-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. FIGURE 19-19: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPxADD<6:0> SSPM3:SSPM0 Reload Reload SCLx Control CLKO BRG Down Counter FOSC/4 TABLE 19-3: I2C™ CLOCK RATE w/BRG FSCL FOSC FCY FCY * 2 BRG Value (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 18h 400 kHz(1) 40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 20 MHz 63h 100 kHz 16 MHz 4 MHz 8 MHz 09h 400 kHz(1) 16 MHz 4 MHz 8 MHz 0Ch 308 kHz 16 MHz 4 MHz 8 MHz 27h 100 kHz 4 MHz 1 MHz 2 MHz 02h 333 kHz(1) 4 MHz 1 MHz 2 MHz 09h 100 kHz 4 MHz 1 MHz 2 MHz 00h 1 MHz(1) Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. © 2009 Microchip Technology Inc. DS39775C-page 265

PIC18F87J50 FAMILY 19.4.7.2 Clock Arbitration SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCLx high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCLx pin (SCLx allowed to float high). event that the clock is held low by an external device When the SCLx pin is allowed to float high, the Baud (Figure19-20). Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 19-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX DX – 1 SCLx deasserted but slave holds SCLx allowed to transition high SCLx low (clock arbitration) SCLx BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCLx is sampled high, reload takes place and BRG starts its count BRG Reload DS39775C-page 266 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.4.8 I2C MASTER MODE START Note: If, at the beginning of the Start condition, CONDITION TIMING the SDAx and SCLx pins are already sam- To initiate a Start condition, the user sets the Start pled low or if during the Start condition, the Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx line is sampled low before the SDAx SCLx pins are sampled high, the Baud Rate Generator line is driven low, a bus collision occurs, is reloaded with the contents of SSPxADD<6:0> and the Bus Collision Interrupt Flag, BCLxIF, is starts its count. If SCLx and SDAx are both sampled set, the Start condition is aborted and the high when the Baud Rate Generator times out (TBRG), I2C module is reset into its Idle state. the SDAx pin is driven low. The action of the SDAx 19.4.8.1 WCOL Status Flag being driven low while SCLx is high is the Start condi- tion and causes the S bit (SSPxSTAT<3>) to be set. If the user writes the SSPxBUF when a Start sequence Following this, the Baud Rate Generator is reloaded is in progress, the WCOL bit is set and the contents of with the contents of SSPxADD<6:0> and resumes its the buffer are unchanged (the write doesn’t occur). count. When the Baud Rate Generator times out Note: Because queueing of events is not (TBRG), the SEN bit (SSPxCON2<0>) will be allowed, writing to the lower 5 bits of automatically cleared by hardware. The Baud Rate SSPxCON2 is disabled until the Start Generator is suspended, leaving the SDAx line held low condition is complete. and the Start condition is complete. FIGURE 19-21: FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here SDAx = 1, At completion of Start bit, SCLx = 1 hardware clears SEN bit and sets SSPxIF bit TBRG TBRG Write to SSPxBUF occurs here 1st bit 2nd bit SDAx TBRG SCLx TBRG S © 2009 Microchip Technology Inc. DS39775C-page 267

PIC18F87J50 FAMILY 19.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPxCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDAx is sampled low when SCLx the SCLx pin is asserted low. When the SCLx pin is goes from low-to-high. sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<5:0> and begins counting. • SCLx goes low before SDAx is The SDAx pin is released (brought high) for one Baud asserted low. This may indicate that Rate Generator count (TBRG). When the Baud Rate another master is attempting to Generator times out, and if SDAx is sampled high, the transmit a data ‘1’. SCLx pin will be deasserted (brought high). When Immediately following the SSPxIF bit getting set, the SCLx is sampled high, the Baud Rate Generator is user may write the SSPxBUF with the 7-bit address in reloaded with the contents of SSPxADD<6:0> and 7-bit mode, or the default first address in 10-bit mode. begins counting. SDAx and SCLx must be sampled After the first eight bits are transmitted and an ACK is high for one TBRG. This action is then followed by received, the user may then transmit an additional eight assertion of the SDAx pin (SDAx = 0) for one TBRG bits of address (10-bit mode) or eight bits of data (7-bit while SCLx is high. Following this, the RSEN bit mode). (SSPxCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the 19.4.9.1 WCOL Status Flag SDAx pin held low. As soon as a Start condition is If the user writes the SSPxBUF when a Repeated Start detected on the SDAx and SCLx pins, the S bit sequence is in progress, the WCOL is set and the (SSPxSTAT<3>) will be set. The SSPxIF bit will not be contents of the buffer are unchanged (the write doesn’t set until the Baud Rate Generator has timed out. occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPxCON2 is disabled until the Repeated Start condition is complete. FIGURE 19-22: REPEATED START CONDITION WAVEFORM S bit set by hardware SDAx = 1, At completion of Start bit, Write to SSPxCON2 occurs here:SDAx = 1, SCLx = 1 hardware clears RSEN bit SCLx (no change). and sets SSPxIF TBRG TBRG TBRG SDAx 1st bit RSEN bit set by hardware on falling edge of ninth clock, Write to SSPxBUF occurs here end of XMIT TBRG SCLx TBRG Sr = Repeated Start DS39775C-page 268 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.4.10 I2C MASTER MODE TRANSMISSION The user should verify that the WCOL bit is clear after each write to SSPxBUF to ensure the transfer is correct. Transmission of a data byte, a 7-bit address or the In all cases, WCOL must be cleared in software. other half of a 10-bit address, is accomplished by sim- ply writing a value to the SSPxBUF register. This action 19.4.10.3 ACKSTAT Status Flag will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next In Transmit mode, the ACKSTAT bit (SSPxCON2<6>) is cleared when the slave has sent an Acknowledge transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is (ACK=0) and is set when the slave does not Acknowl- asserted (see data hold time specification edge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), parameter106). SCLx is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid or when the slave has properly received its data. before SCLx is released high (see data setup time 19.4.11 I2C MASTER MODE RECEPTION specification parameter 107). When the SCLx pin is released high, it is held that way for TBRG. The data on Master mode reception is enabled by programming the the SDAx pin must remain stable for that duration and Receive Enable bit, RCEN (SSPxCON2<3>). some hold time after the next falling edge of SCLx. Note: The MSSP module must be in an inactive After the eighth bit is shifted out (the falling edge of the state before the RCEN bit is set or the eighth clock), the BF flag is cleared and the master RCEN bit will be disregarded. releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth The Baud Rate Generator begins counting and on each bit time if an address match occurred, or if data was rollover, the state of the SCLx pin changes received properly. The status of ACK is written into the (high-to-low/low-to-high) and data is shifted into the ACKDT bit on the falling edge of the ninth clock. If the SSPxSR. After the falling edge of the eighth clock, the master receives an Acknowledge, the Acknowledge receive enable flag is automatically cleared, the con- Status bit, ACKSTAT, is cleared; if not, the bit is set. tents of the SSPxSR are loaded into the SSPxBUF, the After the ninth clock, the SSPxIF bit is set and the BF flag bit is set, the SSPxIF flag bit is set and the Baud master clock (Baud Rate Generator) is suspended until Rate Generator is suspended from counting, holding the next data byte is loaded into the SSPxBUF, leaving SCLx low. The MSSP is now in Idle state awaiting the SCLx low and SDAx unchanged (Figure19-23). next command. When the buffer is read by the CPU, After the write to the SSPxBUF, each bit of the address the BF flag bit is automatically cleared. The user can will be shifted out on the falling edge of SCLx until all then send an Acknowledge bit at the end of reception seven address bits and the R/W bit are completed. On by setting the Acknowledge Sequence Enable bit, the falling edge of the eighth clock, the master will ACKEN (SSPxCON2<4>). deassert the SDAx pin, allowing the slave to respond 19.4.11.1 BF Status Flag with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the In receive operation, the BF bit is set when an address address was recognized by a slave. The status of the or data byte is loaded into SSPxBUF from SSPxSR. It ACK bit is loaded into the ACKSTAT status bit is cleared when the SSPxBUF register is read. (SSPxCON2<6>). Following the falling edge of the 19.4.11.2 SSPOV Status Flag ninth clock transmission of the address, the SSPxIF flag is set, the BF flag is cleared and the Baud Rate In receive operation, the SSPOV bit is set when 8 bits Generator is turned off until another write to the are received into the SSPxSR and the BF flag bit is SSPxBUF takes place, holding SCLx low and allowing already set from a previous reception. SDAx to float. 19.4.11.3 WCOL Status Flag 19.4.10.1 BF Status Flag If the user writes the SSPxBUF when a receive is In Transmit mode, the BF bit (SSPxSTAT<0>) is set already in progress (i.e., SSPxSR is still shifting in a when the CPU writes to SSPxBUF and is cleared when data byte), the WCOL bit is set and the contents of the all 8 bits are shifted out. buffer are unchanged (the write doesn’t occur). 19.4.10.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur) after 2TCY after the SSPxBUF write. If SSPxBUF is rewritten within 2 TCY, the WCOL bit is set and SSPxBUF is updated. This may result in a corrupted transfer. © 2009 Microchip Technology Inc. DS39775C-page 269

PIC18F87J50 FAMILY FIGURE 19-23: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 AT in ON2 = oftware STxC P n s ACKSSP ared i K e >) AC 9 Cl 6 N2< D0 8 e slave, clear ACKSTAT bit (SSPxCO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared in software service routinfrom MSSP interrupt SSPxBUF is written in software om D7 1 xIF Fr ow SP = 0 SCLx held lwhile CPUsponds to S CK re = 0 A W, 9 are R/W A1 ess and R/ 78 d by hardw ave A2 addr 6 eare PxCON2<0> (SEN = ),1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPxBUF written with 7-bit start transmit 12345 Cleared in software SSPxBUF written After Start condition, SEN cl Sn Write SStart co S T<0>) A T S x F SP SDAx SCLx SSPxI BF (S SEN PEN R/W DS39775C-page 270 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 19-24: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) e et ACKEN, start Acknowledge sequence,DAx = ACKDT = 1 PEN bit = 1N clearedwritten herematically D0ACK Bus masterACK is not sentterminatestransfer98PSet SSPxIF at endof receiveSet SSPxIF interruptat end of Acknowledgsequence Set P bit (SSPxSTAT<4>)Cleared insoftwareand SSPxIF SSPOV is set becauseSSPxBUF is still full SS RCEauto D1 7 CLK Write to SSPxCON2<4>to start Acknowledge sequence,SDAx = ACKDT (SSPxCON2<5>) = 0 ACK from master,er configured as a receiverSDAx = ACKDT = 0ogramming SSPxCON2<3> (RCEN = )1 RCEN = , start1RCEN clearednext receiveautomatically Receiving Data from SlaveReceiving Data from SlaveACKD2D5D2D5D3D4D6D7D3D4D6D7D1D0 678956512343124 Data shifted in on falling edge of Set SSPxIF interruptSet SSPxIF interruptat end of receiveat end of Acknowledgesequence Cleared in softwareCleared in softwareCleared in software Last bit is shifted into SSPxSR andcontents are unloaded into SSPxBUF Mastby pr ACK from Slave R/W = 0A1ACK 798 e, Write to SSPxCON2<0> (SEN = ),1begin Start condition SEN = 0Write to SSPxBUF occurs herstart XMIT Transmit Address to Slave A7A6A5A4A3A2SDAx 361245SCLxS SSPxIF Cleared in softwareSDAx = , SCLx = ,01while CPU responds to SSPxIF BF (SSPxSTAT<0>) SSPOV ACKEN © 2009 Microchip Technology Inc. DS39775C-page 271

PIC18F87J50 FAMILY 19.4.12 ACKNOWLEDGE SEQUENCE 19.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDAx pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPxCON2<2>). At the end of a (SSPxCON2<4>). When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDAx pin. If the user wishes to the master will assert the SDAx line low. When the generate an Acknowledge, then the ACKDT bit should SDAx line is sampled low, the Baud Rate Generator is be cleared. If not, the user should set the ACKDT bit reloaded and counts down to 0. When the Baud Rate before starting an Acknowledge sequence. The Baud Generator times out, the SCLx pin will be brought high Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count) (TBRG) and the SCLx pin is deasserted (pulled high). later, the SDAx pin will be deasserted. When the SDAx When the SCLx pin is sampled high (clock arbitration), pin is sampled high while SCLx is high, the P bit the Baud Rate Generator counts for TBRG; the SCLx pin (SSPxSTAT<4>) is set. A TBRG later, the PEN bit is is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure19-26). matically cleared, the Baud Rate Generator is turned off 19.4.13.1 WCOL Status Flag and the MSSP module then goes into an inactive state (Figure19-25). If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the 19.4.12.1 WCOL Status Flag contents of the buffer are unchanged (the write doesn’t If the user writes the SSPxBUF when an Acknowledge occur). sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 19-25: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPxCON2, ACKEN = 1, ACKDT = 0 TBRG TBRG SDAx D0 ACK SCLx 8 9 SSPxIF Cleared in SSPxIF set at Cleared in software the end of receive software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 19-26: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPxCON2, SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG set PEN after SDAx sampled high. P bit (SSPxSTAT<4>) is set Falling edge of PEN bit (SSPxCON2<2>) is cleared by 9th clock hardware and the SSPxIF bit is set TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. DS39775C-page 272 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.4.14 SLEEP OPERATION 19.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master 19.4.15 EFFECTS OF A RESET outputs a ‘1’ on SDAx, by letting SDAx float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCLx pin floats current transfer. high, data should be stable. If the expected data on SDAx is a ‘1’ and the data sampled on the SDAx 19.4.16 MULTI-MASTER MODE pin=0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF In Multi-Master mode, the interrupt generation on the and reset the I2C port to its Idle state (Figure19-27). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDAx and SCLx lines are deasserted and be taken when the P bit (SSPxSTAT<4>) is set, or the the SSPxBUF can be written to. When the user services bus is Idle, with both the S and P bits clear. When the the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the MSSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDAx line must be If a Start, Repeated Start, Stop or Acknowledge condition monitored for arbitration to see if the signal level is the was in progress when the bus collision occurred, the con- expected output level. This check is performed in dition is aborted, the SDAx and SCLx lines are hardware with the result placed in the BCLxIF bit. deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services The states where arbitration can be lost are: the bus collision Interrupt Service Routine, and if the I2C • Address Transfer bus is free, the user can resume communication by • Data Transfer asserting a Start condition. • A Start Condition The master will continue to monitor the SDAx and SCLx • A Repeated Start Condition pins. If a Stop condition occurs, the SSPxIF bit will be set. • An Acknowledge Condition A write to the SSPxBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 19-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDAx. While SCLx is high, Data changes SDAx line pulled low data doesn’t match what is driven while SCLx = 0 by another source by the master; bus collision has occurred SDAx released by master SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF © 2009 Microchip Technology Inc. DS39775C-page 273

PIC18F87J50 FAMILY 19.4.17.1 Bus Collision During a Start If the SDAx pin is sampled low during this count, the Condition BRG is reset and the SDAx line is asserted early (Figure19-30). If, however, a ‘1’ is sampled on the During a Start condition, a bus collision occurs if: SDAx pin, the SDAx pin is asserted low at the end of a) SDAx or SCLx is sampled low at the beginning the BRG count. The Baud Rate Generator is then of the Start condition (Figure19-28). reloaded and counts down to 0. If the SCLx pin is b) SCLx is sampled low before SDAx is asserted sampled as ‘0’ during this time, a bus collision does not low (Figure19-29). occur. At the end of the BRG count, the SCLx pin is asserted low. During a Start condition, both the SDAx and the SCLx pins are monitored. Note: The reason that bus collision is not a factor during a Start condition is that no two bus If the SDAx pin is already low, or the SCLx pin is masters can assert a Start condition at the already low, then all of the following occur: exact same time. Therefore, one master • the Start condition is aborted, will always assert SDAx before the other. • the BCLxIF flag is set and This condition does not cause a bus colli- • the MSSP module is reset to its inactive state sion because the two masters must be (Figure19-28) allowed to arbitrate the first address The Start condition begins with the SDAx and SCLx following the Start condition. If the address pins deasserted. When the SDAx pin is sampled high, is the same, arbitration must be allowed to the Baud Rate Generator is loaded from continue into the data portion, Repeated SSPxADD<6:0> and counts down to 0. If the SCLx pin Start or Stop conditions. is sampled low while SDAx is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 19-28: BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDAx = 1, SCLx = 1 MSSP module reset into Idle state. SEN SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because BCLxIF SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared in software S SSPxIF SSPxIF and BCLxIF are cleared in software DS39775C-page 274 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 19-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start SCLx sequence if SDAx = 1, SCLx = 1 SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared in software S ‘0’ ‘0’ SSPxIF ‘0’ ‘0’ FIGURE 19-30: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Set SSPxIF Less than TBRG TBRG SDAx SDAx pulled low by other master. Reset BRG and assert SDAx. SCLx S SCLx pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 BCLxIF ‘0’ S SSPxIF SDAx = 0, SCLx = 1, Interrupts cleared set SSPxIF in software © 2009 Microchip Technology Inc. DS39775C-page 275

PIC18F87J50 FAMILY 19.4.17.2 Bus Collision During a Repeated If SDAx is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, see Figure19-31). If SDAx is sampled high, the BRG is During a Repeated Start condition, a bus collision reloaded and begins counting. If SDAx goes from occurs if: high-to-low before the BRG times out, no bus collision a) A low level is sampled on SDAx when SCLx occurs because no two masters can assert SDAx at goes from a low level to a high level. exactly the same time. b) SCLx goes low before SDAx is asserted low, If SCLx goes from high-to-low before the BRG times indicating that another master is attempting to out and SDAx has not already been asserted, a bus transmit a data ‘1’. collision occurs. In this case, another master is When the user deasserts SDAx and the pin is allowed attempting to transmit a data ‘1’ during the Repeated to float high, the BRG is loaded with SSPxADD<6:0> Start condition (see Figure19-32). and counts down to 0. The SCLx pin is then deasserted If, at the end of the BRG time-out, both SCLx and SDAx and when sampled high, the SDAx pin is sampled. are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. FIGURE 19-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared in software S ‘0’ SSPxIF ‘0’ FIGURE 19-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx SCLx goes low before SDAx, BCLxIF set BCLxIF. Release SDAx and SCLx. Interrupt cleared in software RSEN S ‘0’ SSPxIF DS39775C-page 276 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 19.4.17.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low. Condition When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with a) After the SDAx pin has been deasserted and SSPxADD<6:0> and counts down to 0. After the BRG allowed to float high, SDAx is sampled low after times out, SDAx is sampled. If SDAx is sampled low, a the BRG has timed out. bus collision has occurred. This is due to another b) After the SCLx pin is deasserted, SCLx is master attempting to drive a data ‘0’ (Figure19-33). If sampled low before SDAx goes high. the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure19-34). FIGURE 19-33: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDAx sampled low after TBRG, set BCLxIF SDAx SDAx asserted low SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ FIGURE 19-34: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes low before SDAx goes high, Assert SDAx set BCLxIF SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ © 2009 Microchip Technology Inc. DS39775C-page 277

PIC18F87J50 FAMILY TABLE 19-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 64 PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE 64 IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 64 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 64 SSP1BUF MSSP1 Receive Buffer/Transmit Register 62 SSP1ADD MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) 65 SSPxMSK(1) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 65 SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 62, 65 SSPxCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 62, 65 GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN SSPxSTAT SMP CKE D/A P S R/W UA BF 62, 65 SSP2BUF MSSP2 Receive Buffer/Transmit Register 62 SSP2ADD MSSP2 Address Register (I2C Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode. Note 1: SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I2C™ Slave operating modes in 7-bit Masking mode. See Section19.4.3.4 “7-Bit Address Masking Mode” for more details. 2: Alternate bit definitions for use in I2C Slave mode operations only. DS39775C-page 278 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 20.0 ENHANCED UNIVERSAL The pins of EUSART1 and EUSART2 are multiplexed SYNCHRONOUS with the functions of PORTC (RC6/TX1/CK1 and RC7/RX1/DT1) and PORTG (RG1/TX2/CK2 and ASYNCHRONOUS RECEIVER RG2/RX2/DT2), respectively. In order to configure TRANSMITTER (EUSART) these pins as an EUSART: The Enhanced Universal Synchronous Asynchronous • For EUSART1: Receiver Transmitter (EUSART) module is one of two - bit SPEN (RCSTA1<7>) must be set (= 1) serial I/O modules. (Generically, the EUSART is also - bit TRISC<7> must be set (= 1) known as a Serial Communications Interface or SCI.) - bit TRISC<6> must be cleared (= 0) for The EUSART can be configured as a full-duplex Asynchronous and Synchronous Master asynchronous system that can communicate with modes peripheral devices, such as CRT terminals and - bit TRISC<6> must be set (= 1) for personal computers. It can also be configured as a Synchronous Slave mode half-duplex synchronous system that can communicate • For EUSART2: with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. - bit SPEN (RCSTA2<7>) must be set (= 1) - bit TRISG<2> must be set (= 1) The Enhanced USART module implements additional features, including automatic baud rate detection and - bit TRISG<1> must be cleared (= 0) for calibration, automatic wake-up on Sync Break recep- Asynchronous and Synchronous Master tion and 12-bit Break character transmit. These make it modes ideally suited for use in Local Interconnect Network bus - bit TRISC<6> must be set (= 1) for (LIN bus) systems. Synchronous Slave mode All members of the PIC18F87J10 family are equipped Note: The EUSART control will automatically with two independent EUSART modules, referred to as reconfigure the pin from input to output as EUSART1 and EUSART2. They can be configured in needed. the following modes: The TXx/CKx I/O pins have an optional open-drain out- • Asynchronous (full duplex) with: put capability. By default, when this pin is used by the - Auto-wake-up on character reception EUSART as an output, it will function as a standard push-pull CMOS output. The TXx/CKx I/O pins’ - Auto-baud calibration open-drain, output feature can be enabled by setting - 12-bit Break character transmission the corresponding UxOD bit in the ODCON2 register. • Synchronous – Master (half duplex) with For more details, see Section10.1.4 “Open-Drain selectable clock polarity Outputs”. • Synchronous – Slave (half duplex) with selectable The operation of each Enhanced USART module is clock polarity controlled through three registers: • Transmit Status and Control (TXSTAx) • Receive Status and Control (RCSTAx) • Baud Rate Control (BAUDCONx) These are detailed on the following pages in Register20-1, Register20-2 and Register20-3, respectively. Note: Throughout this section, references to register and bit names that may be associ- ated with a specific EUSART module are referred to generically by the use of ‘x’ in place of the specific module number. Thus, “RCSTAx” might refer to the Receive Status register for either EUSART1 or EUSART2. © 2009 Microchip Technology Inc. DS39775C-page 279

PIC18F87J50 FAMILY REGISTER 20-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39775C-page 280 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 20-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-Bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-Bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREGx register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2009 Microchip Technology Inc. DS39775C-page 281

PIC18F87J50 FAMILY REGISTER 20-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 DTRXP: Data/Receive Polarity Select bit Asynchronous mode: 1 = Receive data (RXx) is inverted (active low) 0 = Receive data (RXx) is not inverted (active high) Synchronous mode: 1 = Data (DTx) is inverted (active low) 0 = Data (DTx) is not inverted (active high) bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TXx) is a low level 0 = Idle state for transmit (TXx) is a high level Synchronous mode: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator – SPBRGx only (Compatible mode), SPBRGHx value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RXx pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39775C-page 282 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 20.1 Baud Rate Generator (BRG) the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate The BRG is a dedicated, 8-bit or 16-bit generator that for a fast oscillator frequency. supports both the Asynchronous and Synchronous Writing a new value to the SPBRGHx:SPBRGx regis- modes of the EUSART. By default, the BRG operates ters causes the BRG timer to be reset (or cleared). This in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) ensures the BRG does not wait for a timer overflow selects 16-bit mode. before outputting the new baud rate. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits 20.1.1 OPERATION IN POWER-MANAGED BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also MODES control the baud rate. In Synchronous mode, BRGH is The device clock is used to generate the desired baud ignored. Table20-1 shows the formula for computation of rate. When one of the power-managed modes is the baud rate for different EUSART modes which only entered, the new clock source may be operating at a apply in Master mode (internally generated clock). different frequency. This may require an adjustment to Given the desired baud rate and FOSC, the nearest the value in the SPBRGx register pair. integer value for the SPBRGHx:SPBRGx registers can be calculated using the formulas in Table20-1. From this, 20.1.2 SAMPLING the error in baud rate can be determined. An example The data on the RXx pin (either RC7/RX1/DT1 or calculation is shown in Example20-1. Typical baud rates RG2/RX2/DT2) is sampled three times by a majority and error values for the various Asynchronous modes detect circuit to determine if a high or a low level is are shown in Table20-2. It may be advantageous to use present at the RXx pin. TABLE 20-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair © 2009 Microchip Technology Inc. DS39775C-page 283

PIC18F87J50 FAMILY EXAMPLE 20-1: CALCULATING BAUD RATE ERROR For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 20-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page: TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 63 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 63 BAUDCONx ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN 65 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 65 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39775C-page 284 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615. -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — © 2009 Microchip Technology Inc. DS39775C-page 285

PIC18F87J50 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — DS39775C-page 286 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 20.1.3 AUTO-BAUD RATE DETECT Note1: If the WUE bit is set with the ABDEN bit, The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on detection and calibration of baud rate. This feature is the byte following the Break character. active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the bit is clear. incoming character baud rate is within the The automatic baud rate measurement sequence range of the selected BRG clock source. (Figure20-1) begins whenever a Start bit is received Some combinations of oscillator frequency and the ABDEN bit is set. The calculation is and EUSART baud rates are not possible self-averaging. due to bit error rates. Overall system tim- ing and communication baud rates must In the Auto-Baud Rate Detect (ABD) mode, the clock to be taken into consideration when using the the BRG is reversed. Rather than the BRG clocking the Auto-Baud Rate Detection feature. incoming RXx signal, the RXx signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming TABLE 20-4: BRG COUNTER serial byte stream. CLOCK RATES Once the ABDEN bit is set, the state machine will clear BRG16 BRGH BRG Counter Clock the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value 55h (ASCII 0 0 FOSC/512 “U”, which is also the LIN bus Sync character) in order to 0 1 FOSC/128 calculate the proper bit rate. The measurement is taken 1 0 FOSC/128 over both a low and a high bit time in order to minimize 1 1 FOSC/32 any effects caused by asymmetry of the incoming signal. Note: During the ABD sequence, SPBRGx and After a Start bit, the SPBRGx begins counting up, using SPBRGHx are both used as a 16-bit counter, the preselected clock source on the first rising edge of independent of BRG16 setting. RXx. After eight bits on the RXx pin or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGHx:SPBRGx register pair. 20.1.3.1 ABD and EUSART Transmission Once the 5th edge is seen (this should correspond to the Since the BRG clock is reversed during ABD acquisi- Stop bit), the ABDEN bit is automatically cleared. tion, the EUSART transmitter cannot be used during If a rollover of the BRG occurs (an overflow from FFFFh ABD. This means that whenever the ABDEN bit is set, to 0000h), the event is trapped by the ABDOVF status TXREGx cannot be written to. Users should also bit (BAUDCONx<7>). It is set in hardware by BRG roll- ensure that ABDEN does not become set during a overs and can be set or cleared by the user in software. transmit sequence. Failing to do this may result in ABD mode remains active after rollover events and the unpredictable EUSART operation. ABDEN bit remains set (Figure20-2). While calibrating the baud rate period, the BRG regis- ters are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRGx and SPBRGHx will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table20-4 for coun- ter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCxIF interrupt is set once the fifth rising edge on RXx is detected. The value in the RCREGx needs to be read to clear the RCxIF interrupt. The contents of RCREGx should be discarded. © 2009 Microchip Technology Inc. DS39775C-page 287

PIC18F87J50 FAMILY FIGURE 20-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RXx pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE=0. FIGURE 20-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RXx pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h DS39775C-page 288 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 20.2 EUSART Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is The Asynchronous mode of operation is selected by empty and the TXxIF flag bit is set. This interrupt can be clearing the SYNC bit (TXSTAx<4>). In this mode, the enabled or disabled by setting or clearing the interrupt EUSART uses standard Non-Return-to-Zero (NRZ) enable bit, TXxIE. TXxIF will be set regardless of the format (one Start bit, eight or nine data bits and one Stop state of TXxIE; it cannot be cleared in software. TXxIF is bit). The most common data format is 8 bits. An on-chip also not cleared immediately upon loading TXREGx, but dedicated 8-bit/16-bit Baud Rate Generator can be used becomes valid in the second instruction cycle following to derive standard baud rate frequencies from the the load instruction. Polling TXxIF immediately following oscillator. a load of TXREGx will return invalid results. The EUSART transmits and receives the LSb first. The While TXxIF indicates the status of the TXREGx regis- EUSART’s transmitter and receiver are functionally independent but use the same data format and baud ter; another bit, TRMT (TXSTAx<1>), shows the status rate. The Baud Rate Generator produces a clock, either of the TSR register. TRMT is a read-only bit which is set x16 or x64 of the bit shift rate, depending on the BRGH when the TSR register is empty. No interrupt logic is and BRG16 bits (TXSTAx<2> and BAUDCONx<3>). tied to this bit so the user has to poll this bit in order to Parity is not supported by the hardware but can be determine if the TSR register is empty. implemented in software and stored as the 9th data bit. Note1: The TSR register is not mapped in data When operating in Asynchronous mode, the EUSART memory, so it is not available to the user. module consists of the following important elements: 2: Flag bit TXxIF is set when enable bit, • Baud Rate Generator TXEN, is set. • Sampling Circuit To set up an Asynchronous Transmission: • Asynchronous Transmitter 1. Initialize the SPBRGHx:SPBRGx registers for • Asynchronous Receiver the appropriate baud rate. Set or clear the • Auto-Wake-up on Sync Break Character BRGH and BRG16 bits, as required, to achieve • 12-Bit Break Character Transmit the desired baud rate. • Auto-Baud Rate Detection 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit, SPEN. 20.2.1 EUSART ASYNCHRONOUS 3. If interrupts are desired, set enable bit, TXxIE. TRANSMITTER 4. If 9-bit transmission is desired, set transmit bit The EUSART transmitter block diagram is shown in TX9. Can be used as address/data bit. Figure20-3. The heart of the transmitter is the Transmit 5. Enable the transmission by setting bit, TXEN, (Serial) Shift Register (TSR). The Shift register obtains which will also set bit, TXxIF. its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit TXREGx. The TXREGx register is loaded with data in should be loaded in bit, TX9D. software. The TSR register is not loaded until the Stop 7. Load data to the TXREGx register (starts bit has been transmitted from the previous load. As transmission). soon as the Stop bit is transmitted, the TSR is loaded 8. If using interrupts, ensure that the GIE and PEIE with new data from the TXREGx register (if available). bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR Register TXx pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGHx SPBRGx TX9 Baud Rate Generator TX9D © 2009 Microchip Technology Inc. DS39775C-page 289

PIC18F87J50 FAMILY FIGURE 20-4: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 20-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXxIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 63 TXREGx EUSARTx Transmit Register 63 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 63 BAUDCONx ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN 65 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 65 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 65 ODCON2 — — — — U2OD U1OD 62 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. DS39775C-page 290 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 20.2.2 EUSART ASYNCHRONOUS 20.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure20-6. This mode would typically be used in RS-485 systems. The data is received on the RXx pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGHx:SPBRGx registers for whereas the main receive serial shifter operates at the the appropriate baud rate. Set or clear the bit rate or at FOSC. This mode would typically be used BRGH and BRG16 bits, as required, to achieve in RS-232 systems. the desired baud rate. To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing 1. Initialize the SPBRGHx:SPBRGx registers for the SYNC bit and setting the SPEN bit. the appropriate baud rate. Set or clear the 3. If interrupts are required, set the RCEN bit and BRGH and BRG16 bits, as required, to achieve select the desired priority level with the RCxIP bit. the desired baud rate. 4. Set the RX9 bit to enable 9-bit reception. 2. Enable the asynchronous serial port by clearing 5. Set the ADDEN bit to enable address detect. bit, SYNC, and setting bit, SPEN. 6. Enable reception by setting the CREN bit. 3. If interrupts are desired, set enable bit, RCxIE. 7. The RCxIF bit will be set when reception is 4. If 9-bit reception is desired, set bit, RX9. complete. The interrupt will be Acknowledged if 5. Enable the reception by setting bit, CREN. the RCxIE and GIE bits are set. 6. Flag bit, RCxIF, will be set when reception is 8. Read the RCSTAx register to determine if any complete and an interrupt will be generated if error occurred during reception, as well as read enable bit, RCxIE, was set. bit 9 of data (if applicable). 7. Read the RCSTAx register to get the 9th bit (if 9. Read RCREGx to determine if the device is enabled) and determine if any error occurred being addressed. during reception. 10. If any error occurred, clear the CREN bit. 8. Read the 8-bit received data by reading the 11. If the device has been addressed, clear the RCREGx register. ADDEN bit to allow all received data into the 9. If any error occurred, clear the error by clearing receive buffer and interrupt the CPU. enable bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-6: EUSARTx RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGHx SPBRGx ÷ o6r4 MSb RSR Register LSb ÷ 16 or Stop (8) 7 • • • 1 0 Start Baud Rate Generator ÷ 4 RX9 Pin Buffer Data and Control Recovery RXx RX9D RCREGx Register FIFO SPEN 8 Interrupt RCxIF Data Bus RCxIE © 2009 Microchip Technology Inc. DS39775C-page 291

PIC18F87J50 FAMILY FIGURE 20-7: ASYNCHRONOUS RECEPTION RXx (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREGx RCREGx Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set. TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 63 RCREGx EUSARTx Receive Register 63 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 63 BAUDCONx ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN 65 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 65 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 65 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. 20.2.4 AUTO-WAKE-UP ON SYNC BREAK the RXx/DTx line. (This coincides with the start of a CHARACTER Sync Break or a Wake-up Signal character for the LIN protocol.) During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator Following a wake-up event, the module generates an is inactive and a proper byte reception cannot be per- RCxIF interrupt. The interrupt is generated synchro- formed. The auto-wake-up feature allows the controller nously to the Q clocks in normal operating modes to wake-up due to activity on the RXx/DTx line while the (Figure20-8) and asynchronously if the device is in EUSART is operating in Asynchronous mode. Sleep mode (Figure20-9). The interrupt condition is cleared by reading the RCREGx register. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>). Once set, the typical The WUE bit is automatically cleared once a receive sequence on RXx/DTx is disabled and the low-to-high transition is observed on the RXx line EUSART remains in an Idle state, monitoring for a following the wake-up event. At this point, the EUSART wake-up event independent of the CPU mode. A module is in Idle mode and returns to normal operation. wake-up event consists of a high-to-low transition on This signals to the user that the Sync Break event is over. DS39775C-page 292 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 20.2.4.1 Special Considerations Using 20.2.4.2 Special Considerations Using Auto-Wake-up the WUE Bit Since auto-wake-up functions by sensing rising edge The timing of WUE and RCxIF events may cause some transitions on RXx/DTx, information with any state confusion when it comes to determining the validity of changes before the Stop bit may signal a false received data. As noted, setting the WUE bit places the End-of-Character (EOC) and cause data or framing EUSART in an Idle mode. The wake-up event causes a errors. To work properly, therefore, the initial character receive interrupt by setting the RCxIF bit. The WUE bit in the transmission must be all ‘0’s. This can be 00h (8 is cleared after this when a rising edge is seen on bytes) for standard RS-232 devices or 000h (12 bits) for RXx/DTx. The interrupt condition is then cleared by LIN bus. reading the RCREGx register. Ordinarily, the data in RCREGx will be dummy data and should be discarded. Oscillator start-up time must also be considered, especially in applications using oscillators with longer The fact that the WUE bit has been cleared (or is still start-up intervals (i.e., HS or HSPLL mode). The Sync set) and the RCxIF flag is set should not be used as an Break (or Wake-up Signal) character must be of indicator of the integrity of the data in RCREGx. Users sufficient length and be followed by a sufficient interval should consider implementing a parallel method in to allow enough time for the selected oscillator to start firmware to verify received data integrity. and provide proper initialization of the EUSART. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. FIGURE 20-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RXx/DTx Line RCxIF Cleared due to user read of RCREGx Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 20-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RXx/DTx Line Note 1 RCxIF Cleared due to user read of RCREGx SLEEP Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. © 2009 Microchip Technology Inc. DS39775C-page 293

PIC18F87J50 FAMILY 20.2.5 BREAK CHARACTER SEQUENCE 1. Configure the EUSART for the desired mode. The EUSART module has the capability of sending the 2. Set the TXEN and SENDB bits to set up the special Break character sequences that are required by Break character. the LIN bus standard. The Break character transmit 3. Load the TXREGx with a dummy character to consists of a Start bit, followed by twelve ‘0’ bits and a initiate transmission (the value is ignored). Stop bit. The Frame Break character is sent whenever 4. Write ‘55h’ to TXREGx to load the Sync the SENDB and TXEN bits (TXSTAx<3> and character into the transmit FIFO buffer. TXSTAx<5>) are set while the Transmit Shift Register 5. After the Break has been sent, the SENDB bit is is loaded with data. Note that the value of data written reset by hardware. The Sync character now to TXREGx will be ignored and all ‘0’s will be transmits in the preconfigured mode. transmitted. When the TXREGx becomes empty, as indicated by The SENDB bit is automatically reset by hardware after the TXxIF, the next data byte can be written to the corresponding Stop bit is sent. This allows the user TXREGx. to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync 20.2.6 RECEIVING A BREAK CHARACTER character in the LIN specification). The Enhanced USART module can receive a Break Note that the data value written to the TXREGx for the character in two ways. Break character is ignored. The write simply serves the The first method forces configuration of the baud rate purpose of initiating the proper sequence. at a frequency of 9/13 the typical speed. This allows for The TRMT bit indicates when the transmit operation is the Stop bit transition to be at the correct sampling active or Idle, just as it does during normal transmis- location (13 bits for Break versus Start bit and 8 data sion. See Figure20-10 for the timing of the Break bits for typical data). character sequence. The second method uses the auto-wake-up feature 20.2.5.1 Break and Sync Transmit Sequence described in Section20.2.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the The following sequence will send a message frame EUSART will sample the next two transitions on header made up of a Break, followed by an Auto-Baud RXx/DTx, cause an RCxIF interrupt and receive the Sync byte. This sequence is typical of a LIN bus next data byte followed by another interrupt. master. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABDEN bit once the TXxIF interrupt is observed. FIGURE 20-10: SEND BREAK CHARACTER SEQUENCE Write to TXREGx Dummy Write BRG Output (Shift Clock) TXx (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB bit (Transmit Shift Reg. Empty Flag) DS39775C-page 294 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 20.3 EUSART Synchronous Once the TXREGx register transfers the data to the Master Mode TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be The Synchronous Master mode is entered by setting enabled or disabled by setting or clearing the interrupt the CSRC bit (TXSTAx<7>). In this mode, the data is enable bit, TXxIE. TXxIF is set regardless of the state transmitted in a half-duplex manner (i.e., transmission of enable bit, TXxIE; it cannot be cleared in software. It and reception do not occur at the same time). When will reset only when new data is loaded into the transmitting data, the reception is inhibited and vice TXREGx register. versa. Synchronous mode is entered by setting bit, While flag bit, TXxIF, indicates the status of the TXREGx SYNC (TXSTAx<4>). In addition, enable bit, SPEN register, another bit, TRMT (TXSTAx<1>), shows the (RCSTAx<7>), is set in order to configure the TXx and status of the TSR register. TRMT is a read-only bit which RXx pins to CKx (clock) and DTx (data) lines, is set when the TSR is empty. No interrupt logic is tied to respectively. this bit, so the user must poll this bit in order to determine The Master mode indicates that the processor trans- if the TSR register is empty. The TSR is not mapped in mits the master clock on the CKx line. Clock polarity is data memory so it is not available to the user. selected with the SCKP bit (BAUDCONx<4>). Setting To set up a Synchronous Master Transmission: SCKP sets the Idle state on CKx as high, while clearing the bit sets the Idle state as low. This option is provided 1. Initialize the SPBRGHx:SPBRGx registers for the to support Microwire devices with this module. appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. 20.3.1 EUSART SYNCHRONOUS MASTER 2. Enable the synchronous master serial port by TRANSMISSION setting bits, SYNC, SPEN and CSRC. The EUSART transmitter block diagram is shown in 3. If interrupts are desired, set enable bit, TXxIE. Figure20-3. The heart of the transmitter is the Transmit 4. If 9-bit transmission is desired, set bit, TX9. (Serial) Shift Register (TSR). The Shift register obtains 5. Enable the transmission by setting bit, TXEN. its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit TXREGx. The TXREGx register is loaded with data in should be loaded in bit, TX9D. software. The TSR register is not loaded until the last 7. Start transmission by loading data to the bit has been transmitted from the previous load. As TXREGx register. soon as the last bit is transmitted, the TSR is loaded with new data from the TXREGx (if available). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX1/CK1 pin (SCKP = 0) RC6/TX1/CK1 pin (SCKP = 1) Write to TXREG1 Reg Write Word 1 Write Word 2 TX1IF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2). © 2009 Microchip Technology Inc. DS39775C-page 295

PIC18F87J50 FAMILY FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2). TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 63 TXREGx EUSARTx Transmit Register 63 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 63 BAUDCONx ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN 65 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 65 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 65 ODCON2 — — — — U2OD U1OD 62 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. DS39775C-page 296 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 20.3.2 EUSART SYNCHRONOUS 3. Ensure bits, CREN and SREN, are clear. MASTER RECEPTION 4. If interrupts are desired, set enable bit, RCxIE. 5. If 9-bit reception is desired, set bit, RX9. Once Synchronous mode is selected, reception is 6. If a single reception is required, set bit, SREN. enabled by setting either the Single Receive Enable bit, For continuous reception, set bit, CREN. SREN (RCSTAx<5>) or the Continuous Receive 7. Interrupt flag bit, RCxIF, will be set when recep- Enable bit, CREN (RCSTAx<4>). Data is sampled on tion is complete and an interrupt will be generated the RXx pin on the falling edge of the clock. if the enable bit, RCxIE, was set. If enable bit, SREN, is set, only a single word is 8. Read the RCSTAx register to get the 9th bit (if received. If enable bit, CREN, is set, the reception is enabled) and determine if any error occurred continuous until CREN is cleared. If both bits are set, during reception. then CREN takes precedence. 9. Read the 8-bit received data by reading the To set up a Synchronous Master Reception: RCREGx register. 1. Initialize the SPBRGHx:SPBRGx registers for the 10. If any error occurred, clear the error by clearing appropriate baud rate. Set or clear the BRG16 bit, CREN. bit, as required, to achieve the desired baud rate. 11. If using interrupts, ensure that the GIE and PEIE bits 2. Enable the synchronous master serial port by in the INTCON register (INTCON<7:6>) are set. setting bits, SYNC, SPEN and CSRC. FIGURE 20-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX1/CK1 pin (SCKP = 0) RC6/TX1/CK1 pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RC1IF bit (Interrupt) Read RCREG1 Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2). © 2009 Microchip Technology Inc. DS39775C-page 297

PIC18F87J50 FAMILY TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 63 RCREGx EUSARTx Receive Register 63 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 63 BAUDCONx ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN 65 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 65 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 65 ODCON2 — — — — U2OD U1OD 62 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. 20.4 EUSART Synchronous To set up a Synchronous Slave Transmission: Slave Mode 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, Synchronous Slave mode is entered by clearing bit, CSRC. CSRC (TXSTAx<7>). This mode differs from the 2. Clear bits, CREN and SREN. Synchronous Master mode in that the shift clock is sup- plied externally at the CKx pin (instead of being supplied 3. If interrupts are desired, set enable bit, TXxIE. internally in Master mode). This allows the device to 4. If 9-bit transmission is desired, set bit, TX9. transfer or receive data while in any low-power mode. 5. Enable the transmission by setting enable bit, TXEN. 20.4.1 EUSART SYNCHRONOUS 6. If 9-bit transmission is selected, the ninth bit SLAVE TRANSMISSION should be loaded in bit, TX9D. The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the modes is identical, except in the case of Sleep mode. TXREGx register. If two words are written to the TXREGx and then the 8. If using interrupts, ensure that the GIE and PEIE SLEEP instruction is executed, the following will occur: bits in the INTCON register (INTCON<7:6>) are set. a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in the TXREGx register. c) Flag bit, TXxIF, will not be set. d) When the first word has been shifted out of TSR, the TXREGx register will transfer the second word to the TSR and flag bit, TXxIF, will now be set. e) If enable bit, TXxIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. DS39775C-page 298 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 63 TXREGx EUSARTx Transmit Register 63 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 63 BAUDCONx ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN 65 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 65 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. 20.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical, except in the case of Sleep, or any CSRC. Idle mode and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCxIE. Slave mode. 3. If 9-bit reception is desired, set bit, RX9. If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN. entering Sleep or any Idle mode, then a word may be 5. Flag bit, RCxIF, will be set when reception is received while in this low-power mode. Once the word complete. An interrupt will be generated if is received, the RSR register will transfer the data to the enable bit, RCxIE, was set. RCREGx register. If the RCxIE enable bit is set, the 6. Read the RCSTAx register to get the 9th bit (if interrupt generated will wake the chip from the enabled) and determine if any error occurred low-power mode. If the global interrupt is enabled, the during reception. program will branch to the interrupt vector. 7. Read the 8-bit received data by reading the RCREGx register. 8. If any error occurred, clear the error by clearing bit, CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. © 2009 Microchip Technology Inc. DS39775C-page 299

PIC18F87J50 FAMILY TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 63 RCREGx EUSARTx Receive Register 63 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 63 BAUDCONx ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN 65 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 65 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. DS39775C-page 300 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 21.0 10-BIT ANALOG-TO-DIGITAL • A/D Port Configuration Register 2 (ANCON0) CONVERTER (A/D) MODULE • A/D Port Configuration Register 1 (ANCON1) • A/D Result Registers (ADRESH and ADRESL) The Analog-to-Digital (A/D) Converter module has The ADCON0 register, shown in Register21-1, controls 8inputs for the 64-pin devices and 12 for the 80-pin the operation of the A/D module. The ADCON1 register, devices. This module allows conversion of an analog shown in Register21-2, configures the A/D clock source, input signal to a corresponding 10-bit digital number. programmed acquisition time and justification. The module has six registers: The ANCON0 and ANCON1 registers, shown in • A/D Control Register 0 (ADCON0) Register21-4 and Register21-3, configure the • A/D Control Register 1 (ADCON1) functions of the port pins. REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VCFG1 VCFG0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = AVSS bit VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = AVDD bit 5-2 CHS3:CHS0: Analog Channel Select bits 0000 = Channel 00 (AN0) 0001 = Channel 01 (AN1) 0010 = Channel 02 (AN2) 0011 = Channel 03 (AN3) 0100 = Channel 04 (AN4) 0101 = Unused 0110 = Unused 0111 = Channel 07 (AN7) 1000 = Unused 1001 = Unused 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12)(2,3) 1101 = Channel 13 (AN13)(2,3) 1110 = Channel 14 (AN14)(2,3) 1111 =Channel 15 (AN15)(2,3) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 2: These channels are not implemented on 64-pin devices. 3: Performing a conversion on unimplemented channels will return random values. © 2009 Microchip Technology Inc. DS39775C-page 301

PIC18F87J50 FAMILY REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 ADCAL: A/D Calibration bit 1 = Calibration is performed on next A/D conversion 0 = Normal A/D Converter operation (no conversion is performed) bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(2) bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(2) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(2) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 2: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. DS39775C-page 302 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY The ANCON0 and ANCON1 registers are used to ANCON0 and ANCON1 are shared address SFRs, and configure the operation of the I/O pin associated with use the same addresses as the ADCON1 and each analog channel. Setting any one of the PCFG bits ADCON0 registers. The ANCON registers are configures the corresponding pin to operate as a digital accessed by setting the ADSHR bit (WDTCON<4>). only I/O. Clearing a bit configures the pin to operate as See Section5.3.5.1 “Shared Address SFRs” for an analog input for either the A/D Converter or the com- more information. parator module; all digital peripherals are disabled, and digital inputs read as ‘0’. As a rule, I/O pins that are multiplexed with analog inputs default to analog operation on device Resets. REGISTER 21-3: ANCON0: A/D PORT CONFIGURATION REGISTER 2 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG7 — — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PCFG7: Analog Port Configuration bits (AN7) 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads ‘0’ bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 PCFG4:PCFG0: Analog Port Configuration bits (AN4-AN0) 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads ‘0’ REGISTER 21-4: ANCON1: A/D PORT CONFIGURATION REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 PCFG15:PCFG10: Analog Port Configuration bits (AN15-AN10)(1) 1 = Pin configured as a digital port 0 = Pin configured as an analog channel - digital input disabled and reads ‘0’ bit 1-0 Unimplemented: Read as ‘0’ Note 1: AN15 through AN12 are available only in 80-pin devices. © 2009 Microchip Technology Inc. DS39775C-page 303

PIC18F87J50 FAMILY The analog reference voltage is software selectable to the A/D conversion. When the A/D conversion is com- either the device’s positive and negative supply voltage plete, the result is loaded into the ADRESH:ADRESL (AVDD and AVSS), or the voltage level on the register pair, the GO/DONE bit (ADCON0<1>) is RA3/AN3/VREF+ and RA2/AN2/VREF- pins. cleared and A/D Interrupt Flag bit, ADIF, is set. The A/D Converter has a unique feature of being able A device Reset forces all registers to their Reset state. to operate while the device is in Sleep mode. To This forces the A/D module to be turned off and any operate in Sleep, the A/D conversion clock must be conversion in progress is aborted. The value in the derived from the A/D’s internal RC oscillator. ADRESH:ADRESL register pair is not modified for a Power-on Reset. These registers will contain unknown The output of the sample and hold is the input into the data after a Power-on Reset. Converter, which generates the result via successive approximation. The block diagram of the A/D module is shown in Figure21-1. Each port pin associated with the A/D Converter can be configured as an analog input or as a digital I/O. The ADRESH and ADRESL registers contain the result of FIGURE 21-1: A/D BLOCK DIAGRAM CHS3:CHS0 1111 AN15(1) 1110 AN14(1) 1101 AN13(1) 1100 AN12(1) 1011 AN11 1010 AN10 0111 AN7 0100 AN4 VAIN 10-Bit (Input Voltage) 0011 AN3 A/D Converter 0010 AN2 0001 VCFG1:VCFG0 AN1 0000 VDD(2) AN0 VREF+ Reference Voltage VREF- VSS(2) Note 1: Channels AN15 through AN12 are not available on 64-pin devices. 2: I/O pins have diode protection to VDD and VSS. DS39775C-page 304 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY After the A/D module has been configured as desired, 3. Wait the required acquisition time (if required). the selected channel must be acquired before the 4. Start conversion: conversion is started. The analog input channels must • Set GO/DONE bit (ADCON0<1>) have their corresponding TRIS bits selected as an 5. Wait for A/D conversion to complete, by either: input. To determine acquisition time, see Section21.1 “A/D Acquisition Requirements”. After this acquisi- • Polling for the GO/DONE bit to be cleared tion time has elapsed, the A/D conversion can be OR started. An acquisition time can be programmed to • Waiting for the A/D interrupt occur between setting the GO/DONE bit and the actual 6. Read A/D Result registers (ADRESH:ADRESL); start of the conversion. clear bit, ADIF, if required. The following steps should be followed to do an A/D 7. For next conversion, go to step 1 or step 2, as conversion: required. The A/D conversion time per bit is 1. Configure the A/D module: defined as TAD. A minimum wait of 2 TAD is • Configure the required ADC pins as analog required before next acquisition starts. pins using ANCON0, ANCON1 • Set voltage reference using ADCON0 • Select A/D input channel (ADCON0) • Select A/D acquisition time (ADCON1) • Select A/D conversion clock (ADCON1) • Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set GIE bit FIGURE 21-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC ≤ 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE CHOLD = 25 pF VSS Legend: CPIN = input capacitance VT = threshold voltage ILEAKAGE = leakage current at the pin due to VDD various junctions RIC = interconnect resistance SS = sampling switch CHOLD = sample/hold capacitance (from DAC) RSS = sampling switch resistance 1 2 3 4 Sampling Switch (kΩ) © 2009 Microchip Technology Inc. DS39775C-page 305

PIC18F87J50 FAMILY 21.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation21-1 may be used. This equation assumes For the A/D Converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. Analog Input model is shown in Figure21-2. The Equation21-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time, TACQ. This calculation is based on the following application system required to charge the capacitor CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 25 pF at the analog input (due to pin leakage current). The Rs = 2.5 kΩ maximum recommended impedance for analog Conversion Error ≤ 1/2 LSb sources is 2.5kΩ. After the analog input channel is VDD = 3V→Rss = 2 kΩ selected (changed), the channel must be sampled for Temperature = 85°C (system max.) at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 21-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 21-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 μs TCOFF = (Temp – 25°C)(0.02 μs/°C) (85°C – 25°C)(0.02 μs/°C) 1.2 μs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) μs -(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs 1.05 μs TACQ = 0.2 μs + 1.05 μs + 1.2 μs 2.45 μs DS39775C-page 306 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 21.2 Selecting and Configuring TABLE 21-1: TAD vs. DEVICE OPERATING Automatic Acquisition Time FREQUENCIES The ADCON1 register allows the user to select an AD Clock Source (TAD) Maximum acquisition time that occurs each time the GO/DONE Device bit is set. Operation ADCS2:ADCS0 Frequency When the GO/DONE bit is set, sampling is stopped and 2 TOSC 000 2.86 MHz a conversion begins. The user is responsible for ensur- 4 TOSC 100 5.71 MHz ing the required acquisition time has passed between 8 TOSC 001 11.43 MHz selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT2:ACQT0 16 TOSC 101 22.86 MHz bits (ADCON1<5:3>) remain in their Reset state (‘000’) 32 TOSC 010 45.71 MHz and is compatible with devices that do not offer 64 TOSC 110 48.0 MHz programmable acquisition times. RC(2) x11 1.00 MHz(1) If desired, the ACQT bits can be set to select a pro- Note 1: The RC source has a typical TAD time of grammable acquisition time for the A/D module. When 4μs. the GO/DONE bit is set, the A/D module continues to 2: For device frequencies above 1 MHz, the sample the input for the selected acquisition time, then device must be in Sleep mode for the automatically begins a conversion. Since the acquisi- entire conversion or the A/D accuracy may tion time is programmed, there may be no need to wait be out of specification. for an acquisition time between selecting a channel and setting the GO/DONE bit. 21.4 Configuring Analog Port Pins In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the The ANCON0, ANCON1, TRISA, TRISF and TRISH A/D begins sampling the currently selected channel registers control the operation of the A/D port pins. The again. If an acquisition time is programmed, there is port pins needed as analog inputs must have their cor- nothing to indicate if the acquisition time has ended or responding TRIS bits set (input). If the TRIS bit is if the conversion has begun. cleared (output), the digital output level (VOH or VOL) will be converted. 21.3 Selecting the A/D Conversion The A/D operation is independent of the state of the Clock CHS3:CHS0 bits and the TRIS bits. The A/D conversion time per bit is defined as TAD. The Note 1: When reading the PORT register, all pins A/D conversion requires 11 TAD per 10-bit conversion. configured as analog input channels will The source of the A/D conversion clock is software read as cleared (a low level). Pins config- selectable. ured as digital inputs will convert an There are seven possible options for TAD: analog input. Analog levels on a digitally configured input will be accurately • 2 TOSC converted. • 4 TOSC 2: Analog levels on any pin defined as a • 8 TOSC digital input may cause the digital input • 16 TOSC buffer to consume current out of the • 32 TOSC device’s specification limits. • 64 TOSC • Internal RC Oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD (see parameter 130 in Table28-29 for more information). Table21-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. © 2009 Microchip Technology Inc. DS39775C-page 307

PIC18F87J50 FAMILY 21.5 A/D Conversions 21.6 Use of the ECCP2 Trigger Figure21-3 shows the operation of the A/D Converter An A/D conversion can be started by the “Special Event after the GO/DONE bit has been set and the Trigger” of the ECCP2 module. This requires that the ACQT2:ACQT0 bits are cleared. A conversion is CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be started after the following instruction to allow entry into programmed as ‘1011’ and that the A/D module is Sleep mode before the conversion begins. enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition Figure21-4 shows the operation of the A/D Converter and conversion, and the Timer1 (or Timer3) counter will after the GO/DONE bit has been set, the be reset to zero. Timer1 (or Timer3) is reset to auto- ACQT2:ACQT0 bits are set to ‘010’ and selecting a matically repeat the A/D acquisition period with minimal 4TAD acquisition time before the conversion starts. software overhead (moving ADRESH/ADRESL to the Clearing the GO/DONE bit during a conversion will desired location). The appropriate analog input abort the current conversion. The A/D Result register channel must be selected and the minimum acquisition pair will NOT be updated with the partially completed period is either timed by the user, or an appropriate A/D conversion sample. This means the TACQ time is selected before the Special Event Trigger ADRESH:ADRESL registers will continue to contain sets the GO/DONE bit (starts a conversion). the value of the last completed conversion (or the last If the A/D module is not enabled (ADON is cleared), the value written to the ADRESH:ADRESL registers). Special Event Trigger will be ignored by the A/D After the A/D conversion is completed or aborted, a module but will still reset the Timer1 (or Timer3) 2TAD wait is required before the next acquisition can be counter. started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 21-3: A/D CONVERSION TAD CYCLES (ACQT2:ACQT0 = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 21-4: A/D CONVERSION TAD CYCLES (ACQT2:ACQT0 = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. DS39775C-page 308 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 21.7 A/D Converter Calibration If the A/D is expected to operate while the device is in a power-managed mode, the ACQT2:ACQT0 and The A/D Converter in the PIC18F87J10 family of ADCS2:ADCS0 bits in ADCON1 should be updated in devices includes a self-calibration feature which com- accordance with the power-managed mode clock that pensates for any offset generated within the module. will be used. After the power-managed mode is entered The calibration process is automated and is initiated by (either of the power-managed Run modes), an A/D setting the ADCAL bit (ADCON1<6>). The next time acquisition or conversion may be started. Once an the GO/DONE bit is set, the module will perform a acquisition or conversion is started, the device should “dummy” conversion (that is, with reading none of the continue to be clocked by the same power-managed input channels) and store the resulting value internally mode clock source until the conversion has been com- to compensate for the offset. Thus, subsequent offsets pleted. If desired, the device may be placed into the will be compensated. An example of a calibration corresponding power-managed Idle mode during the routine is shown in Example21-1. conversion. The calibration process assumes that the device is in a If the power-managed mode clock frequency is less relatively steady-state operating condition. If A/D than 1MHz, the A/D RC clock source should be calibration is used, it should be performed after each selected. device Reset or if there are other major changes in Operation in the Sleep mode requires the A/D RC clock operating conditions. to be selected. If bits, ACQT2:ACQT0, are set to ‘000’ 21.8 Operation in Power-Managed and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the Modes SLEEP instruction and entry to Sleep mode. The IDLEN The selection of the automatic acquisition time and A/D and SCS bits in the OSCCON register must have conversion clock is determined in part by the clock already been cleared prior to starting the conversion. source and frequency while in a power-managed mode. EXAMPLE 21-1: SAMPLE A/D CALIBRATION ROUTINE BSF WDTCON,ADSHR ;Enable write/read to the shared SFR BCF ANCON0,PCFG0 ;Make Channel 0 analog BCF WDTCON,ADSHR ;Disable write/read to the shared SFR BSF ADCON0,ADON ;Enable A/D module BSF ADCON1,ADCAL ;Enable Calibration BSF ADCON0,GO ;Start a dummy A/D conversion CALIBRATION ; BTFSC ADCON0,GO ;Wait for the dummy conversion to finish BRA CALIBRATION ; BCF ADCON1,ADCAL ;Calibration done, turn off calibration enable ;Proceed with the actual A/D conversion © 2009 Microchip Technology Inc. DS39775C-page 309

PIC18F87J50 FAMILY TABLE 21-2: SUMMARY OF A/D REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 64 PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE 64 IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP 64 ADRESH A/D Result Register High Byte 63 ADRESL A/D Result Register Low Byte 63 ADCON0(1) VCFG1 VCFG0 CHS3 CHS3 CHS1 CHS0 GO/DONE ADON 63 ANCON0(2) PCFG7 — — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 63 ADCON1(1) ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 63 ANCON1(2) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 — — 63 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 63 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 65 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 64 PORTF RF7 RF6 RF5 RF4 RF3 RF2 — — 65 TRISF TRISF5 TRISF4 TRISF5 TRISF4 TRISF3 TRISF2 — — 64 PORTH(3) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 65 TRISH(3) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 64 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0. 2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. 3: This register is not implemented on 64-pin devices. DS39775C-page 310 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 22.0 UNIVERSAL SERIAL BUS 22.1 Overview of the USB Peripheral (USB) PIC18F87J10 family devices contain a full-speed and low-speed, compatible USB Serial Interface Engine This section describes the details of the USB (SIE) that allows fast communication between any USB peripheral. Because of the very specific nature of the host and the PIC® microcontroller. The SIE can be module, knowledge of USB is expected. Some interfaced directly to the USB, utilizing the internal high-level USB information is provided in Section22.9 transceiver. “Overview of USB” only for application design refer- ence. Designers are encouraged to refer to the official Some special hardware features have been included to specification published by the USB Implementers improve performance. Dual access port memory in the Forum (USB-IF) for the latest information. USB Speci- device’s data memory space (USB RAM) has been fication Revision 2.0 is the most current specification at supplied to share direct memory access between the the time of publication of this document. microcontroller core and the SIE. Buffer descriptors are also provided, allowing users to freely program end- point memory usage within the USB RAM space. Figure22-1 presents a general overview of the USB peripheral and its features. FIGURE 22-1: USB PERIPHERAL AND OPTIONS PIC18F87J50 Family External 3.3V VUSB Supply Optional P External Pull-ups(1) FSEN P UPUEN Internal Pull-ups (Full (Low UTRDIS Speed) Speed) Transceiver USB Bus USB Clock from the FS D+ Oscillator Module D- USB Control and Configuration USB SIE 3.9Kbyte USB RAM Note 1: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used. © 2009 Microchip Technology Inc. DS39775C-page 311

PIC18F87J50 FAMILY 22.2 USB Status and Control In addition, the USB Control register contains a status bit, SE0 (UCON<5>), which is used to indicate the The operation of the USB module is configured and occurrence of a single-ended zero on the bus. When managed through three control registers. In addition, a the USB module is enabled, this bit should be moni- total of 22 registers are used to manage the actual USB tored to determine whether the differential data lines transactions. The registers are: have come out of a single-ended zero condition. This • USB Control register (UCON) helps to differentiate the initial power-up state from the • USB Configuration register (UCFG) USB Reset signal. • USB Transfer Status register (USTAT) The overall operation of the USB module is controlled • USB Device Address register (UADDR) by the USBEN bit (UCON<3>). Setting this bit activates • Frame Number registers (UFRMH:UFRML) the module and resets all of the PPBI bits in the Buffer • Endpoint Enable registers 0 through 15 (UEPn) Descriptor Table to ‘0’. This bit also activates the inter- nal pull-up resistors, if they are enabled. Thus, this bit 22.2.1 USB CONTROL REGISTER (UCON) can be used as a soft attach/detach to the USB. Although all status and control bits are ignored when The USB Control register (Register22-1) contains bits this bit is clear, the module needs to be fully preconfig- needed to control the module behavior during transfers. ured prior to setting this bit. This bit cannot be set until The register contains bits that control the following: the USB module is supplied with an active clock • Main USB Peripheral Enable source. If the PLL is being used, it should be enabled • Ping-Pong Buffer Pointer Reset at least two milliseconds (enough time for the PLL to • Control of the Suspend mode lock) before attempting to set the USBEN bit. • Packet Transfer Disable REGISTER 22-1: UCON: USB CONTROL REGISTER U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0 — PPBRST SE0 PKTDIS USBEN(1) RESUME SUSPND — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks 0 = Ping-Pong Buffer Pointers not being reset bit 5 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero active on the USB bus 0 = No single-ended zero detected bit 4 PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing disabled, automatically set when a SETUP token is received 0 = SIE token and packet processing enabled bit 3 USBEN: USB Module Enable bit(1) 1 = USB module and supporting circuitry enabled (device attached) 0 = USB module and supporting circuitry disabled (device detached) bit 2 RESUME: Resume Signaling Enable bit 1 = Resume signaling activated 0 = Resume signaling disabled bit 1 SUSPND: Suspend USB bit 1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive 0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate bit 0 Unimplemented: Read as ‘0’ Note 1: This bit cannot be set if the USB module does not have an appropriate clock source. DS39775C-page 312 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY The PPBRST bit (UCON<6>) controls the Reset status The UCFG register also contains two bits which aid in when Double-Buffering mode (ping-pong buffering) is module testing, debugging and USB certifications. used. When the PPBRST bit is set, all Ping-Pong These bits control output enable state monitoring and Buffer Pointers are set to the Even buffers. PPBRST eye pattern generation. has to be cleared by firmware. This bit is ignored in Note: The USB speed, transceiver and pull-up buffering modes not using ping-pong buffering. should only be configured during the mod- The PKTDIS bit (UCON<4>) is a flag indicating that the ule setup phase. It is not recommended to SIE has disabled packet transmission and reception. switch these settings while the module is This bit is set by the SIE when a SETUP token is enabled. received to allow setup processing. This bit cannot be set by the microcontroller, only cleared; clearing it 22.2.2.1 Internal Transceiver allows the SIE to continue transmission and/or The USB peripheral has a built-in, USB 2.0, full-speed reception. Any pending events within the Buffer and low-speed capable transceiver, internally con- Descriptor Table will still be available, indicated within nected to the SIE. This feature is useful for low-cost, the USTAT register’s FIFO buffer. single chip applications. The UTRDIS bit (UCFG<3>) The RESUME bit (UCON<2>) allows the peripheral to controls the transceiver; it is enabled by default perform a remote wake-up by executing Resume (UTRDIS = 0). The FSEN bit (UCFG<2>) controls the signaling. To generate a valid remote wake-up, transceiver speed; setting the bit enables full-speed firmware must set RESUME for 10ms and then clear operation. the bit. For more information on Resume signaling, see The on-chip USB pull-up resistors are controlled by the Sections7.1.7.5, 11.4.4 and 11.9 in the USB 2.0 UPUEN bit (UCFG<4>). They can only be selected specification. when the on-chip transceiver is enabled. The SUSPND bit (UCON<1>) places the module and The internal USB transceiver obtains power from the supporting circuitry in a low-power mode. The input clock to the SIE is also disabled. This bit should be set VUSB pin. In order to meet USB signalling level specifi- by the software in response to an IDLEIF interrupt. It cations, VUSB must be supplied with a voltage source between 3.0V and 3.6V. The best electrical signal qual- should be reset by the microcontroller firmware after an ity is obtained when a 3.3V supply is used and locally ACTVIF interrupt is observed. When this bit is active, bypassed with a high quality ceramic capacitor. The the device remains attached to the bus but the trans- capacitor should be placed as close as possible to the ceiver outputs remain Idle. The voltage on the VUSB pin may vary depending on the value of this bit. Setting this VUSB and VSS pins found on the same edge of the bit before a IDLEIF request will result in unpredictable package (i.e., route ground of the capacitor to VSS pin25 on 64-lead TQFP packaged parts, or pin 31 on bus behavior. 80-lead TQFP parts). Note: While in Suspend mode, a typical VUSB should be held to within +/-300 mV of VDD. For bus-powered USB device is limited to most applications, VUSB and VDD should be connected 500μA of current. This is the complete together and powered from a nominal 3.3V source. current which may be drawn by the PIC When the USB module is not being used, VUSB should device and its supporting circuitry. Care still be connected to VDD, but VUSB/VDD may be should be taken to assure minimum connected to a 2.0V to 3.6V source. current draw when the device enters Suspend mode. The D+ and D- signal lines can be routed directly to their respective pins on the USB connector or cable (for 22.2.2 USB CONFIGURATION REGISTER hard-wired applications). No additional resistors, (UCFG) capacitors, or magnetic components are required as the D+ and D- drivers have controlled slew rate and Prior to communicating over USB, the module’s output impedance intended to match with the associated internal and/or external hardware must be characteristic impedance of the USB cable. configured. Most of the configuration is performed with In order to meet the USB specifications, the traces the UCFG register (Register22-2).The UFCG register should be less than 30cm long. Ideally, these traces contains most of the bits that control the system level should be designed to have a characteristic impedance behavior of the USB module. These include: matching that of the USB cable. • Bus Speed (full speed versus low speed) • On-Chip Pull-up Resistor Enable • On-Chip Transceiver Enable • Ping-Pong Buffer Usage © 2009 Microchip Technology Inc. DS39775C-page 313

PIC18F87J50 FAMILY REGISTER 22-2: UCFG: USB CONFIGURATION REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UTEYE — — UPUEN(1,2) UTRDIS(1) FSEN(1) PPB1 PPB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled bit 6 Unimplemented: Always should be programmed to ‘0’(3) bit 5 Unimplemented: Read as ‘0’ bit 4 UPUEN: USB On-Chip Pull-up Enable bit(1,2) 1 = On-chip pull-up enabled (pull-up on D+ with FSEN=1 or D- with FSEN=0) 0 = On-chip pull-up disabled bit 3 UTRDIS: On-Chip Transceiver Disable bit(1) 1 = On-chip transceiver disabled 0 = On-chip transceiver active bit 2 FSEN: Full-Speed Enable bit(1) 1 = Full-speed device: controls transceiver edge rates; requires input clock at 48MHz 0 = Low-speed device: controls transceiver edge rates; requires input clock at 6MHz bit 1-0 PPB1:PPB0: Ping-Pong Buffers Configuration bits 11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15 10 = Even/Odd ping-pong buffers enabled for all endpoints 01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0 00 = Even/Odd ping-pong buffers disabled Note 1: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These values must be preconfigured prior to enabling the module. 2: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored. 3: Firmware should never set this bit. Doing so may cause unexpected behavior. DS39775C-page 314 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 22.2.2.2 Internal Pull-up Resistors 22.2.2.4 Ping-Pong Buffer Configuration The PIC18F87J10 family devices have built-in pull-up The usage of ping-pong buffers is configured using the resistors designed to meet the requirements for PPB1:PPB0 bits. Refer to Section22.4.4 “Ping-Pong low-speed and full-speed USB. The UPUEN bit Buffering” for a complete explanation of the ping-pong (UCFG<4>) enables the internal pull-ups. Figure22-1 buffers. shows the pull-ups and their control. 22.2.2.5 Eye Pattern Test Enable Note: The official USB specifications require that USB devices must never source any cur- An automatic eye pattern test can be generated by the module when the UCFG<7> bit is set. The eye pattern rent onto the +5V VBUS line of the USB output will be observable based on module settings, cable. Additionally, USB devices must meaning that the user is first responsible for configuring never source any current on the D+ and D- the SIE clock settings, pull-up resistor and Transceiver data lines whenever the +5V VBUS line is mode. In addition, the module has to be enabled. less than 1.17V. In order to meet this requirement, applications which are not Once UTEYE is set, the module emulates a switch from purely bus powered should monitor the a receive to transmit state and will start transmitting a J-K-J-K bit sequence (K-J-K-J for full speed). The VBUS line and avoid turning on the USB sequence will be repeated indefinitely while the Eye module and the D+ or D- pull-up resistor Pattern Test mode is enabled. until VBUS is greater than 1.17V. VBUS can be connected to and monitored by any 5V Note that this bit should never be set while the module tolerant I/O pin for this purpose. is connected to an actual USB system. This Test mode is intended for board verification to aid with USB certi- 22.2.2.3 External Pull-up Resistors fication tests. It is intended to show a system developer the noise integrity of the USB signals which can be External pull-up may also be used. The VUSB pin may be affected by board traces, impedance mismatches and used to pull up D+ or D-. The pull-up resistor must be proximity to other system components. It does not 1.5kΩ (±5%) as required by the USB specifications. properly test the transition from a receive to a transmit Figure22-2 shows an example. state. Although the eye pattern is not meant to replace the more complex USB certification test, it should aid FIGURE 22-2: EXTERNAL CIRCUITRY during first order system debugging. PIC® Host Microcontroller Controller/HUB VUSB 1.5 kΩ D+ D- Note: The above setting shows a typical connection for a full-speed configuration using an on-chip regulator and an external pull-up resistor. © 2009 Microchip Technology Inc. DS39775C-page 315

PIC18F87J50 FAMILY 22.2.3 USB STATUS REGISTER (USTAT) Clearing the transfer complete flag bit, TRNIF, causes the SIE to advance the FIFO. If the next data in the The USB Status register reports the transaction status FIFO holding register is valid, the SIE will reassert the within the SIE. When the SIE issues a USB transfer interrupt within 6 TCY of clearing TRNIF. If no additional complete interrupt, USTAT should be read to determine data is present, TRNIF will remain clear; USTAT data the status of the transfer. USTAT contains the transfer will no longer be reliable. endpoint number, direction and Ping-Pong Buffer Pointer value (if used). Note: If an endpoint request is received while the USTAT FIFO is full, the SIE will Note: The data in the USB Status register is valid automatically issue a NAK back to the only when the TRNIF interrupt flag is host. asserted. The USTAT register is actually a read window into a FIGURE 22-3: USTAT FIFO four-byte status FIFO, maintained by the SIE. It allows the microcontroller to process one transfer while the USTAT from SIE SIE processes additional endpoints (Figure22-3). When the SIE completes using a buffer for reading or writing data, it updates the USTAT register. If another USB transfer is performed before a transaction complete interrupt is serviced, the SIE will store the 4-Byte FIFO ClearingTRNIF status of the next transfer into the status FIFO. for USTAT AdvancesFIFO Data Bus REGISTER 22-3: USTAT: USB STATUS REGISTER U-0 R-x R-x R-x R-x R-x R-x U-0 — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits (represents the number of the BDT updated by the last USB transfer) 1111 = Endpoint 15 1110 = Endpoint 14 .... 0001 = Endpoint 1 0000 = Endpoint 0 bit 2 DIR: Last BD Direction Indicator bit 1 = The last transaction was an IN token 0 = The last transaction was an OUT or SETUP token bit 1 PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the Odd BD bank 0 = The last transaction was to the Even BD bank bit 0 Unimplemented: Read as ‘0’ Note 1: This bit is only valid for endpoints with available Even and Odd BD registers. DS39775C-page 316 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 22.2.4 USB ENDPOINT CONTROL transactions. For Endpoint 0, this bit should always be cleared since the USB specifications identify Each of the 16 possible bidirectional endpoints has its Endpoint0 as the default control endpoint. own independent control register, UEPn (where ‘n’ rep- resents the endpoint number). Each register has an The EPOUTEN bit (UEPn<2>) is used to enable or dis- identical complement of control bits. The prototype is able USB OUT transactions from the host. Setting this shown in Register22-4. bit enables OUT transactions. Similarly, the EPINEN bit (UEPn<1>) enables or disables USB IN transactions The EPHSHK bit (UEPn<4>) controls handshaking for from the host. the endpoint; setting this bit enables USB handshaking. Typically, this bit is always set except when using The EPSTALL bit (UEPn<0>) is used to indicate a isochronous endpoints. STALL condition for the endpoint. If a STALL is issued on a particular endpoint, the EPSTALL bit for that end- The EPCONDIS bit (UEPn<3>) is used to enable or point pair will be set by the SIE. This bit remains set disable USB control operations (SETUP) through the until it is cleared through firmware, or until the SIE is endpoint. Clearing this bit enables SETUP transac- reset. tions. Note that the corresponding EPINEN and EPOUTEN bits must be set to enable IN and OUT REGISTER 22-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake enabled 0 = Endpoint handshake disabled (typically used for isochronous endpoints) bit 3 EPCONDIS: Bidirectional Endpoint Control bit If EPOUTEN = 1 and EPINEN = 1: 1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed 0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed bit 2 EPOUTEN: Endpoint Output Enable bit 1 = Endpoint n output enabled 0 = Endpoint n output disabled bit 1 EPINEN: Endpoint Input Enable bit 1 = Endpoint n input enabled 0 = Endpoint n input disabled bit 0 EPSTALL: Endpoint Stall Enable bit(1) 1 = Endpoint n is stalled 0 = Endpoint n is not stalled Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored. © 2009 Microchip Technology Inc. DS39775C-page 317

PIC18F87J50 FAMILY 22.2.5 USB ADDRESS REGISTER FIGURE 22-4: IMPLEMENTATION OF (UADDR) USB RAM IN DATA MEMORY SPACE The USB Address register contains the unique USB address that the peripheral will decode when active. UADDR is reset to 00h when a USB Reset is received, 000h Access Ram indicated by URSTIF, or when a Reset is received from 05Fh the microcontroller. The USB address must be written 060h by the microcontroller during the USB setup phase USB Data or User Data (enumeration) as part of the Microchip USB firmware support. 3FFh Buffer Descriptors, 400h 22.2.6 USB FRAME NUMBER REGISTERS (UFRMH:UFRML) USB Data or User Data 4FFh 500h The Frame Number registers contain the 11-bit frame number. The low-order byte is contained in UFRML, while the three high-order bits are contained in UFRMH. The register pair is updated with the current frame number whenever a SOF token is received. For Banks 0 the microcontroller, these registers are read-only. The to 15 Frame Number registers are primarily used for (USB RAM) USB Data or isochronous transfers. The contents of the UFRMH and User Data UFRML registers are only valid when the 48 MHz SIE clock is active (i.e., contents are inaccurate when SUSPND (UCON<1>) bit = 1). 22.3 USB RAM USB data moves between the microcontroller core and the SIE through a memory space known as the USB RAM. This is a special dual access memory that is F00h mapped into the normal data memory space in Banks 0 through 15 (60h to F3Fh) for a total of 3.9 Kbyte F3Fh (Figure22-4). F40h Bank 4 (400h through 4FFh) is used specifically for SFRs F5Fh endpoint buffer control, while Banks 0 through Bank3 F60h and Banks 5 through Bank15 are available for USB FFFh data. Depending on the type of buffering being used, all but 8 bytes of Bank 4 may also be available for use as USB buffer space. Although USB RAM is available to the microcontroller as data memory, the sections that are being accessed by the SIE should not be accessed by the microcontroller. A semaphore mechanism is used to determine the access to a particular buffer at any given time. This is discussed in Section22.4.1.1 “Buffer Ownership”. DS39775C-page 318 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 22.4 Buffer Descriptors and the Buffer FIGURE 22-5: EXAMPLE OF A BUFFER Descriptor Table DESCRIPTOR Address Registers Contents The registers in Bank 4 are used specifically for end- point buffer control in a structure known as the Buffer 400h BD0STAT (xxh) Descriptor Table (BDT). This provides a flexible method Buffer 401h BD0CNT 40h Size of Block for users to construct and control endpoint buffers of Descriptor 402h BD0ADRL 00h various lengths and configuration. Starting 403h BD0ADRH 05h Address The BDT is composed of Buffer Descriptors (BD) which are used to define and control the actual buffers in the 500h USB RAM space. Each BD, in turn, consists of four reg- isters, where n represents one of the 64 possible BDs (range of 0 to 63): Buffer USB Data • BDnSTAT: BD Status register • BDnCNT: BD Byte Count register 53Fh • BDnADRL: BD Address Low register Note: Memory regions not to scale. • BDnADRH: BD Address High register BDs always occur as a four-byte block in the sequence, Unlike other control registers, the bit configuration for BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address the BDnSTAT register is context sensitive. There are of BDnSTAT is always an offset of (4n – 1) (in hexa- two distinct configurations, depending on whether the decimal) from 400h, with n being the buffer descriptor microcontroller or the USB module is modifying the BD number. and buffer at a particular time. Only three bit definitions Depending on the buffering configuration used are shared between the two. (Section22.4.4 “Ping-Pong Buffering”), there are up 22.4.1.1 Buffer Ownership to 32, 33 or 64 sets of buffer descriptors. At a minimum, the BDT must be at least 8 bytes long. This is because Because the buffers and their BDs are shared between the USB specification mandates that every device must the CPU and the USB module, a simple semaphore have Endpoint 0 with both input and output for initial mechanism is used to distinguish which is allowed to setup. Depending on the endpoint and buffering update the BD and associated buffers in memory. configuration, the BDT can be as long as 256 bytes. This is done by using the UOWN bit (BDnSTAT<7>) as Although they can be thought of as Special Function a semaphore to distinguish which is allowed to update Registers, the Buffer Descriptor Status and Address the BD and associated buffers in memory. UOWN is the registers are not hardware mapped, as conventional only bit that is shared between the two configurations microcontroller SFRs in Bank 15 are. If the endpoint cor- of BDnSTAT. responding to a particular BD is not enabled, its registers When UOWN is clear, the BD entry is “owned” by the are not used. Instead of appearing as unimplemented microcontroller core. When the UOWN bit is set, the BD addresses, however, they appear as available RAM. entry and the buffer memory are “owned” by the USB Only when an endpoint is enabled by setting the peripheral. The core should not modify the BD or its UEPn<1> bit does the memory at those addresses corresponding data buffer during this time. Note that become functional as BD registers. As with any address the microcontroller core can still read BDnSTAT while in the data memory space, the BD registers have an the SIE owns the buffer and vice versa. indeterminate value on any device Reset. The buffer descriptors have a different meaning based An example of a BD for a 64-byte buffer, starting at on the source of the register update. Prior to placing 500h, is shown in Figure22-5. A particular set of BD ownership with the USB peripheral, the user can con- registers is only valid if the corresponding endpoint has figure the basic operation of the peripheral through the been enabled using the UEPn register. All BD registers BDnSTAT bits. During this time, the byte count and are available in USB RAM. The BD for each endpoint buffer location registers can also be set. should be set up prior to enabling the endpoint. When UOWN is set, the user can no longer depend on 22.4.1 BD STATUS AND CONFIGURATION the values that were written to the BDs. From this point, the SIE updates the BDs as necessary, overwriting the Buffer descriptors not only define the size of an end- original BD values. The BDnSTAT register is updated point buffer, but also determine its configuration and by the SIE with the token PID and the transfer count, control. Most of the configuration is done with the BD BDnCNT, is updated. Status register, BDnSTAT. Each BD has its own unique and correspondingly numbered BDnSTAT register. © 2009 Microchip Technology Inc. DS39775C-page 319

PIC18F87J50 FAMILY The BDnSTAT byte of the BDT should always be the The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides last byte updated when preparing to arm an endpoint. support for control transfers, usually one-time stalls on The SIE will clear the UOWN bit when a transaction Endpoint 0. It also provides support for the has completed. SET_FEATURE/CLEAR_FEATURE commands speci- fied in Chapter 9 of the USB specification; typically, No hardware mechanism exists to block access when continuous STALLs to any endpoint other than the the UOWN bit is set. Thus, unexpected behavior can default control endpoint. occur if the microcontroller attempts to modify memory when the SIE owns it. Similarly, reading such memory The BSTALL bit enables buffer stalls. Setting BSTALL may produce inaccurate data until the USB peripheral causes the SIE to return a STALL token to the host if a returns ownership to the microcontroller. received token would use the BD in that location. The EPSTALL bit in the corresponding UEPn control regis- 22.4.1.2 BDnSTAT Register (CPU Mode) ter is set and a STALL interrupt is generated when a When UOWN = 0, the microcontroller core owns the STALL is issued to the host. The UOWN bit remains set BD. At this point, the other seven bits of the register and the BDs are not changed unless a SETUP token is take on control functions. received. In this case, the STALL condition is cleared and the ownership of the BD is returned to the The Data Toggle Sync Enable bit, DTSEN microcontroller core. (BDnSTAT<3>), controls data toggle parity checking. Setting DTSEN enables data toggle synchronization by The BD9:BD8 bits (BDnSTAT<1:0>) store the two most significant digits of the SIE byte count; the lower 8 digits the SIE. When enabled, it checks the data packet’s par- are stored in the corresponding BDnCNT register. See ity against the value of DTS (BDnSTAT<6>). If a packet Section22.4.2 “BD Byte Count” for more arrives with an incorrect synchronization, the data will information. essentially be ignored. It will not be written to the USB RAM and the USB transfer complete interrupt flag will not be set. The SIE will send an ACK token back to the host to Acknowledge receipt, however. The effects of the DTSEN bit on the SIE are summarized in Table22-1. TABLE 22-1: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION BDnSTAT Settings Device Response after Receiving Packet OUT Packet from Host DTSEN DTS Handshake UOWN TRNIF BDnSTAT and USTAT Status DATA0 1 0 ACK 0 1 Updated DATA1 1 0 ACK 1 0 Not Updated DATA0 1 1 ACK 1 0 Not Updated DATA1 1 1 ACK 0 1 Updated Either 0 x ACK 0 1 Updated Either, with error x x NAK 1 0 Not Updated Legend: x = don’t care DS39775C-page 320 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 22-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE) R/W-x R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x UOWN(1) DTS(2) —(3) —(3) DTSEN BSTALL BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit(1) 0 = The microcontroller core owns the BD and its corresponding buffer bit 6 DTS: Data Toggle Synchronization bit(2) 1 = Data 1 packet 0 = Data 0 packet bit 5-4 Unimplemented: These bits should always be programmed to ‘0’(3). bit 3 DTSEN: Data Toggle Synchronization Enable bit 1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored except for a SETUP transaction, which is accepted even if the data toggle bits do not match 0 = No data toggle synchronization is performed bit 2 BSTALL: Buffer Stall Enable bit 1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the given location (UOWN bit remains set, BD value is unchanged) 0 = Buffer stall disabled bit 1-0 BC9:BC8: Byte Count 9 and 8 bits The byte count bits represent the number of bytes that will be transmitted for an IN token or received during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023. Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module. 2: This bit is ignored unless DTSEN=1. 3: If these bits are set, USB communication may not work. Hence, these bits should always be maintained as ‘0’. © 2009 Microchip Technology Inc. DS39775C-page 321

PIC18F87J50 FAMILY 22.4.1.3 BDnSTAT Register (SIE Mode) The 10-bit byte count is distributed over two registers. The lower 8 bits of the count reside in the BDnCNT When the BD and its buffer are owned by the SIE, most register. The upper two bits reside in BDnSTAT<1:0>. of the bits in BDnSTAT take on a different meaning. The This represents a valid byte range of 0 to 1023. configuration is shown in Register22-6. Once UOWN is set, any data or control settings previously written 22.4.3 BD ADDRESS VALIDATION there by the user will be overwritten with data from the SIE. The BD Address register pair contains the starting RAM address location for the corresponding endpoint buffer. The BDnSTAT register is updated by the SIE with the No mechanism is available in hardware to validate the token Packet Identifier (PID) which is stored in BD address. BDnSTAT<5:3>. The transfer count in the correspond- ing BDnCNT register is updated. Values that overflow If the value of the BD address does not point to an the 8-bit register carry over to the two most significant address in the USB RAM, or if it points to an address digits of the count, stored in BDnSTAT<1:0>. within another endpoint’s buffer, data is likely to be lost or overwritten. Similarly, overlapping a receive buffer 22.4.2 BD BYTE COUNT (OUT endpoint) with a BD location in use can yield unexpected results. When developing USB The byte count represents the total number of bytes applications, the user may want to consider the that will be transmitted during an IN transfer. After an IN inclusion of software-based address validation in their transfer, the SIE will return the number of bytes sent to code. the host. For an OUT transfer, the byte count represents the maximum number of bytes that can be received and stored in USB RAM. After an OUT transfer, the SIE will return the actual number of bytes received. If the number of bytes received exceeds the corresponding byte count, the data packet will be rejected and a NAK handshake will be generated. When this happens, the byte count will not be updated. REGISTER 22-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE MCU) R/W-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x UOWN — PID3 PID2 PID1 PID0 BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit 1 = The SIE owns the BD and its corresponding buffer bit 6 Reserved: Not written by the SIE bit 5-2 PID3:PID0: Packet Identifier bits The received token PID value of the last transfer (IN, OUT or SETUP transactions only). bit 1-0 BC9:BC8: Byte Count 9 and 8 bits These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer and the actual number of bytes transmitted on an IN transfer. DS39775C-page 322 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 22.4.4 PING-PONG BUFFERING the completion of a transaction (UOWN cleared by the SIE), the pointer is toggled to the Odd BD. After the An endpoint is defined to have a ping-pong buffer when completion of the next transaction, the pointer is it has two sets of BD entries: one set for an Even toggled back to the Even BD and so on. transfer and one set for an Odd transfer. This allows the CPU to process one BD while the SIE is processing the The Even/Odd status of the last transaction is stored in other BD. Double-buffering BDs in this way allows for the PPBI bit of the USTAT register. The user can reset maximum throughput to/from the USB. all Ping-Pong Pointers to Even using the PPBRST bit. The USB module supports four modes of operation: Figure22-6 shows the four different modes of operation and how USB RAM is filled with the BDs. • No ping-pong support • Ping-pong buffer support for OUT Endpoint 0 only BDs have a fixed relationship to a particular endpoint, depending on the buffering configuration. The mapping • Ping-pong buffer support for all endpoints of BDs to endpoints is detailed in Table22-2. This • Ping-pong buffer support for all other Endpoints relationship also means that gaps may occur in the except Endpoint 0 BDT if endpoints are not enabled contiguously. This The ping-pong buffer settings are configured using the theoretically means that the BDs for disabled endpoints PPB1:PPB0 bits in the UCFG register. could be used as buffer space. In practice, users should avoid using such spaces in the BDT unless a The USB module keeps track of the Ping-Pong Pointer method of validating BD addresses is implemented. individually for each endpoint. All pointers are initially reset to the Even BD when the module is enabled. After FIGURE 22-6: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES PPB1:PPB0=00 PPB1:PPB0=01 PPB1:PPB0=10 PPB1:PPB0=11 No Ping-Pong Ping-Pong Buffer Ping-Pong Buffers Ping-Pong Buffers Buffers on EP0 OUT on all EPs on all other EPs except EP0 400h 400h 400h 400h EP0 OUT EP0 OUT Even EP0 OUT Even EP0 OUT Descriptor Descriptor Descriptor Descriptor EP0 IN EP0 OUT Odd EP0 OUT Odd EP0 IN Descriptor Descriptor Descriptor Descriptor EP1 OUT EP0 IN Even EP1 OUT Even Descriptor EP0 IN Descriptor Descriptor Descriptor EP1 IN EP0 IN Odd EP1 OUT Odd Descriptor EP1 OUT Descriptor Descriptor Descriptor EP1 OUT Even EP1 IN Even EP1 IN Descriptor Descriptor Descriptor EP1 OUT Odd EP1 IN Odd EP15 IN Descriptor Descriptor Descriptor 47Fh EP1 IN Even EP15 IN Descriptor 483h Descriptor EP1 IN Odd Descriptor Available as Available Data RAM as EP15 IN Odd Data RAM Descriptor 4F7h Available as Data RAM EP15 IN Odd Descriptor 4FFh 4FFh 4FFh 4FFh Maximum Memory Maximum Memory Maximum Memory Maximum Memory Used: 128 bytes Used: 132 bytes Used: 256 bytes Used: 248 bytes Maximum BDs: Maximum BDs: Maximum BDs: 6 Maximum BDs: 32 (BD0 to BD31) 33 (BD0 to BD32) 4 (BD0 to BD63) 62 (BD0 to BD61) Note: Memory area not shown to scale. © 2009 Microchip Technology Inc. DS39775C-page 323

PIC18F87J50 FAMILY TABLE 22-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Mode 3 Mode 0 Mode 1 Mode 2 Endpoint (Ping-Pong on all other EPs, (No Ping-Pong) (Ping-Pong on EP0 OUT) (Ping-Pong on all EPs) except EP0) Out In Out In Out In Out In 0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1 1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O) 2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O) 3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O) 4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O) 5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O) 6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O) 7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O) 8 16 17 17 18 32 (E), 33 (O) 34 (E), 35 (O) 30 (E), 31 (O) 32 (E), 33 (O) 9 18 19 19 20 36 (E), 37 (O) 38 (E), 39 (O) 34 (E), 35 (O) 36 (E), 37 (O) 10 20 21 21 22 40 (E), 41 (O) 42 (E), 43 (O) 38 (E), 39 (O) 40 (E), 41 (O) 11 22 23 23 24 44 (E), 45 (O) 46 (E), 47 (O) 42 (E), 43 (O) 44 (E), 45 (O) 12 24 25 25 26 48 (E), 49 (O) 50 (E), 51 (O) 46 (E), 47 (O) 48 (E), 49 (O) 13 26 27 27 28 52 (E), 53 (O) 54 (E), 55 (O) 50 (E), 51 (O) 52 (E), 53 (O) 14 28 29 29 30 56 (E), 57 (O) 58 (E), 59 (O) 54 (E), 55 (O) 56 (E), 57 (O) 15 30 31 31 32 60 (E), 61 (O) 62 (E), 63 (O) 58 (E), 59 (O) 60 (E), 61 (O) Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer TABLE 22-3: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BDnSTAT(1) UOWN DTS(4) PID3(2) PID2(2) PID1(2) PID0(2) BC9 BC8 DTSEN(3) BSTALL(3) BDnCNT(1) Byte Count BDnADRL(1) Buffer Address Low BDnADRH(1) Buffer Address High Note 1: For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx). 2: Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values written for DTSEN and BSTALL are no longer valid. 3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the BDnSTAT register are used to configure the DTSEN and BSTALL settings. 4: This bit is ignored unless DTSEN = 1. DS39775C-page 324 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 22.5 USB Interrupts Figure22-7 shows the interrupt logic for the USB module. There are two layers of interrupt registers in The USB module can generate multiple interrupt con- the USB module. The top level consists of overall USB ditions. To accommodate all of these interrupt sources, status interrupts; these are enabled and flagged in the the module is provided with its own interrupt logic UIE and UIR registers, respectively. The second level structure, similar to that of the microcontroller. USB consists of USB error conditions, which are enabled interrupts are enabled with one set of control registers and flagged in the UEIR and UEIE registers. An and trapped with a separate set of flag registers. All interrupt condition in any of these triggers a USB Error sources are funneled into a single USB interrupt Interrupt Flag (UERRIF) in the top level. request, USBIF (PIR2<4>), in the microcontroller’s Interrupts may be used to trap routine events in a USB interrupt logic. transaction. Figure22-8 shows some common events within a USB frame and their corresponding interrupts. FIGURE 22-7: USB INTERRUPT LOGIC FUNNEL Second Level USB Interrupts Top Level USB Interrupts (USB Error Conditions) (USB Status Interrupts) UEIR (Flag) and UEIE (Enable) Registers UIR (Flag) and UIE (Enable) Registers SOFIF SOFIE BTSEF BTSEE TRNIF USBIF TRNIE BTOEF BTOEE IDLEIF DFN8EF IDLEIE DFN8EE UERRIF CRC16EF UERRIE CRC16EE STALLIF CRC5EF STALLIE CRC5EE PIDEF PIDEE ACTVIF ACTVIE URSTIF URSTIE FIGURE 22-8: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS From Host From Host To Host SETUPToken Data ACK Set TRNIF From Host To Host From Host USB Reset IN Token Data ACK Set TRNIF URSTIF From Host From Host To Host Start-of-Frame (SOF) OUT Token Empty Data ACK Set TRNIF SOFIF Transaction Transaction Complete RESET SOF SETUP DATA STATUS SOF Differential Data Control Transfer(1) 1ms Frame Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames. © 2009 Microchip Technology Inc. DS39775C-page 325

PIC18F87J50 FAMILY 22.5.1 USB INTERRUPT STATUS Once an interrupt bit has been set by the SIE, it must REGISTER (UIR) be cleared by software by writing a ‘0’. The flag bits can also be set in software which can aid in firmware The USB Interrupt Status register (Register22-7) con- debugging. tains the flag bits for each of the USB status interrupt sources. Each of these sources has a corresponding interrupt enable bit in the UIE register. All of the USB status flags are ORed together to generate the USBIF interrupt flag for the microcontroller’s interrupt funnel. REGISTER 22-7: UIR: USB INTERRUPT STATUS REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 — SOFIF STALLIF IDLEIF(1) TRNIF(2) ACTVIF(3) UERRIF(4) URSTIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOFIF: Start-of-Frame Token Interrupt bit 1 = A Start-of-Frame token received by the SIE 0 = No Start-of-Frame token received by the SIE bit 5 STALLIF: A STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the SIE 0 = A STALL handshake has not been sent bit 4 IDLEIF: Idle Detect Interrupt bit(1) 1 = Idle condition detected (constant Idle state of 3ms or more) 0 = No Idle condition detected bit 3 TRNIF: Transaction Complete Interrupt bit(2) 1 = Processing of pending transaction is complete; read USTAT register for endpoint information 0 = Processing of pending transaction is not complete or no transaction is pending bit 2 ACTVIF: Bus Activity Detect Interrupt bit(3) 1 = Activity on the D+/D- lines was detected 0 = No activity detected on the D+/D- lines bit 1 UERRIF: USB Error Condition Interrupt bit(4) 1 = An unmasked error condition has occurred 0 = No unmasked error condition has occurred. bit 0 URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset occurred; 00h is loaded into UADDR register 0 = No USB Reset has occurred Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode. 2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens). 3: This bit is typically unmasked only following the detection of a UIDLE interrupt event. 4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and cannot be set or cleared by the user. DS39775C-page 326 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 22.5.1.1 Bus Activity Detect Interrupt Bit clearing the SUSPND bit, the USB module may not be (ACTVIF) immediately operational while waiting for the 96 MHz PLL to lock. The application code should clear the The ACTVIF bit cannot be cleared immediately after ACTVIF flag as shown in Example22-1. the USB module wakes up from Suspend or while the USB module is suspended. A few clock cycles are Only one ACTVIF interrupt is generated when resum- required to synchronize the internal hardware state ing from the USB bus Idle condition. If user firmware machine before the ACTVIF bit can be cleared by clears the ACTVIF bit, the bit will not immediately firmware. Clearing the ACTVIF bit before the internal become set again, even when there is continuous bus hardware is synchronized may not have an effect on traffic. Bus traffic must cease long enough to generate the value of ACTVIF. Additionally, if the USB module another IDLEIF condition before another ACTVIF uses the clock from the 96 MHz PLL source, then after interrupt can be generated. EXAMPLE 22-1: CLEARING ACTVIF BIT (UIR<2>) Assembly: BCF UCON, SUSPND LOOP: BTFSS UIR, ACTVIF BRA DONE BCF UIR, ACTVIF BRA LOOP DONE: C: UCONbits.SUSPND = 0; while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; } © 2009 Microchip Technology Inc. DS39775C-page 327

PIC18F87J50 FAMILY 22.5.2 USB INTERRUPT ENABLE The values in this register only affect the propagation REGISTER (UIE) of an interrupt condition to the microcontroller’s inter- rupt logic. The flag bits are still set by their interrupt The USB Interrupt Enable register (Register22-8) conditions, allowing them to be polled and serviced contains the enable bits for the USB status interrupt without actually generating an interrupt. sources. Setting any of these bits will enable the respective interrupt source in the UIR register. REGISTER 22-8: UIE: USB INTERRUPT ENABLE REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOFIE: Start-of-Frame Token Interrupt Enable bit 1 = Start-of-Frame token interrupt enabled 0 = Start-of-Frame token interrupt disabled bit 5 STALLIE: STALL Handshake Interrupt Enable bit 1 = STALL interrupt enabled 0 = STALL interrupt disabled bit 4 IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle detect interrupt enabled 0 = Idle detect interrupt disabled bit 3 TRNIE: Transaction Complete Interrupt Enable bit 1 = Transaction interrupt enabled 0 = Transaction interrupt disabled bit 2 ACTVIE: Bus Activity Detect Interrupt Enable bit 1 = Bus activity detect interrupt enabled 0 = Bus activity detect interrupt disabled bit 1 UERRIE: USB Error Interrupt Enable bit 1 = USB error interrupt enabled 0 = USB error interrupt disabled bit 0 URSTIE: USB Reset Interrupt Enable bit 1 = USB Reset interrupt enabled 0 = USB Reset interrupt disabled DS39775C-page 328 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 22.5.3 USB ERROR INTERRUPT STATUS Each error bit is set as soon as the error condition is REGISTER (UEIR) detected. Thus, the interrupt will typically not correspond with the end of a token being processed. The USB Error Interrupt Status register (Register22-9) contains the flag bits for each of the error sources Once an interrupt bit has been set by the SIE, it must within the USB peripheral. Each of these sources is be cleared by software by writing a ‘0’. controlled by a corresponding interrupt enable bit in the UEIE register. All of the USB error flags are ORed together to generate the USB Error Interrupt Flag (UERRIF) at the top level of the interrupt logic. REGISTER 22-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BTSEF: Bit Stuff Error Flag bit 1 = A bit stuff error has been detected 0 = No bit stuff error bit 6-5 Unimplemented: Read as ‘0’ bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed) 0 = No bus turnaround time-out bit 3 DFN8EF: Data Field Size Error Flag bit 1 = The data field was not an integral number of bytes 0 = The data field was an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = The CRC16 failed 0 = The CRC16 passed bit 1 CRC5EF: CRC5 Host Error Flag bit 1 = The token packet was rejected due to a CRC5 error 0 = The token packet was accepted bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed © 2009 Microchip Technology Inc. DS39775C-page 329

PIC18F87J50 FAMILY 22.5.4 USB ERROR INTERRUPT ENABLE As with the UIE register, the enable bits only affect the REGISTER (UEIE) propagation of an interrupt condition to the micro- controller’s interrupt logic. The flag bits are still set by The USB Error Interrupt Enable register their interrupt conditions, allowing them to be polled (Register22-10) contains the enable bits for each of and serviced without actually generating an interrupt. the USB error interrupt sources. Setting any of these bits will enable the respective error interrupt source in the UEIR register to propagate into the UERR bit at the top level of the interrupt logic. REGISTER 22-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Bit stuff error interrupt enabled 0 = Bit stuff error interrupt disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Bus turnaround time-out error interrupt enabled 0 = Bus turnaround time-out error interrupt disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Data field size error interrupt enabled 0 = Data field size error interrupt disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16 failure interrupt enabled 0 = CRC16 failure interrupt disabled bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = CRC5 host error interrupt enabled 0 = CRC5 host error interrupt disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = PID check failure interrupt enabled 0 = PID check failure interrupt disabled DS39775C-page 330 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 22.6 USB Power Modes 22.6.2 SELF-POWER ONLY Many USB applications will likely have several different In Self-Power Only mode, the USB application provides sets of power requirements and configuration. The its own power, with very little power being pulled from most common power modes encountered are Bus the USB. Figure22-10 shows an example. Note that an Power Only, Self-Power Only and Dual Power with attach indication is added to indicate when the USB Self-Power Dominance. The most common cases are has been connected and the host is actively powering presented here. Also provided is a means of estimating VBUS. the current consumption of the USB transceiver. In order to meet compliance specifications, the USB module (and the D+ or D- pull-up resistor) should not 22.6.1 BUS POWER ONLY be enabled until the host actively drives VBUS high. One In Bus Power Only mode, all power for the application of the 5.5V tolerant I/O pins may be used for this is drawn from the USB (Figure22-9). This is effectively purpose. the simplest power method for the device. The application should never source any current onto In order to meet the inrush current requirements of the the 5V VBUS pin of the USB cable. USB 2.0 specifications, the total effective capacitance appearing across VBUS and ground must be no more FIGURE 22-10: SELF-POWER ONLY than 10µF. If not, some kind of inrush liming is Attach Sense required. For more details, see section 7.2.4 of the VBUS 5.5VTolerant USB 2.0 specification. ~5V I/O pin 100kΩ According to the USB 2.0 specification, all USB devices VSELF VDD must also support a Low-Power Suspend mode. In the ~3.3V USB Suspend mode, devices must consume no more than 500μA (or 2.5mA for high powered devices that 100kΩ VUSB are remote wake-up capable) from the 5V VBUS line of the USB cable. VSS The host signals the USB device to enter the Suspend mode by stopping all USB traffic to that device for more than 3ms. This condition will cause the IDLEIF bit in the UIR register to become set. During the USB Suspend mode, the D+ or D- pull-up resistor must remain active, which will consume some of the allowed suspend current: 500μA/2.5mA budget. FIGURE 22-9: BUS POWER ONLY Low IQ Regulator 3.3V V~B5UVS VDD VUSB VSS © 2009 Microchip Technology Inc. DS39775C-page 331

PIC18F87J50 FAMILY 22.6.3 DUAL POWER WITH SELF-POWER 22.6.4 USB TRANSCEIVER CURRENT DOMINANCE CONSUMPTION Some applications may require a dual power option. The USB transceiver consumes a variable amount of This allows the application to use internal power prima- current depending on the characteristic impedance of rily, but switch to power from the USB when no internal the USB cable, the length of the cable, the VUSB supply power is available. Figure22-11 shows a simple Dual voltage and the actual data patterns moving across the Power with Self-Power Dominance mode example, USB cable. Longer cables have larger capacitances which automatically switches between Self-Power Only and consume more total energy when switching output and USB Bus Power Only modes. states. Dual power devices must also meet all of the special Data patterns that consist of “IN” traffic consume far requirements for inrush current and Suspend mode more current than “OUT” traffic. IN traffic requires the current and must not enable the USB module until PIC® device to drive the USB cable, whereas OUT VBUS is driven high. See Section22.6.1 “Bus Power traffic requires that the host drive the USB cable. Only” and Section22.6.2 “Self-Power Only” for The data that is sent across the USB cable is NRZI descriptions of those requirements. Additionally, dual encoded. In the NRZI encoding scheme, ‘0’ bits cause power devices must never source current onto the 5V a toggling of the output state of the transceiver (either VBUS pin of the USB cable. from a “J” state to a “K” state, or vise versa). With the exception of the effects of bit-stuffing, NRZI encoded ‘1’ FIGURE 22-11: DUAL POWER EXAMPLE bits do not cause the output state of the transceiver to change. Therefore, IN traffic consisting of data bits of 100kΩ Attach Sense value, ‘0’, cause the most current consumption, as the Low IQ I/O pin transceiver must charge/discharge the USB cable in Regulator 3.3V order to change states. VBUS VDD ~5V More details about NRZI encoding and bit-stuffing can be found in the USB 2.0 specification’s section 7.1, 100kΩ VUSB although knowledge of such details is not required to make USB applications using the PIC18F87J10 family VSELF VSS of microcontrollers. Among other things, the SIE han- ~3.3V dles bit-stuffing/unstuffing, NRZI encoding/decoding and CRC generation/checking in hardware. The total transceiver current consumption will be application-specific. However, to help estimate how much current actually may be required in full-speed Note: Users should keep in mind the limits for applications, Equation22-1 can be used. devices drawing power from the USB. Example 22-2 shows how this equation can be used for According to USB Specification 2.0, this a theoretical application. cannot exceed 100mA per low-power device or 500mA per high-power device. DS39775C-page 332 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY EQUATION 22-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION (60 mA • VUSB • PZERO • PIN • LCABLE) IXCVR = + IPULLUP (3.3V • 5m) Legend: VUSB – Voltage applied to the VUSB pin in volts. (Should be 3.0V to 3.6V.) PZERO – Percentage (in decimal) of the IN traffic bits sent by the PIC® device that are a value of ‘0’. PIN – Percentage (in decimal) of total bus bandwidth that is used for IN traffic. LCABLE – Length (in meters) of the USB cable. The USB 2.0 specification requires that full-speed applications use cables no longer than 5m. IPULLUP – Current which the nominal, 1.5 kΩ pull-up resistor (when enabled) must supply to the USB cable. On the host or hub end of the USB cable, 15 kΩ nominal resistors (14.25kΩ to 24.8kΩ) are present which pull both the D+ and D- lines to ground. During bus Idle conditions (such as between packets or during USB Suspend mode), this results in up to 218μA of quiescent current drawn at 3.3V. IPULLUP is also dependant on bus traffic conditions and can be as high as 2.2mA when the USB bandwidth is fully utilized (either IN or OUT traffic) for data that drives the lines to the “K” state most of the time. EXAMPLE 22-2: CALCULATING USB TRANSCEIVER CURRENT† For this example, the following assumptions are made about the application: • 3.3V will be applied to VUSB and VDD, with the core voltage regulator enabled. • This is a full-speed application that uses one interrupt IN endpoint that can send one packet of 64bytes every 1ms, with no restrictions on the values of the bytes being sent. The application may or may not have additional traffic on OUT endpoints. • A regular USB “B” or “mini-B” connector will be used on the application circuit board. In this case, PZERO = 100% = 1, because there should be no restriction on the value of the data moving through the IN endpoint. All 64kBps of data could potentially be bytes of value, 00h. Since ‘0’ bits cause toggling of the output state of the transceiver, they cause the USB transceiver to consume extra current charging/discharging the cable. In this case, 100% of the data bits sent can be of value ‘0’. This should be considered the “max” value, as normal data will consist of a fair mix of ones and zeros. This application uses 64kBps for IN traffic out of the total bus bandwidth of 1.5MBps (12Mbps), therefore: 64 kBps Pin = = 4.3% = 0.043 1.5 MBps Since a regular “B” or “mini-B” connector is used in this application, the end user may plug in any type of cable up to the maximum allowed 5m length. Therefore, we use the worst-case length: LCABLE = 5 meters Assume IPULLUP = 2.2mA. The actual value of IPULLUP will likely be closer to 218μA, but allow for the worst-case. USB bandwidth is shared between all the devices which are plugged into the root port (via hubs). If the application is plugged into a USB 1.1 hub that has other devices plugged into it, your device may see host to device traffic on the bus, even if it is not addressed to your device. Since any traffic, regardless of source, can increase the IPULLUP current above the base 218μA, it is safest to allow for the worst case of 2.2mA. Therefore: (60 mA • 3.3V • 1 • 0.043 • 5m) IXCVR = + 2.2 mA = 4.8 mA (3.3V • 5m) † The calculated value should be considered an approximation and additional guardband or applica- tion-specific product testing is recommended. The transceiver current is “in addition to” the rest of the current consumed by the PIC18F87J10 family device that is needed to run the core, drive the other I/O lines, power the various modules, etc. © 2009 Microchip Technology Inc. DS39775C-page 333

PIC18F87J50 FAMILY 22.7 Oscillator 22.8 USB Firmware and Drivers The USB module has specific clock requirements. For Microchip provides a number of application-specific full-speed operation, the clock source must be 48MHz. resources, such as USB firmware and driver support. Even so, the microcontroller core and other peripherals Refer to www.microchip.com for the latest firmware and are not required to run at that clock speed. Available driver support. clocking options are described in detail in Section2.3 “Oscillator Settings for USB”. TABLE 22-4: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1) Details on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 81 IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP 85 PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 85 PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE 85 UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 87 UCFG UTEYE — — UPUEN UTRDIS FSEN PPB1 PPB0 87 USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — 87 UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 87 UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 87 UFRMH — — — — — FRM10 FRM9 FRM8 87 UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 87 UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 87 UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 87 UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 87 UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 88 UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 88 UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 88 UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 88 UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 88 UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 88 UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 88 UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 88 UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 87 UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 87 UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 87 UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 87 UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 87 UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 87 UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 87 UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 87 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module. Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table22-3. DS39775C-page 334 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 22.9 Overview of USB 22.9.3 TRANSFERS This section presents some of the basic USB concepts There are four transfer types defined in the USB and useful information necessary to design a USB specification. device. Although much information is provided in this • Isochronous: This type provides a transfer section, there is a plethora of information provided method for large amounts of data (up to within the USB specifications and class specifications. 1023bytes) with timely delivery ensured; Thus, the reader is encouraged to refer to the USB however, the data integrity is not ensured. This is specifications for more information (www.usb.org). If good for streaming applications where small data you are very familiar with the details of USB, then this loss is not critical, such as audio. section serves as a basic, high-level refresher of USB. • Bulk: This type of transfer method allows for large amounts of data to be transferred with ensured 22.9.1 LAYERED FRAMEWORK data integrity; however, the delivery timeliness is USB device functionality is structured into a layered not ensured. framework graphically shown in Figure22-12. Each • Interrupt: This type of transfer provides for level is associated with a functional level within the ensured timely delivery for small blocks of data, device. The highest layer, other than the device, is the plus data integrity is ensured. configuration. A device may have multiple configura- • Control: This type provides for device setup tions. For example, a particular device may have control. multiple power requirements based on Self-Power Only or Bus Power Only modes. While full-speed devices support all transfer types, low-speed devices are limited to interrupt and control For each configuration, there may be multiple transfers only. interfaces. Each interface could support a particular mode of that configuration. 22.9.4 POWER Below the interface is the endpoint(s). Data is directly Power is available from the Universal Serial Bus. The moved at this level. There can be as many as USB specification defines the bus power requirements. 16bidirectional endpoints. Endpoint 0 is always a Devices may either be self-powered or bus powered. control endpoint and by default, when the device is on Self-powered devices draw power from an external the bus, Endpoint 0 must be available to configure the source, while bus powered devices use power supplied device. from the bus. 22.9.2 FRAMES Information communicated on the bus is grouped into 1ms time slots, referred to as frames. Each frame can contain many transactions to various devices and endpoints. Figure22-8 shows an example of a transaction within a frame. FIGURE 22-12: USB LAYERS Device To other Configurations (if any) Configuration To other Interfaces (if any) Interface Interface Endpoint Endpoint Endpoint Endpoint Endpoint © 2009 Microchip Technology Inc. DS39775C-page 335

PIC18F87J50 FAMILY The USB specification limits the power taken from the 22.9.6.2 Configuration Descriptor bus. Each device is ensured 100mA at approximately The configuration descriptor provides information on 5V (one unit load). Additional power may be requested, the power requirements of the device and how many up to a maximum of 500mA. Note that power above different interfaces are supported when in this configu- one unit load is a request and the host or hub is not ration. There may be more than one configuration for a obligated to provide the extra current. Thus, a device device (i.e., low-power and high-power configurations). capable of consuming more than one unit load must be able to maintain a low-power configuration of a one unit 22.9.6.3 Interface Descriptor load or less, if necessary. The interface descriptor details the number of end- The USB specification also defines a Suspend mode. points used in this interface, as well as the class of the In this situation, current must be limited to 500μA, interface. There may be more than one interface for a averaged over 1 second. A device must enter a configuration. Suspend state after 3ms of inactivity (i.e., no SOF tokens for 3ms). A device entering Suspend mode 22.9.6.4 Endpoint Descriptor must drop current consumption within 10ms after The endpoint descriptor identifies the transfer type Suspend. Likewise, when signaling a wake-up, the (Section22.9.3 “Transfers”) and direction, as well as device must signal a wake-up within 10ms of drawing some other specifics for the endpoint. There may be current above the Suspend limit. many endpoints in a device and endpoints may be 22.9.5 ENUMERATION shared in different configurations. When the device is initially attached to the bus, the host 22.9.6.5 String Descriptor enters an enumeration process in an attempt to identify Many of the previous descriptors reference one or the device. Essentially, the host interrogates the device, more string descriptors. String descriptors provide gathering information such as power consumption, data human readable information about the layer rates and sizes, protocol and other descriptive (Section22.9.1 “Layered Framework”) they information; descriptors contain this information. A describe. Often these strings show up in the host to typical enumeration process would be as follows: help the user identify the device. String descriptors are 1. USB Reset: Reset the device. Thus, the device generally optional to save memory and are encoded in is not configured and does not have an address a unicode format. (address 0). 2. Get Device Descriptor: The host requests a 22.9.7 BUS SPEED small portion of the device descriptor. Each USB device must indicate its bus presence and 3. USB Reset: Reset the device again. speed to the host. This is accomplished through a 4. Set Address: The host assigns an address to the 1.5kΩ resistor which is connected to the bus at the device. time of the attachment event. 5. Get Device Descriptor: The host retrieves the Depending on the speed of the device, the resistor device descriptor, gathering info such as either pulls up the D+ or D- line to 3.3V. For a manufacturer, type of device, maximum control low-speed device, the pull-up resistor is connected to packet size. the D- line. For a full-speed device, the pull-up resistor 6. Get configuration descriptors. is connected to the D+ line. 7. Get any other descriptors. 22.9.8 CLASS SPECIFICATIONS AND 8. Set a configuration. DRIVERS The exact enumeration process depends on the host. USB specifications include class specifications which 22.9.6 DESCRIPTORS operating system vendors optionally support. Examples of classes include Audio, Mass Storage, There are eight different standard descriptor types of Communications and Human Interface (HID). In most which five are most important for this device. cases, a driver is required at the host side to ‘talk’ to the USB device. In custom applications, a driver may need 22.9.6.1 Device Descriptor to be developed. Fortunately, drivers are available for The device descriptor provides general information, most common host systems for the most common such as manufacturer, product number, serial number, classes of devices. Thus, these drivers can be reused. the class of the device and the number of configurations. There is only one device descriptor. DS39775C-page 336 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 23.0 COMPARATOR MODULE 23.1 Registers The analog comparator module contains two compara- The CMxCON registers (Register23-1) select the input tors that can be independently configured in a variety of and output configuration for each comparator, as well ways. The inputs can be selected from the analog as the settings for interrupt generation. inputs and two internal voltage references. The digital The CMSTAT register (Register23-2) provides the out- outputs are available at the pin level and can also be put results of the comparators. The bits in this register read through the control register. Multiple output and are read-only. interrupt event generation are also available. A generic single comparator from the module is shown in Figure23-1. Key features of the module includes: • Independent comparator control • Programmable input configuration • Output to both pin and register levels • Programmable output polarity • Independent interrupt generation for each comparator with configurable interrupt-on-change FIGURE 23-1: COMPARATOR SIMPLIFIED BLOCK DIAGRAM CCH1:CCH0 COUTx (CMSTAT<1:0>) CxINB 0 CxINC 1(1) Interrupt CxIND 2(1,2) Logic CMxIF VIRV 3 EVPOL<4:3> CREF COE VIN- CxOUT Polarity CxINA 0 VIN+ Cx Logic CVREF 1 CON CPOL Note 1: Available in 80-pin devices only. 2: Implemented in Comparator 2 only. © 2009 Microchip Technology Inc. DS39775C-page 337

PIC18F87J50 FAMILY REGISTER 23-1: CMxCON: COMPARATOR CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 5 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 4-3 EVPOL1:EVPOL0: Interrupt Polarity Select bits 11 = Interrupt generation on any change of the output(1) 10 = Interrupt generation only on high-to-low transition of the output 01 = Interrupt generation only on low-to-high transition of the output 00 = Interrupt generation is disabled bit 2 CREF: Comparator Reference Select bit (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CxINA pin bit 1-0 CCH1:CCH0: Comparator Channel Select bits 11 = Inverting input of comparator connects to VIRV 10 = Inverting input of comparator connects to CxIND pin(2) 01 = Inverting input of comparator connects to CxINC pin(2) 00 = Inverting input of comparator connects to CxINB pin Note 1: The CMxIF is automatically set any time this mode is selected and must be cleared by the application after the initial configuration. 2: Available in 80-pin devices only. DS39775C-page 338 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 23-2: CMSTAT: COMPARATOR STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R-1 R-1 — — — — — — COUT2 COUT1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 COUT2:COUT1: Comparator x Status bits If CPOL = 0 (non-inverted polarity): 1 = Comparator’s VIN+ > VIN- 0 = Comparator’s VIN+ < VIN- If CPOL = 1 (inverted polarity): 1 = Comparator VIN+ < VIN- 0 = Comparator VIN+ > VIN- © 2009 Microchip Technology Inc. DS39775C-page 339

PIC18F87J50 FAMILY 23.2 Comparator Operation 23.3 Comparator Response Time A single comparator is shown in Figure23-2, along with Response time is the minimum time, after selecting a the relationship between the analog input levels and new reference voltage or input source, before the com- the digital output. When the analog input at VIN+ is less parator output has a valid level. The response time of than the analog input VIN-, the output of the comparator the comparator differs from the settling time of the volt- is a digital low level. When the analog input at VIN+ is age reference. Therefore, both of these times must be greater than the analog input VIN-, the output of the considered when determining the total response to a comparator is a digital high level. The shaded areas of comparator input change. Otherwise, the maximum the output of the comparator in Figure23-2 represent delay of the comparators should be used (see the uncertainty due to input offsets and response time. Section28.0 “Electrical Characteristics”). 23.4 Analog Input Connection FIGURE 23-2: SINGLE COMPARATOR Considerations VIN+ + A simplified circuit for an analog input is shown in Output Figure23-3. Since the analog pins are connected to a VIN- – digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may VIN- occur. A maximum source impedance of 10kΩ is recommended for the analog sources. Any external VIN+ component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. Output FIGURE 23-3: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L5E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage DS39775C-page 340 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 23.5 Comparator Control and The comparator module also allows the selection of an Configuration internally generated voltage reference (CVREF) from the comparator voltage reference module. This module Each comparator has up to eight possible combina- is described in more detail in Section23.0 “Compara- tions of inputs: up to four external analog inputs, and tor Module”. The reference from the comparator one of two internal voltage references. voltage reference module is only available when Both comparators allow a selection of the signal from CREF=1. In this mode, the internal voltage reference pin, CxINA, or the voltage from the comparator refer- is applied to the comparator’s VIN+ pin. ence (CVREF) on the non-inverting channel. This is Note: The comparator input pin selected by compared to either CxINB, CxINC, CXIND or the micro- CCH1:CH0 must be configured as an input controller’s fixed internal reference voltage (VIRV, 1.2V by setting both the corresponding TRISF or nominal) on the inverting channel. The comparator TRISH bit, and the corresponding PCFG bit inputs and outputs are tied to fixed I/O pins, defined in in the ANCON1 register. Table23-1. The available comparator configurations and their corresponding bit settings are shown in 23.5.1.1 Comparator Configurations in 64-Pin Figure23-4. and 80-Pin Devices In PIC18F87J10 family devices, the C and D input TABLE 23-1: COMPARATOR INPUTS AND channels for both comparators are linked to pins in OUTPUTS PORTH and cannot be reassigned to alternate analog Comparator Input or Output I/O Pin inputs. Because of this, 64-pin devices offer a total of 4 different configurations for each comparator. In con- C1INA (VIN+) RF6 trast, 80-pin devices offer a choice of 6 configurations C1INB (VIN-) RF5 for Comparator 1, and 8 configurations for 1 C1INC (VIN-)(1) RH6(1) Comparator2. The configurations shown in Figure23-4 C1OUT RF7 are footnoted to indicate where they are not available. C2INA(VIN+) RF5 23.5.2 COMPARATOR ENABLE AND C2INB(VIN-) RF2 OUTPUT SELECTION 2 C2INC(VIN-)(1) RH4(1) The comparator outputs are read through the CMSTAT C2IND(VIN-)(1) RH5(1) register. The CMSTAT<0> reads the Comparator 1 out- C2OUT RC5 put and CMSTAT<1> reads the Comparator 2 output. These bits are read-only. Note 1: Available in 80-pin devices only. The comparator outputs may also be directly output to 23.5.1 COMPARATOR ENABLE AND the RF1 and RF2 I/O pins by setting the COE bit INPUT SELECTION (CMxCON<6>). When enabled, multiplexors in the output path of the pins switch to the output of the com- Setting the CON bit of the CMxCON register parator. The TRISF<1:2> bits still function as the digital (CMxCON<7>) enables the comparator for operation. output enable for the RF1 and RF2 pins while in this Clearing the CON bit disables the comparator resulting mode. in minimum current consumption. By default, the comparator’s output is at logic high The CCH1:CCH0 bits in the CMxCON register whenever the voltage on VIN+ is greater than on VIN-. (CMxCON<1:0>) direct either one of three analog input The polarity of the comparator outputs can be inverted pins, or the Internal Reference Voltage (VIRV), to the using the CPOL bit (CMxCON<5>). comparator VIN-. Depending on the comparator operat- ing mode, either an external or internal voltage The uncertainty of each of the comparators is related to reference may be used. The analog signal present at the input offset voltage and the response time given in VIN- is compared to the signal at VIN+ and the digital the specifications, as discussed in Section23.2 output of the comparator is adjusted accordingly. “Comparator Operation”. The external reference is used when CREF=0 (CMxCON<2>) and VIN+ is connected to the CxINA pin. When external voltage references are used, the comparator module can be configured to have the ref- erence sources externally. The reference signal must be between VSS and VDD, and can be applied to either pin of the comparator. © 2009 Microchip Technology Inc. DS39775C-page 341

PIC18F87J50 FAMILY FIGURE 23-4: COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx COE VIN- VIN+ Cx Off (Read as ‘0’) CxOUT pin Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 CON = 1, CREF = 0, CCH<1:0> = 01 COE COE CxINB VIN- CxINC VIN- CxINA VIN+ Cx CxOUT CxINA VIN+ Cx CxOUT pin pin Comparator CxIND > CxINA Compare Comparator VIRV > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 10 CON = 1, CREF = 0, CCH<1:0> = 11 COE COE CxIND VIN- VIRV VIN- CxINA VIN+ Cx CxOUT CxINA VIN+ Cx CxOUT pin pin Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 00 CON = 1, CREF = 1, CCH<1:0> = 01 COE COE CxINB VIN- CxINC VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT pin pin Comparator CxIND > CVREF Compare Comparator VIRV > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 10 CON = 1, CREF = 1, CCH<1:0> = 11 COE COE CxIND VIN- VIRV VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT pin pin Note: VIRV is the Internal Reference Voltage (see Table28-2). DS39775C-page 342 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 23.6 Comparator Interrupts low transition of the comparator output. Once the interrupt is generated, it is required to clear the interrupt The comparator interrupt flag is set whenever any of flag by software. the following occurs: When EVPOL<1:0> = 11, the comparator interrupt flag - Low-to-high transition of the comparator is set whenever there is a change in the output value of output either comparator. Software will need to maintain infor- - High-to-low transition of the comparator mation about the status of the output bits, as read from output CMSTAT<1:0>, to determine the actual change that - Any change in the comparator output. occurred. The CMxIF bits (PIR2<6:5>) are the Compar- ator Interrupt Flags. The CMxIF bits must be reset by The comparator interrupt selection is done by the clearing them. Since it is also possible to write a ‘1’ to EVPOL1:EVPOL0 bits in the CMxCON register this register, a simulated interrupt may be initiated. (CMxCON<4:3>). Table23-2 shows the interrupt generation with respect In order to provide maximum flexibility, the output of the to comparator input voltages and EVPOL bit settings. comparator may be inverted using the CPOL bit in the Both the CMxIE bits (PIE2<6:5>) and the PEIE bit CMxCON register (CMxCON<5>). This is functionally (INTCON<6>) must be set to enable the interrupt. In identical to reversing the inverting and non-inverting addition, the GIE bit (INTCON<7>) must also be set. If inputs of the comparator for a particular mode. any of these bits are clear, the interrupt is not enabled, An interrupt is generated on the low-to-high or high-to- though the CMxIF bits will still be set if an interrupt low transition of the comparator output. This mode of condition occurs. A simplified diagram of the interrupt interrupt generation is dependent on EVPOL<1:0> in section is shown in Figure23-3. the CMxCON register. When EVPOL<1:0> = 01 or 10, the interrupt is generated on a low-to-high or high-to- TABLE 23-2: COMPARATOR INTERRUPT GENERATION Comparator Interrupt CPOL EVPOL<1:0> COUTx Transition Input Change Generated VIN+ > VIN- Low-to-High No 00 VIN+ < VIN- High-to-Low No VIN+ > VIN- Low-to-High Yes 01 VIN+ < VIN- High-to-Low No 0 VIN+ > VIN- Low-to-High No 10 VIN+ < VIN- High-to-Low Yes VIN+ > VIN- Low-to-High Yes 11 VIN+ < VIN- High-to-Low Yes VIN+ > VIN- High-to-Low No 00 VIN+ < VIN- Low-to-High No VIN+ > VIN- High-to-Low No 01 VIN+ < VIN- Low-to-High Yes 1 VIN+ > VIN- High-to-Low Yes 10 VIN+ < VIN- Low-to-High No VIN+ > VIN- High-to-Low Yes 11 VIN+ < VIN- Low-to-High Yes © 2009 Microchip Technology Inc. DS39775C-page 343

PIC18F87J50 FAMILY 23.7 Comparator Operation 23.8 Effects of a Reset During Sleep A device Reset forces the CMxCON registers to their When a comparator is active and the device is placed Reset state. This forces both comparators and the in Sleep mode, the comparator remains active and the voltage reference to the OFF state. interrupt is functional, if enabled. This interrupt will wake-up the device from Sleep mode, when enabled. Each operational comparator will consume additional current. To minimize power consumption while in Sleep mode, turn off the comparators (CON=0) before entering Sleep. If the device wakes up from Sleep, the contents of the CMxCON register are not affected. TABLE 23-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 64 PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE 64 IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP 64 CMxCON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 62 CVRCON(1) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 65 CMSTAT — — — — — — COUT2 COUT1 65 ANCON1(1) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 — — 63 ANCON0(1) PCFG7 — — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 63 PORTA — — RA5 RA4 RA3 RA2 RA1 — 65 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 — 64 LATA — — LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 64 PORTC RC7 RC6 RC5 RC4 RC3 RFC2 RFC1 RFC0 65 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 64 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 64 PORTF RF7 RF6 RF5 RF4 RF3 RF2 — — 65 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 — — 64 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 — — 64 PORTH(2) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 65 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 64 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. 2: This register is not implemented on 64-pin devices. DS39775C-page 344 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 24.0 COMPARATOR VOLTAGE A block diagram of the module is shown in Figure24-1. REFERENCE MODULE The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to The comparator voltage reference is a 16-tap resistor conserve power when the reference is not being used. ladder network that provides a selectable reference The module’s supply reference can be provided from voltage. Although its primary purpose is to provide a either device VDD/VSS or an external voltage reference. reference for the analog comparators, it may also be used independently of them. FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ VDD CVRSS = 0 8R CVR3:CVR0 R CVREN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 © 2009 Microchip Technology Inc. DS39775C-page 345

PIC18F87J50 FAMILY 24.1 Configuring the Comparator The comparator reference supply voltage can come Voltage Reference from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The The comparator voltage reference module is controlled voltage source is selected by the CVRSS bit through the CVRCON register (Register24-1). The (CVRCON<4>). comparator voltage reference provides two ranges of The settling time of the comparator voltage reference output voltage, each with 16 distinct levels. The range must be considered when changing the CVREF to be used is selected by the CVRR bit (CVRCON<5>). output (see Table28-3 in Section28.0 “Electrical The primary difference between the ranges is the size Characteristics”). of the steps selected by the CVREF Selection bits The CVRCON register is a shared address SFR and (CVR3:CVR0), with one range offering finer resolution. uses the same address as the PR4 register. The The equations used to calculate the output of the CVRCON register is accessed by setting the ADSHR comparator voltage reference are as follows: bit (WDTCON<4>). If CVRR = 1: CVREF = ((CVR3:CVR0)/24) x (CVRSRC) If CVRR = 0: CVREF=(CVRSRC/4)+((CVR3:CVR0)/32)x (CVRSRC) REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RF5/AN10/C1INB/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/C1INB/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = AVDD – AVSS bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15) When CVRR = 1: CVREF = ((CVR3:CVR0)/24) • (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC) Note 1: CVROE overrides the TRISF<5> bit setting. DS39775C-page 346 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 24.2 Voltage Reference Accuracy/Error The RF5 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive The full range of voltage reference cannot be realized capability, a buffer must be used on the voltage due to the construction of the module. The transistors reference output for external connections to VREF. on the top and bottom of the resistor ladder network Figure24-2 shows an example buffering technique. (Figure24-1) keep CVREF from approaching the refer- ence source rails. The voltage reference is derived 24.4 Operation During Sleep from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested When the device wakes up from Sleep through an absolute accuracy of the voltage reference can be interrupt or a Watchdog Timer time-out, the contents of found in Section28.0 “Electrical Characteristics”. the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage 24.3 Connection Considerations reference should be disabled. The voltage reference module operates independently 24.5 Effects of a Reset of the comparator module. The output of the reference generator may be connected to the RF5 pin if the A device Reset disables the voltage reference by CVROE bit is set. Enabling the voltage reference out- clearing bit, CVREN (CVRCON<7>). This Reset also put onto RA2 when it is configured as a digital input will disconnects the reference from the RA2 pin by clearing increase current consumption. Connecting RF5 as a bit, CVROE (CVRCON<6>) and selects the high-voltage digital output with CVRSS enabled will also increase range by clearing bit, CVRR (CVRCON<5>). The CVR current consumption. value select bits are also cleared. FIGURE 24-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F87J50 CVREF R(1) Module + Voltage RF5 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the Comparator Voltage Reference Configuration bits, CVRCON<5> and CVRCON<3:0>. TABLE 24-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: CVRCON(1) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 65 CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 62 CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 62 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 64 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 — — 64 ANCON0(1) PCFG7 — — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 63 ANCON1(1) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 — — 63 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference. Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1. © 2009 Microchip Technology Inc. DS39775C-page 347

PIC18F87J50 FAMILY NOTES: DS39775C-page 348 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 25.0 SPECIAL FEATURES OF THE 25.1.1 CONSIDERATIONS FOR CPU CONFIGURING THE PIC18F87J50 FAMILY DEVICES PIC18F87J10 family devices include several features Unlike previous PIC18 microcontrollers, devices of the intended to maximize reliability and minimize cost PIC18F87J10 family do not use persistent memory through elimination of external components. These are: registers to store configuration information. The config- • Oscillator Selection uration bytes are implemented as volatile memory, • Resets: which means that configuration data must be - Power-on Reset (POR) programmed each time the device is powered up. - Power-up Timer (PWRT) Configuration data is stored in the four words at the top - Oscillator Start-up Timer (OST) of the on-chip program memory space, known as the - Brown-out Reset (BOR) Flash Configuration Words. It is stored in program memory in the same order shown in Table25-2, with • Interrupts CONFIG1L at the lowest address and CONFIG3H at • Watchdog Timer (WDT) the highest. The data is automatically loaded in the • Fail-Safe Clock Monitor proper Configuration registers during device power-up. • Two-Speed Start-up When creating applications for these devices, users • Code Protection should always specifically allocate the location of the • In-Circuit Serial Programming Flash Configuration Word for configuration data. This is The oscillator can be configured for the application to make certain that program code is not stored in this depending on frequency, power, accuracy and cost. All address when the code is compiled. of the options are discussed in detail in Section2.0 The volatile memory cells used for the Configuration “Oscillator Configurations”. bits always reset to ‘1’ on Power-on Resets. For all A complete discussion of device Resets and interrupts other type of Reset events, the previously programmed is available in previous sections of this data sheet. In values are maintained and used without reloading from addition to their Power-up and Oscillator Start-up program memory. Timers provided for Resets, the PIC18F87J10 family of The four Most Significant bits of CONFIG1H, devices have a configurable Watchdog Timer which is CONFIG2H and CONFIG3H in program memory controlled in software. should also be ‘1111’. This makes these Configuration The inclusion of an internal RC oscillator also provides Words appear to be NOP instructions in the remote the additional benefits of a Fail-Safe Clock Monitor event that their locations are ever executed by (FSCM) and Two-Speed Start-up. FSCM provides for accident. Since Configuration bits are not implemented background monitoring of the peripheral clock and in the corresponding locations, writing ‘1’s to these automatic switchover in the event of its failure. locations has no effect on device operation. Two-Speed Start-up enables code to be executed To prevent inadvertent configuration changes during almost immediately on start-up, while the primary clock code execution, all programmable Configuration bits source completes its start-up delays. are write-once. After a bit is initially programmed during All of these features are enabled and configured by a power cycle, it cannot be written to again. Changing setting the appropriate Configuration register bits. a device configuration requires that power to the device be cycled. 25.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various device configurations. These bits are mapped starting at program memory location 300000h. A complete list is shown in Table25-2. A detailed explanation of the various bit functions is provided in Register25-1 through Register25-6. © 2009 Microchip Technology Inc. DS39775C-page 349

PIC18F87J50 FAMILY TABLE 25-1: MAPPING OF THE FLASH CONFIGURATION WORDS TO THE CONFIGURATION REGISTERS Configuration Register Configuration Byte Code Space Address Address CONFIG1L XXXF8h 300000h CONFIG1H XXXF9h 300001h CONFIG2L XXXFAh 300002h CONFIG2H XXXFBh 300003h CONFIG3L XXXFCh 300004h CONFIG3H XXXFDh 300005h CONFIG4L(1) XXXFEh 300006h CONFIG4H(1) XXXFFh 300007h Note 1: Unimplemented in PIC18F87J10 family devices. TABLE 25-2: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value(1) 300000h CONFIG1L DEBUG XINST STVREN — PLLDIV2 PLLDIV1 PLLDIV0 WDTEN 111- 1111 300001h CONFIG1H —(2) —(2) —(2) —(2) — CP0 CPDIV1 CPDIV0 1111 -111 300002h CONFIG2L IESO FCMEN — — — FOSC2 FOSC1 FOSC0 11-- -111 300003h CONFIG2H —(2) —(2) —(2) —(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 1111 1111 300004h CONFIG3L WAIT(3) BW(3) EMB1(3) EMB0(3) EASHFT(3) — — — 1111 1--- 300005h CONFIG3H —(2) —(2) —(2) —(2) MSSPMSK PMPMX(3) ECCPMX(3) CCP2MX 1111 1111 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxx0 0000(4) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0100 00xx(4) Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’. Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the configuration bytes maintain their previously programmed states. 2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed. 3: Implemented in 80-pin devices only. 4: See Register25-7 and Register25-8 for DEVID values. These registers are read-only and cannot be programmed by the user. DS39775C-page 350 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 25-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-1 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1 DEBUG XINST STVREN — PLLDIV2 PLLDIV1 PLLDIV0 WDTEN bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled bit 4 Unimplemented: Read as ‘0’ bit 3-1 PLLDIV2:PLLDIV0: Oscillator Selection bits Divider must be selected to provide a 4 MHz input into the 96 MHz PLL 111 = No divide - oscillator used directly (4 MHz input) 110 = Oscillator divided by 2 (8 MHz input) 101 = Oscillator divided by 3 (12 MHz input) 100 = Oscillator divided by 4 (16 MHz input) 011 = Oscillator divided by 5 (20 MHz input) 010 = Oscillator divided by 6 (24 MHz input) 001 = Oscillator divided by 10 (40 MHz input) 000 = Oscillator divided by 12 (48 MHz input) bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) © 2009 Microchip Technology Inc. DS39775C-page 351

PIC18F87J50 FAMILY REGISTER 25-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-1 U-1 U-1 U-1 U-0 R/WO-1 R/WO-1 R/WO-1 — — — — — CP0 CPDIV1 CPDIV0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Maintain as ‘1’ bit 3 Unimplemented: Read as ‘0’ bit 2 CP0: Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is code-protected bit 1-0 CPDIV1:CPDIV0: CPU System Clock Selection bits 11 = No CPU system clock divide 10 = CPU system clock divided by 2 01 = CPU system clock divided by 3 00 = CPU system clock divided by 6 DS39775C-page 352 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 25-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/WO-1 R/WO-1 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 IESO FCMEN — — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-3 Unimplemented: Read as ‘0’ bit 2-0 FOSC2:FOSC0: Oscillator Selection bits 111 = ECPLL oscillator with PLL enabled, CLKO on RA6, ECPLL oscillator used by USB 110 = EC oscillator with CLKO on RA6 , EC oscillator used by USB 101 = HSPLL oscillator with PLL enabled, HSPLL oscillator used by USB 100 = HS oscillator, HS oscillator used by USB 011 = INTOSCPLLO, internal oscillator with INTOSCPLL enabled, CLKO on RA6 and port function RA7 010 = INTOSCPLL, Internal oscillator with Port function on RA6 and RA7 001 = INTOSCO internal oscillator block (INTRC/INTOSC) with CLKO on RA6 Port function on RA7 000 = INTOSC internal oscillator block (INTRC/INTOSC) Port function on RA6 and RA7 © 2009 Microchip Technology Inc. DS39775C-page 353

PIC18F87J50 FAMILY REGISTER 25-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 — — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 DS39775C-page 354 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 25-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 WAIT(1) BW(1) EMB1(1) EMB0(1) EASHFT(1) — — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states on the external bus are disabled 0 = Wait states on the external bus are enabled and selected by MEMCON<5:4> bit 6 BW: Data Bus Width Select bit(1) 1 = 16-Bit Data Width modes 0 = 8-Bit Data Width modes bit 5-4 EMB1:EMB0: External Memory Bus Configuration bits(1) 11 = Microcontroller mode, external bus disabled 10 = Extended Microcontroller mode, 12-bit address width for external bus 01 = Extended Microcontroller mode, 16-bit address width for external bus 00 = Extended Microcontroller mode, 20-bit address width for external bus bit 3 EASHFT: External Address Bus Shift Enable bit(1) 1 = Address shifting enabled – external address bus is shifted to start at 000000h 0 = Address shifting disabled – external address bus reflects the PC value bit 2-0 Unimplemented: Read as ‘0’ Note 1: Implemented only on 80-pin devices. © 2009 Microchip Technology Inc. DS39775C-page 355

PIC18F87J50 FAMILY REGISTER 25-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 — — — — MSSPMSK PMPMX(1) ECCPMX(1) CCP2MX bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Maintain as ‘1’ bit 3 MSSPMSK: MSSP V3’s 7-Bit Address Masking Mode Enable bit 1 = 7-Bit Address Masking mode enable 0 = 5-Bit Address Masking mode enable bit 2 PMPMX: PMP pin placement bit for the 80-pin TQFP(1) 1 = PMP pins placed on EMB 0 = PMP pins placed else where bit 1 ECCPMX: ECCPx MUX bit(1) 1 = ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 0 = ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 bit 0 CCP2MX: ECCP2 MUX bit 1 = ECCP2/P2A is multiplexed with RC1 0 = ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (all devices) or with RB3 in Extended Microcontroller mode (80-pin devices only) Note 1: Implemented only on 80-pin devices. DS39775C-page 356 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 25-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F87J50 FAMILY DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 DEV2:DEV0: Device ID bits(1) 111 = PIC18F86J50 110 = reserved 101 = PIC18F85J50 100 = PIC18F67J50 011 = PIC18F66J55 010 = PIC18F66J50 001 = PIC18F87J50 000 = PIC18F65J50 and PIC18F86J55 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Note 1: Where values for DEV2:DEV0 are shared by more than one device number, the specific device is always identified by using the entire DEV10:DEV0 bit sequence. These bits are used with the DEV[10:3] bits in the Device ID Register 2 to identify the part number. REGISTER 25-8: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F87J50 FAMILY DEVICES R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 DEV10:DEV3: Device ID bits(1) These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. 0100 0001 = PIC18F65J50/66J50/66J55/67J50/85J50/86J50 0100 0010 = PIC18F87J50/86J55 Note 1: The values for DEV10:DEV3 may be shared with other device families. The specific device is always identified by using the entire DEV10:DEV0 bit sequence. © 2009 Microchip Technology Inc. DS39775C-page 357

PIC18F87J50 FAMILY 25.2 Watchdog Timer (WDT) 25.2.1 CONTROL REGISTER For PIC18F87J10 family devices, the WDT is driven by The WDTCON register (Register25-9) is a readable the INTRC oscillator. When the WDT is enabled, the and writable register. The SWDTEN bit enables or dis- clock source is also enabled. The nominal WDT period is ables WDT operation. This allows software to override 4ms and has the same stability as the INTRC oscillator. the WDTEN Configuration bit and enable the WDT only if it has been disabled by the Configuration bit. The 4ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected The ADSHR bit selects which SFRs currently are by a multiplexor, controlled by the WDTPS bits in Config- selected and accessible. For additional details, see uration Register 2H. Available periods range from about Section5.3.5.1 “Shared Address SFRs”. 4ms to 135seconds (2.25 minutes depending on LVDSTAT is a read-only status bit that is continuously voltage, temperature and WDT postscaler). The WDT updated and provides information about the current and postscaler are cleared whenever a SLEEP or level of VDDCORE. This bit is only valid when the on-chip CLRWDT instruction is executed, or a clock failure voltage regulator is enabled. (primary or Timer1 oscillator) has occurred. Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: When a CLRWDT instruction is executed, the postscaler count will be cleared. FIGURE 25-1: WDT BLOCK DIAGRAM Enable WDT SWDTEN INTRC Control WDT Counter INTRC Oscillator ÷128 Wake-up from Power-Managed Modes CLRWDT Programmable Postscaler Reset WDT All Device Resets 1:1 to 1:32,768 Reset WDT 4 WDTPS3:WDTPS0 Sleep DS39775C-page 358 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY REGISTER 25-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER R/W-0 R-x U-0 R/W-0 U-0 U-0 U-0 U-0 REGSLP(2) LVDSTAT — ADSHR — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 REGSLP: Voltage Regulator Low-Power Operation Enable bit(2) 1 = On-chip regulator enters low-power operation when device enters Sleep mode 0 = On-chip regulator is active even in Sleep mode bit 6 LVDSTAT: Low-Voltage Detect Status bit 1 = VDDCORE > 2.45V nominal 0 = VDDCORE < 2.45V nominal bit 5 Unimplemented: Read as ‘0’ bit 4 ADSHR: Shared Address SFR Select bit For details of bit operation, see Register5-3. bit 3-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled. 2: The REGSLP bit is automatically cleared when a Low-Voltage Detect condition occurs. TABLE 25-3: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page: RCON IPEN — CM RI TO PD POR BOR 62 WDTCON REGSLP LVDSTAT — ADSHR — — — SWDTEN 63 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer. © 2009 Microchip Technology Inc. DS39775C-page 359

PIC18F87J50 FAMILY 25.3 On-Chip Voltage Regulator FIGURE 25-2: CONNECTIONS FOR THE ON-CHIP REGULATOR All of the PIC18F87J10 family devices power their core digital logic at a nominal 2.5V. For designs that are Regulator Enabled (ENVREG tied to VDD): required to operate at a higher typical voltage, such as 3.3V 3.3V, all devices in the PIC18F87J10 family incorporate an on-chip regulator that allows the device to run its PIC18F87J50 core logic from VDD. VDD ENVREG The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, pro- VDDCORE/VCAP vides power to the core from the other VDD pins. When CF the regulator is enabled, a low-ESR filter capacitor VSS must be connected to the VDDCORE/VCAP pin (Figure25-2). This helps to maintain the stability of the regulator. The recommended value for the filter capac- itor is provided in Section28.3 “DC Characteristics: PIC18F87J50 Family (Industrial)”. Regulator Disabled (ENVREG tied to ground): If ENVREG is tied to VSS, the regulator is disabled. In 2.5V(1) 3.3V(1) this case, separate power for the core logic at a nomi- nal 2.5V must be supplied to the device on the PIC18F87J50 VDDCORE/VCAP pin to run the I/O pins at higher voltage VDD levels, typically 3.3V. Alternatively, the VDDCORE/VCAP ENVREG and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure25-2 for possible VDDCORE/VCAP configurations. VSS 25.3.1 VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION When it is enabled, the on-chip regulator provides a con- Regulator Disabled (VDD tied to VDDCORE): stant voltage of 2.5V nominal to the digital core logic. The regulator can provide this level from a VDD of about 2.5V(1) 2.5V, all the way up to the device’s VDDMAX. It does not PIC18F87J50 have the capability to boost VDD levels below 2.5V. In VDD order to prevent “brown-out” conditions, when the volt- ENVREG age drops too low for the regulator, the regulator enters Tracking mode. In Tracking mode, the regulator output VDDCORE/VCAP follows VDD, with a typical voltage drop of 100mV. VSS The on-chip regulator includes a simple Low-Voltage Detect (LVD) circuit. If VDD drops too low to maintain approximately 2.45V on VDDCORE, the circuit sets the Note 1: These are typical operating voltages. Refer Low-Voltage Detect Interrupt Flag, LVDIF (PIR2<2>). to Section28.1 “DC Characteristics: This can be used to generate an interrupt and put the Supply Voltage” for the full operating application into a low-power operational mode, or trig- ranges of VDD and VDDCORE. ger an orderly shutdown. Low-Voltage Detection is only available when the regulator is enabled. The Low-Voltage Detect interrupt is edge-sensitive and will only be set once per falling edge of VDDCORE. Firm- ware can clear the interrupt flag, but a new interrupt will not be generated until VDDCORE rises back above, and then falls below, the 2.45V nominal threshold. Device Resets will reset the interrupt flag to ‘0’, even if VDDCORE is less than 2.45V. When the regulator is enabled, the LVDSTAT bit in the WDTCON register can be polled to determine the current level of VDDCORE. DS39775C-page 360 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 25.3.2 ON-CHIP REGULATOR AND BOR Substantial Sleep mode power savings can be obtained by setting the REGSLP bit, but device When the on-chip regulator is enabled, PIC18F87J10 wake-up time will increase in order to insure the regu- family devices also have a simple brown-out capability. lator has enough time to stabilize. The REGSLP bit is If the voltage supplied to the regulator is inadequate to automatically cleared by hardware when a Low-Voltage maintain a regulated level, the regulator Reset circuitry Detect condition occurs. will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<0>). 25.4 Two-Speed Start-up The operation of the Brown-out Reset is described in more detail in Section4.4 “Brown-out Reset (BOR)” The Two-Speed Start-up feature helps to minimize the and Section4.4.1 “Detecting BOR”. The brown-out latency period, from oscillator start-up to code execu- voltage levels are specific in Section28.1 “DC Charac- tion, by allowing the microcontroller to use the INTRC teristics: Supply Voltage PIC18F87J50 Family oscillator as a clock source until the primary clock (Industrial)”. source is available. It is enabled by setting the IESO Configuration bit. 25.3.3 POWER-UP REQUIREMENTS Two-Speed Start-up should be enabled only if the The on-chip regulator is designed to meet the power-up primary oscillator mode is HS or HSPLL requirements for the device. If the application does not (Crystal-Based) modes. Since the EC and ECPLL use the regulator, then strict power-up conditions must modes do not require an Oscillator Start-up Timer be adhered to. While powering up, VDDCORE must (OST) delay, Two-Speed Start-up should be disabled. never exceed VDD by 0.3 volts. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the inter- 25.3.4 OPERATION IN SLEEP MODE nal oscillator block as the clock source, following the When enabled, the on-chip regulator always consumes time-out of the Power-up Timer after a Power-on Reset a small incremental amount of current over IDD. This is enabled. This allows almost immediate code includes when the device is in Sleep mode, even execution while the primary oscillator starts and the though the core digital logic does not require power. To OST is running. Once the OST times out, the device provide additional savings in applications where power automatically switches to PRI_RUN mode. resources are critical, the regulator can be configured In all other power-managed modes, Two-Speed to automatically disable itself whenever the device Start-up is not used. The device will be clocked by the goes into Sleep mode. This feature is controlled by the currently selected clock source until the primary clock REGSLP bit (WDTCON<7>, Register25-9). Setting source becomes available. The setting of the IESO bit this bit disables the regulator in Sleep mode and is ignored. reduces its current consumption to a minimum. FIGURE 25-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake from Interrupt Event OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. © 2009 Microchip Technology Inc. DS39775C-page 361

PIC18F87J50 FAMILY 25.4.1 SPECIAL CONSIDERATIONS FOR Clock failure is tested for on the falling edge of the USING TWO-SPEED START-UP sample clock. If a sample clock falling edge occurs while the clock monitor is still set, a clock failure has While using the INTRC oscillator in Two-Speed been detected (Figure25-5). This causes the following: Start-up, the device still obeys the normal command sequences for entering power-managed modes, • the FSCM generates an oscillator fail interrupt by including serial SLEEP instructions (refer to setting bit OSCFIF (PIR2<7>); Section3.1.4 “Multiple Sleep Commands”). In prac- • the device clock source is switched to the internal tice, this means that user code can change the oscillator block (OSCCON is not updated to show SCS1:SCS0 bit settings or issue SLEEP instructions the current clock source – this is the fail-safe before the OST times out. This would allow an applica- condition); and tion to briefly wake-up, perform routine “housekeeping” • the WDT is reset. tasks and return to Sleep before the device starts to During switchover, the postscaler frequency from the operate from the primary oscillator. internal oscillator block may not be sufficiently stable User code can also check if the primary clock source is for timing sensitive applications. In these cases, it may currently providing the device clocking by checking the be desirable to select another clock configuration and status of the OSTS bit (OSCCON<3>). If the bit is set, enter an alternate power-managed mode. This can be the primary oscillator is providing the clock. Otherwise, done to attempt a partial recovery or execute a the internal oscillator block is providing the clock during controlled shutdown. See Section3.1.4 “Multiple wake-up from Reset or Sleep mode. Sleep Commands” and Section25.4.1 “Special Considerations for Using Two-Speed Start-up” for 25.5 Fail-Safe Clock Monitor more details. The Fail-Safe Clock Monitor (FSCM) allows the The FSCM will detect failures of the primary or second- microcontroller to continue operation in the event of an ary clock sources only. If the internal oscillator block external oscillator failure by automatically switching the fails, no failure would be detected, nor would any action device clock to the internal oscillator block. The FSCM be possible. function is enabled by setting the FCMEN Configuration 25.5.1 FSCM AND THE WATCHDOG TIMER bit. Both the FSCM and the WDT are clocked by the When FSCM is enabled, the INTRC oscillator runs at INTRC oscillator. Since the WDT operates with a all times to monitor clocks to peripherals and provide a separate divider and counter, disabling the WDT has backup clock in the event of a clock failure. Clock no effect on the operation of the INTRC oscillator when monitoring (shown in Figure25-4) is accomplished by the FSCM is enabled. creating a sample clock signal which is the INTRC out- put divided by 64. This allows ample time between As already noted, the clock source is switched to the FSCM sample clocks for a peripheral clock edge to INTRC clock when a clock failure is detected; this may occur. The peripheral device clock and the sample mean a substantial change in the speed of code execu- clock are presented as inputs to the clock monitor latch. tion. If the WDT is enabled with a small prescale value, The clock monitor is set on the falling edge of the a decrease in clock speed allows a WDT time-out to device clock source but cleared on the rising edge of occur and a subsequent device Reset. For this reason, the sample clock. fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execu- FIGURE 25-4: FSCM BLOCK DIAGRAM tion speed was changed and decreasing the likelihood of an erroneous time-out. Clock Monitor Latch (edge-triggered) Peripheral S Q Clock INTRC ÷ 64 C Q Source (32 μs) 488 Hz (2.048 ms) Clock Failure Detected DS39775C-page 362 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 25-5: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Clock Monitor Test Clock Monitor Test Clock Monitor Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 25.5.2 EXITING FAIL-SAFE OPERATION 25.5.4 POR OR WAKE-UP FROM SLEEP The fail-safe condition is terminated by either a device The FSCM is designed to detect oscillator failure at any Reset or by entering a power-managed mode. On point after the device has exited Power-on Reset (POR) Reset, the controller starts the primary clock source or low-power Sleep mode. When the primary device specified in Configuration Register 2H (with any clock is either the EC or INTRC modes, monitoring can required start-up delays that are required for the oscil- begin immediately following these events. lator mode, such as OST or PLL timer). The INTRC For HS or HSPLL modes, the situation is somewhat oscillator provides the device clock until the primary different. Since the oscillator may require a start-up clock source becomes ready (similar to a Two-Speed time considerably longer than the FSCM sample clock Start-up). The clock source is then switched to the time, a false clock failure may be detected. To prevent primary clock (indicated by the OSTS bit in the this, the internal oscillator block is automatically config- OSCCON register becoming set). The Fail-Safe Clock ured as the device clock and functions until the primary Monitor then resumes monitoring the peripheral clock. clock is stable (the OST and PLL timers have timed The primary clock source may never become ready out). This is identical to Two-Speed Start-up mode. during start-up. In this case, operation is clocked by the Once the primary clock is stable, the INTRC returns to INTRC oscillator. The OSCCON register will remain in its role as the FSCM source. its Reset state until a power-managed mode is entered. Note: The same logic that prevents false oscilla- 25.5.3 FSCM INTERRUPTS IN tor failure interrupts on POR, or wake from Sleep, will also prevent the detection of POWER-MANAGED MODES the oscillator’s failure to start at all follow- By entering a power-managed mode, the clock ing these events. This can be avoided by multiplexor selects the clock source selected by the monitoring the OSTS bit and using a OSCCON register. Fail-Safe Clock Monitoring of the timing routine to determine if the oscillator power-managed clock source resumes in the is taking too long to start. Even so, no power-managed mode. oscillator failure interrupt will be flagged. If an oscillator failure occurs during power-managed As noted in Section25.4.1 “Special Considerations operation, the subsequent events depend on whether for Using Two-Speed Start-up”, it is also possible to or not the oscillator failure interrupt is enabled. If select another clock configuration and enter an alternate enabled (OSCFIF=1), code execution will be clocked power-managed mode while waiting for the primary by the INTRC multiplexor. An automatic transition back clock to become stable. When the new power-managed to the failed clock source will not occur. mode is selected, the primary clock is disabled. If the interrupt is disabled, subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTRC source. © 2009 Microchip Technology Inc. DS39775C-page 363

PIC18F87J50 FAMILY 25.6 Program Verification and 25.7 In-Circuit Serial Programming Code Protection PIC18F87J10 family microcontrollers can be serially For all devices in the PIC18F87J10 family of devices, programmed while in the end application circuit. This is the on-chip program memory space is treated as a simply done with two lines for clock and data and three single block. Code protection for this block is controlled other lines for power, ground and the programming by one Configuration bit, CP0. This bit inhibits external voltage. This allows customers to manufacture boards reads and writes to the program memory space. It has with unprogrammed devices and then program the no direct effect in normal execution mode. microcontroller just before shipping the product. This also allows the most recent firmware or a custom 25.6.1 CONFIGURATION REGISTER firmware to be programmed. PROTECTION 25.8 In-Circuit Debugger The Configuration registers are protected against untoward changes or reads in two ways. The primary When the DEBUG Configuration bit is programmed to protection is the write-once feature of the Configuration a ‘0’, the In-Circuit Debugger functionality is enabled. bits which prevents reconfiguration once the bit has This function allows simple debugging functions when been programmed during a power cycle. To safeguard used with MPLAB® IDE. When the microcontroller has against unpredictable events, Configuration bit this feature enabled, some resources are not available changes resulting from individual cell level disruptions for general use. Table25-4 shows which resources are (such as ESD events) will cause a parity error and required by the background debugger. trigger a device Reset. This is seen by the user as a Configuration Mismatch (CM) Reset. TABLE 25-4: DEBUGGER RESOURCES The data for the Configuration registers is derived from I/O pins: RB6, RB7 the Flash Configuration Words in program memory. Stack: 2 levels When the CP0 bit set, the source data for device configuration is also protected as a consequence. Program Memory: 512 bytes Data Memory: 10 bytes DS39775C-page 364 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 26.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: The PIC18F87J10 family of devices incorporate the • A literal value to be loaded into a file register standard set of 75 PIC18 core instructions, as well as (specified by ‘k’) an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software • The desired FSR register to load the literal value stack. The extended set is discussed later in this into (specified by ‘f’) section. • No operand required (specified by ‘—’) 26.1 Standard Instruction Set The control instructions may use some of the following operands: The standard PIC18 instruction set adds many enhancements to the previous PIC® instruction sets, • A program memory address (specified by ‘n’) while maintaining an easy migration from these PIC • The mode of the CALL or RETURN instructions instruction sets. Most instructions are a single program (specified by ‘s’) memory word (16 bits), but there are four instructions • The mode of the table read and table write that require two program memory locations. instructions (specified by ‘m’) Each single-word instruction is a 16-bit word divided • No operand required into an opcode, which specifies the instruction type and (specified by ‘—’) one or more operands, which further specify the All instructions are a single word, except for four operation of the instruction. double-word instructions. These instructions were The instruction set is highly orthogonal and is grouped made double-word to contain the required information into four basic categories: in 32 bits. In the second word, the 4 MSbs are ‘1’s. If this second word is executed as an instruction (by • Byte-oriented operations itself), it will execute as a NOP. • Bit-oriented operations All single-word instructions are executed in a single • Literal operations instruction cycle, unless a conditional test is true or the • Control operations program counter is changed as a result of the instruc- The PIC18 instruction set summary in Table26-2 lists tion. In these cases, the execution takes two instruction byte-oriented, bit-oriented, literal and control cycles with the additional instruction cycle(s) executed operations. Table26-1 shows the opcode field as a NOP. descriptions. The double-word instructions execute in two instruction Most byte-oriented instructions have three operands: cycles. 1. The file register (specified by ‘f’) One instruction cycle consists of four oscillator periods. 2. The destination of the result (specified by ‘d’) Thus, for an oscillator frequency of 4MHz, the normal 3. The accessed memory (specified by ‘a’) instruction execution time is 1μs. If a conditional test is true, or the program counter is changed as a result of The file register designator, ‘f’, specifies which file an instruction, the instruction execution time is 2 μs. register is to be used by the instruction. The destination Two-word branch instructions (if true) would take 3 μs. designator, ‘d’, specifies where the result of the Figure26-1 shows the general formats that the instruc- operation is to be placed. If ‘d’ is ‘0’, the result is placed tions can have. All examples use the convention ‘nnh’ in the WREG register. If ‘d’ is ‘1’, the result is placed in to represent a hexadecimal number. the file register specified in the instruction. The instruction set summary, shown in Table26-2, lists All bit-oriented instructions have three operands: the standard instructions recognized by the Microchip 1. The file register (specified by ‘f’) MPASMTM Assembler. 2. The bit in the file register (specified by ‘b’) Section26.1.1 “Standard Instruction Set” provides 3. The accessed memory (specified by ‘a’) a description of each instruction. The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register desig- nator, ‘f’, represents the number of the file in which the bit is located. © 2009 Microchip Technology Inc. DS39775C-page 365

PIC18F87J50 FAMILY TABLE 26-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h). f 12-bit register file address (000h to FFFh). This is the source address. s f 12-bit register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No Change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-Down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-Bit Table Pointer (points to a program memory location). TABLAT 8-Bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or Unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for Indirect Addressing of register files (source). s z 7-bit offset value for Indirect Addressing of register files (destination). d { } Optional argument. [text] Indicates Indexed Addressing. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer, expr. → Assigned to. < > Register bit field. ∈ In the set of. italics User-defined term (font is Courier New). DS39775C-page 366 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC © 2009 Microchip Technology Inc. DS39775C-page 367

PIC18F87J50 FAMILY TABLE 26-2: PIC18F87J50 FAMILY INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39775C-page 368 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 26-2: PIC18F87J50 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. © 2009 Microchip Technology Inc. DS39775C-page 369

PIC18F87J50 FAMILY TABLE 26-2: PIC18F87J50 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move Literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39775C-page 370 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 26.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) + k → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f) → dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ADDLW 15h mode whenever f ≤ 95 (5Fh). See Before Instruction Section26.2.3 “Byte-Oriented and W = 10h Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = 25h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). © 2009 Microchip Technology Inc. DS39775C-page 371

PIC18F87J50 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .AND. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) + (f) + (C) → dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read literal Process Write to GPR bank (default). ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: ANDLW 05Fh in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Before Instruction Section26.2.3 “Byte-Oriented and W = A3h Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = 03h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS39775C-page 372 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 d ∈ [0,1] Operation: if Carry bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (W) .AND. (f) → dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ’1’, then the program Description: The contents of W are ANDed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’ (default). incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a GPR bank (default). two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates Cycles: 1(2) in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section26.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to Words: 1 ‘n’ Data PC No No No No Cycles: 1 operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If Carry = 1; W = 02h PC = address (HERE + 12) REG = C2h If Carry = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39775C-page 373

PIC18F87J50 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b ≤ 7 Operation: if Negative bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: 0 → f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank (default). incremented to fetch the next instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Words: 1 Section26.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to Q Cycle Activity: ‘n’ Data PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No ‘n’ Data operation Before Instruction FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS39775C-page 374 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39775C-page 375

PIC18F87J50 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS39775C-page 376 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 Operation: (PC) + 2 + 2n → PC a ∈ [0,1] Status Affected: None Operation: 1 → f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected. PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the two-cycle instruction. GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section26.2.3 “Byte-Oriented and Decode Read literal Process Write to Bit-Oriented Instructions in Indexed ‘n’ Data PC Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah © 2009 Microchip Technology Inc. DS39775C-page 377

PIC18F87J50 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 0 ≤ b < 7 a ∈ [0,1] a ∈ [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set If ‘a’ is ‘0’ and the extended instruction is enabled, this instruction operates in set is enabled, this instruction operates in Indexed Literal Offset Addressing mode Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39775C-page 378 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b < 7 Operation: if Overflow bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (f<b>) → f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank (default). instruction, the new address will be PC + 2 + 2n. This instruction is then a If ‘a’ is ‘0’ and the extended instruction two-cycle instruction. set is enabled, this instruction operates in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Cycles: 1(2) Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Q1 Q2 Q3 Q4 Words: 1 Decode Read literal Process Write to PC Cycles: 1 ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: Before Instruction PORTC = 0110 0101 [65h] PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39775C-page 379

PIC18F87J50 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: if Zero bit is ‘1’, (PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS, k → PC<20:1>; Status Affected: None if s = 1, Encoding: 1110 0000 nnnn nnnn (W) → WS, Description: If the Zero bit is ‘1’, then the program (STATUS) → STATUSS, will branch. (BSR) → BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will have Encoding: incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk 7 0 instruction, the new address will be 2nd word(k<19:8>) 1111 k kkk kkkk kkkk 19 8 PC + 2 + 2n. This instruction is then a Description: Subroutine call of entire 2-Mbyte two-cycle instruction. memory range. First, return address Words: 1 (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, STATUS and BSR Q Cycle Activity: registers are also pushed into their If Jump: respective shadow registers, WS, Q1 Q2 Q3 Q4 STATUSS and BSRS. If ‘s’ = 0, no Decode Read literal Process Write to update occurs (default). Then, the ‘n’ Data PC 20-bit value ‘k’ is loaded into PC<20:1>. No No No No CALL is a two-cycle instruction. operation operation operation operation Words: 2 If No Jump: Cycles: 2 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process No Q1 Q2 Q3 Q4 ‘n’ Data operation Decode Read literal Push PC to Read literal ‘k’<7:0>, stack ’k’<19:8>, Example: HERE BZ Jump Write to PC Before Instruction No No No No PC = address (HERE) operation operation operation operation After Instruction If Zero = 1; PC = address (Jump) Example: HERE CALL THERE,1 If Zero = 0; Before Instruction PC = address (HERE + 2) PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39775C-page 380 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: 000h → WDT, Operation: 000h → f, 000h → WDT postscaler, 1 → Z 1 → TO, 1 → PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the Watchdog Timer. It also resets the If ‘a’ is ‘0’, the Access Bank is selected. postscaler of the WDT. Status bits, TO If ‘a’ is ‘1’, the BSR is used to select the and PD, are set. GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Cycles: 1 in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Decode No Process No Literal Offset Mode” for details. operation Data operation Words: 1 Example: CLRWDT Cycles: 1 Before Instruction Q Cycle Activity: WDT Counter = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write WDT Counter = 00h register ‘f’ Data register ‘f’ WDT Postscaler = 0 TO = 1 PD = 1 Example: CLRF FLAG_REG,1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h © 2009 Microchip Technology Inc. DS39775C-page 381

PIC18F87J50 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: f → dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank (default). instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank (default). mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Words: 1 Section26.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Cycles: 1(2) register ‘f’ Data destination Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h W = ECh Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL) DS39775C-page 382 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), Operation: (f) – (W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of the W by Description: Compares the contents of data memory performing an unsigned subtraction. location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are greater than the contents of WREG, then the fetched If the contents of ‘f’ are less than the instruction is discarded and a NOP is contents of W, then the fetched executed instead, making this a instruction is discarded and a NOP is two-cycle instruction. executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Note: 3 cycles if skip and followed Section26.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 Words: 1 Decode Read Process No Cycles: 1(2) register ‘f’ Data operation Note: 3 cycles if skip and followed If skip: by a 2-word instruction. Q1 Q2 Q3 Q4 Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process No If skip and followed by 2-word instruction: register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; PC = Address (LESS) Before Instruction If REG ≥ W; PC = Address (HERE) PC = Address (NLESS) W = ? After Instruction If REG > W; PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER) © 2009 Microchip Technology Inc. DS39775C-page 383

PIC18F87J50 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: If [W<3:0> > 9] or [DC = 1] then, a ∈ [0,1] (W<3:0>) + 6 → W<3:0>; else, Operation: (f) – 1 → dest (W<3:0>) → W<3:0> Status Affected: C, DC, N, OV, Z If [W<7:4> > 9] or [C = 1] then, Encoding: 0000 01da ffff ffff (W<7:4>) + 6 → W<7:4>, Description: Decrement register ‘f’. If ‘d’ is ‘0’, the C = 1; result is stored in W. If ‘d’ is ‘1’, the else, result is stored back in register ‘f’ (W<7:4>) → W<7:4> (default). Status Affected: C If ‘a’ is ‘0’, the Access Bank is selected. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Description: DAW adjusts the eight-bit value in W, resulting from the earlier addition of two If ‘a’ is ‘0’ and the extended instruction variables (each in packed BCD format) set is enabled, this instruction operates and produces a correct packed BCD in Indexed Literal Offset Addressing result. mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Words: 1 Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write Q Cycle Activity: register W Data W Q1 Q2 Q3 Q4 Decode Read Process Write to Example 1: DAW register ‘f’ Data destination Before Instruction W = A5h C = 0 Example: DECF CNT, 1, 0 DC = 0 Before Instruction After Instruction CNT = 01h W = 05h Z = 0 C = 1 After Instruction DC = 0 CNT = 00h Example 2: Z = 1 Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS39775C-page 384 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, Operation: (f) – 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is ‘0’, the next instruction If the result is not ‘0’, the next which is already fetched is discarded instruction which is already fetched is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing Section26.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Bit-Oriented Instructions in Indexed Section26.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT ≠ 0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP ≠ 0; PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39775C-page 385

PIC18F87J50 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0 ≤ k ≤ 1048575 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k → PC<20:1> a ∈ [0,1] Status Affected: None Operation: (f) + 1 → dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire 2-Mbyte memory incremented. If ‘d’ is ‘0’, the result is range. The 20-bit value ‘k’ is loaded into placed in W. If ‘d’ is ‘1’, the result is PC<20:1>. GOTO is always a two-cycle placed back in register ‘f’ (default). instruction. If ‘a’ is ‘0’, the Access Bank is selected. Words: 2 If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Cycles: 2 If ‘a’ is ‘0’ and the extended instruction Q Cycle Activity: set is enabled, this instruction operates Q1 Q2 Q3 Q4 in Indexed Literal Offset Addressing Decode Read literal No Read literal mode whenever f ≤ 95 (5Fh). See ‘k’<7:0>, operation ‘k’<19:8>, Section26.2.3 “Byte-Oriented and Write to PC Bit-Oriented Instructions in Indexed No No No No Literal Offset Mode” for details. operation operation operation operation Words: 1 Cycles: 1 Example: GOTO THERE Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 PC = Address (THERE) Decode Read Process Write to register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS39775C-page 386 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, Operation: (f) + 1 → dest, skip if result ≠ 0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’. (default) If the result is not ‘0’, the next If the result is ‘0’, the next instruction instruction which is already fetched is which is already fetched is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG ≠ 0; PC = Address (ZERO) PC = Address (NZERO) If CNT ≠ 0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) © 2009 Microchip Technology Inc. DS39775C-page 387

PIC18F87J50 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) .OR. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) .OR. (f) → dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: IORLW 35h mode whenever f ≤ 95 (5Fh). See Before Instruction Section26.2.3 “Byte-Oriented and W = 9Ah Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = BFh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS39775C-page 388 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0 ≤ f ≤ 2 Operands: 0 ≤ f ≤ 255 0 ≤ k ≤ 4095 d ∈ [0,1] a ∈ [0,1] Operation: k → FSRf Operation: f → dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to file select register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’ (default). Q Cycle Activity: Location ‘f’ can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 Decode Read literal Process Write If ‘a’ is ‘0’, the Access Bank is selected. ‘k’ MSB Data literal ‘k’ If ‘a’ is ‘1’, the BSR is used to select the MSB to GPR bank (default). FSRfH If ‘a’ is ‘0’ and the extended instruction Decode Read literal Process Write literal set is enabled, this instruction operates ‘k’ LSB Data ‘k’ to FSRfL in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Example: LFSR 2, 3ABh Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. FSR2H = 03h FSR2L = ABh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data W Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h © 2009 Microchip Technology Inc. DS39775C-page 389

PIC18F87J50 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0 ≤ f ≤ 4095 Operands: 0 ≤ k ≤ 255 s 0 ≤ f ≤ 4095 d Operation: k → BSR Operation: (f ) → f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffff s Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffff d of BSR<7:4> always remains ‘0’ Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Decode Read Process Write literal Either source or destination can be W literal ‘k’ Data ‘k’ to BSR (a useful special situation). MOVFF is particularly useful for Example: MOVLB 5 transferring a data memory location to a peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h After Instruction The MOVFF instruction cannot use the BSR Register = 05h PCL, TOSU, TOSH or TOSL as the destination register Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS39775C-page 390 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: k → W Operation: (W) → f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: MOVLW 5Ah in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See After Instruction Section26.2.3 “Byte-Oriented and W = 5Ah Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh © 2009 Microchip Technology Inc. DS39775C-page 391

PIC18F87J50 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x k → PRODH:PRODL Operation: (W) x (f) → PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried out 8-bit literal ‘k’. The 16-bit result is between the contents of W and the placed in PRODH:PRODL register pair. register file location ‘f’. The 16-bit result is PRODH contains the high byte. stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W is unchanged. W and ‘f’ are unchanged. None of the Status flags are affected. None of the Status flags are affected. Note that neither Overflow nor Carry is Note that neither Overflow nor Carry is possible in this operation. A Zero result possible in this operation. A Zero result is is possible but not detected. possible but not detected. Words: 1 If ‘a’ is ‘0’, the Access Bank is selected. If Cycles: 1 ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set Decode Read Process Write is enabled, this instruction operates in literal ‘k’ Data registers Indexed Literal Offset Addressing mode PRODH: whenever f ≤ 95 (5Fh). See PRODL Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: MULLW 0C4h Words: 1 Before Instruction W = E2h Cycles: 1 PRODH = ? Q Cycle Activity: PRODL = ? After Instruction Q1 Q2 Q3 Q4 W = E2h Decode Read Process Write PRODH = ADh register ‘f’ Data registers PRODL = 08h PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS39775C-page 392 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: No operation Operation: (f) + 1 → f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] © 2009 Microchip Technology Inc. DS39775C-page 393

PIC18F87J50 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC + 2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS39775C-page 394 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n → PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC + 2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC + 2 + 2n. This instruction is a Decode Start No No two-cycle instruction. reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to PC Flags* = Reset Value ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2) © 2009 Microchip Technology Inc. DS39775C-page 395

PIC18F87J50 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, Operation: k → W, 1 → GIE/GIEH or PEIE/GIEL; (TOS) → PC, if s = 1, PCLATU, PCLATH are unchanged (WS) → W, Status Affected: None (STATUSS) → STATUS, (BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers WS, Q1 Q2 Q3 Q4 STATUSS and BSRS are loaded into Decode Read Process POP PC their corresponding registers W, literal ‘k’ Data from stack, STATUS and BSR. If ‘s’ = 0, no update write to W of these registers occurs (default). No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS RETLW kn ; End of table W = WS BSR = BSRS STATUS = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn DS39775C-page 396 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (TOS) → PC; a ∈ [0,1] if s = 1, (WS) → W, Operation: (f<n>) → dest<n + 1>, (STATUSS) → STATUS, (f<7>) → C, (BSRS) → BSR, (C) → dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry flag. popped and the top of the stack (TOS) If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is loaded into the program counter. If is ‘1’, the result is stored back in register ‘s’= 1, the contents of the shadow ‘f’ (default). registers WS, STATUSS and BSRS are If ‘a’ is ‘0’, the Access Bank is selected. loaded into their corresponding If ‘a’ is ‘1’, the BSR is used to select the registers W, STATUS and BSR. If GPR bank (default). ‘s’ = 0, no update of these registers occurs (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 2 mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Q Cycle Activity: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 © 2009 Microchip Technology Inc. DS39775C-page 397

PIC18F87J50 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n + 1>, Operation: (f<n>) → dest<n – 1>, (f<7>) → dest<0> (f<0>) → C, (C) → dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘0’, the Access Bank is selected. register ‘f’ (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank (default). set is enabled, this instruction operates in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f ≤ 95 (5Fh). See set is enabled, this instruction operates Section26.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f ≤ 95 (5Fh). See Literal Offset Mode” for details. Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39775C-page 398 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: FFh → f Operation: (f<n>) → dest<n – 1>, Status Affected: None (f<0>) → dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank (default). placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f ≤ 95 (5Fh). See per the BSR value (default). Section26.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 © 2009 Microchip Technology Inc. DS39775C-page 399

PIC18F87J50 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: 00h → WDT, a ∈ [0,1] 0 → WDT postscaler, 1 → TO, Operation: (W) – (f) – (C) → dest 0 → PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored in is set. The Watchdog Timer and its W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’ (default). The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is selected. If with the oscillator stopped. ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction operates in Q Cycle Activity: Indexed Literal Offset Addressing mode Q1 Q2 Q3 Q4 whenever f ≤ 95 (5Fh). See Decode No Process Go to Section26.2.3 “Byte-Oriented and operation Data Sleep Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to TO = 1 † register ‘f’ Data destination PD = 0 Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39775C-page 400 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k – (W) → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) → dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the result Q Cycle Activity: is stored back in register ‘f’ (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read Process Write to If ‘a’ is ‘1’, the BSR is used to select the literal ‘k’ Data W GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction operates Before Instruction in Indexed Literal Offset Addressing W = 01h mode whenever f ≤ 95 (5Fh). See C = ? Section26.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 01h Literal Offset Mode” for details. C = 1 ; result is positive Z = 0 Words: 1 N = 0 Cycles: 1 Example 2: SUBLW 02h Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 W = 02h C = ? Decode Read Process Write to After Instruction register ‘f’ Data destination W = 00h C = 1 ; result is zero Example 1: SUBWF REG, 1, 0 Z = 1 Before Instruction N = 0 REG = 3 W = 2 Example 3: SUBLW 02h C = ? Before Instruction After Instruction W = 03h REG = 1 C = ? W = 2 After Instruction C = 1 ; result is positive Z = 0 W = FFh ; (2’s complement) N = 0 C = 0 ; result is negative Z = 0 Example 2: SUBWF REG, 0, 0 N = 1 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 © 2009 Microchip Technology Inc. DS39775C-page 401

PIC18F87J50 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>) → dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement Description: The upper and lower nibbles of register method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) REG = 35h C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39775C-page 402 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR)) → TABLAT, MEMORY(00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR)) → TABLAT, TBLPTR = 00A357h (TBLPTR) + 1 → TBLPTR; Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, Before Instruction (TBLPTR) – 1 → TBLPTR; TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY(01A357h) = 12h (TBLPTR) + 1 → TBLPTR, MEMORY(01A358h) = 34h (Prog Mem (TBLPTR)) → TABLAT After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR<0> = 0:Least Significant Byte of Program Memory Word TBLPTR<0> = 1:Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write Memory) TABLAT) © 2009 Microchip Technology Inc. DS39775C-page 403

PIC18F87J50 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT) → Holding Register, TBLPTR = 00A356h HOLDING REGISTER TBLPTR – No Change; (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT) → Holding Register, TABLAT = 55h (TBLPTR) + 1 → TBLPTR; TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT) → Holding Register, (00A356h) = 55h (TBLPTR) – 1 → TBLPTR; Example 2: TBLWT +*; if TBLWT+*, Before Instruction (TBLPTR) + 1 → TBLPTR, TABLAT = 34h (TABLAT) → Holding Register TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER (01389Bh) = 34h 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section5.0 “Memory Organization” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR<0> = 0: Least Significant Byte of Program Memory Word TBLPTR<0> = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register) DS39775C-page 404 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 a ∈ [0,1] Operation: (W) .XOR. k → W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to set is enabled, this instruction operates literal ‘k’ Data W in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: XORLW 0AFh Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Before Instruction Literal Offset Mode” for details. W = B5h After Instruction Words: 1 W = 1Ah Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT ≠ 00h, PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39775C-page 405

PIC18F87J50 FAMILY XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS39775C-page 406 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 26.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table26-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section26.2.2 “Extended Instruction instruction set, the PIC18F87J50 family of devices also Set”. The opcode field descriptions in Table26-1 (page provide an optional extension to the core CPU function- 366) apply to both the standard and extended PIC18 ality. The added features include eight additional instruction sets. instructions that augment Indirect and Indexed Addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction set these instructions directly in assembler. are enabled by default on unprogrammed devices. The syntax for these commands is Users must properly set or clear the XINST Configura- provided as a reference for users who may tion bit during programming to enable or disable these be reviewing code that has been features. generated by a compiler. The instructions in the extended set can all be classified as literal operations, which either manipulate 26.2.1 EXTENDED INSTRUCTION SYNTAX the File Select Registers, or use them for Indexed Most of the extended instructions use indexed argu- Addressing. Two of the instructions, ADDFSR and ments, using one of the File Select Registers and some SUBFSR, each have an additional special instantiation offset to specify a source or destination register. When for using FSR2. These versions (ADDULNK and an argument for an instruction serves as part of SUBULNK) allow for automatic return after execution. Indexed Addressing, it is enclosed in square brackets The extended instructions are specifically implemented (“[ ]”). This is done to indicate that the argument is used to optimize re-entrant program code (that is, code that as an index or offset. The MPASM™ Assembler will is recursive or that uses a software stack) written in flag an error if it determines that an index or offset value high-level languages, particularly C. Among other is not bracketed. things, they allow users working in high-level When the extended instruction set is enabled, brackets languages to perform certain operations on data are also used to indicate index arguments in structures more efficiently. These include: byte-oriented and bit-oriented instructions. This is in • dynamic allocation and deallocation of software addition to other changes in their syntax. For more stack space when entering and leaving details, see Section26.2.3.1 “Extended Instruction subroutines Syntax with Standard PIC18 Commands”. • Function Pointer invocation Note: In the past, square brackets have been • Software Stack Pointer manipulation used to denote optional arguments in the • manipulation of variables located in a software PIC18 and earlier instruction sets. In this stack text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 26-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None Decrement FSR2 SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None Return © 2009 Microchip Technology Inc. DS39775C-page 407

PIC18F87J50 FAMILY 26.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2, Operation: FSR(f) + k → FSR(f) (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. Q Cycle Activity: The instruction takes two cycles to Q1 Q2 Q3 Q4 execute; a NOP is performed during the second cycle. Decode Read Process Write to literal ‘k’ Data FSR This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates Example: ADDFSR 2, 23h only on FSR2. Before Instruction Words: 1 FSR2 = 03FFh Cycles: 2 After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS39775C-page 408 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY CALLW Subroutine Call using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0 ≤ z ≤ 127 s 0 ≤ f ≤ 4095 Operation: (PC + 2) → TOS, d (W) → PCL, Operation: ((FSR2) + z ) → f s d (PCLATH) → PCH, Status Affected: None (PCLATU) → PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffff d Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’, in the first word, to the value s latched into PCH and PCU, of FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘fd’ in the second word. Both addresses new next instruction is fetched. can be anywhere in the 4096-byte data space (000h to FFFh). Unlike CALL, there is no option to update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an Indirect Addressing register, the Q1 Q2 Q3 Q4 value returned will be 00h. Decode Read Push PC to No Words: 2 WREG stack operation Cycles: 2 No No No No operation operation operation operation Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Before Instruction Decode No No Write PC = address (HERE) operation operation register ‘f’ PCLATH = 10h No dummy (dest) PCLATU = 00h W = 06h read After Instruction PC = 001006h TOS = address (HERE + 2) Example: MOVSF [05h], REG2 PCLATH = 10h PCLATU = 00h Before Instruction W = 06h FSR2 = 80h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h © 2009 Microchip Technology Inc. DS39775C-page 409

PIC18F87J50 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255 0 ≤ z ≤ 127 d Operation: k → (FSR2), Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1 → FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1111 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. Description The contents of the source register are FSR2 is decremented by 1 after the moved to the destination register. The operation. addresses of the source and destination registers are determined by adding the This instruction allows users to push 7-bit literal offsets ‘z ’ or ‘z ’, values onto a software stack. s d respectively, to the value of FSR2. Both Words: 1 registers can be located anywhere in the 4096-byte data memory space Cycles: 1 (000h to FFFh). Q Cycle Activity: The MOVSS instruction cannot use the Q1 Q2 Q3 Q4 PCL, TOSU, TOSH or TOSL as the Decode Read ‘k’ Process Write to destination register. data destination If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. If the Example: PUSHL 08h resultant destination address points to Before Instruction an Indirect Addressing register, the FSR2H:FSR2L = 01ECh instruction will execute as a NOP. Memory (01ECh) = 00h Words: 2 After Instruction Cycles: 2 FSR2H:FSR2L = 01EBh Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS39775C-page 410 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2, Operation: FSRf – k → FSRf (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified contents of the FSR2. A RETURN is then by ‘f’. executed by loading the PC with the Words: 1 TOS. Cycles: 1 The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during the second cycle. Q1 Q2 Q3 Q4 Decode Read Process Write to This may be thought of as a special case register ‘f’ Data destination of the SUBFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Words: 1 Example: SUBFSR 2, 23h Cycles: 2 Before Instruction Q Cycle Activity: FSR2 = 03FFh Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to FSR2 = 03DCh register ‘f’ Data destination No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) © 2009 Microchip Technology Inc. DS39775C-page 411

PIC18F87J50 FAMILY 26.2.3 BYTE-ORIENTED AND 26.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file Note: Enabling the PIC18 instruction set exten- register argument ‘f’ in the standard byte-oriented and sion may cause legacy applications to bit-oriented commands is replaced with the literal offset behave erratically or fail entirely. value ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing (Section5.6.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within the brackets, will the standard PIC18 instruction set are interpreted. generate an error in the MPASM Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is either as a location in the Access Bank (a = 0) or in a never specified; it will automatically be assumed to be GPR bank designated by the BSR (a = 1). When the ‘0’. This is in contrast to standard operation (extended extended instruction set is enabled and a = 0, however, instruction set disabled), when ‘a’ is set on the basis of a file register argument of 5Fh or less is interpreted as the target address. Declaring the Access RAM bit in an offset from the pointer value in FSR2 and not as a this mode will also generate an error in the MPASM literal address. For practical purposes, this means that Assembler. all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bit-oriented The destination argument ‘d’ functions as before. instructions, or almost half of the core PIC18 instruc- In the latest versions of the MPASM Assembler, tions – may behave differently when the extended language support for the extended instruction set must instruction set is enabled. be explicitly invoked. This is done with either the When the content of FSR2 is 00h, the boundaries of the command line option, /y, or the PE directive in the Access RAM are essentially remapped to their original source listing. values. This may be useful in creating 26.2.4 CONSIDERATIONS WHEN backward-compatible code. If this technique is used, it ENABLING THE EXTENDED may be necessary to save the value of FSR2 and INSTRUCTION SET restore it when moving back and forth between C and assembly routines in order to preserve the Stack It is important to note that the extensions to the instruc- Pointer. Users must also keep in mind the syntax tion set may not be beneficial to all users. In particular, requirements of the extended instruction set (see users who are not writing code that uses a software Section26.2.3.1 “Extended Instruction Syntax with stack may not benefit from using the extensions to the Standard PIC18 Commands”). instruction set. Although the Indexed Literal Offset mode can be very Additionally, the Indexed Literal Offset Addressing useful for dynamic stack and pointer manipulation, it mode may create issues with legacy applications can also be very annoying if a simple arithmetic opera- written to the PIC18 assembler. This is because tion is carried out on the wrong register. Users who are instructions in the legacy code may attempt to address accustomed to the PIC18 programming must keep in registers in the Access Bank below 5Fh. Since these mind that, when the extended instruction set is addresses are interpreted as literal offsets to FSR2 enabled, register addresses of 5Fh or less are used for when the instruction set extension is enabled, the Indexed Literal Offset Addressing. application may read or write to the wrong data Representative examples of typical byte-oriented and addresses. bit-oriented instructions in the Indexed Literal Offset When porting an application to the PIC18F87J10 fam- mode are provided on the following page to show how ily, it is very important to consider the type of code. A execution is affected. The operand conditions shown in large, re-entrant application that is written in C and the examples are applicable to all instructions of these would benefit from efficient compilation will do well types. when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39775C-page 412 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 Operands: 0 ≤ f ≤ 95 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ Cycles: 1 is ‘1’, the result is stored back in register ‘f’ (default). Q Cycle Activity: Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1 register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Contents Example: ADDWF [OFST],0 of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction Set Indexed SETF W = 37h (Indexed Literal Offset mode) Contents of 0A2Ch = 20h Syntax: SETF [k] Operands: 0 ≤ k ≤ 95 Operation: FFh → ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh © 2009 Microchip Technology Inc. DS39775C-page 413

PIC18F87J50 FAMILY 26.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set for the PIC18F87J10 family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is ‘0’, disabling the extended instruction set and Indexed Literal Offset Addressing. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: • A menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project • A command line option • A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompany- ing their development systems for the appropriate information. DS39775C-page 414 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 27.0 DEVELOPMENT SUPPORT 27.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- • Integrated Development Environment controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software operating system-based application that contains: • Assemblers/Compilers/Linkers • A single graphical interface to all debugging tools - MPASMTM Assembler - Simulator - MPLAB C18 and MPLAB C30 C Compilers - Programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) • Simulators • A full-featured editor with color-coded context - MPLAB SIM Software Simulator • A multiple project manager • Emulators • Customizable data windows with direct edit of contents - MPLAB ICE 2000 In-Circuit Emulator • High-level source code debugging - MPLAB REAL ICE™ In-Circuit Emulator • Visual device initializer for easy register • In-Circuit Debugger initialization - MPLAB ICD 2 • Mouse over variable inspection • Device Programmers • Drag and drop variables from source to watch - PICSTART® Plus Development Programmer windows - MPLAB PM3 Device Programmer • Extensive on-line help - PICkit™ 2 Development Programmer • Integration of select third party tools, such as • Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR Boards and Evaluation Kits C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2009 Microchip Technology Inc. DS39775C-page 415

PIC18F87J50 FAMILY 27.2 MPASM Assembler 27.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: • Support for the entire dsPIC30F instruction set • Integration into MPLAB IDE projects • Support for fixed-point and floating-point data • User-defined macros to streamline • Command line interface assembly code • Rich directive set • Conditional assembly for multi-purpose source files • Flexible macro language • Directives that allow complete control over the • MPLAB IDE compatibility assembly process 27.6 MPLAB SIM Software Simulator 27.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulat- ing the PIC MCUs and dsPIC® DSCs on an instruction The MPLAB C18 and MPLAB C30 Code Development level. On any given instruction, the data areas can be Systems are complete ANSI C compilers for examined or modified and stimuli can be applied from Microchip’s PIC18 and PIC24 families of microcontrol- a comprehensive stimulus controller. Registers can be lers and the dsPIC30 and dsPIC33 family of digital sig- logged to files for further run-time analysis. The trace nal controllers. These compilers provide powerful buffer and logic analyzer display extend the power of integration capabilities, superior code optimization and the simulator to record and track program execution, ease of use not found with other compilers. actions on I/O, most peripherals and internal registers. For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and debugger. MPLAB C30 CCompilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator 27.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside MPLIB Object Librarian of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS39775C-page 416 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 27.7 MPLAB ICE 2000 27.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes microcontrollers. Software control of the MPLAB ICE the in-circuit debugging capability built into theFlash 2000 In-Circuit Emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers cost- editing, building, downloading and source debugging effective, in-circuit Flash debugging from the graphical from a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step- ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB ICE 2000 In-Circuit Emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 27.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for simple, unified application. maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various 27.8 MPLAB REAL ICE In-Circuit package types. The ICSP™ cable assembly is included Emulator System as a standard item. In Stand-Alone mode, the MPLAB MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set Microchip Flash DSC® and MCU devices. It debugs and code protection in this mode. The MPLAB PM3 programs PIC® and dsPIC® Flash microcontrollers with connects to the host PC via an RS-232 or USB cable. the easy-to-use, powerful graphical user interface of the The MPLAB PM3 has high-speed communications and MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large included with each kit. memory devices and incorporates an SD/MMC card for file storage and secure data applications. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, low- voltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2009 Microchip Technology Inc. DS39775C-page 417

PIC18F87J50 FAMILY 27.11 PICSTART Plus Development 27.13 Demonstration, Development and Programmer Evaluation Boards The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func- Integrated Development Environment software makes tional systems. Most boards include prototyping areas for using the programmer simple and efficient. The adding custom circuitry and provide application firmware PICSTART Plus Development Programmer supports and source code for examination and modification. most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs, Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232 PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional The PICSTART Plus Development Programmer is CE EEPROM memory. compliant. The demonstration and development boards can be used in teaching environments, for prototyping custom 27.12 PICkit 2 Development Programmer circuits and for learning about various microcontroller The PICkit™ 2 Development Programmer is a low-cost applications. programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ demon- an easy-to-use interface for programming many of stration/development board series of circuits, Microchip Microchip’s baseline, mid-range and PIC18F families of has a line of evaluation kits and demonstration software Flash memory microcontrollers. The PICkit 2 Starter Kit for analog filter design, KEELOQ® security ICs, CAN, includes a prototyping development board, twelve IrDA®, PowerSmart® battery management, SEEVAL® sequential lessons, software and HI-TECH’s PICC™ evaluation system, Sigma-Delta ADC, flow rate Lite C compiler, and is designed to help get up to speed sensing, plus many more. quickly using PIC® microcontrollers. The kit provides Check the Microchip web page (www.microchip.com) everything needed to program, evaluate and develop and the latest “Product Selector Guide” (DS00148) for applications using Microchip’s powerful, mid-range the complete list of demonstration, development and Flash memory family of microcontrollers. evaluation kits. DS39775C-page 418 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 28.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD)...........................................-0.3V to 6.0V Voltage on any combined digital and analog pin with respect to VSS (except VDD)........................-0.3V to (VDD + 0.3V) Voltage on VDDCORE with respect to VSS...................................................................................................-0.3V to 2.75V Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V Voltage on VUSB with respect to VSS...................................................................................(VDD – 0.3V) to (VDD + 0.3V) Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Maximum output current sunk by any PORTB and PORTC I/O pin........................................................................25mA Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pin............................................................8mA Maximum output current sunk by any PORTA, PORTF, PORTG and PORTH I/O pin.............................................2mA Maximum output current sourced by any PORTB and PORTC I/O pin..................................................................25mA Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pin.......................................................8mA Maximum output current sourced by any PORTA, PORTF, PORTG and PORTH I/O pin........................................2mA Maximum current sunk by all ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS39775C-page 419

PIC18F87J50 FAMILY FIGURE 28-1: PIC18F87J50 FAMILY VDD FREQUENCY GRAPH (INDUSTRIAL) 4.0V 3.6V 3.5V 3.0V (Note 1) )D PIC18F87J50 Family D V 2.5V ( e g 2.35V a t 2.0V ol V 8 MHz 48 MHz 0 Frequency Note 1: When the USB module is enabled, VUSB and VDD should be connected together and provided 3.0V-3.6V while VDDCORE must be ≥ 2.45V. When the core regulator is enabled and VDD is ≥ 3.0V, it will always regulate to ≥ 2.45V. When the USB module is not enabled, VUSB and VDD should still be connected together, but the wider limits shaded in gray apply. FIGURE 28-2: PIC18F87J50 FAMILY VDDCORE FREQUENCY GRAPH (INDUSTRIAL)(1) 3.00V 2.75V 2.75V )E 2.50V PIC18F87J50 Family 2.45V(2) R O 2.35V C D 2.25V D V e ( 2.00V g a t ol V 8 MHz 48 MHz 0 Frequency Note 1: VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD. 2: When the USB module is enabled, VUSB and VDD should be connected together and provided 3.0V-3.6V while VDDCORE must be ≥ 2.45V. When the core regulator is enabled and VDD is ≥ 3.0V, it will always regulate to ≥ 2.45V. When the USB module is not enabled, VUSB and VDD should still be connected together, but the wider limits shaded in gray apply. DS39775C-page 420 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 28.1 DC Characteristics: Supply Voltage PIC18F87J50 Family (Industrial) PIC18F87J50 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage VDDCORE — 3.6 V ENVREG = 0 2.0 — 3.6 V ENVREG = 1 D001B VDDCORE External Supply for 2.0 — 2.75 V ENVREG = 0 Microcontroller Core D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V D001D AVSS Analog Ground Potential VSS – 0.3 — VSS + 0.3 V D001E VUSB USB Supply Voltage 3.0 3.3 3.6 V USB module enabled(2) D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See Section4.3 “Power-on to ensure internal Reset (POR)” for details Power-on Reset signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section4.3 “Power-on to ensure internal Reset (POR)” for details Power-on Reset signal D005 VBOR Brown-out Reset Voltage — 1.8 — V Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: VUSB should be connected to VDD. When the USB module is disabled, the limits of Figure28-1 apply. © 2009 Microchip Technology Inc. DS39775C-page 421

PIC18F87J50 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F87J50 Family (Industrial) PIC18F87J50 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) All devices 0.5 1.4 μA -40°C VDD = 2.0V(4), 0.5 1.4 μA +25°C VDDCORE = 2.0V 5.5 10.2 μA +85°C (Sleep mode) All devices 0.6 1.5 μA -40°C VDD = 2.5V(4), 0.6 1.5 μA +25°C VDDCORE = 2.5V 6.8 12.6 μA +85°C (Sleep mode) All devices 2.9 7 μA -40°C VDD = 3.3V(5) 3.6 7 μA +25°C (Sleep mode) 9.6 19 μA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (USB module, WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled unless otherwise specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD), REGSLP = 1. 6: This is the module differential current when the USB module is enabled and clocked at 48MHz, but with no USB cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be much higher (see Section22.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode (USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to the USB 2.0 specifications, and therefore, may be as low as 900Ω during Idle conditions. DS39775C-page 422 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) PIC18F87J50 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 5 14.2 μA -40°C VDD = 2.0V, 5.5 14.2 μA +25°C VDDCORE = 2.0V(4) 10 19.0 μA +85°C All devices 6.8 16.5 μA -40°C FOSC = 31kHz VDD = 2.5V, 7.6 16.5 μA +25°C VDDCORE = 2.5V(4) (RC_RUN mode, 14 22.4 μA +85°C internal oscillator source) All devices 37 84 μA -40°C 51 84 μA +25°C VDD = 3.3V(5) 72 108 μA +85°C All devices 0.43 0.82 mA -40°C VDD = 2.0V, 0.47 0.82 mA +25°C VDDCORE = 2.0V(4) 0.52 0.95 mA +85°C All devices 0.52 0.98 mA -40°C FOSC = 1MHz VDD = 2.5V, 0.57 0.98 mA +25°C (RC_RUN mode, VDDCORE = 2.5V(4) 0.63 1.10 mA +85°C internal oscillator source) All devices 0.59 0.96 mA -40°C 0.65 0.96 mA +25°C VDD = 3.3V(5) 0.72 1.18 mA +85°C All devices 0.88 1.45 mA -40°C VDD = 2.0V, 1.0 1.45 mA +25°C VDDCORE = 2.0V(4) 1.1 1.58 mA +85°C All devices 1.2 1.72 mA -40°C FOSC = 4MHz VDD = 2.5V, 1.3 1.72 mA +25°C (RC_RUN mode, VDDCORE = 2.5V(4) 1.4 1.85 mA +85°C internal oscillator source) All devices 1.3 2.87 mA -40°C 1.4 2.87 mA +25°C VDD = 3.3V(5) 1.5 2.96 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (USB module, WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled unless otherwise specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD), REGSLP = 1. 6: This is the module differential current when the USB module is enabled and clocked at 48MHz, but with no USB cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be much higher (see Section22.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode (USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to the USB 2.0 specifications, and therefore, may be as low as 900Ω during Idle conditions. © 2009 Microchip Technology Inc. DS39775C-page 423

PIC18F87J50 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) PIC18F87J50 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2) All devices 3 9.4 μA -40°C VDD = 2.0V, 3.3 9.4 μA +25°C VDDCORE = 2.0V(4) 8.5 17.2 μA +85°C All devices 4 10.5 μA -40°C FOSC = 31kHz VDD = 2.5V, 4.3 10.5 μA +25°C VDDCORE = 2.5V(4) (RC_IDLE mode, 10.3 19.5 μA +85°C internal oscillator source) All devices 34 82 μA -40°C 48 82 μA +25°C VDD = 3.3V(5) 69 105 μA +85°C All devices 0.33 0.75 mA -40°C VDD = 2.0V, 0.37 0.75 mA +25°C VDDCORE = 2.0V(4) 0.41 0.84 mA +85°C All devices 0.39 0.78 mA -40°C FOSC = 1MHz VDD = 2.5V, 0.42 0.78 mA +25°C (RC_IDLE mode, VDDCORE = 2.5V(4) 0.47 0.91 mA +85°C internal oscillator source) All devices 0.43 0.82 mA -40°C 0.48 0.82 mA +25°C VDD = 3.3V(5) 0.54 0.95 mA +85°C All devices 0.53 0.98 mA -40°C VDD = 2.0V, 0.57 0.98 mA +25°C VDDCORE = 2.0V(4) 0.61 1.12 mA +85°C All devices 0.63 1.14 mA -40°C FOSC = 4MHz VDD = 2.5V, 0.67 1.14 mA +25°C (RC_IDLE mode, VDDCORE = 2.5V(4) 0.72 1.25 mA +85°C internal oscillator source) All devices 0.70 1.27 mA -40°C 0.76 1.27 mA +25°C VDD = 3.3V(5) 0.82 1.45 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (USB module, WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled unless otherwise specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD), REGSLP = 1. 6: This is the module differential current when the USB module is enabled and clocked at 48MHz, but with no USB cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be much higher (see Section22.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode (USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to the USB 2.0 specifications, and therefore, may be as low as 900Ω during Idle conditions. DS39775C-page 424 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) PIC18F87J50 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2) All devices 0.17 0.35 mA -40°C VDD = 2.0V, 0.18 0.35 mA +25°C VDDCORE = 2.0V(4) 0.20 0.42 mA +85°C All devices 0.29 0.52 mA -40°C FOSC = 1MHZ VDD = 2.5V, 0.31 0.52 mA +25°C (PRI_RUN mode, VDDCORE = 2.5V(4) 0.34 0.61 mA +85°C EC oscillator) All devices 0.59 1.1 mA -40°C 0.44 0.85 mA +25°C VDD = 3.3V(5) 0.42 0.85 mA +85°C All devices 0.70 1.25 mA -40°C VDD = 2.0V, 0.75 1.25 mA +25°C VDDCORE = 2.0V(4) 0.79 1.36 mA +85°C All devices 1.10 1.7 mA -40°C FOSC = 4MHz VDD = 2.5V, 1.10 1.7 mA +25°C (PRI_RUN mode, VDDCORE = 2.5V(4) 1.12 1.82 mA +85°C EC oscillator) All devices 1.55 1.95 mA -40°C 1.47 1.89 mA +25°C VDD = 3.3V(5) 1.54 1.92 mA +85°C All devices 9.9 14.8 mA -40°C VDD = 2.5V, 9.5 14.8 mA +25°C VDDCORE = 2.5V(4) 10.1 15.2 mA +85°C FOSC = 48MHZ (PRI_RUN mode, All devices 13.3 23.2 mA -40°C EC oscillator) 12.2 22.7 mA +25°C VDD = 3.3V(5) 12.1 22.7 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (USB module, WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled unless otherwise specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD), REGSLP = 1. 6: This is the module differential current when the USB module is enabled and clocked at 48MHz, but with no USB cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be much higher (see Section22.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode (USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to the USB 2.0 specifications, and therefore, may be as low as 900Ω during Idle conditions. © 2009 Microchip Technology Inc. DS39775C-page 425

PIC18F87J50 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) PIC18F87J50 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2) All devices 4.5 5.2 mA -40°C VDD = 2.5V, 4.4 5.2 mA +25°C VDDCORE = 2.5V(4) 4.5 5.2 mA +85°C FOSC = 4MHZ. 16 MHz internal All devices 5.7 6.7 mA -40°C (PRI_RUN HSPLL mode) 5.5 6.3 mA +25°C VDD = 3.3V(5) 5.3 6.3 mA +85°C All devices 10.8 13.5 mA -40°C VDD = 2.5V, 10.8 13.5 mA +25°C VDDCORE = 2.5V(4) 9.9 13.0 mA +85°C FOSC = 12MHZ, 48 MHz internal All devices 13.4 24.1 mA -40°C (PRI_RUN HSPLL mode) 12.3 20.2 mA +25°C VDD = 3.3V(5) 11.2 19.5 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (USB module, WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled unless otherwise specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD), REGSLP = 1. 6: This is the module differential current when the USB module is enabled and clocked at 48MHz, but with no USB cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be much higher (see Section22.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode (USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to the USB 2.0 specifications, and therefore, may be as low as 900Ω during Idle conditions. DS39775C-page 426 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) PIC18F87J50 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2) All devices 0.10 0.26 mA -40°C VDD = 2.0V, 0.07 0.18 mA +25°C VDDCORE = 2.0V(4) 0.09 0.22 mA +85°C All devices 0.25 0.48 mA -40°C FOSC = 1MHz VDD = 2.5V, 0.13 0.30 mA +25°C (PRI_IDLE mode, VDDCORE = 2.5V(4) 0.10 0.26 mA +85°C EC oscillator) All devices 0.45 0.68 mA -40°C 0.26 0.45 mA +25°C VDD = 3.3V(5) 0.30 0.54 mA +85°C All devices 0.36 0.60 mA -40°C VDD = 2.0V, 0.33 0.56 mA +25°C VDDCORE = 2.0V(4) 0.35 0.56 mA +85°C All devices 0.52 0.81 mA -40°C FOSC = 4MHz VDD = 2.5V, 0.45 0.70 mA +25°C (PRI_IDLE mode, VDDCORE = 2.5V(4) 0.46 0.70 mA +85°C EC oscillator) All devices 0.80 1.15 mA -40°C 0.66 0.98 mA +25°C VDD = 3.3V(5) 0.65 0.98 mA +85°C All devices 5.2 6.5 mA -40°C VDD = 2.5V, 4.9 5.9 mA +25°C VDDCORE = 2.5V(4) 3.4 4.5 mA +85°C FOSC = 48MHz (PRI_IDLE mode, All devices 6.2 12.4 mA -40°C EC oscillator) 5.9 11.5 mA +25°C VDD = 3.3V(5) 5.8 11.5 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (USB module, WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled unless otherwise specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD), REGSLP = 1. 6: This is the module differential current when the USB module is enabled and clocked at 48MHz, but with no USB cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be much higher (see Section22.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode (USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to the USB 2.0 specifications, and therefore, may be as low as 900Ω during Idle conditions. © 2009 Microchip Technology Inc. DS39775C-page 427

PIC18F87J50 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) PIC18F87J50 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2) All devices 18 35 µA -40°C VDD = 2.0V, 19 35 µA +25°C VDDCORE = 2.0V(4) 28 49 µA +85°C All devices 20 45 µA -40°C FOSC = 32kHz(3) VDD = 2.5V, 21 45 µA +25°C (SEC_RUN mode, VDDCORE = 2.5V(4) 32 61 µA +85°C Timer1 as clock) All devices 0.06 0.11 mA -40°C 0.07 0.11 mA +25°C VDD = 3.3V(5) 0.09 0.15 mA +85°C All devices 14 28 µA -40°C VDD = 2.0V, 15 28 µA +25°C VDDCORE = 2.0V(4) 24 43 µA +85°C All devices 15 31 µA -40°C FOSC = 32kHz(3) VDD = 2.5V, 16 31 µA +25°C (SEC_IDLE mode, VDDCORE = 2.5V(4) 27 50 µA +85°C Timer1 as clock) All devices 0.05 0.10 mA -40°C 0.06 0.10 mA +25°C VDD = 3.3V(5) 0.08 0.14 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (USB module, WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled unless otherwise specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD), REGSLP = 1. 6: This is the module differential current when the USB module is enabled and clocked at 48MHz, but with no USB cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be much higher (see Section22.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode (USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to the USB 2.0 specifications, and therefore, may be as low as 900Ω during Idle conditions. DS39775C-page 428 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) PIC18F87J50 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Module Differential Currents (ΔIWDT, ΔIOSCB, ΔIAD, ΔIUSB) D022 Watchdog Timer 2.1 7.0 μA -40°C (ΔIWDT) 2.2 7.0 μA +25°C VDDVCDODR E= =2 .20.V0,V(4) 4.3 9.5 μA +85°C 3.0 8.0 μA -40°C VDD = 2.5V, 3.1 8.0 μA +25°C VDDCORE = 2.5V(4) 5.5 10.4 μA +85°C 5.9 12.1 μA -40°C 6.2 12.1 μA +25°C VDD = 3.3V 6.9 13.6 μA +85°C D025 Timer1 Oscillator 14 24 μA -40°C (ΔIOSCB) 15 24 μA +25°C VDDVCDODR E= =2 .20.V0,V (4) 32kHz on Timer1(3) 23 36 μA +85°C 17 26 μA -40°C 18 26 μA +25°C VDDVCDODR E= =2 .25.V5,V(4) 32kHz on Timer1(3) 25 38 μA +85°C 19 35 μA -40°C 21 35 μA +25°C VDD = 3.3V 32kHz on Timer1(3) 28 44 μA +85°C D026 A/D Converter 3.0 10.0 μA VDD = 2.0V, (ΔIAD) -40°C to +85°C VDDCORE = 2.0V(4) 3.0 10.0 μA VDD = 2.5V, A/D on, not converting -40°C to +85°C VDDCORE = 2.5V(4) 3.2 11.0 μA -40°C to +85°C VDD = 3.3V D027 USB Module 1.5 3.2 mA -40°C USB enabled(6), no cable (ΔIUSB) 1.5 3.2 mA +25°C VUSB = 3.3V connected Traffic makes a large 1.5 3.2 mA VDD = 3.3V(5) +85°C difference (see Section22.6.4). Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (USB module, WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled unless otherwise specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD), REGSLP = 1. 6: This is the module differential current when the USB module is enabled and clocked at 48MHz, but with no USB cable attached. When the USB cable is attached or data is being transmitted, the current consumption may be much higher (see Section22.6.4 “USB Transceiver Current Consumption”). During USB Suspend mode (USBEN = 1, SUSPND = 1, bus in Idle state), the USB module current will be dominated by the D+ or D- pull-up resistor. The integrated pull-up resistors use “resistor switching” according to the resistor_ecn supplement to the USB 2.0 specifications, and therefore, may be as low as 900Ω during Idle conditions. © 2009 Microchip Technology Inc. DS39775C-page 429

PIC18F87J50 FAMILY 28.3 DC Characteristics:PIC18F87J50 Family (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage All I/O ports: D030 with TTL buffer VSS 0.15 VDD V D031 with Schmitt Trigger buffer VSS 0.2 VDD V D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V EC, ECPLL modes D034 T13CKI VSS 0.3 V VIH Input High Voltage I/O ports with analog functions: D040 with TTL buffer 0.25 VDD + 0.8V VDD V VDD < 3.3V D041 with Schmitt Trigger buffer 0.8 VDD VDD V Digital-only I/O ports: Dxxx with TTL buffer 0.25 VDD + 0.8V 5.5 V VDD < 3.3V DxxxA 2.0 5.5 V 3.3V ≤ VDD ≤ 3.6V Dxxx with Schmitt Trigger buffer 0.8 VDD 5.5 V D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC, ECPLL modes D044 T13CKI 1.6 VDD V IIL Input Leakage Current(1,2) D060 I/O ports — ±1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR — ±1 μA Vss ≤ VPIN ≤ VDD D063 OSC1 — ±5 μA Vss ≤ VPIN ≤ VDD IPU Weak Pull-up Current D070 IPURB PORTB, PORTD, PORTE, and 80 400 μA VDD = 3.3V, VPIN = VSS PORTJ(3) weak pull-up current Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2: Negative current is defined as current sourced by the pin. 3: Only available in 80-pin devices. DS39775C-page 430 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 28.3 DC Characteristics:PIC18F87J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O ports: PORTA, PORTF, PORTG, — 0.4 V IOL = 2 mA, VDD = 3.3V, PORTH(3) -40°C to +85°C PORTD, PORTE, PORTJ(3) — 0.4 V IOL = 3.4 mA, VDD = 3.3V, -40°C to +85°C PORTB, PORTC — 0.4 V IOL = 3.4 mA, VDD = 3.3V, -40°C to +85°C D083 OSC2/CLKO — 0.4 V IOL = 1.6 mA, VDD = 3.3V, (EC, ECPLL modes) -40°C to +85°C VOH Output High Voltage D090 I/O ports: V PORTA, PORTF, PORTG, 2.4 — V IOH = -2 mA, VDD = 3.3V, PORTH(3) -40°C to +85°C PORTD, PORTE, PORTJ(3) 2.4 — V IOH = -2 mA, VDD = 3.3V, -40°C to +85°C PORTB, PORTC 2.4 — V IOH = -2 mA, VDD = 3.3V, -40°C to +85°C D092 OSC2/CLKO 2.4 — V IOH = -1 mA, VDD = 3.3V, (INTOSC, EC, ECPLL modes) -40°C to +85°C Capacitive Loading Specs on Output Pins D100(3) COSC2 OSC2 pin — 15 pF In HS mode when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 — 50 pF To meet the AC Timing Specifications D102 CB SCLx, SDAx — 400 pF I2C™ Specification Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2: Negative current is defined as current sourced by the pin. 3: Only available in 80-pin devices. © 2009 Microchip Technology Inc. DS39775C-page 431

PIC18F87J50 FAMILY TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym Characteristic Min Typ† Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 10K — — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating voltage D133A TIW Self-Timed Write Cycle Time — 2.8 — ms D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D135 IDDP Supply Current during — 3 14 mA Programming D1xxx TWE Writes per Erase Cycle — — 1 Per one physical-word address † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS39775C-page 432 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 28-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — AVDD – 1.5 V VIRV Internal Reference Voltage — ±1.2(2) — V ±1.2% D302 CMRR Common Mode Rejection Ratio 55 — — dB 300 TRESP Response Time(1) — 150 400 ns 301 TMC2OV Comparator Mode Change to — — 10 μs Output Valid Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. 2: Tolerance is ±1.2%. TABLE 28-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb D312 VRUR Unit Resistor Value (R) — 2k — Ω 310 TSET Settling Time(1) — — 10 μs Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 bits transition from ‘0000’ to ‘1111’. TABLE 28-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. VRGOUT Regulator Output Voltage 2.45 2.5 — V VDD, ENVREG = 3.0V CEFC External Filter Capacitor Value 4.7 10 — μF Capacitor must be low-ESR © 2009 Microchip Technology Inc. DS39775C-page 433

PIC18F87J50 FAMILY TABLE 28-5: USB MODULE SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D313 VUSB USB Voltage 3.0 — 3.6 V Voltage on VUSB pin must be in this range for proper USB operation D314 IIL Input Leakage on pin — — ±1 μA VSS < VPIN < VDD pin at high impedance D315 VILUSB Input Low Voltage for USB — — 0.8 V For VUSB range Buffer D316 VIHUSB Input High Voltage for USB 2.0 — — V For VUSB range Buffer D318 VDIFS Differential Input Sensitivity — — 0.2 V The difference between D+ and D- must exceed this value while VCM is met D319 VCM Differential Common Mode 0.8 — 2.5 V Range D320 ZOUT Driver Output Impedance(1) 28 — 44 Ω D321 VOL Voltage Output Low 0.0 — 0.3 V 1.5 kΩ load connected to 3.6V D322 VOH Voltage Output High 2.8 — 3.6 V 1.5 kΩ load connected to ground Note 1: The D+ and D- signal lines have built-in impedance matching resistors. No external resistors, capacitors or magnetic components are necessary on the D+/D- signal paths between the PIC18F87J10 family device and USB cable. DS39775C-page 434 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 28.4 AC (Timing) Characteristics 28.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition © 2009 Microchip Technology Inc. DS39775C-page 435

PIC18F87J50 FAMILY 28.4.2 TIMING CONDITIONS The temperature and voltages specified in Table28-6 apply to all timing specifications unless otherwise noted. Figure28-3 specifies the load conditions for the timing specifications. TABLE 28-6: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Operating voltage VDD range as described in Section28.1 and Section28.3. FIGURE 28-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω VSS CL = 50 pF for all pins except OSC2/CLKO/RA6 and including D and E outputs as ports CL = 15 pF for OSC2/CLKO/RA6 DS39775C-page 436 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 28-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 28-7: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 48 MHz EC Oscillator mode DC 48 ECPLL Oscillator mode(2) Oscillator Frequency(1) 4 25 MHz HS Oscillator mode 4 25 HSPLL Oscillator mode(3) 1 TOSC External CLKI Period(1) 20.8 — ns EC Oscillator mode 20.8 — ECPLL Oscillator mode(2) Oscillator Period(1) 40.0 250 ns HS Oscillator mode 40.0 250 HSPLL Oscillator mode(3) 2 TCY Instruction Cycle Time(1) 83.3 — ns TCY = 4/FOSC, Industrial 3 TOSL, External Clock in (OSC1) 10 — ns EC Oscillator mode TOSH High or Low Time 4 TOSR, External Clock in (OSC1) — 7.5 ns EC Oscillator mode TOSF Rise or Fall Time Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 2: In order to use the PLL, the external clock frequency must be either 4, 8, 12, 16, 20, 24, 40 or 48 MHz. 3: In order to use the PLL, the crystal/resonator must produce a frequency of either 4, 8, 12, 16, 20 or 24MHz. © 2009 Microchip Technology Inc. DS39775C-page 437

PIC18F87J50 FAMILY TABLE 28-8: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.15V TO 3.6V) Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 48 MHz F11 FSYS On-Chip VCO System Frequency — 96 — MHz F12 t PLL Start-up Time (lock time) — — 2 ms rc F13 ΔCLK CLKO Stability (jitter) -0.25 — +0.25 % † Data in “Typ” column is at 3.3V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 28-9: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES) Param Device Min Typ Max Units Conditions No. INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1) All Devices -2 +/-1 2 % +25°C VDD = 2.7-3.3V -5 — 5 % -10°C to +85°C VDD = 2.0-3.3V -10 +/-1 10 % -40°C to +85°C VDD = 2.0-3.3V INTRC Accuracy @ Freq = 31 kHz(1) All Devices 26.56 — 35.94 kHz -40°C to +85°C VDD = 2.0-3.3V Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given time. When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’, use the INTRC accuracy specification. DS39775C-page 438 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 28-5: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure28-3 for load conditions. TABLE 28-10: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1) 11 TOSH2CKH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1) 12 TCKR CLKO Rise Time — 15 30 ns (Note 1) 13 TCKF CLKO Fall Time — 15 30 ns (Note 1) 14 TCKL2IOV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns 15 TIOV2CKH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns 16 TCKH2IOI Port In Hold after CLKO ↑ 0 — — ns 17 TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1 ↑ (Q2 cycle) to Port Input Invalid 100 — — ns (I/O in hold time) 19 TIOV2OSH Port Input Valid to OSC1 ↑ 0 — — ns (I/O in setup time) 20 TIOR Port Output Rise Time — — 6 ns 21 TIOF Port Output Fall Time — — 5 ns 22† TINP INTx pin High or Low Time TCY — — ns 23† TRBP RB7:RB4 Change INTx High or Low Time TCY — — ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC. © 2009 Microchip Technology Inc. DS39775C-page 439

PIC18F87J50 FAMILY FIGURE 28-6: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 AD<15:0> Address Data from External Address 150 160 163 151 162 161 155 166 167 168 ALE 164 169 171 CE 171A OE 165 Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated. TABLE 28-11: PROGRAM MEMORY READ TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE ↓ 0.25 TCY – 10 — — ns (address setup time) 151 TalL2adl ALE ↓ to Address Out Invalid 5 — — ns (address hold time) 155 TalL2oeL ALE ↓ to OE ↓ 10 0.125 TCY — ns 160 TadZ2oeL AD high-Z to OE ↓ (bus release to OE) 0 — — ns 161 ToeH2adD OE ↑ to AD Driven 0.125 TCY – 5 — — ns 162 TadV2oeH Least Significant Data Valid before OE ↑ 20 — — ns (data setup time) 163 ToeH2adl OE ↑ to Data In Invalid (data hold time) 0 — — ns 164 TalH2alL ALE Pulse Width — 0.25 TCY — ns 165 ToeL2oeH OE Pulse Width 0.5 TCY – 5 0.5 TCY — ns 166 TalH2alH ALE ↑ to ALE ↑ (cycle time) — TCY — ns 167 Tacc Address Valid to Data Valid 0.75 TCY – 25 — — ns 168 Toe OE ↓ to Data Valid — 0.5 TCY – 25 ns 169 TalL2oeH ALE ↓ to OE ↑ 0.625 TCY – 10 — 0.625 TCY + 10 ns 171 TalH2csL Chip Enable Active to ALE ↓ 0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns DS39775C-page 440 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 28-7: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 166 AD<15:0> Address Data Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157 157A UB or LB Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated. TABLE 28-12: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE ↓ (address setup time) 0.25 TCY – 10 — — ns 151 TalL2adl ALE ↓ to Address Out Invalid (address hold time) 5 — — ns 153 TwrH2adl WRn ↑ to Data Out Invalid (data hold time) 5 — — ns 154 TwrL WRn Pulse Width 0.5 TCY – 5 0.5 TCY — ns 156 TadV2wrH Data Valid before WRn ↑ (data setup time) 0.5 TCY – 10 — — ns 157 TbsV2wrL Byte Select Valid before WRn ↓ 0.25 TCY — — ns (byte select setup time) 157A TwrH2bsI WRn ↑ to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 — — ns 166 TalH2alH ALE ↑ to ALE ↑ (cycle time) — TCY — ns 171 TalH2csL Chip Enable Active to ALE ↓ 0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns © 2009 Microchip Technology Inc. DS39775C-page 441

PIC18F87J50 FAMILY FIGURE 28-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure28-3 for load conditions. TABLE 28-13: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period 3.4 4.0 4.6 ms (no postscaler) 32 TOST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period — 65.5 93 ms 34 TIOZ I/O High-Impedance from MCLR — — 3 TCY + 2 μs (Note 1) Low or Watchdog Timer Reset 38 TCSD CPU Start-up Time — 200 — μs (Note 2) Note 1: The maximum TIOZ is the lesser of (3 TCY + 2 μs) or 400 μs. 2: MCLR rising edge to code execution, assuming TPWRT (and TOST if applicable) has already expired. DS39775C-page 442 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 28-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure28-3 for load conditions. TABLE 28-14: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 TT1H T13CKI High Synchronous, no prescaler 0.5 TCY + 20 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 46 TT1L T13CKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 47 TT1P T13CKI Input Synchronous Greater of: — ns N = prescale Period 20ns or value (TCY + 40)/N (1, 2, 4, 8) Asynchronous 60 — ns FT1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 TCKE2TMRI Delay from External T13CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment © 2009 Microchip Technology Inc. DS39775C-page 443

PIC18F87J50 FAMILY FIGURE 28-10: CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure28-3 for load conditions. TABLE 28-15: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With prescaler 10 — ns 51 TCCH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With prescaler 10 — ns 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TCCR CCPx Output Fall Time — 25 ns 54 TCCF CCPx Output Fall Time — 25 ns DS39775C-page 444 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 28-11: PARALLEL MASTER PORT READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 System Clock PMA<13:18> Address PMD<7:0> Address<7:0> Data PM6 PM2 PM7 PM3 PMRD PM5 PMWR PMALL/PMALH PM1 PMCS<2:1> Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated. TABLE 28-16: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No PM1 PMALL/PMALH Pulse Width — 0.5 TCY — ns PM2 Address Out Valid to PMALL/PMALH — 0.75 TCY — ns Invalid (address setup time) PM3 PMALL/PMALH Invalid to Address Out — 0.25 TCY — ns Invalid (address hold time) PM5 PMRD Pulse Width — 0.5 TCY — ns PM6 PMRD or PMENB Active to Data In Valid — — — ns (data setup time) PM7 PMRD or PMENB Inactive to Data In Invalid — — — ns (data hold time) © 2009 Microchip Technology Inc. DS39775C-page 445

PIC18F87J50 FAMILY FIGURE 28-12: PARALLEL MASTER PORT WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 System Clock PMA<13:18> Address PMD<7:0> Address<7:0> Data PM12 PM13 PMRD PMWR PM11 PMALL/ PMALH PMCS<2:1> PM16 Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated. TABLE 28-17: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No PM11 PMWR Pulse Width — 0.5 TCY — ns PM12 Data Out Valid before PMWR or PMENB — — — ns goes Inactive (data setup time) PM13 PMWR or PMEMB Invalid to Data Out — — — ns Invalid (data hold time) PM16 PMCS Pulse Width TCY – 5 — — ns DS39775C-page 446 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 28-13: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SSx 70 SCKx (CKP = 0) 71 72 78 79 SCKx (CKP = 1) 79 78 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure28-3 for load conditions. TABLE 28-18: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 100 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns of Byte 2 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 100 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV © 2009 Microchip Technology Inc. DS39775C-page 447

PIC18F87J50 FAMILY FIGURE 28-14: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SSx 81 SCKx (CKP = 0) 71 72 79 73 SCKx (CKP = 1) 80 78 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure28-3 for load conditions. TABLE 28-19: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 100 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns of Byte 2 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 100 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TCY — ns TDOV2SCL DS39775C-page 448 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 28-15: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SSx 70 SCKx (CKP = 0) 83 71 72 78 79 SCKx (CKP = 1) 79 78 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure28-3 for load conditions. TABLE 28-20: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input 3 TCY — ns TSSL2SCL 70A TSSL2WB SSx ↓ to Write to SSPxBUF 3 TCY — ns 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 100 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 100 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx ↑ to SDOx Output High-Impedance 10 50 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 83 TSCH2SSH, SSx ↑ after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. © 2009 Microchip Technology Inc. DS39775C-page 449

PIC18F87J50 FAMILY FIGURE 28-16: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SSx 70 SCKx 83 (CKP = 0) 71 72 73 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure28-3 for load conditions. TABLE 28-21: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input 3 TCY — ns TSSL2SCL 70A TSSL2WB SSx ↓ to Write to SSPxBUF 3 TCY — ns 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 100 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 100 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx ↑ to SDOx Output High-Impedance 10 50 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TCY — ns TDOV2SCL 82 TSSL2DOV SDOx Data Output Valid after SSx ↓ Edge — 50 ns 83 TSCH2SSH, SSx ↑ after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39775C-page 450 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 28-17: I2C™ BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure28-3 for load conditions. TABLE 28-22: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 28-18: I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure28-3 for load conditions. © 2009 Microchip Technology Inc. DS39775C-page 451

PIC18F87J50 FAMILY TABLE 28-23: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — μs 400 kHz mode 0.6 — μs MSSP modules 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs MSSP modules 1.5 TCY — 102 TR SDAx and SCLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDAx and SCLx Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated 400 kHz mode 0.6 — μs Start condition 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — μs After this period, the first clock 400 kHz mode 0.6 — μs pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — μs 400 kHz mode 0.6 — μs 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT≥250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS39775C-page 452 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 28-19: MSSPx I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure28-3 for load conditions. TABLE 28-24: MSSPx I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. FIGURE 28-20: MSSPx I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 91 107 92 SDAx In 109 109 110 SDAx Out Note: Refer to Figure28-3 for load conditions. © 2009 Microchip Technology Inc. DS39775C-page 453

PIC18F87J50 FAMILY TABLE 28-25: MSSPx I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 1 MHz mode(1) TBD — ns 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) TBD — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free 400 kHz mode 1.3 — ms before a new transmission can start 1 MHz mode(1) TBD — ms D102 CB Bus Capacitive Loading — 400 pF Legend: TBD = To Be Determined Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, parameter #102 + parameter #107=1000+250=1250ns (for 100 kHz mode), before the SCLx line is released. DS39775C-page 454 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY FIGURE 28-21: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 122 Note: Refer to Figure28-3 for load conditions. TABLE 28-26: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid — 40 ns 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns 122 TDTRF Data Out Rise Time and Fall Time — 20 ns FIGURE 28-22: EUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TXx/CKx pin 125 RXx/DTx pin 126 Note: Refer to Figure28-3 for load conditions. TABLE 28-27: EUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CKx ↓ (DTx hold time) 10 — ns 126 TCKL2DTL Data Hold after CKx ↓ (DTx hold time) 15 — ns © 2009 Microchip Technology Inc. DS39775C-page 455

PIC18F87J50 FAMILY TABLE 28-28: A/D CONVERTER CHARACTERISTICS: PIC18F87J50 FAMILY (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±3 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±3 LSb ΔVREF ≥ 3.0V A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range 2.0 — — V VDD < 3.0V (VREFH – VREFL) 3 — — V VDD ≥ 3.0V A21 VREFH Reference Voltage High VSS — VREFH V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 2.5 kΩ Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 μA During VAIN acquisition. — — 150 μA During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source. FIGURE 28-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY (Note 1) GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. DS39775C-page 456 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY TABLE 28-29: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period 0.7 25.0(1) μs TOSC based, VREF ≥ 3.0V — 1 μs A/D RC mode 131 TCNV Conversion Time 11 12 TAD (not including acquisition time)(2) 132 TACQ Acquisition Time(3) 1.4 — μs -40°C to +85°C 135 TSWC Switching Time from Convert → Sample — (Note 4) 137 TDIS Discharge Time 0.2 — μs Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω. 4: On the following cycle of the device clock. © 2009 Microchip Technology Inc. DS39775C-page 457

PIC18F87J50 FAMILY FIGURE 28-24: USB SIGNAL TIMING USB Data Differential Lines 90% VCRS 10% TLR, TFR TLF, TFF TABLE 28-30: USB LOW-SPEED TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. TLR Transition Rise Time 75 — 300 ns CL = 200 to 600pF TLF Transition Fall Time 75 — 300 ns CL = 200 to 600pF TLRFM Rise/Fall Time Matching 80 — 125 % TABLE 28-31: USB FULL-SPEED REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. TFR Transition Rise Time 4 — 20 ns CL = 50pF TFF Transition Fall Time 4 — 20 ns CL = 50pF TFRFM Rise/Fall Time Matching 90 — 111.1 % DS39775C-page 458 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX 18F67J50 XXXXXXXXXX -I/PTe3 XXXXXXXXXX 0710017 YYWWNNN 80-Lead TQFP Example XXXXXXXXXXXX PIC18F87J50 XXXXXXXXXXXX -I/PTe3 YYWWNNN 0710017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS39775C-page 459

PIC18F87J50 FAMILY 29.2 Package Details The following sections give the technical details of the packages. 64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 NOTE 2 α A c φ A2 β A1 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 64 Lead Pitch e 0.50 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-085B DS39775C-page 460 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY 80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 b N NOTE 1 123 NOTE 2 α A c φ β A1 A2 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 80 Lead Pitch e 0.50 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 14.00 BSC Overall Length D 14.00 BSC Molded Package Width E1 12.00 BSC Molded Package Length D1 12.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-092B © 2009 Microchip Technology Inc. DS39775C-page 461

PIC18F87J50 FAMILY NOTES: DS39775C-page 462 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (February 2007) The differences between the devices listed in this data Original data sheet for the PIC18F87J10 family of sheet are shown in TableB-1, devices. Revision B (May 2007) Updated electrical specification data. Revision C (October 2009) Removed “Preliminary” marking. TABLE B-1: DEVICE DIFFERENCES BETWEEN PIC18F87J50 FAMILY MEMBERS Features PIC18F65J50 PIC18F66J50 PIC18F66J55 PIC18F67J50 PIC18F85J50 PIC18F86J50 PIC18F86J55 PIC18F87J50 Program Memory 32K 64K 96K 128K 32K 64K 96K 128K Program Memory 16380 32764 49148 65532 16380 32764 49148 65532 (Instructions) I/O Ports (Pins) Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G, H, J EMB No Yes 10-Bit ADC Module 8 Input Channels 12 Input Channels Packages 64-Pin TQFP 80-Pin TQFP © 2009 Microchip Technology Inc. DS39775C-page 463

PIC18F87J50 FAMILY NOTES: DS39775C-page 464 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY INDEX A Comparator Voltage Reference Output Buffer Example 347 A/D ...................................................................................301 Compare Mode Operation .......................................212 A/D Converter Interrupt, Configuring .......................305 Connections for On-Chip Voltage Regulator ...........360 Acquisition Requirements ........................................306 Demultiplexed Addressing Mode .............................181 ADCAL Bit ................................................................309 Device Clock ..............................................................36 ADRESH Register ....................................................304 Enhanced PWM .......................................................221 Analog Port Pins, Configuring ..................................307 EUSART Transmit ...................................................289 Associated Registers ...............................................310 EUSARTx Receive ..................................................291 Automatic Acquisition Time ......................................307 Calibration ................................................................309 External Power-on Reset Circuit (Slow VDD Power-up) 57 Configuring the Module ............................................305 Fail-Safe Clock Monitor ...........................................362 Conversion Clock (TAD) ...........................................307 Fully Multiplexed Addressing Mode .........................181 Conversion Requirements .......................................457 Generic I/O Port Operation ......................................137 Conversion Status (GO/DONE Bit) ..........................304 Interrupt Logic ..........................................................122 Conversions .............................................................308 LCD Control .............................................................189 Converter Characteristics ........................................456 Legacy Parallel Slave Port ......................................175 Operation in Power-Managed Modes ......................309 MSSP (I2C Mode) ....................................................243 Special Event Trigger (ECCP) .........................220, 308 MSSP (SPI Mode) ...................................................233 Use of the ECCP2 Trigger .......................................308 MSSPx (I2C Master Mode) ......................................263 Absolute Maximum Ratings .............................................419 Multiplexed Addressing Application .........................188 AC (Timing) Characteristics .............................................435 On-Chip Reset Circuit ................................................55 Load Conditions for Device Timing Specifications ...436 Parallel EEPROM (Up to 15-Bit Address, 16-Bit Data) . Parameter Symbology .............................................435 189 Temperature and Voltage Specifications .................436 Parallel EEPROM (Up to 15-Bit Address, 8-Bit Data) ... Timing Conditions ....................................................436 189 ACKSTAT ........................................................................269 Parallel Master/Slave Connection Addressed Buffer 178 ACKSTAT Status Flag .....................................................269 Parallel Master/Slave Connection Buffered .............177 ADCAL Bit ........................................................................309 Partially Multiplexed Addressing Application ...........188 ADCON0 Register Partially Multiplexed Addressing Mode ....................181 GO/DONE Bit ...........................................................304 PIC18F6XJ5X (64-Pin) ..............................................12 ADDFSR ..........................................................................408 PIC18F8XJ5X (80-Pin) ..............................................13 ADDLW ............................................................................371 PMP Module ............................................................167 ADDULNK ........................................................................408 PWM Operation (Simplified) ....................................214 ADDWF ............................................................................371 Reads From Flash Program Memory ......................101 ADDWFC .........................................................................372 Single Comparator ...................................................340 ADRESL Register ............................................................304 Table Read Operation ...............................................97 Analog-to-Digital Converter. See A/D. Table Write Operation ...............................................98 ANDLW ............................................................................372 Table Writes to Flash Program Memory ..................103 ANDWF ............................................................................373 Timer0 in 16-Bit Mode .............................................192 Assembler Timer0 in 8-Bit Mode ...............................................192 MPASM Assembler ..................................................416 Timer1 .....................................................................196 Auto-Wake-up on Sync Break Character .........................292 Timer1 (16-Bit Read/Write Mode) ............................196 B Timer2 .....................................................................202 Baud Rate Generator .......................................................265 Timer3 .....................................................................204 BC ....................................................................................373 Timer3 (16-Bit Read/Write Mode) ............................204 BCF ..................................................................................374 Timer4 .....................................................................208 BF ....................................................................................269 USB Interrupt Logic .................................................325 BF Status Flag .................................................................269 USB Peripheral and Options ...................................311 Block Diagrams Using the Open-Drain Output ..................................138 16-Bit Byte Select Mode ..........................................113 Watchdog Timer ......................................................358 16-Bit Byte Write Mode ............................................111 BN ....................................................................................374 16-Bit Word Write Mode ...........................................112 BNC .................................................................................375 8-Bit Multiplexed Address and Data Application ......188 BNN .................................................................................375 8-Bit Multiplexed Modes ...........................................115 BNOV ..............................................................................376 A/D ...........................................................................304 BNZ .................................................................................376 Analog Input Model ..................................................305 BOR. See Brown-out Reset. Baud Rate Generator ...............................................265 BOV .................................................................................379 Capture Mode Operation .........................................211 BRA .................................................................................377 Comparator Analog Input Model ..............................340 Break Character (12-Bit) Transmit and Receive ..............294 Comparator Configurations ......................................342 BRG. See Baud Rate Generator. Comparator Output ..................................................337 Brown-out Reset (BOR) .....................................................57 Comparator Voltage Reference ...............................345 and On-Chip Voltage Regulator ..............................361 © 2009 Microchip Technology Inc. DS39775C-page 465

PIC18F87J50 FAMILY Detecting ....................................................................57 COMF ..............................................................................382 Disabling in Sleep Mode ............................................57 Comparator ......................................................................337 BSF ..................................................................................377 Analog Input Connection Considerations ................340 BTFSC .............................................................................378 Associated Registers ...............................................344 BTFSS ..............................................................................378 Configuration ...........................................................341 BTG ..................................................................................379 Control .....................................................................341 BZ .....................................................................................380 Effects of a Reset ....................................................344 Enable and Input Selection ......................................341 C Enable and Output Selection ...................................341 C Compilers Interrupts .................................................................343 MPLAB C18 .............................................................416 Operation .................................................................340 MPLAB C30 .............................................................416 Operation During Sleep ...........................................344 Calibration (A/D Converter) ..............................................309 Response Time ........................................................340 CALL ................................................................................380 Comparator Specifications ...............................................433 CALLW .............................................................................409 Comparator Voltage Reference .......................................345 Capture (CCP Module) .....................................................211 Accuracy and Error ..................................................347 Associated Registers ...............................................213 Associated Registers ...............................................347 CCPRxH:CCPRxL Registers ...................................211 Configuring ..............................................................346 CCPx Pin Configuration ...........................................211 Connection Considerations ......................................347 Prescaler ..................................................................211 Effects of a Reset ....................................................347 Software Interrupt ....................................................211 Operation During Sleep ...........................................347 Timer1/Timer3 Mode Selection ................................211 Compare (CCP Module) ..................................................212 Capture (ECCP Module) ..................................................220 Associated Registers ...............................................213 Capture/Compare/PWM (CCP) ........................................209 CCPRx Register ......................................................212 Capture Mode. See Capture. Pin Configuration .....................................................212 CCP Mode and Timer Resources ............................210 Software Interrupt ....................................................212 CCPRxH Register ....................................................210 Timer1/Timer3 Mode Selection ................................212 CCPRxL Register .....................................................210 Compare (ECCP Module) ................................................220 Compare Mode. See Compare. Special Event Trigger ..............................205, 220, 308 ECCP/CCP Timer Interconnect Configurations .......210 Computed GOTO ...............................................................75 Module Configuration ...............................................210 Configuration Bits ............................................................349 Clock Sources ....................................................................42 Configuration Mismatch (CM) Reset ..................................57 Effects of Power-Managed Modes .............................46 Configuration Register Protection ....................................364 Selecting the 31 kHz Source ......................................42 Core Features Selection Using OSCCON Register ...........................42 Easy Migration ...........................................................10 CLRF ................................................................................381 Expanded Memory .......................................................9 CLRWDT ..........................................................................381 Extended Instruction Set ...........................................10 Code Examples External Memory Bus ................................................10 16 x 16 Signed Multiply Routine ..............................120 nanoWatt Technology ..................................................9 16 x 16 Unsigned Multiply Routine ..........................120 Oscillator Options and Features ..................................9 8 x 8 Signed Multiply Routine ..................................119 Universal Serial Bus (USB) ..........................................9 8 x 8 Unsigned Multiply Routine ..............................119 CPFSEQ ..........................................................................382 A/D Calibration Routine ...........................................309 CPFSGT ..........................................................................383 Changing Between Capture Prescalers ...................211 CPFSLT ...........................................................................383 Computed GOTO Using an Offset Value ...................75 Crystal Oscillator/Ceramic Resonator ................................37 Erasing a Flash Program Memory Row ...................102 Customer Change Notification Service ............................477 Fast Register Stack ....................................................75 Customer Notification Service .........................................477 How to Clear RAM (Bank 1) Using Indirect Addressing . Customer Support ............................................................477 90 D Implementing a Real-Time Clock Using a Timer1 Inter- rupt Service ......................................................199 Data Addressing Modes ....................................................90 Initializing PORTA ....................................................140 Comparing Addressing Modes with the Extended In- Initializing PORTB ....................................................143 struction Set Enabled ........................................94 Initializing PORTC ....................................................146 Direct .........................................................................90 Initializing PORTD ....................................................149 Indexed Literal Offset ................................................93 Initializing PORTE ....................................................152 BSR ...................................................................95 Initializing PORTF ....................................................155 Instructions Affected ..........................................93 Initializing PORTG ...................................................158 Mapping Access Bank .......................................95 Initializing PORTH ....................................................161 Indirect .......................................................................90 Initializing PORTJ ....................................................164 Inherent and Literal ....................................................90 Loading the SSP1BUF (SSP1SR) Register .............236 Data Memory .....................................................................78 Reading a Flash Program Memory Word ................101 Access Bank ..............................................................80 Saving STATUS, WREG and BSR Registers in RAM ... Bank Select Register (BSR) ......................................78 136 Extended Instruction Set ...........................................93 Writing to Flash Program Memory ...........................104 General Purpose Registers .......................................80 Code Protection ...............................................................349 Memory Maps DS39775C-page 466 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY PIC18F87J50 Family Devices ...........................79 Baud Rates, Asynchronous Modes .................285 Shared Address Registers .................................82 High Baud Rate Select (BRGH Bit) .................283 Special Function Registers ................................81 Sampling .........................................................283 Special Function Registers ........................................81 Synchronous Master Mode ......................................295 Context Defined SFRs .......................................82 Associated Registers, Receive ........................298 USB RAM ...................................................................78 Associated Registers, Transmit .......................296 DAW .................................................................................384 Reception ........................................................297 DC Characteristics ...........................................................430 Transmission ...................................................295 Power-Down and Supply Current ............................422 Synchronous Slave Mode ........................................298 Supply Voltage .........................................................421 Associated Registers, Receive ........................300 DCFSNZ ..........................................................................385 Associated Registers, Transmit .......................299 DECF ...............................................................................384 Reception ........................................................299 DECFSZ ...........................................................................385 Transmission ...................................................298 Development Support ......................................................415 Extended Instruction Set Device Differences ...........................................................463 ADDFSR ..................................................................408 Device Overview ..................................................................9 ADDULNK ...............................................................408 Details on Individual Family Members .......................10 CALLW ....................................................................409 Features (64-Pin Devices) .........................................11 MOVSF ....................................................................409 Features (80-Pin Devices) .........................................11 MOVSS ....................................................................410 Direct Addressing ...............................................................91 PUSHL .....................................................................410 SUBFSR ..................................................................411 E SUBULNK ................................................................411 ECCP External Clock Input ...........................................................38 Associated Registers ...............................................232 External Memory Bus ......................................................107 Capture and Compare Modes ..................................220 16-Bit Byte Select Mode ..........................................113 Enhanced PWM Mode .............................................221 16-Bit Byte Write Mode ............................................111 Standard PWM Mode ...............................................220 16-Bit Data Width Modes .........................................110 Effect on Standard PIC Instructions .................................412 16-Bit Mode Timing .................................................114 Electrical Characteristics ..................................................419 16-Bit Word Write Mode ..........................................112 Enhanced Capture/Compare/PWM (ECCP) ....................217 8-Bit Data Width Mode ............................................115 Capture Mode. See Capture (ECCP Module). 8-Bit Mode Timing ...................................................116 ECCP1/ECCP3 Outputs and Program Memory Mode ... Address and Data Line Usage (table) .....................109 218 Address and Data Width ..........................................109 ECCP2 Outputs and Program Memory Modes ........218 Address Shifting ......................................................109 Outputs and Configuration .......................................218 Control .....................................................................108 Pin Configurations for ECCP1 .................................219 I/O Port Functions ....................................................107 Pin Configurations for ECCP2 .................................219 Operation in Power-Managed Modes ......................117 Pin Configurations for ECCP3 .................................220 Program Memory Modes .........................................110 PWM Mode. See PWM (ECCP Module). Extended Microcontroller .................................110 Timer Resources ......................................................218 Microcontroller .................................................110 Use of CCP4/CCP5 with ECCP1/ECCP3 ................218 Wait States ..............................................................110 Enhanced Universal Synchronous Asynchronous Receiver Weak Pull-ups on Port Pins .....................................110 Transmitter (EUSART). See EUSART. F ENVREG pin ....................................................................360 Equations Fail-Safe Clock Monitor ...........................................349, 362 A/D Acquisition Time ................................................306 Interrupts in Power-Managed Modes ......................363 A/D Minimum Charging Time ...................................306 POR or Wake-up From Sleep ..................................363 Calculating the Minimum Required Acquisition Time ..... WDT During Oscillator Failure .................................362 306 Fast Register Stack ...........................................................75 Estimating USB Transceiver Current Consumption .333 Firmware Instructions ......................................................365 Errata ...................................................................................7 Flash Configuration Words ..............................................349 EUSART Flash Program Memory .....................................................97 Asynchronous Mode ................................................289 Associated Registers ...............................................106 12-Bit Break Transmit and Receive .................294 Control Registers .......................................................98 Associated Registers, Receive ........................292 EECON1 and EECON2 .....................................98 Associated Registers, Transmit .......................290 TABLAT (Table Latch) Register ......................100 Auto-Wake-up on Sync Break .........................292 TBLPTR (Table Pointer) Register ....................100 Receiver ...........................................................291 Erase Sequence ......................................................102 Setting Up 9-Bit Mode with Address Detect .....291 Erasing ....................................................................102 Transmitter .......................................................289 Operation During Code-Protect ...............................106 Baud Rate Generator Reading ...................................................................101 Operation in Power-Managed Mode ................283 Table Pointer Baud Rate Generator (BRG) ....................................283 Boundaries Based on Operation .....................100 Associated Registers .......................................284 Table Pointer Boundaries ........................................100 Auto-Baud Rate Detect ....................................287 Table Reads and Table Writes ..................................97 Baud Rate Error, Calculating ...........................284 Write Sequence .......................................................103 © 2009 Microchip Technology Inc. DS39775C-page 467

PIC18F87J50 FAMILY Writing ......................................................................103 Indirect Addressing ............................................................91 Unexpected Termination ..................................106 INFSNZ ............................................................................387 Write Verify ......................................................106 Initialization Conditions for All Registers ......................61–67 FSCM. See Fail-Safe Clock Monitor. Instruction Cycle ................................................................76 Clocking Scheme .......................................................76 G Flow/Pipelining ...........................................................76 GOTO ...............................................................................386 Instruction Set ..................................................................365 ADDLW ....................................................................371 H ADDWF ....................................................................371 Hardware Multiplier ..........................................................119 ADDWF (Indexed Literal Offset Mode) ....................413 8 x 8 Multiplication Algorithms .................................119 ADDWFC .................................................................372 Operation .................................................................119 ANDLW ....................................................................372 Performance Comparison (table) .............................119 ANDWF ....................................................................373 I BC ............................................................................373 BCF .........................................................................374 I/O Ports ...........................................................................137 BN ............................................................................374 Input Pull-up Configuration ......................................138 BNC .........................................................................375 Open-Drain Outputs .................................................138 BNN .........................................................................375 Pin Capabilities ........................................................137 BNOV ......................................................................376 TTL Input Buffer Option ...........................................138 BNZ .........................................................................376 I2C Mode (MSSP) BOV .........................................................................379 Acknowledge Sequence Timing ...............................272 BRA .........................................................................377 Associated Registers ...............................................278 BSF ..........................................................................377 Baud Rate Generator ...............................................265 BSF (Indexed Literal Offset Mode) ..........................413 Bus Collision BTFSC .....................................................................378 During a Repeated Start Condition ..................276 BTFSS .....................................................................378 During a Stop Condition ...................................277 BTG .........................................................................379 Clock Arbitration .......................................................266 BZ ............................................................................380 Clock Stretching .......................................................258 CALL ........................................................................380 10-Bit Slave Receive Mode (SEN = 1) .............258 CLRF .......................................................................381 10-Bit Slave Transmit Mode .............................258 CLRWDT .................................................................381 7-Bit Slave Receive Mode (SEN = 1) ...............258 COMF ......................................................................382 7-Bit Slave Transmit Mode ...............................258 CPFSEQ ..................................................................382 Clock Synchronization and the CKP bit ...................259 CPFSGT ..................................................................383 Effects of a Reset .....................................................273 CPFSLT ...................................................................383 General Call Address Support .................................262 DAW ........................................................................384 I2C Clock Rate w/BRG .............................................265 DCFSNZ ..................................................................385 Master Mode ............................................................263 DECF .......................................................................384 Operation .........................................................264 DECFSZ ..................................................................385 Reception .........................................................269 Extended Instructions ..............................................407 Repeated Start Condition Timing .....................268 Considerations when Enabling ........................412 Start Condition Timing .....................................267 Syntax ..............................................................407 Transmission ....................................................269 Use with MPLAB IDE Tools .............................414 Multi-Master Communication, Bus Collision and Arbitra- General Format ........................................................367 tion ...................................................................273 GOTO ......................................................................386 Multi-Master Mode ...................................................273 INCF ........................................................................386 Operation .................................................................248 INCFSZ ....................................................................387 Read/Write Bit Information (R/W Bit) ...............248, 251 INFSNZ ....................................................................387 Registers ..................................................................243 IORLW .....................................................................388 Serial Clock (RC3/SCKx/SCLx) ...............................251 IORWF .....................................................................388 Slave Mode ..............................................................248 LFSR .......................................................................389 Addressing .......................................................248 MOVF ......................................................................389 Addressing Masking Modes MOVFF ....................................................................390 5-Bit .........................................................249 MOVLB ....................................................................390 7-Bit .........................................................250 MOVLW ...................................................................391 Reception .........................................................251 MOVWF ...................................................................391 Transmission ....................................................251 MULLW ....................................................................392 Sleep Operation .......................................................273 MULWF ....................................................................392 Stop Condition Timing ..............................................272 NEGF .......................................................................393 INCF .................................................................................386 NOP .........................................................................393 INCFSZ ............................................................................387 Opcode Field Descriptions .......................................366 In-Circuit Debugger ..........................................................364 POP .........................................................................394 In-Circuit Serial Programming (ICSP) ......................349, 364 PUSH .......................................................................394 Indexed Literal Offset Addressing RCALL .....................................................................395 and Standard PIC18 Instructions .............................412 RESET .....................................................................395 Indexed Literal Offset Mode .............................................412 RETFIE ....................................................................396 DS39775C-page 468 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY RETLW ....................................................................396 MOVF ..............................................................................389 RETURN ..................................................................397 MOVFF ............................................................................390 RLCF ........................................................................397 MOVLB ............................................................................390 RLNCF .....................................................................398 MOVLW ...........................................................................391 RRCF .......................................................................398 MOVSF ............................................................................409 RRNCF ....................................................................399 MOVSS ............................................................................410 SETF ........................................................................399 MOVWF ...........................................................................391 SETF (Indexed Literal Offset Mode) ........................413 MPLAB ASM30 Assembler, Linker, Librarian ..................416 SLEEP .....................................................................400 MPLAB ICD 2 In-Circuit Debugger ..................................417 Standard Instructions ...............................................365 MPLAB ICE 2000 High-Performance Universal In-Circuit Em- SUBFWB ..................................................................400 ulator ........................................................................417 SUBLW ....................................................................401 MPLAB Integrated Development Environment Software .415 SUBWF ....................................................................401 MPLAB PM3 Device Programmer ...................................417 SUBWFB ..................................................................402 MPLAB REAL ICE In-Circuit Emulator System ...............417 SWAPF ....................................................................402 MPLINK Object Linker/MPLIB Object Librarian ...............416 TBLRD .....................................................................403 MSSP TBLWT .....................................................................404 ACK Pulse .......................................................248, 251 TSTFSZ ...................................................................405 I2C Mode. See I2C Mode. XORLW ....................................................................405 Module Overview .....................................................233 XORWF ....................................................................406 SPI Master/Slave Connection ..................................237 INTCON Register TMR4 Output for Clock Shift ....................................208 RBIF Bit ....................................................................143 MULLW ............................................................................392 INTCON Registers ...........................................................123 MULWF ............................................................................392 Inter-Integrated Circuit. See I2C. N Internal Oscillator Block .....................................................38 Adjustment .................................................................39 NEGF ...............................................................................393 OSCTUNE Register ...................................................39 NOP .................................................................................393 Internal RC Oscillator O Use with WDT ..........................................................358 Internal Voltage Reference Specifications .......................433 Oscillator Configuration .....................................................35 Internet Address ...............................................................477 Internal Oscillator Block .............................................38 Interrupt Sources .............................................................349 Oscillator Control .......................................................35 A/D Conversion Complete .......................................305 Oscillator Modes and USB Operation ........................36 Capture Complete (CCP) .........................................211 Oscillator Selection ..........................................................349 Compare Complete (CCP) .......................................212 Oscillator Settings for USB ................................................40 Interrupt-on-Change (RB7:RB4) ..............................143 Oscillator Start-up Timer (OST) .........................................46 TMR0 Overflow ........................................................193 Oscillator Switching ...........................................................42 TMR1 Overflow ........................................................195 Oscillator Transitions .........................................................43 TMR2 to PR2 Match (PWM) ....................................221 Oscillator, Timer1 .....................................................195, 205 TMR3 Overflow ................................................203, 205 Oscillator, Timer3 .............................................................203 TMR4 to PR4 Match ................................................208 P TMR4 to PR4 Match (PWM) ....................................207 Packaging ........................................................................459 Interrupts ..........................................................................121 Details ......................................................................460 During, Context Saving ............................................136 Marking ....................................................................459 INTx Pin ...................................................................136 Parallel Master Port (PMP) ..............................................167 PORTB, Interrupt-on-Change ..................................136 Application Examples ..............................................188 TMR0 .......................................................................136 Associated Registers ...............................................190 Interrupts, Flag Bits Master Port Modes ..................................................180 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) .....143 Module Registers .....................................................168 INTOSC Frequency Drift ....................................................39 Slave Port Modes ....................................................175 INTOSC, INTRC. See Internal Oscillator Block. PICSTART Plus Development Programmer ....................418 IORLW .............................................................................388 PIE Registers ...................................................................129 IORWF .............................................................................388 Pin Functions IPR Registers ...................................................................132 AVDD ..........................................................................21 L AVDD ..........................................................................34 LFSR ................................................................................389 AVSS ..........................................................................21 AVSS ..........................................................................34 M ENVREG .............................................................21, 34 Master Clear (MCLR) .........................................................57 MCLR ..................................................................14, 22 Master Synchronous Serial Port (MSSP). See MSSP. OSC1/CLKI/RA7 ..................................................14, 22 Memory Organization .........................................................69 OSC2/CLKO/RA6 ................................................14, 22 Data Memory .............................................................78 RA0/AN0 ..............................................................15, 23 Program Memory .......................................................69 RA1/AN1 ..............................................................15, 23 Memory Programming Requirements ..............................432 RA2/AN2/VREF- ...................................................15, 23 Microchip Internet Web Site .............................................477 RA3/AN3/VREF+ ..................................................15, 23 © 2009 Microchip Technology Inc. DS39775C-page 469

PIC18F87J50 FAMILY RA4/PMD5/T0CKI ......................................................23 RG1/PMA7/TX2/CK2 ...........................................21, 31 RA4/T0CKI .................................................................15 RG2/PMA6/RX2/DT2 ...........................................21, 31 RA5/AN4/C2INA ........................................................15 RG3/PMCS1/CCP4/P3D .....................................21, 31 RA5/PMD4/AN4/C2INA .............................................23 RG4/PMCS2/CCP5/P1D .....................................21, 31 RA6 ......................................................................15, 23 RH0/A16 ....................................................................32 RA7 ......................................................................15, 23 RH1/A17 ....................................................................32 RB0/FLT0/INT0 ....................................................16, 24 RH2/A18/PMD7 .........................................................32 RB1/INT1/PMA4 ..................................................16, 24 RH3/A19/PMD6 .........................................................32 RB2/INT2/PMA3 ..................................................16, 24 RH4/PMD3/AN12/P3C/C2INC ...................................32 RB3/INT3/ECCP2/P2A/PMA2 ....................................24 RH5/PMBE/AN13/P3B/C2IND ...................................32 RB3/INT3/PMA2 ........................................................16 RH6/PMRD/AN14/P1C/C1INC ..................................32 RB4/KBI0/PMA1 ..................................................16, 24 RH7/PMWR/AN15/P1B .............................................33 RB5/KBI1/PMA0 ..................................................16, 24 RJ0/ALE ....................................................................34 RB6/KBI2/PGC ....................................................16, 24 RJ1/OE ......................................................................34 RB7/KBI3/PGD ....................................................16, 24 RJ2/WRL ...................................................................34 RC0/T1OSO/T13CKI ...........................................17, 25 RJ3/WRH ...................................................................34 RC1/T1OSI/ECCP2/P2A ......................................17, 25 RJ4/BA0 ....................................................................34 RC2/ECCP1/P1A .................................................17, 25 RJ5/CE ......................................................................34 RC3/SCK1/SCL1 .................................................17, 25 RJ6/LB .......................................................................34 RC4/SDI1/SDA1 ..................................................17, 25 RJ7/UB ......................................................................34 RC5/SDO1/C2OUT ..............................................17, 25 VDD ............................................................................21 RC6/TX1/CK1 ......................................................17, 25 VDD ............................................................................34 RC7/RX1/DT1 ......................................................17, 25 VDDCORE/VCAP .....................................................21, 34 RD0/AD0/PMD0 .........................................................26 VSS ............................................................................21 RD0/PMD0 .................................................................18 VSS ............................................................................34 RD1/AD1/PMD1 .........................................................26 VUSB ....................................................................21, 34 RD1/PMD1 .................................................................18 Pinout I/O Descriptions RD2/AD2/PMD2 .........................................................26 PIC18F6XJ5X (64-Pin TQFP) ....................................14 RD2/PMD2 .................................................................18 PIC18F8XJ5X (80-Pin TQFP) ....................................22 RD3/AD3/PMD3 .........................................................26 PIR Registers ...................................................................126 RD3/PMD3 .................................................................18 PLL Frequency Multiplier ...................................................38 RD4/AD4/PMD4/SDO2 ..............................................26 POP .................................................................................394 RD4/PMD4/SDO2 ......................................................18 POR. See Power-on Reset. RD5/AD5/PMD5/SDI2/SDA2 .....................................26 PORTA RD5/PMD5/SDI2/SDA2 .............................................18 Associated Registers ...............................................142 RD6/AD6/PMD6/SCK2/SCL2 ....................................27 LATA Register .........................................................140 RD6/PMD6/SCK2/SCL2 ............................................18 PORTA Register ......................................................140 RD7/AD7/PMD7/SS2 .................................................27 TRISA Register ........................................................140 RD7/PMD7/SS2 .........................................................18 PORTB RE0/AD8/PMRD/P2D ................................................28 Associated Registers ...............................................145 RE0/PMRD/P2D ........................................................19 LATB Register .........................................................143 RE1/AD9/PMWR/P2C ................................................28 PORTB Register ......................................................143 RE1/PMWR/P2C ........................................................19 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........143 RE2/AD10/PMBE/P2B ...............................................28 TRISB Register ........................................................143 RE2/PMBE/P2B .........................................................19 PORTC RE3/AD11/PMA13/P3C/REFO ..................................28 Associated Registers ...............................................148 RE3/PMA13/P3C/REFO ............................................19 LATC Register .........................................................146 RE4/AD12/PMA12/P3B .............................................28 PORTC Register ......................................................146 RE4/PMA12/P3B .......................................................19 RC3/SCKx/SCLx Pin ...............................................251 RE5/AD13/PMA11/P1C .............................................28 TRISC Register ........................................................146 RE5/PMA11/P1C .......................................................19 PORTD RE6/AD14/PMA10/P1B .............................................29 Associated Registers ...............................................151 RE6/PMA10/P1B .......................................................19 LATD Register .........................................................149 RE7/AD15/PMA9/ECCP2/P2A ..................................29 PORTD Register ......................................................149 RE7/PMA9/ECCP2/P2A ............................................19 TRISD Register ........................................................149 RF2/PMA5/AN7/C2INB ........................................20, 30 PORTE RF3/D- .................................................................20, 30 Associated Registers ...............................................154 RF4/D+ .................................................................20, 30 LATE Register .........................................................152 RF5/AN10/C1INB/CVREF ...........................................20 PORTE Register ......................................................152 RF5/PMD2/AN10/C1INB/CVREF ................................30 TRISE Register ........................................................152 RF6/AN11/C1INA .......................................................20 PORTF RF6/PMD1/AN11/C1INA ............................................30 Associated Registers ...............................................157 RF7/PMD0/SS1/C1OUT ............................................30 LATF Register ..........................................................155 RF7/SS1/C1OUT .......................................................20 PORTF Register ......................................................155 RG0/PMA8/ECCP3/P3A ......................................21, 31 TRISF Register ........................................................155 DS39775C-page 470 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY PORTG Extended Microcontroller (Address Shifting) .....72 Associated Registers ...............................................160 Memory Access (table) ......................................72 LATG Register .........................................................158 Microcontroller ...................................................71 PORTG Register ......................................................158 Reset Vector ..............................................................70 TRISG Register ........................................................158 Program Verification and Code Protection ......................364 PORTH Programming, Device Instructions ...................................365 Associated Registers ...............................................163 Pulse-Width Modulation. See PWM (CCP Module) and PWM LATH Register .........................................................161 (ECCP Module). PORTH Register ......................................................161 PUSH ...............................................................................394 TRISH Register ........................................................161 PUSH and POP Instructions ..............................................74 PORTJ PUSHL .............................................................................410 Associated Registers ...............................................165 PWM (CCP Module) LATJ Register ..........................................................164 Associated Registers ...............................................216 PORTJ Register .......................................................164 Duty Cycle ...............................................................214 TRISJ Register .........................................................164 Example Frequencies/Resolutions ..........................215 Power-Managed Modes .....................................................47 Operation Setup ......................................................215 and EUSART Operation ...........................................283 Period ......................................................................214 and SPI Operation ...................................................241 PR2/PR4 Registers .................................................214 Clock Transitions and Status Indicators .....................48 TMR2 (TMR4) to PR2 (PR4) Match ........................214 Entering ......................................................................47 TMR2 to PR2 Match ................................................221 Exiting Idle and Sleep Modes ....................................53 TMR4 to PR4 Match ................................................207 By Interrupt ........................................................53 PWM (ECCP Module) ......................................................221 By Reset ............................................................53 CCPR1H:CCPR1L Registers ..................................221 By WDT Time-out ..............................................53 Direction Change in Full-Bridge Output Mode .........226 Without an Oscillator Start-up Delay ..................53 Duty Cycle ...............................................................222 Idle Modes .................................................................51 Effects of a Reset ....................................................231 PRI_IDLE ...........................................................52 Enhanced PWM Auto-Shutdown .............................228 RC_IDLE ............................................................53 Example Frequencies/Resolutions ..........................222 SEC_IDLE .........................................................52 Full-Bridge Mode .....................................................225 Multiple Sleep Commands .........................................48 Full-Bridge Output Application Example ..................226 Run Modes .................................................................48 Half-Bridge Mode .....................................................224 PRI_RUN ...........................................................48 Half-Bridge Output Mode Applications Example .....224 RC_RUN ............................................................50 Output Configurations ..............................................222 SEC_RUN ..........................................................48 Output Relationships (Active-High) .........................223 Selecting ....................................................................47 Output Relationships (Active-Low) ..........................223 Sleep Mode ................................................................51 Period ......................................................................221 Summary (table) ........................................................47 Programmable Dead-Band Delay ............................228 Power-on Reset (POR) ......................................................57 Setup for PWM Operation .......................................231 Power-up Delays ................................................................46 Start-up Considerations ...........................................229 Power-up Timer (PWRT) .............................................46, 58 Q Time-out Sequence ....................................................58 Prescaler Q Clock ....................................................................215, 222 Timer2 ......................................................................222 R Prescaler, Timer0 .............................................................193 Prescaler, Timer2 (Timer4) ..............................................215 RAM. See Data Memory. PRI_IDLE Mode .................................................................52 RC_IDLE Mode ..................................................................53 PRI_RUN Mode .................................................................48 RC_RUN Mode ..................................................................50 Program Counter ...............................................................73 RCALL .............................................................................395 PCL, PCH and PCU Registers ...................................73 RCON Register PCLATH and PCLATU Registers ..............................73 Bit Status During Initialization ....................................60 Program Memory Reader Response ............................................................478 ALU Register File .......................................................................80 Status .................................................................89 Register File Summary ................................................83–88 Extended Instruction Set ............................................92 Registers Flash Configuration Words ........................................70 ADCON0 (A/D Control 0) .........................................301 Hard Memory Vectors ................................................70 ADCON1 (A/D Control 1) .........................................302 Instructions .................................................................77 ANCON0 (A/D Port Configuration 2) .......................303 Two-Word ..........................................................77 ANCON1 (A/D Port Configuration 1) .......................303 Interrupt Vector ..........................................................70 BAUDCONx (Baud Rate Control) ............................282 Look-up Tables ..........................................................75 BDnSTAT (Buffer Descriptor n Status, CPU Mode) 321 Memory Maps ............................................................69 BDnSTAT (Buffer Descriptor n Status, SIE Mode) ..322 Hard Vectors and Configuration Words .............70 CCPxCON (CCPx Control) ......................................209 Modes ................................................................72 CCPxCON (ECCPx Control) ...................................217 Modes ........................................................................71 CMSTAT (Comparator Status) ................................339 Extended Microcontroller ...................................71 CMxCON (Comparator Control x) ...........................338 CONFIG1H (Configuration 1 High) ..........................352 © 2009 Microchip Technology Inc. DS39775C-page 471

PIC18F87J50 FAMILY CONFIG1L (Configuration 1 Low) ............................351 MCLR Reset, During Power-Managed Modes ..........55 CONFIG2H (Configuration 2 High) ..........................354 MCLR Reset, Normal Operation ................................55 CONFIG3H (Configuration 3 High) ..........................356 Power-on Reset (POR) ..............................................55 CONFIG3L (Configuration 3 Low) ......................71, 355 RESET Instruction .....................................................55 CVRCON (Comparator Voltage Reference Control) 346 Stack Full Reset .........................................................55 DEVID1 (Device ID 1) ..............................................357 Stack Underflow Reset ..............................................55 DEVID2 (Device ID 2) ..............................................357 Watchdog Timer (WDT) Reset ..................................55 ECCPxAS (ECCPx Auto-Shutdown Control) ...........229 Resets ..............................................................................349 ECCPxDEL (ECCPx PWM Delay) ...........................228 Brown-out Reset (BOR) ...........................................349 EECON1 (EEPROM Control 1) ..................................99 Oscillator Start-up Timer (OST) ...............................349 INTCON (Interrupt Control) ......................................123 Power-on Reset (POR) ............................................349 INTCON2 (Interrupt Control 2) .................................124 Power-up Timer (PWRT) .........................................349 INTCON3 (Interrupt Control 3) .................................125 RETFIE ............................................................................396 IPR1 (Peripheral Interrupt Priority 1) ........................132 RETLW ............................................................................396 IPR2 (Peripheral Interrupt Priority 2) ........................133 RETURN ..........................................................................397 IPR3 (Peripheral Interrupt Priority 3) ........................134 Revision History ...............................................................463 MEMCON (External Memory Bus Control) ..............108 RLCF ...............................................................................397 ODCON1 (Peripheral Open-Drain Control 1) ...........139 RLNCF .............................................................................398 ODCON2 (Peripheral Open-Drain Control 2) ...........139 RRCF ...............................................................................398 ODCON3 (Peripheral Open-Drain Control 3) ...........139 RRNCF ............................................................................399 OSCCON (Oscillator Control) ....................................44 S OSCTUNE (Oscillator Tuning) ...................................40 PADCFG1 (Pad Configuration Control 1) ................140 SCKx ................................................................................233 PIE1 (Peripheral Interrupt Enable 1) ........................129 SDIx .................................................................................233 PIE2 (Peripheral Interrupt Enable 2) ........................130 SDOx ...............................................................................233 PIE3 (Peripheral Interrupt Enable 3) ........................131 SEC_IDLE Mode ...............................................................52 PIR1 (Peripheral Interrupt Request (Flag) 1) ...........126 SEC_RUN Mode ................................................................48 PIR2 (Peripheral Interrupt Request (Flag) 2) ...........127 Serial Clock, SCKx ..........................................................233 PIR3 (Peripheral Interrupt Request (Flag) 3) ...........128 Serial Data In (SDIx) ........................................................233 PMADDRH (Parallel Port Address High Byte) .........174 Serial Data Out (SDOx) ...................................................233 PMCONH (Parallel Port Control High Byte) .............168 Serial Peripheral Interface. See SPI Mode. PMCONL (Parallel Port Control Low Byte) ..............169 SETF ................................................................................399 PMEH (Parallel Port Enable High Byte) ...................171 Slave Select (SSx) ...........................................................233 PMEL (Parallel Port Enable Low Byte) ....................172 SLEEP .............................................................................400 PMMODEH (Parallel Port Mode High Byte) .............170 Software Simulator (MPLAB SIM) ...................................416 PMMODEL (Parallel Port Mode Low Byte) ..............171 Special Event Trigger. See Compare (ECCP Module). PMSTATH (Parallel Port Status High Byte) .............172 Special Features of the CPU ...........................................349 PMSTATL (Parallel Port Status Low Byte) ..............173 Special Function Registers RCON (Reset Control) .......................................56, 135 Shared Registers .......................................................82 RCSTAx (Receive Status and Control) ....................281 SPI Mode (MSSP) ...........................................................233 SSPxCON1 (MSSPx Control 1, I2C Mode) ..............245 Associated Registers ...............................................242 SSPxCON1 (MSSPx Control 1, SPI Mode) .............235 Bus Mode Compatibility ...........................................241 SSPxMSK (I2C Slave Address Mask) ......................247 Clock Speed, Interactions ........................................241 SSPxSTAT (MSSPx Status, I2C Mode) ...................244 Effects of a Reset ....................................................241 SSPxSTAT (MSSPx Status, SPI Mode) ..................234 Enabling SPI I/O ......................................................237 STATUS .....................................................................89 Master Mode ............................................................238 STKPTR (Stack Pointer) ............................................74 Master/Slave Connection .........................................237 T0CON (Timer0 Control) ..........................................191 Operation .................................................................236 T1CON (Timer1 Control) ..........................................195 Operation in Power-Managed Modes ......................241 T2CON (Timer2 Control) ..........................................201 Serial Clock ..............................................................233 T3CON (Timer3 Control) ..........................................203 Serial Data In ...........................................................233 T4CON (Timer4 Control) ..........................................207 Serial Data Out ........................................................233 TXSTAx (Transmit Status and Control) ...................280 Slave Mode ..............................................................239 UCFG (USB Configuration) ......................................314 Slave Select .............................................................233 UCON (USB Control) ...............................................312 Slave Select Synchronization ..................................239 UEIE (USB Error Interrupt Enable) ..........................330 SPI Clock .................................................................238 UEIR (USB Error Interrupt Status) ...........................329 SSPxBUF Register ..................................................238 UEPn (USB Endpoint n Control) ..............................317 SSPxSR Register ....................................................238 UIE (USB Interrupt Enable) ......................................328 Typical Connection ..................................................237 UIR (USB Interrupt Status) ......................................326 SSPOV ............................................................................269 USTAT (USB Status) ...............................................316 SSPOV Status Flag .........................................................269 WDTCON (Watchdog Timer Control) .......................359 SSPxSTAT Register RESET .............................................................................395 R/W Bit ............................................................248, 251 Reset ..................................................................................55 SSx ..................................................................................233 Brown-out Reset (BOR) .............................................55 Stack Full/Underflow Resets ..............................................75 SUBFSR ..........................................................................411 DS39775C-page 472 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY SUBFWB ..........................................................................400 Asynchronous Transmission ...................................290 SUBLW ............................................................................401 Asynchronous Transmission (Back-to-Back) ...........290 SUBULNK ........................................................................411 Automatic Baud Rate Calculation ............................288 SUBWF ............................................................................401 Auto-Wake-up Bit (WUE) During Normal Operation 293 SUBWFB ..........................................................................402 Auto-Wake-up Bit (WUE) During Sleep ...................293 SWAPF ............................................................................402 Baud Rate Generator with Clock Arbitration ............266 BRG Overflow Sequence ........................................288 T BRG Reset Due to SDAx Arbitration During Start Condi- Table Pointer Operations (table) ......................................100 tion ...................................................................275 Table Reads/Table Writes .................................................75 Bus Collision During a Repeated Start Condition (Case TBLRD .............................................................................403 1) .....................................................................276 TBLWT .............................................................................404 Bus Collision During a Repeated Start Condition (Case Timer0 ..............................................................................191 2) .....................................................................276 Associated Registers ...............................................193 Bus Collision During a Start Condition (SCLx = 0) ..275 Operation .................................................................192 Bus Collision During a Stop Condition (Case 1) ......277 Overflow Interrupt ....................................................193 Bus Collision During a Stop Condition (Case 2) ......277 Prescaler ..................................................................193 Bus Collision During Start Condition (SDAx Only) ..274 Switching Assignment ......................................193 Bus Collision for Transmit and Acknowledge ..........273 Prescaler Assignment (PSA Bit) ..............................193 Capture/Compare/PWM (Including ECCP Modules) 444 Prescaler Select (T0PS2:T0PS0 Bits) .....................193 CLKO and I/O ..........................................................439 Prescaler. See Prescaler, Timer0. Clock Synchronization .............................................259 Reads and Writes in 16-Bit Mode ............................192 Clock/Instruction Cycle ..............................................76 Source Edge Select (T0SE Bit) ................................192 EUSARTx Synchronous Receive (Master/Slave) ....455 Source Select (T0CS Bit) .........................................192 EUSARTx Synchronous Transmission (Master/Slave) . Timer1 ..............................................................................195 455 16-Bit Read/Write Mode ...........................................197 Example SPI Master Mode (CKE = 0) .....................447 Associated Registers ...............................................200 Example SPI Master Mode (CKE = 1) .....................448 Interrupt ....................................................................198 Example SPI Slave Mode (CKE = 0) .......................449 Operation .................................................................196 Example SPI Slave Mode (CKE = 1) .......................450 Oscillator ..........................................................195, 197 External Clock .........................................................437 Layout Considerations .....................................197 External Memory Bus for SLEEP (Extended Microcon- Overflow Interrupt ....................................................195 troller Mode) ............................................114, 116 Resetting, Using the ECCP Special Event Trigger ..198 External Memory Bus for TBLRD (Extended Microcon- Special Event Trigger (ECCP) .................................220 troller Mode) ............................................114, 116 TMR1H Register ......................................................195 Fail-Safe Clock Monitor ...........................................363 TMR1L Register .......................................................195 First Start Bit Timing ................................................267 Use as a Clock Source ............................................197 Full-Bridge PWM Output ..........................................225 Use as a Real-Time Clock .......................................198 Half-Bridge PWM Output .........................................224 Timer2 ..............................................................................201 I2C Acknowledge Sequence ....................................272 Associated Registers ...............................................202 I2C Bus Data ............................................................451 Interrupt ....................................................................202 I2C Bus Start/Stop Bits ............................................451 Operation .................................................................201 I2C Master Mode (7 or 10-Bit Transmission) ...........270 Output ......................................................................202 I2C Master Mode (7-Bit Reception) .........................271 PR2 Register ............................................................221 I2C Slave Mode (10-Bit Reception, SEN = 0, ADMSK = TMR2 to PR2 Match Interrupt ..................................221 01001) .............................................................255 Timer3 ..............................................................................203 I2C Slave Mode (10-Bit Reception, SEN = 0) ..........256 16-Bit Read/Write Mode ...........................................205 I2C Slave Mode (10-Bit Reception, SEN = 1) ..........261 Associated Registers ...............................................205 I2C Slave Mode (10-Bit Transmission) ....................257 Operation .................................................................204 I2C Slave Mode (7-Bit Reception, SEN = 0, ADMSK = Oscillator ..........................................................203, 205 01011) .............................................................253 Overflow Interrupt ............................................203, 205 I2C Slave Mode (7-Bit Reception, SEN = 0) ............252 Special Event Trigger (ECCP) .................................205 I2C Slave Mode (7-Bit Reception, SEN = 1) ............260 TMR3H Register ......................................................203 I2C Slave Mode (7-Bit Transmission) ......................254 TMR3L Register .......................................................203 I2C Slave Mode General Call Address Sequence (7 or Timer4 ..............................................................................207 10-Bit Address Mode) ......................................262 Associated Registers ...............................................208 I2C Stop Condition Receive or Transmit Mode ........272 MSSP Clock Shift .....................................................208 MSSPx I2C Bus Data ...............................................453 Operation .................................................................207 MSSPx I2C Bus Start/Stop Bits ...............................453 Postscaler. See Postscaler, Timer4. Parallel Master Port Read .......................................445 PR4 Register ............................................................207 Parallel Master Port Write ........................................446 Prescaler. See Prescaler, Timer4. Parallel Slave Port Read .................................176, 179 TMR4 Register .........................................................207 Parallel Slave Port Write ..................................176, 179 TMR4 to PR4 Match Interrupt ..........................207, 208 Program Memory Read ...........................................440 Timing Diagrams Program Memory Write ...........................................441 A/D Conversion ........................................................456 PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Dis- Asynchronous Reception .........................................292 © 2009 Microchip Technology Inc. DS39775C-page 473

PIC18F87J50 FAMILY abled) ...............................................................230 Modules) ..........................................................444 PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart En- CLKO and I/O Requirements ...................................439 abled) ...............................................................230 EUSARTx Synchronous Receive Requirements .....455 PWM Direction Change ...........................................227 EUSARTx Synchronous Transmission Requirements ... PWM Direction Change at Near 100% Duty Cycle ..227 455 PWM Output ............................................................214 Example SPI Mode Requirements (Master Mode, CKE = Read and Write, 8-Bit Data, Demultiplexed Address 183 0) .....................................................................447 Read, 16-Bit Data, Demultiplexed Address .............186 Example SPI Mode Requirements (Master Mode, CKE = Read, 16-Bit Multiplexed Data, Fully Multiplexed 16-Bit 1) .....................................................................448 Address ............................................................187 Example SPI Mode Requirements (Slave Mode, CKE = Read, 16-Bit Multiplexed Data, Partially Multiplexed Ad- 0) .....................................................................449 dress ................................................................186 Example SPI Slave Mode Requirements (CKE = 1) 450 Read, 8-Bit Data, Fully Multiplexed 16-Bit Address .185 External Clock Requirements ..................................437 Read, 8-Bit Data, Partially Multiplexed Address ......183 I2C Bus Data Requirements (Slave Mode) ..............452 Read, 8-Bit Data, Partially Multiplexed Address, Enable I2C Bus Start/Stop Bits Requirements (Slave Mode) ..... Strobe ..............................................................184 451 Read, 8-Bit Data, Wait States Enabled, Partially Multi- MSSPx I2C Bus Data Requirements .......................454 plexed Address ................................................183 MSSPx I2C Bus Start/Stop Bits Requirements ........453 Repeated Start Condition .........................................268 Parallel Master Port Read Requirements ................445 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer Parallel Master Port Write Requirements ................446 (OST) and Power-up Timer (PWRT) ................442 PLL Clock ................................................................438 Send Break Character Sequence ............................294 Program Memory Read Requirements ....................440 Slave Synchronization .............................................239 Program Memory Write Requirements ....................441 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) Reset, Watchdog Timer, Oscillator Start-up Timer, Pow- ............................................................................59 er-up Timer and Brown-out Reset Requirements .. SPI Mode (Master Mode) .........................................238 442 SPI Mode (Slave Mode, CKE = 0) ...........................240 Timer0 and Timer1 External Clock Requirements ...443 SPI Mode (Slave Mode, CKE = 1) ...........................240 USB Full-Speed Requirements ................................458 Synchronous Reception (Master Mode, SREN) ......297 USB Low-Speed Requirements ...............................458 Synchronous Transmission ......................................295 TSTFSZ ...........................................................................405 Synchronous Transmission (Through TXEN) ..........296 Two-Speed Start-up .................................................349, 361 Time-out Sequence on Power-up (MCLR Not Tied to Two-Word Instructions VDD), Case 1 ......................................................58 Example Cases ..........................................................77 Time-out Sequence on Power-up (MCLR Not Tied to TXSTAx Register VDD), Case 2 ......................................................59 BRGH Bit .................................................................283 Time-out Sequence on Power-up (MCLR Tied to VDD, U VDD Rise < TPWRT) ............................................58 Timer0 and Timer1 External Clock ..........................443 Universal Serial Bus Transition for Entry to Idle Mode ................................52 Address Register (UADDR) .....................................318 Transition for Entry to SEC_RUN Mode ....................49 Associated Registers ...............................................334 Transition for Entry to Sleep Mode ............................51 Buffer Descriptor Table ............................................319 Transition for Two-Speed Start-up (INTRC to HSPLL) .. Buffer Descriptors ....................................................319 361 Address Validation ...........................................322 Transition for Wake From Idle to Run Mode ..............52 Assignment in Different Buffering Modes ........324 Transition for Wake From Sleep (HSPLL) .................51 BDnSTAT Register (CPU Mode) .....................320 Transition From RC_RUN Mode to PRI_RUN Mode .50 BDnSTAT Register (SIE Mode) .......................322 Transition From SEC_RUN Mode to PRI_RUN Mode Byte Count .......................................................322 (HSPLL) .............................................................49 Example ...........................................................319 Transition to RC_RUN Mode .....................................50 Memory Map ....................................................323 USB Signal ...............................................................458 Ownership .......................................................319 Write, 16-Bit Data, Demultiplexed Address ..............186 Ping-Pong Buffering ........................................323 Write, 16-Bit Multiplexed Data, Fully Multiplexed 16-Bit Register Summary ...........................................324 Address ............................................................187 Status and Configuration .................................319 Write, 16-Bit Multiplexed Data, Partially Multiplexed Ad- Class Specifications and Drivers .............................336 dress ................................................................187 Descriptors ...............................................................336 Write, 8-Bit Data, Fully Multiplexed 16-Bit Address .185 Endpoint Control ......................................................317 Write, 8-Bit Data, Partially Multiplexed Address ......184 Enumeration ............................................................336 Write, 8-Bit Data, Partially Multiplexed Address, Enable External Pull-up Resistors .......................................315 Strobe ..............................................................185 Eye Pattern Test Enable ..........................................315 Write, 8-Bit Data, Wait States Enabled, Partially Multi- Firmware and Drivers ..............................................334 plexed Address ................................................184 Frame Number Registers ........................................318 Timing Diagrams and Specifications Frames ....................................................................335 AC Characteristics Internal Pull-up Resistors .........................................315 Internal RC Accuracy .......................................438 Internal Transceiver .................................................313 Capture/Compare/PWM Requirements (Including ECCP Interrupts .................................................................325 and USB Transactions .....................................325 DS39775C-page 474 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY Layered Framework .................................................335 Oscillator Requirements ...........................................334 Overview ..........................................................311, 335 Ping-Pong Buffer Configuration ...............................315 Power .......................................................................335 Power Modes ...........................................................331 Bus Power Only ...............................................331 Dual Power with Self-Power Dominance .........332 Self-Power Only ...............................................331 RAM .........................................................................318 Memory Map ....................................................318 Speed .......................................................................336 Status and Control ...................................................312 Transfer Types .........................................................335 UFRMH:UFRML Registers ......................................318 USB RAM Serial Interface Engine (SIE) .....................................78 USB Specifications ..........................................................434 USB. See Universal Serial Bus. V VDDCORE/VCAP Pin ...........................................................360 Voltage Reference Specifications ....................................433 Voltage Regulator (On-Chip) ...........................................360 Operation in Sleep Mode .........................................361 W Watchdog Timer (WDT) ...........................................349, 358 Associated Registers ...............................................359 Control Register .......................................................358 During Oscillator Failure ..........................................362 Programming Considerations ..................................358 WCOL ......................................................267, 268, 269, 272 WCOL Status Flag ...................................267, 268, 269, 272 WWW Address .................................................................477 WWW, On-Line Support ......................................................7 X XORLW ............................................................................405 XORWF ............................................................................406 © 2009 Microchip Technology Inc. DS39775C-page 475

PIC18F87J50 FAMILY NOTES: DS39775C-page 476 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS39775C-page 477

PIC18F87J50 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F87J50 Family Literature Number: DS39775C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39775C-page 478 © 2009 Microchip Technology Inc.

PIC18F87J50 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18F86J50-I/PT 301 = Industrial temp., Range TQFP package, QTP pattern #301. b) PIC18F66J55T-I/PT = Tape and reel, Industrial temp., TQFP package. Device PIC18F65J50/66J50/66J55/67J50(1), PIC18F85J50/86J50/86J55/87J50(1), PIC18F65J50/66J50/66J55/67J50T(2), PIC18F85J50/86J50/86J55/87J50T(2); Temperature Range I = -40°C to +85°C (Industrial) Package PT = TQFP (Thin Quad Flatpack) Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) Note1: F = Standard Voltage Range 2: T = In tape and reel © 2009 Microchip Technology Inc. DS39775C-page 479

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18F65J50-I/PT PIC18F65J50T-I/PT PIC18F66J50-I/PT PIC18F66J50T-I/PT PIC18F66J55-I/PT PIC18F66J55T- I/PT PIC18F67J50-I/PT PIC18F67J50T-I/PT PIC18F85J50-I/PT PIC18F85J50T-I/PT PIC18F86J50-I/PT PIC18F86J50T-I/PT PIC18F86J55-I/PT PIC18F86J55T-I/PT PIC18F87J50-I/PT PIC18F87J50T-I/PT