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PIC18F85J10-I/PT产品简介:
ICGOO电子元器件商城为您提供PIC18F85J10-I/PT由Microchip设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 PIC18F85J10-I/PT价格参考。MicrochipPIC18F85J10-I/PT封装/规格:嵌入式 - 微控制器, PIC 微控制器 IC PIC® 18J 8-位 40MHz 32KB(16K x 16) 闪存 80-TQFP(12x12)。您可以下载PIC18F85J10-I/PT参考资料、Datasheet数据手册功能说明书,资料中有PIC18F85J10-I/PT 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
A/D位大小 | 10 bit |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC MCU 8BIT 32KB FLASH 80TQFP8位微控制器 -MCU 32 KB FL 2 KB RAM |
EEPROM容量 | - |
产品分类 | |
I/O数 | 66 |
品牌 | Microchip Technology |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 嵌入式处理器和控制器,微控制器 - MCU,8位微控制器 -MCU,Microchip Technology PIC18F85J10-I/PTPIC® 18J |
数据手册 | http://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en022070点击此处下载产品Datasheet点击此处下载产品Datasheethttp://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en531149http://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en531665http://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en021030http://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en535068http://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en531662 |
产品型号 | PIC18F85J10-I/PT |
PCN设计/规格 | http://www.microchip.com/mymicrochip/NotificationDetails.aspx?id=5624&print=view |
RAM容量 | 2K x 8 |
产品培训模块 | http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=2046http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=24868http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=25053 |
产品目录页面 | |
产品种类 | 8位微控制器 -MCU |
供应商器件封装 | 80-TQFP(12x12) |
其它名称 | PIC18F85J10IPT |
包装 | 托盘 |
可用A/D通道 | 15 |
可编程输入/输出端数量 | 66 |
商标 | Microchip Technology |
处理器系列 | PIC18 |
外设 | 欠压检测/复位,POR,PWM,WDT |
安装风格 | SMD/SMT |
定时器数量 | 5 Timer |
封装 | Tray |
封装/外壳 | 80-TQFP |
封装/箱体 | TQFP-80 |
工作温度 | -40°C ~ 85°C |
工作电源电压 | 3.6 V |
工厂包装数量 | 119 |
振荡器类型 | 内部 |
接口类型 | EUSART, I2C, SPI |
数据RAM大小 | 2 kB |
数据Ram类型 | SRAM |
数据总线宽度 | 8 bit |
数据转换器 | A/D 15x10b |
最大工作温度 | + 85 C |
最大时钟频率 | 40 MHz |
最小工作温度 | - 40 C |
标准包装 | 119 |
核心 | PIC |
核心处理器 | PIC |
核心尺寸 | 8-位 |
片上ADC | Yes |
片上DAC | Without DAC |
电压-电源(Vcc/Vdd) | 2 V ~ 3.6 V |
电源电压-最大 | 3.6 V |
电源电压-最小 | 2.7 V |
程序存储器大小 | 32 kB |
程序存储器类型 | Flash |
程序存储容量 | 32KB(16K x 16) |
系列 | PIC18 |
输入/输出端数量 | 66 I/O |
连接性 | EBI/EMI, I²C, SPI, UART/USART |
速度 | 40MHz |
配用 | /product-detail/zh/MA180015/MA180015-ND/1279969/product-detail/zh/AC162062/AC162062-ND/1015413/product-detail/zh/AC164328/AC164328-ND/957547 |
PIC18F87J10 Family Data Sheet 64/80-Pin, High-Performance 1-Mbit Flash Microcontrollers with nanoWatt Technology © 2009 Microchip Technology Inc. DS39663F
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of Microchip MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries. WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard, arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39663F-page ii © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology Special Microcontroller Features: Peripheral Highlights: • Operating Voltage Range: 2.0V to 3.6V • High-Current Sink/Source 25mA/25mA • 5.5V Tolerant Input (digital pins only) (PORTB and PORTC) • On-Chip 2.5V Regulator • Four Programmable External Interrupts • Low-Power, High-Speed CMOS Flash Technology • Four Input Change Interrupts • C Compiler Optimized Architecture: • Two Capture/Compare/PWM (CCP) modules - Optional extended instruction set designed to • Three Enhanced Capture/Compare/PWM (ECCP) optimize re-entrant code modules: • Priority Levels for Interrupts - One, two or four PWM outputs • 8 x 8 Single-Cycle Hardware Multiplier - Selectable polarity • Extended Watchdog Timer (WDT): - Programmable dead time - Programmable period from 4ms to 131s - Auto-shutdown and auto-restart • Single-Supply In-Circuit Serial Programming™ • Two Master Synchronous Serial Port (MSSP) (ICSP™) via Two Pins modules Supporting 3-Wire SPI (all 4 modes) and I2C™ Master and Slave modes • In-Circuit Debug (ICD) with Three Break points via Two Pins • Two Enhanced Addressable USART modules: • Power-Managed modes: - Supports RS-485, RS-232 and LIN/2602 - Run: CPU on, peripherals on - Auto-wake-up on Start bit - Idle: CPU off, peripherals on - Auto-Baud Detect (ABD) - Sleep: CPU off, peripherals off • 10-Bit, up to 15-Channel Analog-to-Digital Converter module (A/D): • Flash Program Memory: - Auto-acquisition capability - 1000 erase/write cycle endurance typical - Conversion available during Sleep - 20 year retention minimum - Self-calibration feature - Self-write capability during normal operation • Dual Analog Comparators with Input Multiplexing Flexible Oscillator Structure: External Memory Bus • Two Crystal modes, up to 40MHz (PIC18F8XJ10/8XJ15 only): • 4x Phase Lock Loop (PLL) • Address Capability of up to 2Mbytes • Two External Clock modes, up to 40 MHz • 8-Bit or 16-Bit Interface • Internal 31kHz Oscillator • 12-Bit, 16-Bit and 20-Bit Addressing modes • Secondary Oscillator using Timer1 @ 32 kHz • Two-Speed Oscillator Start-up • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops © 2009 Microchip Technology Inc. DS39663F-page 1
PIC18F87J10 FAMILY Device (FblyPatsreohsg)ra#mI nS siMntregumlcet-oWiorynosrd SRM(bAeyMmte oDsra)yta I/O A1/D0- B(ciht) (EPCCWCCPMP/) SMPSISPMI2aCs™ter EUSART omparators Timers8/16-Bit xternal Bus C E PIC18F65J10 32K 16384 2048 50 11 2/3 2 Y Y 2 2 2/3 N PIC18F65J15 48K 24576 2048 50 11 2/3 2 Y Y 2 2 2/3 N PIC18F66J10 64K 32768 2048 50 11 2/3 2 Y Y 2 2 2/3 N PIC18F66J15 96K 49152 3936 50 11 2/3 2 Y Y 2 2 2/3 N PIC18F67J10 128K 65536 3936 50 11 2/3 2 Y Y 2 2 2/3 N PIC18F85J10 32K 16384 2048 66 15 2/3 2 Y Y 2 2 2/3 Y PIC18F85J15 48K 24576 2048 66 15 2/3 2 Y Y 2 2 2/3 Y PIC18F86J10 64K 32768 2048 66 15 2/3 2 Y Y 2 2 2/3 Y PIC18F86J15 96K 49152 3936 66 15 2/3 2 Y Y 2 2 2/3 Y PIC18F87J10 128K 65536 3936 66 15 2/3 2 Y Y 2 2 2/3 Y Pin Diagrams 64-Pin TQFP Pins are up to 5.5V tolerant 1)(1)/P2A DO2DI2/SDA2CK2/SCL2S2 B (2 SSSS S/P23C3B1C1BCCPSP0 SP1SP2SP3SP4/SP5/SP6/SP7/ CPPPPEP PPPPPPP E2/E3/E4/E5/E6/E7/D0/ DD SS D1/D2/D3/D4/D5/D6/D7/ RRRRRRRVVRRRRRRR 4321 098765 4321 09 6666 655555 5555 54 RE1/WR/P2C 1 48 RB0/INT0/FLT0 RE0/RD/P2D 2 47 RB1/INT1 RG0/ECCP3/P3A 3 46 RB2/INT2 RG1/TX2/CK2 4 45 RB3/INT3 RG2/RX2/DT2 5 44 RB4/KBI0 RG3/CCP4/P3D 6 43 RB5/KBI1 MCLR 7 42 RB6/KBI2/PGC PIC18F6XJ10 RG4/CCP5/P1D 8 41 VSS VSS 9 PIC18F6XJ15 40 OSC2/CLKO VDDCORE/VCAP 10 39 OSC1/CLKI RF7/SS1 11 38 VDD RF6/AN11 12 37 RB7/KBI3/PGD RF5/AN10/CVREF 13 36 RC5/SDO1 RF4/AN9 14 35 RC4/SDI1/SDA1 RF3/AN8 15 34 RC3/SCK1/SCL1 RF2/AN7/C1OUT 16 33 RC2/ECCP1/P1A 7890123456789012 1112222222222333 F1/AN6/C2OUTENVREGAVDD AVSSRA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1RA0/AN0VSS VDD RA5/AN4RA4/T0CKI(1)(1)ECCP2/P2AT1OSO/T13CKIRC6/TX1/CK1RC7/RX1/DT1 R SI/C0/ OR 1 T 1/ C R Note 1: The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit. DS39663F-page 2 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY Pin Diagrams (Continued) 80-Pin TQFP Pins are up to 5.5V tolerant A17 A16 AD10/CS/P2B(2)AD11/P3C(2)AD12/P3B(2)AD13/P1C(2)AD14/P1B(1)(1)AD15/ECCP2/P2A AD0/PSP0 AD1/PSP1 AD2/PSP2 AD3/PSP3 AD4/PSP4/SDO2 AD5/PSP5/SDI2/SDA2 AD6/PSP6/SCK2/SCL2 AD7/PSP7/SS2 ALE OE H1/ H0/ E2/ E3/ E4/ E5/ E6/ E7/ D0/ DD SS D1/ D2/ D3/ D4/ D5/ D6/ D7/ J0/ J1/ R R R R R R R R R V V R R R R R R R R R 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 RH2/A18 1 60 RJ2/WRL RH3/A19 2 59 RJ3/WRH RE1/AD9/WR/P2C 3 58 RB0/INT0/FLT0 RE0/AD8/RD/P2D 4 57 RB1/INT1 RG0/ECCP3/P3A 5 56 RB2/INT2 RG1/TX2/CK2 6 55 RB3/INT3/ECCP2(1)/P2A(1) RG2/RX2/DT2 7 54 RB4/KBI0 RG3/CCP4/P3D 8 53 RB5/KBI1 MCLR 9 52 RB6/KBI2/PGC PIC18F8XJ10 RG4/CCP5/P1D 10 51 VSS VSS 11 PIC18F8XJ15 50 OSC2/CLKO VDDCORE/VCAP 12 49 OSC1/CLKI RF7/SS1 13 48 VDD RF6/AN11 14 47 RB7/KBI3/PGD RF5/AN10/CVREF 15 46 RC5/SDO1 RF4/AN9 16 45 RC4/SDI1/SDA1 RF3/AN8 17 44 RC3/SCK1/SCL1 RF2/AN7/C1OUT 18 43 RC2/ECCP1/P1A RH7/AN15/P1B(2) 19 42 RJ7/UB RH6/AN14/P1C(2) 20 41 RJ6/LB 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 (2)RH5/AN13/P3B(2)RH4/AN12/P3C RF1/AN6/C2OUT ENVREG AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0 VSS VDD RA5/AN4 RA4/T0CKI(1)(1)SI/ECCP2/P2A C0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 RJ4/BA0 RJ5/CE O R 1 T 1/ C R Note 1: The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit and the program memory mode. 2: P1B, P1C, P3B and P3C pin placement depends on the setting of the ECCPMX Configuration bit. © 2009 Microchip Technology Inc. DS39663F-page 3
PIC18F87J10 FAMILY Table of Contents 1.0 Device Overview..........................................................................................................................................................................5 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers...................................................................................................27 3.0 Oscillator Configurations............................................................................................................................................................31 4.0 Power-Managed Modes.............................................................................................................................................................39 5.0 Reset..........................................................................................................................................................................................47 6.0 Memory Organization.................................................................................................................................................................59 7.0 Flash Program Memory..............................................................................................................................................................85 8.0 External Memory Bus.................................................................................................................................................................95 9.0 8 x 8 Hardware Multiplier..........................................................................................................................................................107 10.0 Interrupts..................................................................................................................................................................................109 11.0 I/O Ports...................................................................................................................................................................................125 12.0 Timer0 Module.........................................................................................................................................................................151 13.0 Timer1 Module.........................................................................................................................................................................155 14.0 Timer2 Module.........................................................................................................................................................................161 15.0 Timer3 Module.........................................................................................................................................................................163 16.0 Timer4 Module.........................................................................................................................................................................167 17.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................169 18.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................177 19.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................193 20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................239 21.0 10-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................261 22.0 Comparator Module..................................................................................................................................................................271 23.0 Comparator Voltage Reference Module...................................................................................................................................277 24.0 Special Features of the CPU....................................................................................................................................................281 25.0 Instruction Set Summary..........................................................................................................................................................293 26.0 Development Support...............................................................................................................................................................343 27.0 Electrical Characteristics..........................................................................................................................................................347 28.0 Packaging Information..............................................................................................................................................................385 Appendix A: Migration Between High-End Device Families...............................................................................................................391 Appendix B: Revision History.............................................................................................................................................................393 Index..................................................................................................................................................................................................395 The Microchip Web Site.....................................................................................................................................................................405 Customer Change Notification Service..............................................................................................................................................405 Customer Support..............................................................................................................................................................................405 Reader Response..............................................................................................................................................................................406 Product Identification System.............................................................................................................................................................407 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39663F-page 4 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 1.0 DEVICE OVERVIEW The internal oscillator block provides a stable reference source that gives the family additional features for This document contains device specific information for robust operation: the following devices: • Fail-Safe Clock Monitor: This option constantly • PIC18F65J10 • PIC18F85J10 monitors the main clock source against a reference signal provided by the internal oscillator. If a clock • PIC18F65J15 • PIC18F85J15 failure occurs, the controller is switched to the • PIC18F66J10 • PIC18F86J10 internal oscillator, allowing for continued low-speed • PIC18F66J15 • PIC18F86J15 operation or a safe application shutdown. • PIC18F67J10 • PIC18F87J10 • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source This family introduces a new line of low-voltage devices from Power-on Reset, or wake-up from Sleep with the main traditional advantage of all PIC18 micro- mode, until the primary clock source is available. controllers – namely, high computational performance and a rich feature set – at an extremely competitive 1.1.3 EXPANDED MEMORY price point. These features make the PIC18F87J10 family a logical choice for many high-performance The PIC18F87J10 family provides ample room for applications where cost is a primary consideration. application code, from 32Kbytes to 128Kbytes of code space. The Flash cells for program memory are rated to last up to 100 erase/write cycles. The PIC18F87J10 1.1 Core Features family also provides plenty of room for dynamic application data, with up to 3936bytes of data RAM. 1.1.1 nanoWatt TECHNOLOGY All of the devices in the PIC18F87J10 family incorporate 1.1.4 EXTERNAL MEMORY BUS a range of features that can significantly reduce power In the unlikely event that 128Kbytes of memory are consumption during operation. Key items include: inadequate for an application, the 80-pin members of • Alternate Run Modes: By clocking the controller the PIC18F87J10 family also implement an external from the Timer1 source or the internal RC oscilla- memory bus. This allows the controller’s internal tor, power consumption during code execution program counter to address a memory space of up to can be reduced by as much as 90%. 2Mbytes, permitting a level of data access that few • Multiple Idle Modes: The controller can also run 8-bit devices can claim. This allows additional memory with its CPU core disabled but the peripherals still options, including: active. In these states, power consumption can be • Using combinations of on-chip and external reduced even further, to as little as 4% of normal memory up to the 2-Mbyte limit operation requirements. • Using external Flash memory for reprogrammable • On-the-Fly Mode Switching: The application code or large data tables power-managed modes are invoked by user code • Using external RAM devices for storing large during operation, allowing the user to incorporate amounts of variable data power-saving ideas into their application’s software design. 1.1.5 EXTENDED INSTRUCTION SET The PIC18F87J10 family implements the optional 1.1.2 OSCILLATOR OPTIONS AND extension to the PIC18 instruction set, adding 8 new FEATURES instructions and an Indexed Addressing mode. All of the devices in the PIC18F87J10 family offer five Enabled as a device configuration option, the extension different oscillator options, allowing users a range of has been specifically designed to optimize re-entrant choices in developing application hardware. These application code originally developed in high-level include: languages, such as ‘C’. • Two Crystal modes, using crystals or ceramic resonators. • Two External Clock modes, offering the option of a divide-by-4 clock output. • A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes which allows clock speeds of up to 40MHz. • An internal RC oscillator with a fixed 31-kHz output which provides an extremely low-power option for timing-insensitive applications. © 2009 Microchip Technology Inc. DS39663F-page 5
PIC18F87J10 FAMILY 1.1.6 EASY MIGRATION 1.3 Details on Individual Family Members Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth Devices in the PIC18F87J10 family are available in migration path as applications grow and evolve. 64-pin and 80-pin packages. Block diagrams for the The consistent pinout scheme used throughout the two groups are shown in Figure1-1 and Figure1-2. entire family also aids in migrating to the next larger The devices are differentiated from each other in four device. This is true when moving between the 64-pin ways: members, between the 80-pin members, or even jumping from 64-pin to 80-pin devices. 1. Flash program memory (six sizes, ranging from 32Kbytes for PIC18FX5J10 devices to The PIC18F87J10 family is also pin compatible with 128Kbytes for PIC18FX7J10). other PIC18 families, such as the PIC18F8720 and 2. Data RAM (2048 bytes for PIC18F8722. This allows a new dimension to the PIC18FX5J10/X5J15/X6J10 devices, 3936 evolution of applications, allowing developers to select bytes for PIC18FX6J15/X7J10 devices). different price points within Microchip’s PIC18 portfolio, while maintaining the same feature set. 3. A/D channels (11 for 64-pin devices, 15 for 80-pin devices). 1.2 Other Special Features 4. I/O ports (7 bidirectional ports on 64-pin devices, 9 bidirectional ports on 80-pin devices). • Communications: The PIC18F87J10 family All other features for devices in this family are identical. incorporates a range of serial communication These are summarized in Table1-1 and Table1-2. peripherals, including 2 independent Enhanced USARTs and 2 Master SSP modules, capable of The pinouts for all devices are listed in Table1-3 and both SPI and I2C™ (Master and Slave) modes of Table1-4. operation. In addition, one of the general purpose I/O ports can be reconfigured as an 8-bit Parallel Slave Port for direct processor-to-processor communications. • CCP Modules: All devices in the family incorporate two Capture/Compare/PWM (CCP) modules and three Enhanced CCP modules to maximize flexibility in control applications. Up to four different time bases may be used to perform several different operations at once. Each of the three ECCPs offers up to four PWM outputs, allowing for a total of 12 PWMs. The ECCPs also offer many beneficial features, including polarity selection, programmable dead time, auto-shutdown and restart and Half-Bridge and Full-Bridge Output modes. • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section27.0 “Electrical Characteristics” for time-out periods. DS39663F-page 6 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F87J10 FAMILY (64-PIN DEVICES) Features PIC18F65J10 PIC18F65J15 PIC18F66J10 PIC18F66J15 PIC18F67J10 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 32K 48K 64K 96K 128K Program Memory (Instructions) 16384 24576 32768 49152 65536 Data Memory (Bytes) 2048 2048 2048 3936 3936 Interrupt Sources 27 I/O Ports Ports A, B, C, D, E, F, G Timers 5 Capture/Compare/PWM Modules 2 Enhanced Capture/ 3 Compare/PWM Modules Serial Communications MSSP (2), Enhanced USART (2) Parallel Communications (PSP) Yes 10-Bit Analog-to-Digital Module 11 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set enabled Packages 64-pin TQFP TABLE 1-2: DEVICE FEATURES FOR THE PIC18F87J10 FAMILY (80-PIN DEVICES) Features PIC18F85J10 PIC18F85J15 PIC18F86J10 PIC18F86J15 PIC18F87J10 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 32K 48K 64K 96K 128K Program Memory (Instructions) 16384 24576 32768 49152 65536 Data Memory (Bytes) 2048 2048 2048 3936 3936 Interrupt Sources 27 I/O Ports Ports A, B, C, D, E, F, G, H, J Timers 5 Capture/Compare/PWM Modules 2 Enhanced Capture/ 3 Compare/PWM Modules Serial Communications MSSP (2), Enhanced USART (2) Parallel Communications (PSP) Yes 10-Bit Analog-to-Digital Module 15 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set enabled Packages 80-pin TQFP © 2009 Microchip Technology Inc. DS39663F-page 7
PIC18F87J10 FAMILY FIGURE 1-1: PIC18F6XJ10/6XJ15 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch inc/dec logic 8 8 RA0:RA5(1) Data Memory (2.0, 3.9 21 PCLAT U PCLATH Kbytes) 20 Address Latch PCU PCH PCL Program Counter 12 PORTB Data Address<12> RB0:RB7(1) 31 Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (96Kbytes) FSR1 Data Latch FSR2 12 PORTC inc/dec RC0:RC7(1) 8 logic Table Latch Address ROM Latch Instruction Bus <16> Decode PORTD IR RD0:RD7(1) 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL PORTE RE0:RE7(1) 8 x 8 Multiply 3 OSC2/CLKO Timing Power-up 8 OSC1/CLKI Generation Timer BITOP W Oscillator 8 8 8 Start-up Timer INTRC Oscillator Power-on 8 8 PORTF Reset RF1:RF7(1) Precision ALU<8> Band Gap Watchdog Reference Timer 8 ENVREG Brown-out Voltage Reset(2) Regulator PORTG RG0:RG4(1) VDDCORE/VCAP VDD,VSS MCLR ADC 10-Bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators ECCP1 ECCP2 ECCP3 CCP4 CCP5 EUSART1 EUSART2 MSSP1 MSSP2 Note 1: See Table1-3 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. DS39663F-page 8 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 1-2: PIC18F8XJ10/8XJ15 (80-PIN) BLOCK DIAGRAM Data Bus<8> PORTA Table Pointer<21> 8 8 Data Latch RA0:RA5(1) Data Memory (2.0, 3.9 inc/dec logic PCLAT U PCLATH Kbytes) 21 20 Address Latch PCU PCH PCL PORTB Program Counter 12 RB0:RB7(1) Data Address<12> 31 Level Stack nterface PArod(1gd2rra8emsK sbM yLeteamstc)ohry STKPTR BSR4 FFSSRR1012 ABccaen4sks RPCO0:RRTCC7(1) us I Data Latch FSR2 12 B m ste 8 inloc/gdiecc PORTD Sy Table Latch RD0:RD7(1) Address ROM Latch Decode Instruction Bus <16> PORTE IR RE0:RE7(1) AD15:AD0, A19:A16 (Multiplexed with PORTD, 8 PORTE and PORTH) PORTF PRODH PRODL State Machine IDnestcroudcteio &n RF1:RF7(1) Control Signals Control 8 x 8 Multiply 3 8 BITOP W OSC2/CLKO Timing Power-up 8 8 8 PORTG OSC1/CLKI Generation Timer RG0:RG4(1) Oscillator 8 8 Start-up Timer INTRC Oscillator Power-on ALU<8> PORTH Reset Precision 8 RH0:RH7(1) Band Gap Watchdog Reference Timer ENVREG Brown-out RVeoglutalagteor Reset(2) PORTJ RJ0:RJ7(1) VDDCORE/VCAP VDD,VSS MCLR ADC 10-Bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators ECCP1 ECCP2 ECCP3 CCP4 CCP5 EUSART1 EUSART2 MSSP1 MSSP2 Note 1: See Table1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. DS39663F-page 9
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type TQFP MCLR 7 I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OSC1/CLKI 39 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) OSC2/CLKO 40 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. PORTA is a bidirectional I/O port. RA0/AN0 24 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 23 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF- 22 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 21 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 28 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4 27 RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. DS39663F-page 10 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 48 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. FLT0 I ST ECCP1/2/3 Fault input. RB1/INT1 47 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. RB2/INT2 46 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. RB3/INT3 45 RB3 I/O TTL Digital I/O. INT3 I ST External interrupt 3. RB4/KBI0 44 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1 43 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. RB6/KBI2/PGC 42 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 37 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39663F-page 11
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 30 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/ECCP2/P2A 29 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. ECCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. P2A(1) O — ECCP2 PWM output A. RC2/ECCP1/P1A 33 RC2 I/O ST Digital I/O. ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output. P1A O — ECCP1 PWM output A. RC3/SCK1/SCL1 34 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O I2C/SMB Synchronous serial clock input/output for I2C™ mode. RC4/SDI1/SDA1 35 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O I2C/SMB I2C data I/O. RC5/SDO1 36 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. RC6/TX1/CK1 31 RC6 I/O ST Digital I/O. TX1 O — EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1). RC7/RX1/DT1 32 RC7 I/O ST Digital I/O. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. DS39663F-page 12 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTD is a bidirectional I/O port. RD0/PSP0 58 RD0 I/O ST Digital I/O. PSP0 I/O TTL Parallel Slave Port data. RD1/PSP1 55 RD1 I/O ST Digital I/O. PSP1 I/O TTL Parallel Slave Port data. RD2/PSP2 54 RD2 I/O ST Digital I/O. PSP2 I/O TTL Parallel Slave Port data. RD3/PSP3 53 RD3 I/O ST Digital I/O. PSP3 I/O TTL Parallel Slave Port data. RD4/PSP4/SDO2 52 RD4 I/O ST Digital I/O. PSP4 I/O TTL Parallel Slave Port data. SDO2 O — SPI data out. RD5/PSP5/SDI2/SDA2 51 RD5 I/O ST Digital I/O. PSP5 I/O TTL Parallel Slave Port data. SDI2 I ST SPI data in. SDA2 I/O I2C/SMB I2C™ data I/O. RD6/PSP6/SCK2/SCL2 50 RD6 I/O ST Digital I/O. PSP6 I/O TTL Parallel Slave Port data. SCK2 I/O ST Synchronous serial clock input/output for SPI mode. SCL2 I/O I2C/SMB Synchronous serial clock input/output for I2C mode. RD7/PSP7/SS2 49 RD7 I/O ST Digital I/O. PSP7 I/O TTL Parallel Slave Port data. SS2 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39663F-page 13
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTE is a bidirectional I/O port. RE0/RD/P2D 2 RE0 I/O ST Digital I/O. RD I TTL Read control for Parallel Slave Port. P2D O — ECCP2 PWM output D. RE1/WR/P2C 1 RE1 I/O ST Digital I/O. WR I TTL Write control for Parallel Slave Port. P2C O — ECCP2 PWM output C. RE2/CS/P2B 64 RE2 I/O ST Digital I/O. CS I TTL Chip select control for Parallel Slave Port. P2B O — ECCP2 PWM output B. RE3/P3C 63 RE3 I/O ST Digital I/O. P3C O — ECCP3 PWM output C. RE4/P3B 62 RE4 I/O ST Digital I/O. P3B O — ECCP3 PWM output B. RE5/P1C 61 RE5 I/O ST Digital I/O. P1C O — ECCP1 PWM output C. RE6/P1B 60 RE6 I/O ST Digital I/O. P1B O — ECCP1 PWM output B. RE7/ECCP2/P2A 59 RE7 I/O ST Digital I/O. ECCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. P2A(2) O — ECCP2 PWM output A. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. DS39663F-page 14 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTF is a bidirectional I/O port. RF1/AN6/C2OUT 17 RF1 I/O ST Digital I/O. AN6 I Analog Analog input 6. C2OUT O — Comparator 2 output. RF2/AN7/C1OUT 16 RF2 I/O ST Digital I/O. AN7 I Analog Analog input 7. C1OUT O — Comparator 1 output. RF3/AN8 15 RF3 I/O ST Digital I/O. AN8 I Analog Analog input 8. RF4/AN9 14 RF4 I/O ST Digital I/O. AN9 I Analog Analog input 9. RF5/AN10/CVREF 13 RF5 I/O ST Digital I/O. AN10 I Analog Analog input 10. CVREF O — Comparator reference voltage output. RF6/AN11 12 RF6 I/O ST Digital I/O. AN11 I Analog Analog input 11. RF7/SS1 11 RF7 I/O ST Digital I/O. SS1 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39663F-page 15
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTG is a bidirectional I/O port. RG0/ECCP3/P3A 3 RG0 I/O ST Digital I/O. ECCP3 I/O ST Capture 3 input/Compare 3 output/PWM 3 output. P3A O — ECCP3 PWM output A. RG1/TX2/CK2 4 RG1 I/O ST Digital I/O. TX2 O — EUSART2 asynchronous transmit. CK2 I/O ST EUSART2 synchronous clock (see related RX2/DT2). RG2/RX2/DT2 5 RG2 I/O ST Digital I/O. RX2 I ST EUSART2 asynchronous receive. DT2 I/O ST EUSART2 synchronous data (see related TX2/CK2). RG3/CCP4/P3D 6 RG3 I/O ST Digital I/O. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM 4 output. P3D O — ECCP3 PWM output D. RG4/CCP5/P1D 8 RG4 I/O ST Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output. P1D O — ECCP1 PWM output D. VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins. VDD 26, 38, 57 P — Positive supply for peripheral digital logic and I/O pins. AVSS 20 P — Ground reference for analog modules. AVDD 19 P — Positive supply for analog modules. ENVREG 18 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP 10 Core logic power or external filter capacitor connection. VDDCORE P — Positive supply for microcontroller core logic (regulator disabled). VCAP P — External filter capacitor connection (regulator enabled). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. DS39663F-page 16 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type TQFP MCLR 9 I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OSC1/CLKI 49 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) OSC2/CLKO 50 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. PORTA is a bidirectional I/O port. RA0/AN0 30 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 29 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF- 28 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 27 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 34 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4 33 RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. DS39663F-page 17
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 58 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. FLT0 I ST ECCP1/2/3 Fault input. RB1/INT1 57 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. RB2/INT2 56 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. RB3/INT3/ECCP2/P2A 55 RB3 I/O TTL Digital I/O. INT3 I ST External interrupt 3. ECCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. P2A(1) O — ECCP2 PWM output A. RB4/KBI0 54 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1 53 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. RB6/KBI2/PGC 52 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 47 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39663F-page 18 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 36 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/ECCP2/P2A 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. ECCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. P2A(2) O — ECCP2 PWM output A. RC2/ECCP1/P1A 43 RC2 I/O ST Digital I/O. ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output. P1A O — ECCP1 PWM output A. RC3/SCK1/SCL1 44 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O I2C/SMB Synchronous serial clock input/output for I2C™ mode. RC4/SDI1/SDA1 45 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O I2C/SMB I2C data I/O. RC5/SDO1 46 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. RC6/TX1/CK1 37 RC6 I/O ST Digital I/O. TX1 O — EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1). RC7/RX1/DT1 38 RC7 I/O ST Digital I/O. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. DS39663F-page 19
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTD is a bidirectional I/O port. RD0/AD0/PSP0 72 RD0 I/O ST Digital I/O. AD0 I/O TTL External memory address/data 0. PSP0 I/O TTL Parallel Slave Port data. RD1/AD1/PSP1 69 RD1 I/O ST Digital I/O. AD1 I/O TTL External memory address/data 1. PSP1 I/O TTL Parallel Slave Port data. RD2/AD2/PSP2 68 RD2 I/O ST Digital I/O. AD2 I/O TTL External memory address/data 2. PSP2 I/O TTL Parallel Slave Port data. RD3/AD3/PSP3 67 RD3 I/O ST Digital I/O. AD3 I/O TTL External memory address/data 3. PSP3 I/O TTL Parallel Slave Port data. RD4/AD4/PSP4/SDO2 66 RD4 I/O ST Digital I/O. AD4 I/O TTL External memory address/data 4. PSP4 I/O TTL Parallel Slave Port data. SDO2 O — SPI data out. RD5/AD5/PSP5/ 65 SDI2/SDA2 RD5 I/O ST Digital I/O. AD5 I/O TTL External memory address/data 5. PSP5 I/O TTL Parallel Slave Port data. SDI2 I ST SPI data in. SDA2 I/O I2C/SMB I2C™ data I/O. RD6/AD6/PSP6/ 64 SCK2/SCL2 RD6 I/O ST Digital I/O. AD6 I/O TTL External memory address/data 6. PSP6 I/O TTL Parallel Slave Port data. SCK2 I/O ST Synchronous serial clock input/output for SPI mode. SCL2 I/O I2C/SMB Synchronous serial clock input/output for I2C mode. RD7/AD7/PSP7/SS2 63 RD7 I/O ST Digital I/O. AD7 I/O TTL External memory address/data 7. PSP7 I/O TTL Parallel Slave Port data. SS2 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39663F-page 20 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTE is a bidirectional I/O port. RE0/AD8/RD/P2D 4 RE0 I/O ST Digital I/O. AD8 I/O TTL External memory address/data 8. RD I TTL Read control for Parallel Slave Port. P2D O — ECCP2 PWM output D. RE1/AD9/WR/P2C 3 RE1 I/O ST Digital I/O. AD9 I/O TTL External memory address/data 9. WR I TTL Write control for Parallel Slave Port. P2C O — ECCP2 PWM output C. RE2/AD10/CS/P2B 78 RE2 I/O ST Digital I/O. AD10 I/O TTL External memory address/data 10. CS I TTL Chip select control for Parallel Slave Port. P2B O — ECCP2 PWM output B. RE3/AD11/P3C 77 RE3 I/O ST Digital I/O. AD11 I/O TTL External memory address/data 11. P3C(3) O — ECCP3 PWM output C. RE4/AD12/P3B 76 RE4 I/O ST Digital I/O. AD12 I/O TTL External memory address/data 12. P3B(3) O — ECCP3 PWM output B. RE5/AD13/P1C 75 RE5 I/O ST Digital I/O. AD13 I/O TTL External memory address/data 13. P1C(3) O — ECCP1 PWM output C. RE6/AD14/P1B 74 RE6 I/O ST Digital I/O. AD14 I/O TTL External memory address/data 14. P1B(3) O — ECCP1 PWM output B. RE7/AD15/ECCP2/P2A 73 RE7 I/O ST Digital I/O. AD15 I/O TTL External memory address/data 15. ECCP2(4) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. P2A(4) O — ECCP2 PWM output A. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. DS39663F-page 21
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTF is a bidirectional I/O port. RF1/AN6/C2OUT 23 RF1 I/O ST Digital I/O. AN6 I Analog Analog input 6. C2OUT O — Comparator 2 output. RF2/AN7/C1OUT 18 RF2 I/O ST Digital I/O. AN7 I Analog Analog input 7. C1OUT O — Comparator 1 output. RF3/AN8 17 RF3 I/O ST Digital I/O. AN8 I Analog Analog input 8. RF4/AN9 16 RF4 I/O ST Digital I/O. AN9 I Analog Analog input 9. RF5/AN10/CVREF 15 RF5 I/O ST Digital I/O. AN10 I Analog Analog input 10. CVREF O — Comparator reference voltage output. RF6/AN11 14 RF6 I/O ST Digital I/O. AN11 I Analog Analog input 11. RF7/SS1 13 RF7 I/O ST Digital I/O. SS1 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39663F-page 22 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTG is a bidirectional I/O port. RG0/ECCP3/P3A 5 RG0 I/O ST Digital I/O. ECCP3 I/O ST Capture 3 input/Compare 3 output/PWM 3 output. P3A O — ECCP3 PWM output A. RG1/TX2/CK2 6 RG1 I/O ST Digital I/O. TX2 O — EUSART2 asynchronous transmit. CK2 I/O ST EUSART2 synchronous clock (see related RX2/DT2). RG2/RX2/DT2 7 RG2 I/O ST Digital I/O. RX2 I ST EUSART2 asynchronous receive. DT2 I/O ST EUSART2 synchronous data (see related TX2/CK2). RG3/CCP4/P3D 8 RG3 I/O ST Digital I/O. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM 4 output. P3D O — ECCP3 PWM output D. RG4/CCP5/P1D 10 RG4 I/O ST Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output. P1D O — ECCP1 PWM output D. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. DS39663F-page 23
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTH is a bidirectional I/O port. RH0/A16 79 RH0 I/O ST Digital I/O. A16 I/O TTL External memory address/data 16. RH1/A17 80 RH1 I/O ST Digital I/O. A17 I/O TTL External memory address/data 17. RH2/A18 1 RH2 I/O ST Digital I/O. A18 I/O TTL External memory address/data 18. RH3/A19 2 RH3 I/O ST Digital I/O. A19 I/O TTL External memory address/data 19. RH4/AN12/P3C 22 RH4 I/O ST Digital I/O. AN12 I Analog Analog input 12. P3C(5) O — ECCP3 PWM output C. RH5/AN13/P3B 21 RH5 I/O ST Digital I/O. AN13 I Analog Analog input 13. P3B(5) O — ECCP3 PWM output B. RH6/AN14/P1C 20 RH6 I/O ST Digital I/O. AN14 I Analog Analog input 14. P1C(5) O — ECCP1 PWM output C. RH7/AN15/P1B 19 RH7 I/O ST Digital I/O. AN15 I Analog Analog input 15. P1B(5) O — ECCP1 PWM output B. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39663F-page 24 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTJ is a bidirectional I/O port. RJ0/ALE 62 RJ0 I/O ST Digital I/O. ALE O — External memory address latch enable. RJ1/OE 61 RJ1 I/O ST Digital I/O. OE O — External memory output enable. RJ2/WRL 60 RJ2 I/O ST Digital I/O. WRL O — External memory write low control. RJ3/WRH 59 RJ3 I/O ST Digital I/O. WRH O — External memory write high control. RJ4/BA0 39 RJ4 I/O ST Digital I/O. BA0 O — External memory byte address 0 control. RJ5/CE 40 RJ5 I/O ST Digital I/O CE O — External memory chip enable control. RJ6/LB 41 RJ6 I/O ST Digital I/O. LB O — External memory low byte control. RJ7/UB 42 RJ7 I/O ST Digital I/O. UB O — External memory high byte control. VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins. VDD 32, 48, 71 P — Positive supply for peripheral digital logic and I/O pins. AVSS 26 P — Ground reference for analog modules. AVDD 25 P — Positive supply for analog modules. ENVREG 24 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP 12 Core logic power or external filter capacitor connection. VDDCORE P — Positive supply for microcontroller core logic (regulator disabled). VCAP P — External filter capacitor connection (regulator enabled). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C/SMB = I2C™/SMBus input buffer Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode). 2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. DS39663F-page 25
PIC18F87J10 FAMILY NOTES: DS39663F-page 26 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH PIC18FJ MINIMUM CONNECTIONS MICROCONTROLLERS C2(2) 2.1 Basic Connection Requirements VDD Getting started with the PIC18F87J10 family of 8-bit R1 DD SS (1) (1) microcontrollers requires attention to a minimal set of V V R2 device pin connections before proceeding with MCLR ENVREG development. VCAP/VDDCORE C1 The following pins must always be connected: C7 PIC18FXXJXX • All VDD and VSS pins (see Section2.2 “Power Supply Pins”) VSS VDD C6(2) C3(2) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S VSS D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(2) C4(2) • ENVREG (if implemented) and VCAP/VDDCORE pins (see Section2.4 “Voltage Regulator Pins (ENVREG and VCAP/VDDCORE)”) Key (all values are recommendations): These pins must also be connected if they are being C1 through C6: 0.1 μF, 20V ceramic used in the end application: C7: 10 μF, 6.3V or greater, tantalum or ceramic • PGC/PGD pins used for In-Circuit Serial R1: 10 kΩ Programming™ (ICSP™) and debugging purposes R2: 100Ω to 470Ω (see Section2.5 “ICSP Pins”) Note 1: See Section2.4 “Voltage Regulator Pins • OSCI and OSCO pins when an external oscillator (ENVREG and VCAP/VDDCORE)” for source is used explanation of ENVREG pin connections. (see Section2.6 “External Oscillator Pins”) 2: The example shown is for a PIC18FJ device Additionally, the following pins may be required: with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; • VREF+/VREF- pins used when external voltage adjust the number of decoupling capacitors reference for analog modules is implemented appropriately. Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1. © 2009 Microchip Technology Inc. DS39663F-page 27
PIC18F87J10 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: device Reset, and device programming The use of decoupling capacitors on every pair of and debugging. If programming and debugging are power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct AVSS, is required. connection to VDD may be all that is required. The Consider the following criteria when using decoupling addition of other components, to help increase the capacitors: application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical • Value and type of capacitor: A 0.1 μF (100 nF), configuration is shown in Figure2-1. Other circuit 10-20V capacitor is recommended. The capacitor designs may be implemented depending on the should be a low-ESR device with a resonance application’s requirements. frequency in the range of 200MHz and higher. Ceramic capacitors are recommended. During programming and debugging, the resistance • Placement on the printed circuit board: The and capacitance that can be added to the pin must decoupling capacitors should be placed as close be considered. Device programmers and debuggers to the pins as possible. It is recommended to drive the MCLR pin. Consequently, specific voltage place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the capacitor can be placed on another layer on the application and PCB requirements. For example, it is PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated length from the pin to the capacitor is no greater from the MCLR pin during programming and than 0.25inch (6mm). debugging operations by using a jumper (Figure2-2). • Handling high-frequency noise: If the board is The jumper is replaced for normal run-time experiencing high-frequency noise (upward of operations. tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling Any components associated with the MCLR pin capacitor. The value of the second capacitor can should be placed within 0.25 inch (6mm) of the pin. be in the range of 0.01μF to 0.001μF. Place this second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN capacitor. In high-speed circuit designs, consider CONNECTIONS implementing a decade pair of capacitances as close to the power and ground pins as possible VDD (e.g., 0.1μF in parallel with 0.001μF). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the JP PIC18FXXJXX decoupling capacitors are first in the power chain. Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R1≤10kΩ is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10kΩ. Ensure that the On boards with power traces running longer than six MCLR pin VIH and VIL specifications are met. inches in length, it is suggested to use a tank capacitor 2: R2≤470Ω will limit any current flowing into for integrated circuits including microcontrollers to MCLR from the external capacitor, C, in the supply a local power source. The value of the tank event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical capacitor should be determined based on the trace Overstress (EOS). Ensure that the MCLR pin resistance that connects the power supply source to VIH and VIL specifications are met. the device and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7μF to 47μF. DS39663F-page 28 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 2.4 Voltage Regulator Pins (ENVREG 2.5 ICSP Pins and VCAP/VDDCORE) The PGC and PGD pins are used for In-Circuit Serial The on-chip voltage regulator enable pin, ENVREG, Programming (ICSP) and debugging purposes. It is must always be connected directly to either a supply recommended to keep the trace length between the voltage or to ground. Tying ENVREG to VDD enables ICSP connector and the ICSP pins on the device as the regulator, while tying it to ground disables the short as possible. If the ICSP connector is expected to regulator. Refer to Section24.3 “On-Chip Voltage experience an ESD event, a series resistor is recom- Regulator” for details on connecting and using the mended, with the value in the range of a few tens of on-chip regulator. ohms, not to exceed 100Ω. When the regulator is enabled, a low-ESR (<5Ω) Pull-up resistors, series diodes and capacitors on the capacitor is required on the VCAP/VDDCORE pin to PGC and PGD pins are not recommended as they will stabilize the voltage regulator output voltage. The interfere with the programmer/debugger com- VCAP/VDDCORE pin must not be connected to VDD and munications to the device. If such discrete components must use a capacitor of 10 μF connected to ground. The are an application requirement, they should be removed type can be ceramic or tantalum. A suitable example is from the circuit during programming and debugging. the Murata GRM21BF50J106ZE01 (10 μF, 6.3V) or Alternatively, refer to the AC/DC characteristics and equivalent. Designers may use Figure2-3 to evaluate timing requirements information in the respective device ESR equivalence of candidate devices. Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) It is recommended that the trace length not exceed and input low (VIL) requirements. 0.25inch (6mm). Refer to Section27.0 “Electrical Characteristics” for additional information. For device emulation, ensure that the “Communication Channel Select” (i.e., PGC/PGD pins) programmed When the regulator is disabled, the VCAP/VDDCORE pin into the device matches the physical connections for must be tied to a voltage supply at the VDDCORE level. the ICSP to the MPLAB® ICD 2, MPLAB ICD 3 or Refer to Section27.0 “Electrical Characteristics” for REALICE™ emulator. information on VDD and VDDCORE. For more information on the ICD 2, ICD 3 and REAL ICE Note that the “LF” versions of some low pin count emulator connection requirements, refer to the following PIC18FJ parts (e.g., the PIC18LF45J10) do not have documents that are available on the Microchip web site. the ENVREG pin. These devices are provided with the voltage regulator permanently disabled; they must • “MPLAB® ICD 2 In-Circuit Debugger User’s always be provided with a supply voltage on the Guide” (DS51331) VDDCORE pin. • “Using MPLAB® ICD 2” (poster) (DS51265) • “MPLAB® ICD 2 Design Advisory” (DS51566) FIGURE 2-3: FREQUENCY vs. ESR • “Using MPLAB® ICD 3” (poster) (DS51765) PERFORMANCE FOR • “MPLAB® ICD 3 Design Advisory” (DS51764) SUGGESTED VCAP • “MPLAB® REAL ICE™ In-Circuit Emulator User’s 10 Guide” (DS51616) • “Using MPLAB® REAL ICE™ In-Circuit Emulator” (poster) (DS51749) 1 )Ω R ( 0.1 S E 0.01 0.001 0.01 0.1 1 10 100 1000 10,000 Frequency (MHz) Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25°C, 0V DC bias. © 2009 Microchip Technology Inc. DS39663F-page 29
PIC18F87J10 FAMILY 2.6 External Oscillator Pins FIGURE 2-4: SUGGESTED PLACEMENT OF THE OSCILLATOR Many microcontrollers have options for at least two CIRCUIT oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section3.0 “Oscillator Configurations” for details). Main Oscillator The oscillator circuit should be placed on the same 13 side of the board as the device. Place the oscillator Guard Ring 14 circuit close to the respective oscillator pins with no 15 more than 0.5inch (12mm) between the circuit Guard Trace 16 components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Secondary 17 of the board. Oscillator 18 Use a grounded copper pour around the oscillator 19 circuit to isolate it from surrounding circuits. The 20 grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a 2.7 Unused I/Os two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested Unused I/O pins should be configured as outputs and layout is shown in Figure2-4. driven to a logic low state. Alternatively, connect a 1kΩ For additional information and design guidance on to 10kΩ resistor to VSS on unused pins and drive the oscillator circuits, please refer to these Microchip output to logic low. Application Notes, available at the corporate web site (www.microchip.com): • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” DS39663F-page 30 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 3.0 OSCILLATOR FIGURE 3-1: CRYSTAL/CERAMIC CONFIGURATIONS RESONATOR OPERATION (HS OR HSPLL 3.1 Oscillator Types CONFIGURATION) The PIC18F87J10 family of devices can be operated in C1(1) OSC1 five different oscillator modes: To 1. HS High-Speed Crystal/Resonator Internal XTAL (3) Logic 2. HSPLL High-Speed Crystal/Resonator RF with Software PLL Control OSC2 Sleep 3. EC External Clock with FOSC/4 Output 4. ECPLL External Clock with Software PLL C2(1) RS(2) PIC18F87J10 Control 5. INTRC Internal 31kHz Oscillator Note 1: See Table3-1 and Table3-2 for initial values of C1 and C2. Four of these are selected by the user by programming 2: A series resistor (RS) may be required for AT the FOSC<2:0> Configuration bits. The fifth mode strip cut crystals. (INTRC) may be invoked under software control; it can also be configured as the default mode on device 3: RF varies with the oscillator mode chosen. Resets. TABLE 3-1: CAPACITOR SELECTION FOR 3.2 Crystal Oscillator/Ceramic CERAMIC RESONATORS Resonators (HS Modes) Typical Capacitor Values Used: In HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to Mode Freq. OSC1 OSC2 establish oscillation. Figure3-1 shows the pin HS 8.0 MHz 27 pF 27 pF connections. 16.0 MHz 22 pF 22 pF The oscillator design requires the use of a parallel cut Capacitor values are for design guidance only. crystal. These capacitors were tested with the resonators Note: Use of a series cut crystal may give a fre- listed below for basic start-up and operation. These quency out of the crystal manufacturer’s values are not optimized. specifications. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table3-2 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2009 Microchip Technology Inc. DS39663F-page 31
PIC18F87J10 FAMILY TABLE 3-2: CAPACITOR SELECTION FOR 3.3 External Clock Input (EC Modes) CRYSTAL OSCILLATOR The EC and ECPLL Oscillator modes require an exter- Typical Capacitor Values nal clock source to be connected to the OSC1 pin. Osc Type Crystal Tested: There is no oscillator start-up time required after a Freq. Power-on Reset or after an exit from Sleep mode. C1 C2 In the EC Oscillator mode, the oscillator frequency HS 4 MHz 27 pF 27 pF divided by 4 is available on the OSC2 pin. This signal 8 MHz 22 pF 22 pF may be used for test purposes or to synchronize other 20 MHz 15 pF 15 pF logic. Figure3-2 shows the pin connections for the EC Oscillator mode. Capacitor values are for design guidance only. These capacitors were tested with the crystals listed FIGURE 3-2: EXTERNAL CLOCK below for basic start-up and operation. These values INPUT OPERATION are not optimized. (EC CONFIGURATION) Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected Clock from OSC1/CLKI VDD and temperature range for the application. Ext. System PIC18F87J10 See the notes following this table for additional FOSC/4 OSC2/CLKO information. Crystals Used: 4 MHz An external clock source may also be connected to the 8 MHz OSC1 pin in the HS mode, as shown in Figure3-3. In this configuration, the divide-by-4 output on OSC2 is 20 MHz not available. Note1: Higher capacitance increases the stability FIGURE 3-3: EXTERNAL CLOCK INPUT of oscillator but also increases the OPERATION (HS OSC start-up time. CONFIGURATION) 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for Clock from OSC1 appropriate values of external Ext. System PIC18F87J10 components. (HS Mode) Open OSC2 3: Rs may be required to avoid overdriving crystals with low drive level specification. 4: Always verify oscillator performance over the VDD and temperature range that is expected for the application. DS39663F-page 32 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 3.4 PLL Frequency Multiplier FIGURE 3-4: PLL BLOCK DIAGRAM A Phase Locked Loop (PLL) circuit is provided as an HSPLL or ECPLL (CONFIG2L) option for users who want to use a lower frequency PLL Enable (OSCTUNE) oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due OSC2 to high-frequency crystals, or users who require higher Phase clock speeds from an internal oscillator. For these HS or EC FIN Comparator reasons, the HSPLL and ECPLL modes are available. OSC1 Mode FOUT The HSPLL and ECPLL modes provide the ability to selectively run the device at 4 times the external oscil- Loop Filter lating source to produce frequencies up to 40MHz. The PLL is enabled by setting the PLLEN bit in the OSCTUNE register (Register3-1). ÷4 VCO SYSCLK X U M REGISTER 3-1: OSCTUNE: PLL CONTROL REGISTER U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — PLLEN(1) — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PLLEN: Frequency Multiplier PLL Enable bit(1) 1 = PLL enabled 0 = PLL disabled bit 5-0 Unimplemented: Read as ‘0’ Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and read as ‘0’. © 2009 Microchip Technology Inc. DS39663F-page 33
PIC18F87J10 FAMILY 3.5 Internal Oscillator Block The primary oscillators include the External Crystal and Resonator modes and the External Clock modes. The PIC18F87J10 family of devices includes an inter- The particular mode is defined by the FOSC<2:0> nal oscillator source (INTRC) which provides a nominal Configuration bits. The details of these modes are 31kHz output. The INTRC is enabled on device covered earlier in this chapter. power-up and clocks the device during its configuration The secondary oscillators are those external sources cycle until it enters operating mode. INTRC is also not connected to the OSC1 or OSC2 pins. These enabled if it is selected as the device clock source or if sources may continue to operate even after the any of the following are enabled: controller is placed in a power-managed mode. • Fail-Safe Clock Monitor • Watchdog Timer PIC18F87J10 family devices offer the Timer1 oscillator as a secondary oscillator. This oscillator, in all • Two-Speed Start-up power-managed modes, is often the time base for These features are discussed in greater detail in functions such as a real-time clock. Section24.0 “Special Features of the CPU”. Most often, a 32.768kHz watch crystal is connected The INTRC can also be optionally configured as the between the RC0/T1OSO/T13CKI and RC1/T1OSI default clock source on device start-up by setting the pins. Loading capacitors are also connected from each FOSC2 Configuration bit. This is discussed in pin to ground. Section3.6.1 “Oscillator Control Register”. The Timer1 oscillator is discussed in greater detail in 3.6 Clock Sources and Section13.3 “Timer1 Oscillator”. Oscillator Switching In addition to being a primary clock source, the internal oscillator is available as a power-managed mode The PIC18F87J10 family includes a feature that allows clock source. The INTRC source is also used as the the device clock source to be switched from the main clock source for several special features, such as the oscillator to an alternate clock source. PIC18F87J10 WDT and Fail-Safe Clock Monitor. family devices offer two alternate clock sources. When an alternate clock source is enabled, the various The clock sources for the PIC18F87J10 family devices power-managed operating modes are available. areshown in Figure3-5. See Section24.0 “Special Features of the CPU” for Configuration register details. Essentially, there are three clock sources for these devices: • Primary oscillators • Secondary oscillators • Internal oscillator FIGURE 3-5: PIC18F87J10 FAMILY CLOCK DIAGRAM PIC18F87J10 Family Primary Oscillator HS, EC OSC2 Sleep HSPLL, ECPLL 4 x PLL OSC1 Secondary Oscillator T1OSC X Peripherals T1OSO U M T1OSCEN Enable T1OSI Oscillator Internal Oscillator INTRC Source CPU IDLEN Clock Control FOSC<2:0> OSCCON <1:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up DS39663F-page 34 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 3.6.1 OSCILLATOR CONTROL REGISTER 3.6.1.1 System Clock Selection and the FOSC2 Configuration Bit The OSCCON register (Register3-2) controls several aspects of the device clock’s operation, both in The SCS bits are cleared on all forms of Reset. In the full-power operation and in power-managed modes. device’s default configuration, this means the primary oscillator defined by FOSC<1:0> (that is, one of the HC The System Clock Select bits, SCS<1:0>, select the clock source. The available clock sources are the or EC modes) is used as the primary clock source on device Resets. primary clock (defined by the FOSC<2:0> Configura- tion bits), the secondary clock (Timer1 oscillator) and The default clock configuration on Reset can be the internal oscillator. The clock source changes after changed with the FOSC2 Configuration bit. The effect of one or more of the bits are written to, following a brief this bit is to set the clock source selected when clock transition interval. SCS<1:0> = 00. When FOSC2 = 1 (default), the oscillator source defined by FOSC<1:0> is selected The OSTS (OSCCON<3>) and T1RUN (T1CON<6>) bits indicate which clock source is currently providing whenever SCS<1:0> = 00. When FOSC2 = 0, the the device clock. The OSTS bit indicates that the INTRC oscillator is selected whenever SCS<1:2>=00. Oscillator Start-up Timer (OST) has timed out and the Because the SCS bits are cleared on Reset, the FOSC2 setting also changes the default oscillator mode on primary clock is providing the device clock in primary clock modes. The T1RUN bit indicates when the Reset. Timer1 oscillator is providing the device clock in Regardless of the setting of FOSC2, INTRC will always secondary clock modes. In power-managed modes, be enabled on device power-up. It will serve as the only one of these bits will be set at any time. If neither clock source until the device has loaded its configura- of these bits are set, the INTRC is providing the clock, tion values from memory. It is at this point that the or the internal oscillator has just started and is not yet FOSC Configuration bits are read and the oscillator stable. selection of the operational mode is made. The IDLEN bit determines if the device goes into Sleep Note that either the primary clock or the internal mode or one of the Idle modes when the SLEEP oscillator will have two bit setting options, at any given instruction is executed. time, depending on the setting of FOSC2. The use of the flag and control bits in the OSCCON 3.6.2 OSCILLATOR TRANSITIONS register is discussed in more detail in Section4.0 “Power-Managed Modes”. PIC18F87J10 family devices contain circuitry to prevent clock “glitches” when switching between clock Note 1: The Timer1 oscillator must be enabled to sources. A short pause in the device clock occurs select the secondary clock source. The during the clock switch. The length of this pause is the Timer1 oscillator is enabled by setting the sum of two cycles of the old clock source and three to T1OSCEN bit in the Timer1 Control regis- four cycles of the new clock source. This formula ter (T1CON<3>). If the Timer1 oscillator is assumes that the new clock source is stable. not enabled, then any attempt to select a Clock transitions are discussed in greater detail in secondary clock source when executing a Section4.1.2 “Entering Power-Managed Modes”. SLEEP instruction will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts. © 2009 Microchip Technology Inc. DS39663F-page 35
PIC18F87J10 FAMILY REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 U-0 U-0 U-0 R-q(1) U-0 R/W-0 R/W-0 IDLEN — — — OSTS — SCS1 SCS0 bit 7 bit 0 Legend: q = Value determined by configuration R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 Unimplemented: Read as ‘0’ bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 11 = Internal oscillator 10 = Primary oscillator 01 = Timer1 oscillator When FOSC2 = 1: 00 = Primary oscillator When FOSC2 = 0: 00 = Internal oscillator Note 1: The Reset value is ‘0’ when HS mode and Two-Speed Start-up are both enabled; otherwise, it is ‘1’. DS39663F-page 36 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 3.7 Effects of Power-Managed Modes Timer1 oscillator may be operating to support a on the Various Clock Sources Real-Time Clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, When PRI_IDLE mode is selected, the designated PSP, INTx pins and others). Peripherals that may add primary oscillator continues to run without interruption. significant current consumption are listed in For all other power-managed modes, the oscillator Section27.2 “DC Characteristics: Power-Down and using the OSC1 pin is disabled. The OSC1 pin (and Supply Current”. OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and 3.8 Power-up Delays SEC_IDLE), the Timer1 oscillator is operating and Power-up delays are controlled by two timers, so that providing the device clock. The Timer1 oscillator may no external Reset circuitry is required for most applica- also run in all power-managed modes if required to tions. The delays ensure that the device is kept in clock Timer1 or Timer3. Reset until the device power supply is stable under In RC_RUN and RC_IDLE modes, the internal oscilla- normal circumstances and the primary clock is operat- tor provides the device clock source. The 31kHz ing and stable. For additional information on power-up INTRC output can be used directly to provide the clock delays, see Section5.5 “Power-up Timer (PWRT)”. and may be enabled to support various special The first timer is the Power-up Timer (PWRT), which features, regardless of the power-managed mode (see provides a fixed delay on power-up (parameter 33, Section24.2 “Watchdog Timer (WDT)” through Table27-12). It is always enabled. Section24.5 “Fail-Safe Clock Monitor” for more information on WDT, Fail-Safe Clock Monitor and The second timer is the Oscillator Start-up Timer Two-Speed Start-up). (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS modes). The OST does If the Sleep mode is selected, all clock sources are this by counting 1024 oscillator cycles before allowing stopped. Since all the transistor switching currents the oscillator to clock the device. have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage There is a delay of interval, TCSD (parameter 38, currents). Table27-12), following POR, while the controller becomes ready to execute instructions. Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output) HS, HSPLL Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table5-2 in Section5.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. DS39663F-page 37
PIC18F87J10 FAMILY NOTES: DS39663F-page 38 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 4.0 POWER-MANAGED MODES 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three The PIC18F87J10 family devices provide the ability to clock sources for power-managed modes. They are: manage power consumption by simply managing clock- ing to the CPU and the peripherals. In general, a lower • The primary clock, as defined by the FOSC<2:0> clock frequency and a reduction in the number of circuits Configuration bits being clocked constitutes lower consumed power. For • The secondary clock (Timer1 oscillator) the sake of managing power in an application, there are • The internal oscillator three primary modes of operation: • Run mode 4.1.2 ENTERING POWER-MANAGED MODES • Idle mode • Sleep mode Switching from one power-managed mode to another begins by loading the OSCCON register. The These modes define which portions of the device are SCS<1:0> bits select the clock source and determine clocked and at what speed. The Run and Idle modes which Run or Idle mode is to be used. Changing these may use any of the three available clock sources bits causes an immediate switch to the new clock (primary, secondary or internal oscillator block); the source, assuming that it is running. The switch may Sleep mode does not use a clock source. also be subject to clock transition delays. These are The power-managed modes include several discussed in Section4.1.3 “Clock Transitions and power-saving features offered on previous PIC® Status Indicators” and subsequent sections. devices. One is the clock switching feature, offered in Entry to the power-managed Idle or Sleep modes is other PIC18 devices, allowing the controller to use the triggered by the execution of a SLEEP instruction. The Timer1 oscillator in place of the primary oscillator. Also actual mode that results depends on the status of the included is the Sleep mode, offered by all PIC devices, IDLEN bit. where all device clocks are stopped. Depending on the current mode and the mode being 4.1 Selecting Power-Managed Modes switched to, a change to a power-managed mode does not always require setting all of these bits. Many Selecting a power-managed mode requires two transitions may be done by changing the oscillator decisions: if the CPU is to be clocked or not and which select bits, or changing the IDLEN bit, prior to issuing a clock source is to be used. The IDLEN bit SLEEP instruction. If the IDLEN bit is already (OSCCON<7>) controls CPU clocking, while the configured correctly, it may only be necessary to SCS<1:0> bits (OSCCON<1:0>) select the clock perform a SLEEP instruction to switch to the desired source. The individual modes, bit settings, clock mode. sources and affected modules are summarized in Table4-1. TABLE 4-1: POWER-MANAGED MODES OSCCON Bits<7,1:0> Module Clocking Mode Available Clock and Oscillator Source IDLEN(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 10 Clocked Clocked Primary – HS, EC, HSPLL, ECPLL; this is the normal full-power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 11 Clocked Clocked Internal Oscillator PRI_IDLE 1 10 Off Clocked Primary – HS, EC, HSPLL, ECPLL SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 11 Off Clocked Internal Oscillator Note 1: IDLEN reflects its value when the SLEEP instruction is executed. © 2009 Microchip Technology Inc. DS39663F-page 39
PIC18F87J10 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS 4.2 Run Modes INDICATORS In the Run modes, clocks to both the core and The length of the transition between clock sources is peripherals are active. The difference between these the sum of two cycles of the old clock source and three modes is the clock source. to four cycles of the new clock source. This formula assumes that the new clock source is stable. 4.2.1 PRI_RUN MODE Two bits indicate the current clock source and its The PRI_RUN mode is the normal, full-power execu- status: OSTS (OSCCON<3>) and T1RUN tion mode of the microcontroller. This is also the default (T1CON<6>). In general, only one of these bits will be mode upon a device Reset unless Two-Speed Start-up set while in a given power-managed mode. When the is enabled (see Section24.4 “Two-Speed Start-up” OSTS bit is set, the primary clock is providing the for details). In this mode, the OSTS bit is set. (see device clock. When the T1RUN bit is set, the Timer1 Section3.6.1 “Oscillator Control Register”). oscillator is providing the clock. If neither of these bits is set, INTRC is clocking the device. 4.2.2 SEC_RUN MODE Note: Executing a SLEEP instruction does not The SEC_RUN mode is the compatible mode to the necessarily place the device into Sleep “clock switching” feature offered in other PIC18 mode. It acts as the trigger to place the devices. In this mode, the CPU and peripherals are controller into either the Sleep mode or clocked from the Timer1 oscillator. This gives users the one of the Idle modes, depending on the option of lower power consumption while still using a setting of the IDLEN bit. high-accuracy clock source. SEC_RUN mode is entered by setting the SCS<1:0> 4.1.4 MULTIPLE SLEEP COMMANDS bits to ‘01’. The device clock source is switched to the The power-managed mode that is invoked with the Timer1 oscillator (see Figure4-1), the primary oscilla- SLEEP instruction is determined by the setting of the tor is shut down, the T1RUN bit (T1CON<6>) is set and IDLEN bit at the time the instruction is executed. If the OSTS bit is cleared. another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. DS39663F-page 40 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY On transitions from SEC_RUN mode to PRI_RUN, the Note: The Timer1 oscillator should already be peripherals and CPU continue to be clocked from the running prior to entering SEC_RUN mode. Timer1 oscillator while the primary clock is started. If the T1OSCEN bit is not set when the When the primary clock becomes ready, a clock switch SCS<1:0> bits are set to ‘01’, entry to back to the primary clock occurs (see Figure4-2). SEC_RUN mode will not occur. If the When the clock switch is complete, the T1RUN bit is Timer1 oscillator is enabled, but not yet cleared, the OSTS bit is set and the primary clock is running, device clocks will be delayed until providing the clock. The IDLEN and SCS bits are not the oscillator has started. In such affected by the wake-up; the Timer1 oscillator situations, initial oscillator operation is far continues to run. from stable and unpredictable operation may result. FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> Bits Changed OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. © 2009 Microchip Technology Inc. DS39663F-page 41
PIC18F87J10 FAMILY 4.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC In RC_RUN mode, the CPU and peripherals are while the primary clock is started. When the primary clocked from the internal oscillator; the primary clock is clock becomes ready, a clock switch to the primary shut down. This mode provides the best power conser- clock occurs (see Figure4-4). When the clock switch is vation of all the Run modes while still executing code. complete, the OSTS bit is set and the primary clock is It works well for user applications which are not highly providing the device clock. The IDLEN and SCS bits timing sensitive or do not require high-speed clocks at are not affected by the switch. The INTRC source will all times. continue to run if either the WDT or the Fail-Safe Clock This mode is entered by setting the SCS bits to ‘11’. Monitor is enabled. When the clock source is switched to the INTRC (see Figure4-3), the primary oscillator is shut down and the OSTS bit is cleared. FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> Bits Changed OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS39663F-page 42 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 4.3 Sleep Mode 4.4 Idle Modes The power-managed Sleep mode is identical to the The Idle modes allow the controller’s CPU to be legacy Sleep mode offered in all other PIC devices. It is selectively shut down while the peripherals continue to entered by clearing the IDLEN bit (the default state on operate. Selecting a particular Idle mode allows users device Reset) and executing the SLEEP instruction. to further manage power consumption. This shuts down the selected oscillator (Figure4-5). All If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is clock source status bits are cleared. executed, the peripherals will be clocked from the clock Entering the Sleep mode from any other mode does not source selected using the SCS<1:0> bits; however, the require a clock switch. This is because no clocks are CPU will not be clocked. The clock source status bits are needed once the controller has entered Sleep. If the not affected. Setting IDLEN and executing a SLEEP WDT is selected, the INTRC source will continue to instruction provides a quick method of switching from a operate. If the Timer1 oscillator is enabled, it will also given Run mode to its corresponding Idle mode. continue to run. If the WDT is selected, the INTRC source will continue When a wake event occurs in Sleep mode (by interrupt, to operate. If the Timer1 oscillator is enabled, it will also Reset or WDT time-out), the device will not be clocked continue to run. until the clock source selected by the SCS<1:0> bits Since the CPU is not executing instructions, the only becomes ready (see Figure4-6), or it will be clocked exits from any of the Idle modes are by interrupt, WDT from the internal oscillator if either the Two-Speed time-out or a Reset. When a wake event occurs, CPU Start-up or the Fail-Safe Clock Monitor are enabled execution is delayed by an interval of TCSD (see Section24.0 “Special Features of the CPU”). In (parameter38, Table27-12) while it becomes ready to either case, the OSTS bit is set when the primary clock execute code. When the CPU begins executing code, is providing the device clocks. The IDLEN and SCS bits it resumes with the same clock source for the current are not affected by the wake-up. Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. © 2009 Microchip Technology Inc. DS39663F-page 43
PIC18F87J10 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes, in that it does not disable the primary device peripherals continue to be clocked from the Timer1 clock. For timing-sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by set- the fastest resumption of device operation with its more ting the IDLEN bit and executing a SLEEP instruction. If accurate primary clock source, since the clock source the device is in another Run mode, set IDLEN first, then does not have to “warm up” or transition from another set SCS<1:0> to ‘01’ and execute SLEEP. When the oscillator. clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared PRI_IDLE mode is entered from PRI_RUN mode by and the T1RUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then set the SCS bits to ‘10’ and execute SLEEP. be clocked from the Timer1 oscillator. After an interval Although the CPU is disabled, the peripherals continue of TCSD following the wake event, the CPU begins exe- to be clocked from the primary clock source specified cuting code being clocked by the Timer1 oscillator. The by the FOSC<1:0> Configuration bits. The OSTS bit IDLEN and SCS bits are not affected by the wake-up; remains set (see Figure4-7). the Timer1 oscillator continues to run (see Figure4-8). When a wake event occurs, the CPU is clocked from the Note: The Timer1 oscillator should already be primary clock source. A delay of interval, TCSD, is running prior to entering SEC_IDLE mode. required between the wake event and when code If the T1OSCEN bit is not set when the execution starts. This is required to allow the CPU to SLEEP instruction is executed, the SLEEP become ready to execute instructions. After the instruction will be ignored and entry to wake-up, the OSTS bit remains set. The IDLEN and SEC_IDLE mode will not occur. If the SCS bits are not affected by the wake-up (see Timer1 oscillator is enabled, but not yet Figure4-8). running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event DS39663F-page 44 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 4.4.3 RC_IDLE MODE 4.5.2 EXIT BY WDT TIME-OUT In RC_IDLE mode, the CPU is disabled but the A WDT time-out will cause different actions depending peripherals continue to be clocked from the internal on which power-managed mode the device is in when oscillator. This mode allows for controllable power the time-out occurs. conservation during Idle periods. If the device is not executing code (all Idle modes and From RC_RUN, this mode is entered by setting the Sleep mode), the time-out will result in an exit from the IDLEN bit and executing a SLEEP instruction. If the power-managed mode (see Section4.2 “Run device is in another Run mode, first set IDLEN, then Modes” and Section4.3 “Sleep Mode”). If the device clear the SCS bits and execute SLEEP. When the clock is executing code (all Run modes), the time-out will source is switched to the INTRC, the primary oscillator result in a WDT Reset (see Section24.2 “Watchdog is shut down and the OSTS bit is cleared. Timer (WDT)”). When a wake event occurs, the peripherals continue to The Watchdog Timer and postscaler are cleared by one be clocked from the INTRC. After a delay of TCSD of the following events: following the wake event, the CPU begins executing • executing a SLEEP or CLRWDT instruction code being clocked by the INTRC. The IDLEN and • the loss of a currently selected clock source (if the SCS bits are not affected by the wake-up. The INTRC Fail-Safe Clock Monitor is enabled) source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. 4.5.3 EXIT BY RESET 4.5 Exiting Idle and Sleep Modes Exiting an Idle or Sleep mode by Reset automatically forces the device to run from the INTRC. An exit from Sleep mode, or any of the Idle modes, is triggered by an interrupt, a Reset or a WDT time-out. 4.5.4 EXIT WITHOUT AN OSCILLATOR This section discusses the triggers that cause exits START-UP DELAY from power-managed modes. The clocking subsystem Certain exits from power-managed modes do not actions are discussed in each of the power-managed invoke the OST at all. There are two cases: modes sections (see Section4.2 “Run Modes”, Section4.3 “Sleep Mode” and Section4.4 “Idle • PRI_IDLE mode, where the primary clock source Modes”). is not stopped; and • the primary clock source is either the EC or 4.5.1 EXIT BY INTERRUPT ECPLL mode. Any of the available interrupt sources can cause the In these instances, the primary clock source either device to exit from an Idle mode, or the Sleep mode, to does not require an oscillator start-up delay, since it is a Run mode. To enable this functionality, an interrupt already running (PRI_IDLE), or normally does not source must be enabled by setting its enable bit in one require an oscillator start-up delay (EC). However, a of the INTCON or PIE registers. The exit sequence is fixed delay of interval, TCSD, following the wake event initiated when the corresponding interrupt flag bit is set. is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction On all exits from Idle or Sleep modes by interrupt, code execution resumes on the first clock cycle following this execution branches to the interrupt vector if the delay. GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section10.0 “Interrupts”). A fixed delay of interval TCSD following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2009 Microchip Technology Inc. DS39663F-page 45
PIC18F87J10 FAMILY NOTES: DS39663F-page 46 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 5.0 RESET 5.1 RCON Register The PIC18F87J10 family of devices differentiate Device Reset events are tracked through the RCON between various kinds of Reset: register (Register). The lower five bits of the register indicate that a specific Reset event has occurred. In a) Power-on Reset (POR) most cases, these bits can only be set by the event and b) MCLR Reset during normal operation must be cleared by the application after the event. The c) MCLR Reset during power-managed modes state of these flag bits, taken together, can be read to d) Watchdog Timer (WDT) Reset (during indicate the type of Reset that just occurred. This is execution) described in more detail in Section5.6 “Reset State e) Brown-out Reset (BOR) of Registers”. f) RESET Instruction The RCON register also has a control bit for setting g) Stack Full Reset interrupt priority (IPEN). Interrupt priority is discussed in Section10.0 “Interrupts”. h) Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section6.1.6.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section24.2 “Watchdog Timer (WDT)”. A simplified block diagram of the on-chip Reset circuit is shown in Figure5-1. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset(1) S PWRT 32 μs PWRT 65.5 ms Chip_Reset R Q INTRC 11-Bit Ripple Counter Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. © 2009 Microchip Technology Inc. DS39663F-page 47
PIC18F87J10 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. 2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section5.4.1 “Detecting BOR” for more information. 3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset. DS39663F-page 48 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 5.2 Master Clear (MCLR) FIGURE 5-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering a hard SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path VDD VDD which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, D R R1 including the WDT. MCLR 5.3 Power-on Reset (POR) C PIC18F87J10 A Power-on Reset condition is generated on-chip whenever VDD rises above a certain threshold. This Note 1: External Power-on Reset circuit is required allows the device to start in the initialized state when only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor VDD is adequate for operation. quickly when VDD powers down. To take advantage of the POR circuitry, tie the MCLR 2: R < 40kΩ is recommended to make sure that pin through a resistor (1kΩ to 10kΩ) to VDD. This will the voltage drop across R does not violate eliminate external RC components usually needed to the device’s electrical specification. create a Power-on Reset delay. A minimum rise rate for 3: R1 ≥ 1 kΩ will limit any current flowing into VDD is specified (parameter D004). For a slow rise MCLR from external capacitor C, in the event time, see Figure5-2. of MCLR/VPP pin breakdown, due to When the device starts normal operation (i.e., exits the Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the 5.4.1 DETECTING BOR device must be held in Reset until the operating The BOR bit always resets to ‘0’ on any BOR or POR conditions are met. event. This makes it difficult to determine if a BOR POR events are captured by the POR bit (RCON<1>). event has occurred just by reading the state of BOR The state of the bit is set to ‘0’ whenever a POR occurs; alone. A more reliable method is to simultaneously it does not change for any other Reset event. POR is check the state of both POR and BOR. This assumes not reset to ‘1’ by any hardware event. To capture that the POR bit is reset to ‘1’ in software immediately multiple events, the user manually resets the bit to ‘1’ after any POR event. If BOR is ‘0’ while POR is ‘1’, it in software following any POR. can be reliably assumed that a BOR event has occurred. 5.4 Brown-out Reset (BOR) If the voltage regulator is disabled, Brown-out Reset functionality is disabled. In this case, the BOR bit The PIC18F87J10 family of devices incorporate a cannot be used to determine a BOR event. The BOR simple BOR function when the internal regulator is bit is still cleared by a POR event. enabled (ENVREG pin is tied to VDD). Any drop of VDD below VBOR (parameter D005) for greater than time TBOR (parameter 35) will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. Once a BOR has occurred, the Power-up Timer will keep the chip in Reset for TPWRT (parameter33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. © 2009 Microchip Technology Inc. DS39663F-page 49
PIC18F87J10 FAMILY 5.5 Power-up Timer (PWRT) 5.5.1 TIME-OUT SEQUENCE PIC18F87J10 family devices incorporate an on-chip If enabled, the PWRT time-out is invoked after the POR Power-up Timer (PWRT) to help regulate the Power-on pulse has cleared. The total time-out will vary based on Reset process. The PWRT is always enabled. The the status of the PWRT. Figure5-3, Figure5-4, main function is to ensure that the device voltage is Figure5-5 and Figure5-6 all depict time-out stable before code is executed. sequences on power-up with the Power-up Timer enabled. The Power-up Timer (PWRT) of the PIC18F87J10 family devices is an 11-bit counter which uses the INTRC Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the PWRT will expire. Bringing source as the clock input. This yields an approximate MCLR high will begin execution immediately time interval of 2048x32μs=65.6ms. While the (Figure5-5). This is useful for testing purposes, or to PWRT is counting, the device is held in Reset. synchronize more than one PIC18FXXXX device The power-up time delay depends on the INTRC clock operating in parallel. and will vary from chip-to-chip due to temperature and process variation. See DC parameter33 for details. FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET DS39663F-page 50 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. DS39663F-page 51
PIC18F87J10 FAMILY 5.6 Reset State of Registers Table5-2 describes the Reset states for all of the Special Function Registers. These are categorized by Most registers are unaffected by a Reset. Their status Power-on and Brown-out Resets, Master Clear and is unknown on POR and unchanged by all other WDT Resets and WDT wake-ups. Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table5-1. These bits are used in software to determine the nature of the Reset. TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter(1) RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 0 0 0 0 RESET Instruction 0000h 0 u u u u u u Brown-out 0000h 1 1 1 u 0 u u MCLR during power-managed 0000h u 1 u u u u u Run modes MCLR during power-managed 0000h u 1 0 u u u u Idle modes and Sleep mode WDT time-out during full-power 0000h u 0 u u u u u or power-managed Run modes MCLR during full-power 0000h u u u u u u u execution Stack Full Reset (STVREN = 1) 0000h u u u u u 1 u Stack Underflow Reset 0000h u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u u u u u u 1 actual Reset, STVREN = 0) WDT time-out during PC + 2 u 0 0 u u u u power-managed Idle or Sleep modes Interrupt exit from PC + 2 u u 0 u u u u power-managed modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0008h or 0018h). DS39663F-page 52 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TOSU PIC18F6XJ1X PIC18F8XJ1X ---0 0000 ---0 0000 ---0 uuuu(1) TOSH PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu(1) TOSL PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu(1) STKPTR PIC18F6XJ1X PIC18F8XJ1X 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU PIC18F6XJ1X PIC18F8XJ1X ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu PCL PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F6XJ1X PIC18F8XJ1X --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F6XJ1X PIC18F8XJ1X 0000 000x 0000 000u uuuu uuuu(3) INTCON2 PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu(3) INTCON3 PIC18F6XJ1X PIC18F8XJ1X 1100 0000 1100 0000 uuuu uuuu(3) INDF0 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A POSTINC0 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A POSTDEC0 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A PREINC0 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A PLUSW0 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A FSR0H PIC18F6XJ1X PIC18F8XJ1X ---- xxxx ---- uuuu ---- uuuu FSR0L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A POSTINC1 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A POSTDEC1 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A PREINC1 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A PLUSW1 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A FSR1H PIC18F6XJ1X PIC18F8XJ1X ---- xxxx ---- uuuu ---- uuuu FSR1L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F6XJ1X PIC18F8XJ1X ---- 0000 ---- 0000 ---- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. DS39663F-page 53
PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets INDF2 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A POSTINC2 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A POSTDEC2 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A PREINC2 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A PLUSW2 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A FSR2H PIC18F6XJ1X PIC18F8XJ1X ---- xxxx ---- uuuu ---- uuuu FSR2L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F6XJ1X PIC18F8XJ1X ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu TMR0L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F6XJ1X PIC18F8XJ1X 0--- q-00 0--- q-00 u--- q-uu WDTCON PIC18F6XJ1X PIC18F8XJ1X ---- ---0 ---- ---0 ---- ---u RCON(4) PIC18F6XJ1X PIC18F8XJ1X 0--1 1100 0--q qquu u--u qquu TMR1H PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F6XJ1X PIC18F8XJ1X 0000 0000 u0uu uuuu uuuu uuuu TMR2 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 1111 1111 T2CON PIC18F6XJ1X PIC18F8XJ1X -000 0000 -000 0000 -uuu uuuu SSP1BUF PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu SSP1ADD PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu SSP1STAT PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu SSP1CON1 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu SSP1CON2 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu ADRESH PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F6XJ1X PIC18F8XJ1X 0-00 0000 0-00 0000 u-uu uuuu ADCON1 PIC18F6XJ1X PIC18F8XJ1X --00 0000 --00 0000 --uu uuuu ADCON2 PIC18F6XJ1X PIC18F8XJ1X 0-00 0000 0-00 0000 u-uu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. DS39663F-page 54 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets CCPR1H PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu CCPR3H PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCPR3L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCP3CON PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu ECCP1AS PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu CVRCON PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu CMCON PIC18F6XJ1X PIC18F8XJ1X 0000 0111 0000 0111 uuuu uuuu TMR3H PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F6XJ1X PIC18F8XJ1X 0000 0000 uuuu uuuu uuuu uuuu PSPCON PIC18F6XJ1X PIC18F8XJ1X 0000 ---- 0000 ---- uuuu ---- SPBRG1 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu RCREG1 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu TXREG1 PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu TXSTA1 PIC18F6XJ1X PIC18F8XJ1X 0000 0010 0000 0010 uuuu uuuu RCSTA1 PIC18F6XJ1X PIC18F8XJ1X 0000 000x 0000 000x uuuu uuuu EECON2 PIC18F6XJ1X PIC18F8XJ1X ---- ---- ---- ---- ---- ---- EECON1 PIC18F6XJ1X PIC18F8XJ1X ---0 x00- ---0 u00- ---0 u00- IPR3 PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu PIR3 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu(3) PIE3 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu IPR2 PIC18F6XJ1X PIC18F8XJ1X 11-- 1-11 11-- 1-11 uu-- u-uu PIR2 PIC18F6XJ1X PIC18F8XJ1X 00-- 0-00 00-- 0-00 uu-- u-uu(3) PIE2 PIC18F6XJ1X PIC18F8XJ1X 00-- 0-00 00-- 0-00 uu-- u-uu IPR1 PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu PIR1 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu(3) PIE1 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu MEMCON PIC18F6XJ1X PIC18F8XJ1X 0-00 --00 0-00 --00 u-uu --uu OSCTUNE PIC18F6XJ1X PIC18F8XJ1X -0-- ---- -0-- ---- -u-- ---- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. DS39663F-page 55
PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TRISJ PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu TRISH PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu TRISG PIC18F6XJ1X PIC18F8XJ1X ---1 1111 ---1 1111 ---u uuuu TRISF PIC18F6XJ1X PIC18F8XJ1X 1111 111- 1111 111- uuuu uuu- TRISE PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu TRISD PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu TRISA PIC18F6XJ1X PIC18F8XJ1X --11 1111 --11 1111 --uu uuuu LATJ PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu LATH PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu LATG PIC18F6XJ1X PIC18F8XJ1X ---x xxxx ---u uuuu ---u uuuu LATF PIC18F6XJ1X PIC18F8XJ1X xxxx xxx- uuuu uuu- uuuu uuu- LATE PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu LATD PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu LATC PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu LATA PIC18F6XJ1X PIC18F8XJ1X --xx xxxx --uu uuuu --uu uuuu PORTJ PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu PORTH PIC18F6XJ1X PIC18F8XJ1X 0000 xxxx uuuu uuuu uuuu uuuu PORTG PIC18F6XJ1X PIC18F8XJ1X 111x xxxx 111u uuuu uuuu uuuu PORTF PIC18F6XJ1X PIC18F8XJ1X x000 000- x000 000- uuuu uuu- PORTE PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu PORTD PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu PORTA PIC18F6XJ1X PIC18F8XJ1X --0x 0000 --0u 0000 --uu uuuu SPBRGH1 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu BAUDCON1 PIC18F6XJ1X PIC18F8XJ1X 01-0 0-00 01-0 0-00 uu-u u-uu SPBRG2 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu BAUDCON2 PIC18F6XJ1X PIC18F8XJ1X 01-0 0-00 01-0 0-00 uu-u u-uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. DS39663F-page 56 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets ECCP1DEL PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu TMR4 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu PR4 PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 1111 1111 T4CON PIC18F6XJ1X PIC18F8XJ1X -000 0000 -000 0000 -uuu uuuu CCPR4H PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCPR4L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCP4CON PIC18F6XJ1X PIC18F8XJ1X --00 0000 --00 0000 --uu uuuu CCPR5H PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCPR5L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCP5CON PIC18F6XJ1X PIC18F8XJ1X --00 0000 --00 0000 --uu uuuu SPBRG2 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu RCREG2 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu TXREG2 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu TXSTA2 PIC18F6XJ1X PIC18F8XJ1X 0000 0010 0000 0010 uuuu uuuu RCSTA2 PIC18F6XJ1X PIC18F8XJ1X 0000 000x 0000 000x uuuu uuuu ECCP3AS PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu ECCP3DEL PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu ECCP2AS PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu ECCP2DEL PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu SSP2BUF PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu SSP2ADD PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu SSP2STAT PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu SSP2CON1 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu SSP2CON2 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. DS39663F-page 57
PIC18F87J10 FAMILY NOTES: DS39663F-page 58 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 6.0 MEMORY ORGANIZATION 6.1 Program Memory Organization There are two types of memory in PIC18 Flash PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address will return all ‘0’s (a As Harvard architecture devices, the data and program NOP instruction). memories use separate busses; this allows for The entire PIC18F87J10 family offers a range of concurrent access of the two memory spaces. on-chip Flash program memory sizes, from 32Kbytes Additional detailed information on the operation of the (up to 16,384 single-word instructions) to 128Kbytes Flash program memory is provided in Section7.0 (65,536 single-word instructions). The program “Flash Program Memory”. memory maps for individual family members are shown in Figure6-3. FIGURE 6-1: MEMORY MAPS FOR PIC18F87J10 FAMILY DEVICES PC<20:0> 21 CALL, CALLW, RCALL, RETURN, RETFIE, RETLW, ADDULNK, SUBULNK Stack Level 1 • • • Stack Level 31 PIC18FX5J10 PIC18FX5J15 PIC18FX6J10 PIC18FX6J15 PIC18FX7J10 000000h On-Chip On-Chip On-Chip On-Chip On-Chip Memory Memory Memory Memory Memory 005FFFh Config. Words 007FFFh Config. Words 00BFFFh Config. Words 00FFFFh Config. Words e 017FFFh c a p S y or m Config. Words 01FFFFh Me er s U Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 1FFFFFh Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. © 2009 Microchip Technology Inc. DS39663F-page 59
PIC18F87J10 FAMILY 6.1.1 HARD MEMORY VECTORS 6.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded Because PIC18F87J10 family devices do not have per- return vectors in their program memory space. The sistent configuration memory, the top four words of Reset vector address is the default value to which the on-chip program memory are reserved for configuration program counter returns on all device Resets; it is information. On Reset, the configuration information is located at 0000h. copied into the Configuration registers. PIC18 devices also have two interrupt vector The Configuration Words are stored in their program addresses for the handling of high-priority and memory location in numerical order, starting with the low-priority interrupts. The high-priority interrupt vector lower byte of CONFIG1 at the lowest address and end- is located at 0008h and the low-priority interrupt vector ing with the upper byte of CONFIG4. For these devices, is at 0018h. Their locations in relation to the program only Configuration Words, CONFIG1 through memory map are shown in Figure6-2. CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Word for devices FIGURE 6-2: HARD VECTOR AND in the PIC18F87J10 family are shown in Table6-1. CONFIGURATION WORD Their location in the memory map is shown with the LOCATIONS FOR other memory vectors in Figure6-2. PIC18F87J10 FAMILY Additional details on the device Configuration Words DEVICES are provided in Section24.1 “Configuration Bits”. TABLE 6-1: FLASH CONFIGURATION Reset Vector 0000h WORD FOR PIC18F87J10 High-Priority Interrupt Vector 0008h FAMILY DEVICES Low-Priority Interrupt Vector 0018h Program Configuration Device Memory Word (Kbytes) Addresses PIC18F65J10 On-Chip 32 7FF8h to 7FFFh PIC18F85J10 Program Memory PIC18F65J15 48 BFF8h to BFFFh PIC18F85J15 PIC18F66J10 64 FFF8h to FFFFh PIC18F86J10 PIC18F66J15 17FF8h to to Flash Configuration Words (Top of Memory-7) 96 (Top of Memory) PIC18F86J15 17FFFh PIC18F67J10 1FFF8h to to 128 PIC18F87J10 1FFFFh Read ‘0’ 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure6-1 for device-specific values). Shaded area represents unimplemented memory. Areas are not shown to scale. DS39663F-page 60 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 6.1.3 PIC18F8XJ10/8XJ15 PROGRAM • The Extended Microcontroller Mode allows MEMORY MODES access to both internal and external program memories as a single block. The device can The 80-pin devices in this family can address up to a access its entire on-chip program memory; above total of 2Mbytes of program memory. This is achieved this, the device accesses external program through the external memory bus. There are two memory up to the 2-Mbyte program space limit. distinct operating modes available to the controllers: Execution automatically switches between the • Microcontroller (MC) two memories as required. • Extended Microcontroller (EMC) The setting of the EMB Configuration bits also controls The program memory mode is determined by setting the address bus width of the external memory bus. This the EMB Configuration bits (CONFIG3L<5:4>), as is covered in more detail in Section8.0 “External shown in Register6-1. (See also Section24.1 Memory Bus”. “Configuration Bits” for additional details on the In all modes, the microcontroller has complete access device Configuration bits.) to data RAM. The program memory modes operate as follows: Figure6-3 compares the memory maps of the different • The Microcontroller Mode accesses only on-chip program memory modes. The differences between Flash memory. Attempts to read above the top of on-chip and external memory access limitations are on-chip memory causes a read of all ‘0’s (a NOP more fully explained in Table6-2. instruction). The Microcontroller mode is also the only operating mode available to 64-pin devices. REGISTER 6-1: CONFIG3L: CONFIGURATION REGISTER 3 LOW R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 WAIT BW EMB1 EMB0 EASHFT — — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value after erase ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Wait: External Bus Wait Enable bit 1 = Wait states on the external bus are disabled 0 = Wait states on the external bus are enabled and selected by MEMCON<5:4> bit 6 BW: Data Bus Width Select bit 1 = 16-Bit Data Width modes 0 = 8-Bit Data Width modes bit 5-4 EMB<1:0>: External Memory Bus Configuration bits 11 = Microcontroller mode, external bus disabled 10 = Extended Microcontroller mode, 12-bit address width for external bus 01 = Extended Microcontroller mode, 16-bit address width for external bus 00 = Extended Microcontroller mode, 20-bit address width for external bus bit 3 EASHFT: External Address Bus Shift Enable bit 1 = Address shifting enabled – external address bus is shifted to start at 000000h 0 = Address shifting disabled – external address bus reflects the PC value bit 2-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS39663F-page 61
PIC18F87J10 FAMILY 6.1.4 EXTENDED MICROCONTROLLER To avoid this, the Extended Microcontroller mode MODE AND ADDRESS SHIFTING implements an address shifting option to enable auto- matic address translation. In this mode, addresses By default, devices in Extended Microcontroller mode presented on the external bus are shifted down by the directly present the program counter value on the size of the on-chip program memory and are remapped external address bus for those addresses in the range to start at 0000h. This allows the complete use of the of the external memory space. In practical terms, this external memory device’s memory space. means addresses in the external memory device below the top of on-chip memory are unavailable. FIGURE 6-3: MEMORY MAPS FOR PIC18F87J10 FAMILY PROGRAM MEMORY MODES Microcontroller Mode(1) Extended Microcontroller Mode(2) Extended Microcontroller Mode with Address Shifting(2) On-Chip External On-Chip External On-Chip Memory Memory Memory Memory Memory Space Space Space Space Space 000000h 000000h 000000h On-Chip On-Chip On-Chip No Program Program Program Access Memory Memory Memory (Top of Memory) (Top of Memory) External (Top of Memory) (Top of Memory) + 1 (Top of Memory) + 1 Memory (Top of Memory) + 1 Mapped Reads ‘0’s External Mapped to Memory to External External Memory 1FFFFFh – Memory Space (Top of Memory) Space 1FFFFFh 1FFFFFh 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure6-1 for device-specific values). Shaded areas represent unimplemented, or inaccessible areas, depending on the mode. Note 1: This mode is the only available mode on 64-pin devices and the default on 80-pin devices. 2: These modes are only available on 80-pin devices. TABLE 6-2: MEMORY ACCESS FOR PIC18F8XJ10/8XJ15 PROGRAM MEMORY MODES Internal Program Memory External Program Memory Operating Mode Execution Table Read Table Write Execution Table Read Table Write From From To From From To Microcontroller Yes Yes Yes No Access No Access No Access Extended Microcontroller Yes Yes Yes Yes Yes Yes DS39663F-page 62 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 6.1.5 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and is contained in three separate 8-bit registers. The the stack is readable and writable through the low byte, known as the PCL register, is both readable Top-of-Stack Special Function Registers. Data can also and writable. The high byte, or PCH register, contains be pushed to, or popped from the stack, using these the PC<15:8> bits; it is not directly readable or writable. registers. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack. register contains the PC<20:16> bits; it is also not The Stack Pointer is first incremented and the location directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the register are performed through the PCLATU register. contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred a pop from the stack. The contents of the location to the program counter by any operation that writes pointed to by the STKPTR are transferred to the PC PCL. Similarly, the upper two bytes of the program and then the Stack Pointer is decremented. counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all offsets to the PC (see Section6.1.8.1 “Computed Resets. There is no RAM associated with the location GOTO”). corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is The PC addresses bytes in the program memory. To full, has overflowed or has underflowed. prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to 6.1.6.1 Top-of-Stack Access a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. Only the top of the return address stack (TOS) is read- able and writable. A set of three registers, The CALL, RCALL, GOTO and program branch TOSU:TOSH:TOSL, hold the contents of the stack instructions write to the program counter directly. For location pointed to by the STKPTR register these instructions, the contents of PCLATH and (Figure6-4). This allows users to implement a software PCLATU are not transferred to the program counter. stack if necessary. After a CALL, RCALL or interrupt (and ADDULNK and SUBULNK instructions if the 6.1.6 RETURN ADDRESS STACK extended instruction set is enabled), the software can The return address stack allows any combination of up read the pushed value by reading the to 31 program calls and interrupts to occur. The PC is TOSU:TOSH:TOSL registers. These values can be pushed onto the stack when a CALL or RCALL instruc- placed on a user-defined software stack. At return time, tion is executed, or an interrupt is Acknowledged. The the software can return these values to PC value is pulled off the stack on a RETURN, RETLW TOSU:TOSH:TOSL and do a return. or a RETFIE instruction (and on ADDULNK and The user must disable the global interrupt enable bits SUBULNK instructions if the extended instruction set is while accessing the stack to prevent inadvertent stack enabled). PCLATU and PCLATH are not affected by corruption. any of the RETURN or CALL instructions. FIGURE 6-4: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack<20:0> Top-of-Stack Registers Stack Pointer 11111 TOSU TOSH TOSL 11110 STKPTR<4:0> 00h 1Ah 34h 11101 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 © 2009 Microchip Technology Inc. DS39663F-page 63
PIC18F87J10 FAMILY 6.1.6.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The STKPTR register (Register6-2) contains the Stack to the PC and set the STKUNF bit, while the Stack Pointer value, the STKFUL (Stack Full) status bit and Pointer remains at zero. The STKUNF bit will remain the STKUNF (Stack Underflow) status bit. The value of set until cleared by software or until a POR occurs. the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System (RTOS) for return stack maintenance. not the same as a Reset, as the contents of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a 6.1.6.3 PUSH and POP Instructions POR. Since the Top-of-Stack is readable and writable, the The action that takes place when the stack becomes ability to push values onto the stack and pull values off full depends on the state of the STVREN (Stack Over- the stack, without disturbing normal program execu- flow Reset Enable) Configuration bit. (Refer to tion, is a desirable feature. The PIC18 instruction set Section24.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control. (default), the 31st push will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data onto the stack, set the STKFUL bit and reset the or a return address on the stack. device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto Pointer will be set to zero. the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st push and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by Any additional pushes will not overwrite the 31st push decrementing the Stack Pointer. The previous value and the STKPTR will remain at 31. pushed onto the stack then becomes the TOS value. REGISTER 6-2: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. DS39663F-page 64 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 6.1.6.4 Stack Full and Underflow Resets 6.1.8 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in There may be programming situations that require the Configuration Register 1L. When STVREN is set, a full creation of data structures, or look-up tables, in or underflow condition will set the appropriate STKFUL program memory. For PIC18 devices, look-up tables or STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit, but not cause • Table Reads a device Reset. The STKFUL or STKUNF bit is cleared by the user software or a Power-on Reset. 6.1.8.1 Computed GOTO 6.1.7 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in A Fast Register Stack is provided for the STATUS, Example6-2. WREG and BSR registers to provide a “fast return” option for interrupts. This stack is only one level deep A look-up table can be formed with an ADDWF PCL and is neither readable nor writable. It is loaded with the instruction and a group of RETLW nn instructions. The current value of the corresponding register when the W register is loaded with an offset into the table before processor vectors for an interrupt. All interrupt sources executing a call to that table. The first instruction of the will push values into the Stack registers. The values in called routine is the ADDWF PCL instruction. The next the registers are then loaded back into the working instruction executed will be one of the RETLW nn registers if the RETFIE, FAST instruction is used to instructions that returns the value ‘nn’ to the calling return from the interrupt. function. If both low and high-priority interrupts are enabled, the The offset value (in WREG) specifies the number of Stack registers cannot be used reliably to return from bytes that the program counter should advance and low-priority interrupts. If a high-priority interrupt occurs should be multiples of 2 (LSb = 0). while servicing a low-priority interrupt, the Stack In this method, only one data byte may be stored in register values stored by the low-priority interrupt will each instruction location and room on the return be overwritten. In these cases, users must save the key address stack is required. registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 6-2: COMPUTED GOTO USING Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE interrupts are used, the Fast Register Stack can be MOVF OFFSET, W used to restore the STATUS, WREG and BSR registers CALL TABLE at the end of a subroutine call. To use the Fast Register ORG nn00h Stack for a subroutine call, a CALL label, FAST TABLE ADDWF PCL instruction must be executed to save the STATUS, RETLW nnh WREG and BSR registers to the Fast Register Stack. A RETLW nnh RETURN, FAST instruction is then executed to restore RETLW nnh these registers from the Fast Register Stack. . . Example6-1 shows a source code example that uses . the Fast Register Stack during a subroutine call and return. 6.1.8.2 Table Reads EXAMPLE 6-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per ;STACK program word while programming. The Table Pointer • (TBLPTR) specifies the byte address and the Table • Latch (TABLAT) contains the data that is read from the program memory. Data is transferred from program SUB1 • memory one byte at a time. • RETURN FAST ;RESTORE VALUES SAVED Table read operation is discussed further in ;IN FAST REGISTER STACK Section7.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. DS39663F-page 65
PIC18F87J10 FAMILY 6.2 PIC18 Instruction Cycle 6.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles, Q1 6.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are pipe- The microcontroller clock input, whether from an lined in such a manner that a fetch takes one instruction internal or external source, is internally divided by four cycle, while the decode and execute takes another to generate four non-overlapping quadrature clocks instruction cycle. However, due to the pipelining, each (Q1, Q2, Q3 and Q4). Internally, the program counter is instruction effectively executes in one cycle. If an incremented on every Q1; the instruction is fetched instruction causes the program counter to change (e.g., from the program memory and latched into the instruc- GOTO), then two cycles are required to complete the tion register during Q4. The instruction is decoded and instruction (Example6-3). executed during the following Q1 through Q4. The A fetch cycle begins with the Program Counter (PC) clocks and instruction execution flow are shown in incrementing in Q1. Figure6-5. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-5: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Q3 Phase Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS39663F-page 66 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruc- tion. Since instructions are always stored on word The program memory is addressed in bytes. Instruc- boundaries, the data contained in the instruction is a tions are stored as two bytes or four bytes in program word address. The word address is written to PC<20:1> memory. The Least Significant Byte of an instruction which accesses the desired byte address in program word is always stored in a program memory location memory. Instruction #2 in Figure6-6 shows how the with an even address (LSB = 0). To maintain alignment instruction, GOTO 0006h, is encoded in the program with instruction boundaries, the PC increments in steps memory. Program branch instructions, which encode a of 2 and the LSB will always read ‘0’ (see Section6.1.5 relative address offset, operate in the same manner. The “Program Counter”). offset value stored in a branch instruction represents the Figure6-6 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section25.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 6-6: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0 ↓ Program Memory 000000h Byte Locations → 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 6.2.4 TWO-WORD INSTRUCTIONS and used by the instruction sequence. If the first word is skipped for some reason and the second word is The standard PIC18 instruction set has four two-word executed by itself, a NOP is executed instead. This is instructions: CALL, MOVFF, GOTO and LSFR. In all necessary for cases when the two-word instruction is cases, the second word of the instructions always has preceded by a conditional instruction that changes the ‘1111’ as its four Most Significant bits; the other 12 bits PC. Example6-4 shows how this works. are literal data, usually a data memory address. Note: See Section6.5 “Program Memory and The use of ‘1111’ in the 4 MSbs of an instruction the Extended Instruction Set” for specifies a special form of NOP. If the instruction is information on two-word instructions in the executed in proper sequence – immediately after the extended instruction set. first word – the data in the second word is accessed EXAMPLE 6-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code © 2009 Microchip Technology Inc. DS39663F-page 67
PIC18F87J10 FAMILY 6.3 Data Memory Organization 6.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section6.6 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit 12-bit address, allowing up to 4096 bytes of data low-order address and a 4-bit Bank Pointer. memory. The memory space is divided into as many as Most instructions in the PIC18 instruction set make use 16 banks that contain 256 bytes each. The of the Bank Pointer, known as the Bank Select Register PIC18FX5J10/X5J15/X6J10 devices, with up to (BSR). This SFR holds the 4 Most Significant bits of a 64Kbytes of program memory, implement 8 complete location’s address; the instruction itself includes the banks for a total of 2048 bytes. PIC18FX6J15 and 8Least Significant bits. Only the four lower bits of the PIC18FX7J10 devices, with 96 or 128Kbytes of BSR are implemented (BSR<3:0>). The upper four bits program memory, implement all available banks and are unused; they will always read ‘0’ and cannot be provide 3936 bytes of data memory available to the written to. The BSR can be loaded directly by using the user. Figure6-7 and Figure6-8 show the data memory MOVLB instruction. organization for the devices. The value of the BSR indicates the bank in data The data memory contains Special Function Registers memory. The 8 bits in the instruction show the location (SFRs) and General Purpose Registers (GPRs). The in the bank and can be thought of as an offset from the SFRs are used for control and status of the controller bank’s lower boundary. The relationship between the and peripheral functions, while GPRs are used for data BSR’s value and the bank division in data memory is storage and scratchpad operations in the user’s shown in Figure6-9. application. Any read of an unimplemented location will Since up to 16 registers may share the same low-order read as ‘0’s. address, the user must always be careful to ensure that The instruction set and architecture allow operations the proper bank is selected before performing a data across all banks. The entire data memory may be read or write. For example, writing what should be accessed by Direct, Indirect or Indexed Addressing program data to an 8-bit address of F9h while the BSR modes. Addressing modes are discussed later in this is 0Fh, will end up resetting the program counter. section. While any bank can be selected, only those banks that To ensure that commonly used registers (select SFRs are actually implemented can be read or written to. and select GPRs) can be accessed in a single cycle, Writes to unimplemented banks are ignored, while PIC18 devices implement an Access Bank. This is a reads from unimplemented banks will return ‘0’s. Even 256-byte memory space that provides fast access to so, the STATUS register will still be affected as if the select SFRs and the lower portion of GPR Bank 0 with- operation was successful. The data memory map in out using the BSR. Section6.3.2 “Access Bank” Figure6-7 indicates which banks are implemented. provides a detailed description of the Access RAM. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. DS39663F-page 68 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 6-7: DATA MEMORY MAP FOR PIC18FX5J10/X5J15/X6J10 DEVICES When a = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 00h Access Bank is used. 000h = 0000 Access RAM 05Fh The first 96 bytes are general Bank 0 060h purpose RAM (from Bank 0). GPR FFh 0FFh The second 160 bytes are 00h 100h Special Function Registers = 0001 Bank 1 GPR (from Bank 15). FFh 1FFh = 0010 00h 200h When a = 1: Bank 2 GPR The BSR specifies the bank FFh 2FFh used by the instruction. 00h 300h = 0011 Bank 3 GPR FFh 3FFh 00h 400h = 0100 Bank 4 GPR FFh 4FFh 00h 500h = 0101 Bank 5 GPR FFh 5FFh 00h 600h = 0110 Bank 6 GPR FFh 6FFh = 0111 00h 700h Access Bank Bank 7 GPR 00h FFh 7FFh Access RAM Low 00h 800h 5Fh Access RAM High 60h (SFRs) FFh = 1000 Bank 8 Unused to Read as ‘0’ = 1110 Bank 14 FFh EFFh = 1111 00h Unused F00h F5Fh Bank 15 SFR F60h FFh FFFh © 2009 Microchip Technology Inc. DS39663F-page 69
PIC18F87J10 FAMILY FIGURE 6-8: DATA MEMORY MAP FOR PIC18FX6J15/X7J10 DEVICES When a = 0: BSR<3:0> Data Memory Map The BSR is ignored and the Access Bank is used. 00h 000h Access RAM The first 96 bytes are general = 0000 05Fh Bank 0 060h purpose RAM (from Bank 0). GPR FFh 0FFh The remaining 160 bytes are 00h 100h Special Function Registers = 0001 Bank 1 GPR (from Bank 15). FFh 1FFh = 0010 00h 200h When a = 1: Bank 2 GPR The BSR specifies the bank FFh 2FFh used by the instruction. 00h 300h = 0011 Bank 3 GPR FFh 3FFh 00h 400h = 0100 Bank 4 GPR FFh 4FFh 00h 500h = 0101 Bank 5 GPR FFh 5FFh 00h 600h = 0110 Bank 6 GPR Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 GPR Access RAM Low 5Fh FFh 7FFh Access RAM High 60h 00h 800h = 1000 (SFRs) Bank 8 GPR FFh FFh 8FFh 00h 900h = 1001 Bank 9 GPR FFh 9FFh 00h A00h = 1010 Bank 10 GPR FFh AFFh 00h B00h = 1011 Bank 11 GPR FFh BFFh 00h C00h = 1100 GPR Bank 12 FFh CFFh 00h D00h = 1101 GPR Bank 13 FFh DFFh 00h E00h = 1110 GPR Bank 14 FFh EFFh = 1111 00h GPR F00h F5Fh Bank 15 SFR F60h FFh FFFh DS39663F-page 70 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 6-9: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 7 BSR(1) 0 000h Data Memory 00h 7 From Opcode(2) 0 0 0 0 0 0 0 1 0 Bank 0 FFh 11 11 11 11 11 11 11 11 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 6.3.2 ACCESS BANK Using this “forced” addressing allows the instruction to operate on a data address in a single cycle without While the use of the BSR with an embedded 8-bit updating the BSR first. For 8-bit addresses of 60h and address allows users to address the entire range of above, this means that users can evaluate and operate data memory, it also means that the user must always on SFRs more efficiently. The Access RAM below 60h ensure that the correct bank is selected. Otherwise, is a good place for data values that the user might need data may be read from or written to the wrong location. to access rapidly, such as immediate computational This can be disastrous if a GPR is the intended target results or common program variables. Access RAM of an operation, but an SFR is written to instead. also allows for faster and more code efficient context Verifying and/or changing the BSR for each read or saving and switching of variables. write to data memory can become very inefficient. The mapping of the Access Bank is slightly different To streamline access for the most commonly used data when the extended instruction set is enabled (XINST memory locations, the data memory is configured with Configuration bit = 1). This is discussed in more detail an Access Bank, which allows users to access a in Section6.6.3 “Mapping the Access Bank in mapped block of memory without specifying a BSR. Indexed Literal Offset Mode”. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of 6.3.3 GENERAL PURPOSE memory (60h-FFh) in Bank 15. The lower half is known REGISTER FILE as the “Access RAM” and is composed of GPRs. The upper half is where the device’s SFRs are mapped. PIC18 devices may have banked memory in the GPR These two areas are mapped contiguously in the area. This is data RAM which is available for use by all Access Bank and can be addressed in a linear fashion instructions. GPRs start at the bottom of Bank 0 by an 8-bit address (Figure6-7). (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a The Access Bank is used by core PIC18 instructions Power-on Reset and are unchanged on all other that include the Access RAM bit (the ‘a’ parameter in Resets. the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. © 2009 Microchip Technology Inc. DS39663F-page 71
PIC18F87J10 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, The Special Function Registers (SFRs) are registers Resets and interrupts) and those related to the used by the CPU and peripheral modules for controlling peripheral functions. The Reset and Interrupt registers the desired operation of the device. These registers are are described in their respective chapters, while the implemented as static RAM. SFRs start at the top of ALU’s STATUS register is described later in this data memory (FFFh) and extend downward to occupy section. Registers related to the operation of the more than the top half of Bank 15 (F60h to FFFh). A list peripheral features are described in the chapter for that of these registers is given in Table6-3 and Table6-4. peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. TABLE 6-3: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J10 FAMILY DEVICES Address Name Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 F7Fh SPBRGH1 FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 F7Eh BAUDCON1 FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 F7Dh SPBRGH2 FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch MEMCON(3) F7Ch BAUDCON2 FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE F7Bh —(2) FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(3) F7Ah —(2) FF9h PCL FD9h FSR2L FB9h CCPR3H F99h TRISH(3) F79h ECCP1DEL FF8h TBLPTRU FD8h STATUS FB8h CCPR3L F98h TRISG F78h TMR4 FF7h TBLPTRH FD7h TMR0H FB7h CCP3CON F97h TRISF F77h PR4 FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE F76h T4CON FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD F75h CCPR4H FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h CCPR4L FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h CCP4CON FF2h INTCON FD2h —(2) FB2h TMR3L F92h TRISA F72h CCPR5H FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(3) F71h CCPR5L FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH(3) F70h CCP5CON FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG F6Fh SPBRG2 FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF F6Eh RCREG2 FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE F6Dh TXREG2 FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD F6Ch TXSTA2 FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh RCSTA2 FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB F6Ah ECCP3AS FE9h FSR0L FC9h SSP1BUF FA9h —(2) F89h LATA F69h ECCP3DEL FE8h WREG FC8h SSP1ADD FA8h —(2) F88h PORTJ(3) F68h ECCP2AS FE7h INDF1(1) FC7h SSP1STAT FA7h EECON2 F87h PORTH(3) F67h ECCP2DEL FE6h POSTINC1(1) FC6h SSP1CON1 FA6h EECON1 F86h PORTG F66h SSP2BUF FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h PORTF F65h SSP2ADD FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h SSP2STAT FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h SSP2CON1 FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SSP2CON2 FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h —(2) FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h —(2) Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available on 64-pin devices. DS39663F-page 72 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 53, 63 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 53, 63 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 53, 63 STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 53, 64 PCLATU — — bit 21(1) Holding Register for PC<20:16> ---0 0000 53, 63 PCLATH Holding Register for PC<15:8> 0000 0000 53, 63 PCL PC Low Byte (PC<7:0>) 0000 0000 53, 63 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 53, 93 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 53, 93 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 53, 93 TABLAT Program Memory Table Latch 0000 0000 53, 93 PRODH Product Register High Byte xxxx xxxx 53, 107 PRODL Product Register Low Byte xxxx xxxx 53, 107 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 53, 111 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 53, 112 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 53, 113 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 53, 79 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 53, 80 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 53, 80 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 53, 80 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – N/A 53, 80 value of FSR0 offset by W FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 53, 79 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 53, 79 WREG Working Register xxxx xxxx 53 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 53, 79 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 53, 80 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 53, 80 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 53, 80 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – N/A 53, 80 value of FSR1 offset by W FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 53, 79 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 53, 79 BSR — — — — Bank Select Register ---- 0000 53, 68 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 54, 79 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 54, 80 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 54, 80 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 54, 80 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – N/A 54, 80 value of FSR2 offset by W FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 54, 79 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 54, 79 STATUS — — — N OV Z DC C ---x xxxx 54, 78 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 21 of the PC is only available in Serial Programming modes. 2: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 80-pin devices. 3: This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller mode. 4: The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’. 5: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. © 2009 Microchip Technology Inc. DS39663F-page 73
PIC18F87J10 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TMR0H Timer0 Register High Byte 0000 0000 54, 153 TMR0L Timer0 Register Low Byte xxxx xxxx 54, 153 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 54, 151 OSCCON IDLEN — — — OSTS(5) — SCS1 SCS0 0--- q-00 36, 54 WDTCON — — — — — — — SWDTEN --- ---0 54, 287 RCON IPEN — — RI TO PD POR BOR 0--1 1100 48, 54, 123 TMR1H Timer1 Register High Byte xxxx xxxx 54, 159 TMR1L Timer1 Register Low Byte xxxx xxxx 54, 159 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 54, 155 TMR2 Timer2 Register 0000 0000 54, 162 PR2 Timer2 Period Register 1111 1111 54, 162 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 54, 161 SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 54, 203, 238 SSP1ADD MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) 0000 0000 54, 203 SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 54, 194, 204 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 54, 195, 204 SSP1CON2 GCEN ACKSTAT ACKDT/ ACKEN/ RCEN/ PEN/ RSEN/ SEN 0000 0000 54, 206 ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 ADRESH A/D Result Register High Byte xxxx xxxx 54, 269 ADRESL A/D Result Register Low Byte xxxx xxxx 54, 269 ADCON0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0-00 0000 54, 261 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 54, 262 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 54, 263 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 55, 192 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 55, 192 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 55, 177 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 55, 192 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 55, 192 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 55, 177 CCPR3H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 55, 192 CCPR3L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 55, 192 CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 55, 177 ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1(2) PSS1BD0(2) 0000 0000 55, 189 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 55, 277 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 55, 271 TMR3H Timer3 Register High Byte xxxx xxxx 55, 165 TMR3L Timer3 Register Low Byte xxxx xxxx 55, 165 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 55, 163 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 55, 149 SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 55, 243 RCREG1 EUSART1 Receive Register 0000 0000 55, 251, 252 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 21 of the PC is only available in Serial Programming modes. 2: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 80-pin devices. 3: This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller mode. 4: The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’. 5: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. DS39663F-page 74 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TXREG1 EUSART1 Transmit Register xxxx xxxx 55, 249, 250 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 55, 240 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 55, 241 EECON2 Program Memory Control Register 2 (not a physical register) ---- ---- 55 EECON1 — — — FREE WRERR WREN WR — ---0 x00- 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 1111 1111 55, 123 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 0000 0000 55, 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 0000 0000 55, 120 IPR2 OSCFIP CMIP — — BCL1IP — TMR3IP CCP2IP 11-- 1-11 55, 121 PIR2 OSCFIF CMIF — — BCL1IF — TMR3IF CCP2IF 00-- 0-00 55, 115 PIE2 OSCFIE CMIE — — BCL1IE — TMR3IE CCP2IE 00-- 0-00 55, 120 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 55, 120 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 55, 114 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 55, 117 MEMCON(3) EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 55, 96 OSCTUNE — PLLEN(4) — — — — — — -0-- ---- 33, 55 TRISJ(2) TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111 56, 147 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111 56, 145 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ---1 1111 56, 143 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — 1111 111- 56, 141 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 56, 139 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 56, 136 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 56, 133 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 56, 130 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 56, 127 LATJ(2) LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx xxxx 56, 147 LATH(2) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx 56, 145 LATG — — — LATG4 LATG3 LATG2 LATG1 LATG0 ---x xxxx 56, 143 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 — xxxx xxx- 56, 141 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx 56, 139 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 56, 136 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 56, 133 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 56, 130 LATA — — LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 --xx xxxx 56, 127 PORTJ(2) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx 56, 147 PORTH(2) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 0000 xxxx 56, 145 PORTG RDPU REPU RJPU(2) RG4 RG3 RG2 RG1 RG0 111x xxxx 56, 143 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — x000 000- 56, 141 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 56, 139 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 56, 136 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 56, 133 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 56, 130 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 56, 127 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 21 of the PC is only available in Serial Programming modes. 2: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 80-pin devices. 3: This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller mode. 4: The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’. 5: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. © 2009 Microchip Technology Inc. DS39663F-page 75
PIC18F87J10 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 56, 243 BAUDCON1 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 56, 242 SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 56, 243 BAUDCON2 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 56, 242 ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 57, 188 TMR4 Timer4 Register 0000 0000 57, 168 PR4 Timer4 Period Register 1111 1111 57, 168 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 57, 167 CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 57, 170 CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 57, 170 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 57, 169 CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 57, 170 CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 57, 170 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 57, 169 SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 57, 243 RCREG2 EUSART2 Receive Register 0000 0000 57, 251, 252 TXREG2 EUSART2 Transmit Register 0000 0000 57, 249, 250 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 57, 240 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 57, 241 ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 57, 189 ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 57, 188 ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 57, 189 ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 57, 188 SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 57, 203, 238 SSP2ADD MSSP2 Address Register (I2C™ Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) 0000 0000 57, 203 SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 57, 194, 204 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 57, 206, 205 SSP2CON2 GCEN ACKSTAT ACKDT/ ACKEN/ RCEN/ PEN/ RSEN/ SEN 0000 0000 57, 206 ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 21 of the PC is only available in Serial Programming modes. 2: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 80-pin devices. 3: This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller mode. 4: The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’. 5: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. DS39663F-page 76 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 6.3.5 STATUS REGISTER register then reads back as ‘000u u1uu’. It is recom- mended, therefore, that only BCF, BSF, SWAPF, MOVFF The STATUS register, shown in Register6.4, contains and MOVWF instructions are used to alter the STATUS the arithmetic status of the ALU. The STATUS register register because these instructions do not affect the Z, can be the operand for any instruction, as with any C, DC, OV or N bits in the STATUS register. other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, For other instructions not affecting any Status bits, see then the write to these five bits is disabled. the instruction set summaries in Table25-2 and Table25-3. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the Note: The C and DC bits operate as a Borrow STATUS register as destination may be different than and Digit Borrow bit respectively, in intended. For example, CLRF STATUS will set the Z bit subtraction. but leave the other bits unchanged. The STATUS REGISTER 6-3: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. 2: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. DS39663F-page 77
PIC18F87J10 FAMILY 6.4 Data Addressing Modes Purpose Register File”), or a location in the Access Bank (Section6.3.2 “Access Bank”) as the data Note: The execution of some instructions in the source for the instruction. core PIC18 instruction set are changed The Access RAM bit ‘a’ determines how the address is when the PIC18 extended instruction set is interpreted. When ‘a’ is ‘1’, the contents of the BSR enabled. See Section6.6 “Data Memory (Section6.3.1 “Bank Select Register”) are used with and the Extended Instruction Set” for the address to determine the complete 12-bit address more information. of the register. When ‘a’ is ‘0’, the address is interpreted While the program memory can be addressed in only as being a register in the Access Bank. Addressing that one way – through the program counter – information uses the Access RAM is sometimes also known as in the data memory space can be addressed in several Direct Forced Addressing mode. ways. For most instructions, the addressing mode is A few instructions, such as MOVFF, include the entire fixed. Other instructions may use up to three modes, 12-bit address (either source or destination) in their depending on which operands are used and whether or opcodes. In these cases, the BSR is ignored entirely. not the extended instruction set is enabled. The destination of the operation’s results is determined The addressing modes are: by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are • Inherent stored back in the source register, overwriting its origi- nal contents. When ‘d’ is ‘0’, the results are stored in • Literal the W register. Instructions without the ‘d’ argument • Direct have a destination that is implicit in the instruction; their • Indirect destination is either the target register being operated An additional addressing mode, Indexed Literal Offset, on or the W register. is available when the extended instruction set is 6.4.3 INDIRECT ADDRESSING enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section6.6.1 “Indexed Indirect Addressing allows the user to access a location Addressing with Literal Offset”. in data memory without giving a fixed address in the instruction. This is done by using File Select Registers 6.4.1 INHERENT AND LITERAL (FSRs) as pointers to the locations to be read or written ADDRESSING to. Since the FSRs are themselves located in RAM as Many PIC18 control instructions do not need any Special Function Registers, they can also be directly argument at all; they either perform an operation that manipulated under program control. This makes FSRs globally affects the device, or they operate implicitly on very useful in implementing data structures such as one register. This addressing mode is known as tables and arrays in data memory. Inherent Addressing. Examples include SLEEP, RESET The registers for Indirect Addressing are also and DAW. implemented with Indirect File Operands (INDFs) that Other instructions work in a similar way, but require an permit automatic manipulation of the pointer value with additional explicit argument in the opcode. This is auto-incrementing, auto-decrementing or offsetting known as Literal Addressing mode, because they with another value. This allows for efficient code using require some literal value as an argument. Examples loops, such as the example of clearing an entire RAM include ADDLW and MOVLW, which respectively, add or bank in Example6-5. It also enables users to perform move a literal value to the W register. Other examples Indexed Addressing and other Stack Pointer include CALL and GOTO, which include a 20-bit operations for program memory in data memory. program memory address. EXAMPLE 6-5: HOW TO CLEAR RAM 6.4.2 DIRECT ADDRESSING (BANK 1) USING Direct Addressing specifies all or part of the source INDIRECT ADDRESSING and/or destination address of the operation within the LFSR FSR0, 100h ; opcode itself. The options are specified by the NEXT CLRF POSTINC0 ; Clear INDF arguments accompanying the instruction. ; register then ; inc pointer In the core PIC18 instruction set, bit-oriented and BTFSS FSR0H, 1 ; All done with byte-oriented instructions use some version of Direct ; Bank1? Addressing by default. All of these instructions include BRA NEXT ; NO, clear next some 8-bit Literal Address as their Least Significant CONTINUE ; YES, continue Byte. This address specifies either a register address in one of the banks of data RAM (Section6.3.3 “General DS39663F-page 78 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 6.4.3.1 FSR Registers and the the SFR space but are not physically implemented. INDF Operand Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read At the core of Indirect Addressing are three sets of from INDF1, for example, reads the data at the address registers: FSR0, FSR1 and FSR2. Each represents a indicated by FSR1H:FSR1L. Instructions that use the pair of 8-bit registers, FSRnH and FSRnL. The four INDF registers as operands actually use the contents upper bits of the FSRnH register are not used, so each of their corresponding FSR as a pointer to the instruc- FSR pair holds a 12-bit value. This represents a value tion’s target. The INDF operand is just a convenient that can address the entire range of the data memory way of using the pointer. in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current Indirect Addressing is accomplished with a set of Indi- contents of the BSR and the Access RAM bit have no rect File Operands, INDF0 through INDF2. These can effect on determining the target address. be thought of as “virtual” registers: they are mapped in FIGURE 6-10: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 Indirect Addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 1 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains E00h FCCh. This means the contents of Bank 14 location FCCh will be added to that F00h of the W register and stored back in Bank 15 FCCh. FFFh Data Memory © 2009 Microchip Technology Inc. DS39663F-page 79
PIC18F87J10 FAMILY 6.4.3.2 FSR Registers and POSTINC, 6.4.3.3 Operations by FSRs on FSRs POSTDEC, PREINC and PLUSW Indirect Addressing operations that target other FSRs In addition to the INDF operand, each FSR register pair or virtual registers represent special cases. For also has four additional indirect operands. Like INDF, example, using an FSR to point to one of the virtual reg- these are “virtual” registers that cannot be indirectly isters will not result in successful operations. As a read or written to. Accessing these registers actually specific case, assume that FSR0H:FSR0L contains accesses the associated FSR register pair, but also FE7h, the address of INDF1. Attempts to read the performs a specific action on its stored value. They are: value of the INDF1, using INDF0 as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as • POSTDEC: accesses the FSR value, then the operand, will result in a NOP. automatically decrements it by ‘1’ afterwards • POSTINC: accesses the FSR value, then On the other hand, using the virtual registers to write to automatically increments it by ‘1’ afterwards an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any • PREINC: increments the FSR value by ‘1’, then incrementing or decrementing. Thus, writing to INDF2 uses it in the operation or POSTDEC2 will write the same value to the • PLUSW: adds the signed value of the W register FSR2H:FSR2L. (range of -127 to 128) to that of the FSR and uses the new value in the operation Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct In this context, accessing an INDF register uses the operations. Users should proceed cautiously when value in the FSR registers without changing them. working on these registers, particularly if their code Similarly, accessing a PLUSW register gives the FSR uses Indirect Addressing. value offset by the value in the W register; neither value is actually changed in the operation. Accessing the Similarly, operations by Indirect Addressing are gener- other virtual registers changes the value of the FSR ally permitted on all other SFRs. Users should exercise registers. the appropriate caution that they do not inadvertently change settings that might affect the operation of the Operations on the FSRs with POSTDEC, POSTINC device. and PREINC affect the entire register pair; that is, roll- overs of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. DS39663F-page 80 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 6.5 Program Memory and the When using the extended instruction set, this Extended Instruction Set addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0); The operation of program memory is unaffected by the and use of the extended instruction set. • The file address argument is less than or equal to Enabling the extended instruction set adds five 5Fh. additional two-word commands to the existing PIC18 Under these conditions, the file address of the instruction set: ADDFSR, CALLW, MOVSF, MOVSS and instruction is not interpreted as the lower byte of an SUBFSR. These instructions are executed as described address (used with the BSR in Direct Addressing) or as in Section6.2.4 “Two-Word Instructions”. an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer 6.6 Data Memory and the Extended specified by FSR2. The offset and the contents of Instruction Set FSR2 are added to obtain the target address of the operation. Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain 6.6.2 INSTRUCTIONS AFFECTED BY aspects of data memory and its addressing. Specifically, INDEXED LITERAL OFFSET MODE the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of Any of the core PIC18 instructions that can use Direct a new addressing mode for the data memory space. Addressing are potentially affected by the Indexed This mode also alters the behavior of Indirect Literal Offset Addressing mode. This includes all Addressing using FSR2 and its associated operands. byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instruc- What does not change is just as important. The size of tions that only use Inherent or Literal Addressing the data memory space is unchanged, as well as its modes are unaffected. linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct Additionally, byte-oriented and bit-oriented instructions and Indirect Addressing mode; inherent and literal are not affected if they do not use the Access Bank instructions do not change at all. Indirect Addressing (Access RAM bit is ‘1’) or include a file address of 60h with FSR0 and FSR1 also remains unchanged. or above. Instructions meeting these criteria will continue to execute as before. A comparison of the dif- 6.6.1 INDEXED ADDRESSING WITH ferent possible addressing modes when the extended LITERAL OFFSET instruction set is enabled is shown in Figure6-11. Enabling the PIC18 extended instruction set changes Those who desire to use byte-oriented or bit-oriented the behavior of Indirect Addressing using the FSR2 instructions in the Indexed Literal Offset mode should register pair and its associated file operands. Under the note the changes to assembler syntax for this mode. proper conditions, instructions that use the Access This is described in more detail in Section25.2.1 Bank – that is, most bit-oriented and byte-oriented “Extended Instruction Syntax”. instructions – can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. © 2009 Microchip Technology Inc. DS39663F-page 81
PIC18F87J10 FAMILY FIGURE 6-11: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When a = 0 and f ≥ 60h: The instruction executes in 060h Direct Forced mode. ‘f’ is Bank 0 interpreted as a location in the 100h Access RAM between 060h 00h and FFFh. This is the same as Bank 1 through 60h locations F60h to FFFh Bank 14 (Bank15) of data memory. Valid range for ‘f’ Locations below 060h are not FFh available in this addressing F00h Access RAM mode. Bank 15 F60h SFRs FFFh Data Memory When a = 0 and f ≤ 5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 060h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F60h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When a = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 060h Direct mode (also known as Direct Long mode). ‘f’ is 100h interpreted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F60h SFRs FFFh Data Memory DS39663F-page 82 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue The use of Indexed Literal Offset Addressing mode to use Direct Addressing as before. Any Indirect or effectively changes how the lower part of Access RAM Indexed Addressing operation that explicitly uses any (00h to 5Fh) is mapped. Rather than containing just the of the indirect file operands (including FSR2) will con- contents of the bottom part of Bank 0, this mode maps tinue to operate as standard Indirect Addressing. Any the contents from Bank 0 and a user-defined “window” instruction that uses the Access Bank, but includes a that can be located anywhere in the data memory register address of greater than 05Fh, will use Direct space. The value of FSR2 establishes the lower bound- Addressing and the normal Access Bank map. ary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). 6.6.4 BSR IN INDEXED LITERAL Addresses in the Access RAM above 5Fh are mapped OFFSET MODE as previously described (see Section6.3.2 “Access Bank”). An example of Access Bank remapping in this Although the Access Bank is remapped when the addressing mode is shown in Figure6-12. extended instruction set is enabled, the operation of the BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. FIGURE 6-12: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a Not Accessible FSR2H:FSR2L = 120h 05Fh Locations in the region Bank 0 from the FSR2 Pointer 100h (120h) to the pointer plus 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Bank 1 “Window” Access RAM (000h-05Fh). 200h 5Fh Special Function Regis- 60h ters at F60h through FFFh are mapped to 60h Bank 2 through FFh, as usual. through SFRs Bank 0 addresses below Bank 14 5Fh are not available in FFh this mode. They can still Access Bank be addressed by using the F00h BSR. Bank 15 F60h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. DS39663F-page 83
PIC18F87J10 FAMILY NOTES: DS39663F-page 84 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte • Table Read (TBLRD) at a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 64 bytes at a time. Program memory is The program memory space is 16 bits wide, while the erased in blocks of 1024 bytes at a time. A bulk erase data RAM space is 8 bits wide. Table reads and table operation may not be issued from user code. writes move data between these two memory spaces Writing or erasing program memory will cease through an 8-bit register (TABLAT). instruction fetches until the operation is complete. The Table read operations retrieve data from program program memory cannot be accessed during the write memory and place it into the data RAM space. or erase, therefore, code cannot execute. An internal Figure7-1 shows the operation of a table read with programming timer terminates program memory writes program memory and data RAM. and erases. Table write operations store data from the data memory A value written to program memory does not need to be space into holding registers in program memory. The a valid instruction. Executing a program memory procedure to write the contents of the holding registers location that forms an invalid instruction results in a into program memory is detailed in Section7.5 “Writing NOP. to Flash Program Memory”. Figure7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. DS39663F-page 85
PIC18F87J10 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section7.5 “Writing to Flash Program Memory”. 7.2 Control Registers The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is Several control registers are used in conjunction with set in hardware when the WR bit is set and cleared the TBLRD and TBLWT instructions. These include the: when the internal programming timer expires and the • EECON1 register write operation is complete. • EECON2 register Note: During normal operation, the WRERR is • TABLAT register read as ‘1’. This can indicate that a write • TBLPTR registers operation was prematurely terminated by a Reset, or a write operation was 7.2.1 EECON1 AND EECON2 REGISTERS attempted improperly. The EECON1 register (Register7.2.2) is the control The WR control bit initiates write operations. The bit register for memory accesses. The EECON2 register is cannot be cleared, only set, in software. It is cleared in not a physical register; it is used exclusively in the hardware at the completion of the write operation. memory write and erase sequences. Reading EECON2 will read all ‘0’s. The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. DS39663F-page 86 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 — — — FREE WRERR WREN WR — bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program Write Enable bit 1 = Allows write cycles to Flash program memory 0 = Inhibits write cycles to Flash program memory bit 1 WR: Write Control bit 1 = Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is complete bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS39663F-page 87
PIC18F87J10 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the SFR space. The Table Latch register is used to Flash program memory. hold 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the TBLPTR memory and data RAM. determine which byte is read from program memory into TABLAT. 7.2.3 TABLE POINTER REGISTER (TBLPTR) When a TBLWT is executed, the seven LSbs of the Table Pointer register (TBLPTR<6:0>) determine which The Table Pointer (TBLPTR) register addresses a byte of the 64 program memory holding registers is written within the program memory. The TBLPTR is comprised to. When the timed write to program memory begins of three SFR registers: Table Pointer Upper Byte, Table (via the WR bit), the 12 MSbs of the TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<21:10>) determine which program memory (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- block of 1024 bytes is written to. For more detail, see ters join to form a 22-bit wide pointer. The low-order Section7.5 “Writing to Flash Program Memory”. 21bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to When an erase of program memory is executed, the the Device ID, the User ID and the Configuration bits. 12MSbs of the Table Pointer register point to the 1024-byte block that will be erased. The Least The Table Pointer register, TBLPTR, is used by the Significant bits are ignored. TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the Figure7-3 describes the relevant boundaries of table operation. These operations are shown in TBLPTR based on Flash program memory operations. Table7-1. These operations on the TBLPTR only affect the low-order 21bits. TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE: TBLPTR<21:10> TABLE WRITE: TBLPTR<21:6> TABLE READ: TBLPTR<21:0> DS39663F-page 88 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 7.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure7-4 shows the interface between the internal program memory and the TABLAT. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVF WORD_ODD © 2009 Microchip Technology Inc. DS39663F-page 89
PIC18F87J10 FAMILY 7.4 Erasing Flash Program Memory 7.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or The sequence of events for erasing a block of internal through ICSP control, can larger blocks of program program memory location is: memory be bulk erased. Word erase in the Flash array 1. Load Table Pointer register with the address of is not supported. the block being erased. When initiating an erase sequence from the micro- 2. Set the WREN and FREE bits (EECON1<2,4>) controller itself, a block of 1024 bytes of program to enable the erase operation. memory is erased. The Most Significant 12 bits of the 3. Disable interrupts. TBLPTR<21:10> point to the block being erased. 4. Write 55h to EECON2. TBLPTR<9:0> are ignored. 5. Write 0AAh to EECON2. The EECON1 register commands the erase operation. 6. Set the WR bit. This will begin the erase cycle. The WREN bit must be set to enable write operations. 7. The CPU will stall for duration of the erase for The FREE bit is set to select an erase operation. For TIE (see parameter D133B). protection, the write initiate sequence for EECON2 8. Re-enable interrupts. must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 7-2: ERASING FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS39663F-page 90 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 7.5 Writing to Flash Program Memory The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip The minimum programming block is 32 words or charge pump, rated to operate over the voltage range 64bytes. Word or byte programming is not supported. of the device. Table writes are used internally to load the holding Note1: Unlike previous PIC devices, members of registers needed to program the Flash memory. There the PIC18F87J10 family do not reset the are 64 holding registers used by the table writes for holding registers after a write occurs. The programming. holding registers must be cleared or Since the Table Latch (TABLAT) is only a single byte, the overwritten before a programming TBLWT instruction may need to be executed 64times for sequence. each programming operation. All of the table write 2: To maintain the endurance of the program operations will essentially be short writes because only memory cells, each Flash byte should not the holding registers are written. At the end of updating be programmed more than one time the 64 holding registers, the EECON1 register must be between erase operations. Before written to in order to start the programming operation attempting to modify the contents of the with a long write. target cell a second time, a block erase, The long write is necessary for programming the inter- or a bulk erase of the entire memory, must nal Flash. Instruction execution is halted while in a long be performed. write cycle. The long write will be terminated by the internal programming timer. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxx3F Holding Register Holding Register Holding Register Holding Register Program Memory 7.5.1 FLASH PROGRAM MEMORY WRITE 8. Disable interrupts. SEQUENCE 9. Write 55h to EECON2. The sequence of events for programming an internal 10. Write 0AAh to EECON2. program memory location should be: 11. Set the WR bit. This will begin the write cycle. 1. Read 1024 bytes into RAM. 12. The CPU will stall for duration of the write for TIW (see parameter D133A). 2. Update data values in RAM as necessary. 13. Re-enable interrupts. 3. Load Table Pointer register with address being erased. 14. Repeat steps 6 through 13 until all 1024 bytes are written to program memory. 4. Execute the erase procedure. 15. Verify the memory (table read). 5. Load Table Pointer register with address of first byte being written, minus 1. An example of the required code is shown in 6. Write the 64 bytes into the holding registers with Example7-3 on the following page. auto-increment. Note: Before setting the WR bit, the Table 7. Set the WREN bit (EECON1<2>) to enable byte Pointer address needs to be within the writes. intended address range of the 64 bytes in the holding register. © 2009 Microchip Technology Inc. DS39663F-page 91
PIC18F87J10 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base address MOVWF TBLPTRU ; of the memory block, minus 1 MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts MOVLW D'16' MOVWF WRITE_COUNTER ; Need to write 16 blocks of 64 to write ; one erase block of 1024 RESTART_BUFFER MOVLW D'64' MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L FILL_BUFFER ... ; read the new data from I2C, SPI, ; PSP, USART, etc. WRITE_BUFFER MOVLW D’64 ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS MOVFF POSTINC0, WREG ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_WORD_TO_HREGS PROGRAM_MEMORY BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory DECFSZ WRITE_COUNTER ; done with one write cycle BRA RESTART_BUFFER ; if not done replacing the erase block DS39663F-page 92 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 7.5.2 WRITE VERIFY 7.6 Flash Program Operation During Code Protection Depending on the application, good programming practice may dictate that the value written to the See Section24.6 “Program Verification and Code memory should be verified against the original value. Protection” for details on code protection of Flash This should be used in applications where excessive program memory. writes can stress bits near the specification limit. 7.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and repro- grammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 53 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 53 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 53 TABLAT Program Memory Table Latch 53 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 EECON2 Program Memory Control Register 2 (not a physical register) 55 EECON1 — — — FREE WRERR WREN WR — 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during program memory access. © 2009 Microchip Technology Inc. DS39663F-page 93
PIC18F87J10 FAMILY NOTES: DS39663F-page 94 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 8.0 EXTERNAL MEMORY BUS The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE Note: The external memory bus is not and PORTH) are multiplexed with the address/data bus implemented on 64-pin devices. for a total of 20 available lines, while PORTJ is multiplexed with the bus control signals. The external memory bus allows the device to access external memory devices (such as Flash, EPROM, A list of the pins and their functions is provided in SRAM, etc.) as program or data memory. It supports Table8-1. both 8 and 16-Bit Data Width modes and three address widths of up to 20 bits. TABLE 8-1: PIC18F8XJ10/8XJ15 EXTERNAL BUS – I/O PORT FUNCTIONS Name Port Bit External Memory Bus Function RD0/AD0 PORTD 0 Address Bit 0 Or Data Bit 0 RD1/AD1 PORTD 1 Address Bit 1 Or Data Bit 1 RD2/AD2 PORTD 2 Address Bit 2 Or Data Bit 2 RD3/AD3 PORTD 3 Address Bit 3 Or Data Bit 3 RD4/AD4 PORTD 4 Address Bit 4 Or Data Bit 4 RD5/AD5 PORTD 5 Address Bit 5 Or Data Bit 5 RD6/AD6 PORTD 6 Address Bit 6 Or Data Bit 6 RD7/AD7 PORTD 7 Address Bit 7 Or Data Bit 7 RE0/AD8 PORTE 0 Address Bit 8 Or Data Bit 8 RE1/AD9 PORTE 1 Address Bit 9 Or Data Bit 9 RE2/AD10 PORTE 2 Address Bit 10 Or Data Bit 10 RE3/AD11 PORTE 3 Address Bit 11 Or Data Bit 11 RE4/AD12 PORTE 4 Address Bit 12 Or Data Bit 12 RE5/AD13 PORTE 5 Address Bit 13 Or Data Bit 13 RE6/AD14 PORTE 6 Address Bit 14 Or Data Bit 14 RE7/AD15 PORTE 7 Address Bit 15 Or Data Bit 15 RH0/A16 PORTH 0 Address Bit 16 RH1/A17 PORTH 1 Address Bit 17 RH2/A18 PORTH 2 Address Bit 18 RH3/A19 PORTH 3 Address Bit 19 RJ0/ALE PORTJ 0 Address Latch Enable (ALE) Control Pin RJ1/OE PORTJ 1 Output Enable (OE) Control Pin RJ2/WRL PORTJ 2 Write Low (WRL) Control Pin RJ3/WRH PORTJ 3 Write High (WRH) Control Pin RJ4/BA0 PORTJ 4 Byte Address Bit 0 (BA0) RJ5/CE PORTJ 5 Chip Enable (CE) Control Pin RJ6/LB PORTJ 6 Lower Byte Enable (LB) Control Pin RJ7/UB PORTJ 7 Upper Byte Enable (UB) Control Pin Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. © 2009 Microchip Technology Inc. DS39663F-page 95
PIC18F87J10 FAMILY 8.1 External Memory Bus Control The operation of the EBDIS bit is also influenced by the program memory mode being used. This is discussed The operation of the interface is controlled by the in more detail in Section8.5 “Program Memory MEMCON register (Register8-1). This register is Modes and the External Memory Bus”. available in all program memory operating modes The WAIT bits allow for the addition of wait states to except Microcontroller mode. In this mode, the register external memory operations. The use of these bits is is disabled and cannot be written to. discussed in Section8.3 “Wait States”. The EBDIS bit (MEMCON<7>) controls the operation The WM bits select the particular operating mode used of the bus and related port functions. Clearing EBDIS when the bus is operating in 16-Bit Data Width mode. enables the interface and disables the I/O functions of These are discussed in more detail in Section8.6 the ports, as well as any other functions multiplexed to “16-Bit Data Width Modes”. These bits have no effect those pins. Setting the bit enables the I/O ports and when an 8-Bit Data Width mode is selected. other functions, but allows the interface to override everything else on the pins when an external memory operation is required. By default, the external bus is always enabled and disables all other I/O. REGISTER 8-1: MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EBDIS — WAIT1 WAIT0 — — WM1 WM0 bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EBDIS: External Bus Disable bit 1 = External bus enabled when microcontroller accesses external memory; otherwise, all external bus drivers are mapped as I/O ports 0 = External bus always enabled, I/O ports are disabled bit 6 Unimplemented: Read as ‘0’ bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY bit 3-2 Unimplemented: Read as ‘0 bit 1-0 WM<1:0>: TBLWT Operation with 16-Bit Data Bus Width Select bits 1x = Word Write mode: TABLAT0 and TABLAT1 word output; WRH active when TABLAT1 written 01 = Byte Select mode: TABLAT data copied on both MSB and LSB; WRH and (UB or LB) will activate 00 = Byte Write mode: TABLAT data copied on both MSB and LSB; WRH or WRL will activate DS39663F-page 96 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 8.2 Address and Data Width 8.2.1 ADDRESS SHIFTING ON THE EXTERNAL BUS The PIC18F87J10 family of devices can be indepen- dently configured for different address and data widths By default, the address presented on the external bus on the same memory bus. Both address and data width is the value of the PC. In practical terms, this means are set by Configuration bits in the CONFIG3L register. that addresses in the external memory device below As Configuration bits, this means that these options the top of on-chip memory are unavailable to the micro- can only be configured by programming the device and controller. To access these physical locations, the glue are not controllable in software. logic between the microcontroller and the external memory must somehow translate addresses. The BW bit selects an 8-bit or 16-bit data bus width. Setting this bit (default) selects a data width of 16 bits. To simplify the interface, the external bus offers an extension of Extended Microcontroller mode that The EMB<1:0> bits determine both the program automatically performs address shifting. This feature is memory operating mode and the address bus width. controlled by the EASHFT Configuration bit. Setting The available options are 20-bit, 16-bit and 12-bit, as this bit offsets addresses on the bus by the size of the well as Microcontroller mode (external bus disabled). microcontroller’s on-chip program memory and sets Selecting a 16-bit or 12-bit width makes a correspond- the bottom address at 0000h. This allows the device to ing number of high-order lines available for I/O use the entire range of physical addresses of the functions. These pins are no longer affected by the external memory. setting of the EBDIS bit. For example, selecting a 16-Bit Addressing mode (EMB<1:0>=01) disables 8.2.2 21-BIT ADDRESSING A<19:16> and allows PORTH<3:0> to function without As an extension of 20-bit address width operation, the interruptions from the bus. Using the smaller address external memory bus can also fully address a 2-Mbyte widths allows users to tailor the memory bus to the size memory space. This is done by using the Bus Address of the external memory space for a particular design bit 0 (BA0) control line as the Least Significant bit of the while freeing up pins for dedicated I/O operation. address. The UB and LB control signals may also be Because the EMB bits have the effect of disabling pins used with certain memory devices to select the upper for memory bus operations, it is important to always and lower bytes within a 16-bit wide data word. select an address width at least equal to the data width. This addressing mode is available in both 8-Bit and If a 12-bit address width is used with a 16-bit data certain 16-Bit Data Width modes. Additional details are width, the upper four bits of data will not be available on provided in Section8.6.3 “16-Bit Byte Select Mode” the bus. and Section8.7 “8-Bit Mode”. All combinations of address and data widths require multiplexing of address and data information on the same lines. The address and data multiplexing, as well as I/O ports made available by the use of smaller address widths, are summarized in Table8-2. TABLE 8-2: ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS Multiplexed Data and Address Only Lines (and Ports Available Data Width Address Width Address Lines (and Corresponding Ports) for I/O Corresponding Ports) AD<11:8> PORTE<7:4>, 12-Bit (PORTE<3:0>) All of PORTH AD<15:8> 16-Bit AD<7:0> All of PORTH 8-Bit (PORTE<7:0>) (PORTD<7:0>) A<19:16>, AD<15:8> 20-Bit (PORTH<3:0>, — PORTE<7:0>) 16-Bit AD<15:0> — All of PORTH 16-Bit (PORTD<7:0>, A<19:16> 20-Bit — PORTE<7:0>) (PORTH<3:0>) © 2009 Microchip Technology Inc. DS39663F-page 97
PIC18F87J10 FAMILY 8.3 Wait States If the device fetches or accesses external memory while EBDIS = 1, the pins will switch to external bus. If While it may be assumed that external memory devices the EBDIS bit is set by a program executing from exter- will operate at the microcontroller clock rate, this is nal memory, the action of setting the bit will be delayed often not the case. In fact, many devices require longer until the program branches into the internal memory. At times to write or retrieve data than the time allowed by that time, the pins will change from external bus to I/O the execution of table read or table write operations. ports. To compensate for this, the external memory bus can If the device is executing out of internal memory when be configured to add a fixed delay to each table opera- EBDIS = 0, the memory bus address/data and control tion using the bus. Wait states are enabled by setting pins will not be active. They will go to a state where the the WAIT Configuration bit. When enabled, the amount active address/data pins are tri-state; the CE, OE, of delay is set by the WAIT<1:0> bits (MEMCON<5:4>). WRH, WRL, UB and LB signals are ‘1’ and ALE and The delay is based on multiples of microcontroller BA0 are ‘0’. Note that only those pins associated with instruction cycle time and are added following the the current address width are forced to tri-state; the instruction cycle when the table operation is executed. other pins continue to function as I/O. In the case of The range is from no delay to 3TCY (default value). 16-bit address width, for example, only AD<15:0> (PORTD and PORTE) are affected; A<19:16> 8.4 Port Pin Weak Pull-ups (PORTH<3:0>) continue to function as I/O. With the exception of the upper address lines, In all external memory modes, the bus takes priority A<19:16>, the pins associated with the external over any other peripherals that may share pins with it. memory bus are equipped with weak pull-ups. The This includes the Parallel Slave Port and serial commu- pull-ups are controlled by the upper three bits of the nications modules which would otherwise take priority PORTG register. They are named RDPU, REPU and over the I/O port. RJPU and control pull-ups on PORTD, PORTE and PORTJ, respectively. Clearing one of these bits 8.6 16-Bit Data Width Modes enables the corresponding pull-ups for that port. All In 16-Bit Data Width mode, the external memory pull-ups are disabled by default on all device Resets. interface can be connected to external memories in three different configurations: 8.5 Program Memory Modes and the External Memory Bus • 16-Bit Byte Write • 16-Bit Word Write The PIC18F87J10 family of devices is capable of • 16-Bit Byte Select operating in one of two program memory modes, using combinations of on-chip and external program memory. The configuration to be used is determined by the The functions of the multiplexed port pins depend on WM<1:0> bits in the MEMCON register the program memory mode selected, as well as the (MEMCON<1:0>). These three different configurations setting of the EBDIS bit. allow the designer maximum flexibility in using both 8-bit and 16-bit devices with 16-bit data. In Microcontroller Mode, the bus is not active and the pins have their port functions only. Writes to the For all 16-bit modes, the Address Latch Enable (ALE) MEMCOM register are not permitted. The Reset value pin indicates that the address bits, AD<15:0>, are avail- of EBDIS (‘0’) is ignored and EMB pins behave as I/O able on the external memory interface bus. Following ports. the address latch, the Output Enable signal (OE) will enable both bytes of program memory at once to form In Extended Microcontroller Mode, the external a 16-bit instruction word. The Chip Enable signal (CE) program memory bus shares I/O port functions on the is active at any time that the microcontroller accesses pins. When the device is fetching or doing table external memory, whether reading or writing; it is read/table write operations on the external program inactive (asserted high) whenever the device is in memory space, the pins will have the external bus Sleep mode. function. In Byte Select mode, JEDEC standard Flash memories If the device is fetching and accessing internal program will require BA0 for the byte address line and one I/O memory locations only, the EBDIS control bit will line to select between Byte and Word mode. The other change the pins from external memory to I/O port 16-bit modes do not need BA0. JEDEC standard static functions. When EBDIS = 0, the pins function as the RAM memories will use the UB or LB signals for byte external bus. When EBDIS = 1, the pins function as I/O selection. ports. DS39663F-page 98 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 8.6.1 16-BIT BYTE WRITE MODE During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the Figure8-1 shows an example of 16-Bit Byte Write AD<15:0> bus. The appropriate WRH or WRL control mode for PIC18F87J10 family devices. This mode is line is strobed on the LSb of the TBLPTR. used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. FIGURE 8-1: 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18F8XJ10 (MSB) (LSB) A<19:0> AD<7:0> 373 A<x:0> A<x:0> D<15:8> D<7:0> D<7:0> D<7:0> CE CE AD<15:8> 373 OE WR(2) OE WR(2) ALE A<19:16>(1) CE OE WRH WRL Address Bus Data Bus Control Lines Note 1: Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. DS39663F-page 99
PIC18F87J10 FAMILY 8.6.2 16-BIT WORD WRITE MODE During a TBLWT cycle to an odd address (TBLPTR<0>= 1), the TABLAT data is presented on Figure8-2 shows an example of 16-Bit Word Write the upper byte of the AD<15:0> bus. The contents of mode for PIC18F65J10 devices. This mode is used for the holding latch are presented on the lower byte of the word-wide memories which include some of the AD<15:0> bus. EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit The WRH signal is strobed for each write cycle; the memory and table writes to any type of word-wide WRL pin is unused. The signal on the BA0 pin indicates external memories. This method makes a distinction the LSb of the TBLPTR, but it is left unconnected. between TBLWT cycles to even or odd addresses. Instead, the UB and LB signals are active to select both bytes. The obvious limitation to this method is that the During a TBLWT cycle to an even address table write must be done in pairs on a specific word (TBLPTR<0>= 0), the TABLAT data is transferred to a boundary to correctly write a word location. holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. No write signals are activated. FIGURE 8-2: 16-BIT WORD WRITE MODE EXAMPLE PIC18F8XJ10 AD<7:0> 373 A<20:1> A<x:0> JEDEC Word EPROM Memory D<15:0> D<15:0> CE OE WR(2) AD<15:8> 373 ALE A<19:16>(1) CE OE WRH Address Bus Data Bus Control Lines Note 1: Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”. DS39663F-page 100 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 8.6.3 16-BIT BYTE SELECT MODE Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC Figure8-3 shows an example of 16-Bit Byte Select standard Flash memories require that a controller I/O mode. This mode allows table write operations to port pin be connected to the memory’s BYTE/WORD word-wide external memories with byte selection pin to provide the select signal. They also use the BA0 capability. This generally includes both word-wide signal from the controller as a byte address. JEDEC Flash and SRAM devices. standard static RAM memories, on the other hand, use During a TBLWT cycle, the TABLAT data is presented the UB or LB signals to select the byte. on the upper and lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is not used. The BA0 or UB/LB signals are used to select the byte to be written, based on the Least Significant bit of the TBLPTR register. FIGURE 8-3: 16-BIT BYTE SELECT MODE EXAMPLE PIC18F8XJ10 A<20:1> AD<7:0> 373 A<x:1> JEDEC Word FLASH Memory D<15:0> D<15:0> 138(3) CE AD<15:8> 373 A0 ALE BYTE/WORD OE WR(1) A<19:16>(2) OE WRH WRL A<20:1> A<x:1> JEDEC Word BA0 SRAM Memory I/O D<15:0> CE D<15:0> LB LB UB UB OE WR(1) Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”. 2: Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2009 Microchip Technology Inc. DS39663F-page 101
PIC18F87J10 FAMILY 8.6.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure8-4 and Figure8-5. FIGURE 8-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:0> CF33h 9256h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW Execution FIGURE 8-5: EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:0> 3AAAh 0003h 3AABh 0E55h CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction Execution INST(PC – 2) SLEEP DS39663F-page 102 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 8.7 8-Bit Mode will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the In 8-Bit Data Width mode, the external memory bus second byte will be enabled to form the 16-bit instruc- operates only in Multiplexed mode; that is, data shares tion word. The Least Significant bit of the address, BA0, the 8 Least Significant bits of the address bus. must be connected to the memory devices in this Figure8-6 shows an example of 8-Bit Multiplexed mode. The Chip Enable signal (CE) is active at any mode for 80-pin devices. This mode is used for a single time that the microcontroller accesses external 8-bit memory connected for 16-bit operation. The memory, whether reading or writing. It is inactive instructions will be fetched as two 8-bit bytes on a (asserted high) whenever the device is in Sleep mode. shared data/address bus. The two bytes are sequen- This generally includes basic EPROM and Flash tially fetched within one instruction cycle (TCY). devices. It allows table writes to byte-wide external Therefore, the designer must choose external memory memories. devices according to timing calculations based on During a TBLWT instruction cycle, the TABLAT data is 1/2TCY (2 times the instruction rate). For proper mem- presented on the upper and lower bytes of the ory speed selection, glue logic propagation delay times AD<15:0> bus. The appropriate level of the BA0 control must be considered, along with setup and hold times. line is strobed on the LSb of the TBLPTR. The Address Latch Enable (ALE) pin indicates that the address bits, AD<15:0>, are available on the external memory interface bus. The Output Enable signal (OE) FIGURE 8-6: 8-BIT MULTIPLEXED MODE EXAMPLE D<7:0> PIC18F8XJ10 A<19:0> AD<7:0> 373 A<x:1> ALE D<15:8> A0 D<7:0> AD<15:8>(1) CE A<19:16>(1) OE WR(2) BA0 CE OE WRL Address Bus Data Bus Control Lines Note 1: Upper order address bits are only used for 20-bit address width. The upper AD byte is used for all address widths except 8-bit. 2: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. DS39663F-page 103
PIC18F87J10 FAMILY 8.7.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure8-7 and Figure8-8. FIGURE 8-7: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:8> CFh AD<7:0> 33h 92h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW Execution FIGURE 8-8: EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:8> 3Ah 3Ah AD<7:0> AAh 00h 03h ABh 0Eh 55h BA0 CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction Execution INST(PC – 2) SLEEP DS39663F-page 104 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 8.8 Operation in Power-Managed In Sleep and Idle modes, the microcontroller core does Modes not need to access data; bus operations are suspended. The state of the external bus is frozen, with In alternate power-managed Run modes, the external the address/data pins and most of the control pins hold- bus continues to operate normally. If a clock source ing at the same state they were in when the mode was with a lower speed is selected, bus operations will run invoked. The only potential changes are the CE, LB at that speed. In these cases, excessive access times and UB pins, which are held at logic high. for the external memory may result if wait states have been enabled and added to external memory opera- tions. If operations in a lower power Run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. © 2009 Microchip Technology Inc. DS39663F-page 105
PIC18F87J10 FAMILY NOTES: DS39663F-page 106 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 9.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 9-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 9.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY register. ROUTINE Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the MOVF ARG1, W advantages of higher computational throughput and MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit allows the PIC18 devices to be used in many applica- SUBWF PRODH, F ; PRODH = PRODH tions previously reserved for digital signal processors. ; - ARG1 A comparison of various hardware and software MOVF ARG2, W multiply operations, along with the savings in memory BTFSC ARG1, SB ; Test Sign Bit and execution time, is shown in Table9-1. SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 9.2 Operation Example9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the argu- ments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without Hardware Multiply 13 69 6.9 μs 27.6 μs 69 μs 8 x 8 unsigned Hardware Multiply 1 1 100 ns 400 ns 1 μs Without Hardware Multiply 33 91 9.1 μs 36.4 μs 91 μs 8 x 8 signed Hardware Multiply 6 6 600 ns 2.4 μs 6 μs Without Hardware Multiply 21 242 24.2 μs 96.8 μs 242 μs 16 x 16 unsigned Hardware Multiply 28 28 2.8 μs 11.2 μs 28 μs Without Hardware Multiply 52 254 25.4 μs 102.6 μs 254 μs 16 x 16 signed Hardware Multiply 35 40 4.0 μs 16.0 μs 40 μs © 2009 Microchip Technology Inc. DS39663F-page 107
PIC18F87J10 FAMILY Example9-3 shows the sequence to do a 16 x 16 EQUATION 9-2: 16 x 16 SIGNED unsigned multiplication. Equation9-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + EQUATION 9-1: 16 x 16 UNSIGNED (ARG1H • ARG2L • 28) + MULTIPLICATION (ARG1L • ARG2H • 28) + ALGORITHM (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L (-1 • ARG1H<7> • ARG2H:ARG2L • 216) = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + EXAMPLE 9-4: 16 x 16 SIGNED (ARG1L • ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 9-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example9-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation9-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers ; (RES3:RES0). To account for the sign bits of the SIGN_ARG1 arguments, the MSb for each argument pair is tested BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? and the appropriate subtractions are done. BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS39663F-page 108 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 10.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are Members of the PIC18F87J10 family of devices have compatible with PIC® mid-range devices. In multiple interrupt sources and an interrupt priority Compatibility mode, the interrupt priority bits for each feature that allows most interrupt sources to be source have no effect. INTCON<6> is the PEIE bit assigned a high-priority level or a low-priority level. The which enables/disables all peripheral interrupt sources. high-priority interrupt vector is at 0008h and the INTCON<7> is the GIE bit which enables/disables all low-priority interrupt vector is at 0018h. High-priority interrupt sources. All interrupts branch to address interrupt events will interrupt any low-priority interrupts 0008h in Compatibility mode. that may be in progress. When an interrupt is responded to, the global interrupt There are thirteen registers which are used to control enable bit is cleared to disable further interrupts. If the interrupt operation. These registers are: IPEN bit is cleared, this is the GIE bit. If interrupt priority • RCON levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a • INTCON low-priority interrupt. Low-priority interrupts are not • INTCON2 processed while high-priority interrupts are in progress. • INTCON3 The return address is pushed onto the stack and the • PIR1, PIR2, PIR3 PC is loaded with the interrupt vector address (0008h • PIE1, PIE2, PIE3 or 0018h). Once in the Interrupt Service Routine, the • IPR1, IPR2, IPR3 source(s) of the interrupt can be determined by polling It is recommended that the Microchip header files the interrupt flag bits. The interrupt flag bits must be supplied with MPLAB® IDE be used for the symbolic bit cleared in software before re-enabling interrupts to names in these registers. This allows the avoid recursive interrupts. assembler/compiler to automatically take care of the The “return from interrupt” instruction, RETFIE, exits placement of these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL In general, interrupt sources have three bits to control if priority levels are used) which re-enables interrupts. their operation. They are: For external interrupt events, such as the INTx pins or • Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. • Enable bit that allows program execution to Individual interrupt flag bits are set regardless of the branch to the interrupt vector address when the status of their corresponding enable bit or the GIE bit. flag bit is set • Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while The interrupt priority feature is enabled by setting the any interrupt is enabled. Doing so may IPEN bit (RCON<7>). When interrupt priority is cause erratic microcontroller behavior. enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. DS39663F-page 109
PIC18F87J10 FAMILY FIGURE 10-1: PIC18F87J10 FAMILY INTERRUPT LOGIC TMR0IF Wake-up if in TMR0IE Idle or Sleep modes TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE Interrupt to CPU INT1IP Vector to Location INT2IF PIR1<7:0> INT2IE 0008h PIE1<7:0> INT2IP IPR1<7:0> INT3IF INT3IE INT3IP GIE/GIEH PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> IPEN PIR3<7, 0> IPEN PIE3<7, 0> IPR3<7, 0> PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> Interrupt to CPU PIR3<7, 0> TTMMRR00IIEF IPEN V00e1c8tohr to Location PIE3<7, 0> TMR0IP IPR3<7, 0> RBIF RBIE RBIP GIE/GIEH PEIE/GIEL INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP DS39663F-page 110 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 10.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers which contain various enable, priority and flag interrupt enable bit. User software should bits. ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. DS39663F-page 111
PIC18F87J10 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39663F-page 112 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. DS39663F-page 113
PIC18F87J10 FAMILY 10.2 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the Global peripheral interrupts. Due to the number of peripheral Interrupt Enable bit, GIE (INTCON<7>). interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RCREGx, is full (cleared when RCREGx is read) 0 = The EUSART1 receive buffer is empty bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TXREGx, is empty (cleared when TXREGx is written) 0 = The EUSART1 transmit buffer is full bit 3 SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow DS39663F-page 114 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 OSCFIF CMIF — — BCL1IF — TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTRC (must be cleared in software) 0 = Device clock operating bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 Unimplemented: Read as ‘0’ bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. DS39663F-page 115
PIC18F87J10 FAMILY REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 6 BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 5 RC2IF: EUSART2 Receive Interrupt Flag bit 1 = The EUSART2 Receive Buffer, RCREGx, is full (cleared when RCREGx is read) 0 = The EUSART2 Receive Buffer is empty bit 4 TX2IF: EUSART2 Transmit Interrupt Flag bit 1 = The EUSART2 Transmit Buffer, TXREGx, is empty (cleared when TXREGx is written) 0 = The EUSART2 Transmit Buffer is full bit 3 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred bit 2 CCP5IF: CCP5 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 1 CCP4IF: CCP4 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 0 CCP3IF: ECCP3 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. DS39663F-page 116 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enables the EUSART1 receive interrupt 0 = Disables the EUSART1 receive interrupt bit 4 TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enables the EUSART1 transmit interrupt 0 = Disables the EUSART1 transmit interrupt bit 3 SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt bit 2 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enables the ECCP1 interrupt 0 = Disables the ECCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2009 Microchip Technology Inc. DS39663F-page 117
PIC18F87J10 FAMILY REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 OSCFIE CMIE — — BCL1IE — TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module) 1 = Enabled 0 = Disabled bit 2 Unimplemented: Read as ‘0’ bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39663F-page 118 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module) 1 = Enabled 0 = Disabled bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP5IE: CCP5 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. DS39663F-page 119
PIC18F87J10 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIP: Parallel Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39663F-page 120 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 OSCFIP CMIP — — BCL1IP — TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority bit 2 Unimplemented: Read as ‘0’ bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. DS39663F-page 121
PIC18F87J10 FAMILY REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module) 1 = High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IE: TMR4 to PR4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP5IP: CCP5 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit 1 = High priority 0 = Low priority DS39663F-page 122 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 10-13: RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register4-1. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register4-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register4-1. bit 1 POR: Power-on Reset Status bit(2) For details of bit operation, see Register4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register4-1. © 2009 Microchip Technology Inc. DS39663F-page 123
PIC18F87J10 FAMILY 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, In 8-bit mode (which is the default), an overflow in the RB2/INT2 and RB3/INT3 pins are edge-triggered. If the TMR0 register (FFh→00h) will set flag bit, TMR0IF. In corresponding INTEDGx bit in the INTCON2 register is 16-bit mode, an overflow in the TMR0H:TMR0L register set (= 1), the interrupt is triggered by a rising edge; if pair (FFFFh→0000h) will set TMR0IF. The interrupt the bit is clear, the trigger is on the falling edge. When can be enabled/disabled by setting/clearing enable bit, a valid edge appears on the RBx/INTx pin, the TMR0IE (INTCON<5>). Interrupt priority for Timer0 is corresponding flag bit, INTxIF, is set. This interrupt can determined by the value contained in the interrupt prior- be disabled by clearing the corresponding enable bit, ity bit, TMR0IP (INTCON2<2>). See Section12.0 INTxIE. Flag bit, INTxIF, must be cleared in software in “Timer0 Module” for further details on the Timer0 the Interrupt Service Routine before re-enabling the module. interrupt. 10.8 PORTB Interrupt-on-Change All external interrupts (INT0, INT1, INT2 and INT3) can wake-up the processor from the power-managed An input-on-change PORTB<7:4> sets flag bit, RBIF modes if bit, INTxIE, was set prior to going into the (INTCON<0>). The interrupt can be enabled/disabled power-managed modes. If the Global Interrupt Enable by setting/clearing enable bit, RBIE (INTCON<3>). bit, GIE, is set, the processor will branch to the interrupt Interrupt priority for PORTB interrupt-on-change is vector following wake-up. determined by the value contained in the interrupt Interrupt priority for INT1, INT2 and INT3 is determined priority bit, RBIP (INTCON2<0>). by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and 10.9 Context Saving During Interrupts INT3IP (INTCON2<1>). There is no priority bit associated with INT0. It is always a high-priority During interrupts, the return PC address is saved on interrupt source. the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section6.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 10-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS39663F-page 124 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 11.0 I/O PORTS 11.1 I/O Port Pin Capabilities Depending on the device selected and features When developing an application, the capabilities of the enabled, there are up to nine ports available. Some port pins must be considered. Outputs on some pins pins of the I/O ports are multiplexed with an alternate have higher output drive strength than others. Similarly, function from the peripheral features on the device. In some pins can tolerate higher than VDD input levels. general, when a peripheral is enabled, that pin may not 11.1.1 PIN OUTPUT DRIVE be used as a general purpose I/O pin. Each port has three registers for its operation. These The output pin drive strengths vary for groups of pins registers are: intended to meet the needs for a variety of applications. PORTB and PORTC are designed to drive higher • TRIS register (Data Direction register) loads, such as LEDs. The external memory interface • PORT register (reads the levels on the pins of the ports (PORTD, PORTE and PORTJ) are designed to device) drive medium loads. All other ports are designed for • LAT register (Output Latch register) small loads, typically indication only. Table11-1 sum- marizes the output capabilities. Refer to Section27.0 The Output Latch (LAT register) is useful for “Electrical Characteristics” for more details. read-modify-write operations on the value that the I/O pins are driving. TABLE 11-1: OUTPUT DRIVE LEVELS A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure11-1. Port Drive Description PORTA Minimum Intended for indication. FIGURE 11-1: GENERIC I/O PORT PORTF OPERATION PORTG PORTH(1) RD LAT PORTD Medium Sufficient drive levels for external memory interfacing Data PORTE Bus as well as indication. D Q PORTJ(1) WR LAT I/O pin(1) PORTB High Suitable for direct LED drive or Port CK PORTC levels. Data Latch Note 1: These ports are not available on 64-pin D Q devices. WR TRIS CK TRIS Latch Input Buffer RD TRIS Q D ENEN RD Port © 2009 Microchip Technology Inc. DS39663F-page 125
PIC18F87J10 FAMILY 11.1.2 INPUT PINS AND VOLTAGE 11.2 PORTA, TRISA and CONSIDERATIONS LATA Registers The voltage tolerance of pins used as device inputs is PORTA is a 6-bit wide, bidirectional port. The corre- dependent on the pin’s input function. Pins that are used sponding Data Direction register is TRISA. Setting a as digital only inputs are able to handle DC voltages up TRISA bit (= 1) will make the corresponding PORTA pin to 5.5V, a level typical for digital logic circuits. In contrast, an input (i.e., put the corresponding output driver in a pins that also have analog input functions of any kind high-impedance mode). Clearing a TRISA bit (= 0) will can only tolerate voltages up to VDD. Voltage excursions make the corresponding PORTA pin an output (i.e., put beyond VDD on these pins should be avoided. the contents of the output latch on the selected pin). Table11-2 summarizes the input capabilities. Refer to Section27.0 “Electrical Characteristics” for more Reading the PORTA register reads the status of the details. pins, whereas writing to it, will write to the port latch. The Output Latch register (LATA) is also memory TABLE 11-2: INPUT VOLTAGE LEVELS mapped. Read-modify-write operations on the LATA register read and write the latched output value for Tolerated Port or Pin Description PORTA. Input The RA4 pin is multiplexed with the Timer0 module PORTA<5:0> VDD Only VDD input levels clock input to become the RA4/T0CKI pin. The other PORTC<1:0> tolerated. PORTA pins are multiplexed with the analog VREF+ and PORTF<6:1> VREF- inputs. The operation of pins RA<5:0> as A/D Converter inputs is selected by clearing or setting the PORTH<7:4>(1) PCFG<3:0> control bits in the ADCON1 register. PORTB<7:0> 5.5V Tolerates input levels Note: RA5 and RA<3:0> are configured as PORTC<7:2> above VDD, useful for analog inputs on any Reset and are read most standard logic. PORTD<7:0> as ‘0’. RA4 is configured as a digital input. PORTE<7:0> The RA4/T0CKI pin is a Schmitt Trigger input. All other PORTF<7> PORTA pins have TTL input levels and full CMOS PORTG<4:0> output drivers. PORTH<3:0>(1) The TRISA register controls the direction of the PORTA PORTJ<7:0>(1) pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are Note 1: These ports are not available on 64-pin maintained set when using them as analog inputs. devices. EXAMPLE 11-1: INITIALIZING PORTA CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW 07h ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVWF 07h ; Configure comparators MOVWF CMCON ; for digital input MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs DS39663F-page 126 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 11-3: PORTA FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA A/D Input Channel 1. Default input configuration on POR; does not affect digital output. RA2/AN2/VREF- RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when CVREF output enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. AN2 1 I ANA A/D Input Channel 2 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. VREF- 1 I ANA A/D and Comparator low reference voltage input. RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D Input Channel 3. Default input configuration on POR. VREF+ 1 I ANA A/D high reference voltage input. RA4/T0CKI RA4 0 O DIG LATA<4> data output. 1 I ST PORTA<4> data input; default configuration on POR. T0CKI x I ST Timer0 clock input. RA5/AN4 RA5 0 O DIG LATA<5> data output; not affected by analog input. 1 I TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 I ANA A/D Input Channel 4. Default configuration on POR. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 56 LATA — — LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 56 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. © 2009 Microchip Technology Inc. DS39663F-page 127
PIC18F87J10 FAMILY 11.3 PORTB, TRISB and Four of the PORTB pins (RB<7:4>) have an LATB Registers interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any PORTB is an 8-bit wide, bidirectional port. The corre- RB<7:4> pin configured as an output is excluded from sponding Data Direction register is TRISB. Setting a the interrupt-on-change comparison). The input pins (of TRISB bit (= 1) will make the corresponding PORTB RB<7:4>) are compared with the old value latched on pin an input (i.e., put the corresponding output driver in the last read of PORTB. The “mismatch” outputs of a high-impedance mode). Clearing a TRISB bit (= 0) RB<7:4> are ORed together to generate the RB Port will make the corresponding PORTB pin an output (i.e., Change Interrupt with Flag bit, RBIF (INTCON<0>). put the contents of the output latch on the selected pin). This interrupt can wake the device from All pins on PORTB are digital only and tolerate voltages power-managed modes. The user, in the Interrupt up to 5.5V. Service Routine, can clear the interrupt in the following The Output Latch register (LATB) is also memory manner: mapped. Read-modify-write operations on the LATB a) Any read or write of PORTB (except with the register read and write the latched output value for MOVFF (ANY), PORTB instruction). This will PORTB. end the mismatch condition. b) Clear flag bit, RBIF. EXAMPLE 11-2: INITIALIZING PORTB A mismatch condition will continue to set flag bit, RBIF. CLRF PORTB ; Initialize PORTB by Reading PORTB will end the mismatch condition and ; clearing output allow flag bit, RBIF, to be cleared. ; data latches CLRF LATB ; Alternate method The interrupt-on-change feature is recommended for ; to clear output wake-up on key depression operation and operations ; data latches where PORTB is only used for the interrupt-on-change MOVLW 0CFh ; Value used to feature. Polling of PORTB is not recommended while ; initialize data using the interrupt-on-change feature. ; direction MOVWF TRISB ; Set RB<3:0> as inputs For 80-pin devices, RB3 can be configured as the ; RB<5:4> as outputs alternate peripheral pin for the ECCP2 module and ; RB<7:6> as inputs Enhanced PWM Output 2A by clearing the CCP2MX Configuration bit. This applies only to 80-pin devices Each of the PORTB pins has a weak internal pull-up. A operating in Extended Microcontroller mode. If the single control bit can turn on all the pull-ups. This is device is in Microcontroller mode, the alternate performed by clearing bit, RBPU (INTCON2<7>). The assignment for ECCP2 is RE7. As with other ECCP2 weak pull-up is automatically turned off when the port configurations, the user must ensure that the TRISB<3> pin is configured as an output. The pull-ups are bit is set appropriately for the intended operation. disabled on a Power-on Reset. DS39663F-page 128 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 11-5: PORTB FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RB0/INT0/FLT0 RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. INT0 1 I ST External Interrupt 0 input. FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software. RB1/INT1 RB1 0 O DIG LATB<1> data output. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. INT1 1 I ST External Interrupt 1 input. RB2/INT2 RB2 0 O DIG LATB<2> data output. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. INT2 1 I ST External Interrupt 2 input. RB3/INT3/ RB3 0 O DIG LATB<3> data output. ECCP2/P2A 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. INT3 1 I ST External Interrupt 3 input. ECCP2(1) 0 O DIG CCP2 compare output and CCP2 PWM output; takes priority over port data. 1 I ST CCP2 capture input. P2A(1) 0 O DIG ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RB4/KBI0 RB4 0 O DIG LATB<4> data output. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. KBI0 I TTL Interrupt-on-pin change. RB5/KBI1 RB5 0 O DIG LATB<5> data output. 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 I TTL Interrupt-on-pin change. RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-pin change. PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(2) RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-pin change. PGD x O DIG Serial execution data output for ICSP and ICD operation.(2) x I ST Serial execution data input for ICSP and ICD operation.(2) Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode, 80-pin devices only); default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD are enabled. © 2009 Microchip Technology Inc. DS39663F-page 129
PIC18F87J10 FAMILY TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 56 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 56 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 53 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 53 Legend: Shaded cells are not used by PORTB. DS39663F-page 130 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 11.4 PORTC, TRISC and Note: These pins are configured as digital inputs LATC Registers on any device Reset. PORTC is an 8-bit wide, bidirectional port. The corre- The contents of the TRISC register are affected by sponding Data Direction register is TRISC. Setting a peripheral overrides. Reading TRISC always returns TRISC bit (= 1) will make the corresponding PORTC the current contents, even though a peripheral device pin an input (i.e., put the corresponding output driver in may be overriding one or more of the pins. a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., EXAMPLE 11-3: INITIALIZING PORTC put the contents of the output latch on the selected pin). Only PORTC pins, RC2 through RC7, are digital only CLRF PORTC ; Initialize PORTC by ; clearing output pins and can tolerate input voltages up to 5.5V. ; data latches The Output Latch register (LATC) is also memory CLRF LATC ; Alternate method mapped. Read-modify-write operations on the LATC ; to clear output register read and write the latched output value for ; data latches PORTC. MOVLW 0CFh ; Value used to ; initialize data PORTC is multiplexed with several peripheral functions ; direction (Table11-7). The pins have Schmitt Trigger input MOVWF TRISC ; Set RC<3:0> as inputs buffers. RC1 is normally configured by Configuration ; RC<5:4> as outputs bit, CCP2MX, as the default peripheral pin for the ; RC<7:6> as inputs ECCP2 module and enhanced PWM output, P2A (default state, CCP2MX = 1). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2009 Microchip Technology Inc. DS39663F-page 131
PIC18F87J10 FAMILY TABLE 11-7: PORTC FUNCTIONS TRIS Pin Name Function I/O I/O Type Description Setting RC0/T1OSO/ RC0 0 O DIG LATC<0> data output. T13CKI 1 I ST PORTC<0> data input. T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T13CKI 1 I ST Timer1/Timer3 counter input. RC1/T1OSI/ RC1 0 O DIG LATC<1> data output. ECCP2/P2A 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. ECCP2(1) 0 O DIG CCP2 compare output and CCP2 PWM output; takes priority over port data. 1 I ST CCP2 capture input. P2A(1) 0 O DIG ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC2/ECCP1/ RC2 0 O DIG LATC<2> data output. P1A 1 I ST PORTC<2> data input. ECCP1 0 O DIG CCP1 compare output and CCP1 PWM output; takes priority over port data. 1 I ST CCP1 capture input. P1A 0 O DIG ECCP1 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC3/SCK1/ RC3 0 O DIG LATC<3> data output. SCL1 1 I ST PORTC<3> data input. SCK1 0 O DIG SPI clock output (MSSP1 module); takes priority over port data. 1 I ST SPI clock input (MSSP1 module). SCL1 0 O DIG I2C™ clock output (MSSP1 module); takes priority over port data. 1 I I2C/SMB I2C clock input (MSSP1 module); input type depends on module setting. RC4/SDI1/ RC4 0 O DIG LATC<4> data output. SDA1 1 I ST PORTC<4> data input. SDI1 1 I ST SPI data input (MSSP1 module). SDA1 1 O DIG I2C data output (MSSP1 module); takes priority over port data. 1 I I2C/SMB I2C data input (MSSP1 module); input type depends on module setting. RC5/SDO1 RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO1 0 O DIG SPI data output (MSSP1 module); takes priority over port data. RC6/TX1/CK1 RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX1 1 O DIG Synchronous serial data output (EUSART1 module); takes priority over port data. CK1 1 O DIG Synchronous serial data input (EUSART1 module). User must configure as an input. 1 I ST Synchronous serial clock input (EUSART1 module). RC7/RX1/DT1 RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX1 1 I ST Asynchronous serial receive data input (EUSART1 module). DT1 1 O DIG Synchronous serial data output (EUSART1 module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART1 module). User must configure as an input. Legend: PWR = Power Supply, O = Output, I = Input, I2C™/SMB = I2C/SMBus input buffer, ANA = Analog Signal, DIG = Digital Out- put, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2/P2A when the CCP2MX Configuration bit is set. DS39663F-page 132 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 56 LATC LATC7 LATBC6 LATC5 LATCB4 LATC3 LATC2 LATC1 LATC0 56 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 56 © 2009 Microchip Technology Inc. DS39663F-page 133
PIC18F87J10 FAMILY 11.5 PORTD, TRISD and PORTD can also be configured to function as an 8-bit LATD Registers wide, parallel microprocessor port by setting the PSPMODE control bit (PSPCON<4>). In this mode, PORTD is an 8-bit wide, bidirectional port. The corre- parallel port data takes priority over other digital I/O (but sponding Data Direction register is TRISD. Setting a not the external memory interface). When the parallel TRISD bit (= 1) will make the corresponding PORTD port is active, the input buffers are TTL. For more pin an input (i.e., put the corresponding output driver in information, refer to Section11.11 “Parallel Slave a high-impedance mode). Clearing a TRISD bit (= 0) Port”. will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). EXAMPLE 11-4: INITIALIZING PORTD All pins on PORTD are digital only and tolerate voltages up to 5.5V. CLRF PORTD ; Initialize PORTD by ; clearing output The Output Latch register (LATD) is also memory ; data latches mapped. Read-modify-write operations on the LATD CLRF LATD ; Alternate method register read and write the latched output value for ; to clear output PORTD. ; data latches MOVLW 0CFh ; Value used to All pins on PORTD are implemented with Schmitt ; initialize data Trigger input buffers. Each pin is individually ; direction configurable as an input or output. MOVWF TRISD ; Set RD<3:0> as inputs Note: These pins are configured as digital inputs ; RD<5:4> as outputs ; RD<7:6> as inputs on any device Reset. On 80-pin devices, PORTD is multiplexed with the system bus as part of the external memory interface. I/O port and other functions are only available when the interface is disabled by setting the EBDIS bit (MEMCON<7>). When the interface is enabled, PORTD is the low-order byte of the multiplexed address/data bus (AD<7:0>). The TRISD bits are also overridden. Each of the PORTD pins has a weak internal pull-up. The pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up. A single control bit can turn off all the pull-ups. This is performed by clearing bit, RDPU (PORTG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on all device Resets. DS39663F-page 134 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 11-9: PORTD FUNCTIONS TRIS Pin Name Function I/O I/O Type Description Setting RD0/AD0/PSP0 RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. AD0(2) x O DIG External memory interface, address/data bit 0 output.(1) x I TTL External memory interface, data bit 0 input.(1) PSP0 O DIG PSP read output data (LATD<0>); takes priority over port data. I TTL PSP write data input. RD1/AD1/PSP1 RD1 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. AD1(2) x O DIG External memory interface, address/data bit 1 output.(1) x I TTL External memory interface, data bit 1 input.(1) PSP1 x O DIG PSP read output data (LATD<1>); takes priority over port data. x I TTL PSP write data input. RD2/AD2/PSP2 RD2 0 O DIG LATD<2> data output. 1 I ST PORTD<2> data input. AD2(2) x O DIG External memory interface, address/data bit 2 output.(1) x I TTL External memory interface, data bit 2 input.(1) PSP2 x O DIG PSP read output data (LATD<2>); takes priority over port data. x I TTL PSP write data input. RD3/AD3/PSP3 RD3 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. AD3(2) x O DIG External memory interface, address/data bit 3 output.(1) x I TTL External memory interface, data bit 3 input.(1) PSP3 x O DIG PSP read output data (LATD<3>); takes priority over port data. x I TTL PSP write data input. RD4/AD4/ RD4 0 O DIG LATD<4> data output. PSP4/SDO2 1 I ST PORTD<4> data input. AD4(2) x O DIG External memory interface, address/data bit 4 output.(1) x I TTL External memory interface, data bit 4 input.(1) PSP4 x O DIG PSP read output data (LATD<4>); takes priority over port data. x I TTL PSP write data input. SDO2 0 O DIG SPI data output (MSSP2 module); takes priority over port data. RD5/AD5/ RD5 0 O DIG LATD<5> data output. PSP5/SDI2/ 1 I ST PORTD<5> data input. SDA2 AD5(2) x O DIG External memory interface, address/data bit 5 output.(1) x I TTL External memory interface, data bit 5 input.(1) PSP5 x O DIG PSP read output data (LATD<5>); takes priority over port data. x I TTL PSP write data input. SDI2 1 I ST SPI data input (MSSP2 module). SDA2 1 O DIG I2C™ data output (MSSP2 module); takes priority over port data. 1 I I2C/SMB I2C data input (MSSP2 module); input type depends on module setting. Legend: PWR = Power Supply, O = Output, I = Input, I2C™/SMB = I2C/SMBus input buffer, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PSP I/O. 2: Available on 80-pin devices only. © 2009 Microchip Technology Inc. DS39663F-page 135
PIC18F87J10 FAMILY TABLE 11-9: PORTD FUNCTIONS (CONTINUED) TRIS Pin Name Function I/O I/O Type Description Setting RD6/AD6/ RD6 0 O DIG LATD<6> data output. PSP6/SCK2/ 1 I ST PORTD<6> data input. SCL2 AD6(2) x O DIG-3 External memory interface, address/data bit 6 output.(1) x I TTL External memory interface, data bit 6 input.(1) PSP6 x O DIG PSP read output data (LATD<6>); takes priority over port data. x I TTL PSP write data input. SCK2 0 O DIG SPI clock output (MSSP2 module); takes priority over port data. 1 I ST SPI clock input (MSSP2 module). SCL2 0 O DIG I2C™ clock output (MSSP2 module); takes priority over port data. 1 I I2C/SMB I2C clock input (MSSP2 module); input type depends on module setting. RD7/AD7/ RD7 0 O DIG LATD<7> data output. PSP7/SS2 1 I ST PORTD<7> data input. AD7(2) x O DIG External memory interface, address/data bit 7 output.(1) x I TTL External memory interface, data bit 7 input.(1) PSP7 x O DIG PSP read output data (LATD<7>); takes priority over port data. x I TTL PSP write data input. SS2 x I TTL Slave select input for MSSP (MSSP2 module). Legend: PWR = Power Supply, O = Output, I = Input, I2C™/SMB = I2C/SMBus input buffer, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PSP I/O. 2: Available on 80-pin devices only. TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 56 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 56 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56 PORTG RDPU REPU RJPU(1) RG4 RG3 RG2 RG1 RG0 56 Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on 64-pin devices, read as ‘0’. DS39663F-page 136 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 11.6 PORTE, TRISE and PORTE is also multiplexed with Enhanced PWM LATE Registers outputs B and C for ECCP1 and ECCP3 and outputs B, C and D for ECCP2. For all devices, their default PORTE is a 7-bit wide, bidirectional port. The corre- assignments are on PORTE<6:3>. On 80-pin devices, sponding Data Direction register is TRISE. Setting a the multiplexing for the outputs of ECCP1 and ECCP3 TRISE bit (= 1) will make the corresponding PORTE is controlled by the ECCPMX Configuration bit. pin an input (i.e., put the corresponding output driver in Clearing this bit reassigns the P1B/P1C and P3B/P3C a high-impedance mode). Clearing a TRISE bit (= 0) outputs to PORTH. will make the corresponding PORTE pin an output (i.e., For devices operating in Microcontroller mode, pin RE7 put the contents of the output latch on the selected pin). can be configured as the alternate peripheral pin for the All pins on PORTE are digital only and tolerate voltages ECCP2 module and Enhanced PWM output 2A. This is up to 5.5V. done by clearing the CCP2MX Configuration bit. The Output Latch register (LATE) is also memory When the Parallel Slave Port is active on PORTD, three mapped. Read-modify-write operations on the LATE of the PORTE pins (RE0, RE1 and RE2) are configured register read and write the latched output value for as digital control inputs for the port. The control PORTE. functions are summarized in Table11-11. The reconfig- All pins on PORTE are implemented with Schmitt uration occurs automatically when the PSPMODE Trigger input buffers. Each pin is individually control bit (PSPCON<4>) is set. Users must still make configurable as an input or output. certain the corresponding TRISE bits are set to configure these pins as digital inputs. Note: These pins are configured as digital inputs on any device Reset. EXAMPLE 11-5: INITIALIZING PORTE On 80-pin devices, PORTE is multiplexed with the CLRF PORTE ; Initialize PORTE by system bus as part of the external memory interface. ; clearing output I/O port and other functions are only available when the ; data latches interface is disabled, by setting the EBDIS bit CLRF LATE ; Alternate method (MEMCON<7>). When the interface is enabled, ; to clear output PORTE is the high-order byte of the multiplexed ; data latches MOVLW 03h ; Value used to address/data bus (AD<15:8>). The TRISE bits are also ; initialize data overridden. ; direction Each of the PORTE pins has a weak internal pull-up. MOVWF TRISE ; Set RE<1:0> as inputs The pull-ups are provided to keep the inputs at a known ; RE<7:2> as outputs state for the external memory interface while powering up. A single control bit can turn off all the pull-ups. This is performed by clearing bit, REPU (PORTG<6>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on any device Reset. © 2009 Microchip Technology Inc. DS39663F-page 137
PIC18F87J10 FAMILY TABLE 11-11: PORTE FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RE0/AD8/RD/ RE0 0 O DIG LATE<0> data output. P2D 1 I ST PORTE<0> data input. AD8(3) x O DIG External memory interface, address/data bit 8 output.(2) x I TTL External memory interface, data bit 8 input.(2) RD 1 I TTL Parallel Slave Port read enable control input. P2D 0 O DIG ECCP2 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE1/AD9/WR/ RE1 0 O DIG LATE<1> data output. P2C 1 I ST PORTE<1> data input. AD9(3) x O DIG External memory interface, address/data bit 9 output.(2) x I TTL External memory interface, data bit 9 input.(2) WR 1 I TTL Parallel Slave Port write enable control input. P2C 0 O DIG ECCP2 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE2/AD10/CS/ RE2 0 O DIG LATE<2> data output. P2B 1 I ST PORTE<2> data input. AD10(3) x O DIG External memory interface, address/data bit 10 output.(2) x I TTL External memory interface, data bit 10 input.(2) CS 1 I TTL Parallel Slave Port chip select control input. P2B 0 O DIG ECCP2 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE3/AD11/ RE3 0 O DIG LATE<3> data output. P3C 1 I ST PORTE<3> data input. AD11(3) x O DIG External memory interface, address/data bit 11 output.(2) x I TTL External memory interface, data bit 11 input.(2) P3C(1) 0 O DIG ECCP3 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE4/AD12/ RE4 0 O DIG LATE<4> data output. P3B 1 I ST PORTE<4> data input. AD12(3) x O DIG External memory interface, address/data bit 12 output.(2) x I TTL External memory interface, data bit 12 input.(2) P3B(1) 0 O DIG ECCP3 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE5/AD13/ RE5 0 O DIG LATE<5> data output. P1C 1 I ST PORTE<5> data input. AD13(3) x O DIG External memory interface, address/data bit 13 output.(2) x I TTL External memory interface, data bit 13 input.(2) P1C(1) 0 O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only). 2: External memory interface I/O takes priority over all other digital and PSP I/O. 3: Available on 80-pin devices only. 4: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (all devices in Microcontroller mode). DS39663F-page 138 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 11-11: PORTE FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RE6/AD14/ RE6 0 O DIG LATE<6> data output. P1B 1 I ST PORTE<6> data input. AD14(3) x O DIG External memory interface, address/data bit 14 output.(2) x I TTL External memory interface, data bit 14 input.(2) P1B(1) 0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE7/AD15/ RE7 0 O DIG LATE<7> data output. ECCP2/P2A 1 I ST PORTE<7> data input. AD15(3) x O DIG External memory interface, address/data bit 15 output.(2) x I TTL External memory interface, data bit 15 input.(2) ECCP2(4) 0 O DIG CCP2 compare output and CCP2 PWM output; takes priority over port data. 1 I ST CCP2 capture input. P2A(4) 0 O DIG ECCP2 Enhanced PWM output, Channel A; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only). 2: External memory interface I/O takes priority over all other digital and PSP I/O. 3: Available on 80-pin devices only. 4: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (all devices in Microcontroller mode). TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 56 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 56 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 56 PORTG RDPU REPU RJPU(1) RG4 RG3 RG2 RG1 RG0 56 Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. DS39663F-page 139
PIC18F87J10 FAMILY 11.7 PORTF, LATF and TRISF Registers Note1: On device Resets, pins, RF<6:1>, are PORTF is a 7-bit wide, bidirectional port. The corre- configured as analog inputs and are read sponding Data Direction register is TRISF. Setting a as ‘0’. TRISF bit (= 1) will make the corresponding PORTF pin 2: To configure PORTF as digital I/O, turn off an input (i.e., put the corresponding output driver in a comparators and set ADCON1 value. high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin). EXAMPLE 11-6: INITIALIZING PORTF Only pin 7 of PORTF has no analog input; it is the only pin that can tolerate voltages up to 5.5V. CLRF PORTF ; Initialize PORTF by ; clearing output The Output Latch register (LATF) is also memory ; data latches mapped. Read-modify-write operations on the LATF CLRF LATF ; Alternate method register read and write the latched output value for ; to clear output PORTF. ; data latches All pins on PORTF are implemented with Schmitt MOVLW 07h ; Trigger input buffers. Each pin is individually MOVWF CMCON ; Turn off comparators MOVLW 0Fh; configurable as an input or output. MOVWF ADCON1 ; Set PORTF as digital I/O PORTF is multiplexed with several analog peripheral MOVLW 0CEh ; Value used to functions, including the A/D Converter and comparator ; initialize data inputs, as well as the comparator outputs. Pins, RF2 ; direction through RF6, may be used as comparator inputs or MOVWF TRISF ; Set RF3:RF1 as inputs outputs by setting the appropriate bits in the CMCON ; RF5:RF4 as outputs ; RF7:RF6 as inputs register. To use RF<6:3> as digital inputs, it is also necessary to turn off the comparators. DS39663F-page 140 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 11-13: PORTF FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RF1/AN6/ RF1 0 O DIG LATF<1> data output; not affected by analog input. C2OUT 1 I ST PORTF<1> data input; disabled when analog input enabled. AN6 1 I ANA A/D Input Channel 6. Default configuration on POR. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. RF2/AN7/ RF2 0 O DIG LATF<2> data output; not affected by analog input. C1OUT 1 I ST PORTF<2> data input; disabled when analog input enabled. AN7 1 I ANA A/D Input Channel 7. Default configuration on POR. C1OUT 0 O TTL Comparator 1 output; takes priority over port data. RF3/AN8 RF3 0 O DIG LATF<3> data output; not affected by analog input. 1 I ST PORTF<3> data input; disabled when analog input enabled. AN8 1 I ANA A/D Input Channel 8 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. RF4/AN9 RF4 0 O DIG LATF<4> data output; not affected by analog input. 1 I ST PORTF<4> data input; disabled when analog input enabled. AN9 1 I ANA A/D Input Channel 9 and Comparator C2- input. Default input configuration on POR; does not affect digital output. RF5/AN10/ RF5 0 O DIG LATF<5> data output; not affected by analog input. Disabled when CVREF CVREF output enabled. 1 I ST PORTF<5> data input; disabled when analog input enabled. Disabled when CVREF output enabled. AN10 1 I ANA A/D Input Channel 10 and Comparator C1+ input. Default input configuration on POR. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RF6/AN11 RF6 0 O DIG LATF<6> data output; not affected by analog input. 1 I ST PORTF<6> data input; disabled when analog input enabled. AN11 1 I ANA A/D Input Channel 11 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RF7/SS1 RF7 0 O DIG LATF<7> data output. 1 I ST PORTF<7> data input. SS1 1 I TTL Slave select input for MSSP (MSSP1 module). Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — 56 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 — 56 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — 56 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 55 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. © 2009 Microchip Technology Inc. DS39663F-page 141
PIC18F87J10 FAMILY 11.8 PORTG, TRISG and Although the port is only five bits wide, PORTG<7:5> LATG Registers bits are still implemented. These are used to control the weak pull-ups on the I/O ports associated with the PORTG is a 5-bit wide, bidirectional port. The corre- external memory bus (PORTD, PORTE and PORTJ). sponding Data Direction register is TRISG. Setting a Setting these bits enables the pull-ups. Since these are TRISG bit (= 1) will make the corresponding PORTG control bits and are not associated with port I/O, the pin an input (i.e., put the corresponding output driver in corresponding TRISG and LATG bits are not a high-impedance mode). Clearing a TRISG bit (= 0) implemented. will make the corresponding PORTG pin an output (i.e., put the contents of the output latch on the selected pin). EXAMPLE 11-7: INITIALIZING PORTG All pins on PORTG are digital only and tolerate voltages up to 5.5V. CLRF PORTG ; Initialize PORTG by ; clearing output The Output Latch register (LATG) is also memory ; data latches mapped. Read-modify-write operations on the LATG CLRF LATG ; Alternate method register read and write the latched output value for ; to clear output PORTG. ; data latches MOVLW 04h ; Value used to PORTG is multiplexed with EUSART2 functions ; initialize data (Table11-15). PORTG pins have Schmitt Trigger input ; direction buffers. MOVWF TRISG ; Set RG1:RG0 as outputs When enabling peripheral functions, care should be ; RG2 as input ; RG4:RG3 as inputs taken in defining TRIS bits for each PORTG pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. DS39663F-page 142 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 11-15: PORTG FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RG0/ECCP3/ RG0 0 O DIG LATG<0> data output. P3A 1 I ST PORTG<0> data input. ECCP3 O DIG CCP3 compare and PWM output; takes priority over port data. I ST CCP3 capture input. P3A 0 O DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RG1/TX2/CK2 R21 0 O DIG LATG<1> data output. 1 I ST PORTG<1> data input. TX2 1 O DIG Synchronous serial data output (EUSART2 module); takes priority over port data. CK2 1 O DIG Synchronous serial data input (EUSART2 module). User must configure as an input. 1 I ST Synchronous serial clock input (EUSART2 module). RG2/RX2/DT2 RG2 0 O DIG LATG<2> data output. 1 I ST PORTG<2> data input. RX2 1 I ST Asynchronous serial receive data input (EUSART2 module). DT2 1 O DIG Synchronous serial data output (EUSART2 module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART2 module). User must configure as an input. RG3/CCP4/ RG3 0 O DIG LATG<3> data output. P3D 1 I ST PORTG<3> data input. CCP4 0 O DIG CCP4 compare output and CCP4 PWM output; takes priority over port data. 1 I ST CCP4 capture input. P3D 0 O DIG ECCP3 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RG4/CCP5/ RG4 0 O DIG LATG<4> data output. P1D 1 I ST PORTG<4> data input. CCP5 0 O DIG CCP5 compare output and CCP5 PWM output; takes priority over port data. 1 I ST CCP5 capture input. P1D 0 O DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTG RDPU REPU RJPU(1) RG4 RG3 RG2 RG1 RG0 56 LATG — — — LATG4 LATG3 LATG2 LATG1 LATG0 56 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. DS39663F-page 143
PIC18F87J10 FAMILY 11.9 PORTH, LATH and When the external memory interface is enabled, four of TRISH Registers the PORTH pins function as the high-order address lines for the interface. The address output from the Note: PORTH is available only on 80-pin interface takes priority over other digital I/O. The devices. corresponding TRISH bits are also overridden. PORTH is an 8-bit wide, bidirectional I/O port. The cor- PORTH pins, RH4 through RH7, are multiplexed with responding Data Direction register is TRISH. Setting a analog converter inputs. The operation of these pins as TRISH bit (= 1) will make the corresponding PORTH analog inputs is selected by clearing or setting the pin an input (i.e., put the corresponding output driver in PCFG<3:0> control bits in the ADCON1 register. a high-impedance mode). Clearing a TRISH bit (= 0) PORTH can also be configured as the alternate will make the corresponding PORTH pin an output (i.e., Enhanced PWM output Channels B and C for the put the contents of the output latch on the selected pin). ECCP1 and ECCP3 modules. This is done by clearing PORTH<3:0> pins are digital only and tolerate voltages the ECCPMX Configuration bit. up to 5.5V. The Output Latch register (LATH) is also memory EXAMPLE 11-8: INITIALIZING PORTH mapped. Read-modify-write operations on the LATH CLRF PORTH ; Initialize PORTH by register read and write the latched output value for ; clearing output PORTH. ; data latches CLRF LATH ; Alternate method All pins on PORTH are implemented with Schmitt ; to clear output Trigger input buffers. Each pin is individually ; data latches configurable as an input or output. MOVLW 0Fh ; Configure PORTH as MOVWF ADCON1 ; digital I/O MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISH ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs ; RH7:RH6 as inputs DS39663F-page 144 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 11-17: PORTH FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RH0/A16 RH0 0 O DIG LATH<0> data output. 1 I ST PORTH<0> data input. A16 x O DIG External memory interface, address line 16. Takes priority over port data. RH1/A17 RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. A17 x O DIG External memory interface, address line 17. Takes priority over port data. RH2/A18 RH2 0 O DIG LATH<2> data output. 1 I ST PORTH<2> data input. A18 x O DIG External memory interface, address line 18. Takes priority over port data. RH3/A19 RH3 0 O DIG LATH<3> data output. 1 I ST PORTH<3> data input. A19 x O DIG External memory interface, address line 19. Takes priority over port data. RH4/AN12/P3C RH4 0 O DIG LATH<4> data output. 1 I ST PORTH<4> data input. AN12 I ANA A/D input channel 12. Default input configuration on POR; does not affect digital output. P3C(1) 0 O DIG ECCP3 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RH5/AN13/P3B RH5 0 O DIG LATH<5> data output. 1 I ST PORTH<5> data input. AN13 I ANA A/D input channel 13. Default input configuration on POR; does not affect digital output. P3B(1) 0 O DIG ECCP3 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RH6/AN14/P1C RH6 0 O DIG LATH<6> data output. 1 I ST PORTH<6> data input. AN14 I ANA A/D input channel 14. Default input configuration on POR; does not affect digital output. P1C(1) 0 O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RH7/AN15/P1B RH7 0 O DIG LATH<7> data output. 1 I ST PORTH<7> data input. AN15 I ANA A/D input channel 15. Default input configuration on POR; does not affect digital output. P1B(1) 0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments are PORTE<6:3>. TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTH RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 56 LATH LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 56 TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 56 © 2009 Microchip Technology Inc. DS39663F-page 145
PIC18F87J10 FAMILY 11.10 PORTJ, TRISJ and When the external memory interface is enabled, all of LATJ Registers the PORTJ pins function as control outputs for the interface. This occurs automatically when the interface Note: PORTJ is available only on 80-pin devices. is enabled by clearing the EBDIS control bit (MEMCON<7>). The TRISJ bits are also overridden. PORTJ is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISJ. Setting a Each of the PORTJ pins has a weak internal pull-up. TRISJ bit (= 1) will make the corresponding PORTJ pin The pull-ups are provided to keep the inputs at a known an input (i.e., put the corresponding output driver in a state for the external memory interface while powering high-impedance mode). Clearing a TRISJ bit (= 0) will up. A single control bit can turn off all the pull-ups. This make the corresponding PORTJ pin an output (i.e., put is performed by clearing bit, RJPU (PORTG<5>). The the contents of the output latch on the selected pin). All weak pull-up is automatically turned off when the port pins on PORTJ are digital only and tolerate voltages up pin is configured as an output. The pull-ups are to 5.5V. disabled on any device Reset. The Output Latch register (LATJ) is also memory EXAMPLE 11-9: INITIALIZING PORTJ mapped. Read-modify-write operations on the LATJ register read and write the latched output value for CLRF PORTJ ; Initialize PORTG by PORTJ. ; clearing output ; data latches All pins on PORTJ are implemented with Schmitt CLRF LATJ ; Alternate method Trigger input buffers. Each pin is individually ; to clear output configurable as an input or output. ; data latches MOVLW 0CFh ; Value used to Note: These pins are configured as digital inputs ; initialize data on any device Reset. ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs DS39663F-page 146 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 11-19: PORTJ FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RJ0/ALE RJ0 0 O DIG LATJ<0> data output. 1 I ST PORTJ<0> data input. ALE x O DIG External memory interface address latch enable control output; takes priority over digital I/O. RJ1/OE RJ1 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input. OE x O DIG External memory interface output enable control output; takes priority over digital I/O. RJ2/WRL RJ2 0 O DIG LATJ<2> data output. 1 I ST PORTJ<2> data input. WRL x O DIG External memory bus write low byte control; takes priority over digital I/O. RJ3/WRH RJ3 0 O DIG LATJ<3> data output. 1 I ST PORTJ<3> data input. WRH x O DIG External memory interface write high byte control output; takes priority over digital I/O. RJ4/BA0 RJ4 0 O DIG LATJ<4> data output. 1 I ST PORTJ<4> data input. BA0 x O DIG External memory interface byte address 0 control output; takes priority over digital I/O. RJ5/CE RJ5 0 O DIG LATJ<5> data output. 1 I ST PORTJ<5> data input. CE x O DIG External memory interface chip enable control output; takes priority over digital I/O. RJ6/LB RJ6 0 O DIG LATJ<6> data output. 1 I ST PORTJ<6> data input. LB x O DIG External memory interface lower byte enable control output; takes priority over digital I/O. RJ7/UB RJ7 0 O DIG LATJ<7> data output. 1 I ST PORTJ<7> data input. UB x O DIG External memory interface upper byte enable control output; takes priority over digital I/O. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-20: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTJ RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 56 LATJ LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 56 TRISJ TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 56 PORTG RDPU REPU RJPU RG4 RG3 RG2 RG1 RG0 56 Legend: Shaded cells are not used by PORTJ. © 2009 Microchip Technology Inc. DS39663F-page 147
PIC18F87J10 FAMILY 11.11 Parallel Slave Port FIGURE 11-2: PORTD AND PORTE BLOCK DIAGRAM PORTD can also function as an 8-bit wide Parallel (PARALLEL SLAVE PORT) Slave Port, or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set. It is asynchronously readable and writable by the external world through RD Data Bus D Q control input pin (RE0/RD) and WR control input pin RDx (RE1/WR). WR LATD Pin CK or Note: For 80-pin devices, the Parallel Slave Port PORTD Data Latch TTL is available only in Microcontroller mode. Q D The PSP can directly interface to an 8-bit micro- processor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting RD PORTD ENEN the PSPMODE bit enables port pin, RE0/RD, to be the TRIS Latch RD input, RE1/WR to be the WR input and RE2/CS to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register RD LATD (TRISE<2:0>) must be configured as inputs (set). A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are One bit of PORTD detected high. The PSPIF and IBF flag bits are both set Set Interrupt Flag when the write ends. PSPIF (PIR1<7>) A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit is set. If the user writes new data to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines are detected high, the Read TTL RD PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set Chip Select TTL CS before servicing the PSP. When this happens, the IBF and OBF bits can be polled and the appropriate action Write taken. TTL WR The timing for the control signals in Write and Read Note: I/O pin has protection diodes to VDD and VSS. modes is shown in Figure11-3 and Figure11-4, respectively. DS39663F-page 148 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 11-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word had not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF © 2009 Microchip Technology Inc. DS39663F-page 149
PIC18F87J10 FAMILY FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 56 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 56 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 56 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 56 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 56 PSPCON IBF OBF IBOV PSPMODE — — — — 55 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. DS39663F-page 150 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 12.0 TIMER0 MODULE The T0CON register (Register12-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software-selectable operation as a timer or counter A simplified block diagram of the Timer0 module in 8-bit in both 8-bit or 16-bit modes mode is shown in Figure12-1. Figure12-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. DS39663F-page 151
PIC18F87J10 FAMILY 12.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter. The timer/counter. mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on 12.2 Timer0 Reads and Writes in every clock by default unless a different prescaler value 16-Bit Mode is selected (see Section12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited TMR0H is not the actual high byte of Timer0 in 16-bit for the following two instruction cycles. The user can mode. It is actually a buffered version of the real high work around this by writing an adjusted value to the byte of Timer0 which is not directly readable nor writ- TMR0 register. able (refer to Figure12-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of The Counter mode is selected by setting the T0CS bit TMR0L. This provides the ability to read all 16 bits of (= 1). In this mode, Timer0 increments either on every Timer0 without having to verify that the read of the high rising or falling edge of pin RA4/T0CKI. The increment- and low byte were valid, due to a rollover between ing edge is determined by the Timer0 Source Edge successive reads of the high and low byte. Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input Similarly, a write to the high byte of Timer0 must also are discussed below. take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a An external clock source can be used to drive Timer0; write occurs to TMR0L. This allows all 16 bits of Timer0 however, it must meet certain requirements to ensure to be updated at once. that the external clock can be synchronized with the FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI Pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) T0CS 3 8 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with TMR0 Set 1 Internal TMR0L High Byte TMR0IF T0CKI Pin ProPgrreasmcamlearble 0 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39663F-page 152 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 12.3 Prescaler 12.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. The prescaler assignment is fully under software Its value is set by the PSA and T0PS<2:0> bits control and can be changed “on-the-fly” during program (T0CON<3:0>) which determine the prescaler execution. assignment and prescale ratio. 12.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0 from 1:2 through 1:256 in power-of-2 increments are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before TMR0, BSF TMR0, etc.) clear the prescaler count. re-enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TMR0L Timer0 Register Low Byte 54 TMR0H Timer0 Register High Byte 54 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 54 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. DS39663F-page 153
PIC18F87J10 FAMILY NOTES: DS39663F-page 154 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 13.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is shown in Figure13-1. A block diagram of the module’s The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure13-2. features: The module incorporates its own low-power oscillator • Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1 counter oscillator can also be used as a low-power clock source • Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation. and TMR1L) Timer1 can also be used to provide Real-Time Clock • Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal device clock or Timer1 oscillator internal options addition of external components and code overhead. • Interrupt-on-overflow Timer1 is controlled through the T1CON Control • Reset on CCP Special Event Trigger register (Register13-1). It also contains the Timer1 • Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from the RC0/T1OSO/T13CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. DS39663F-page 155
PIC18F87J10 FAMILY 13.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled. • Timer When Timer1 is enabled, the RC1/T1OSI and • Synchronous Counter RC0/T1OSO/T13CKI pins become inputs. This means • Asynchronous Counter the values of TRISC<1:0> are ignored and the pins are read as ‘0’. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input On/Off 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Set Clear TMR1 TMR1L HiTgMh RBy1te TMR1IF (CCP Special Event Trigger) on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 T1CKPS<1:0> On/Off T1SYNC TMR1ON Clear TMR1 TMR1L HiTgMh RB1yte STMetR 1IF (CCP Special Event Trigger) on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39663F-page 156 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 13.2 Timer1 16-Bit Read/Write Mode TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(2,3,4) Timer1 can be configured for 16-bit reads and writes (see Figure13-2). When the RD16 control bit Oscillator Freq. C1 C2 (T1CON<7>) is set, the address for TMR1H is mapped Type to a buffer register for the high byte of Timer1. A read LP 32kHz 27pF(1) 27pF(1) from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register. This Note1: Microchip suggests these values as a provides the user with the ability to accurately read all starting point in validating the oscillator 16 bits of Timer1 without having to determine whether circuit. a read of the high byte, followed by a read of the low 2: Higher capacitance increases the stability byte, has become invalid due to a rollover between of the oscillator but also increases the reads. start-up time. A write to the high byte of Timer1 must also take place 3: Since each resonator/crystal has its own through the TMR1H Buffer register. The Timer1 high characteristics, the user should consult byte is updated with the contents of TMR1H when a the resonator/crystal manufacturer for write occurs to TMR1L. This allows a user to write all appropriate values of external 16 bits to both the high and low bytes of Timer1 at once. components. The high byte of Timer1 is not directly readable or 4: Capacitor values are for design guidance writable in this mode. All reads and writes must take only. place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. 13.3.1 USING TIMER1 AS A The prescaler is only cleared on writes to TMR1L. CLOCK SOURCE 13.3 Timer1 Oscillator The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select An on-chip crystal oscillator circuit is incorporated bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device between pins T1OSI (input) and T1OSO (amplifier switches to SEC_RUN mode; both the CPU and output). It is enabled by setting the Timer1 Oscillator peripherals are clocked from the Timer1 oscillator. If the Enable bit, T1OSCEN (T1CON<3>). The oscillator is a IDLEN bit (OSCCON<7>) is cleared and a SLEEP low-power circuit rated for 32kHz crystals. It will instruction is executed, the device enters SEC_IDLE continue to run during all power-managed modes. The mode. Additional details are available in Section4.0 circuit for a typical LP oscillator is shown in Figure13-3. “Power-Managed Modes”. Table13-1 shows the capacitor selection for the Timer1 Whenever the Timer1 oscillator is providing the clock oscillator. source, the Timer1 System Clock Status Flag, T1RUN The user must provide a software time delay to ensure (T1CON<6>), is set. This can be used to determine the proper start-up of the Timer1 oscillator. controller’s current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe FIGURE 13-3: EXTERNAL Clock Monitor. If the Clock Monitor is enabled and the COMPONENTS FOR THE Timer1 oscillator fails while providing the clock, polling TIMER1 LP OSCILLATOR the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. C1 PIC18F87J10 27 pF 13.3.2 LOW-POWER TIMER1 OPTION T1OSI The Timer1 oscillator can operate at two distinct levels of power consumption based on device configuration. XTAL When the LPT1OSC Configuration bit is set, the Timer1 32.768 kHz oscillator operates in a low-power mode. When LPT1OSC is not set, Timer1 operates at a higher power T1OSO C2 level. Power consumption for a particular mode is rela- 27 pF tively constant regardless of the device’s operating mode. The default Timer1 configuration is the higher Note: See the Notes with Table13-1 for additional power mode. information about capacitor selection. As the low-power Timer1 mode tends to be more sensitive to interference, high noise environments may cause some oscillator instability. The low-power option is, therefore, best suited for low noise applications where power conservation is an important design consideration. © 2009 Microchip Technology Inc. DS39663F-page 157
PIC18F87J10 FAMILY 13.3.3 TIMER1 OSCILLATOR LAYOUT 13.5 Resetting Timer1 Using the ECCP CONSIDERATIONS Special Event Trigger The Timer1 oscillator circuit draws very little power If ECCP1 or ECCP2 is configured to use Timer1 and to during operation. Due to the low-power nature of the generate a Special Event Trigger in Compare mode oscillator, it may also be sensitive to rapidly changing (CCPxM<3:0>=1011), this signal will reset Timer3. signals in close proximity. The trigger from ECCP2 will also start an A/D conver- The oscillator circuit, shown in Figure13-3, should be sion if the A/D module is enabled (see Section18.2.1 located as close as possible to the microcontroller. “Special Event Trigger” for more information). There should be no circuits passing within the oscillator The module must be configured as either a timer or a circuit boundaries other than VSS or VDD. synchronous counter to take advantage of this feature. If a high-speed circuit must be located near the oscilla- When used this way, the CCPRxH:CCPRxL register tor (such as the ECCP1 pin in Output Compare or PWM pair effectively becomes a period register for Timer1. mode, or the primary oscillator using the OSC2 pin), a If Timer1 is running in Asynchronous Counter mode, grounded guard ring around the oscillator circuit, as this Reset operation may not work. shown in Figure13-4, may be helpful when used on a In the event that a write to Timer1 coincides with a single-sided PCB or in addition to a ground plane. Special Event Trigger, the write operation will take precedence. FIGURE 13-4: OSCILLATOR CIRCUIT WITH GROUNDED Note: The Special Event Triggers from the GUARD RING ECCPx module will not set the TMR1IF interrupt flag bit (PIR1<0>). VDD 13.6 Using Timer1 as a Real-Time Clock VSS Adding an external LP oscillator to Timer1 (such as the OSC1 one described in Section13.3 “Timer1 Oscillator” OSC2 above) gives users the option to include RTC function- ality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate RC0 the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can RC1 completely eliminate the need for a separate RTC device and battery backup. RC2 The application code routine, RTCisr, shown in Example13-1, demonstrates a simple method to Note: Not drawn to scale. increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls 13.4 Timer1 Interrupt the routine which increments the seconds counter by The TMR1 register pair (TMR1H:TMR1L) increments one. Additional counters for minutes and hours are from 0000h to FFFFh and rolls over to 0000h. The incremented as the previous counter overflows. Timer1 interrupt, if enabled, is generated on overflow Since the register pair is 16 bits wide, counting up to which is latched in interrupt flag bit, TMR1IF overflow the register directly from a 32.768kHz clock (PIR1<0>). This interrupt can be enabled or disabled would take 2 seconds. To force the overflow at the by setting or clearing the Timer1 Interrupt Enable bit, required one-second intervals, it is necessary to pre- TMR1IE (PIE1<0>). load it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1) as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. DS39663F-page 158 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done CLRF hours ; Reset hours RETURN ; Done TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 TMR1L Timer1 Register Low Byte 54 TMR1H Timer1 Register High Byte 54 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54 Legend: Shaded cells are not used by the Timer1 module. © 2009 Microchip Technology Inc. DS39663F-page 159
PIC18F87J10 FAMILY NOTES: DS39663F-page 160 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 14.0 TIMER2 MODULE 14.1 Timer2 Operation The Timer2 module incorporates the following features: In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 4-bit counter/prescaler on the • 8-Bit Timer and Period registers (TMR2 and PR2, clock input gives direct input, divide-by-4 and respectively) divide-by-16 prescale options. These are selected by • Readable and writable (both registers) the prescaler control bits, T2CKPS<1:0> • Software programmable prescaler (T2CON<1:0>). The value of TMR2 is compared to that (1:1, 1:4 and 1:16) of the Period register, PR2, on each clock cycle. When • Software programmable postscaler the two values match, the comparator generates a (1:1 through 1:16) match signal as the timer output. This signal also resets • Interrupt on TMR2 to PR2 match the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section14.2 • Optional use as the shift clock for the “Timer2 Interrupt”). MSSP module The TMR2 and PR2 registers are both directly readable The module is controlled through the T2CON register and writable. The TMR2 register is cleared on any (Register14-1) which enables or disables the timer and device Reset, while the PR2 register initializes at FFh. configures the prescaler and postscaler. Timer2 can be Both the prescaler and postscaler counters are cleared shut off by clearing control bit, TMR2ON (T2CON<2>), on the following events: to minimize power consumption. • a write to the TMR2 register A simplified block diagram of the module is shown in Figure14-1. • a write to the T2CON register • any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 © 2009 Microchip Technology Inc. DS39663F-page 161
PIC18F87J10 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 Output Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2 to PR2 match) pro- the CCP modules, where it is used as a time base for vides the input for the 4-bit output counter/postscaler. operations in PWM mode. This counter generates the TMR2 match interrupt flag Timer2 can be optionally used as the shift clock source which is latched in TMR2IF (PIR1<1>). The interrupt is for the MSSP module operating in SPI mode. enabled by setting the TMR2 Match Interrupt Enable Additional information is provided in Section19.0 bit, TMR2IE (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set TMR2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSP) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 TMR2 Timer2 Register 54 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 54 PR2 Timer2 Period Register 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. DS39663F-page 162 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 15.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure15-1. A block diagram of the module’s The Timer3 timer/counter module incorporates these operation in Read/Write mode is shown in Figure15-2. features: The Timer3 module is controlled through the T3CON • Software selectable operation as a 16-bit timer or register (Register15-1). It also selects the clock source counter options for the CCP and ECCP modules; see • Readable and writable 8-bit registers (TMR3H Section17.1.1 “CCP Modules and Timer and TMR3L) Resources” for more information. • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 15-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits 11 =Timer3 and Timer4 are the clock sources for all CCP/ECCP modules 10 =Timer3 and Timer4 are the clock sources for ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 and ECCP2 01 =Timer3 and Timer4 are the clock sources for ECCP2, ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 00 = Timer1 and Timer2 are the clock sources for all CCP/ECCP modules bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. DS39663F-page 163
PIC18F87J10 FAMILY 15.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared Timer3 can operate in one of three modes: (= 0), Timer3 increments on every internal instruction • Timer cycle (FOSC/4). When the bit is set, Timer3 increments • Synchronous Counter on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. • Asynchronous Counter As with Timer1, the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. FIGURE 15-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 On/Off T3CKPS<1:0> T3SYNC TMR3ON CCPx Special Event Trigger Clear TMR3 TMR3 Set CCPx Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 15-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T13CKI/T1OSO 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 T3CKPS<1:0> On/Off T3SYNC TMR3ON CCPx Special Event Trigger Clear TMR3 TMR3 Set CCPx Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39663F-page 164 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes The TMR3 register pair (TMR3H:TMR3L) increments (see Figure15-2). When the RD16 control bit from 0000h to FFFFh and overflows to 0000h. The (T3CON<7>) is set, the address for TMR3H is mapped Timer3 interrupt, if enabled, is generated on overflow to a buffer register for the high byte of Timer3. A read and is latched in interrupt flag bit, TMR3IF (PIR2<1>). from TMR3L will load the contents of the high byte of This interrupt can be enabled or disabled by setting or Timer3 into the Timer3 High Byte Buffer register. This clearing the Timer3 Interrupt Enable bit, TMR3IE provides the user with the ability to accurately read all (PIE2<1>). 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low 15.5 Resetting Timer3 Using the ECCP byte, has become invalid due to a rollover between Special Event Trigger reads. If ECCP1 or ECCP2 is configured to use Timer3 and to A write to the high byte of Timer3 must also take place generate a Special Event Trigger in Compare mode through the TMR3H Buffer register. The Timer3 high (CCPxM<3:0>=1011), this signal will reset Timer3. byte is updated with the contents of TMR3H when a The trigger from ECCP2 will also start an A/D conver- write occurs to TMR3L. This allows a user to write all sion if the A/D module is enabled (see Section18.2.1 16 bits to both the high and low bytes of Timer3 at once. “Special Event Trigger” for more information). The high byte of Timer3 is not directly readable or The module must be configured as either a timer or writable in this mode. All reads and writes must take synchronous counter to take advantage of this feature. place through the Timer3 High Byte Buffer register. When used this way, the CCPRxH:CCPRxL register Writes to TMR3H do not clear the Timer3 prescaler. pair effectively becomes a period register for Timer3. The prescaler is only cleared on writes to TMR3L. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. 15.3 Using the Timer1 Oscillator as the Timer3 Clock Source In the event that a write to Timer3 coincides with a Special Event Trigger from an ECCP module, the write The Timer1 internal oscillator may be used as the clock will take precedence. source for Timer3. The Timer1 oscillator is enabled by Note: The Special Event Triggers from the setting the T1OSCEN (T1CON<3>) bit. To use it as the ECCPx module will not set the TMR3IF Timer3 clock source, the TMR3CS bit must also be set. interrupt flag bit (PIR1<0>). As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section13.0 “Timer1 Module”. TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR2 OSCFIF CMIF — — BCL1IF — TMR3IF CCP2IF 55 PIE2 OSCFIE CMIE — — BCL1IE — TMR3IE CCP2IE 55 IPR2 OSCFIP CMIP — — BCL1IP — TMR3IP CCP2IP 55 TMR3L Timer3 Register Low Byte 55 TMR3H Timer3 Register High Byte 55 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. DS39663F-page 165
PIC18F87J10 FAMILY NOTES: DS39663F-page 166 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 16.0 TIMER4 MODULE 16.1 Timer4 Operation The Timer4 timer module has the following features: Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is • 8-Bit Timer register (TMR4) readable and writable and is cleared on any device • 8-Bit Period register (PR4) Reset. The input clock (FOSC/4) has a prescale option • Readable and writable (both registers) of 1:1, 1:4 or 1:16, selected by control bits • Software programmable prescaler (1:1, 1:4, 1:16) T4CKPS<1:0> (T4CON<1:0>). The match output of • Software programmable postscaler (1:1 to 1:16) TMR4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR4 • Interrupt on TMR4 match of PR4 interrupt, latched in flag bit, TMR4IF (PIR3<3>). Timer4 has a control register shown in Register16-1. The prescaler and postscaler counters are cleared Timer4 can be shut off by clearing control bit, TMR4ON when any of the following occurs: (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 are also • a write to the TMR4 register controlled by this register. Figure16-1 is a simplified • a write to the T4CON register block diagram of the Timer4 module. • any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR4 is not cleared when T4CON is written. REGISTER 16-1: T4CON: TIMER4 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T4OUTPS<3:0>: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off bit 1-0 T4CKPS<1:0>: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 © 2009 Microchip Technology Inc. DS39663F-page 167
PIC18F87J10 FAMILY 16.2 Timer4 Interrupt 16.3 Output of TMR4 The Timer4 module has an 8-Bit Period register, PR4, The output of TMR4 (before the postscaler) is used which is both readable and writable. Timer4 increments only as a PWM time base for the CCP modules. It is not from 00h until it matches PR4 and then resets to 00h on used as a baud rate clock for the MSSP as is the the next increment cycle. The PR4 register is initialized Timer2 output. to FFh upon Reset. FIGURE 16-1: TIMER4 BLOCK DIAGRAM 4 1:1 to 1:16 T4OUTPS<3:0> Set TMR4IF Postscaler 2 T4CKPS<1:0> TMR4 Output (to PWM) TMR4/PR4 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR4 Comparator PR4 Prescaler 8 8 8 Internal Data Bus TABLE 16-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 TMR4 Timer4 Register 57 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 57 PR4 Timer4 Period Register 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module. DS39663F-page 168 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 17.0 CAPTURE/COMPARE/PWM register. For the sake of clarity, all CCP module opera- (CCP) MODULES tion in the following sections is described with respect to CCP4, but is equally applicable to CCP5. Members of the PIC18F87J10 family of devices all have Capture and compare operations described in this a total of five CCP (Capture/Compare/PWM) modules. chapter apply to all standard and Enhanced CCP Two of these (CCP4 and CCP5) implement standard modules. The operations of PWM mode, described in Capture, Compare and Pulse-Width Modulation (PWM) Section17.4 “PWM Mode”, apply to CCP4 and CCP5 modes and are discussed in this section. The other three only. modules (ECCP1, ECCP2, ECCP3) implement standard Capture and Compare modes, as well as Note: Throughout this section and Section18.0 Enhanced PWM modes. These are discussed in “Enhanced Capture/Compare/PWM (ECCP) Section18.0 “Enhanced Capture/Compare/PWM Module”, references to register and bit names (ECCP) Module”. that may be associated with a specific CCP module are referred to generically by the use of Each CCP/ECCP module contains a 16-bit register ‘x’ or ‘y’ in place of the specific module number. which can operate as a 16-Bit Capture register, a 16-Bit Thus, “CCPxCON” might refer to the control Compare register or a PWM Master/Slave Duty Cycle register for ECCP1, ECCP2, ECCP3, CCP4 or CCP5. REGISTER 17-1: CCPxCON: CCPx CONTROL REGISTER (CCP4 AND CCP5) U0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: CCP Module x PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCxB<9:2>) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCP Module x Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode; initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode; initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Reserved 11xx = PWM mode © 2009 Microchip Technology Inc. DS39663F-page 169
PIC18F87J10 FAMILY 17.1 CCP Module Configuration The assignment of a particular timer to a module is determined by the Timer to CCP enable bits in the Each Capture/Compare/PWM module is associated T3CON register (Register15-1, page163). Depending with a control register (generically, CCPxCON) and a on the configuration selected, up to four timers may be data register (CCPRx). The data register, in turn, is active at once, with modules in the same configuration comprised of two 8-bit registers: CCPRxL (low byte) (capture/compare or PWM) sharing timer resources. and CCPRxH (high byte). All registers are both The possible configurations are shown in Figure17-1. readable and writable. 17.1.2 ECCP2 PIN ASSIGNMENT 17.1.1 CCP MODULES AND TIMER The pin assignment for ECCP2 (capture input, RESOURCES compare and PWM output) can change, based on The CCP/ECCP modules utilize Timers 1, 2, 3 or 4, device configuration. The CCP2MX Configuration bit depending on the mode selected. Timer1 and Timer3 determines which pin ECCP2 is multiplexed to. By are available to modules in Capture or Compare default, it is assigned to RC1 (CCP2MX = 1). If the modes, while Timer2 and Timer4 are available for Configuration bit is cleared, ECCP2 is multiplexed with modules in PWM mode. RE7 on 64-pin devices and RB3 or RE7 on 80-pin devices depending on mode setting. TABLE 17-1: CCP MODE – TIMER Changing the pin assignment of ECCP2 does not auto- RESOURCE matically change any requirements for configuring the CCP Mode Timer Resource port pin. Users must always verify that the appropriate TRIS register is configured correctly for ECCP2 Capture Timer1 or Timer3 operation regardless of where it is located. Compare Timer1 or Timer3 PWM Timer2 or Timer4 FIGURE 17-1: CCP/ECCP AND TIMER INTERCONNECT CONFIGURATIONS T3CCP<2:1> = 00 T3CCP<2:1> = 01 T3CCP<2:1> = 10 T3CCP<2:1> = 11 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 ECCP1 ECCP1 ECCP1 ECCP1 ECCP2 ECCP2 ECCP2 ECCP2 ECCP3 ECCP3 ECCP3 ECCP3 CCP4 CCP4 CCP4 CCP4 CCP5 CCP5 CCP5 CCP5 TMR2 TMR4 TMR2 TMR4 TMR2 TMR4 TMR2 TMR4 Timer1 is used for all capture Timer1 and Timer2 are used Timer1 and Timer2 are used Timer3 is used for all capture and compare operations for for capture and compare or for capture and compare or and compare operations for all CCP modules. Timer2 is PWM operations for ECCP1 PWM operations for ECCP1 all CCP modules. Timer4 is used for PWM operations for only (depending on selected and ECCP2 only (depending used for PWM operations for all CCP modules. Modules mode). on the mode selected for each all CCP modules. Modules may share either timer All other modules use either module). Both modules may may share either timer resource as a common time Timer3 or Timer4. Modules use a timer as a common time resource as a common time base. may share either timer base if they are both in base. Timer3 and Timer4 are not resource as a common time capture/compare or PWM Timer1 and Timer2 are not modes. available. base if they are in available. capture/compare or PWM The other modules use either modes. Timer3 or Timer4. Modules may share either timer resource as a common time base if they are in capture/compare or PWM modes. DS39663F-page 170 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 17.2 Capture Mode 17.2.3 SOFTWARE INTERRUPT In Capture mode, the CCPRxH:CCPRxL register pair When the Capture mode is changed, a false capture captures the 16-bit value of the TMR1 or TMR3 interrupt may be generated. The user should keep the registers when an event occurs on the corresponding CCPxIE interrupt enable bit clear to avoid false CCPx pin. An event is defined as one of the following: interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. • every falling edge • every rising edge 17.2.4 CCP PRESCALER • every 4th rising edge There are four prescaler settings in Capture mode. • every 16th rising edge They are specified as part of the operating mode The event is selected by the mode select bits, selected by the mode select bits (CCPxM<3:0>). Whenever the CCP module is turned off or Capture CCPxM<3:0> (CCPxCON<3:0>). When a capture is mode is disabled, the prescaler counter is cleared. This made, the interrupt request flag bit, CCPxIF, is set; it means that any Reset will clear the prescaler counter. must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old Switching from one capture prescaler to another may captured value is overwritten by the new captured value. generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from 17.2.1 CCP PIN CONFIGURATION a non-zero prescaler. Example17-1 shows the In Capture mode, the appropriate CCPx pin should be recommended method for switching between capture configured as an input by setting the corresponding prescalers. This example also clears the prescaler TRIS direction bit. counter and will not generate the “false” interrupt. Note: If RG4/CCP5 is configured as an output, a EXAMPLE 17-1: CHANGING BETWEEN write to the port can cause a capture CAPTURE PRESCALERS condition. (CCP5 SHOWN) 17.2.2 TIMER1/TIMER3 MODE SELECTION CLRF CCP5CON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load WREG with the The timers that are to be used with the capture feature ; new prescaler mode (Timer1 and/or Timer3) must be running in Timer mode or ; value and CCP ON Synchronized Counter mode. In Asynchronous Counter MOVWF CCP5CON ; Load CCP5CON with mode, the capture operation will not work. The timer to be ; this value used with each CCP module is selected in the T3CON register (see Section17.1.1 “CCP Modules and Timer Resources”). FIGURE 17-2: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP4IF T3CCP2 TMR3 Enable CCP4 pin Prescaler and CCPR4H CCPR4L ÷ 1, 4, 16 Edge Detect TMR1 T3CCP2 Enable 4 TMR1H TMR1L CCP4CON<3:0> Set CCP5IF 4 Q1:Q4 4 CCP5CON<3:0> T3CCP1 TMR3H TMR3L T3CCP2 TMR3 Enable CCP5 pin Prescaler and CCPR5H CCPR5L ÷ 1, 4, 16 Edge Detect TMR1 Enable T3CCP2 T3CCP1 TMR1H TMR1L © 2009 Microchip Technology Inc. DS39663F-page 171
PIC18F87J10 FAMILY 17.3 Compare Mode Note: Clearing the CCP5CON register will force the RG4 compare output latch (depend- In Compare mode, the 16-Bit CCPRx register value is ing on device configuration) to the default constantly compared against either the TMR1 or TMR3 low level. This is not the PORTB or register pair value. When a match occurs, the CCPx pin PORTC I/O data latch. can be: • driven high 17.3.2 TIMER1/TIMER3 MODE SELECTION • driven low Timer1 and/or Timer3 must be running in Timer mode • toggled (high-to-low or low-to-high) or Synchronized Counter mode if the CCP module is • remains unchanged (that is, reflects the state of using the compare feature. In Asynchronous Counter the I/O latch) mode, the compare operation may not work. The action on the pin is based on the value of the mode 17.3.3 SOFTWARE INTERRUPT MODE select bits (CCPxM<3:0>). At the same time, the interrupt flag bit, CCPxIF, is set. When the Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the corresponding CCPx pin is 17.3.1 CCP PIN CONFIGURATION not affected. Only a CCP interrupt is generated, if enabled and the CCPxIE bit is set. The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit. FIGURE 17-3: COMPARE MODE OPERATION BLOCK DIAGRAM Set CCP4IF CCPR4H CCPR4L CCP4 Pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCP4CON<3:0> 0 TMR1H TMR1L 0 1 TMR3H TMR3L 1 T3CCP1 T3CCP2 Set CCP5IF CCP5 Pin Comparator Compare Output S Q Match Logic R TRIS 4 Output Enable CCPR5H CCPR5L CCP5CON<3:0> DS39663F-page 172 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 17-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 RCON IPEN — — RI TO PD POR BOR 54 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR2 OSCFIF CMIF — — BCL1IF — TMR3IF CCP2IF 55 PIE2 OSCFIE CMIE — — BCL1IE — TMR3IE CCP2IE 55 IPR2 OSCFIP CMIP — — BCL1IP — TMR3IP CCP2IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 56 TMR1L Timer1 Register Low Byte 54 TMR1H Timer1 Register High Byte 54 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54 TMR3H Timer3 Register High Byte 55 TMR3L Timer3 Register Low Byte 55 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 55 CCPR4L Capture/Compare/PWM Register 4 Low Byte 57 CCPR4H Capture/Compare/PWM Register 4 High Byte 57 CCPR5L Capture/Compare/PWM Register 5 Low Byte 57 CCPR5H Capture/Compare/PWM Register 5 High Byte 57 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 57 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by capture/compare, Timer1 or Timer3. © 2009 Microchip Technology Inc. DS39663F-page 173
PIC18F87J10 FAMILY 17.4 PWM Mode 17.4.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCPx pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since (PR4) register. The PWM period can be calculated the CCP4 and CCP5 pins are multiplexed with a using Equation17-1: PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. EQUATION 17-1: Note: Clearing the CCP4CON or CCP5CON PWM Period = [(PR2) + 1] • 4 • TOSC • register will force the RG3 or RG4 output (TMR2 Prescale Value) latch (depending on device configuration) to the default low level. This is not the PWM frequency is defined as 1/[PWM period]. PORTG I/O data latch. When TMR2 (TMR4) is equal to PR2 (PR4), the Figure17-4 shows a simplified block diagram of the following three events occur on the next increment CCP module in PWM mode. cycle: For a step-by-step procedure on how to set up a CCP • TMR2 (TMR4) is cleared module for PWM operation, see Section17.4.3 • The CCPx pin is set (exception: if PWM duty “Setup for PWM Operation”. cycle=0%, the CCPx pin will not be set) • The PWM duty cycle is latched from CCPRxL into FIGURE 17-4: SIMPLIFIED PWM BLOCK CCPRxH DIAGRAM Note: The Timer2 and Timer 4 postscalers (see Duty Cycle Register Section14.0 “Timer2 Module” and 9 0 Section16.0 “Timer4 Module”) are not CCPR1L CCP1CON<5:4> used in the determination of the PWM frequency. The postscaler could be used Latch Duty Cycle to have a servo update rate at a different CCPR1H (1) frequency than the PWM output. Comparator S Q 17.4.2 PWM DUTY CYCLE R ECCP1 The PWM duty cycle is specified by writing to the Reset TMR2 Pin CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available. The CCPRxL contains TMR2 = PR2 Match 2 LSbs Latched the eight MSbs and the CCPxCON<5:4> contains the Comparator from Q Clocks two LSbs. This 10-bit value is represented by CCPRxL:CCPxCON<5:4>. Equation17-2 is used to PR2 calculate the PWM duty cycle in time. TRIS Set CCPx pin Output Enable EQUATION 17-2: Note1: The two LSbs of the Duty Cycle register are held by a 2-bit latch that is part of the module’s hardware. It is physically separate from the CCPR registers. PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) • TOSC • (TMR2 Prescale Value) A PWM output (Figure17-5) has a time base (period) and a time that the output stays high (duty cycle). CCPRxL and CCPxCON<5:4> can be written to at any The frequency of the PWM is the inverse of the time, but the duty cycle value is not latched into period (1/period). CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. FIGURE 17-5: PWM OUTPUT Period Duty Cycle TMR2 (TMR4) = PR2 (PR4) TMR2 (TMR4) = Duty Cycle TMR2 (TMR4) = PR2 (TMR4) DS39663F-page 174 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY The CCPRxH register and a 2-bit internal latch are 17.4.3 SETUP FOR PWM OPERATION used to double-buffer the PWM duty cycle. This The following steps should be taken when configuring double-buffering is essential for glitchless PWM the CCP module for PWM operation: operation. 1. Set the PWM period by writing to the PR2 (PR4) When the CCPRxH and 2-bit latch match TMR2 register. (TMR4), concatenated with an internal 2-bit Q clock or 2. Set the PWM duty cycle by writing to the 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is CCPRxL register and CCPxCON<5:4> bits. cleared. 3. Make the CCPx pin an output by clearing the The maximum PWM resolution (bits) for a given PWM appropriate TRIS bit. frequency is given by Equation17-3: 4. Set the TMR2 (TMR4) prescale value, then enable Timer2 (Timer4) by writing to T2CON EQUATION 17-3: (T4CON). (FOSC ) log 5. Configure the CCPx module for PWM operation. FPWM PWM Resolution (max) = bits log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 © 2009 Microchip Technology Inc. DS39663F-page 175
PIC18F87J10 FAMILY TABLE 17-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 RCON IPEN — — RI TO PD POR BOR 54 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 56 TMR2 Timer2 Register 54 PR2 Timer2 Period Register 54 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 54 TMR4 Timer4 Register 57 PR4 Timer4 Period Register 57 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 57 CCPR4L Capture/Compare/PWM Register 4 Low Byte 57 CCPR4H Capture/Compare/PWM Register 4 High Byte 57 CCPR5L Capture/Compare/PWM Register 5 Low Byte 57 CCPR5H Capture/Compare/PWM Register 5 High Byte 57 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 57 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4. DS39663F-page 176 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 18.0 ENHANCED CAPTURE/ The control register for the Enhanced CCP module is COMPARE/PWM (ECCP) shown in Register18-1. It differs from the CCP4CON/ CCP5CON registers in that the two Most Significant MODULE bits are implemented to control PWM functionality. In the PIC18F87J10 family of devices, three of the CCP In addition to the expanded range of modes available modules are implemented as standard CCP modules through the Enhanced CCPxCON register, the ECCP with Enhanced PWM capabilities. These include the modules each have two additional registers associated provision for 2 or 4 output channels, user-selectable with Enhanced PWM operation and auto-shutdown polarity, dead-band control and automatic shutdown features. They are: and restart. The Enhanced features are discussed in • ECCPxDEL (Dead-Band Delay) detail in Section18.4 “Enhanced PWM Mode”. Capture, Compare and single-output PWM functions of • ECCPxAS (Auto-Shutdown Configuration) the ECCP module are the same as described for the standard CCP module. REGISTER 18-1: CCPxCON: ENHANCED CCPx CONTROL REGISTER (ECCP1/ECCP2/ECCP3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as capture/compare input/output; PxB, PxC, PxD assigned as port pins If CCPxM<3:2> = 11: 00 = Single output: PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DCxB<1:0>: PWM Duty Cycle Bit 1 and Bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the 2 LSbs of the 10-bit PWM duty cycle. The 8 MSbs of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: Enhanced CCP Module x Mode Select bits 0000 =Capture/Compare/PWM off (resets ECCPx module) 0001 =Reserved 0010 =Compare mode, toggle output on match 0011 =Capture mode 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, initialize ECCPx pin low, set output on compare match (set CCPxIF) 1001 =Compare mode, initialize ECCPx pin high, clear output on compare match (set CCPxIF) 1010 =Compare mode, generate software interrupt only, ECCPx pin reverts to I/O state 1011 =Compare mode, trigger special event (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCP2 trigger also starts A/D conversion if A/D module is enabled)(1) 1100 =PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 =PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 =PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 =PWM mode: PxA, PxC active-low; PxB, PxD active-low Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3. © 2009 Microchip Technology Inc. DS39663F-page 177
PIC18F87J10 FAMILY 18.1 ECCP Outputs and Configuration 18.1.2 ECCP2 OUTPUTS AND PROGRAM MEMORY MODES Each of the Enhanced CCP modules may have up to four PWM outputs, depending on the selected For 80-pin devices, the program memory mode of the operating mode. These outputs, designated PxA device (Section6.1.3 “PIC18F8XJ10/8XJ15 Program through PxD, are multiplexed with various I/O pins. Memory Modes”) also impacts pin multiplexing for the Some ECCP pin assignments are constant, while module. others change based on device configuration. For The ECCP2 input/output (ECCP2/P2A) can be multi- those pins that do change, the controlling bits are: plexed to one of three pins. The default assignment • CCP2MX Configuration bit (CCP2MX Configuration bit is set) for all devices is RC1. Clearing CCP2MX reassigns ECCP2/P2A to • ECCPMX Configuration bit (80-pin devices only) RE7. • Program Memory Operating mode, set by the EMB Configuration bits (80-pin devices only) An additional option exists for 80-pin devices. When these devices are operating in Microcontroller mode, The pin assignments for the Enhanced CCP modules the multiplexing options described above still apply. In are summarized in Table18-1, Table18-2 and Extended Microcontroller mode, clearing CCP2MX Table18-3. To configure the I/O pins as PWM outputs, reassigns ECCP2/P2A to RB3. the proper PWM mode must be selected by setting the PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>, 18.1.3 USE OF CCP4 AND CCP5 WITH respectively). The appropriate TRIS direction bits for ECCP1 AND ECCP3 the corresponding port pins must also be set as outputs. Only the ECCP2 module has four dedicated output pins that are available for use. Assuming that the I/O ports 18.1.1 ECCP1/ECCP3 OUTPUTS AND or other multiplexed functions on those pins are not PROGRAM MEMORY MODE needed, they may be used whenever needed without interfering with any other CCP module. In 80-pin devices, the use of Extended Microcontroller mode has an indirect effect on the use of ECCP1 and ECCP1 and ECCP3, on the other hand, only have ECCP3 in Enhanced PWM modes. By default, PWM three dedicated output pins: ECCPx/PxA, PxB and outputs, P1B/P1C and P3B/P3C, are multiplexed to PxC. Whenever these modules are configured for PORTE pins, along with the high-order byte of the Quad PWM mode, the pin normally used for CCP4 or external memory bus. When the bus is active in CCP5 becomes the PxD output pins for ECCP3 and Extended Microcontroller mode, it overrides the ECCP1, respectively. The CCP4 and CCP5 modules Enhanced CCP outputs and makes them unavailable. remain functional but their outputs are overridden. Because of this, ECCP1 and ECCP3 can only be used in compatible (single-output) PWM modes when the 18.1.4 ECCP MODULES AND TIMER device is in Extended Microcontroller mode and default RESOURCES pin configuration. Like the standard CCP modules, the ECCP modules An exception to this configuration is when a 12-bit can utilize Timers 1, 2, 3 or 4, depending on the mode address width is selected for the external bus selected. Timer1 and Timer3 are available for modules (EMB<1:0> Configuration bits = 01). In this case, the in Capture or Compare modes, while Timer2 and upper pins of PORTE continue to operate as digital I/O, Timer4 are available for modules in PWM mode. even when the external bus is active. P1B/P1C and Additional details on timer resources are provided in P3B/P3C remain available for use as Enhanced PWM Section17.1.1 “CCP Modules and Timer outputs. Resources”. If an application requires the use of additional PWM outputs during Enhanced microcontroller operation, the P1B/P1C and P3B/P3C outputs can be reassigned to the upper bits of PORTH. This is done by clearing the ECCPMX Configuration bit. DS39663F-page 178 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 18-1: PIN CONFIGURATIONS FOR ECCP1 CCP1CON ECCP Mode RC2 RE6 RE5 RG4 RH7 RH6 Configuration All PIC18F6XJ10/6XJ15 Devices: Compatible CCP 00xx 11xx ECCP1 RE6 RE5 RG4/CCP5 N/A N/A Dual PWM 10xx 11xx P1A P1B RE5 RG4/CCP5 N/A N/A Quad PWM x1xx 11xx P1A P1B P1C P1D N/A N/A PIC18F8XJ10/8XJ15 Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A RE6/AD14 RE5/AD13 RG4/CCP5 P1B RH6/AN14 Quad PWM x1xx 11xx P1A RE6/AD14 RE5/AD13 P1D P1B P1C PIC18F8XJ10/8XJ15 Devices, ECCPMX = 1, Extended Microcontroller mode, 16-Bit or 20-Bit Address Width: Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 PIC18F8XJ10/8XJ15 Devices, ECCPMX = 1, Microcontroller mode or Extended Microcontroller mode, 12-Bit Address Width: Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A P1B RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Quad PWM x1xx 11xx P1A P1B P1C P1D RH7/AN15 RH6/AN14 Legend: x = Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. Note 1: With ECCP1 in Quad PWM mode, CCP5’s output is overridden by P1D; otherwise, CCP5 is fully operational. TABLE 18-2: PIN CONFIGURATIONS FOR ECCP2 CCP2CON ECCP Mode RB3 RC1 RE7 RE2 RE1 RE0 Configuration All Devices, CCP2MX = 1, Either Operating mode: Compatible CCP 00xx 11xx RB3/INT3 ECCP2 RE7 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 P2A RE7 P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 P2A RE7 P2B P2C P2D All Devices, CCP2MX = 0, Microcontroller mode: Compatible CCP 00xx 11xx RB3/INT3 RC1/T1OS1 ECCP2 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 RC1/T1OS1 P2A P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 RC1/T1OS1 P2A P2B P2C P2D PIC18F8XJ10/8XJ15 Devices, CCP2MX = 0, Extended Microcontroller mode: Compatible CCP 00xx 11xx ECCP2 RC1/T1OS1 RE7/AD15 RE2/CS RE1/WR RE0/RD Dual PWM 10xx 11xx P2A RC1/T1OS1 RE7/AD15 P2B RE1/WR RE0/RD Quad PWM x1xx 11xx P2A RC1/T1OS1 RE7/AD15 P2B P2C P2D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. © 2009 Microchip Technology Inc. DS39663F-page 179
PIC18F87J10 FAMILY TABLE 18-3: PIN CONFIGURATIONS FOR ECCP3 CCP3CON ECCP Mode RG0 RE4 RE3 RG3 RH5 RH4 Configuration All PIC18F6XJ10/6XJ15 Devices: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RG3/CCP4 N/A N/A Dual PWM 10xx 11xx P3A P3B RE3 RG3/CCP4 N/A N/A Quad PWM x1xx 11xx P3A P3B P3C P3D N/A N/A PIC18F8XJ10/8XJ15 Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P3A RE6/AD14 RE5/AD13 RG3/CCP4 P3B RH6/AN14 Quad PWM x1xx 11xx P3A RE6/AD14 RE5/AD13 P3D P3B P3C PIC18F8XJ10/8XJ15 Devices, ECCPMX = 1, Extended Microcontroller mode, 16-Bit or 20-Bit Address Width: Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14 PIC18F8XJ10/8XJ15 Devices, ECCPMX = 1, Microcontroller mode or Extended Microcontroller mode, 12-Bit Address Width: Compatible CCP 00xx 11xx ECCP3 RE4/AD12 RE3/AD11 RG3/CCP4 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A P3B RE3/AD11 RG3/CCP4 RH5/AN13 RH4/AN12 Quad PWM x1xx 11xx P3A P3B P3C P3D RH5/AN13 RH4/AN12 Legend: x = Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode. Note 1: With ECCP3 in Quad PWM mode, CCP4’s output is overridden by P1D; otherwise, CCP4 is fully operational. 18.2 Capture and Compare Modes Special Event Triggers are not implemented for ECCP3, CCP4 or CCP5. Selecting the Special Event Except for the operation of the Special Event Trigger Trigger mode for these modules has the same effect as discussed below, the Capture and Compare modes of selecting the Compare with Software Interrupt mode the ECCP module are identical in operation to that of (CCPxM<3:0> = 1010). CCP4. These are discussed in detail in Section17.2 “Capture Mode” and Section17.3 “Compare Note: The Special Event Trigger from ECCP2 Mode”. will not set the Timer1 or Timer3 interrupt flag bits. 18.2.1 SPECIAL EVENT TRIGGER ECCP1 and ECCP2 incorporate an internal hardware 18.3 Standard PWM Mode trigger that is generated in Compare mode on a match When configured in Single Output mode, the ECCP between the CCPRx register pair and the selected module functions identically to the standard CCP timer. This can be used in turn to initiate an action. This module in PWM mode, as described in Section17.4 mode is selected by setting CCPxCON<3:0> to ‘1011’. “PWM Mode”. This is also sometimes referred to as The Special Event Trigger output of either ECCP1 or “Compatible CCP” mode as in Tables18-1 ECCP2 resets the TMR1 or TMR3 register pair, depend- through18-3. ing on which timer resource is currently selected. This Note: When setting up single-output PWM allows the CCPRx register pair to effectively be a 16-bit operations, users are free to use either of programmable period register for Timer1 or Timer3. In the processes described in Section17.4.3 addition, the ECCP2 Special Event Trigger will also start “Setup for PWM Operation” or an A/D conversion if the A/D module is enabled. Section18.4.9 “Setup for PWM Opera- tion”. The latter is more generic but will work for either single or multi-output PWM. DS39663F-page 180 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 18.4 Enhanced PWM Mode waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction The Enhanced PWM mode provides additional PWM cycle (4 TOSC). output options for a broader range of control applica- As before, the user must manually configure the tions. The module is a backward compatible version of appropriate TRIS bits for output. the standard CCP module and offers up to four outputs, designated PxA through PxD. Users are also able to 18.4.1 PWM PERIOD select the polarity of the signal (either active-high or active-low). The module’s output mode and polarity The PWM period is specified by writing to the PR2 areconfigured by setting the PxM<1:0> and register. The PWM period can be calculated using the CCPxM<3:0> bits of the CCPxCON register equation: (CCPxCON<7:6> and CCPxCON<3:0>, respectively). EQUATION 18-1: For the sake of clarity, Enhanced PWM mode operation is described generically throughout this section with PWM Period = [(PR2) + 1] • 4 • TOSC • respect to ECCP1 and TMR2 modules. Control register (TMR2 Prescale Value) names are presented in terms of ECCP1. All three Enhanced modules, as well as the two timer resources, PWM frequency is defined as 1/[PWM period]. When can be used interchangeably and function identically. TMR2 is equal to PR2, the following three events occur TMR2 or TMR4 can be selected for PWM operation by on the next increment cycle: selecting the proper bits in T3CON. • TMR2 is cleared Figure18-1 shows a simplified block diagram of PWM • The ECCP1 pin is set (if PWM duty cycle=0%, operation. All control registers are double-buffered and the ECCP1 pin will not be set) are loaded at the beginning of a new PWM cycle (the • The PWM duty cycle is copied from CCPR1L into period boundary when Timer2 resets) in order to pre- CCPR1H vent glitches on any of the outputs. The exception is the PWM Delay register, ECCP1DEL, which is loaded at Note: The Timer2 postscaler (see Section14.0 either the duty cycle boundary or the boundary period “Timer2 Module”) is not used in the (whichever comes first). Because of the buffering, the determination of the PWM frequency. The module waits until the assigned timer resets instead of postscaler could be used to have a servo starting immediately. This means that Enhanced PWM update rate at a different frequency than the PWM output. FIGURE 18-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> P1M1<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L ECCP1/P1A ECCP1/P1A TRISx<x> CCPR1H (Slave) P1B P1B Output TRISx<x> Comparator R Q Controller P1C P1C TMR2 (Note 1) S TRISx<x> Comparator P1D P1D Clear Timer, TRISx<x> set ECCP1 pin and PR2 latch D.C. ECCP1DEL Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. DS39663F-page 181
PIC18F87J10 FAMILY 18.4.2 PWM DUTY CYCLE Note: If the PWM duty cycle value is longer than The PWM duty cycle is specified by writing to the the PWM period, the ECCP1 pin will not CCPR1L register and to the CCP1CON<5:4> bits. Up be cleared. to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the 18.4.3 PWM OUTPUT CONFIGURATIONS two LSbs. This 10-bit value is represented by The P1M<1:0> bits in the CCP1CON register allow one CCPR1L:CCP1CON<5:4>. The PWM duty cycle is of four configurations: calculated by the equation: • Single Output EQUATION 18-2: • Half-Bridge Output PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • • Full-Bridge Output, Forward mode TOSC • (TMR2 Prescale Value) • Full-Bridge Output, Reverse mode The Single Output mode is the standard PWM mode CCPR1L and CCP1CON<5:4> can be written to at any discussed in Section18.4 “Enhanced PWM Mode”. time but the duty cycle value is not copied into The Half-Bridge and Full-Bridge Output modes are CCPR1H until a match between PR2 and TMR2 occurs covered in detail in the sections that follow. (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The general relationship of the outputs in all configurations is summarized in Figure18-2. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM opera- tion. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the ECCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: EQUATION 18-3: log(FOSC) FPWM PWM Resolution (max) = bits log(2) TABLE 18-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 DS39663F-page 182 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 18-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 PR2 + 1 Duty CCP1CON<7:6> SIGNAL Cycle Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive FIGURE 18-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 Duty PR2 + 1 CCP1CON<7:6> SIGNAL Cycle Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive P1B Modulated (Full-Bridge, 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: The dead-band delay is programmed using the ECCP1DEL register (Section18.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. DS39663F-page 183
PIC18F87J10 FAMILY 18.4.4 HALF-BRIDGE MODE FIGURE 18-4: HALF-BRIDGE PWM OUTPUT In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output Period Period signal is output on the P1A pin, while the complemen- tary PWM output signal is output on the P1B pin Duty Cycle (Figure18-4). This mode can be used for half-bridge P1A(2) applications, as shown in Figure18-5, or for full-bridge td applications, where four power switches are being td modulated with two PWM signals. P1B(2) In Half-Bridge Output mode, the programmable dead-band delay can be used to prevent shoot-through (1) (1) (1) current in half-bridge power devices. The value of bits, P1DC<6:0>, sets the number of instruction cycles td = Dead Band Delay before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains Note 1: At this time, the TMR2 register is equal to the inactive during the entire cycle. See Section18.4.6 PR2 register. “Programmable Dead-Band Delay” for more details 2: The output signals are shown as active-high. on dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTE<6> data latches, the TRISC<2> and TRISE<6> bits must be cleared to configure P1A and P1B as outputs. FIGURE 18-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) PIC18F87J10 FET Driver + P1A V - Load FET Driver + P1B V - V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F87J10 FET FET Driver Driver P1A Load FET FET Driver Driver P1B V- DS39663F-page 184 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 18.4.5 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the port pins as described in Table18-1, Table18-2 In Full-Bridge Output mode, four pins are used as and Table18-3. The corresponding TRIS bits must be outputs; however, only two outputs are active at a time. cleared to make the P1A, P1B, P1C and P1D pins In the Forward mode, pin P1A is continuously active outputs. and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure18-6. FIGURE 18-6: FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: The output signal is shown as active-high. © 2009 Microchip Technology Inc. DS39663F-page 185
PIC18F87J10 FAMILY FIGURE 18-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F87J10 FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D 18.4.5.1 Direction Change in Full-Bridge Mode 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ 2. The turn-off time of the power switch, including reverse direction. When the application firmware the power device and driver circuit, is greater changes this direction control bit, the module will than the turn-on time. assume the new direction on the next PWM cycle. Figure18-9 shows an example where the PWM direc- Just before the end of the current PWM period, the tion changes from forward to reverse at a near 100% modulated outputs (P1B and P1D) are placed in their duty cycle. At time t1, the outputs P1A and P1D inactive state, while the unmodulated outputs (P1A and become inactive, while output P1C becomes active. In P1C) are switched to drive in the opposite direction. this example, since the turn-off time of the power This occurs in a time interval of (4 TOSC * (Timer2 devices is longer than the turn-on time, a shoot-through Prescale Value) before the next PWM period begins. current may flow through power devices QC and QD The Timer2 prescaler will be either 1, 4 or 16, depend- (see Figure18-7) for the duration of ‘t’. The same ing on the value of the T2CKPS bits (T2CON<1:0>). phenomenon will occur to power devices QA and QB During the interval from the switch of the unmodulated for PWM direction change from reverse to forward. outputs to the beginning of the next period, the If changing PWM direction at high duty cycle is required modulated outputs (P1B and P1D) remain inactive. for an application, one of the following requirements This relationship is shown in Figure18-8. must be met: Note that in the Full-Bridge Output mode, the ECCP1 1. Reduce PWM for a PWM period before module does not provide any dead-band delay. In changing directions. general, since only one output is modulated at all times, 2. Use switch drivers that can drive the switches off dead-band delay is not required. However, there is a faster than they can drive them on. situation where a dead-band delay might be required. Other options to prevent shoot-through current may This situation occurs when both of the following exist. conditions are true: DS39663F-page 186 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 18-8: PWM DIRECTION CHANGE Period(1) Period SIGNAL P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written at any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 18-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A(1) P1B(1) DC P1C(1) P1D(1) DC t (2) ON External Switch C(1) t (3) OFF External Switch D(1) Potential t = t – t (2,3) OFF ON Shoot-Through Current(1) Note 1: All signals are shown as active-high. 2: t is the turn-on delay of power switch, QC, and its driver. ON 3: t is the turn-off delay of power switch, QD, and its driver. OFF © 2009 Microchip Technology Inc. DS39663F-page 187
PIC18F87J10 FAMILY 18.4.6 PROGRAMMABLE DEAD-BAND A shutdown event can be caused by either of the two DELAY comparator modules or the FLT0 pin (or any combination of these three sources). The comparators may be used In half-bridge applications, where all power switches to monitor a voltage input proportional to a current being are modulated at the PWM frequency at all times, the monitored in the bridge circuit. If the voltage exceeds a power switches normally require more time to turn off threshold, the comparator switches state and triggers a than to turn on. If both the upper and lower power shutdown. Alternatively, a low-level digital signal on the switches are switched at the same time (one turned on FLT0 pin can also trigger a shutdown. The and the other turned off), both switches may be on for auto-shutdown feature can be disabled by not selecting a short period of time until one switch completely turns any auto-shutdown sources. The auto-shutdown sources off. During this brief interval, a very high current to be used are selected using the ECCP1AS<2:0> bits (shoot-through current) may flow through both power (bits<6:4> of the ECCP1AS register). switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flow- When a shutdown occurs, the output pins are ing during switching, turning on either of the power asynchronously placed in their shutdown states, switches is normally delayed to allow the other switch specified by the PSS1AC<1:0> and PSS1BD<1:0> bits to completely turn off. (ECCP1AS<3:0>). Each pin pair (P1A/P1C and P1B/ P1D) may be set to drive high, drive low or be tri-stated In the Half-Bridge Output mode, a digitally program- (not driving). The ECCP1ASE bit (ECCP1AS<7>) is mable dead-band delay is available to avoid also set to hold the Enhanced PWM outputs in their shoot-through current from destroying the bridge shutdown states. power switches. The delay occurs at the signal transition from the non-active state to the active state. The ECCP1ASE bit is set by hardware when a See Figure18-4 for illustration. The lower seven bits of shutdown event occurs. If automatic restarts are not the ECCP1DEL register (Register18-2) set the delay enabled, the ECCP1ASE bit is cleared by firmware period in terms of microcontroller instruction cycles when the cause of the shutdown clears. If automatic (TCY or 4 TOSC). restarts are enabled, the ECCP1ASE bit is automati- cally cleared when the cause of the auto-shutdown has 18.4.7 ENHANCED PWM cleared. AUTO-SHUTDOWN If the ECCP1ASE bit is set when a PWM period begins, When the ECCP1 is programmed for any of the the PWM outputs remain in their shutdown state for that Enhanced PWM modes, the active output pins may be entire PWM period. When the ECCP1ASE bit is configured for auto-shutdown. Auto-shutdown immedi- cleared, the PWM outputs will return to normal ately places the Enhanced PWM output pins into a operation at the beginning of the next PWM period. defined shutdown state when a shutdown event Note: Writing to the ECCP1ASE bit is disabled occurs. while a shutdown condition is active. REGISTER 18-2: ECCPxDEL: PWM DEAD-BAND DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPxASE must be cleared in software to restart the PWM bit 6-0 PxDC<6:0>: PWM Delay Count bits Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. DS39663F-page 188 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 18-3: ECCPxAS: ENHANCED CCPx AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPxASE: ECCPx Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCPx outputs are in a shutdown state 0 = ECCPx outputs are operating bit 6-4 ECCPxAS<2:0>: ECCPx Auto-Shutdown Source Select bits 111 = FLT0 or Comparator 1 or Comparator 2 110 = FLT0 or Comparator 2 101 = FLT0 or Comparator 1 100 = FLT0 011 = Either Comparator 1 or 2 010 = Comparator 2 output 001 = Comparator 1 output 000 = Auto-shutdown is disabled bit 3-2 PSSxAC<1:0>: Pins A and C Shutdown State Control bits 1x = Pins A and C tri-state 01 = Drive Pins A and C to ‘1’ 00 = Drive Pins A and C to ‘0’ bit 1-0 PSSxBD<1:0>: Pins B and D Shutdown State Control bits(1) 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ 00 = Drive Pins B and D to ‘0’ 18.4.7.1 Auto-Shutdown and Automatic The Auto-Shutdown mode can be forced by writing a ‘1’ Restart to the ECCP1ASE bit. The auto-shutdown feature can be configured to allow 18.4.8 START-UP CONSIDERATIONS automatic restarts of the module following a shutdown event. This is enabled by setting the P1RSEN bit of the When the ECCP1 module is used in the PWM mode, ECCP1DEL register (ECCP1DEL<7>). the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output In Shutdown mode with P1RSEN = 1 (Figure18-10), pins. When the microcontroller is released from Reset, the ECCP1ASE bit will remain set for as long as the all of the I/O pins are in the high-impedance state. The cause of the shutdown continues. When the shutdown external circuits must keep the power switch devices in condition clears, the ECCP1ASE bit is cleared. If the OFF state until the microcontroller drives the I/O P1RSEN =0 (Figure18-11), once a shutdown condi- pins with the proper signal levels, or activates the PWM tion occurs, the ECCP1ASE bit will remain set until it is output(s). cleared by firmware. Once ECCP1ASE is cleared, the Enhanced PWM will resume at the beginning of the The CCP1M<1:0> bits (CCP1CON<1:0>) allow the next PWM period. user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output Note: Writing to the ECCP1ASE bit is disabled pins (P1A/P1C and P1B/P1D). The PWM output while a shutdown condition is active. polarities must be selected before the PWM pins are Independent of the P1RSEN bit setting, if the configured as outputs. Changing the polarity configura- auto-shutdown source is one of the comparators, the tion while the PWM pins are configured as outputs is shutdown condition is a level. The ECCP1ASE bit not recommended since it may result in damage to the cannot be cleared as long as the cause of the shutdown application circuits. persists. © 2009 Microchip Technology Inc. DS39663F-page 189
PIC18F87J10 FAMILY The P1A, P1B, P1C and P1D output latches may not be proper output mode and complete a full PWM cycle in the proper states when the PWM module is initialized. before configuring the PWM pins as outputs. The com- Enabling the PWM pins for output at the same time as pletion of a full PWM cycle is indicated by the TMR2IF the ECCP1 module may cause damage to the applica- bit being set as the second PWM period begins. tion circuit. The ECCP1 module must be enabled in the FIGURE 18-10: PWM AUTO-SHUTDOWN (P1RSEN = 1, AUTO-RESTART ENABLED) PWM Period ShutdownEvent ECCP1ASE bit PWM Activity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes FIGURE 18-11: PWM AUTO-SHUTDOWN (P1RSEN = 0, AUTO-RESTART DISABLED) PWM Period ShutdownEvent ECCP1ASE bit PWM Activity Normal PWM ECCP1ASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes DS39663F-page 190 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 18.4.9 SETUP FOR PWM OPERATION 8. If auto-restart operation is required, set the PxRSEN bit (ECCPxDEL<7>). The following steps should be taken when configuring the ECCPx module for PWM operation: 9. Configure and start TMRx (TMR2 or TMR4): • Clear the TMRx interrupt flag bit by clearing 1. Configure the PWM pins, PxA and PxB (and the TMRxIF bit (PIR1<1> for Timer2 or PxC and PxD, if used), as inputs by setting the PIR3<3> for Timer4). corresponding TRIS bits. • Set the TMRx prescale value by loading the 2. Set the PWM period by loading the PR2 (PR4) TxCKPS bits (TxCON<1:0>). register. • Enable Timer2 (or Timer4) by setting the 3. Configure the ECCPx module for the desired TMRxON bit (TxCON<2>). PWM mode and configuration by loading the CCPxCON register with the appropriate values: 10. Enable PWM outputs after a new PWM cycle has started: • Select one of the available output configurations and direction with the • Wait until TMRx overflows (TMRxIF bit is set). PxM<1:0> bits. • Enable the ECCPx/PxA, PxB, PxC and/or • Select the polarities of the PWM output PxD pin outputs by clearing the respective signals with the CCPxM<3:0> bits. TRIS bits. 4. Set the PWM duty cycle by loading the CCPRxL • Clear the ECCPxASE bit (ECCPxAS<7>). register and the CCPxCON<5:4> bits. 18.4.10 EFFECTS OF A RESET 5. For auto-shutdown: Both Power-on Reset and subsequent Resets will force • Disable auto-shutdown; ECCP1ASE = 0. all ports to Input mode and the ECCP registers to their • Configure auto-shutdown source. Reset states. • Wait for Run condition. This forces the Enhanced CCP module to reset to a 6. For Half-Bridge Output mode, set the state compatible with the standard CCP module. dead-band delay by loading ECCPxDEL<6:0> with the appropriate value. 7. If auto-shutdown operation is required, load the ECCPxAS register: • Select the auto-shutdown sources using the ECCPxAS<2:0> bits. • Select the shutdown states of the PWM output pins using the PSSxAC<1:0> and PSSxBD<1:0> bits. • Set the ECCPxASE bit (ECCPxAS<7>). © 2009 Microchip Technology Inc. DS39663F-page 191
PIC18F87J10 FAMILY TABLE 18-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 RCON IPEN — — RI TO PD POR BOR 54 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR2 OSCFIF CMIF — — BCL1IF — TMR3IF CCP2IF 55 PIE2 OSCFIE CMIE — — BCL1IE — TMR3IE CCP2IE 55 IPR2 OSCFIP CMIP — — BCL1IP — TMR3IP CCP2IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 56 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 56 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 56 TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 56 TMR1L Timer1 Register Low Byte 54 TMR1H Timer1 Register High Byte 54 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54 TMR2 Timer2 Register 54 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 54 PR2 Timer2 Period Register 54 TMR3L Timer3 Register Low Byte 55 TMR3H Timer3 Register High Byte 55 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 55 TMR4 Timer4 Register 57 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 57 PR4 Timer4 Period Register 57 CCPRxL(1) Capture/Compare/PWM Register x Low Byte 55 CCPRxH(1) Capture/Compare/PWM Register x High Byte 55, CCPxCON(1) PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 55 ECCPxAS(1) ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 55, 57 ECCPxDEL(1) PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: Generic term for all of the identical registers of this name for all Enhanced CCP modules, where ‘x’ identifies the individual module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same generic name are identical. DS39663F-page 192 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.0 MASTER SYNCHRONOUS 19.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four modes of SPI are supported. To accomplish 19.1 Master SSP (MSSP) Module communication, typically three pins are used: Overview • Serial Data Out (SDOx) – RC5/SDO1 or RD4/SDO2 The Master Synchronous Serial Port (MSSP) module is • Serial Data In (SDIx) – RC4/SDI1/SDA1 or a serial interface, useful for communicating with other RD5/SDI2/SDA2 peripheral or microcontroller devices. These peripheral • Serial Clock (SCKx) – RC3/SCK1/SCL1 or devices may be serial EEPROMs, shift registers, RD6/SCK2/SCL2 display drivers, A/D Converters, etc. The MSSP module can operate in one of two modes: Additionally, a fourth pin may be used when in a Slave mode of operation: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) • Slave Select (SSx) – RF7/SS1 or RD7/SS2 - Full Master mode Figure19-1 shows the block diagram of the MSSP - Slave mode (with general address call) module when operating in SPI mode. The I2C interface supports the following modes in FIGURE 19-1: MSSP BLOCK DIAGRAM hardware: (SPIMODE) • Master mode Internal • Multi-Master mode Data Bus • Slave mode (with address masking for both 10-bit Read Write and 7-bit addressing) All members of the PIC18F87J10 family have two SSPxBUF reg MSSP modules, designated as MSSP1 and MSSP2. Each module operates independently of the other. SDIx Note: Throughout this section, generic refer- ences to an MSSP module in any of its SSPxSR reg operating modes may be interpreted as SDOx bit 0 Shift Clock being equally applicable to MSSP1 or MSSP2. Register names and module I/O signals use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module when required. Control SSx SSxControl bit names are not individuated. Enable Edge 19.2 Control Registers Select Each MSSP module has three associated control regis- 2 ters. These include a status register (SSPxSTAT) and Clock Select two control registers (SSPxCON1 and SSPxCON2). The use of these registers and their individual Configuration SSPM<3:0> bits differ significantly depending on whether the MSSP SMP:CKE ( ) 4 TMR2 Output module is operated in SPI or I2C mode. SCKx 2 2 Edge Additional details are provided under the individual sections. Select Prescaler TOSC 4, 16, 64 Note: In devices with more than one MSSP Data to TXx/RXx in SSPxSR module, it is very important to pay close TRIS bit attention to SSPCON register names. SSP1CON1 and SSP1CON2 control Note: Only port I/O names are used in this diagram for different operational aspects of the same the sake of brevity. Refer to the text for a full list of module, while SSP1CON1 and multiplexed functions. SSP2CON1 control the same features for two different modules. © 2009 Microchip Technology Inc. DS39663F-page 193
PIC18F87J10 FAMILY 19.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data Each MSSP module has four registers for SPI mode bytes are written to or read from. operation. These are: In receive operations, SSPxSR and SSPxBUF • MSSP Control Register 1 (SSPxCON1) together create a double-buffered receiver. When • MSSP Status Register (SSPxSTAT) SSPxSR receives a complete byte, it is transferred to • Serial Receive/Transmit Buffer Register SSPxBUF and the SSPxIF interrupt is set. (SSPxBUF) During transmission, the SSPxBUF is not • MSSP Shift Register (SSPxSR) – Not directly double-buffered. A write to SSPxBUF will write to both accessible SSPxBUF and SSPxSR. SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. REGISTER 19-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE(1) D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Note 1: The polarity of the clock state is set by the CKP bit (SSPxCON1<4>). DS39663F-page 194 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 19-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of over- flow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins(2) bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin(3) 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled(3) 0011 = SPI Master mode, clock = TMR2 output/2(3) 0010 = SPI Master mode, clock = FOSC/64(3) 0001 = SPI Master mode, clock = FOSC/16(3) 0000 = SPI Master mode, clock = FOSC/4(3) Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. © 2009 Microchip Technology Inc. DS39663F-page 195
PIC18F87J10 FAMILY 19.3.2 OPERATION reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data When initializing the SPI, several options need to be will be ignored and the Write Collision Detect bit, WCOL specified. This is done by programming the appropriate (SSPxCON1<7>), will be set. User software must clear control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). the WCOL bit so that it can be determined if the following These control bits allow the following to be specified: write(s) to the SSPxBUF register completed • Master mode (SCKx is the clock output) successfully. • Slave mode (SCKx is the clock input) When the application software is expecting to receive • Clock Polarity (Idle state of SCKx) valid data, the SSPxBUF should be read before the next • Data Input Sample Phase (middle or end of data byte of data to transfer is written to the SSPxBUF. The output time) Buffer Full bit, BF (SSPxSTAT<0>), indicates when • Clock Edge (output data on rising/falling edge of SSPxBUF has been loaded with the received data SCKx) (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the • Clock Rate (Master mode only) SPI is only a transmitter. Generally, the MSSP interrupt • Slave Select mode (Slave mode only) is used to determine when the transmission/reception Each MSSP module consists of a transmit/receive shift has completed. If the interrupt method is not going to be register (SSPxSR) and a buffer register (SSPxBUF). used, then software polling can be done to ensure that a The SSPxSR shifts the data in and out of the device, write collision does not occur. Example19-1 shows the MSb first. The SSPxBUF holds the data that was written loading of the SSPxBUF (SSPxSR) for data to the SSPxSR until the received data is ready. Once the transmission. 8 bits of data have been received, that byte is moved to The SSPxSR is not directly readable or writable and the SSPxBUF register. Then, the Buffer Full detect bit, can only be accessed by addressing the SSPxBUF BF (SSPxSTAT<0>), and the interrupt flag bit, SSPxIF, register. Additionally, the SSPxSTAT register indicates are set. This double-buffering of the received data the various status conditions. (SSPxBUF) allows the next byte to start reception before EXAMPLE 19-1: LOADING THE SSP1BUF (SSP1SR) REGISTER LOOP BTFSS SSP1STAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSP1BUF, W ;WREG reg = contents of SSP1BUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSP1BUF ;New data to xmit DS39663F-page 196 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.3.3 ENABLING SPI I/O Any serial port function that is not desired may be overridden by programming the corresponding Data To enable the serial port, MSSP Enable bit, SSPEN Direction (TRIS) register to the opposite value. (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the 19.3.4 TYPICAL CONNECTION SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as Figure19-2 shows a typical connection between two serial port pins. For the pins to behave as the serial port microcontrollers. The master controller (Processor 1) function, some must have their data direction bits (in initiates the data transfer by sending the SCKx signal. the TRIS register) appropriately programmed as Data is shifted out of both shift registers on their pro- follows: grammed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to • SDIx is automatically controlled by the the same Clock Polarity (CKP), then both controllers SPI module would send and receive data at the same time. • SDOx must have the TRISC<5> or TRISD<4> bit Whether the data is meaningful (or dummy data) cleared depends on the application software. This leads to • SCKx (Master mode) must have the TRISC<3> or three scenarios for data transmission: TRISD<6>bit cleared • Master sends data – Slave sends dummy data • SCKx (Slave mode) must have the TRISC<3> or • Master sends data – Slave sends data TRISD<6> bit set • Master sends dummy data – Slave sends data • SSx must have the TRISF<7> or TRISD<7> bit set FIGURE 19-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDOx SDIx Serial Input Buffer Serial Input Buffer (SSPxBUF) (SSPxBUF) SDIx SDOx Shift Register Shift Register (SSPxSR) (SSPxSR) MSb LSb MSb LSb Serial Clock SCKx SCKx PROCESSOR 1 PROCESSOR 2 © 2009 Microchip Technology Inc. DS39663F-page 197
PIC18F87J10 FAMILY 19.3.5 MASTER MODE shown in Figure19-3, Figure19-5 and Figure19-6, where the MSB is transmitted first. In Master mode, the The master can initiate the data transfer at any time SPI clock rate (bit rate) is user programmable to be one because it controls the SCKx. The master determines of the following: when the slave (Processor 1, Figure19-2) is to broadcast data by the software protocol. • FOSC/4 (or TCY) In Master mode, the data is transmitted/received as • FOSC/16 (or 4 • TCY) soon as the SSPxBUF register is written to. If the SPI • FOSC/64 (or 16 • TCY) is only going to receive, the SDOx output could be dis- • Timer2 output/2 abled (programmed as an input). The SSPxSR register This allows a maximum data rate (at 40MHz) of will continue to shift in the signal present on the SDIx 10.00Mbps. pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as Figure19-3 shows the waveforms for Master mode. if a normal received byte (interrupts and status bits When the CKE bit is set, the SDOx data is valid before appropriately set). This could be useful in receiver there is a clock edge on SCKx. The change of the input applications as a “Line Activity Monitor” mode. sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received The clock polarity is selected by appropriately data is shown. programming the CKP bit (SSPxCON1<4>). This then, would give waveforms for SPI communication as FIGURE 19-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDIx (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF DS39663F-page 198 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.3.6 SLAVE MODE transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable In Slave mode, the data is transmitted and received as depending on the application. the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Note1: When the SPI is in Slave mode While in Slave mode, the external clock is supplied by with SSx pin control enabled the external clock source on the SCKx pin. This (SSPxCON1<3:0>=0100), the SPI external clock must meet the minimum high and low module will reset if the SSx pin is set to VDD. times as specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE While in Sleep mode, the slave can transmit/receive set, then the SSx pin control must be data. When a byte is received, the device can be enabled. configured to wake-up from Sleep. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SSx pin to 19.3.7 SLAVE SELECT a high level or clearing the SSPEN bit. SYNCHRONIZATION To emulate two-wire communication, the SDOx pin can The SSx pin allows a Synchronous Slave mode. The be connected to the SDIx pin. When the SPI needs to SPI must be in Slave mode with the SSx pin control operate as a receiver, the SDOx pin can be configured enabled (SSPxCON1<3:0> = 04h). When the SSx pin as an input. This disables transmissions from the is low, transmission and reception are enabled and the SDOx. The SDIx can always be left as an input (SDI SDOx pin is driven. When the SSx pin goes high, the function) since it cannot create a bus conflict. SDOx pin is no longer driven, even if in the middle of a FIGURE 19-4: SLAVE SYNCHRONIZATION WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 7 bit 0 SDIx bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF © 2009 Microchip Technology Inc. DS39663F-page 199
PIC18F87J10 FAMILY FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF FIGURE 19-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPxSR to SSPxBUF DS39663F-page 200 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.3.8 OPERATION IN POWER-MANAGED 19.3.10 BUS MODE COMPATIBILITY MODES Table19-1 shows the compatibility between the In SPI Master mode, module clocks may be operating standard SPI modes and the states of the CKP and at a different speed than when in Full-Power mode; in CKE control bits. the case of the Sleep mode, all clocks are halted. TABLE 19-1: SPI BUS MODES In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the Control Bits State Standard SPI Mode secondary clock (Timer1 oscillator) or the INTOSC Terminology CKP CKE source. See Section3.6 “Clock Sources and Oscillator Switching” for additional information. 0, 0 0 1 In most cases, the speed that the master clocks SPI 0, 1 0 0 data is not important; however, this should be 1, 0 1 1 evaluated for each system. 1, 1 1 0 If MSSP interrupts are enabled, they can wake the con- There is also an SMP bit which controls when the data troller from Sleep mode, or one of the Idle modes, when is sampled. the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts 19.3.11 SPI CLOCK SPEED AND MODULE should be disabled. INTERACTIONS If the Sleep mode is selected, all module clocks are Because MSSP1 and MSSP2 are independent halted and the transmission/reception will remain in modules, they can operate simultaneously at different that state until the devices wakes. After the device data rates. Setting the SSPM<3:0> bits of the returns to Run mode, the module will resume SSPxCON1 register determines the rate for the transmitting and receiving data. corresponding module. In SPI Slave mode, the SPI Transmit/Receive Shift An exception is when both modules use Timer2 as a register operates asynchronously to the device. This time base in Master mode. In this instance, any allows the device to be placed in any power-managed changes to the Timer2 module’s operation will affect mode and data to be shifted into the SPI both MSSP modules equally. If different bit rates are Transmit/Receive Shift register. When all 8 bits have required for each module, the user should select one of been received, the MSSP interrupt flag bit will be set the other three time base options for one of the and if enabled, will wake the device. modules. 19.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. © 2009 Microchip Technology Inc. DS39663F-page 201
PIC18F87J10 FAMILY TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 56 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — 56 SSP1BUF MSSP1 Receive Buffer/Transmit Register 54 SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 54, 57 SSPxSTAT SMP CKE D/A P S R/W UA BF 54, 57 SSP2BUF MSSP2 Receive Buffer/Transmit Register 57 Legend: Shaded cells are not used by the MSSP module in SPI mode. DS39663F-page 202 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4 I2C Mode 19.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call These are: support) and provides interrupts on Start and Stop bits • MSSP Control Register 1 (SSPxCON1) in hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPxCON2) function). The MSSP module implements the standard • MSSP Status Register (SSPxSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPxBUF) Two pins are used for data transfer: • MSSP Shift Register (SSPxSR) – Not directly • Serial clock (SCLx) – RC3/SCK1/SCL1 or accessible RD6/SCK2/SCL2 • MSSP Address Register (SSPxADD) • Serial data (SDAx) – RC4/SDI1/SDA1 or SSPxCON1, SSPxCON2 and SSPxSTAT are the RD5/SDI2/SDA2 control and status registers in I2C mode operation. The The user must configure these pins as inputs by setting SSPxCON1 and SSPxCON2 registers are readable and the associated TRIS bits. writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are FIGURE 19-7: MSSP BLOCK DIAGRAM read/write. (I2C™ MODE) SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data Internal bytes are written to or read from. Data Bus SSPxADD register holds the slave device address Read Write when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the SSPxBUF reg SCLx lower seven bits of SSPxADD act as the Baud Rate Generator reload value. Shift Clock In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When SSPxSR reg SSPxSR receives a complete byte, it is transferred to SDAx MSb LSb SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not Match Detect Addr Match double-buffered. A write to SSPxBUF will write to both Address Mask SSPxBUF and SSPxSR. SSPxADD reg Start and Set, Reset Stop bit Detect S, P bits (SSPxSTAT reg) Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. © 2009 Microchip Technology Inc. DS39663F-page 203
PIC18F87J10 FAMILY REGISTER 19-3: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode. DS39663F-page 204 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 19-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins(1) 0 = Disables serial port and configures these pins as I/O port pins(1) bit 4 CKP: SCKx Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch); used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled(2) 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled(2) 1011 = I2C Firmware Controlled Master mode (slave Idle)(2) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))(2) 0111 = I2C Slave mode, 10-bit address(2) 0110 = I2C Slave mode, 7-bit address(2) Note 1: When enabled, the SDAx and SCLx pins must be properly configured as input or output. 2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. © 2009 Microchip Technology Inc. DS39663F-page 205
PIC18F87J10 FAMILY REGISTER 19-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT/ ACKEN/ RCEN/ PEN/ RSEN/ SEN(2) ADMSK5(1) ADMSK4 ADMSK3 ADMSK2 ADMSK1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT/ADMSK5: Acknowledge Data bit (Master Receive mode only)(1) In Master Receive mode: 1 = Not Acknowledge 0 = Acknowledge In Slave mode: 1 = Address masking of ADD5 enabled 0 = Address masking of ADD5 disabled bit 4 ACKEN/ADMSK4: Acknowledge Sequence Enable bit In Master Receive mode:(2) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle In Slave mode: 1 = Address masking of ADD4 enabled 0 = Address masking of ADD4 disabled bit 3 RCEN/ADMSK3: Receive Enable bit (Master Receive mode only) In Master Receive mode:(2) 1 = Enables Receive mode for I2C 0 = Receive Idle In Slave mode: 1 = Address masking of ADD3 enabled 0 = Address masking of ADD3 disabled bit 2 PEN/ADMSK2: Stop Condition Enable bit In Master mode:(2) 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle In Slave mode: 1 = Address masking of ADD2 enabled 0 = Address masking of ADD2 disabled Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: For bits, ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). DS39663F-page 206 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 19-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MODE) (CONTINUED) bit 1 RSEN/ADMSK1: Repeated Start Condition Enable bit In Master mode:(2) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle In Slave mode (7-Bit Addressing mode): 1 = Address masking of ADD1 enabled 0 = Address masking of ADD1 disabled In Slave mode (10-Bit Addressing mode): 1 = Address masking of ADD1 and ADD0 enabled 0 = Address masking of ADD1 and ADD0 disabled bit 0 SEN: Start Condition Enable/Stretch Enable bit(2) In Master mode: 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: For bits, ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). © 2009 Microchip Technology Inc. DS39663F-page 207
PIC18F87J10 FAMILY REGISTER 19-6: SSPxADD: MSSP1 and MSSP2 ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADD<7:0>: MSSP Address bits Note 1: MSSP1 and MSSP2 Address register in I2C Slave mode. MSSP1 and MSSP2 Baud Rate Reload register in I2C Master mode. DS39663F-page 208 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.2 OPERATION 19.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPxCON1<5>). a Start condition to occur. Following the Start condition, The SSPxCON1 register allows control of the I2C the 8 bits are shifted into the SSPxSR register. All incoming bits are sampled with the rising edge of the operation. Four mode selection bits (SSPxCON1<3:0>) allow one of the following I2C modes to be selected: clock (SCLx) line. The value of register, SSPxSR<7:1>, is compared to the value of the SSPxADD register. The • I2C Master mode, clock address is compared on the falling edge of the eighth • I2C Slave mode (7-bit addressing) clock (SCLx) pulse. If the addresses match and the BF • I2C Slave mode (10-bit addressing) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit addressing) with Start and 1. The SSPxSR register value is loaded into the Stop bit interrupts enabled SSPxBUF register. • I2C Slave mode (10-bit addressing) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is 4. The MSSP Interrupt Flag bit, SSPxIF, is set (and Idle interrupt is generated, if enabled) on the falling Selection of any I2C mode with the SSPEN bit set edge of the ninth SCLx pulse. forces the SCLx and SDAx pins to be open-drain, In 10-Bit Addressing mode, two address bytes need to provided these pins are programmed as inputs by be received by the slave. The five Most Significant bits setting the appropriate TRISC or TRISD bits. To ensure (MSbs) of the first address byte specify if this is a 10-bit proper operation of the module, pull-up resistors must address. Bit, R/W (SSPxSTAT<2>), must specify a be provided externally to the SCLx and SDAx pins. write so the slave device will receive the second address byte. For a 10-bit address, the first byte would 19.4.3 SLAVE MODE equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the In Slave mode, the SCLx and SDAx pins must be two MSbs of the address. The sequence of events for configured as inputs (TRISC<4:3> set). The MSSP 10-bit addressing is as follows, with steps 7 through 9 module will override the input state with the output data for the slave-transmitter: when required (slave-transmitter). 1. Receive first (high) byte of address (bits, The I2C Slave mode hardware will always generate an SSPxIF, BF and UA, are set on address match). interrupt on an address match. Address masking will 2. Update the SSPxADD register with second (low) allow the hardware to generate an interrupt for more byte of address (clears bit, UA, and releases the than one address (up to 31 in 7-bit addressing and up SCLx line). to 63 in 10-bit addressing). Through the mode select 3. Read the SSPxBUF register (clears bit, BF) and bits, the user can also choose to interrupt on Start and clear flag bit, SSPxIF. Stop bits. 4. Receive second (low) byte of address (bits, When an address is matched, or the data transfer after SSPxIF, BF and UA, are set). an address match is received, the hardware auto- 5. Update the SSPxADD register with the first matically will generate the Acknowledge (ACK) pulse (high) byte of address. If match releases the and load the SSPxBUF register with the received value SCLx line, this will clear bit, UA. currently in the SSPxSR register. 6. Read the SSPxBUF register (clears bit, BF) and Any combination of the following conditions will cause clear flag bit, SSPxIF. the MSSP module not to give this ACK pulse: 7. Receive Repeated Start condition. • The Buffer Full bit, BF (SSPxSTAT<0>), was set 8. Receive first (high) byte of address (bits, before the transfer was received. SSPxIF and BF, are set). • The overflow bit, SSPOV (SSPxCON1<6>), was 9. Read the SSPxBUF register (clears bit, BF) and set before the transfer was received. clear flag bit, SSPxIF. In this case, the SSPxSR register value is not loaded into the SSPxBUF, but bit, SSPxIF, is set. The BF bit is cleared by reading the SSPxBUF register, while bit, SSPOV, is cleared through software. The SCLx clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. © 2009 Microchip Technology Inc. DS39663F-page 209
PIC18F87J10 FAMILY 19.4.3.2 Address Masking • 10-Bit Addressing mode Masking an address bit causes that bit to become a Address Mask bits, ADMSK<5:2>, mask the “don’t care”. When one address bit is masked, two corresponding address bits in the SSPxADD addresses will be Acknowledged and cause an register. In addition, ADMSK<1> simultaneously interrupt. It is possible to mask more than one address masks the two LSBs of the address, ADD<1:0>. bit at a time, which makes it possible to Acknowledge For any ADMSK bits that are active up to 31 addresses in 7-bit mode and up to (ADMSK<x>=1), the corresponding address bit is 63addresses in 10-bit mode (see Example19-2). ignored (ADD<x> = x). Also note, that although in The I2C slave behaves the same way whether address 10-Bit Addressing mode, the upper address bits reuse part of the SSPxADD register bits; the masking is used or not. However, when address masking is used, the I2C slave can Acknowledge address mask bits do not interact with those bits. They only affect the lower address bits. multiple addresses and cause interrupts. When this occurs, it is necessary to determine which address Note1: ADMSK<1> masks the two Least caused the interrupt by checking SSPxBUF. Significant bits of the address. • 7-Bit Addressing mode 2: The two Most Significant bits of the Address Mask bits, ADMSK<5:1>, mask the address are not affected by address corresponding address bits in the SSPxADD masking. register. For any ADMSK bits that are active (ADMSK<x>=1), the corresponding address bit is ignored (ADD<x>=x). For the module to issue an address Acknowledge, it is sufficient to match only on addresses that do not have an active address mask. EXAMPLE 19-2: ADDRESS MASKING 7-Bit Addressing: SSPxADD<7:1> = 1010 0000 ADMSK<5:1> = 00 111 Addresses Acknowledged = 0xA0, 0xA2, 0xA4, 0xA6 0xA8, 0xAA, 0xAC, 0xAE 10-Bit Addressing: SSPxADD<7:0> = 1010 0000 (The two MSbs are ignored in this example since they are not affected.) ADMSK<5:1> = 00 111 Addresses Acknowledged = 0xA0, 0xA1, 0xA2, 0xA3 0xA4, 0xA5, 0xA6, 0xA7 0xA8, 0xA9, 0xAA 0xAB 0xAC, 0xAD, 0xAE, 0xAF The upper two bits are not affected by the address masking. DS39663F-page 210 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.3.3 Reception 19.4.3.4 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPxSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPxSTAT register is set. The received address is the SSPxBUF register and the SDAx line is held low loaded into the SSPxBUF register. The ACK pulse will (ACK). be sent on the ninth bit and the SCLx pin is held low regardless of SEN (see Section19.4.4 “Clock When the address byte overflow condition exists, then Stretching” for more detail). By stretching the clock, the no Acknowledge (ACK) pulse is given. An overflow the master will be unable to assert another clock pulse condition is defined as either bit, BF (SSPxSTAT<0>), until the slave is done preparing the transmit data. The is set, or bit, SSPOV (SSPxCON1<6>), is set. transmit data must be loaded into the SSPxBUF regis- An MSSP interrupt is generated for each data transfer ter which also loads the SSPxSR register. Then pin, byte. The interrupt flag bit, SSPxIF, must be cleared in SCLx, should be enabled by setting bit, CKP software. The SSPxSTAT register is used to determine (SSPxCON1<4>). The eight data bits are shifted out on the status of the byte. the falling edge of the SCLx input. This ensures that the If SEN is enabled (SSPxCON2<0> = 1), SCLx will be SDAx signal is valid during the SCLx high time held low (clock stretch) following each data transfer. The (Figure19-10). clock must be released by setting bit, CKP The ACK pulse from the master-receiver is latched on (SSPxCON1<4>). See Section19.4.4 “Clock the rising edge of the ninth SCLx input pulse. If the Stretching” for more detail. SDAx line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset and the slave monitors for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, pin, SCLx, must be enabled by setting bit, CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. © 2009 Microchip Technology Inc. DS39663F-page 211
PIC18F87J10 FAMILY 2 FIGURE 19-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESSING) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e eceiving D4 4 n softwarF is read R D6D5 23 Cleared iSSPxBU 7 D 1 = 0 ACK 9 W 8 R/ A1 7 2 )0 A 6 = ddress A3 5 n SEN A e Receiving A5A4 34 set to ‘’ wh0 e SDAxA7A6 SCLx12S SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP(CKP does not r DS39663F-page 212 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 2 FIGURE 19-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESSING) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 pt. u D1 7 nterr n i D2 6 e a s u Data D3 5 e d ca Receiving D5D4 34 ared in softwarPxBUF is read owledged an D6 2 CleSS Ackn e D7 1 ’).0 X will b K 9 a ‘ X. R/W = 0 AC 8 a ‘’ or 1 5.X.A3. Receiving Address SDAxA7A6A5XA3XX SCLx1234567S SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP(CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can be either x 2:In this example, an address equal to A7.A6.A © 2009 Microchip Technology Inc. DS39663F-page 213
PIC18F87J10 FAMILY 2 FIGURE 19-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING) P R S K F I AC 9 PxI S D0 8 m S o Data D1 7 Fr Transmitting D5D4D3D2 3456 eared in software UF is written in software et in software D6 2 Cl SSPxB KP is s C D7 1 R S ACK 9 PxIF I S S D0 8 m o Fr D1 7 Transmitting Data D6D7D5D4D3D2 234561 SCLx held lowwhile CPUresponds to SSPxIF Cleared in software SSPxBUF is written in software Clear by reading CKP is set in software K C A 9 0 = W 8 R/ 1 A 7 ess A2 6 Addr A3 5 g n eivi A4 4 ec R A5 3 >) 7 A6A7 12 Data in sampled > or PIR3< 0>) <4>) 3 < N DAx CLx S SPxIF (PIR1< F (SSPxSTAT KP (SSPxCO S S S B C DS39663F-page 214 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 19-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESSING) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 untilDD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPxADD is updated with highbyte of address nd cause an interrupt. Clock is held low Clock is held low untilupdate of SSPxAupdate of SSPxADD has taken placetaken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACKACKDAx11110A9A8A7A6A5XA3A2XXD7 CLx1234567891234567891S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPxADD needs to bewhen SSPxADD is updatedupdatedwith low byte of address UA is set indicating thatSSPxADD needs to beupdated KP(CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can be either a ‘’ or a ‘’).x10 2:In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged a 3:Note that the Most Significant bits of the address are not affected by the bit masking. S S S B S U C © 2009 Microchip Technology Inc. DS39663F-page 215
PIC18F87J10 FAMILY FIGURE 19-12: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 untilDD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPxADD is updated with highbyte of address d low SPxA D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACKDAx11110A9A8A7A6A5A4A3A2A1 CLx1234567891234567S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPxADD needs to bewhen SSPxADD is updatedupdatedwith low byte of address UA is set indicating thatSSPxADD needs to beupdated KP(CKP does not reset to ‘’ when SEN = )00 S S S B S U C DS39663F-page 216 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 2 FIGURE 19-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCLx low w Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressTransmitting Data ByteR/W = 1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPxBUFWrite of SSPxBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPxADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPxADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with lowbyte of address UA is set indicating thatSSPxADD needs to beupdated R/ 8 h be Receive First Byte of Address DAx11110A9A8 CLx1234567S SPxIF (PIR1<3> or PIR3<7>) F (SSPxSTAT<0>) SSPxBUF is written witcontents of SSPxSR A (SSPxSTAT<1>) UA is set indicating thatthe SSPxADD needs to updated KP (SSPxCON1<4>) S S S B U C © 2009 Microchip Technology Inc. DS39663F-page 217
PIC18F87J10 FAMILY 19.4.4 CLOCK STRETCHING 19.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The 7-Bit Slave Transmit mode implements clock The SEN bit (SSPxCON2<0>) allows clock stretching stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data regardless of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCLx line 19.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPxBUF before the master device In 7-Bit Slave Receive mode, on the falling edge of the can initiate another transmit sequence (see ninth clock at the end of the ACK sequence, if the BF Figure19-10). bit is set, the CKP bit in the SSPxCON1 register is Note1: If the user loads the contents of automatically cleared, forcing the SCLx output to be SSPxBUF, setting the BF bit before the held low. The CKP being cleared to ‘0’ will assert the falling edge of the ninth clock, the CKP bit SCLx line low. The CKP bit must be set in the user’s will not be cleared and clock stretching ISR before reception is allowed to continue. By holding will not occur. the SCLx line low, the user has time to service the ISR 2: The CKP bit can be set in software and read the contents of the SSPxBUF before the regardless of the state of the BF bit. master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure19-15). 19.4.4.4 Clock Stretching for 10-Bit Slave Transmit Mode Note1: If the user reads the contents of the SSPxBUF before the falling edge of the In 10-Bit Slave Transmit mode, clock stretching is ninth clock, the BF bit will be cleared. The controlled during the first two address sequences by CKP bit will not be cleared and clock the state of the UA bit, just as it is in 10-Bit Slave stretching will not occur. Receive mode. The first two addresses are followed by a third address sequence which contains the 2: The CKP bit can be set in software high-order bits of the 10-bit address and the R/W bit regardless of the state of the BF bit. The set to ‘1’. After the third address sequence is user should be careful to clear the BF bit performed, the UA bit is not set, the module is now in the ISR before the next receive configured in Transmit mode and clock stretching is sequence in order to prevent an overflow controlled by the BF flag as in 7-Bit Slave Transmit condition. mode (see Figure19-13). 19.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPxADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPxADD register before the falling edge of the ninth clock occurs, and if the user hasn’t cleared the BF bit by reading the SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39663F-page 218 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.4.5 Clock Synchronization and already asserted the SCLx line. The SCLx output will the CKP Bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx. This When the CKP bit is cleared, the SCLx output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, clearing the CKP bit will not assert the minimum high time requirement for SCLx (see SCLx output low until the SCLx output is already Figure19-14). sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 19-14: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX DX – 1 SCLx Master device CKP asserts clock Master device deasserts clock WR SSPxCON1 © 2009 Microchip Technology Inc. DS39663F-page 219
PIC18F87J10 FAMILY 2 FIGURE 19-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESSING) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R D5 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPxBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 >) A6 2 R3<7 >) A7 1 > or PI 0>) ON1<6 DAx CLxS SPxIF (PIR1<3 F (SSPxSTAT< SPOV (SSPxC KP S S S B S C DS39663F-page 220 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 19-16: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESSING) Clock is not held lowbecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D 8 1 D 7 e Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared in softwareCleared in softwar Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPxADD register beforethe falling edge of the ninth clock will have noeffect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 DAx11110A9A8A7A6A5A4A3A2A1A0ACK CLx12345678912345678S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardware whenthe SSPxADD needs to beSSPxADD is updated with lowupdatedbyte of address after falling edgeof ninth clock UA is set indicating thatSSPxADD needs to beupdated KPNote:An update of the SSPxADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. S S S B S U C © 2009 Microchip Technology Inc. DS39663F-page 221
PIC18F87J10 FAMILY 19.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPxSR is SUPPORT transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK The addressing procedure for the I2C bus is such that bit), the SSPxIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the the master. The exception is the general call address interrupt can be checked by reading the contents of the which can address all devices. When this address is SSPxBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device specific or a general call address. Acknowledge. In 10-bit mode, the SSPxADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit is set (SSPxSTAT<1>). If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second The general call address is recognized when the half of the address is not necessary, the UA bit will not General Call Enable bit, GCEN, is enabled be set and the slave will begin receiving data after the (SSPxCON2<7> set). Following a Start bit detect, 8 bits Acknowledge (Figure19-17). are shifted into the SSPxSR and the address is compared against the SSPxADD. It is also compared to the general call address and fixed in hardware. FIGURE 19-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK General Call Address SDAx ACK D7 D6 D5 D4 D3 D2 D1 D0 SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPxIF BF (SSPxSTAT<0>) Cleared in software SSPxBUF is read SSPOV (SSPxCON1<6>) ‘0’ GCEN (SSPxCON2<7>) ‘1’ DS39663F-page 222 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPxCON1 and by setting of events. For instance, the user is not the SSPEN bit. In Master mode, the SCLx and SDAx allowed to initiate a Start condition and lines are manipulated by the MSSP hardware if the immediately write the SSPxBUF register to TRIS bits are set. initiate transmission before the Start condi- tion is complete. In this case, the Master mode of operation is supported by interrupt SSPxBUF will not be written to and the generation on the detection of the Start and Stop con- WCOL bit will be set, indicating that a write ditions. The Stop (P) and Start (S) bits are cleared from to the SSPxBUF did not occur. a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the The following events will cause the MSSP Interrupt bus is Idle, with both the S and P bits clear. Flag bit, SSPxIF, to be set (and MSSP interrupt, if In Firmware Controlled Master mode, user code enabled): conducts all I2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options. • Acknowledge transmit 1. Assert a Start condition on SDAx and SCLx. • Repeated Start 2. Assert a Repeated Start condition on SDAx and SCLx. 3. Write to the SSPxBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDAx and SCLx. 2 FIGURE 19-18: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM<3:0> Data Bus SSPxADD<6:0> Read Write SSPxBUF Baud Rate Generator SDAx Shift SDAx In Clock ct e SSPxSR Detce) MSb LSb L ur e Oo abl WCk s SCLx Receive En StAarcGtk bneiont,we Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCLx In Write Collision Detect Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1) Clock Arbitration Set SSPxIF, BCLxIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPxCON2) end of XMIT/RCV © 2009 Microchip Technology Inc. DS39663F-page 223
PIC18F87J10 FAMILY 19.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPxCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPxIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPxBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDAx, while SCLx outputs the serial clock. The 4. Address is shifted out the SDAx pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPxCON2 register (SSPxCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the end of a serial transfer. SSPxIF bit. In Master Receive mode, the first byte transmitted 7. The user loads the SSPxBUF with eight bits of contains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDAx pin until all 8 bits logic ‘1’. Thus, the first byte transmitted is a 7-bit slave are transmitted. address, followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDAx, while SCLx outputs slave device and writes its value into the the serial clock. Serial data is received 8 bits at a time. SSPxCON2 register (SSPxCON2<6>). After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the 10. The MSSP module generates an interrupt at the beginning and end of transmission. end of the ninth clock cycle by setting the SSPxIF bit. The Baud Rate Generator used for the SPI mode 11. The user generates a Stop condition by setting operation is used to set the SCLx clock frequency for either 100kHz, 400kHz or 1MHz I2C operation. See the Stop Enable bit, PEN (SSPxCON2<2>). Section19.4.7 “Baud Rate” for more detail. 12. Interrupt is generated once the Stop condition is complete. DS39663F-page 224 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.7 BAUD RATE 19.4.7.1 Baud Rate and Module In I2C Master mode, the Baud Rate Generator (BRG) Interdependence reload value is placed in the lower 7 bits of the Because MSSP1 and MSSP2 are independent, they SSPxADD register (Figure19-19). When a write can operate simultaneously in I2C Master mode at occurs to SSPxBUF, the Baud Rate Generator will different baud rates. This is done by using different automatically begin counting. The BRG counts down to BRG reload values for each module. 0 and stops until another reload has taken place. The Because this mode derives its basic clock source from BRG count is decremented twice per instruction cycle the system clock, any changes to the clock will affect (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the both modules in the same proportion. It may be BRG is reloaded automatically. possible to change one or both baud rates back to a Once the given operation is complete (i.e., transmis- previous value by changing the BRG reload value. sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCLx pin will remain in its last state. Table19-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. FIGURE 19-19: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPxADD<6:0> SSPM<3:0> Reload Reload SCLx Control CLKO BRG Down Counter FOSC/4 TABLE 19-3: I2C™ CLOCK RATE w/BRG FSCL FOSC FCY FCY * 2 BRG Value (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 18h 400 kHz 40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 20 MHz 63h 100 kHz 16 MHz 4 MHz 8 MHz 09h 400 kHz 16 MHz 4 MHz 8 MHz 0Ch 308 kHz 16 MHz 4 MHz 8 MHz 27h 100 kHz 4 MHz 1 MHz 2 MHz 02h 333 kHz 4 MHz 1 MHz 2 MHz 09h 100 kHz 4 MHz 1 MHz 2 MHz 00h 1 MHz © 2009 Microchip Technology Inc. DS39663F-page 225
PIC18F87J10 FAMILY 19.4.7.2 Clock Arbitration SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCLx high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCLx pin (SCLx allowed to float high). event that the clock is held low by an external device When the SCLx pin is allowed to float high, the Baud (Figure19-20). Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 19-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX DX – 1 SCLx deasserted but slave holds SCLx allowed to transition high SCLx low (clock arbitration) SCLx BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCLx is sampled high, reload takes place and BRG starts its count BRG Reload DS39663F-page 226 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.8 I2C MASTER MODE START Note: If at the beginning of the Start condition, the CONDITION TIMING SDAx and SCLx pins are already sampled To initiate a Start condition, the user sets the Start low, or if during the Start condition, the Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx line is sampled low before the SDAx SCLx pins are sampled high, the Baud Rate Generator line is driven low, a bus collision occurs, the is reloaded with the contents of SSPxADD<6:0> and Bus Collision Interrupt Flag, BCLxIF, is set, starts its count. If SCLx and SDAx are both sampled the Start condition is aborted and the I2C high when the Baud Rate Generator times out (TBRG), module is reset into its Idle state. the SDAx pin is driven low. The action of the SDAx 19.4.8.1 WCOL Status Flag being driven low while SCLx is high is the Start condi- tion and causes the S bit (SSPxSTAT<3>) to be set. If the user writes the SSPxBUF when a Start sequence Following this, the Baud Rate Generator is reloaded is in progress, the WCOL bit is set and the contents of with the contents of SSPxADD<6:0> and resumes its the buffer are unchanged (the write doesn’t occur). count. When the Baud Rate Generator times out Note: Because queueing of events is not (TBRG), the SEN bit (SSPxCON2<0>) will be auto- allowed, writing to the lower 5 bits of matically cleared by hardware; the Baud Rate Generator SSPxCON2 is disabled until the Start is suspended, leaving the SDAx line held low and the condition is complete. Start condition is complete. FIGURE 19-21: FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here SDAx = 1, At completion of Start bit, SCLx = 1 hardware clears SEN bit and sets SSPxIF bit TBRG TBRG Write to SSPxBUF occurs here 1st bit 2nd bit SDAx TBRG SCLx TBRG S © 2009 Microchip Technology Inc. DS39663F-page 227
PIC18F87J10 FAMILY 19.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPxCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDAx is sampled low when SCLx the SCLx pin is asserted low. When the SCLx pin is goes from low-to-high. sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<5:0> and begins counting. • SCLx goes low before SDAx is The SDAx pin is released (brought high) for one Baud asserted low. This may indicate that Rate Generator count (TBRG). When the Baud Rate another master is attempting to Generator times out, if SDAx is sampled high, the SCLx transmit a data ‘1’. pin will be deasserted (brought high). When SCLx is Immediately following the SSPxIF bit getting set, the sampled high, the Baud Rate Generator is reloaded user may write the SSPxBUF with the 7-bit address in with the contents of SSPxADD<6:0> and begins 7-bit mode or the default first address in 10-bit mode. counting. SDAx and SCLx must be sampled high for After the first eight bits are transmitted and an ACK is one TBRG. This action is then followed by assertion of received, the user may then transmit an additional eight the SDAx pin (SDAx = 0) for one TBRG while SCLx is bits of address (10-bit mode) or eight bits of data (7-bit high. Following this, the RSEN bit (SSPxCON2<1>) will mode). be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As 19.4.9.1 WCOL Status Flag soon as a Start condition is detected on the SDAx and If the user writes the SSPxBUF when a Repeated Start SCLx pins, the S bit (SSPxSTAT<3>) will be set. The sequence is in progress, the WCOL is set and the SSPxIF bit will not be set until the Baud Rate Generator contents of the buffer are unchanged (the write doesn’t has timed out. occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPxCON2 is disabled until the Repeated Start condition is complete. FIGURE 19-22: REPEATED START CONDITION WAVEFORM S bit set by hardware SDAx = 1, At completion of Start bit, Write to SSPxCON2 occurs here:SDAx = 1, SCLx = 1 hardware clears RSEN bit SCLx (no change). and sets SSPxIF TBRG TBRG TBRG SDAx 1st bit RSEN bit set by hardware on falling edge of ninth clock, Write to SSPxBUF occurs here end of Xmit TBRG SCLx TBRG Sr = Repeated Start DS39663F-page 228 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.10 I2C MASTER MODE TRANSMISSION The user should verify that the WCOL bit is clear after each write to SSPxBUF to ensure the transfer is correct. Transmission of a data byte, a 7-bit address, or the In all cases, WCOL must be cleared in software. other half of a 10-bit address, is accomplished by sim- ply writing a value to the SSPxBUF register. This action 19.4.10.3 ACKSTAT Status Flag will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next In Transmit mode, the ACKSTAT bit (SSPxCON2<6>) is cleared when the slave has sent an Acknowledge transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is (ACK=0) and is set when the slave does not Acknowl- asserted (see data hold time specification edge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), parameter106). SCLx is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid or when the slave has properly received its data. before SCLx is released high (see data setup time 19.4.11 I2C MASTER MODE RECEPTION specification parameter 107). When the SCLx pin is released high, it is held that way for TBRG. The data on Master mode reception is enabled by programming the the SDAx pin must remain stable for that duration and Receive Enable bit, RCEN (SSPxCON2<3>). some hold time after the next falling edge of SCLx. Note: The MSSP module must be in an inactive After the eighth bit is shifted out (the falling edge of the state before the RCEN bit is set or the eighth clock), the BF flag is cleared and the master RCEN bit will be disregarded. releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth The Baud Rate Generator begins counting and on each bit time if an address match occurred, or if data was rollover, the state of the SCLx pin changes received properly. The status of ACK is written into the (high-to-low/low-to-high) and data is shifted into the ACKDT bit on the falling edge of the ninth clock. If the SSPxSR. After the falling edge of the eighth clock, the master receives an Acknowledge, the Acknowledge receive enable flag is automatically cleared, the con- Status bit, ACKSTAT, is cleared; if not, the bit is set. tents of the SSPxSR are loaded into the SSPxBUF, the After the ninth clock, the SSPxIF bit is set and the BF flag bit is set, the SSPxIF flag bit is set and the Baud master clock (Baud Rate Generator) is suspended until Rate Generator is suspended from counting, holding the next data byte is loaded into the SSPxBUF, leaving SCLx low. The MSSP is now in Idle state awaiting the SCLx low and SDAx unchanged (Figure19-23). next command. When the buffer is read by the CPU, After the write to the SSPxBUF, each bit of the address the BF flag bit is automatically cleared. The user can will be shifted out on the falling edge of SCLx until all then send an Acknowledge bit at the end of reception seven address bits and the R/W bit are completed. On by setting the Acknowledge Sequence Enable bit, the falling edge of the eighth clock, the master will ACKEN (SSPxCON2<4>). deassert the SDAx pin, allowing the slave to respond 19.4.11.1 BF Status Flag with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the In receive operation, the BF bit is set when an address address was recognized by a slave. The status of the or data byte is loaded into SSPxBUF from SSPxSR. It ACK bit is loaded into the ACKSTAT status bit is cleared when the SSPxBUF register is read. (SSPxCON2<6>). Following the falling edge of the 19.4.11.2 SSPOV Status Flag ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator In receive operation, the SSPOV bit is set when 8 bits is turned off until another write to the SSPxBUF takes are received into the SSPxSR and the BF flag bit is place, holding SCLx low and allowing SDAx to float. already set from a previous reception. 19.4.10.1 BF Status Flag 19.4.11.3 WCOL Status Flag In Transmit mode, the BF bit (SSPxSTAT<0>) is set If the user writes the SSPxBUF when a receive is when the CPU writes to SSPxBUF and is cleared when already in progress (i.e., SSPxSR is still shifting in a all 8 bits are shifted out. data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). 19.4.10.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur) 2TCY after the SSPxBUF write. If SSPxBUF is rewritten within 2 TCY, the WCOL bit is set and SSPxBUF is updated. This may result in a corrupted transfer. © 2009 Microchip Technology Inc. DS39663F-page 229
PIC18F87J10 FAMILY FIGURE 19-23: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESSING) 1 AT in ON2 = oftware STxC P n s ACKSSP ared i K e >) AC 9 Cl 6 N2< D0 8 e slave, clear ACKSTAT bit (SSPxCO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared in software service routinfrom MSSP interrupt SSPxBUF is written in software om D7 1 xIF Fr ow SP = 0 SCLx held lwhile CPUsponds to S CK re = 0 A W, 9 are R/W A1 ess and R/ 78 d by hardw ave A2 addr 6 eare PxCON2<0> (SEN = ),1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPxBUF written with 7-bit start transmit 12345 Cleared in software SSPxBUF written After Start condition, SEN cl Sn Write SStart co S T<0>) A T S x F SP SDAx SCLx SSPxI BF (S SEN PEN R/W DS39663F-page 230 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 19-24: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESSING) Write to SSPCON2<4>to start Acknowledge sequence,SDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequence,ACK from Master,ster configured as a receiverSDA = ACKDT = SDA = ACKDT = 10programming SSPCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7ACK Bus masterACK is not sentterminatestransfer 987651234567891234PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of AcknowledgeSet SSPIF interruptSet SSPIF interruptsequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Maby ACK from Slave R/W = 1A1ACK 789 Write to SSPCON2<0> (SEN = ),1begin Start condition SEN = 0Write to SSPBUF occurs here,start XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 123456SCLS SSPIF Cleared in softwareSDA = , SCL = 01while CPU responds to SSPIF BF SSPOV ACKEN © 2009 Microchip Technology Inc. DS39663F-page 231
PIC18F87J10 FAMILY 19.4.12 ACKNOWLEDGE SEQUENCE 19.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDAx pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPxCON2<2>). At the end of a (SSPxCON2<4>). When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDAx pin. If the user wishes to the master will assert the SDAx line low. When the generate an Acknowledge, then the ACKDT bit should SDAx line is sampled low, the Baud Rate Generator is be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate before starting an Acknowledge sequence. The Baud Generator times out, the SCLx pin will be brought high Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count) (TBRG) and the SCLx pin is deasserted (pulled high). later, the SDAx pin will be deasserted. When the SDAx When the SCLx pin is sampled high (clock arbitration), pin is sampled high while SCLx is high, the P bit the Baud Rate Generator counts for TBRG. The SCLx pin (SSPxSTAT<4>) is set. A TBRG later, the PEN bit is is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure19-26). matically cleared, the Baud Rate Generator is turned off 19.4.13.1 WCOL Status Flag and the MSSP module then goes into an inactive state (Figure19-25). If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the 19.4.12.1 WCOL Status Flag contents of the buffer are unchanged (the write doesn’t If the user writes the SSPxBUF when an Acknowledge occur). sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 19-25: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPxCON2, ACKEN = 1, ACKDT = 0 TBRG TBRG SDAx D0 ACK SCLx 8 9 SSPxIF Cleared in SSPxIF set at Cleared in software the end of receive software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 19-26: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPxCON2, SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG set PEN after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Falling edge of PEN bit (SSPxCON2<2>) is cleared by 9th clock hardware and the SSPxIF bit is set TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS39663F-page 232 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.14 SLEEP OPERATION 19.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master 19.4.15 EFFECTS OF A RESET outputs a ‘1’ on SDAx, by letting SDAx float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCLx pin floats current transfer. high, data should be stable. If the expected data on SDAx is a ‘1’ and the data sampled on the SDAx 19.4.16 MULTI-MASTER MODE pin=0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF, In Multi-Master mode, the interrupt generation on the and reset the I2C port to its Idle state (Figure19-27). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDAx and SCLx lines are deasserted and be taken when the P bit (SSPxSTAT<4>) is set, or the the SSPxBUF can be written to. When the user services bus is Idle, with both the S and P bits clear. When the the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the MSSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDAx line must be If a Start, Repeated Start, Stop or Acknowledge condition monitored for arbitration to see if the signal level is the was in progress when the bus collision occurred, the con- expected output level. This check is performed in dition is aborted, the SDAx and SCLx lines are hardware with the result placed in the BCLxIF bit. deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services The states where arbitration can be lost are: the bus collision Interrupt Service Routine and if the I2C • Address Transfer bus is free, the user can resume communication by • Data Transfer asserting a Start condition. • A Start Condition The master will continue to monitor the SDAx and SCLx • A Repeated Start Condition pins. If a Stop condition occurs, the SSPxIF bit will be set. • An Acknowledge Condition A write to the SSPxBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 19-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDAx. While SCLx is high, Data changes SDAx line pulled low data doesn’t match what is driven while SCLx = 0 by another source by the master. Bus collision has occurred. SDAx released by master SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF © 2009 Microchip Technology Inc. DS39663F-page 233
PIC18F87J10 FAMILY 19.4.17.1 Bus Collision During a Start If the SDAx pin is sampled low during this count, the Condition BRG is reset and the SDAx line is asserted early (Figure19-30). If, however, a ‘1’ is sampled on the During a Start condition, a bus collision occurs if: SDAx pin, the SDAx pin is asserted low at the end of a) SDAx or SCLx are sampled low at the beginning the BRG count. The Baud Rate Generator is then of the Start condition (Figure19-28). reloaded and counts down to 0. If the SCLx pin is b) SCLx is sampled low before SDAx is asserted sampled as ‘0’ during this time, a bus collision does not low (Figure19-29). occur. At the end of the BRG count, the SCLx pin is asserted low. During a Start condition, both the SDAx and the SCLx pins are monitored. Note: The reason that bus collision is not a factor during a Start condition is that no two bus If the SDAx pin is already low, or the SCLx pin is masters can assert a Start condition at the already low, then all of the following occur: exact same time. Therefore, one master • the Start condition is aborted, will always assert SDAx before the other. • the BCLxIF flag is set and This condition does not cause a bus colli- • the MSSP module is reset to its inactive state sion because the two masters must be (Figure19-28). allowed to arbitrate the first address The Start condition begins with the SDAx and SCLx following the Start condition. If the address pins deasserted. When the SDAx pin is sampled high, is the same, arbitration must be allowed to the Baud Rate Generator is loaded from continue into the data portion, Repeated SSPxADD<6:0> and counts down to 0. If the SCLx pin Start or Stop conditions. is sampled low while SDAx is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 19-28: BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDAx = 1, SCLx = 1 MSSP module reset into Idle state. SEN SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because BCLxIF SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared in software S SSPxIF SSPxIF and BCLxIF are cleared in software DS39663F-page 234 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 19-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start SCLx sequence if SDAx = 1, SCLx = 1 SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared in software S ‘0’ ‘0’ SSPxIF ‘0’ ‘0’ FIGURE 19-30: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Set SSPxIF Less than TBRG TBRG SDAx SDAx pulled low by other master. Reset BRG and assert SDAx. SCLx S SCLx pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 BCLxIF ‘0’ S SSPxIF SDAx = 0, SCLx = 1, Interrupts cleared set SSPxIF in software © 2009 Microchip Technology Inc. DS39663F-page 235
PIC18F87J10 FAMILY 19.4.17.2 Bus Collision During a Repeated If SDAx is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure19-31). If SDAx is sampled high, the BRG is reloaded and During a Repeated Start condition, a bus collision begins counting. If SDAx goes from high-to-low before occurs if: the BRG times out, no bus collision occurs because no a) A low level is sampled on SDAx when SCLx two masters can assert SDAx at exactly the same time. goes from low level to high level. If SCLx goes from high-to-low before the BRG times b) SCLx goes low before SDAx is asserted low, out and SDAx has not already been asserted, a bus indicating that another master is attempting to collision occurs. In this case, another master is transmit a data ‘1’. attempting to transmit a data ‘1’ during the Repeated When the user deasserts SDAx and the pin is allowed Start condition (see Figure19-32). to float high, the BRG is loaded with SSPxADD<6:0> If, at the end of the BRG time-out, both SCLx and SDAx and counts down to 0. The SCLx pin is then deasserted are still high, the SDAx pin is driven low and the BRG is and when sampled high, the SDAx pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. FIGURE 19-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared in software S ‘0’ SSPxIF ‘0’ FIGURE 19-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx SCLx goes low before SDAx, BCLxIF set BCLxIF. Release SDAx and SCLx. Interrupt cleared in software RSEN S ‘0’ SSPxIF DS39663F-page 236 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.17.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low. Condition When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with a) After the SDAx pin has been deasserted and SSPxADD<6:0> and counts down to 0. After the BRG allowed to float high, SDAx is sampled low after times out, SDAx is sampled. If SDAx is sampled low, a the BRG has timed out. bus collision has occurred. This is due to another b) After the SCLx pin is deasserted, SCLx is master attempting to drive a data ‘0’ (Figure19-33). If sampled low before SDAx goes high. the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure19-34). FIGURE 19-33: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDAx sampled low after TBRG, set BCLxIF SDAx SDAx asserted low SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ FIGURE 19-34: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes low before SDAx goes high, Assert SDAx set BCLxIF SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ © 2009 Microchip Technology Inc. DS39663F-page 237
PIC18F87J10 FAMILY TABLE 19-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR2 OSCFIF CMIF — — BCL1IF — TMR3IF CCP2IF 55 PIE2 OSCFIE CMIE — — BCL1IE — TMR3IE CCP2IE 55 IPR2 OSCFIP CMIP — — BCL1IP — TMR3IP CCP2IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 56 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56 SSP1BUF MSSP1 Receive Buffer/Transmit Register 54 SSP1ADD MSSP1 Address Register (I2C™ Slave mode), 57 MSSP1 Baud Rate Reload Register (I2C Master mode) SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 54, 57 SSPxCON2 GCEN ACKSTAT ACKDT/ ACKEN/ RCEN/ PEN/ RSEN/ SEN 54, 57 ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SSPxSTAT SMP CKE D/A P S R/W UA BF 54, 57 SSP2BUF MSSP2 Receive Buffer/Transmit Register 54 SSP2ADD MSSP2 Address Register (I2C Slave mode), 57 MSSP2 Baud Rate Reload Register (I2C Master mode) Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode. DS39663F-page 238 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 20.0 ENHANCED UNIVERSAL The pins of EUSART1 and EUSART2 are multiplexed SYNCHRONOUS with the functions of PORTC (RC6/TX1/CK1 and RC7/RX1/DT1) and PORTG (RG1/TX2/CK2 and ASYNCHRONOUS RECEIVER RG2/RX2/DT2), respectively. In order to configure TRANSMITTER (EUSART) these pins as an EUSART: The Enhanced Universal Synchronous Asynchronous • For EUSART1: Receiver Transmitter (EUSART) module is one of two - bit, SPEN (RCSTA1<7>), must be set (= 1) serial I/O modules. (Generically, the EUSART is also - bit, TRISC<7>, must be set (= 1) known as a Serial Communications Interface or SCI.) - bit, TRISC<6>, must be cleared (= 0) for The EUSART can be configured as a full-duplex Asynchronous and Synchronous Master asynchronous system that can communicate with modes peripheral devices, such as CRT terminals and - bit, TRISC<6>, must be set (= 1) for personal computers. It can also be configured as a Synchronous Slave mode half-duplex synchronous system that can communicate • For EUSART2: with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. - bit, SPEN (RCSTA2<7>), must be set (= 1) - bit, TRISG<2>, must be set (= 1) The Enhanced USART module implements additional features, including automatic baud rate detection and - bit, TRISG<1>, must be cleared (= 0) for calibration, automatic wake-up on Sync Break recep- Asynchronous and Synchronous Master tion and 12-bit Break character transmit. These make it modes ideally suited for use in Local Interconnect Network bus - bit, TRISC<6> must be set (= 1) for (LIN bus) systems. Synchronous Slave mode All members of the PIC18F87J10 family are equipped Note: The EUSART control will automatically with two independent EUSART modules, referred to as reconfigure the pin from input to output as EUSART1 and EUSART2. They can be configured in needed. the following modes: The operation of each Enhanced USART module is • Asynchronous (full duplex) with: controlled through three registers: - Auto-Wake-up on character reception • Transmit Status and Control (TXSTAx) - Auto-Baud calibration • Receive Status and Control (RCSTAx) - 12-bit Break character transmission • Baud Rate Control (BAUDCONx) • Synchronous – Master (half duplex) with These are detailed on the following pages in selectable clock polarity Register20-1, Register20-2 and Register20-3, • Synchronous – Slave (half duplex) with selectable respectively. clock polarity Note: Throughout this section, references to register and bit names that may be associ- ated with a specific EUSART module are referred to generically by the use of ‘x’ in place of the specific module number. Thus, “RCSTAx” might refer to the Receive Status register for either EUSART1 or EUSART2. © 2009 Microchip Technology Inc. DS39663F-page 239
PIC18F87J10 FAMILY REGISTER 20-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39663F-page 240 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 20-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading the RCREGx register and receiving the next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2009 Microchip Technology Inc. DS39663F-page 241
PIC18F87J10 FAMILY REGISTER 20-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous modes: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator – SPBRGx only (Compatible mode), SPBRGHx value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RXx pin – interrupt generated on falling edge; bit cleared in hardware on the following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39663F-page 242 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 20.1 Baud Rate Generator (BRG) the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate The BRG is a dedicated 8-bit or 16-bit generator that for a fast oscillator frequency. supports both the Asynchronous and Synchronous Writing a new value to the SPBRGHx:SPBRGx regis- modes of the EUSART. By default, the BRG operates ters causes the BRG timer to be reset (or cleared). This in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) ensures the BRG does not wait for a timer overflow selects 16-bit mode. before outputting the new baud rate. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits 20.1.1 OPERATION IN POWER-MANAGED BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also MODES control the baud rate. In Synchronous mode, BRGH is The device clock is used to generate the desired baud ignored. Table20-1 shows the formula for computation of rate. When one of the power-managed modes is the baud rate for different EUSART modes which only entered, the new clock source may be operating at a apply in Master mode (internally generated clock). different frequency. This may require an adjustment to Given the desired baud rate and FOSC, the nearest the value in the SPBRGx register pair. integer value for the SPBRGHx:SPBRGx registers can be calculated using the formulas in Table20-1. From this, 20.1.2 SAMPLING the error in baud rate can be determined. An example The data on the RXx pin (either RC7/RX1/DT1 or calculation is shown in Example20-1. Typical baud rates RG2/RX2/DT2) is sampled three times by a majority and error values for the various Asynchronous modes detect circuit to determine if a high or a low level is are shown in Table20-2. It may be advantageous to use present at the RXx pin. TABLE 20-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-Bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-Bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-Bit/Asynchronous 0 1 1 16-Bit/Asynchronous 1 0 x 8-Bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-Bit/Synchronous Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair © 2009 Microchip Technology Inc. DS39663F-page 243
PIC18F87J10 FAMILY EXAMPLE 20-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 20-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 56 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 56 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39663F-page 244 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate Value Rate Value Rate Value Rate Value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate Value Rate Value Rate Value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate Value Rate Value Rate Value Rate Value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Value Rate Value Rate Value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — © 2009 Microchip Technology Inc. DS39663F-page 245
PIC18F87J10 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Value Rate Value Rate Value Rate Value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate Value Rate Value Rate Value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Value Rate Value Rate Value Rate Value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate Value Rate Value Rate Value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — DS39663F-page 246 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 20.1.3 AUTO-BAUD RATE DETECT Note1: If the WUE bit is set with the ABDEN bit, The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on detection and calibration of baud rate. This feature is the byte following the Break character. active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the bit is clear. incoming character baud rate is within the The automatic baud rate measurement sequence range of the selected BRG clock source. (Figure20-1) begins whenever a Start bit is received Some combinations of oscillator frequency and the ABDEN bit is set. The calculation is and EUSART baud rates are not possible self-averaging. due to bit error rates. Overall system tim- ing and communication baud rates must In the Auto-Baud Rate Detect (ABD) mode, the clock to be taken into consideration when using the the BRG is reversed. Rather than the BRG clocking the Auto-Baud Rate Detection feature. incoming RXx signal, the RXx signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is 3: To maximize baud rate range, it is recom- used as a counter to time the bit period of the incoming mended to set the BRG16 bit if the serial byte stream. auto-baud feature is used. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate TABLE 20-4: BRG COUNTER Detect must receive a byte with the value 55h (ASCII CLOCK RATES “U”, which is also the LIN bus Sync character) in order to BRG16 BRGH BRG Counter Clock calculate the proper bit rate. The measurement is taken over both a low and a high bit time in order to minimize 0 0 FOSC/512 any effects caused by asymmetry of the incoming signal. 0 1 FOSC/128 After a Start bit, the SPBRGx begins counting up, using 1 0 FOSC/128 the preselected clock source on the first rising edge of RXx. After eight bits on the RXx pin or the fifth rising 1 1 FOSC/32 edge, an accumulated value totalling the proper BRG period is left in the SPBRGHx:SPBRGx register pair. 20.1.3.1 ABD and EUSART Transmission Once the 5th edge is seen (this should correspond to the Since the BRG clock is reversed during ABD acquisi- Stop bit), the ABDEN bit is automatically cleared. tion, the EUSART transmitter cannot be used during If a rollover of the BRG occurs (an overflow from FFFFh ABD. This means that whenever the ABDEN bit is set, to 0000h), the event is trapped by the ABDOVF status TXREGx cannot be written to. Users should also bit (BAUDCONx<7>). It is set in hardware by BRG roll- ensure that ABDEN does not become set during a overs and can be set or cleared by the user in software. transmit sequence. Failing to do this may result in ABD mode remains active after rollover events and the unpredictable EUSART operation. ABDEN bit remains set (Figure20-2). While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock can be configured by the BRG16 and BRGH bits. The BRG16 bit must be set to use both SPBRG1 and SPBRGH1 as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table20-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCxIF interrupt is set once the fifth rising edge on RXx is detected. The value in the RCREGx needs to be read to clear the RCxIF interrupt. The contents of RCREGx should be discarded. © 2009 Microchip Technology Inc. DS39663F-page 247
PIC18F87J10 FAMILY FIGURE 20-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RXx pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE=0. FIGURE 20-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RXx pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h DS39663F-page 248 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 20.2 EUSART Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is The Asynchronous mode of operation is selected by empty and the TXxIF flag bit is set. This interrupt can be clearing the SYNC bit (TXSTAx<4>). In this mode, the enabled or disabled by setting or clearing the interrupt EUSART uses standard Non-Return-to-Zero (NRZ) enable bit, TXxIE. TXxIF will be set regardless of the format (one Start bit, eight or nine data bits and one Stop state of TXxIE; it cannot be cleared in software. TXxIF is bit). The most common data format is 8 bits. An on-chip also not cleared immediately upon loading TXREGx, but dedicated 8-bit/16-bit Baud Rate Generator can be used becomes valid in the second instruction cycle following to derive standard baud rate frequencies from the the load instruction. Polling TX1IF immediately following oscillator. a load of TXREGx will return invalid results. The EUSART transmits and receives the LSb first. The While TXxIF indicates the status of the TXREGx regis- EUSART’s transmitter and receiver are functionally independent but use the same data format and baud ter, another bit, TRMT (TXSTAx<1>), shows the status rate. The Baud Rate Generator produces a clock, either of the TSR register. TRMT is a read-only bit which is set x16 or x64 of the bit shift rate, depending on the BRGH when the TSR register is empty. No interrupt logic is and BRG16 bits (TXSTAx<2> and BAUDCONx<3>). tied to this bit so the user has to poll this bit in order to Parity is not supported by the hardware but can be determine if the TSR register is empty. implemented in software and stored as the 9th data bit. Note1: The TSR register is not mapped in data When operating in Asynchronous mode, the EUSART memory, so it is not available to the user. module consists of the following important elements: 2: Flag bit, TX1IF, is set when enable bit • Baud Rate Generator TXEN is set. • Sampling Circuit To set up an Asynchronous Transmission: • Asynchronous Transmitter 1. Initialize the SPBRGHx:SPBRGx registers for • Asynchronous Receiver the appropriate baud rate. Set or clear the • Auto-Wake-up on Sync Break Character BRGH and BRG16 bits, as required, to achieve • 12-Bit Break Character Transmit the desired baud rate. • Auto-Baud Rate Detection 2. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. 20.2.1 EUSART ASYNCHRONOUS 3. If interrupts are desired, set enable bit, TXxIE. TRANSMITTER 4. If 9-bit transmission is desired, set transmit bit, The EUSART transmitter block diagram is shown in TX9; can be used as address/data bit. Figure20-3. The heart of the transmitter is the Transmit 5. Enable the transmission by setting bit, TXEN, (Serial) Shift Register (TSR). The Shift register obtains which will also set bit, TXxIF. its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit TXREGx. The TXREGx register is loaded with data in should be loaded in bit, TX9D. software. The TSR register is not loaded until the Stop 7. Load data to the TXREGx register (starts bit has been transmitted from the previous load. As transmission). soon as the Stop bit is transmitted, the TSR is loaded 8. If using interrupts, ensure that the GIE and PEIE with new data from the TXREGx register (if available). bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR Register TXx Pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGHx SPBRGx TX9 Baud Rate Generator TX9D © 2009 Microchip Technology Inc. DS39663F-page 249
PIC18F87J10 FAMILY FIGURE 20-4: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 20-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXxIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 TXREGx EUSARTx Transmit Register 55 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 56 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 56 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 56 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. DS39663F-page 250 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 20.2.2 EUSART ASYNCHRONOUS 20.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure20-6. This mode would typically be used in RS-485 systems. The data is received on the RXx pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGHx:SPBRGx registers for whereas the main receive serial shifter operates at the the appropriate baud rate. Set or clear the bit rate or at FOSC. This mode would typically be used BRGH and BRG16 bits, as required, to achieve in RS-232 systems. the desired baud rate. To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing 1. Initialize the SPBRGHx:SPBRGx registers for the SYNC bit and setting the SPEN bit. the appropriate baud rate. Set or clear the 3. If interrupts are required, set the RCEN bit and BRGH and BRG16 bits, as required, to achieve select the desired priority level with the RCxIP bit. the desired baud rate. 4. Set the RX9 bit to enable 9-bit reception. 2. Enable the asynchronous serial port by clearing 5. Set the ADDEN bit to enable address detect. bit, SYNC, and setting bit, SPEN. 6. Enable reception by setting the CREN bit. 3. If interrupts are desired, set enable bit, RCxIE. 7. The RCxIF bit will be set when reception is 4. If 9-bit reception is desired, set bit, RX9. complete. The interrupt will be Acknowledged if 5. Enable the reception by setting bit, CREN. the RCxIE and GIE bits are set. 6. Flag bit, RCxIF, will be set when reception is 8. Read the RCSTAx register to determine if any complete and an interrupt will be generated if error occurred during reception, as well as read enable bit, RCxIE, was set. bit 9 of data (if applicable). 7. Read the RCSTAx register to get the 9th bit (if 9. Read RCREGx to determine if the device is enabled) and determine if any error occurred being addressed. during reception. 10. If any error occurred, clear the CREN bit. 8. Read the 8-bit received data by reading the 11. If the device has been addressed, clear the RCREGx register. ADDEN bit to allow all received data into the 9. If any error occurred, clear the error by clearing receive buffer and interrupt the CPU. enable bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-6: EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGHx SPBRGx ÷ o6r4 MSb RSR Register LSb ÷ 16 or Stop (8) 7 • • • 1 0 Start Baud Rate Generator ÷ 4 RX9 Pin Buffer Data and Control Recovery RXx RX9D RCREGx Register FIFO SPEN 8 Interrupt RCxIF Data Bus RCxIE © 2009 Microchip Technology Inc. DS39663F-page 251
PIC18F87J10 FAMILY FIGURE 20-7: ASYNCHRONOUS RECEPTION RXx (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREGx RCREGx Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set. TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 RCREGx EUSARTx Receive Register 55 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 56 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 56 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 56 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. 20.2.4 AUTO-WAKE-UP ON SYNC BREAK the RXx/DTx line. (This coincides with the start of a CHARACTER Sync Break or a Wake-up Signal character for the LIN protocol.) During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator Following a wake-up event, the module generates an is inactive and a proper byte reception cannot be per- RCxIF interrupt. The interrupt is generated synchro- formed. The auto-wake-up feature allows the controller nously to the Q clocks in normal operating modes to wake-up due to activity on the RXx/DTx line while the (Figure20-8) and asynchronously if the device is in EUSART is operating in Asynchronous mode. Sleep mode (Figure20-9). The interrupt condition is cleared by reading the RCREGx register. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>). Once set, the typical The WUE bit is automatically cleared once a receive sequence on RXx/DTx is disabled and the low-to-high transition is observed on the RXx line EUSART remains in an Idle state, monitoring for a following the wake-up event. At this point, the EUSART wake-up event independent of the CPU mode. A module is in Idle mode and returns to normal operation. wake-up event consists of a high-to-low transition on This signals to the user that the Sync Break event is over. DS39663F-page 252 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 20.2.4.1 Special Considerations Using 20.2.4.2 Special Considerations Using Auto-Wake-up the WUE Bit Since auto-wake-up functions by sensing rising edge The timing of WUE and RCxIF events may cause some transitions on RXx/DTx, information with any state confusion when it comes to determining the validity of changes before the Stop bit may signal a false received data. As noted, setting the WUE bit places the end-of-character and cause data or framing errors. To EUSART in an Idle mode. The wake-up event causes a work properly, therefore, the initial character in the receive interrupt by setting the RCxIF bit. The WUE bit transmission must be all ‘0’s. This can be 00h (8 bytes) is cleared after this when a rising edge is seen on for standard RS-232 devices or 000h (12 bits) for LIN RXx/DTx. The interrupt condition is then cleared by bus. reading the RCREGx register. Ordinarily, the data in RCREGx will be dummy data and should be discarded. Oscillator start-up time must also be considered, especially in applications using oscillators with longer The fact that the WUE bit has been cleared (or is still start-up intervals (i.e., HS or HSPLL mode). The Sync set) and the RCxIF flag is set should not be used as an Break (or Wake-up Signal) character must be of indicator of the integrity of the data in RCREGx. Users sufficient length and be followed by a sufficient interval should consider implementing a parallel method in to allow enough time for the selected oscillator to start firmware to verify received data integrity. and provide proper initialization of the EUSART. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. FIGURE 20-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RXx/DTx Line RCxIF Cleared due to user read of RCREGx Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 20-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RXx/DTx Line Note 1 RCxIF Cleared due to user read of RCREGx SLEEP Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. © 2009 Microchip Technology Inc. DS39663F-page 253
PIC18F87J10 FAMILY 20.2.5 BREAK CHARACTER SEQUENCE 1. Configure the EUSART for the desired mode. The EUSART module has the capability of sending the 2. Set the TXEN and SENDB bits to set up the special Break character sequences that are required by Break character. the LIN bus standard. The Break character transmit 3. Load the TXREGx with a dummy character to consists of a Start bit, followed by twelve ‘0’ bits and a initiate transmission (the value is ignored). Stop bit. The Frame Break character is sent whenever 4. Write ‘55h’ to TXREGx to load the Sync the SENDB and TXEN bits (TXSTAx<3> and character into the transmit FIFO buffer. TXSTAx<5>) are set while the Transmit Shift Register 5. After the Break has been sent, the SENDB bit is is loaded with data. Note that the value of data written reset by hardware. The Sync character now to TXREGx will be ignored and all ‘0’s will be transmits in the preconfigured mode. transmitted. When the TXREGx becomes empty, as indicated by The SENDB bit is automatically reset by hardware after the TXxIF, the next data byte can be written to the corresponding Stop bit is sent. This allows the user TXREGx. to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync 20.2.6 RECEIVING A BREAK CHARACTER character in the LIN specification). The Enhanced USART module can receive a Break Note that the data value written to the TXREGx for the character in two ways. Break character is ignored. The write simply serves the The first method forces configuration of the baud rate purpose of initiating the proper sequence. at a frequency of 9/13 the typical speed. This allows for The TRMT bit indicates when the transmit operation is the Stop bit transition to be at the correct sampling active or Idle, just as it does during normal transmis- location (13 bits for Break versus Start bit and 8 data sion. See Figure20-10 for the timing of the Break bits for typical data). character sequence. The second method uses the auto-wake-up feature 20.2.5.1 Break and Sync Transmit Sequence described in Section20.2.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the The following sequence will send a message frame EUSART will sample the next two transitions on header made up of a Break, followed by an Auto-Baud RXx/DTx, cause an RCxIF interrupt and receive the Sync byte. This sequence is typical of a LIN bus next data byte followed by another interrupt. master. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABDEN bit once the TXxIF interrupt is observed. FIGURE 20-10: SEND BREAK CHARACTER SEQUENCE Write to TXREGx Dummy Write BRG Output (Shift Clock) TXx (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB bit (Transmit Shift Reg. Empty Flag) DS39663F-page 254 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 20.3 EUSART Synchronous Once the TXREGx register transfers the data to the Master Mode TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be The Synchronous Master mode is entered by setting enabled or disabled by setting or clearing the interrupt the CSRC bit (TXSTAx<7>). In this mode, the data is enable bit, TXxIE. TXxIF is set regardless of the state transmitted in a half-duplex manner (i.e., transmission of enable bit, TXxIE; it cannot be cleared in software. It and reception do not occur at the same time). When will reset only when new data is loaded into the transmitting data, the reception is inhibited and vice TXREGx register. versa. Synchronous mode is entered by setting bit, While flag bit, TXxIF, indicates the status of the TXREGx SYNC (TXSTAx<4>). In addition, enable bit, SPEN register, another bit, TRMT (TXSTAx<1>), shows the (RCSTAx<7>), is set in order to configure the TXx and status of the TSR register. TRMT is a read-only bit which RXx pins to CKx (clock) and DTx (data) lines, is set when the TSR is empty. No interrupt logic is tied to respectively. this bit, so the user must poll this bit in order to determine The Master mode indicates that the processor trans- if the TSR register is empty. The TSR is not mapped in mits the master clock on the CKx line. Clock polarity is data memory so it is not available to the user. selected with the SCKP bit (BAUDCONx<4>); setting To set up a Synchronous Master Transmission: SCKP sets the Idle state on CKx as high, while clearing the bit sets the Idle state as low. This option is provided 1. Initialize the SPBRGHx:SPBRGx registers for the to support Microwire devices with this module. appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. 20.3.1 EUSART SYNCHRONOUS MASTER 2. Enable the synchronous master serial port by TRANSMISSION setting bits, SYNC, SPEN and CSRC. The EUSART transmitter block diagram is shown in 3. If interrupts are desired, set enable bit, TXxIE. Figure20-3. The heart of the transmitter is the Transmit 4. If 9-bit transmission is desired, set bit, TX9. (Serial) Shift Register (TSR). The Shift register obtains 5. Enable the transmission by setting bit, TXEN. its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit TXREGx. The TXREGx register is loaded with data in should be loaded in bit, TX9D. software. The TSR register is not loaded until the last 7. Start transmission by loading data to the bit has been transmitted from the previous load. As TXREGx register. soon as the last bit is transmitted, the TSR is loaded with new data from the TXREGx (if available). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX1/CK1 pin (SCKP = 0) RC6/TX1/CK1 pin (SCKP = 1) Write to TXREG1 Reg Write Word 1 Write Word 2 TX1IF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2). © 2009 Microchip Technology Inc. DS39663F-page 255
PIC18F87J10 FAMILY FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2). TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 TXREGx EUSARTx Transmit Register 55 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 56 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 56 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. DS39663F-page 256 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 20.3.2 EUSART SYNCHRONOUS 3. Ensure bits, CREN and SREN, are clear. MASTER RECEPTION 4. If interrupts are desired, set enable bit, RCxIE. 5. If 9-bit reception is desired, set bit, RX9. Once Synchronous mode is selected, reception is 6. If a single reception is required, set bit, SREN. enabled by setting either the Single Receive Enable bit, For continuous reception, set bit, CREN. SREN (RCSTAx<5>), or the Continuous Receive 7. Interrupt flag bit, RCxIF, will be set when recep- Enable bit, CREN (RCSTAx<4>). Data is sampled on tion is complete and an interrupt will be generated the RXx pin on the falling edge of the clock. if the enable bit, RCxIE, was set. If enable bit, SREN, is set, only a single word is 8. Read the RCSTAx register to get the 9th bit (if received. If enable bit, CREN, is set, the reception is enabled) and determine if any error occurred continuous until CREN is cleared. If both bits are set, during reception. then CREN takes precedence. 9. Read the 8-bit received data by reading the To set up a Synchronous Master Reception: RCREGx register. 1. Initialize the SPBRGHx:SPBRGx registers for the 10. If any error occurred, clear the error by clearing appropriate baud rate. Set or clear the BRG16 bit, CREN. bit, as required, to achieve the desired baud rate. 11. If using interrupts, ensure that the GIE and PEIE bits 2. Enable the synchronous master serial port by in the INTCON register (INTCON<7:6>) are set. setting bits, SYNC, SPEN and CSRC. FIGURE 20-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX1/CK1 pin (SCKP = 0) RC6/TX1/CK1 pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RC1IF bit (Interrupt) Read RCREG1 Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2). TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 RCREGx EUSARTx Receive Register 55 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 56 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 56 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. © 2009 Microchip Technology Inc. DS39663F-page 257
PIC18F87J10 FAMILY 20.4 EUSART Synchronous To set up a Synchronous Slave Transmission: Slave Mode 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, Synchronous Slave mode is entered by clearing bit, CSRC. CSRC (TXSTAx<7>). This mode differs from the 2. Clear bits, CREN and SREN. Synchronous Master mode in that the shift clock is sup- plied externally at the CKx pin (instead of being supplied 3. If interrupts are desired, set enable bit, TXxIE. internally in Master mode). This allows the device to 4. If 9-bit transmission is desired, set bit, TX9. transfer or receive data while in any low-power mode. 5. Enable the transmission by setting enable bit, TXEN. 20.4.1 EUSART SYNCHRONOUS 6. If 9-bit transmission is selected, the ninth bit SLAVE TRANSMISSION should be loaded in bit, TX9D. The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the modes is identical, except in the case of Sleep mode. TXREGx register. If two words are written to the TXREGx and then the 8. If using interrupts, ensure that the GIE and PEIE SLEEP instruction is executed, the following will occur: bits in the INTCON register (INTCON<7:6>) are set. a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in the TXREGx register. c) Flag bit, TXxIF, will not be set. d) When the first word has been shifted out of TSR, the TXREGx register will transfer the second word to the TSR and flag bit, TXxIF, will now be set. e) If enable bit, TXxIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 TXREGx EUSARTx Transmit Register 55 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 56 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 56 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. DS39663F-page 258 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 20.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical, except in the case of Sleep, or any CSRC. Idle mode and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCxIE. Slave mode. 3. If 9-bit reception is desired, set bit, RX9. If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN. entering Sleep or any Idle mode, then a word may be 5. Flag bit, RCxIF, will be set when reception is received while in this low-power mode. Once the word complete. An interrupt will be generated if is received, the RSR register will transfer the data to the enable bit, RCxIE, was set. RCREGx register; if the RCxIE enable bit is set, the 6. Read the RCSTAx register to get the 9th bit (if interrupt generated will wake the chip from the enabled) and determine if any error occurred Low-Power mode. If the global interrupt is enabled, the during reception. program will branch to the interrupt vector. 7. Read the 8-bit received data by reading the RCREGx register. 8. If any error occurred, clear the error by clearing bit, CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 RCREGx EUSARTx Receive Register 55 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 56 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 56 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. © 2009 Microchip Technology Inc. DS39663F-page 259
PIC18F87J10 FAMILY NOTES: DS39663F-page 260 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 21.0 10-BIT ANALOG-TO-DIGITAL The module has five registers: CONVERTER (A/D) MODULE • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) The Analog-to-Digital (A/D) Converter module has • A/D Control Register 0 (ADCON0) 11inputs for the 64-pin devices and 15 for the 80-pin devices. This module allows conversion of an analog • A/D Control Register 1 (ADCON1) input signal to a corresponding 10-bit digital number. • A/D Control Register 2 (ADCON2) The ADCON0 register, shown in Register21-1, controls the operation of the A/D module. The ADCON1 register, shown in Register21-2, configures the functions of the port pins. The ADCON2 register, shown in Register21-3, configures the A/D clock source, programmed acquisition time and justification. REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADCAL: A/D Calibration bit 1 = Calibration is performed on next A/D conversion 0 = Normal A/D Converter operation (no calibration is performed) bit 6 Unimplemented: Read as ‘0’ bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Unused 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12)(1,2) 1101 = Unimplemented(1,2) 1110 = Unimplemented(1,2) 1111 = Unimplemented(1,2) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Note 1: These channels are not implemented on 64-pin devices. 2: Performing a conversion on unimplemented channels will return random values. © 2009 Microchip Technology Inc. DS39663F-page 261
PIC18F87J10 FAMILY REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = AVSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = AVDD bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits: PCFG<3:0> (1)15 (1)14 (1)13 (1)12 N11 N10 N9 N8 N7 N6 N4 N3 N2 N1 N0 N N N N A A A A A A A A A A A A A A A 0000 A A A A A A A A A A A A A A A 0001 D D A A A A A A A A A A A A A 0010 D D D A A A A A A A A A A A A 0011 D D D D A A A A A A A A A A A 0100 D D D D D A A A A A A A A A A 0101 D D D D D D A A A A A A A A A 0110 D D D D D D D A A A A A A A A 0111 D D D D D D D D A A A A A A A 1000 D D D D D D D D D A A A A A A 1001 D D D D D D D D D D A A A A A 1010 D D D D D D D D D D A A A A A 1011 D D D D D D D D D D D A A A A 1100 D D D D D D D D D D D D A A A 1101 D D D D D D D D D D D D D A A 1110 D D D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D D D A = Analog input D = Digital I/O Note 1: AN12 through AN15 are available only in 80-pin devices. DS39663F-page 262 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 21-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. © 2009 Microchip Technology Inc. DS39663F-page 263
PIC18F87J10 FAMILY The analog reference voltage is software selectable to the A/D conversion. When the A/D conversion is com- either the device’s positive and negative supply voltage plete, the result is loaded into the ADRESH:ADRESL (AVDD and AVSS), or the voltage level on the register pair, the GO/DONE bit (ADCON0<1>) is RA3/AN3/VREF+ and RA2/AN2/VREF- pins. cleared and A/D Interrupt Flag bit, ADIF, is set. The A/D Converter has a unique feature of being able A device Reset forces all registers to their Reset state. to operate while the device is in Sleep mode. To This forces the A/D module to be turned off and any operate in Sleep, the A/D conversion clock must be conversion in progress is aborted. The value in the derived from the A/D’s internal RC oscillator. ADRESH:ADRESL register pair is not modified for a Power-on Reset. These registers will contain unknown The output of the sample and hold is the input into the data after a Power-on Reset. converter, which generates the result via successive approximation. The block diagram of the A/D module is shown in Figure21-1. Each port pin associated with the A/D Converter can be configured as an analog input or as a digital I/O. The ADRESH and ADRESL registers contain the result of FIGURE 21-1: A/D BLOCK DIAGRAM CHS<3:0> 1111 AN15(1) 1110 AN14(1) 1101 AN13(1) 1100 AN12(1) 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7 0110 AN6 0100 AN4 VAIN 10-Bit (Input Voltage) 0011 AN3 A/D Converter 0010 AN2 0001 VCFG<1:0> AN1 0000 VDD(2) AN0 VREF+ Reference Voltage VREF- VSS(2) Note 1: Channels AN15 through AN12 are not available on 64-pin devices. 2: I/O pins have diode protection to VDD and VSS. DS39663F-page 264 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY After the A/D module has been configured as desired, 3. Wait the required acquisition time (if required). the selected channel must be acquired before the 4. Start conversion: conversion is started. The analog input channels must • Set GO/DONE bit (ADCON0<1>) have their corresponding TRIS bits selected as an 5. Wait for A/D conversion to complete, by either: input. To determine acquisition time, see Section21.1 “A/D Acquisition Requirements”. After this acquisi- • Polling for the GO/DONE bit to be cleared tion time has elapsed, the A/D conversion can be OR started. An acquisition time can be programmed to • Waiting for the A/D interrupt occur between setting the GO/DONE bit and the actual 6. Read A/D Result registers (ADRESH:ADRESL); start of the conversion. clear bit, ADIF, if required. The following steps should be followed to do an A/D 7. For next conversion, go to step 1 or step 2, as conversion: required. The A/D conversion time per bit is 1. Configure the A/D module: defined as TAD. A minimum wait of 2 TAD is • Configure analog pins, voltage reference and required before next acquisition starts. digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D acquisition time (ADCON2) • Select A/D conversion clock (ADCON2) • Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set GIE bit FIGURE 21-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC ≤ 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance 6V VT = Threshold Voltage 5V ILEAKAGE = Leakage Current at the pin due to VDD 4V various junctions 3V RIC = Interconnect Resistance 2V SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) RSS = Sampling Switch Resistance 1 2 3 4 Sampling Switch (kΩ) © 2009 Microchip Technology Inc. DS39663F-page 265
PIC18F87J10 FAMILY 21.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation21-1 may be used. This equation assumes For the A/D Converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is shown in Figure21-2. The Equation21-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time, TACQ. This calculation is based on the following application system required to charge the capacitor, CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 25 pF at the analog input (due to pin leakage current). The Rs = 2.5 kΩ maximum recommended impedance for analog Conversion Error ≤ 1/2 LSb sources is 2.5kΩ. After the analog input channel is VDD = 3V→Rss = 2 kΩ selected (changed), the channel must be sampled for Temperature = 85°C (system max.) at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 21-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 21-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 μs TCOFF = (Temp – 25°C)(0.02 μs/°C) (85°C – 25°C)(0.02 μs/°C) 1.2 μs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) μs -(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs 1.05 μs TACQ = 0.2 μs + 1 μs + 1.2 μs 2.4 μs DS39663F-page 266 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 21.2 Selecting and Configuring TABLE 21-1: TAD vs. DEVICE OPERATING Automatic Acquisition Time FREQUENCIES The ADCON2 register allows the user to select an AD Clock Source (TAD) Maximum acquisition time that occurs each time the GO/DONE Device bit is set. Operation ADCS<2:0> Frequency When the GO/DONE bit is set, sampling is stopped and 2 TOSC 000 2.86 MHz a conversion begins. The user is responsible for ensur- 4 TOSC 100 5.71 MHz ing the required acquisition time has passed between 8 TOSC 001 11.43 MHz selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT<2:0> bits 16 TOSC 101 22.86 MHz (ADCON2<5:3>) remain in their Reset state (‘000’) and 32 TOSC 010 40.0 MHz is compatible with devices that do not offer 64 TOSC 110 40.0 MHz programmable acquisition times. RC(2) x11 1.00 MHz(1) If desired, the ACQT bits can be set to select a pro- Note 1: The RC source has a typical TAD time of grammable acquisition time for the A/D module. When 4μs. the GO/DONE bit is set, the A/D module continues to 2: For device frequencies above 1 MHz, the sample the input for the selected acquisition time, then device must be in Sleep mode for the entire automatically begins a conversion. Since the acquisi- conversion or the A/D accuracy may be out tion time is programmed, there may be no need to wait of specification. for an acquisition time between selecting a channel and setting the GO/DONE bit. 21.4 Configuring Analog Port Pins In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the The ADCON1, TRISA, TRISF and TRISH registers A/D begins sampling the currently selected channel control the operation of the A/D port pins. The port pins again. If an acquisition time is programmed, there is needed as analog inputs must have their correspond- nothing to indicate if the acquisition time has ended or ing TRIS bits set (input). If the TRIS bit is cleared if the conversion has begun. (output), the digital output level (VOH or VOL) will be converted. 21.3 Selecting the A/D Conversion The A/D operation is independent of the state of the Clock CHS<3:0> bits and the TRIS bits. The A/D conversion time per bit is defined as TAD. The Note 1: When reading the port register, all pins A/D conversion requires 11 TAD per 10-bit conversion. configured as analog input channels will The source of the A/D conversion clock is software read as cleared (a low level). Pins config- selectable. ured as digital inputs will convert an analog input. Analog levels on a digitally There are seven possible options for TAD: configured input will be accurately • 2 TOSC converted. • 4 TOSC 2: Analog levels on any pin defined as a • 8 TOSC digital input may cause the digital input • 16 TOSC buffer to consume current out of the • 32 TOSC device’s specification limits. • 64 TOSC • Internal RC Oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD (see parameter 130 in Table27-27 for more information). Table21-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. © 2009 Microchip Technology Inc. DS39663F-page 267
PIC18F87J10 FAMILY 21.5 A/D Conversions 21.6 Use of the ECCP2 Trigger Figure21-3 shows the operation of the A/D Converter An A/D conversion can be started by the “Special Event after the GO/DONE bit has been set and the Trigger” of the ECCP2 module. This requires that the ACQT<2:0> bits are cleared. A conversion is started CCP2M<3:0> bits (CCP2CON<3:0>) be programmed after the following instruction to allow entry into Sleep as ‘1011’ and that the A/D module is enabled (ADON mode before the conversion begins. bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion Figure21-4 shows the operation of the A/D Converter and the Timer1 (or Timer3) counter will be reset to zero. after the GO/DONE bit has been set, the ACQT<2:0> Timer1 (or Timer3) is reset to automatically repeat the bits are set to ‘010’ and a 4TAD acquisition time has A/D acquisition period with minimal software overhead been selected before the conversion starts. (moving ADRESH/ADRESL to the desired location). Clearing the GO/DONE bit during a conversion will The appropriate analog input channel must be selected abort the current conversion. The A/D Result register and the minimum acquisition period is either timed by pair will NOT be updated with the partially completed the user, or an appropriate TACQ time is selected before A/D conversion sample. This means the the Special Event Trigger sets the GO/DONE bit (starts ADRESH:ADRESL registers will continue to contain a conversion). the value of the last completed conversion (or the last If the A/D module is not enabled (ADON is cleared), the value written to the ADRESH:ADRESL registers). Special Event Trigger will be ignored by the A/D module After the A/D conversion is completed or aborted, a but will still reset the Timer1 (or Timer3) counter. 2TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 21-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 21-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. DS39663F-page 268 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 21.7 A/D Converter Calibration If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and The A/D Converter in the PIC18F87J10 family of ADCS<2:0> bits in ADCON2 should be updated in devices includes a self-calibration feature which com- accordance with the power-managed mode clock that pensates for any offset generated within the module. will be used. After the power-managed mode is entered The calibration process is automated and is initiated by (either of the power-managed Run modes), an A/D setting the ADCAL bit (ADCON0<7>). The next time acquisition or conversion may be started. Once an the GO/DONE bit is set, the module will perform a acquisition or conversion is started, the device should “dummy” conversion (that is, with reading none of the continue to be clocked by the same power-managed input channels) and store the resulting value internally mode clock source until the conversion has been com- to compensate for offset. Thus, subsequent offsets will pleted. If desired, the device may be placed into the be compensated. corresponding power-managed Idle mode during the The calibration process assumes that the device is in a conversion. relatively steady-state operating condition. If A/D If the power-managed mode clock frequency is less calibration is used, it should be performed after each than 1MHz, the A/D RC clock source should be device Reset or if there are other major changes in selected. operating conditions. Operation in the Sleep mode requires the A/D RC clock 21.8 Operation in Power-Managed to be selected. If bits, ACQT<2:0>, are set to ‘000’ and a conversion is started, the conversion will be delayed Modes one instruction cycle to allow execution of the SLEEP The selection of the automatic acquisition time and A/D instruction and entry to Sleep mode. The IDLEN and conversion clock is determined in part by the clock SCS bits in the OSCCON register must have already source and frequency while in a power-managed been cleared prior to starting the conversion. mode. TABLE 21-2: SUMMARY OF A/D REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR2 OSCFIF CMIF — — BCL1IF — TMR3IF CCP2IF 55 PIE2 OSCFIE CMIE — — BCL1IE — TMR3IE CCP2IE 55 IPR2 OSCFIP CMIP — — BCL1IP — TMR3IP CCP2IP 55 ADRESH A/D Result Register High Byte 54 ADRESL A/D Result Register Low Byte 54 ADCON0 ADCAL — CHS3 CHS3 CHS1 CHS0 GO/DONE ADON 54 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 54 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 55 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 56 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — 56 TRISF TRISF5 TRISF4 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — 56 PORTH(1) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 56 TRISH(1) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: This register is not implemented on 64-pin devices. © 2009 Microchip Technology Inc. DS39663F-page 269
PIC18F87J10 FAMILY NOTES: DS39663F-page 270 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 22.0 COMPARATOR MODULE The CMCON register (Register22-1) selects the comparator input and output configuration. Block The analog comparator module contains two diagrams of the various comparator configurations are comparators that can be configured in a variety of shown in Figure22-1. ways. The inputs can be selected from the analog inputs multiplexed with pins RF1 through RF6, as well as the on-chip voltage reference (see Section23.0 “Comparator Voltage Reference Module”). The digi- tal outputs (normal or inverted) are available at the pin level and can also be read through the control register. REGISTER 22-1: CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM<2:0> = 110: 1 = C1 VIN- connects to RA5/AN10/CVREF C2 VIN- connects to RF3/AN8 0 = C1 VIN- connects to RF6/AN11 C2 VIN- connects to RF4/AN9 bit 2-0 CM<2:0>: Comparator Mode bits Figure22-1 shows the Comparator modes and the CM<2:0> bit settings. © 2009 Microchip Technology Inc. DS39663F-page 271
PIC18F87J10 FAMILY 22.1 Comparator Configuration mode is changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Section27.0 “Electrical Characteristics”. tors, shown in Figure22-1. Bits, CM<2:0>, of the CMCON register are used to select these modes. The Note: Comparator interrupts should be disabled TRISF register controls the data direction of the during a Comparator mode change; comparator pins for each mode. If the Comparator otherwise, a false interrupt may occur. FIGURE 22-1: COMPARATOR I/O OPERATING MODES Comparator Outputs Disabled Comparators Off (POR Default Value) CM<2:0> = 000 CM<2:0> = 111 RF6/AN11 A VIN- RF6/AN11 D VIN- RF5/AN10/ A VIN+ C1 Off (Read as ‘0’) RF5/AN10/ D VIN+ C1 Off (Read as ‘0’) CVREF CVREF RF4/AN9 A VIN- RF4/AN9 D VIN- RF3/AN8 A VIN+ C2 Off (Read as ‘0’) RF3/AN8 D VIN+ C2 Off (Read as ‘0’) Two Independent Comparators Two Independent Comparators with Outputs CM<2:0> = 010 CM<2:0> = 011 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10/ A VIN+ C1 C1OUT RF5/AN10/ A VIN+ C1 C1OUT CVREF CVREF RF2/AN7/C1OUT* RF4/AN9 A VIN- RF4/AN9 A VIN- RF3/AN8 A VIN+ C2 C2OUT RF3/AN8 A VIN+ C2 C2OUT RF1/AN6/C2OUT* Two Common Reference Comparators Two Common Reference Comparators with Outputs CM<2:0> = 100 CM<2:0> = 101 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10/ A VIN+ C1 C1OUT RF5/AN10/ A VIN+ C1 C1OUT CVREF CVREF RF2/AN7/C1OUT* RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF1/AN6/C2OUT* One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM<2:0> = 001 CM<2:0> = 110 RF6/AN11 A VIN- RF6/AN11 A CIS = 0 VIN- RF5/AN10/ A VIN+ C1 C1OUT RCFV5R/EAFN10/ A CIS = 1 VIN+ C1 C1OUT CVREF RF2/AN7/C1OUT* RF4/AN9 A CIS = 0 VIN- RF4/AN9 D VIN- RF3/AN8 A CIS = 1 VIN+ C2 C2OUT RF3/AN8 D VIN+ C2 Off (Read as ‘0’) CVREF From VREF module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs. DS39663F-page 272 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 22.2 Comparator Operation 22.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure22-2, along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference from the the digital output. When the analog input at VIN+ is less comparator voltage reference module. This module is than the analog input VIN-, the output of the comparator described in more detail in Section23.0 “Comparator is a digital low level. When the analog input at VIN+ is Voltage Reference Module”. greater than the analog input VIN-, the output of the The internal reference is only available in the mode comparator is a digital high level. The shaded areas of where four inputs are multiplexed to two comparators the output of the comparator in Figure22-2 represent (CM<2:0>=110). In this mode, the internal voltage the uncertainty due to input offsets and response time. reference is applied to the VIN+ pin of both comparators. 22.3 Comparator Reference 22.4 Comparator Response Time Depending on the comparator operating mode, either an external or internal voltage reference may be used. Response time is the minimum time, after selecting a The analog signal present at VIN- is compared to the new reference voltage or input source, before the signal at VIN+ and the digital output of the comparator comparator output has a valid level. If the internal ref- is adjusted accordingly (Figure22-2). erence is changed, the maximum delay of the internal voltage reference must be considered when using the FIGURE 22-2: SINGLE COMPARATOR comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section27.0 “Electrical Characteristics”). VIN+ + 22.5 Comparator Outputs Output VIN- – The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RF1 and RF2 I/O pins. When enabled, multiplexors in the output path of the RF1 and RF2 pins will switch and the output of each pin will be the unsynchronized output of the VIN- comparator. The uncertainty of each of the comparators is related to the input offset voltage and VIN+ the response time given in the specifications. Figure22-3 shows the comparator output block diagram. Output The TRISF bits will still function as an output enable/ disable for the RF1 and RF2 pins while in this mode. The polarity of the comparator outputs can be changed 22.3.1 EXTERNAL REFERENCE SIGNAL using the C2INV and C1INV bits (CMCON<5:4>). When external voltage references are used, the Note1: When reading the PORT register, all pins comparator module can be configured to have the com- configured as analog inputs will read as a parators operate from the same or different reference ‘0’. Pins configured as digital inputs will sources. However, threshold detector applications may convert an analog input according to the require the same reference. The reference signal must Schmitt Trigger input specification. be between VSS and VDD and can be applied to either 2: Analog levels on any pin defined as a pin of the comparator(s). digital input may cause the input buffer to consume more current than is specified. © 2009 Microchip Technology Inc. DS39663F-page 273
PIC18F87J10 FAMILY FIGURE 22-3: COMPARATOR OUTPUT BLOCK DIAGRAM X E L + Port Pins P TI To RF1 or UL - RF2 Pin M D Q Bus CxINV Data Read CMCON EN D Q Set CMIF bit EN CL From Other Reset Comparator 22.6 Comparator Interrupts 22.7 Comparator Operation During Sleep The comparator interrupt flag is set whenever there is a change in the output value of either comparator. When a comparator is active and the device is placed Software will need to maintain information about the in Sleep mode, the comparator remains active and the status of the output bits, as read from CMCON<7:6>, to interrupt is functional, if enabled. This interrupt will determine the actual change that occurred. The CMIF wake-up the device from Sleep mode, when enabled. bit (PIR2<6>) is the Comparator Interrupt Flag. The Each operational comparator will consume additional CMIF bit must be reset by clearing it. Since it is also current, as shown in the comparator specifications. To possible to write a ‘1’ to this register, a simulated minimize power consumption while in Sleep mode, turn interrupt may be initiated. off the comparators (CM<2:0>=111) before entering Both the CMIE bit (PIE2<6>) and the PEIE bit Sleep. If the device wakes up from Sleep, the contents (INTCON<6>) must be set to enable the interrupt. In of the CMCON register are not affected. addition, the GIE bit (INTCON<7>) must also be set. If 22.8 Effects of a Reset any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt A device Reset forces the CMCON register to its Reset condition occurs. state, causing the comparator modules to be turned off Note: If a change in the CMCON register (CM<2:0>=111). However, the input pins (RF3 (C1OUT or C2OUT) should occur when a through RF6) are configured as analog inputs by read operation is being executed (start of default on device Reset. The I/O configuration for these the Q2 cycle), then the CMIF (PIR2 pins is determined by the setting of the PCFG<3:0> bits register) interrupt flag may not get set. (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at Reset The user, in the Interrupt Service Routine, can clear the time. interrupt in the following manner: a) Any read or write of CMCON will end the mismatch condition. b) Clear flag bit, CMIF. A mismatch condition will continue to set flag bit, CMIF. Reading CMCON will end the mismatch condition and allow flag bit, CMIF, to be cleared. DS39663F-page 274 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 22.9 Analog Input Connection range by more than 0.6V in either direction, one of the Considerations diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10kΩ is A simplified circuit for an analog input is shown in recommended for the analog sources. Any external Figure22-4. Since the analog pins are connected to a component connected to an analog input pin, such as digital output, they have reverse biased diodes to VDD a capacitor or a Zener diode, should have very little and VSS. The analog input, therefore, must be between leakage current. VSS and VDD. If the input voltage deviates from this FIGURE 22-4: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L5E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR2 OSCFIF CMIF — — BCL1IF — TMR3IF CCP2IF 55 PIE2 OSCFIE CMIE — — BCL1IE — TMR3IE CCP2IE 55 IPR2 OSCFIP CMIP — — BCL1IP — TMR3IP CCP2IP 55 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 55 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 55 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — 56 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 — 56 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. © 2009 Microchip Technology Inc. DS39663F-page 275
PIC18F87J10 FAMILY NOTES: DS39663F-page 276 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 23.0 COMPARATOR VOLTAGE to be used is selected by the CVRR bit (CVRCON<5>). REFERENCE MODULE The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits The comparator voltage reference is a 16-tap resistor (CVR<3:0>), with one range offering finer resolution. ladder network that provides a selectable reference The equations used to calculate the output of the voltage. Although its primary purpose is to provide a comparator voltage reference are as follows: reference for the analog comparators, it may also be If CVRR = 1: used independently of them. CVREF = ((CVR<3:0>)/24) x (CVRSRC) A block diagram of the module is shown in Figure23-1. If CVRR = 0: The resistor ladder is segmented to provide two ranges CVREF=(CVRSRC/4)+((CVR<3:0>)/32)x of CVREF values and has a power-down function to (CVRSRC) conserve power when the reference is not being used. The comparator reference supply voltage can come The module’s supply reference can be provided from either device VDD/VSS or an external voltage reference. from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit 23.1 Configuring the Comparator (CVRCON<4>). Voltage Reference The settling time of the comparator voltage reference The comparator voltage reference module is controlled must be considered when changing the CVREF through the CVRCON register (Register23-1). The output (see Table27-3 in Section27.0 “Electrical comparator voltage reference provides two ranges of Characteristics”). output voltage, each with 16 distinct levels. The range REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = VDD – VSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0 ≤ (CVR<3:0>) ≤ 15) When CVRR = 1: CVREF = ((CVR<3:0>)/24) • (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) • (CVRSRC) Note 1: CVROE overrides the TRISF<5> bit setting. © 2009 Microchip Technology Inc. DS39663F-page 277
PIC18F87J10 FAMILY FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ VDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 23.2 Voltage Reference Accuracy/Error 23.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit, CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RA2 pin by clearing (Figure23-1) keep CVREF from approaching the refer- bit, CVROE (CVRCON<6>), and selects the high- ence source rails. The voltage reference is derived voltage range by clearing bit, CVRR (CVRCON<5>). from the reference source; therefore, the CVREF output The CVR value select bits are also cleared. changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be 23.5 Connection Considerations found in Section27.0 “Electrical Characteristics”. The voltage reference module operates independently 23.3 Operation During Sleep of the comparator module. The output of the reference generator may be connected to the RF5 pin if the When the device wakes up from Sleep through an CVROE bit is set. Enabling the voltage reference out- interrupt or a Watchdog Timer time-out, the contents of put onto RA2 when it is configured as a digital input will the CVRCON register are not affected. To minimize increase current consumption. Connecting RF5 as a current consumption in Sleep mode, the voltage digital output with CVRSS enabled will also increase reference should be disabled. current consumption. The RF5 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure23-2 shows an example buffering technique. DS39663F-page 278 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 23-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F87J10 CVREF R(1) Module + Voltage RF5 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the comparator voltage reference Configuration bits, CVRCON<5> and CVRCON<3:0>. TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 55 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 55 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference. © 2009 Microchip Technology Inc. DS39663F-page 279
PIC18F87J10 FAMILY NOTES: DS39663F-page 280 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 24.0 SPECIAL FEATURES OF THE 24.1.1 CONSIDERATIONS FOR CPU CONFIGURING THE PIC18F87J10 FAMILY DEVICES PIC18F87J10 family devices include several features Unlike previous PIC18 microcontrollers, devices of the intended to maximize reliability and minimize cost PIC18F87J10 family do not use persistent memory through elimination of external components. These are: registers to store configuration information. The config- • Oscillator Selection uration bytes are implemented as volatile memory • Resets: which means that configuration data must be - Power-on Reset (POR) programmed each time the device is powered up. - Power-up Timer (PWRT) Configuration data is stored in the four words at the top - Oscillator Start-up Timer (OST) of the on-chip program memory space, known as the - Brown-out Reset (BOR) Flash Configuration Words. It is stored in program memory in the same order shown in Table24-2, with • Interrupts CONFIG1L at the lowest address and CONFIG3H at • Watchdog Timer (WDT) the highest. The data is automatically loaded in the • Fail-Safe Clock Monitor proper Configuration registers during device power-up. • Two-Speed Start-up When creating applications for these devices, users • Code Protection should always specifically allocate the location of the • In-Circuit Serial Programming Flash Configuration Word for configuration data; this is The oscillator can be configured for the application to make certain that program code is not stored in this depending on frequency, power, accuracy and cost. All address when the code is compiled. of the options are discussed in detail in Section3.0 The volatile memory cells used for the Configuration “Oscillator Configurations”. bits always reset to ‘1’ on Power-on Resets. For all A complete discussion of device Resets and interrupts other type of Reset events, the previously programmed is available in previous sections of this data sheet. values are maintained and used without reloading from program memory. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, the PIC18F87J10 family of The four Most Significant bits of CONFIG1H, devices have a configurable Watchdog Timer which is CONFIG2H and CONFIG3H in program memory controlled in software. should also be ‘1111’. This makes these Configuration The inclusion of an internal RC oscillator also provides Words appear to be NOP instructions in the remote event that their locations are ever executed by the additional benefits of a Fail-Safe Clock Monitor accident. Since Configuration bits are not implemented (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and in the corresponding locations, writing ‘1’s to these automatic switchover in the event of its failure. locations has no effect on device operation. Two-Speed Start-up enables code to be executed To prevent inadvertent configuration changes during almost immediately on start-up, while the primary clock code execution, all programmable Configuration bits source completes its start-up delays. are write-once. After a bit is initially programmed during All of these features are enabled and configured by a power cycle, it cannot be written to again. Changing setting the appropriate Configuration register bits. a device configuration requires that power to the device be cycled. 24.1 Configuration Bits TABLE 24-1: MAPPING OF THE FLASH The Configuration bits can be programmed (read as CONFIGURATION WORDS TO ‘0’) or left unprogrammed (read as ‘1’) to select various THE CONFIGURATION device configurations. These bits are mapped starting REGISTERS at program memory location 300000h. A complete list is shown in Table24-2. A detailed explanation of the Configuration Code Space various bit functions is provided in Register24-1 Configuration Byte Address Register Address through Register24-6. CONFIG1L XXXF8h 300000h CONFIG1H XXXF9h 300001h CONFIG2L XXXFAh 300002h CONFIG2H XXXFBh 300003h CONFIG3L XXXFCh 300004h CONFIG3H XXXFDh 300005h CONFIG4L(1) XXXFEh 300006h CONFIG4H(1) XXXFFh 300007h Note 1: Unimplemented in PIC18F87J10 family devices. © 2009 Microchip Technology Inc. DS39663F-page 281
PIC18F87J10 FAMILY TABLE 24-2: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value(1) 300000h CONFIG1L DEBUG XINST STVREN — — — — WDTEN 111- ---1 300001h CONFIG1H —(2) —(2) —(2) —(2) —(3) CP0 — — ---- 01-- 300002h CONFIG2L IESO FCMEN — — — FOSC2 FOSC1 FOSC0 11-- -111 300003h CONFIG2H —(2) —(2) —(2) —(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111 300004h CONFIG3L WAIT(4) BW(4) EMB1(4) EMB0(4) EASHFT(4) — — — 1111 1--- 300005h CONFIG3H —(2) —(2) —(2) —(2) — — ECCPMX(4) CCP2MX ---- --11 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(5) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 10x1(5) Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’. Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the configuration bytes maintain their previously programmed states. 2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed. 3: This bit should always be maintained as ‘0’. 4: Implemented in 80-pin devices only. On 64-pin devices, these bits are reserved and should always be maintained as ‘1’. 5: See Register24-7 and Register24-8 for DEVID values. These registers are read-only and cannot be programmed by the user. DS39663F-page 282 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 24-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 U-0 R/WO-1 DEBUG XINST STVREN — — — — WDTEN bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled bit 4-1 Unimplemented: Read as ‘0’ bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) REGISTER 24-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-0 U-0 U-0 U-0 U-0 R/WO-1 U-0 U-0 — — — — —(1) CP0 — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 CP0: Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is code-protected bit 1-0 Unimplemented: Read as ‘0’ Note 1: This bit should always be maintained as ‘0’. © 2009 Microchip Technology Inc. DS39663F-page 283
PIC18F87J10 FAMILY REGISTER 24-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/WO-1 R/WO-1 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 IESO FCMEN — — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-3 Unimplemented: Read as ‘0’ bit 2 FOSC2: Default/Reset System Clock Select bit 1 = Clock selected by FOSC<1:0> as a system clock is enabled when OSCCON<1:0> = 00 0 = INTRC enabled as a system clock when OSCCON<1:0> = 00 bit 1-0 FOSC<1:0>: Oscillator Selection bits 11 = EC oscillator, PLL enabled and under software control, CLKO function on OSC2 10 = EC oscillator, CLKO function on OSC2 01 = HS oscillator, PLL enabled and under software control 00 = HS oscillator REGISTER 24-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1 — — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 DS39663F-page 284 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY REGISTER 24-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 WAIT(1) BW(1) EMB1(1) EMB0(1) EASHFT(1) — — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states for operations on external memory bus disabled 0 = Wait states for operations on external memory bus enabled bit 6 BW: Data Bus Width Select bit(1) 1 = 16-Bit External Bus mode 0 = 8-Bit External Bus mode bit 5-4 EMB<1:0>: External Memory Bus Configuration bits(1) 11 = Microcontroller mode – external bus disabled 10 = Extended Microcontroller mode,12-Bit Address mode 01 = Extended Microcontroller mode,16-Bit Address mode 00 = Extended Microcontroller mode, 20-Bit Address mode bit 3 EASHFT: External Address Bus Shift Enable bit(1) 1 = Address shifting enabled; address on external bus is offset to start at 000000h 0 = Address shifting disabled; address on external bus reflects the PC value bit 2-0 Unimplemented: Read as ‘0’ Note 1: Implemented only on 80-pin devices. REGISTER 24-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-0 U-0 U-0 U-0 U-0 U-0 R/WO-1 R/WO-1 — — — — — — ECCPMX(1) CCP2MX bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 ECCPMX: ECCPx MUX bit(1) 1 = ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 0 = ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 bit 0 CCP2MX: ECCP2 MUX bit 1 = ECCP2/P2A is multiplexed with RC1 0 = ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (all devices) or with RB3 in Extended Microcontroller mode (80-pin devices only) Note 1: Available only on 80-pin devices. © 2009 Microchip Technology Inc. DS39663F-page 285
PIC18F87J10 FAMILY REGISTER 24-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F87J10 FAMILY DEVICES R R R R R R R R DEV2(1) DEV1(1) DEV0(1) REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 DEV<2:0>: Device ID bits(1) 111 = PIC18F85J10 101 = PIC18F67J10 100 = PIC18F66J15 011 = PIC18F66J10 or PIC18F87J10 010 = PIC18F65J15 or PIC18F86J15 001 = PIC18F65J10 or PIC18F86J10 000 = PIC18F85J15 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. Note 1: Where values for DEV<2:0> are shared by more than one device number, the specific device is always identified by using the entire DEV<10:0> bit sequence. REGISTER 24-8: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F87J10 FAMILY DEVICES R R R R R R R R DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1) bit 7 bit 0 Legend: R = Read-only bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-0 DEV<10:3>: Device ID bits(1) These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. 0001 0101 = PIC18F65J10/65J15/66J10/66J15/67J10/85J10 devices 0001 0111 = PIC18F85J15/86J10/86J15/87J10 devices Note 1: The values for DEV<10:3> may be shared with other device families. The specific device is always identified by using the entire DEV<10:0> bit sequence. DS39663F-page 286 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 24.2 Watchdog Timer (WDT) Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts For PIC18F87J10 family devices, the WDT is driven by when executed. the INTRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 2: When a CLRWDT instruction is executed, 4ms and has the same stability as the INTRC oscillator. the postscaler count will be cleared. The 4ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected 24.2.1 CONTROL REGISTER by a multiplexor, controlled by the WDTPS bits in Config- The WDTCON register (Register24-9) is a readable uration Register 2H. Available periods range from about and writable register. The SWDTEN bit enables or dis- 4ms to 135seconds (2.25 minutes depending on ables WDT operation. This allows software to override voltage, temperature and WDT postscaler). The WDT the WDTEN Configuration bit and enable the WDT only and postscaler are cleared whenever a SLEEP or if it has been disabled by the Configuration bit. CLRWDT instruction is executed, or a clock failure (primary or Timer1 oscillator) has occurred. FIGURE 24-1: WDT BLOCK DIAGRAM Enable WDT SWDTEN INTRC Control WDT Counter INTRC Oscillator ÷128 Wake-up from Power-Managed Modes CLRWDT Programmable Postscaler Reset WDT Reset All Device Resets 1:1 to 1:32,768 WDT 4 WDTPS<3:0> Sleep REGISTER 24-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled. TABLE 24-3: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page RCON IPEN — — RI TO PD POR BOR 54 WDTCON — — — — — — — SWDTEN 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer. © 2009 Microchip Technology Inc. DS39663F-page 287
PIC18F87J10 FAMILY 24.3 On-Chip Voltage Regulator FIGURE 24-2: CONNECTIONS FOR THE ON-CHIP REGULATOR All of the PIC18F87J10 family devices power their core digital logic at a nominal 2.5V. For designs that are Regulator Enabled (ENVREG tied to VDD): required to operate at a higher typical voltage, such as 3.3V 3.3V, all devices in the PIC18F87J10 family incorporate an on-chip regulator that allows the device to run its PIC18FXXJ10/XXJ15 core logic from VDD. VDD ENVREG The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, pro- VDDCORE/VCAP vides power to the core from the other VDD pins. When CF the regulator is enabled, a low-ESR filter capacitor VSS must be connected to the VDDCORE/VCAP pin (Figure24-2). This helps to maintain the stability of the regulator. The recommended value for the filter capac- itor is provided in Section27.3 “DC Characteristics: PIC18F87J10 Family (Industrial)”. Regulator Disabled (ENVREG tied to ground): If ENVREG is tied to VSS, the regulator is disabled. In 2.5V(1) 3.3V(1) this case, separate power for the core logic at a nomi- nal 2.5V must be supplied to the device on the PIC18FXXJ10/XXJ15 VDDCORE/VCAP pin to run the I/O pins at higher voltage VDD levels, typically 3.3V. Alternatively, the VDDCORE/VCAP ENVREG and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure24-2 for possible VDDCORE/VCAP configurations. VSS 24.3.1 ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC18F87J10 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to Regulator Disabled (VDD tied to VDDCORE): maintain a regulated level, the regulator Reset circuitry will generate a BOR Reset. This event is captured by 2.5V(1) the BOR flag bit (RCON<0>). PIC18FXXJ10/XXJ15 The operation of the BOR is described in more detail in VDD Section5.4 “Brown-out Reset (BOR)” and ENVREG Section5.4.1 “Detecting BOR”. The brown-out voltage levels are specific in Section27.1 “DC Characteristics: VDDCORE/VCAP Supply Voltage, PIC18F87J10 Family (Industrial)”. VSS 24.3.2 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up Note 1: These are typical operating voltages. Refer requirements for the device. If the application does not to Section27.1 “DC Characteristics: use the regulator, then strict power-up conditions must Supply Voltage” for the full operating be adhered to. While powering up, VDDCORE must ranges of VDD and VDDCORE. never exceed VDD by 0.3 volts. DS39663F-page 288 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 24.4 Two-Speed Start-up In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the The Two-Speed Start-up feature helps to minimize the currently selected clock source until the primary clock latency period, from oscillator start-up to code execu- source becomes available. The setting of the IESO bit tion, by allowing the microcontroller to use the INTRC is ignored. oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO 24.4.1 SPECIAL CONSIDERATIONS FOR Configuration bit. USING TWO-SPEED START-UP Two-Speed Start-up should be enabled only if the While using the INTRC oscillator in Two-Speed primary oscillator mode is HS or HSPLL Start-up, the device still obeys the normal command (Crystal-based) modes. Since the EC and ECPLL sequences for entering power-managed modes, modes do not require an OST start-up delay, including serial SLEEP instructions (refer to Two-Speed Start-up should be disabled. Section4.1.4 “Multiple Sleep Commands”). In When enabled, Resets and wake-ups from Sleep mode practice, this means that user code can change the cause the device to configure itself to run from the SCS1:SCS0 bits setting or issue SLEEP instructions internal oscillator block as the clock source, following before the OST times out. This would allow an applica- the time-out of the Power-up Timer after a Power-on tion to briefly wake-up, perform routine “housekeeping” Reset is enabled. This allows almost immediate code tasks and return to Sleep before the device starts to execution while the primary oscillator starts and the operate from the primary oscillator. OST is running. Once the OST times out, the device User code can also check if the primary clock source is automatically switches to PRI_RUN mode. currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. FIGURE 24-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake from Interrupt Event OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. © 2009 Microchip Technology Inc. DS39663F-page 289
PIC18F87J10 FAMILY 24.5 Fail-Safe Clock Monitor During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable The Fail-Safe Clock Monitor (FSCM) allows the for timing sensitive applications. In these cases, it may microcontroller to continue operation in the event of an be desirable to select another clock configuration and external oscillator failure by automatically switching the enter an alternate power-managed mode. This can be device clock to the internal oscillator block. The FSCM done to attempt a partial recovery or execute a function is enabled by setting the FCMEN Configuration controlled shutdown. See Section4.1.4 “Multiple bit. Sleep Commands” and Section24.4.1 “Special When FSCM is enabled, the INTRC oscillator runs at Considerations for Using Two-Speed Start-up” for all times to monitor clocks to peripherals and provide a more details. backup clock in the event of a clock failure. Clock The FSCM will detect failures of the primary or second- monitoring (shown in Figure24-4) is accomplished by ary clock sources only. If the internal oscillator block creating a sample clock signal which is the INTRC out- fails, no failure would be detected, nor would any action put divided by 64. This allows ample time between be possible. FSCM sample clocks for a peripheral clock edge to occur. The peripheral device clock and the sample 24.5.1 FSCM AND THE WATCHDOG TIMER clock are presented as inputs to the Clock Monitor latch Both the FSCM and the WDT are clocked by the (CM). The CM is set on the falling edge of the device INTRC oscillator. Since the WDT operates with a clock source but cleared on the rising edge of the separate divider and counter, disabling the WDT has sample clock. no effect on the operation of the INTRC oscillator when the FSCM is enabled. FIGURE 24-4: FSCM BLOCK DIAGRAM As already noted, the clock source is switched to the Clock Monitor INTRC clock when a clock failure is detected; this may Latch (CM) (edge-triggered) mean a substantial change in the speed of code execu- Peripheral tion. If the WDT is enabled with a small prescale value, S Q Clock a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, fail-safe clock events also reset the WDT and INTRC postscaler, allowing it to start timing from when execu- ÷ 64 C Q Source tion speed was changed and decreasing the likelihood of an erroneous time-out. (32 μs) 488 Hz (2.048 ms) 24.5.2 EXITING FAIL-SAFE OPERATION Clock The fail-safe condition is terminated by either a device Failure Reset or by entering a power-managed mode. On Detected Reset, the controller starts the primary clock source specified in Configuration Register 2H (with any Clock failure is tested for on the falling edge of the required start-up delays that are required for the oscil- sample clock. If a sample clock falling edge occurs lator mode, such as OST or PLL timer). The INTRC while CM is still set, a clock failure has been detected oscillator provides the device clock until the primary (Figure24-5). This causes the following: clock source becomes ready (similar to a Two-Speed • the FSCM generates an oscillator fail interrupt by Start-up). The clock source is then switched to the setting bit, OSCFIF (PIR2<7>); primary clock (indicated by the OSTS bit in the • the device clock source is switched to the internal OSCCON register becoming set). The Fail-Safe Clock oscillator block (OSCCON is not updated to show Monitor then resumes monitoring the peripheral clock. the current clock source – this is the fail-safe The primary clock source may never become ready condition); and during start-up. In this case, operation is clocked by the • the WDT is reset. INTRC oscillator. The OSCCON register will remain in its Reset state until a power-managed mode is entered. DS39663F-page 290 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 24-5: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 24.5.3 FSCM INTERRUPTS IN 24.5.4 POR OR WAKE-UP FROM SLEEP POWER-MANAGED MODES The FSCM is designed to detect oscillator failure at any By entering a power-managed mode, the clock point after the device has exited Power-on Reset multiplexor selects the clock source selected by the (POR) or low-power Sleep mode. When the primary OSCCON register. Fail-Safe Monitoring of the device clock is either EC or INTRC modes, monitoring power-managed clock source resumes in the can begin immediately following these events. power-managed mode. For HS or HSPLL modes, the situation is somewhat dif- If an oscillator failure occurs during power-managed ferent. Since the oscillator may require a start-up time operation, the subsequent events depend on whether considerably longer than the FSCM sample clock time, or not the oscillator failure interrupt is enabled. If a false clock failure may be detected. To prevent this, enabled (OSCFIF=1), code execution will be clocked the internal oscillator block is automatically configured by the INTRC multiplexor. An automatic transition back as the device clock and functions until the primary clock to the failed clock source will not occur. is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the If the interrupt is disabled, subsequent interrupts while primary clock is stable, the INTRC returns to its role as in Idle mode will cause the CPU to begin executing the FSCM source. instructions while being clocked by the INTRC source. Note: The same logic that prevents false oscilla- tor failure interrupts on POR, or wake from Sleep, will also prevent the detection of the oscillator’s failure to start at all follow- ing these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section24.4.1 “Special Considerations for Using Two-Speed Start-up”, it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power-managed mode is selected, the primary clock is disabled. © 2009 Microchip Technology Inc. DS39663F-page 291
PIC18F87J10 FAMILY 24.6 Program Verification and 24.7 In-Circuit Serial Programming Code Protection PIC18F87J10 family microcontrollers can be serially For all devices in the PIC18F87J10 family of devices, programmed while in the end application circuit. This is the on-chip program memory space is treated as a simply done with two lines for clock and data and three single block. Code protection for this block is controlled other lines for power, ground and the programming by one Configuration bit, CP0. This bit inhibits external voltage. This allows customers to manufacture boards reads and writes to the program memory space. It has with unprogrammed devices and then program the no direct effect in normal execution mode. microcontroller just before shipping the product. This also allows the most recent firmware or a custom 24.6.1 CONFIGURATION REGISTER firmware to be programmed. PROTECTION 24.8 In-Circuit Debugger The Configuration registers are protected against untoward changes or reads in two ways. The primary When the DEBUG Configuration bit is programmed to protection is the write-once feature of the Configuration a ‘0’, the In-Circuit Debugger functionality is enabled. bits which prevents reconfiguration once the bit has This function allows simple debugging functions when been programmed during a power cycle. To safeguard used with MPLAB® IDE. When the microcontroller has against unpredictable events, Configuration bit this feature enabled, some resources are not available changes resulting from individual cell-level disruptions for general use. Table24-4 shows which resources are (such as ESD events) will cause a parity error and required by the background debugger. trigger a device Reset. The data for the Configuration registers is derived from TABLE 24-4: DEBUGGER RESOURCES the Flash Configuration Words in program memory. I/O pins: RB6, RB7 When the CP0 bit set, the source data for device Stack: 2 levels configuration is also protected as a consequence. Program Memory: 512 bytes Data Memory: 10 bytes DS39663F-page 292 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 25.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: The PIC18F87J10 family of devices incorporate the • A literal value to be loaded into a file register standard set of 75 PIC18 core instructions, as well as (specified by ‘k’) an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software • The desired FSR register to load the literal value stack. The extended set is discussed later in this into (specified by ‘f’) section. • No operand required (specified by ‘—’) 25.1 Standard Instruction Set The control instructions may use some of the following operands: The standard PIC18 instruction set adds many enhancements to the previous PIC® MCU instruction • A program memory address (specified by ‘n’) sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions PIC MCU instruction sets. Most instructions are a (specified by ‘s’) single program memory word (16 bits), but there are • The mode of the table read and table write four instructions that require two program memory instructions (specified by ‘m’) locations. • No operand required Each single-word instruction is a 16-bit word divided (specified by ‘—’) into an opcode, which specifies the instruction type and All instructions are a single word, except for four one or more operands, which further specify the double-word instructions. These instructions were operation of the instruction. made double-word to contain the required information The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If into four basic categories: this second word is executed as an instruction (by itself), it will execute as a NOP. • Byte-oriented operations • Bit-oriented operations All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the • Literal operations program counter is changed as a result of the instruc- • Control operations tion. In these cases, the execution takes two instruction The PIC18 instruction set summary in Table25-2 lists cycles with the additional instruction cycle(s) executed byte-oriented, bit-oriented, literal and control as a NOP. operations. Table25-1 shows the opcode field The double-word instructions execute in two instruction descriptions. cycles. Most byte-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. 1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4MHz, the normal 2. The destination of the result (specified by ‘d’) instruction execution time is 1μs. If a conditional test is 3. The accessed memory (specified by ‘a’) true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 μs. The file register designator, ‘f’, specifies which file reg- Two-word branch instructions (if true) would take 3 μs. ister is to be used by the instruction. The destination Figure25-1 shows the general formats that the instruc- designator, ‘d’, specifies where the result of the tions can have. All examples use the convention ‘nnh’ operation is to be placed. If ‘d’ is zero, the result is to represent a hexadecimal number. placed in the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction. The Instruction Set Summary, shown in Table25-2, lists the standard instructions recognized by the All bit-oriented instructions have three operands: Microchip MPASMTM Assembler. 1. The file register (specified by ‘f’) Section25.1.1 “Standard Instruction Set” provides 2. The bit in the file register (specified by ‘b’) a description of each instruction. 3. The accessed memory (specified by ‘a’) The bit field designator, ‘b’, selects the number of the bit affected by the operation, while the file register designator, ‘f’, represents the number of the file in which the bit is located. © 2009 Microchip Technology Inc. DS39663F-page 293
PIC18F87J10 FAMILY TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). f 12-bit Register file address (000h to FFFh). This is the source address. s f 12-bit Register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No Change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-Down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or Unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for Indirect Addressing of register files (source). s z 7-bit offset value for Indirect Addressing of register files (destination). d { } Optional argument. [text] Indicates an Indexed Address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr. → Assigned to. < > Register bit field. ∈ In the set of. italics User-defined term (font is Courier). DS39663F-page 294 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC © 2009 Microchip Technology Inc. DS39663F-page 295
PIC18F87J10 FAMILY TABLE 25-2: PIC18F87J10 FAMILY INSTRUCTION SET 16-bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. DS39663F-page 296 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 25-2: PIC18F87J10 FAMILY INSTRUCTION SET (CONTINUED) 16-bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. © 2009 Microchip Technology Inc. DS39663F-page 297
PIC18F87J10 FAMILY TABLE 25-2: PIC18F87J10 FAMILY INSTRUCTION SET (CONTINUED) 16-bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move Literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. DS39663F-page 298 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 25.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) + k → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f) → dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. Q Cycle Activity: If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data W set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: ADDLW 15h Section25.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = 10h Literal Offset Mode” for details. After Instruction Words: 1 W = 25h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). © 2009 Microchip Technology Inc. DS39663F-page 299
PIC18F87J10 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .AND. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) + (f) + (C) → dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location, ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read literal Process Write to GPR bank. ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: ANDLW 05Fh in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Before Instruction Section25.2.3 “Byte-Oriented and W = A3h Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = 03h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS39663F-page 300 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 d ∈ [0,1] Operation: if Carry bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (W) .AND. (f) → dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ’1’, then the program Description: The contents of W are ANDed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’. incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a GPR bank. two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates Cycles: 1(2) in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section25.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to Words: 1 ‘n’ Data PC No No No No Cycles: 1 operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If Carry = 1; W = 02h PC = address (HERE + 12) REG = C2h If Carry = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39663F-page 301
PIC18F87J10 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b ≤ 7 Operation: if Negative bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: 0 → f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank. incremented to fetch the next instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Words: 1 Section25.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to Q Cycle Activity: ‘n’ Data PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No ‘n’ Data operation Before Instruction FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS39663F-page 302 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39663F-page 303
PIC18F87J10 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS39663F-page 304 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 Operation: (PC) + 2 + 2n → PC a ∈ [0,1] Status Affected: None Operation: 1 → f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected. PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the two-cycle instruction. GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section25.2.3 “Byte-Oriented and Decode Read literal Process Write to Bit-Oriented Instructions in Indexed ‘n’ Data PC Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah © 2009 Microchip Technology Inc. DS39663F-page 305
PIC18F87J10 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 0 ≤ b < 7 a ∈ [0,1] a ∈ [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction set If ‘a’ is ‘0’ and the extended instruction is enabled, this instruction operates in set is enabled, this instruction operates in Indexed Literal Offset Addressing mode Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39663F-page 306 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b < 7 Operation: if Overflow bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (f<b>) → f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank. instruction, the new address will be PC + 2 + 2n. This instruction is then a If ‘a’ is ‘0’ and the extended instruction two-cycle instruction. set is enabled, this instruction operates in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Cycles: 1(2) Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Q1 Q2 Q3 Q4 Words: 1 Decode Read literal Process Write to PC Cycles: 1 ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: Before Instruction PORTC = 0110 0101 [65h] PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39663F-page 307
PIC18F87J10 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: if Zero bit is ‘1’, (PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS, k → PC<20:1>; Status Affected: None if s = 1, Encoding: 1110 0000 nnnn nnnn (W) → WS, Description: If the Zero bit is ‘1’, then the program (STATUS) → STATUSS, will branch. (BSR) → BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will have Encoding: incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk 7 0 instruction, the new address will be 2nd word(k<19:8>) 1111 k kkk kkkk kkkk 19 8 PC + 2 + 2n. This instruction is then a Description: Subroutine call of entire 2-Mbyte two-cycle instruction. memory range. First, return address Words: 1 (PC+ 4) is pushed onto the return stack. Cycles: 1(2) If ‘s’ = 1, the W, STATUS and BSR registers are also pushed into their Q Cycle Activity: respective shadow registers, WS, If Jump: STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs. Then, the 20-bit value ‘k’ Decode Read literal Process Write to is loaded into PC<20:1>. CALL is a ‘n’ Data PC two-cycle instruction. No No No No Words: 2 operation operation operation operation Cycles: 2 If No Jump: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No ‘n’ Data operation Decode Read literal Push PC to Read literal ‘k’<7:0>, stack ’k’<19:8>, Write to PC Example: HERE BZ Jump No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction Example: HERE CALL THERE,1 If Zero = 1; PC = address (Jump) Before Instruction If Zero = 0; PC = address (HERE) PC = address (HERE + 2) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39663F-page 308 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: 000h → WDT, Operation: 000h → f, 000h → WDT postscaler, 1 → Z 1 → TO, 1 → PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the Watchdog Timer. It also resets the If ‘a’ is ‘0’, the Access Bank is selected. postscaler of the WDT. Status bits, TO If ‘a’ is ‘1’, the BSR is used to select the and PD, are set. GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Cycles: 1 in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Decode No Process No Literal Offset Mode” for details. operation Data operation Words: 1 Example: CLRWDT Cycles: 1 Before Instruction Q Cycle Activity: WDT Counter = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write WDT Counter = 00h register ‘f’ Data register ‘f’ WDT Postscaler = 0 TO = 1 PD = 1 Example: CLRF FLAG_REG,1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h © 2009 Microchip Technology Inc. DS39663F-page 309
PIC18F87J10 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: f → dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’. If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank. instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank. mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Words: 1 Section25.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Cycles: 1(2) register ‘f’ Data destination Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h W = ECh Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL) DS39663F-page 310 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), Operation: (f) – (W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of the W by Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the If the contents of ‘f’ are less than the contents of WREG, then the fetched contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Note: 3 cycles if skip and followed Section25.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 Words: 1 Decode Read Process No Cycles: 1(2) register ‘f’ Data operation Note: 3 cycles if skip and followed If skip: by a 2-word instruction. Q1 Q2 Q3 Q4 Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process No If skip and followed by 2-word instruction: register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; PC = Address (LESS) Before Instruction If REG ≥ W; PC = Address (HERE) PC = Address (NLESS) W = ? After Instruction If REG > W; PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER) © 2009 Microchip Technology Inc. DS39663F-page 311
PIC18F87J10 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: If [W<3:0> > 9] or [DC = 1] then, a ∈ [0,1] (W<3:0>) + 6 → W<3:0>; else, Operation: (f) – 1 → dest (W<3:0>) → W<3:0>; Status Affected: C, DC, N, OV, Z If [W<7:4> > 9] or [C = 1] then, Encoding: 0000 01da ffff ffff (W<7:4>) + 6 → W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the C = 1, result is stored in W. If ‘d’ is ‘1’, the else, result is stored back in register ‘f’. (W<7:4>) → W<7:4> If ‘a’ is ‘0’, the Access Bank is selected. Status Affected: C If ‘a’ is ‘1’, the BSR is used to select the Encoding: 0000 0000 0000 0111 GPR bank. Description: DAW adjusts the eight-bit value in W, If ‘a’ is ‘0’ and the extended instruction resulting from the earlier addition of two set is enabled, this instruction operates variables (each in packed BCD format) in Indexed Literal Offset Addressing and produces a correct packed BCD mode whenever f ≤ 95 (5Fh). See result. Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Words: 1 Literal Offset Mode” for details. Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write Q1 Q2 Q3 Q4 register W Data W Decode Read Process Write to register ‘f’ Data destination Example 1: DAW Before Instruction W = A5h Example: DECF CNT, 1, 0 C = 0 Before Instruction DC = 0 CNT = 01h After Instruction Z = 0 W = 05h After Instruction C = 1 DC = 0 CNT = 00h Z = 1 Example 2: Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS39663F-page 312 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, Operation: (f) – 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’. placed back in register ‘f’. If the result is ‘0’, the next instruction If the result is not ‘0’, the next which is already fetched is discarded instruction which is already fetched is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing Section25.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Bit-Oriented Instructions in Indexed Section25.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT ≠ 0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP ≠ 0; PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39663F-page 313
PIC18F87J10 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0 ≤ k ≤ 1048575 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k → PC<20:1> a ∈ [0,1] Status Affected: None Operation: (f) + 1 → dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire 2-Mbyte memory incremented. If ‘d’ is ‘0’, the result is range. The 20-bit value ‘k’ is loaded into placed in W. If ‘d’ is ‘1’, the result is PC<20:1>. GOTO is always a two-cycle placed back in register ‘f’. instruction. If ‘a’ is ‘0’, the Access Bank is selected. Words: 2 If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Cycles: 2 If ‘a’ is ‘0’ and the extended instruction Q Cycle Activity: set is enabled, this instruction operates Q1 Q2 Q3 Q4 in Indexed Literal Offset Addressing Decode Read literal No Read literal mode whenever f ≤ 95 (5Fh). See ‘k’<7:0>, operation ‘k’<19:8>, Section25.2.3 “Byte-Oriented and Write to PC Bit-Oriented Instructions in Indexed No No No No Literal Offset Mode” for details. operation operation operation operation Words: 1 Cycles: 1 Example: GOTO THERE Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 PC = Address (THERE) Decode Read Process Write to register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS39663F-page 314 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, Operation: (f) + 1 → dest, skip if result ≠ 0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’. placed back in register ‘f’. If the result is not ‘0’, the next If the result is ‘0’, the next instruction instruction which is already fetched is which is already fetched is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG ≠ 0; PC = Address (ZERO) PC = Address (NZERO) If CNT ≠ 0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) © 2009 Microchip Technology Inc. DS39663F-page 315
PIC18F87J10 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) .OR. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) .OR. (f) → dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. Q Cycle Activity: If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data W set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: IORLW 35h mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = 9Ah Literal Offset Mode” for details. After Instruction W = BFh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS39663F-page 316 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0 ≤ f ≤ 2 Operands: 0 ≤ f ≤ 255 0 ≤ k ≤ 4095 d ∈ [0,1] a ∈ [0,1] Operation: k → FSRf Operation: f → dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to file select register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’. Location ‘f’ Q Cycle Activity: can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 Decode Read literal Process Write If ‘a’ is ‘0’, the Access Bank is selected. ‘k’ MSB Data literal ‘k’ If ‘a’ is ‘1’, the BSR is used to select the MSB to GPR bank. FSRfH If ‘a’ is ‘0’ and the extended instruction Decode Read literal Process Write literal set is enabled, this instruction operates ‘k’ LSB Data ‘k’ to FSRfL in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Example: LFSR 2, 3ABh Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. FSR2H = 03h FSR2L = ABh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data W Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h © 2009 Microchip Technology Inc. DS39663F-page 317
PIC18F87J10 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0 ≤ f ≤ 4095 Operands: 0 ≤ k ≤ 255 s 0 ≤ f ≤ 4095 d Operation: k → BSR Operation: (f ) → f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffff s Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffff d of BSR<7:4> always remains ‘0’ Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Decode Read Process Write literal Either source or destination can be W literal ‘k’ Data ‘k’ to BSR (a useful special situation). MOVFF is particularly useful for Example: MOVLB 5 transferring a data memory location to a peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h After Instruction The MOVFF instruction cannot use the BSR Register = 05h PCL, TOSU, TOSH or TOSL as the destination register Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS39663F-page 318 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: k → W Operation: (W) → f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank. literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: MOVLW 5Ah in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See After Instruction Section25.2.3 “Byte-Oriented and W = 5Ah Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh © 2009 Microchip Technology Inc. DS39663F-page 319
PIC18F87J10 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x k → PRODH:PRODL Operation: (W) x (f) → PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried out 8-bit literal ‘k’. The 16-bit result is between the contents of W and the placed in PRODH:PRODL register pair. register file location ‘f’. The 16-bit result is PRODH contains the high byte. stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W is unchanged. W and ‘f’ are unchanged. None of the Status flags are affected. None of the Status flags are affected. Note that neither Overflow nor Carry is Note that neither Overflow nor Carry is possible in this operation. A Zero result possible in this operation. A Zero result is is possible but not detected. possible but not detected. Words: 1 If ‘a’ is ‘0’, the Access Bank is selected. If Cycles: 1 ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set Decode Read Process Write is enabled, this instruction operates in literal ‘k’ Data registers Indexed Literal Offset Addressing mode PRODH: whenever f ≤ 95 (5Fh). See PRODL Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: MULLW 0C4h Words: 1 Before Instruction W = E2h Cycles: 1 PRODH = ? Q Cycle Activity: PRODL = ? Q1 Q2 Q3 Q4 After Instruction W = E2h Decode Read Process Write PRODH = ADh register ‘f’ Data registers PRODL = 08h PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS39663F-page 320 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: No operation Operation: (f) + 1 → f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] © 2009 Microchip Technology Inc. DS39663F-page 321
PIC18F87J10 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC + 2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS39663F-page 322 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n → PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC + 2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC + 2 + 2n. This instruction is a Decode Start No No two-cycle instruction. reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Flags* = Reset Value Decode Read literal Process Write to PC ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2) © 2009 Microchip Technology Inc. DS39663F-page 323
PIC18F87J10 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, Operation: k → W, 1 → GIE/GIEH or PEIE/GIEL; (TOS) → PC, if s = 1, PCLATU, PCLATH are unchanged (WS) → W, Status Affected: None (STATUSS) → STATUS, (BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers WS, Q1 Q2 Q3 Q4 STATUSS and BSRS are loaded into Decode Read Process POP PC their corresponding registers W, literal ‘k’ Data from stack, STATUS and BSR. If ‘s’ = 0, no update write to W of these registers occurs. No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS RETLW kn ; End of table W = WS BSR = BSRS STATUS = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn DS39663F-page 324 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (TOS) → PC; a ∈ [0,1] if s = 1, (WS) → W, Operation: (f<n>) → dest<n + 1>, (STATUSS) → STATUS, (f<7>) → C, (BSRS) → BSR, (C) → dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry flag. popped and the top of the stack (TOS) If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is loaded into the program counter. If is ‘1’, the result is stored back in register ‘s’= 1, the contents of the shadow ‘f’. registers WS, STATUSS and BSRS are If ‘a’ is ‘0’, the Access Bank is selected. loaded into their corresponding If ‘a’ is ‘1’, the BSR is used to select the registers W, STATUS and BSR. If GPR bank. ‘s’ = 0, no update of these registers occurs. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 2 mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Q Cycle Activity: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 © 2009 Microchip Technology Inc. DS39663F-page 325
PIC18F87J10 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n + 1>, Operation: (f<n>) → dest<n – 1>, (f<7>) → dest<0> (f<0>) → C, (C) → dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’. flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘0’, the Access Bank is selected. register ‘f’. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank. set is enabled, this instruction operates in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f ≤ 95 (5Fh). See set is enabled, this instruction operates Section25.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f ≤ 95 (5Fh). See Literal Offset Mode” for details. Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39663F-page 326 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: FFh → f Operation: (f<n>) → dest<n – 1>, Status Affected: None (f<0>) → dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank. placed back in register ‘f’. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f ≤ 95 (5Fh). See per the BSR value. Section25.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 © 2009 Microchip Technology Inc. DS39663F-page 327
PIC18F87J10 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: 00h → WDT, a ∈ [0,1] 0 → WDT postscaler, 1 → TO, Operation: (W) – (f) – (C) → dest 0 → PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored in is set. The Watchdog Timer and its W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’. The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is selected. If with the oscillator stopped. ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction operates in Q Cycle Activity: Indexed Literal Offset Addressing mode Q1 Q2 Q3 Q4 whenever f ≤ 95 (5Fh). See Decode No Process Go to Section25.2.3 “Byte-Oriented and operation Data Sleep Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to TO = 1 † register ‘f’ Data destination PD = 0 Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39663F-page 328 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k – (W) → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) → dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the result Q Cycle Activity: is stored back in register ‘f’. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read Process Write to If ‘a’ is ‘1’, the BSR is used to select the literal ‘k’ Data W GPR bank. If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction operates Before Instruction in Indexed Literal Offset Addressing W = 01h mode whenever f ≤ 95 (5Fh). See C = ? Section25.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 01h Literal Offset Mode” for details. C = 1 ; result is positive Z = 0 Words: 1 N = 0 Cycles: 1 Example 2: SUBLW 02h Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 W = 02h C = ? Decode Read Process Write to After Instruction register ‘f’ Data destination W = 00h C = 1 ; result is zero Example 1: SUBWF REG, 1, 0 Z = 1 Before Instruction N = 0 REG = 3 W = 2 Example 3: SUBLW 02h C = ? Before Instruction After Instruction W = 03h REG = 1 C = ? W = 2 After Instruction C = 1 ; result is positive W = FFh ; (2’s complement) Z = 0 C = 0 ; result is negative N = 0 Z = 0 Example 2: SUBWF REG, 0, 0 N = 1 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 © 2009 Microchip Technology Inc. DS39663F-page 329
PIC18F87J10 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>) → dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored Description: The upper and lower nibbles of register in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’. is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing Section25.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) REG = 35h C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39663F-page 330 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR)) → TABLAT, MEMORY(00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR)) → TABLAT, TBLPTR = 00A357h (TBLPTR) + 1 → TBLPTR; Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, Before Instruction (TBLPTR) – 1 → TBLPTR; TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY(01A357h) = 12h (TBLPTR) + 1 → TBLPTR, MEMORY(01A358h) = 34h (Prog Mem (TBLPTR)) → TABLAT After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write Memory) TABLAT) © 2009 Microchip Technology Inc. DS39663F-page 331
PIC18F87J10 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT) → Holding Register, TBLPTR = 00A356h HOLDING REGISTER TBLPTR – No Change; (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT) → Holding Register, TABLAT = 55h (TBLPTR) + 1 → TBLPTR; TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT) → Holding Register, (00A356h) = 55h (TBLPTR) – 1 → TBLPTR; Example 2: TBLWT +*; if TBLWT+*, Before Instruction (TBLPTR) + 1 → TBLPTR, TABLAT = 34h (TABLAT) → Holding Register TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER 8 holding registers the TABLAT is written (01389Bh) = 34h to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section6.0 “Memory Organization” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register) DS39663F-page 332 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 a ∈ [0,1] Operation: (W) .XOR. k → W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to set is enabled, this instruction operates literal ‘k’ Data W in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: XORLW 0AFh Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Before Instruction Literal Offset Mode” for details. W = B5h After Instruction Words: 1 W = 1Ah Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT ≠ 00h, PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39663F-page 333
PIC18F87J10 FAMILY XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS39663F-page 334 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 25.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table25-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section25.2.2 “Extended Instruction instruction set, the PIC18F87J10 family of devices also Set”. The opcode field descriptions in Table25-1 (page provide an optional extension to the core CPU function- 294) apply to both the standard and extended PIC18 ality. The added features include eight additional instruction sets. instructions that augment Indirect and Indexed Addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction set these instructions directly in assembler. are disabled by default on unprogrammed devices. The syntax for these commands is Users must properly set or clear the XINST Configura- provided as a reference for users who may tion bit during programming to enable or disable these be reviewing code that has been features. generated by a compiler. The instructions in the extended set can all be classified as literal operations, which either manipulate 25.2.1 EXTENDED INSTRUCTION SYNTAX the File Select Registers, or use them for Indexed Most of the extended instructions use indexed argu- Addressing. Two of the instructions, ADDFSR and ments, using one of the File Select Registers and some SUBFSR, each have an additional special instantiation offset to specify a source or destination register. When for using FSR2. These versions (ADDULNK and an argument for an instruction serves as part of SUBULNK) allow for automatic return after execution. Indexed Addressing, it is enclosed in square brackets The extended instructions are specifically implemented (“[ ]”). This is done to indicate that the argument is used to optimize re-entrant program code (that is, code that as an index or offset. The MPASM™ Assembler will is recursive or that uses a software stack) written in flag an error if it determines that an index or offset value high-level languages, particularly C. Among other is not bracketed. things, they allow users working in high-level When the extended instruction set is enabled, brackets languages to perform certain operations on data are also used to indicate index arguments in structures more efficiently. These include: byte-oriented and bit-oriented instructions. This is in • dynamic allocation and deallocation of software addition to other changes in their syntax. For more stack space when entering and leaving details, see Section25.2.3.1 “Extended Instruction subroutines Syntax with Standard PIC18 Commands”. • function pointer invocation Note: In the past, square brackets have been • software Stack Pointer manipulation used to denote optional arguments in the • manipulation of variables located in a software PIC18 and earlier instruction sets. In this stack text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 25-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None Decrement FSR2 SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None Return © 2009 Microchip Technology Inc. DS39663F-page 335
PIC18F87J10 FAMILY 25.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2, Operation: FSR(f) + k → FSR(f) (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. Q Cycle Activity: The instruction takes two cycles to Q1 Q2 Q3 Q4 execute; a NOP is performed during the second cycle. Decode Read Process Write to literal ‘k’ Data FSR This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates Example: ADDFSR 2, 23h only on FSR2. Before Instruction Words: 1 FSR2 = 03FFh Cycles: 2 After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS39663F-page 336 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY CALLW Subroutine Call using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0 ≤ z ≤ 127 s 0 ≤ f ≤ 4095 Operation: (PC + 2) → TOS, d (W) → PCL, Operation: ((FSR2) + z ) → f s d (PCLATH) → PCH, Status Affected: None (PCLATU) → PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffff d Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’, in the first word, to the value s latched into PCH and PCU, of FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘fd’ in the second word. Both addresses new next instruction is fetched. can be anywhere in the 4096-byte data space (000h to FFFh). Unlike CALL, there is no option to update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an Indirect Addressing register, the Q1 Q2 Q3 Q4 value returned will be 00h. Decode Read Push PC to No Words: 2 WREG stack operation Cycles: 2 No No No No operation operation operation operation Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Before Instruction Decode No No Write PC = address (HERE) operation operation register ‘f’ PCLATH = 10h No dummy (dest) PCLATU = 00h W = 06h read After Instruction PC = 001006h TOS = address (HERE + 2) Example: MOVSF [05h], REG2 PCLATH = 10h PCLATU = 00h Before Instruction W = 06h FSR2 = 80h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h © 2009 Microchip Technology Inc. DS39663F-page 337
PIC18F87J10 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255 0 ≤ z ≤ 127 d Operation: k → (FSR2), Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1 → FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1111 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. Description The contents of the source register are FSR2 is decremented by 1 after the moved to the destination register. The operation. addresses of the source and destination registers are determined by adding the This instruction allows users to push 7-bit literal offsets ‘z ’ or ‘z ’, values onto a software stack. s d respectively, to the value of FSR2. Both Words: 1 registers can be located anywhere in the 4096-byte data memory space Cycles: 1 (000h to FFFh). Q Cycle Activity: The MOVSS instruction cannot use the Q1 Q2 Q3 Q4 PCL, TOSU, TOSH or TOSL as the Decode Read ‘k’ Process Write to destination register. data destination If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. If the Example: PUSHL 08h resultant destination address points to Before Instruction an Indirect Addressing register, the FSR2H:FSR2L = 01ECh instruction will execute as a NOP. Memory (01ECh) = 00h Words: 2 After Instruction Cycles: 2 FSR2H:FSR2L = 01EBh Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS39663F-page 338 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2, Operation: FSRf – k → FSRf (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified contents of the FSR2. A RETURN is then by ‘f’. executed by loading the PC with the Words: 1 TOS. Cycles: 1 The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during the second cycle. Q1 Q2 Q3 Q4 Decode Read Process Write to This may be thought of as a special case register ‘f’ Data destination of the SUBFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Words: 1 Example: SUBFSR 2, 23h Cycles: 2 Before Instruction Q Cycle Activity: FSR2 = 03FFh Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to FSR2 = 03DCh register ‘f’ Data destination No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) © 2009 Microchip Technology Inc. DS39663F-page 339
PIC18F87J10 FAMILY 25.2.3 BYTE-ORIENTED AND 25.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file Note: Enabling the PIC18 instruction set exten- register argument ‘f’ in the standard byte-oriented and sion may cause legacy applications to bit-oriented commands is replaced with the literal offset behave erratically or fail entirely. value ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing (Section6.6.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within the brackets, will the standard PIC18 instruction set are interpreted. generate an error in the MPASM Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is either as a location in the Access Bank (a = 0) or in a never specified; it will automatically be assumed to be GPR bank designated by the BSR (a = 1). When the ‘0’. This is in contrast to standard operation (extended extended instruction set is enabled and a = 0, however, instruction set disabled), when ‘a’ is set on the basis of a file register argument of 5Fh or less is interpreted as the target address. Declaring the Access RAM bit in an offset from the pointer value in FSR2 and not as a this mode will also generate an error in the MPASM literal address. For practical purposes, this means that Assembler. all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bit-oriented The destination argument ‘d’ functions as before. instructions, or almost half of the core PIC18 instruc- In the latest versions of the MPASM Assembler, tions – may behave differently when the extended language support for the extended instruction set must instruction set is enabled. be explicitly invoked. This is done with either the When the content of FSR2 is 00h, the boundaries of the command line option, /y, or the PE directive in the Access RAM are essentially remapped to their original source listing. values. This may be useful in creating 25.2.4 CONSIDERATIONS WHEN backward-compatible code. If this technique is used, it ENABLING THE EXTENDED may be necessary to save the value of FSR2 and INSTRUCTION SET restore it when moving back and forth between C and assembly routines in order to preserve the Stack It is important to note that the extensions to the instruc- Pointer. Users must also keep in mind the syntax tion set may not be beneficial to all users. In particular, requirements of the extended instruction set (see users who are not writing code that uses a software Section25.2.3.1 “Extended Instruction Syntax with stack may not benefit from using the extensions to the Standard PIC18 Commands”). instruction set. Although the Indexed Literal Offset mode can be very Additionally, the Indexed Literal Offset Addressing useful for dynamic stack and pointer manipulation, it mode may create issues with legacy applications can also be very annoying if a simple arithmetic opera- written to the PIC18 assembler. This is because tion is carried out on the wrong register. Users who are instructions in the legacy code may attempt to address accustomed to the PIC18 programming must keep in registers in the Access Bank below 5Fh. Since these mind that, when the extended instruction set is addresses are interpreted as literal offsets to FSR2 enabled, register addresses of 5Fh or less are used for when the instruction set extension is enabled, the Indexed Literal Offset Addressing. application may read or write to the wrong data Representative examples of typical byte-oriented and addresses. bit-oriented instructions in the Indexed Literal Offset When porting an application to the PIC18F87J10 mode are provided on the following page to show how family, it is very important to consider the type of code. execution is affected. The operand conditions shown in A large, re-entrant application that is written in C and the examples are applicable to all instructions of these would benefit from efficient compilation will do well types. when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39663F-page 340 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 Operands: 0 ≤ f ≤ 95 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ Cycles: 1 is ‘1’, the result is stored back in register ‘f’. Q Cycle Activity: Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1 register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Contents Example: ADDWF [OFST],0 of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction Set Indexed SETF W = 37h (Indexed Literal Offset mode) Contents of 0A2Ch = 20h Syntax: SETF [k] Operands: 0 ≤ k ≤ 95 Operation: FFh → ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh © 2009 Microchip Technology Inc. DS39663F-page 341
PIC18F87J10 FAMILY 25.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set for the PIC18F87J10 family. This includes the • A menu option or dialog box within the MPLAB C18 C Compiler, MPASM assembly language environment that allows the user to configure the and MPLAB Integrated Development Environment language tool and its settings for the project (IDE). • A command line option When selecting a target device for software • A directive in the source code development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for These options vary between different compilers, the XINST Configuration bit is ‘0’, disabling the assemblers and development environments. Users are extended instruction set and Indexed Literal Offset encouraged to review the documentation accompany- Addressing. For proper execution of applications ing their development systems for the appropriate developed to take advantage of the extended instruc- information. tion set, XINST must be set during programming. DS39663F-page 342 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 26.0 DEVELOPMENT SUPPORT 26.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- • Integrated Development Environment controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software operating system-based application that contains: • Assemblers/Compilers/Linkers • A single graphical interface to all debugging tools - MPASMTM Assembler - Simulator - MPLAB C18 and MPLAB C30 C Compilers - Programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) • Simulators • A full-featured editor with color-coded context - MPLAB SIM Software Simulator • A multiple project manager • Emulators • Customizable data windows with direct edit of contents - MPLAB ICE 2000 In-Circuit Emulator • High-level source code debugging - MPLAB REAL ICE™ In-Circuit Emulator • Visual device initializer for easy register • In-Circuit Debugger initialization - MPLAB ICD 2 • Mouse over variable inspection • Device Programmers • Drag and drop variables from source to watch - PICSTART® Plus Development Programmer windows - MPLAB PM3 Device Programmer • Extensive on-line help - PICkit™ 2 Development Programmer • Integration of select third party tools, such as • Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR Boards and Evaluation Kits C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2009 Microchip Technology Inc. DS39663F-page 343
PIC18F87J10 FAMILY 26.2 MPASM Assembler 26.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: • Support for the entire dsPIC30F instruction set • Integration into MPLAB IDE projects • Support for fixed-point and floating-point data • User-defined macros to streamline • Command line interface assembly code • Rich directive set • Conditional assembly for multi-purpose source files • Flexible macro language • Directives that allow complete control over the • MPLAB IDE compatibility assembly process 26.6 MPLAB SIM Software Simulator 26.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulat- ing the PIC MCUs and dsPIC® DSCs on an instruction The MPLAB C18 and MPLAB C30 Code Development level. On any given instruction, the data areas can be Systems are complete ANSI C compilers for examined or modified and stimuli can be applied from Microchip’s PIC18 and PIC24 families of microcon- a comprehensive stimulus controller. Registers can be trollers and the dsPIC30 and dsPIC33 family of digital logged to files for further run-time analysis. The trace signal controllers. These compilers provide powerful buffer and logic analyzer display extend the power of integration capabilities, superior code optimization and the simulator to record and track program execution, ease of use not found with other compilers. actions on I/O, most peripherals and internal registers. For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and debugger. MPLAB C30 CCompilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator 26.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside MPLIB Object Librarian of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS39663F-page 344 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 26.7 MPLAB ICE 2000 26.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes microcontrollers. Software control of the MPLAB ICE the in-circuit debugging capability built into theFlash 2000 In-Circuit Emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers cost- editing, building, downloading and source debugging effective, in-circuit Flash debugging from the graphical from a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step- ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB ICE 2000 In-Circuit Emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 26.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for simple, unified application. maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various 26.8 MPLAB REAL ICE In-Circuit package types. The ICSP™ cable assembly is included Emulator System as a standard item. In Stand-Alone mode, the MPLAB MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set Microchip Flash DSC and MCU devices. It debugs and code protection in this mode. The MPLAB PM3 programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable. with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large included with each kit. memory devices and incorporates an SD/MMC card for file storage and secure data applications. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, Low- Voltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2009 Microchip Technology Inc. DS39663F-page 345
PIC18F87J10 FAMILY 26.11 PICSTART Plus Development 26.13 Demonstration, Development and Programmer Evaluation Boards The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func- Integrated Development Environment software makes tional systems. Most boards include prototyping areas for using the programmer simple and efficient. The adding custom circuitry and provide application firmware PICSTART Plus Development Programmer supports and source code for examination and modification. most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs, Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232 PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional The PICSTART Plus Development Programmer is CE EEPROM memory. compliant. The demonstration and development boards can be used in teaching environments, for prototyping custom 26.12 PICkit 2 Development Programmer circuits and for learning about various microcontroller The PICkit™ 2 Development Programmer is a low-cost applications. programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ demon- an easy-to-use interface for programming many of stration/development board series of circuits, Microchip Microchip’s baseline, mid-range and PIC18F families of has a line of evaluation kits and demonstration software Flash memory microcontrollers. The PICkit 2 Starter Kit for analog filter design, KEELOQ® security ICs, CAN, includes a prototyping development board, twelve IrDA®, PowerSmart battery management, SEEVAL® sequential lessons, software and HI-TECH’s PICC™ evaluation system, Sigma-Delta ADC, flow rate Lite C compiler, and is designed to help get up to speed sensing, plus many more. quickly using PIC® microcontrollers. The kit provides Check the Microchip web page (www.microchip.com) everything needed to program, evaluate and develop for the complete list of demonstration, development applications using Microchip’s powerful, mid-range and evaluation kits. Flash memory family of microcontrollers. DS39663F-page 346 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD)...........................................-0.3V to 6.0V Voltage on any combined digital and analog pin with respect to VSS (except VDD)........................-0.3V to (VDD + 0.3V) Voltage on VDDCORE with respect to VSS...................................................................................................-0.3V to 2.75V Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 3.6V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Maximum output current sunk by any PORTB and PORTC I/O pin........................................................................25mA Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pin............................................................8mA Maximum output current sunk by any PORTA, PORTF, PORTG and PORTH I/O pin.............................................4mA Maximum output current sourced by any PORTB and PORTC I/O pin..................................................................25mA Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pin.......................................................8mA Maximum output current sourced by any PORTA, PORTF, PORTG and PORTH I/O pin........................................4mA Maximum current sunk by all ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS39663F-page 347
PIC18F87J10 FAMILY FIGURE 27-1: PIC18F87J10 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (INDUSTRIAL) 3.00V 2.75V 2.7V 1) ()E 2.50V PIC18F6XJ10/6XJ15/8XJ10/8XJ15 R O 2.35V C 2.25V D D V ( e 2.00V g a t ol V 4 MHz 40 MHz Frequency For VDDCORE values, 2V to 2.35V, FMAX = (102.85 MHz/V) * (VDDCORE – 2V) + 4 MHz Note 1: For devices without the voltage regulator, VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD ≤ 3.6V. DS39663F-page 348 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 27-2: PIC18F87J10 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (INDUSTRIAL) 4.0V 3.6V 3.5V ) PIC18F6XJ10/6XJ15/8XJ10/8XJ15 D D 3.0V 2.7V V ( e 2.5V g a t l o V 4 MHz 40 MHz Frequency • FMAX = 25 MHz in 8-bit External Memory mode. • FMAX = 40 MHz in all other modes for VDD > 2.35V. © 2009 Microchip Technology Inc. DS39663F-page 349
PIC18F87J10 FAMILY 27.1 DC Characteristics: Supply Voltage, PIC18F87J10 Family (Industrial) PIC18F87J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage VDDCORE — 3.6 V ENVREG = 0 2.7 — 3.6 V ENVREG = 1 D001B VDDCORE External Supply for 2.0 — 2.7 V ENVREG = 0 Microcontroller Core D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V D001D AVSS Analog Ground Voltage VSS – 0.3 — VSS + 0.3 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.15 V See Section5.3 “Power-on to ensure Internal Reset (POR)” for details Power-on Reset Signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section5.3 “Power-on to Ensure Internal Reset (POR)” for details Power-on Reset Signal D005 VBOR Brown-out Reset (BOR) 2.35 2.5 2.7 V Voltage Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. DS39663F-page 350 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F87J10 Family (Industrial) PIC18F87J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) All devices 27 69 μA -40°C VDD = 2.0V(5) 43 69 μA +25°C (Sleep mode) 121 149 μA +85°C All devices 49 104 μA -40°C VDD = 2.5V(5) 69 104 μA +25°C (Sleep mode) 166 184 μA +85°C All devices 75 203 μA -40°C VDD = 3.3V(6) 100 203 μA +25°C (Sleep mode) 140 289 μA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: ENVREG tied to VSS, voltage regulator disabled. 6: ENVREG tied to VDD, voltage regulator enabled. © 2009 Microchip Technology Inc. DS39663F-page 351
PIC18F87J10 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) PIC18F87J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) All devices 1.8 3.27 mA -40°C 1.8 3.27 mA +25°C VDD = 2.0V 1.9 3.27 mA +85°C All devices 4.0 5.57 mA -40°C FOSC = 31kHz 3.7 5.57 mA +25°C VDD = 2.5V (RC_RUN mode, 3.5 5.57 mA +85°C internal oscillator source) All devices 4.0 5.97 mA -40°C 3.8 5.97 mA +25°C VDD = 3.3V 3.7 5.97 mA +85°C All devices 1.8 3.27 mA -40°C 1.8 3.27 mA +25°C VDD = 2.0V 1.9 3.27 mA +85°C All devices 4.0 5.57 mA -40°C FOSC = 31kHz 3.7 5.57 mA +25°C VDD = 2.5V (RC_IDLE mode, 3.5 5.57 mA +85°C internal oscillator source) All devices 4.0 5.97 mA -40°C 3.8 5.97 mA +25°C VDD = 3.3V 3.7 5.97 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: ENVREG tied to VSS, voltage regulator disabled. 6: ENVREG tied to VDD, voltage regulator enabled. DS39663F-page 352 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) PIC18F87J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) All devices 1.8 3.27 mA -40°C 1.8 3.27 mA +25°C VDD = 2.0V(5) 1.9 3.27 mA +85°C All devices 4.0 5.57 mA -40°C FOSC = 1MHZ 3.7 5.57 mA +25°C VDD = 2.5V(5) (PRI_RUN mode, 3.5 5.57 mA +85°C EC oscillator) All devices 4.0 5.97 mA -40°C 3.8 5.97 mA +25°C VDD = 3.3V(6) 3.7 5.97 mA +85°C All devices 2.4 4.47 mA -40°C 2.4 4.47 mA +25°C VDD = 2.0V(5) 2.5 4.47 mA +85°C All devices 4.7 6.97 mA -40°C FOSC = 4MHz 4.4 6.97 mA +25°C VDD = 2.5V(5) (PRI_RUN mode, 4.3 6.97 mA +85°C EC oscillator) All devices 5.1 7.47 mA -40°C 4.9 7.47 mA +25°C VDD = 3.3V(6) 4.7 7.47 mA +85°C All devices 13.4 18.7 mA -40°C 13.0 18.7 mA +25°C VDD = 2.5V(5) 13.0 18.7 mA +85°C FOSC = 40MHZ (PRI_RUN mode, All devices 14.5 19.7 mA -40°C EC oscillator) 14.4 19.7 mA +25°C VDD = 3.3V(6) 14.5 19.7 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: ENVREG tied to VSS, voltage regulator disabled. 6: ENVREG tied to VDD, voltage regulator enabled. © 2009 Microchip Technology Inc. DS39663F-page 353
PIC18F87J10 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) PIC18F87J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 7.2 12.1 mA -40°C FOSC = 4MHZ, 6.8 12.1 mA +25°C VDD = 2.5V(5) 16 MHz internal 6.9 12.1 mA +85°C (PRI_RUN HSPLL mode) All devices 7.6 13.1 mA -40°C FOSC = 4MHZ, 7.5 13.1 mA +25°C VDD = 3.3V(6) 16 MHz internal 7.3 13.1 mA +85°C (PRI_RUN HSPLL mode) All devices 10.9 18.7 mA -40°C FOSC = 10MHZ, 10.6 18.7 mA +25°C VDD = 2.5V(5) 40 MHz internal 10.3 18.7 mA +85°C (PRI_RUN HSPLL mode) All devices 11.9 19.7 mA -40°C FOSC = 10MHZ, 11.8 19.7 mA +25°C VDD = 3.3V(6) 40 MHz internal 11.7 19.7 mA +85°C (PRI_RUN HSPLL mode) Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: ENVREG tied to VSS, voltage regulator disabled. 6: ENVREG tied to VDD, voltage regulator enabled. DS39663F-page 354 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) PIC18F87J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) All devices 1.8 3.27 mA -40°C 1.8 3.27 mA +25°C VDD = 2.0V(5) 1.9 3.27 mA +85°C All devices 4.0 5.57 mA -40°C FOSC = 1MHz 3.7 5.57 mA +25°C VDD = 2.5V(5) (PRI_IDLE mode, 3.5 5.57 mA +85°C EC oscillator) All devices 4.2 5.97 mA -40°C 4.0 5.97 mA +25°C VDD = 3.3V(6) 3.8 5.97 mA +85°C All devices 2.4 4.47 mA -40°C 2.4 4.47 mA +25°C VDD = 2.0V(5) 2.5 4.47 mA +85°C All devices 4.7 6.97 mA -40°C FOSC = 4MHz 4.4 6.97 mA +25°C VDD = 2.5V(5) (PRI_IDLE mode, 4.8 6.97 mA +85°C EC oscillator) All devices 5.1 7.47 mA -40°C 4.9 7.47 mA +25°C VDD = 3.3V(6) 4.8 7.47 mA +85°C All devices 13.4 18.7 mA -40°C 13.0 18.7 mA +25°C VDD = 2.5V(5) 13.0 18.7 mA +85°C FOSC = 40MHz (PRI_IDLE mode, All devices 14.8 19.7 mA -40°C EC oscillator) 14.4 19.7 mA +25°C VDD = 3.3V(6) 14.5 19.7 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: ENVREG tied to VSS, voltage regulator disabled. 6: ENVREG tied to VDD, voltage regulator enabled. © 2009 Microchip Technology Inc. DS39663F-page 355
PIC18F87J10 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) PIC18F87J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) All devices 1.8 3.27 mA -10°C 1.8 3.27 mA +25°C VDD = 2.0V(5) 1.9 3.27 mA +70°C All devices 4.0 5.57 mA -10°C FOSC = 32kHz(4) 3.7 5.57 mA +25°C VDD = 2.5V(5) (SEC_RUN mode, 3.5 5.57 mA +70°C Timer1 as clock) All devices 4.2 5.97 mA -10°C 4.0 5.97 mA +25°C VDD = 3.3V(6) 3.8 5.97 mA +70°C All devices 1.8 3.27 mA -10°C 1.8 3.27 mA +25°C VDD = 2.0V(5) 1.9 3.27 mA +70°C All devices 4.0 5.57 mA -10°C FOSC = 32kHz(4) 3.7 5.57 mA +25°C VDD = 2.5V(5) (SEC_IDLE mode, 3.5 5.57 mA +70°C Timer1 as clock) All devices 4.2 5.97 mA -10°C 4.0 5.97 mA +25°C VDD = 3.3V(6) 3.8 5.97 mA +70°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: ENVREG tied to VSS, voltage regulator disabled. 6: ENVREG tied to VDD, voltage regulator enabled. DS39663F-page 356 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) PIC18F87J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Module Differential Currents (ΔIWDT, ΔIOSCB, ΔIAD) D022 Watchdog Timer 1.9 4.5 μA -40°C (ΔIWDT) 1.9 5.1 μA +25°C VDD = 2.0V 1.3 5.1 μA +85°C 2.7 5.4 μA -40°C 2.75 6.0 μA +25°C VDD = 2.5V 1.7 6.0 μA +85°C 1.3 10.5 μA -40°C 2.1 10.5 μA +25°C VDD = 3.3V 2.0 10.5 μA +85°C D025 Timer1 Oscillator 8.1 18.5 μA -40°C (ΔIOSCB) 10.8 19.1 μA +25°C VDD = 2.0V 32kHz on Timer1(3) 13.9 19.1 μA +85°C 8.2 18.5 μA -40°C 11.0 19.1 μA +25°C VDD = 2.5V 32kHz on Timer1(3) 13.9 19.1 μA +85°C 7.9 19.1 μA -40°C 10.7 19.1 μA +25°C VDD = 3.3V 32kHz on Timer1(3) 13.5 19.1 μA +85°C D026 A/D Converter 1.2 10.9 μA -40°C to +85°C VDD = 2.0V (ΔIAD) 1.2 11.4 μA -40°C to +85°C VDD = 2.5V A/D on, not converting 1.2 11.9 μA -40°C to +85°C VDD = 3.3V Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 5: ENVREG tied to VSS, voltage regulator disabled. 6: ENVREG tied to VDD, voltage regulator enabled. © 2009 Microchip Technology Inc. DS39663F-page 357
PIC18F87J10 FAMILY 27.3 DC Characteristics: PIC18F87J10 Family (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage All I/O Ports: D030 with TTL buffer VSS 0.15 VDD V VDD < 3.3V D030A — 0.8 V 3.3V ≤ VDD ≤ 3.6V D031 with Schmitt Trigger Buffer VSS 0.2 VDD V D031A RC3 and RC4 VSS 0.3 VDD V I2C™ enabled D031B VSS 0.8 V SMBus enabled D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V EC, ECPLL modes(1) D034 T1CKI VSS 0.3 V VIH Input High Voltage I/O Ports with non 5.5V Tolerance:(4) D040 with TTL Buffer 0.25 VDD + 0.8V VDD V VDD < 3.3V D040A 2.0 VDD V 3.3V ≤ VDD ≤ 3.6V D041 with Schmitt Trigger Buffer 0.8 VDD VDD V I/O Ports with 5.5V Tolerance:(4) D041A RC3 and RC4 0.7 VDD VDD V I2C enabled D041B 2.1 VDD V SMBus enabled Dxxx with TTL Buffer 0.25 VDD + 0.8V 5.5 V VDD < 3.3V DxxxA 2.0 5.5 V 3.3V ≤ VDD ≤ 3.6V Dxxx with Schmitt Trigger Buffer 0.8 VDD 5.5 V D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC, ECPLL modes D044 T1CKI 1.6 VDD V IIL Input Leakage Current(2,3) D060 I/O Ports with non 5.5V — ±1 μA VSS ≤ VPIN ≤ VDD, Tolerance:(4) Pin at high-impedance D060A I/O Ports with 5.5V — ±1 μA Vss ≤ VPIN ≤ 5.5V. Tolerance:(4) Pin at high-impedance D061 MCLR — ±1 μA Vss ≤ VPIN ≤ VDD D063 OSC1 — ±5 μA Vss ≤ VPIN ≤ VDD Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Refer to Table11-2 for the pins that have corresponding tolerance limits. DS39663F-page 358 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 27.3 DC Characteristics: PIC18F87J10 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. IPU Weak Pull-up Current D070 IPURB PORTB Weak Pull-up Current 30 240 μA VDD = 3.3V, VPIN = VSS VOL Output Low Voltage D080 I/O Ports (PORTB, PORTC) — 0.4 V IOL = 8.5 mA, VDD 3.3V I/O Ports (PORTD, PORTE, — 0.4 V IOL = 3.4 mA, VDD 3.3V PORTJ) I/O Ports (PORTA, PORTF, — 0.4 V IOL = 3.4 mA, VDD 3.3V PORTG, PORTH) D083 OSC2/CLKO — 0.4 V IOL = 1.0 mA, VDD 3.3V (EC, ECIO modes) VOH Output High Voltage(3) D090 I/O Ports (PORTB, PORTC) 2.4 — V IOL = -6 mA, VDD 3.3V I/O Ports (PORTD, PORTE, 2.4 — V IOL = -2 mA, VDD 3.3V PORTJ) I/O Ports (PORTA, PORTF, 2.4 — V IOL = -2 mA, VDD 3.3V PORTG, PORTH) D092 OSC2/CLKO 2.4 — V IOL = 1 mA, VDD 3.3V (EC, ECIO modes) Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 Pin — 15 pF In HS mode when external clock is used to drive OSC1 D101 CIO All I/O Pins — 50 pF To meet the AC Timing Specifications D102 CB SCLx, SDAx — 400 pF I2C™ Specification Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Refer to Table11-2 for the pins that have corresponding tolerance limits. © 2009 Microchip Technology Inc. DS39663F-page 359
PIC18F87J10 FAMILY TABLE 27-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym Characteristic Min Typ† Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 100 1K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132 VPEW Voltage for Self-Timed Erase or Write VDD 2.35 — 3.6 V ENVREG = 0 VDDCORE 2.25 — 2.7 V ENVREG = 1 D133A TIW Self-Timed Write Cycle Time — 2.8 — ms D133B TIE Self-Timed Page Erase Cycle — 33.0 — ms Time D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D135 IDDP Supply Current during — 10 — mA Programming D140 TWE Writes per Erase Cycle — — 1 For each physical address † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS39663F-page 360 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 27-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ±5.0 ±25 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB D303 TRESP Response Time(1) — 150 400 ns D304 TMC2OV Comparator Mode Change to — — 10 μs Output Valid D305 VIRV Internal Reference Voltage — 1.2 — V Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 27-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb D312 VRUR Unit Resistor Value (R) — 2k — Ω D313 TSET Settling Time(1) — — 10 μs Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. TABLE 27-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. VRGOUT Regulator Output Voltage — 2.5 — V CEFC External Filter Capacitor Value 4.7 10 — μF Capacitor must be low series resistance (<5 Ohms) © 2009 Microchip Technology Inc. DS39663F-page 361
PIC18F87J10 FAMILY 27.4 AC (Timing) Characteristics 27.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS39663F-page 362 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 27.4.2 TIMING CONDITIONS The temperature and voltages specified in Table27-5 apply to all timing specifications unless otherwise noted. Figure27-3 specifies the load conditions for the timing specifications. TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section27.1 and Section27.3. FIGURE 27-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports © 2009 Microchip Technology Inc. DS39663F-page 363
PIC18F87J10 FAMILY 27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-4: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 25 MHz HS Oscillator mode DC 40 MHz EC Oscillator mode DC 10 MHz HSPLL, ECPLL Oscillator modes Oscillator Frequency(1) 4 25 MHz HS Oscillator mode 4 10 MHz HS/EC + PLL Oscillator mode 1 TOSC External CLKI Period(1) 40 — ns HS Oscillator mode 25 — ns EC Oscillator mode Oscillator Period(1) 40 250 ns HS Oscillator mode 100 250 ns HS/EC + PLL Oscillator mode 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, Industrial 3 TOSL, External Clock in (OSC1) 10 — ns HS Oscillator mode TOSH High or Low Time 4 TOSR, External Clock in (OSC1) — 7.5 ns HS Oscillator mode TOSF Rise or Fall Time Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS39663F-page 364 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 3.6V) Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 10 MHz F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz F12 t PLL Start-up Time (Lock Time) — — 2 ms rc F13 ΔCLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 27-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F87J10 FAMILY (INDUSTRIAL) Param Characteristic Min Typ Max Units Conditions No. INTRC Accuracy @ Freq = 31 kHz(1) 21.88 — 40.63 kHz -40°C to +85°C, VDD = 2.0-3.3V Note 1: INTRC frequency after calibration. Change of INTRC frequency as VDD changes. © 2009 Microchip Technology Inc. DS39663F-page 365
PIC18F87J10 FAMILY FIGURE 27-5: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure27-3 for load conditions. TABLE 27-9: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1) 11 TOSH2CKH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1) 12 TCKR CLKO Rise Time — 15 30 ns (Note 1) 13 TCKF CLKO Fall Time — 15 30 ns (Note 1) 14 TCKL2IOV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns 15 TIOV2CKH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns 16 TCKH2IOI Port In Hold after CLKO ↑ 0 — — ns 17 TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1 ↑ (Q2 cycle) to Port Input Invalid 100 — — ns 18A (I/O in hold time) 200 — — ns VDD = 2.0V 19 TIOV2OSH Port Input Valid to OSC1 ↑ 0 — — ns (I/O in setup time) 20 TIOR Port Output Rise Time — — 6 ns 20A — — — — 21 TIOF Port Output Fall Time — — 5 ns 21A — — — — 22† TINP INTx Pin High or Low Time TCY — — ns 23† TRBP RB<7:4> Change INTx High or Low Time TCY — — ns Legend: TBD = To Be Determined † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. DS39663F-page 366 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 27-6: PROGRAM MEMORY FETCH TIMING DIAGRAM (8-BIT) Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:8> Address Address 167 166 150 161 151 AD<7:0> Address Data Data Address 162 153 162A 155 154 163 BA0 170 ALE 170A 168 CE OE TABLE 27-7: PROGRAM MEMORY FETCH TIMING REQUIREMENTS (8-BIT) Param Symbol Characteristics Min Typ Max Units No 150 TadV2aIL Address Out Valid to ALE ↓ (address setup time) 0.25 TCY – 10 — — ns 151 TaIL2adl ALE ↓ to Address Out Invalid (address hold time) 5 — — ns 153 BA01 BA0 ↑ to Most Significant Data Valid 0.125 TCY — — ns 154 BA02 BA0 ↓ to Least Significant Data Valid 0.125 TCY — — ns 155 TaIL2oeL ALE ↓ to OE ↓ 0.125 TCY — — ns 161 ToeH2adD OE ↑ to A/D Driven 0.125 TCY – 5 — — ns 162 TadV2oeH Least Significant Data Valid Before OE ↑ 20 — — ns (data setup time 162A TadV2oeH Most Significant Data Valid Before OE ↑ 0.25 TCY + 20 — — ns (data setup time) 163 ToeH2adI OE ↑ to Data in Invalid (data Hold Time) 0 — — ns 166 TaIH2aIH ALE ↑ to ALE ↑ (cycle time) — TCY — ns 167 TACC Address Valid to Data Valid 0.5 TCY – 10 — — ns 168 Toe OE ↓ to Data Valid — — 0.125 TCY + 5 ns 170 TubH2oeH BA0 = 0 Valid Before OE ↑ 0.25 TCY — — ns 170A TubL2oeH BA0 = 1 Valid Before OE ↑ 0.5 TCY — — ns © 2009 Microchip Technology Inc. DS39663F-page 367
PIC18F87J10 FAMILY FIGURE 27-8: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 AD<15:0> Address Data from External Address 150 160 163 151 162 161 155 166 167 168 ALE 164 169 171 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated. TABLE 27-10: CLKO AND I/O TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE ↓ 0.25 TCY – 10 — — ns (address setup time) 151 TalL2adl ALE ↓ to Address Out Invalid 5 — — ns (address hold time) 155 TalL2oeL ALE ↓ to OE ↓ 10 0.125 TCY — ns 160 TadZ2oeL AD High-Z to OE ↓ (bus release to OE) 0 — — ns 161 ToeH2adD OE ↑ to AD Driven 0.125 TCY – 5 — — ns 162 TadV2oeH LS Data Valid before OE ↑ (data setup time) 20 — — ns 163 ToeH2adl OE ↑ to Data In Invalid (data hold time) 0 — — ns 164 TalH2alL ALE Pulse Width — 0.25 TCY — ns 165 ToeL2oeH OE Pulse Width 0.5 TCY – 5 0.5 TCY — ns 166 TalH2alH ALE ↑ to ALE ↑ (cycle time) — TCY — ns 167 Tacc Address Valid to Data Valid 0.75 TCY – 25 — — ns 168 Toe OE ↓ to Data Valid — 0.5 TCY – 25 ns 169 TalL2oeH ALE ↓ to OE ↑ 0.625 TCY – 10 — 0.625 TCY + 10 ns 171 TalH2csL Chip Enable Active to ALE ↓ 0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns DS39663F-page 368 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 27-9: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 166 AD<15:0> Address Data Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157 157A UB or LB Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated. TABLE 27-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE ↓ (address setup time) 0.25 TCY – 10 — — ns 151 TalL2adl ALE ↓ to Address Out Invalid (address hold time) 5 — — ns 153 TwrH2adl WRn ↑ to Data Out Invalid (data hold time) 5 — — ns 154 TwrL WRn Pulse Width 0.5 TCY – 5 0.5 TCY — ns 156 TadV2wrH Data Valid before WRn ↑ (data setup time) 0.5 TCY – 10 — — ns 157 TbsV2wrL Byte Select Valid before WRn ↓ 0.25 TCY — — ns (byte select setup time) 157A TwrH2bsI WRn ↑ to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 — — ns 166 TalH2alH ALE ↑ to ALE ↑ (cycle time) — TCY — ns 171 TalH2csL Chip Enable Active to ALE ↓ 0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns © 2009 Microchip Technology Inc. DS39663F-page 369
PIC18F87J10 FAMILY FIGURE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure27-3 for load conditions. TABLE 27-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period 3.5 4.1 4.9 ms (no postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 57.4 66 77.7 ms 34 TIOZ I/O High-Impedance from MCLR — 2 — μs Low or Watchdog Timer Reset 38 TCSD CPU Start-up Time — 200 — μs DS39663F-page 370 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 27-11: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure27-3 for load conditions. TABLE 27-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 TT1H T13CKI High Synchronous, no prescaler 0.5 TCY + 20 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 46 TT1L T13CKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 47 TT1P T13CKI Input Synchronous Greater of: — ns N = prescale Period 20ns or value (TCY + 40)/N (1, 2, 4, 8) Asynchronous 60 — ns FT1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 TCKE2TMRI Delay from External T13CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment © 2009 Microchip Technology Inc. DS39663F-page 371
PIC18F87J10 FAMILY FIGURE 27-12: CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure27-3 for load conditions. TABLE 27-14: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With prescaler 10 — ns 51 TCCH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With prescaler 10 — ns 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TCCR CCPx Output Fall Time — 25 ns 54 TCCF CCPx Output Fall Time — 25 ns TABLE 27-15: PARALLEL SLAVE PORT REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 62 TdtV2wrH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns 63 TwrH2dtI WR ↑ or CS ↑ to Data–In Invalid (hold time) 20 — ns 64 TrdL2dtV RD ↓ and CS ↓ to Data–Out Valid — 80 ns 65 TrdH2dtI RD ↑ or CS ↓ to Data–Out Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being Cleared from — 3 TCY WR ↑ or CS ↑ DS39663F-page 372 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 27-13: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SSx 70 SCKx (CKP = 0) 71 72 78 79 SCKx (CKP = 1) 79 78 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure27-3 for load conditions. TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input TCY — ns TSSL2SCL 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 1) of Byte 2 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV Note 1: Only if Parameter #71A and #72A are used. © 2009 Microchip Technology Inc. DS39663F-page 373
PIC18F87J10 FAMILY FIGURE 27-14: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SSx 81 SCKx (CKP = 0) 71 72 79 73 SCKx (CKP = 1) 80 78 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure27-3 for load conditions. TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 1) of Byte 2 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TCY — ns TDOV2SCL Note 1: Only if Parameter #71A and #72A are used. DS39663F-page 374 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 27-15: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SSx 70 SCKx (CKP = 0) 83 71 72 78 79 SCKx (CKP = 1) 79 78 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure27-3 for load conditions. TABLE 27-18: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input TCY — ns TSSL2SCL 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx ↑ to SDOx Output High-Impedance 10 50 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 83 TSCH2SSH, SSx ↑ after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. © 2009 Microchip Technology Inc. DS39663F-page 375
PIC18F87J10 FAMILY FIGURE 27-16: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SSx 70 SCKx 83 (CKP = 0) 71 72 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure27-3 for load conditions. TABLE 27-19: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input TCY — ns TSSL2SCL 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 20 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx ↑ to SDOx Output High-Impedance 10 50 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 82 TSSL2DOV SDOx Data Output Valid after SSx ↓ Edge — 50 ns 83 TSCH2SSH, SSx ↑ after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39663F-page 376 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 27-17: I2C™ BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure27-3 for load conditions. TABLE 27-20: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 27-18: I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure27-3 for load conditions. © 2009 Microchip Technology Inc. DS39663F-page 377
PIC18F87J10 FAMILY TABLE 27-21: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — μs 400 kHz mode 0.6 — μs MSSP Module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs MSSP Module 1.5 TCY — 102 TR SDAx and SCLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDAx and SCLx Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated 400 kHz mode 0.6 — μs Start condition 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — μs After this period, the first clock 400 kHz mode 0.6 — μs pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode — 0.9 μs 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode — — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — μs 400 kHz mode 0.6 — μs 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode — — μs before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT≥250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS39663F-page 378 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 27-19: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure27-3 for load conditions. TABLE 27-22: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. FIGURE 27-20: MASTER SSP I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 91 107 92 SDAx In 109 109 110 SDAx Out Note: Refer to Figure27-3 for load conditions. © 2009 Microchip Technology Inc. DS39663F-page 379
PIC18F87J10 FAMILY TABLE 27-23: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 1 MHz mode(1) — — ns 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) — — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free 400 kHz mode 1.3 — ms before a new transmission can start 1 MHz mode(1) — — ms D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, parameter #102 + parameter #107=1000+250=1250ns (for 100 kHz mode), before the SCLx line is released. DS39663F-page 380 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 27-21: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 122 Note: Refer to Figure27-3 for load conditions. TABLE 27-24: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid — 40 ns 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns 122 TDTRF Data Out Rise Time and Fall Time — 20 ns FIGURE 27-22: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TXx/CKx pin 125 RXx/DTx pin 126 Note: Refer to Figure27-3 for load conditions. TABLE 27-25: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CKx ↓ (DTx hold time) 10 — ns 126 TCKL2DTL Data Hold after CKx ↓ (DTx hold time) 15 — ns © 2009 Microchip Technology Inc. DS39663F-page 381
PIC18F87J10 FAMILY TABLE 27-26: A/D CONVERTER CHARACTERISTICS: PIC18F87J10 FAMILY (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±3 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±3 LSb ΔVREF ≥ 3.0V A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range 2.0 — — V VDD < 3.0V (VREFH – VREFL) 3 — — V VDD ≥ 3.0V A21 VREFH Reference Voltage High VSS — VREFH V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 2.5 kΩ Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 μA During VAIN acquisition. — — 150 μA During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source. FIGURE 27-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. DS39663F-page 382 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY TABLE 27-27: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period 0.7 25.0(1) μs TOSC based, VREF ≥ 3.0V 131 TCNV Conversion Time 11 12 TAD (not including acquisition time) (Note 2) 132 TACQ Acquisition Time (Note 3) 1.4 — μs -40°C to +85°C 135 TSWC Switching Time from Convert → Sample — (Note 4) 136 TDIS Discharge Time 0.2 — μs Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω. 4: On the following cycle of the device clock. © 2009 Microchip Technology Inc. DS39663F-page 383
PIC18F87J10 FAMILY NOTES: DS39663F-page 384 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX 18F67J10 XXXXXXXXXX -I/PTe3 XXXXXXXXXX 0910017 YYWWNNN 80-Lead TQFP Example XXXXXXXXXXXX PIC18F87J10 XXXXXXXXXXXX -I/PTe3 YYWWNNN 0910017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS39663F-page 385
PIC18F87J10 FAMILY 28.2 Package Details The following sections give the technical details of the packages. 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(cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)@/1 DS39663F-page 386 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:27)(cid:28)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) © 2009 Microchip Technology Inc. DS39663F-page 387
PIC18F87J10 FAMILY )(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 E e E1 b N NOTE1 123 NOTE2 α A c φ β A1 A2 L L1 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 @(cid:4) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)/(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)(cid:6)(cid:17)1 DS39663F-page 388 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY )(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) © 2009 Microchip Technology Inc. DS39663F-page 389
PIC18F87J10 FAMILY NOTES: DS39663F-page 390 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY APPENDIX A: MIGRATION BETWEEN HIGH-END DEVICE FAMILIES Devices in the PIC18F87J10 and PIC18F8722 families are very similar in their functions and feature sets. However, there are some potentially important differ- ences which should be considered when migrating an application across device families to achieve a new design goal. These are summarized in TableA-1. The areas of difference which could be a major impact on migration are discussed in greater detail later in this section. TABLE A-1: NOTABLE DIFFERENCES BETWEEN PIC18F8722 AND PIC18F87J10 FAMILIES Characteristic PIC18F87J10 Family PIC18F8722 Family Operating Frequency 40 MHz @ 2.7V 40 MHz @ 4.2V Supply Voltage 2.0V-3.6V, dual voltage requirement 2.0V-5.5V Operating Current Low Lower Program Memory Endurance 1,000 write/erase cycles (typical) 100,000 write/erase cycles (typical) I/O Sink/Source at 25mA PORTB and PORTC only All ports Input Voltage Tolerance on I/O pins 5.5V on digital only pins VDD on all I/O pins I/O 66 (RA7, RA6, RE3 and RF0 70 not available) Pull-ups PORTB, PORTD, PORTE PORTB and PORTJ Oscillator Options Limited options (EC, HS, PLL, More options (EC, HS, XT, LP, RC, fixed 32kHz INTRC) PLL, flexible INTRC) Program Memory Retention 20 years (minimum) 40 years (minimum) Programming Time (Normalized) 2.8 ms/byte (2.8ms/64-byte block) 15.6μs/byte (1ms/64-byte block) 64 Programming Entry Low Voltage, Key Sequence VPP and LVP Code Protection Single block, all or nothing Multiple code protection blocks Configuration Words Stored in last 4 words of Stored in Configuration Space, Program Memory space starting at 300000h Start-up Time from Sleep 200µs (typical) 10µs (typical) Power-up Timer Always on Configurable Data EEPROM Not available Available BOR Simple BOR with Voltage Regulator Programmable BOR LVD Not available Available A/D Channels 15 16 A/D Calibration Required Not required Microprocessor mode (EMB) Not available Available External Memory Addressing Address shifting available Address shifting not available In-Circuit Emulation Not available Available © 2009 Microchip Technology Inc. DS39663F-page 391
PIC18F87J10 FAMILY A.1 Power Requirement Differences A.3 Oscillator Differences The most significant difference between the PIC18F8722 devices have a greater range of oscillator PIC18F87J10 and PIC18F8722 device families is the options than PIC18F87J10 devices. The latter family is power requirements. PIC18F87J10 devices are limited primarily to operating modes that support HS designed on a smaller process; this results in lower and EC oscillators. maximum voltage and higher leakage current. In addition, the PIC18F87J10 has an internal RC The operating voltage range for PIC18F87J10 devices oscillator with only a fixed 32kHz output. The higher is 2.0V to 3.6V. In addition, these devices have split frequency RC modes of the PIC18F8722 family are not power requirements: one for the core logic and one for available. the I/O. One of the VDD pins is separated for the core Both device families have an internal PLL. For the logic supply (VDDCORE). This pin has specific voltage PIC18F87J10 family, however, the PLL must be and capacitor requirements as described in enabled in software. Section27.0 “Electrical Characteristics”. The clocking differences should be considered when making a conversion between the PIC18F8722 and A.2 Pin Differences PIC18F87J10 device families. There are several differences in the pinouts between the PIC18F87J10 and the PIC18F8722 families: A.4 Peripherals • Input voltage tolerance Peripherals must also be considered when making a • Output current capabilities conversion between the PIC18F87J10 and the • Available I/O PIC18F8722 families: Pins on the PIC18F87J10 that have digital only input • External Memory Bus: The external memory bus capability will tolerate voltages up to 5.5V and are thus on the PIC18F87J10 does not support Micro- tolerant to voltages above VDD. Table11-1 in controller mode; however, it does support external Section11.0 “I/O Ports” contains the complete list. address offset. In addition to input differences, there are output differ- • A/D Converter: There are only 15 channels on ences as well. PIC18F87J10 devices have three PIC18F87J10 devices. The converters for these classes of pin output current capability: high, medium devices also require a calibration step prior to and low. Not all I/O pins can source or sink equal levels normal operation. of current. Only PORTB and PORTC support the • Data EEPROM: PIC18F87J10 devices do not 25mA source/sink capability that is supported by all have this module. output pins on the PIC18F8722. Table11-2 in • BOR: PIC18F87J10 devices do not have a Section11.0 “I/O Ports” contains the complete list of programmable BOR. Simple brown-out capability output capabilities. is provided through the use of the internal voltage There are additional differences in how some pin func- regulator. tions are implemented on PIC18F87J10 devices. First, • LVD: PIC18F87J10 devices do not have this the OSC1/OSC2 oscillator pins are strictly dedicated to module. the external oscillator function; there is no option to re-allocate these pins to I/O (RA6 or RA7) as on PIC18F8722 devices. Second, the MCLR pin is dedicated only to MCLR and cannot be configured as an input (RG5). Finally, RF0 does not exist on PIC18F87J10 devices. All of these pin differences (including power pin differences) should be accounted for when making a conversion between PIC18F8722 and PIC18F87J10 devices. DS39663F-page 392 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY APPENDIX B: REVISION HISTORY Revision A (December 2004) Original data sheet for PIC18F87J10 family devices. Revision B (July 2005) Packaging diagrams have been updated. Document updated from Advanced to Preliminary. Updated all TBDs in Section27.0 “Electrical Characteristics”. Edits to text throughout document. Revision C (December 2005) Packaging diagrams have been updated. Minor edits to text throughout document. Revision D (June 2006) Electrical characteristics and packaging diagrams have been updated. Minor edits to text throughout document. Revision E (June 2009) Pin diagrams have been edited to indicate 5.5V tolerant input pins. Packaging diagrams have been updated. Section2.0 “Guidelines for Getting Started with PIC18FJ Microcontrollers” has been added. Minor text edits throughout the document. Revision F (September 2009) Added Appendix B: “Revision History”. © 2009 Microchip Technology Inc. DS39663F-page 393
PIC18F87J10 FAMILY NOTES: DS39663F-page 394 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY INDEX Block Diagrams 16-Bit Byte Select Mode ..........................................101 A 16-Bit Byte Write Mode ..............................................99 16-Bit Word Write Mode ..........................................100 A/D ...................................................................................261 8-Bit Multiplexed Modes ..........................................103 A/D Converter Interrupt, Configuring .......................265 A/D ...........................................................................264 Acquisition Requirements ........................................266 Analog Input Model ..................................................265 ADCAL Bit ................................................................269 Baud Rate Generator ..............................................225 ADCON0 Register ....................................................261 Capture Mode Operation .........................................171 ADCON1 Register ....................................................261 Comparator Analog Input Model ..............................275 ADCON2 Register ....................................................261 Comparator I/O Operating Modes ...........................272 ADRESH Register ............................................261, 264 Comparator Output ..................................................274 ADRESL Register ....................................................261 Comparator Voltage Reference ...............................278 Analog Port Pins ......................................................148 Comparator Voltage Reference Output Analog Port Pins, Configuring ..................................267 Buffer Example ................................................279 Associated Registers ...............................................269 Compare Mode Operation .......................................172 Automatic Acquisition Time ......................................267 Connections for On-Chip Voltage Regulator ...........288 Calculating the Minimum Required Device Clock ..............................................................34 Acquisition Time ..............................................266 Enhanced PWM Simplified ......................................181 Calibration ................................................................269 EUSART Receive ....................................................251 Configuring the Module ............................................265 EUSART Transmit ...................................................249 Conversion Clock (TAD) ...........................................267 External Power-on Reset Circuit Conversion Requirements .......................................383 Conversion Status (GO/DONE Bit) ..........................264 (Slow VDD Power-up) ........................................49 Fail-Safe Clock Monitor ...........................................290 Conversions .............................................................268 Generic I/O Port Operation ......................................125 Converter Characteristics ........................................382 Interrupt Logic ..........................................................110 Operation in Power-Managed Modes ......................269 MSSP (I2C Master Mode) ........................................223 Special Event Trigger (ECCP) .........................180, 268 MSSP (I2C Mode) ....................................................203 Use of the ECCP2 Trigger .......................................268 MSSP (SPI Mode) ...................................................193 Absolute Maximum Ratings .............................................347 On-Chip Reset Circuit ................................................47 AC (Timing) Characteristics .............................................362 PIC18F6XJ10/6XJ15 ...................................................8 Load Conditions for Device Timing PIC18F8XJ10/8XJ15 ...................................................9 Specifications ...................................................363 PLL ............................................................................33 Parameter Symbology .............................................362 PORTD and PORTE (Parallel Slave Port) ...............148 Temperature and Voltage Specifications .................363 PWM Operation (Simplified) ....................................174 Timing Conditions ....................................................363 Reads from Flash Program Memory .........................89 ACKSTAT ........................................................................229 Recommended Minimum Connections ......................27 ACKSTAT Status Flag .....................................................229 Single Comparator ...................................................273 ADCAL Bit ........................................................................269 Table Read Operation ...............................................85 ADCON0 Register ............................................................261 Table Write Operation ...............................................86 GO/DONE Bit ...........................................................264 Table Writes to Flash Program Memory ....................91 ADCON1 Register ............................................................261 Timer0 in 16-Bit Mode .............................................152 ADCON2 Register ............................................................261 Timer0 in 8-Bit Mode ...............................................152 ADDFSR ..........................................................................336 Timer1 .....................................................................156 ADDLW ............................................................................299 Timer1 (16-Bit Read/Write Mode) ............................156 ADDULNK ........................................................................336 Timer2 .....................................................................162 ADDWF ............................................................................299 Timer3 .....................................................................164 ADDWFC .........................................................................300 Timer3 (16-Bit Read/Write Mode) ............................164 ADRESH Register ............................................................261 Timer4 .....................................................................168 ADRESL Register ....................................................261, 264 Watchdog Timer ......................................................287 Analog-to-Digital Converter. See A/D. BN ....................................................................................302 ANDLW ............................................................................300 BNC .................................................................................303 ANDWF ............................................................................301 BNN .................................................................................303 Assembler BNOV ..............................................................................304 MPASM Assembler ..................................................344 BNZ .................................................................................304 Auto-Wake-up on Sync Break Character .........................252 BOR. See Brown-out Reset. B BOV .................................................................................307 Basic Connection Requirements ........................................27 BRA .................................................................................305 Baud Rate Generator .......................................................225 Break Character (12-Bit) Transmit and Receive ..............254 BC ....................................................................................301 BRG. See Baud Rate Generator. BCF ..................................................................................302 Brown-out Reset (BOR) .....................................................49 BF ....................................................................................229 and On-Chip Voltage Regulator ..............................288 BF Status Flag .................................................................229 Detecting ...................................................................49 © 2009 Microchip Technology Inc. DS39663F-page 395
PIC18F87J10 FAMILY BSF ..................................................................................305 Comparator ......................................................................271 BTFSC .............................................................................306 Analog Input Connection Considerations ................275 BTFSS ..............................................................................306 Associated Registers ...............................................275 BTG ..................................................................................307 Configuration ...........................................................272 BZ .....................................................................................308 Effects of a Reset ....................................................274 Interrupts .................................................................274 C Operation .................................................................273 C Compilers Operation During Sleep ...........................................274 MPLAB C18 .............................................................344 Outputs ....................................................................273 MPLAB C30 .............................................................344 Reference ................................................................273 Calibration (A/D Converter) ..............................................269 External Signal ................................................273 CALL ................................................................................308 Internal Signal ..................................................273 CALLW .............................................................................337 Response Time ........................................................273 Capture (CCP Module) .....................................................171 Comparator Specifications ...............................................361 Associated Registers ...............................................173 Comparator Voltage Reference .......................................277 CCP Pin Configuration .............................................171 Accuracy and Error ..................................................278 CCPRxH:CCPRxL Registers ...................................171 Associated Registers ...............................................279 Prescaler ..................................................................171 Configuring ..............................................................277 Software Interrupt ....................................................171 Connection Considerations ......................................278 Timer1/Timer3 Mode Selection ................................171 Effects of a Reset ....................................................278 Capture (ECCP Module) ..................................................180 Operation During Sleep ...........................................278 Capture/Compare/PWM (CCP) ........................................169 Compare (CCP Module) ..................................................172 Capture Mode. See Capture. Associated Registers ...............................................173 CCP Mode and Timer Resources ............................170 CCPRx Register ......................................................172 CCPRxH Register ....................................................170 Pin Configuration .....................................................172 CCPRxL Register .....................................................170 Software Interrupt ....................................................172 Compare Mode. See Compare. Timer1/Timer3 Mode Selection ................................172 Module Configuration ...............................................170 Compare (ECCP Module) ................................................180 Timer Interconnect Configurations ...........................170 Special Event Trigger ..............................165, 180, 268 Clock Sources ....................................................................34 Computed GOTO ...............................................................65 Selection and the FOSC2 Configuration Bit ...............35 Configuration Bits ............................................................281 Selection Using OSCCON Register ...........................35 Configuration Register Protection ....................................292 CLRF ................................................................................309 Core Features CLRWDT ..........................................................................309 Easy Migration .............................................................6 Code Examples Expanded Memory .......................................................5 16 x 16 Signed Multiply Routine ..............................108 Extended Instruction Set .............................................5 16 x 16 Unsigned Multiply Routine ..........................108 External Memory Bus ..................................................5 8 x 8 Signed Multiply Routine ..................................107 nanoWatt Technology ..................................................5 8 x 8 Unsigned Multiply Routine ..............................107 Oscillator Options and Features ..................................5 Changing Between Capture Prescalers ...................171 CPFSEQ ..........................................................................310 Computed GOTO Using an Offset Value ...................65 CPFSGT ..........................................................................311 Erasing Flash Program Memory ................................90 CPFSLT ...........................................................................311 Fast Register Stack ....................................................65 Crystal Oscillator/Ceramic Resonator ................................31 How to Clear RAM (Bank 1) Using Customer Change Notification Service ............................405 Indirect Addressing ............................................78 Customer Notification Service .........................................405 Implementing a Real-Time Clock Using a Customer Support ............................................................405 Timer1 Interrupt Service ..................................159 D Initializing PORTA ....................................................126 Initializing PORTB ....................................................128 Data Addressing Modes ....................................................78 Initializing PORTC ....................................................131 Comparing Addressing Modes with Initializing PORTD ....................................................134 the Extended Instruction Set Enabled ...............82 Initializing PORTE ....................................................137 Direct .........................................................................78 Initializing PORTF ....................................................140 Indexed Literal Offset ................................................81 Initializing PORTG ...................................................142 BSR ...................................................................83 Initializing PORTH ....................................................144 Instructions Affected ..........................................81 Initializing PORTJ ....................................................146 Mapping Access Bank .......................................83 Loading the SSP1BUF (SSP1SR) Register .............196 Indirect .......................................................................78 Reading a Flash Program Memory Word ..................89 Inherent and Literal ....................................................78 Saving STATUS, WREG and BSR Data Memory .....................................................................68 Registers in RAM .............................................124 Access Bank ..............................................................71 Writing to Flash Program Memory .............................92 Bank Select Register (BSR) ......................................68 Code Protection ...............................................................281 Extended Instruction Set ...........................................81 COMF ...............................................................................310 General Purpose Registers .......................................71 DS39663F-page 396 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY Memory Maps Baud Rate Generator (BRG) ...................................243 PIC18FX5J10/X5J15/X6J10 Devices ................69 Associated Registers .......................................244 PIC18FX6J15/X7J10 Devices ...........................70 Auto-Baud Rate Detect ....................................247 Special Function Registers ................................72 Baud Rate Error, Calculating ...........................244 Special Function Registers ........................................72 Baud Rates, Asynchronous Modes .................245 DAW .................................................................................312 High Baud Rate Select (BRGH Bit) .................243 DC Characteristics ...........................................................358 Sampling .........................................................243 Power-Down and Supply Current ............................351 Synchronous Master Mode ......................................255 Supply Voltage .........................................................350 Associated Registers, Receive ........................257 DCFSNZ ..........................................................................313 Associated Registers, Transmit .......................256 DECF ...............................................................................312 Reception ........................................................257 DECFSZ ...........................................................................313 Transmission ...................................................255 Development Support ......................................................343 Synchronous Slave Mode ........................................258 Device Overview ..................................................................5 Associated Registers, Receive ........................259 Details on Individual Family Members .........................6 Associated Registers, Transmit .......................258 Features (64-Pin Devices) ...........................................7 Reception ........................................................259 Features (80-Pin Devices) ...........................................7 Transmission ...................................................258 Direct Addressing ...............................................................79 Extended Instruction Set ADDFSR ..................................................................336 E ADDULNK ...............................................................336 ECCP CALLW ....................................................................337 Associated Registers ...............................................192 MOVSF ....................................................................337 Capture and Compare Modes ..................................180 MOVSS ....................................................................338 Enhanced PWM Mode .............................................181 PUSHL .....................................................................338 Standard PWM Mode ...............................................180 SUBFSR ..................................................................339 Effect on Standard PIC MCU Instructions ........................340 SUBULNK ................................................................339 Effects of Power-Managed Modes on External Clock Input (EC Modes) ......................................32 Various Clock Sources ...............................................37 External Memory Bus ........................................................95 Electrical Characteristics ..................................................347 16-Bit Byte Select Mode ..........................................101 Enhanced Capture/Compare/PWM (ECCP) ....................177 16-Bit Byte Write Mode ..............................................99 Capture Mode. See Capture (ECCP Module). 16-Bit Data Width Modes ...........................................98 ECCP1/ECCP3 Outputs and 16-Bit Mode Timing .................................................102 Program Memory Mode ...................................178 16-Bit Word Write Mode ..........................................100 ECCP2 Outputs and Program 8-Bit Mode ...............................................................103 Memory Modes ................................................178 8-Bit Mode Timing ...................................................104 Outputs and Configuration .......................................178 Address and Data Line Usage (table) .......................97 Pin Configurations for ECCP1 .................................179 Address and Data Width ............................................97 Pin Configurations for ECCP2 .................................179 Address Shifting ........................................................97 Pin Configurations for ECCP3 .................................180 Control .......................................................................96 PWM Mode. See PWM (ECCP Module). I/O Port Functions ......................................................95 Timer Resources ......................................................178 Operation in Power-Managed Modes ......................105 Use of CCP4/CCP5 with ECCP1/ECCP3 ................178 Program Memory Modes ...........................................98 Enhanced Universal Synchronous Asynchronous Receiver Extended Microcontroller ...................................98 Transmitter (EUSART). See EUSART. Microcontroller ...................................................98 ENVREG Pin ....................................................................288 Wait States ................................................................98 Equations Weak Pull-ups on Port Pins .......................................98 A/D Acquisition Time ................................................266 F A/D Minimum Charging Time ...................................266 Errata ...................................................................................4 Fail-Safe Clock Monitor ...........................................281, 290 EUSART Interrupts in Power-Managed Modes ......................291 Asynchronous Mode ................................................249 POR or Wake-up from Sleep ...................................291 12-Bit Break Transmit and Receive .................254 WDT During Oscillator Failure .................................290 Associated Registers, Receive ........................252 Fast Register Stack ...........................................................65 Associated Registers, Transmit .......................250 Firmware Instructions ......................................................293 Auto-Wake-up on Sync Break .........................252 Flash Configuration Words ..............................................281 Receiver ...........................................................251 Flash Program Memory .....................................................85 Setting Up 9-Bit Mode with Address Detect .....251 Associated Registers .................................................93 Transmitter .......................................................249 Control Registers .......................................................86 Baud Rate Generator EECON1 and EECON2 .....................................86 Operation in Power-Managed Mode ................243 TABLAT (Table Latch) Register ........................88 TBLPTR (Table Pointer) Register ......................88 © 2009 Microchip Technology Inc. DS39663F-page 397
PIC18F87J10 FAMILY Erase Sequence ........................................................90 In-Circuit Serial Programming (ICSP) ......................281, 292 Erasing .......................................................................90 Indexed Literal Offset Addressing Operation During Code-Protect .................................93 and Standard PIC18 Instructions .............................340 Reading ......................................................................89 Indexed Literal Offset Mode .............................................340 Table Pointer Indirect Addressing ............................................................79 Boundaries Based on Operation ........................88 INFSNZ ............................................................................315 Table Pointer Boundaries ..........................................88 Initialization Conditions for all Registers ......................53–57 Table Reads and Table Writes ..................................85 Instruction Cycle ................................................................66 Write Sequence .........................................................91 Clocking Scheme .......................................................66 Writing ........................................................................91 Flow/Pipelining ...........................................................66 Unexpected Termination ....................................93 Instruction Set ..................................................................293 Write Verify ........................................................93 ADDLW ....................................................................299 FSCM. See Fail-Safe Clock Monitor. ADDWF ....................................................................299 ADDWF (Indexed Literal Offset Mode) ....................341 G ADDWFC .................................................................300 GOTO ...............................................................................314 ANDLW ....................................................................300 ANDWF ....................................................................301 H BC ............................................................................301 Hardware Multiplier ..........................................................107 BCF .........................................................................302 Introduction ..............................................................107 BN ............................................................................302 Operation .................................................................107 BNC .........................................................................303 Hardware Various Multiply BNN .........................................................................303 Performance Comparisons ......................................107 BNOV ......................................................................304 I BNZ .........................................................................304 BOV .........................................................................307 I/O Ports ...........................................................................125 BRA .........................................................................305 Pin Capabilities ........................................................125 BSF ..........................................................................305 I2C Mode (MSSP) BSF (Indexed Literal Offset Mode) ..........................341 Acknowledge Sequence Timing ...............................232 BTFSC .....................................................................306 Associated Registers ...............................................238 BTFSS .....................................................................306 Baud Rate Generator ...............................................225 BTG .........................................................................307 Bus Collision BZ ............................................................................308 During a Repeated Start Condition ..................236 CALL ........................................................................308 During a Stop Condition ...................................237 CLRF .......................................................................309 Clock Arbitration .......................................................226 CLRWDT .................................................................309 Clock Stretching .......................................................218 COMF ......................................................................310 10-Bit Slave Receive Mode (SEN = 1) .............218 CPFSEQ ..................................................................310 10-Bit Slave Transmit Mode .............................218 CPFSGT ..................................................................311 7-Bit Slave Receive Mode (SEN = 1) ...............218 CPFSLT ...................................................................311 7-Bit Slave Transmit Mode ...............................218 DAW ........................................................................312 Clock Synchronization and the CKP bit ...................219 DCFSNZ ..................................................................313 Effects of a Reset .....................................................233 DECF .......................................................................312 General Call Address Support .................................222 DECFSZ ..................................................................313 I2C Clock Rate w/BRG .............................................225 Extended Instructions ..............................................335 Master Mode ............................................................223 Considerations when Enabling ........................340 Operation .........................................................224 Syntax ..............................................................335 Reception .........................................................229 Use with MPLAB IDE Tools .............................342 Repeated Start Condition Timing .....................228 General Format ........................................................295 Start Condition Timing .....................................227 GOTO ......................................................................314 Transmission ....................................................229 INCF ........................................................................314 Multi-Master Communication, Bus Collision INCFSZ ....................................................................315 and Arbitration ..................................................233 INFSNZ ....................................................................315 Multi-Master Mode ...................................................233 IORLW .....................................................................316 Operation .................................................................209 IORWF .....................................................................316 Read/Write Bit Information (R/W Bit) ...............209, 211 LFSR .......................................................................317 Registers ..................................................................203 MOVF ......................................................................317 Serial Clock (RC3/SCKx/SCLx) ...............................211 MOVFF ....................................................................318 Slave Mode ..............................................................209 MOVLB ....................................................................318 Addressing .......................................................209 MOVLW ...................................................................319 Reception .........................................................211 MOVWF ...................................................................319 Transmission ....................................................211 MULLW ....................................................................320 Sleep Operation .......................................................233 MULWF ....................................................................320 Stop Condition Timing ..............................................232 NEGF .......................................................................321 INCF .................................................................................314 NOP .........................................................................321 INCFSZ ............................................................................315 Opcode Field Descriptions .......................................294 In-Circuit Debugger ..........................................................292 DS39663F-page 398 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY POP .........................................................................322 Microchip Internet Web Site .............................................405 PUSH .......................................................................322 MOVF ..............................................................................317 RCALL .....................................................................323 MOVFF ............................................................................318 RESET .....................................................................323 MOVLB ............................................................................318 RETFIE ....................................................................324 MOVLW ...........................................................................319 RETLW ....................................................................324 MOVSF ............................................................................337 RETURN ..................................................................325 MOVSS ............................................................................338 RLCF ........................................................................325 MOVWF ...........................................................................319 RLNCF .....................................................................326 MPLAB ASM30 Assembler, Linker, Librarian ..................344 RRCF .......................................................................326 MPLAB ICD 2 In-Circuit Debugger ..................................345 RRNCF ....................................................................327 MPLAB ICE 2000 High-Performance Universal SETF ........................................................................327 In-Circuit Emulator ...................................................345 SETF (Indexed Literal Offset Mode) ........................341 MPLAB Integrated Development SLEEP .....................................................................328 Environment Software .............................................343 Standard Instructions ...............................................293 MPLAB PM3 Device Programmer ...................................345 SUBFWB ..................................................................328 MPLAB REAL ICE In-Circuit Emulator System ...............345 SUBLW ....................................................................329 MPLINK Object Linker/MPLIB Object Librarian ...............344 SUBWF ....................................................................329 MSSP SUBWFB ..................................................................330 ACK Pulse .......................................................209, 211 SWAPF ....................................................................330 Control Registers (general) .....................................193 TBLRD .....................................................................331 I2C Mode. See I2C Mode. TBLWT .....................................................................332 Module Overview .....................................................193 TSTFSZ ...................................................................333 SPI Master/Slave Connection ..................................197 XORLW ....................................................................333 TMR4 Output for Clock Shift ....................................168 XORWF ....................................................................334 MULLW ............................................................................320 INTCON Register MULWF ............................................................................320 RBIF Bit ....................................................................128 N INTCON Registers ...........................................................111 Inter-Integrated Circuit. See I2C. NEGF ...............................................................................321 Internal Oscillator Block .....................................................34 NOP .................................................................................321 Internal RC Oscillator Notable Differences Between PIC18F8722 Use with WDT ..........................................................287 and PIC18F87J10 Families .....................................391 Internal Voltage Reference Specifications .......................361 Oscillator Options ....................................................392 Internet Address ...............................................................405 Peripherals ..............................................................392 Interrupt Sources .............................................................281 Power Requirements ...............................................392 A/D Conversion Complete .......................................265 O Capture Complete (CCP) .........................................171 Compare Complete (CCP) .......................................172 Oscillator Configuration .....................................................31 Interrupt-on-Change (RB7:RB4) ..............................128 EC ..............................................................................31 TMR0 Overflow ........................................................153 ECPLL .......................................................................31 TMR1 Overflow ........................................................155 HS ..............................................................................31 TMR2 to PR2 Match (PWM) ....................................181 HS Modes ..................................................................31 TMR3 Overflow ................................................163, 165 HSPLL .......................................................................31 TMR4 to PR4 Match ................................................168 INTRC ........................................................................31 TMR4 to PR4 Match (PWM) ....................................167 Oscillator Selection ..........................................................281 Interrupts ..........................................................................109 Oscillator Start-up Timer (OST) .........................................37 During Context Saving .............................................124 Oscillator Switching ...........................................................34 INTx Pin ...................................................................124 Oscillator Transitions .........................................................35 PORTB, Interrupt-on-Change ..................................124 Oscillator, Timer1 .....................................................155, 165 TMR0 .......................................................................124 Oscillator, Timer3 .............................................................163 Interrupts, Flag Bits P Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) .....128 Packaging ........................................................................385 IORLW .............................................................................316 Details ......................................................................386 IORWF .............................................................................316 Marking ....................................................................385 IPR Registers ...................................................................120 Parallel Slave Port (PSP) .................................................148 L Associated Registers ...............................................150 LFSR ................................................................................317 PORTD ....................................................................148 RE0/RD Pin .............................................................148 M RE1/WR Pin ............................................................148 Master Clear (MCLR) .........................................................49 RE2/CS Pin .............................................................148 Master Synchronous Serial Port (MSSP). See MSSP. Select (PSPMODE Bit) ............................................148 Memory Organization .........................................................59 PICSTART Plus Development Programmer ....................346 Data Memory .............................................................68 PIE Registers ...................................................................117 Program Memory .......................................................59 Memory Programming Requirements ..............................360 © 2009 Microchip Technology Inc. DS39663F-page 399
PIC18F87J10 FAMILY Pin Functions RF2/AN7/C1OUT .................................................15, 22 AVDD ..........................................................................16 RF3/AN8 ..............................................................15, 22 AVDD ..........................................................................25 RF4/AN9 ..............................................................15, 22 AVSS ..........................................................................16 RF5/AN10/CVREF ................................................15, 22 AVSS ..........................................................................25 RF6/AN11 ............................................................15, 22 ENVREG ..............................................................16, 25 RF7/SS1 ..............................................................15, 22 MCLR ...................................................................10, 17 RG0/ECCP3/P3A .................................................16, 23 OSC1/CLKI ..........................................................10, 17 RG1/TX2/CK2 ......................................................16, 23 OSC2/CLKO ........................................................10, 17 RG2/RX2/DT2 ......................................................16, 23 RA0/AN0 ..............................................................10, 17 RG3/CCP4/P3D ...................................................16, 23 RA1/AN1 ..............................................................10, 17 RG4/CCP5/P1D ...................................................16, 23 RA2/AN2/VREF- ....................................................10, 17 RH0/A16 ....................................................................24 RA3/AN3/VREF+ ...................................................10, 17 RH1/A17 ....................................................................24 RA4/T0CKI ...........................................................10, 17 RH2/A18 ....................................................................24 RA5/AN4 ..............................................................10, 17 RH3/A19 ....................................................................24 RB0/INT0/FLT0 ....................................................11, 18 RH4/AN12/P3C ..........................................................24 RB1/INT1 .............................................................11, 18 RH5/AN13/P3B ..........................................................24 RB2/INT2 .............................................................11, 18 RH6/AN14/P1C ..........................................................24 RB3/INT3 ...................................................................11 RH7/AN15/P1B ..........................................................24 RB3/INT3/ECCP2/P2A ..............................................18 RJ0/ALE ....................................................................25 RB4/KBI0 .............................................................11, 18 RJ1/OE ......................................................................25 RB5/KBI1 .............................................................11, 18 RJ2/WRL ...................................................................25 RB6/KBI2/PGC ....................................................11, 18 RJ3/WRH ...................................................................25 RB7/KBI3/PGD ....................................................11, 18 RJ4/BA0 ....................................................................25 RC0/T1OSO/T13CKI ...........................................12, 19 RJ5/CE ......................................................................25 RC1/T1OSI/ECCP2/P2A ......................................12, 19 RJ6/LB .......................................................................25 RC2/ECCP1/P1A .................................................12, 19 RJ7/UB ......................................................................25 RC3/SCK1/SCL1 .................................................12, 19 VDD ............................................................................16 RC4/SDI1/SDA1 ..................................................12, 19 VDD ............................................................................25 RC5/SDO1 ...........................................................12, 19 VDDCORE/VCAP .....................................................16, 25 RC6/TX1/CK1 ......................................................12, 19 VSS ............................................................................16 RC7/RX1/DT1 ......................................................12, 19 VSS ............................................................................25 RD0/AD0/PSP0 ..........................................................20 Pinout I/O Descriptions RD0/PSP0 ..................................................................13 PIC18F6XJ10/6XJ15 .................................................10 RD1/AD1/PSP1 ..........................................................20 PIC18F8XJ10/8XJ15 .................................................17 RD1/PSP1 ..................................................................13 Pins RD2/AD2/PSP2 ..........................................................20 ENVREG ...................................................................29 RD2/PSP2 ..................................................................13 External Oscillator ......................................................30 RD3/AD3/PSP3 ..........................................................20 ICSP ..........................................................................29 RD3/PSP3 ..................................................................13 Master Clear (MCLR ..................................................28 RD4/AD4/PSP4/SDO2 ...............................................20 Power Supply ............................................................28 RD4/PSP4/SDO2 .......................................................13 VCAP/VDDCORE ...........................................................29 RD5/AD5/PSP5/SDI2/SDA2 ......................................20 PIR Registers ...................................................................114 RD5/PSP5/SDI2/SDA2 ..............................................13 PLL ....................................................................................33 RD6/AD6/PSP6/SCK2/SCL2 .....................................20 ECPLL Oscillator Mode .............................................33 RD6/PSP6/SCK2/SCL2 .............................................13 HSPLL Oscillator Mode .............................................33 RD7/AD7/PSP7/SS2 ..................................................20 POP .................................................................................322 RD7/PSP7/SS2 ..........................................................13 POR. See Power-on Reset. RE0/AD8/RD/P2D ......................................................21 PORTA RE0/RD/P2D ..............................................................14 Associated Registers ...............................................127 RE1/AD9/WR/P2C .....................................................21 LATA Register .........................................................126 RE1/WR/P2C .............................................................14 PORTA Register ......................................................126 RE2/AD10/CS/P2B ....................................................21 TRISA Register ........................................................126 RE2/CS/P2D ..............................................................14 PORTB RE3/AD11/P3C ..........................................................21 Associated Registers ...............................................130 RE3/P3C ....................................................................14 LATB Register .........................................................128 RE4/AD12/P3B ..........................................................21 PORTB Register ......................................................128 RE4/P3B ....................................................................14 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........128 RE5/AD13/P1C ..........................................................21 TRISB Register ........................................................128 RE5/P1C ....................................................................14 PORTC RE6/AD14/P1B ..........................................................21 Associated Registers ...............................................133 RE6/P1B ....................................................................14 LATC Register .........................................................131 RE7/AD15/ECCP2/P2A .............................................21 PORTC Register ......................................................131 RE7/ECCP2/P2A .......................................................14 RC3/SCKx/SCLx Pin ...............................................211 RF1/AN6/C2OUT .................................................15, 22 TRISC Register ........................................................131 DS39663F-page 400 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY PORTD PRI_RUN Mode .................................................................40 Associated Registers ...............................................136 Program Counter ...............................................................63 LATD Register .........................................................134 PCL, PCH and PCU Registers ..................................63 PORTD Register ......................................................134 PCLATH and PCLATU Registers ..............................63 TRISD Register ........................................................134 Program Memory PORTE Extended Instruction Set ...........................................81 Analog Port Pins ......................................................148 Flash Configuration Words ........................................60 Associated Registers ...............................................139 Hard Memory Vectors ................................................60 LATE Register ..........................................................137 Instructions ................................................................67 PORTE Register ......................................................137 Two-Word ..........................................................67 PSP Mode Select (PSPMODE Bit) ..........................148 Interrupt Vector ..........................................................60 RE0/RD Pin ..............................................................148 Look-up Tables ..........................................................65 RE1/WR Pin .............................................................148 Memory Maps ............................................................59 RE2/CS Pin ..............................................................148 Hard Vectors and Configuration Words .............60 TRISE Register ........................................................137 Modes PORTF Extended Microcontroller ...................................61 Associated Registers ...............................................141 Extended Microcontroller (Address Shifting) .....62 LATF Register ..........................................................140 Memory Access (table) ......................................62 PORTF Register ......................................................140 Microcontroller ...................................................61 TRISF Register ........................................................140 Modes (PIC18F8XJ10/8XJ15) ...................................61 PORTG Reset Vector ..............................................................60 Associated Registers ...............................................143 Program Verification and Code Protection ......................292 LATG Register .........................................................142 Programming, Device Instructions ...................................293 PORTG Register ......................................................142 PSP.See Parallel Slave Port. TRISG Register ........................................................142 Pulse-Width Modulation. See PWM (CCP Module) PORTH and PWM (ECCP Module). Associated Registers ...............................................145 PUSH ...............................................................................322 LATH Register .........................................................144 PUSH and POP Instructions ..............................................64 PORTH Register ......................................................144 PUSHL .............................................................................338 TRISH Register ........................................................144 PWM (CCP Module) PORTJ Associated Registers ...............................................176 Associated Registers ...............................................147 Duty Cycle ...............................................................174 LATJ Register ..........................................................146 Example Frequencies/Resolutions ..........................175 PORTJ Register .......................................................146 Operation Setup ......................................................175 TRISJ Register .........................................................146 Period ......................................................................174 Power-Managed Modes .....................................................39 PR2/PR4 Registers .................................................174 and EUSART Operation ...........................................243 TMR2 (TMR4) to PR2 (PR4) Match ........................174 and SPI Operation ...................................................201 TMR2 to PR2 Match ................................................181 Clock Transitions and Status Indicators .....................40 TMR4 to PR4 Match ................................................167 Entering ......................................................................39 PWM (ECCP Module) ......................................................181 Exiting Idle and Sleep Modes ....................................45 CCPR1H:CCPR1L Registers ..................................181 By Interrupt ........................................................45 Direction Change in Full-Bridge Output Mode .........186 By Reset ............................................................45 Duty Cycle ...............................................................182 By WDT Time-out ..............................................45 Effects of a Reset ....................................................191 Without an Oscillator Start-up Delay ..................45 Enhanced PWM Auto-Shutdown .............................188 Idle Modes .................................................................43 Example Frequencies/Resolutions ..........................182 PRI_IDLE ...........................................................44 Full-Bridge Application Example ..............................186 RC_IDLE ............................................................45 Full-Bridge Mode .....................................................185 SEC_IDLE .........................................................44 Half-Bridge Mode .....................................................184 Multiple Sleep Commands .........................................40 Half-Bridge Output Mode Applications Example .....184 Run Modes .................................................................40 Output Configurations ..............................................182 PRI_RUN ...........................................................40 Output Relationships (Active-High) .........................183 RC_RUN ............................................................42 Output Relationships (Active-Low) ..........................183 SEC_RUN ..........................................................40 Period ......................................................................181 Selecting ....................................................................39 Programmable Dead-Band Delay ............................188 Sleep Mode ................................................................43 Setup for PWM Operation .......................................191 Summary (table) ........................................................39 Start-up Considerations ...........................................189 Power-on Reset (POR) ......................................................49 Q Power-up Delays ................................................................37 Power-up Timer (PWRT) .............................................37, 50 Q Clock ....................................................................175, 182 Time-out Sequence ....................................................50 R Prescaler Timer2 ......................................................................182 RAM. See Data Memory. Prescaler, Timer0 .............................................................153 RC_IDLE Mode ..................................................................45 Prescaler, Timer2 (Timer4) ..............................................175 RC_RUN Mode ..................................................................42 PRI_IDLE Mode .................................................................44 RCALL .............................................................................323 © 2009 Microchip Technology Inc. DS39663F-page 401
PIC18F87J10 FAMILY RCON Register Reset .................................................................................47 Bit Status During Initialization ....................................52 Brown-out Reset (BOR) .............................................47 Reader Response ............................................................406 MCLR Reset, During Power-Managed Modes ..........47 Register File .......................................................................71 MCLR Reset, Normal Operation ................................47 Register File Summary .................................................73–76 Power-on Reset (POR) ..............................................47 Registers RESET Instruction .....................................................47 ADCON0 (A/D Control 0) .........................................261 Stack Full Reset .........................................................47 ADCON1 (A/D Control 1) .........................................262 Stack Underflow Reset ..............................................47 ADCON2 (A/D Control 2) .........................................263 Watchdog Timer (WDT) Reset ..................................47 BAUDCONx (Baud Rate Control) ............................242 Resets ..............................................................................281 CCPxCON (CCPx Control) ......................................169 Brown-out Reset (BOR) ...........................................281 CCPxCON (ECCPx Control) ....................................177 Oscillator Start-up Timer (OST) ...............................281 CMCON (Comparator Control) ................................271 Power-on Reset (POR) ............................................281 CONFIG1H (Configuration 1 High) ..........................283 Power-up Timer (PWRT) .........................................281 CONFIG1L (Configuration 1 Low) ............................283 RETFIE ............................................................................324 CONFIG2H (Configuration 2 High) ..........................284 RETLW ............................................................................324 CONFIG2L (Configuration 2 Low) ............................284 RETURN ..........................................................................325 CONFIG3H (Configuration 3 High) ..........................285 Return Address Stack ........................................................63 CONFIG3L (Configuration 3 Low) ......................61, 285 Return Stack Pointer (STKPTR) ........................................64 CVRCON (Comparator Voltage RLCF ...............................................................................325 Reference Control) ...........................................277 RLNCF .............................................................................326 DEVID1 (Device ID 1) ..............................................286 RRCF ...............................................................................326 DEVID2 (Device ID 2) ..............................................286 RRNCF ............................................................................327 ECCPxAS (Enhanced CCPx Auto-Shutdown S Control) ............................................................189 ECCPxDEL (PWM Dead-Band Delay) .....................188 SCKx ................................................................................193 EECON1 (EEPROM Control 1) ..................................87 SDIx .................................................................................193 INTCON (Interrupt Control) ......................................111 SDOx ...............................................................................193 INTCON2 (Interrupt Control 2) .................................112 SEC_IDLE Mode ...............................................................44 INTCON3 (Interrupt Control 3) .................................113 SEC_RUN Mode ................................................................40 IPR1 (Peripheral Interrupt Priority 1) ........................120 Serial Clock, SCKx ..........................................................193 IPR2 (Peripheral Interrupt Priority 2) ........................121 Serial Data In (SDIx) ........................................................193 IPR3 (Peripheral Interrupt Priority 3) ........................122 Serial Data Out (SDOx) ...................................................193 MEMCON (External Memory Bus Control) ................96 Serial Peripheral Interface. See SPI Mode. OSCCON (Oscillator Control) ....................................36 SETF ................................................................................327 OSCTUNE (PLL Control) ...........................................33 Slave Select (SSx) ...........................................................193 PIE1 (Peripheral Interrupt Enable 1) ........................117 SLEEP .............................................................................328 PIE2 (Peripheral Interrupt Enable 2) ........................118 Sleep PIE3 (Peripheral Interrupt Enable 3) ........................119 OSC1 and OSC2 Pin States ......................................37 PIR1 (Peripheral Interrupt Request (Flag) 1) ...........114 Software Simulator (MPLAB SIM) ...................................344 PIR2 (Peripheral Interrupt Request (Flag) 2) ...........115 Special Event Trigger. See Compare (ECCP Module). PIR3 (Peripheral Interrupt Request (Flag) 3) ...........116 Special Features of the CPU ...........................................281 PSPCON (Parallel Slave Port Control) ....................149 SPI Mode (MSSP) ...........................................................193 RCON (Reset Control) .......................................48, 123 Associated Registers ...............................................202 RCSTAx (Receive Status and Control) ....................241 Bus Mode Compatibility ...........................................201 SSPxADD (MSSP1 and MSSP2 Address) ..............208 Clock Speed, Interactions ........................................201 SSPxCON1 (MSSPx Control 1, I2C Mode) ..............205 Effects of a Reset ....................................................201 SSPxCON1 (MSSPx Control 1, SPI Mode) .............195 Enabling SPI I/O ......................................................197 SSPxCON2 (MSSPx Control 2, Master Mode ............................................................198 I2C Master Mode) .............................................206 Master/Slave Connection .........................................197 SSPxSTAT (MSSPx Status, I2C Mode) ...................204 Operation .................................................................196 SSPxSTAT (MSSPx Status, SPI Mode) ..................194 Operation in Power-Managed Modes ......................201 STATUS .....................................................................77 Serial Clock ..............................................................193 STKPTR (Stack Pointer) ............................................64 Serial Data In ...........................................................193 T0CON (Timer0 Control) ..........................................151 Serial Data Out ........................................................193 T1CON (Timer1 Control) ..........................................155 Slave Mode ..............................................................199 T2CON (Timer2 Control) ..........................................161 Slave Select .............................................................193 T3CON (Timer3 Control) ..........................................163 Slave Select Synchronization ..................................199 T4CON (Timer4 Control) ..........................................167 SPI Clock .................................................................198 TXSTAx (Transmit Status and Control) ...................240 SSPxBUF Register ..................................................198 WDTCON (Watchdog Timer Control) .......................287 SSPxSR Register ....................................................198 RESET .............................................................................323 Typical Connection ..................................................197 SSPOV ............................................................................229 DS39663F-page 402 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY SSPOV Status Flag .........................................................229 Timer4 .............................................................................167 SSPxSTAT Register Associated Registers ...............................................168 R/W Bit .............................................................209, 211 MSSP Clock Shift ....................................................168 SSx ..................................................................................193 Operation .................................................................167 Stack Full/Underflow Resets ..............................................65 Postscaler. See Postscaler, Timer4. SUBFSR ..........................................................................339 PR4 Register ...........................................................167 SUBFWB ..........................................................................328 Prescaler. See Prescaler, Timer4. SUBLW ............................................................................329 TMR4 Register ........................................................167 SUBULNK ........................................................................339 TMR4 to PR4 Match Interrupt ..........................167, 168 SUBWF ............................................................................329 Timing Diagrams SUBWFB ..........................................................................330 A/D Conversion .......................................................382 SWAPF ............................................................................330 Asynchronous Reception .........................................252 Asynchronous Transmission ...................................250 T Asynchronous Transmission (Back to Back) ...........250 Table Pointer Operations (table) ........................................88 Automatic Baud Rate Calculation ............................248 Table Reads/Table Writes .................................................65 Auto-Wake-up Bit (WUE) During TBLRD .............................................................................331 Normal Operation ............................................253 TBLWT .............................................................................332 Auto-Wake-up Bit (WUE) During Sleep ...................253 Timer0 ..............................................................................151 Baud Rate Generator with Clock Arbitration ............226 Associated Registers ...............................................153 BRG Overflow Sequence ........................................248 Operation .................................................................152 BRG Reset Due to SDAx Arbitration During Overflow Interrupt ....................................................153 Start Condition .................................................235 Prescaler ..................................................................153 Bus Collision During a Repeated Start Switching Assignment ......................................153 Condition (Case 1) ...........................................236 Prescaler Assignment (PSA Bit) ..............................153 Bus Collision During a Repeated Start Prescaler Select (T0PS2:T0PS0 Bits) .....................153 Condition (Case 2) ...........................................236 Prescaler. See Prescaler, Timer0. Bus Collision During a Start Condition Reads and Writes in 16-Bit Mode ............................152 (SCLx = 0) .......................................................235 Source Edge Select (T0SE Bit) ................................152 Bus Collision During a Stop Source Select (T0CS Bit) .........................................152 Condition (Case 1) ...........................................237 Timer1 ..............................................................................155 Bus Collision During a Stop 16-Bit Read/Write Mode ...........................................157 Condition (Case 2) ...........................................237 Associated Registers ...............................................159 Bus Collision During Start Condition Interrupt ....................................................................158 (SDAx Only) .....................................................234 Low-Power Option ...................................................157 Bus Collision for Transmit and Acknowledge ..........233 Operation .................................................................156 Capture/Compare/PWM (Including Oscillator ..........................................................155, 157 ECCP Modules) ...............................................372 Layout Considerations .....................................158 CLKO and I/O ..........................................................366 Oscillator, as Secondary Clock ..................................34 Clock Synchronization .............................................219 Overflow Interrupt ....................................................155 Clock/Instruction Cycle ..............................................66 Resetting, Using the ECCP EUSART Synchronous Receive Special Event Trigger ......................................158 (Master/Slave) .................................................381 Special Event Trigger (ECCP) .................................180 EUSART Synchronous Transmission TMR1H Register ......................................................155 (Master/Slave) .................................................381 TMR1L Register .......................................................155 Example SPI Master Mode (CKE = 0) .....................373 Use as a Clock Source ............................................157 Example SPI Master Mode (CKE = 1) .....................374 Use as a Real-Time Clock .......................................158 Example SPI Slave Mode (CKE = 0) .......................375 Timer2 ..............................................................................161 Example SPI Slave Mode (CKE = 1) .......................376 Associated Registers ...............................................162 External Clock (All Modes Except PLL) ...................364 Interrupt ....................................................................162 External Memory Bus for Sleep Operation .................................................................161 (Extended Microcontroller Mode) ............102, 104 Output ......................................................................162 External Memory Bus for TBLRD PR2 Register ............................................................181 (Extended Microcontroller Mode) ............102, 104 TMR2 to PR2 Match Interrupt ..................................181 Fail-Safe Clock Monitor ...........................................291 Timer3 ..............................................................................163 First Start Bit Timing ................................................227 16-Bit Read/Write Mode ...........................................165 Full-Bridge PWM Output ..........................................185 Associated Registers ...............................................165 Half-Bridge PWM Output .........................................184 Operation .................................................................164 I2C Acknowledge Sequence ....................................232 Oscillator ..........................................................163, 165 I2C Bus Data ............................................................377 Overflow Interrupt ............................................163, 165 I2C Bus Start/Stop Bits ............................................377 Special Event Trigger (ECCP) .................................165 I2C Master Mode (7 or 10-Bit Transmission) ...........230 TMR3H Register ......................................................163 I2C Master Mode (7-Bit Reception) .........................231 TMR3L Register .......................................................163 © 2009 Microchip Technology Inc. DS39663F-page 403
PIC18F87J10 FAMILY I2C Slave Mode (10-Bit Reception, SEN = 0, Capture/Compare/PWM Requirements ADMSK = 01001) .............................................215 (Including ECCP Modules) ..............................372 I2C Slave Mode (10-Bit Reception, SEN = 0) ..........216 CLKO and I/O Requirements ...........................366, 368 I2C Slave Mode (10-Bit Reception, SEN = 1) ..........221 EUSART Synchronous Receive I2C Slave Mode (10-Bit Transmission) .....................217 Requirements ..................................................381 I2C Slave Mode (7-Bit Reception, SEN = 0, EUSART Synchronous Transmission ADMSK = 01011) .............................................213 Requirements ..................................................381 I2C Slave Mode (7-Bit Reception, SEN = 0) ............212 Example SPI Mode Requirements I2C Slave Mode (7-Bit Reception, SEN = 1) ............220 (Master Mode, CKE = 0) ..................................373 I2C Slave Mode (7-Bit Transmission) .......................214 Example SPI Mode Requirements I2C Slave Mode General Call Address Sequence (Master Mode, CKE = 1) ..................................374 (7 or 10-Bit Addressing Mode) .........................222 Example SPI Mode Requirements I2C Stop Condition Receive or Transmit Mode ........232 (Slave Mode, CKE = 0) ....................................375 Master SSP I2C Bus Data ........................................379 Example SPI Slave Mode Requirements Master SSP I2C Bus Start/Stop Bits ........................379 (CKE = 1) .........................................................376 Parallel Slave Port (PSP) Read ...............................150 External Clock Requirements ..................................364 Parallel Slave Port (PSP) Write ...............................149 I2C Bus Data Requirements (Slave Mode) ..............378 Program Memory Read ............................................368 I2C Bus Start/Stop Bits Requirements Program Memory Write ............................................369 (Slave Mode) ...................................................377 PWM Auto-Shutdown (P1RSEN = 0, Master SSP I2C Bus Data Requirements ................380 Auto-Restart Disabled) .....................................190 Master SSP I2C Bus Start/Stop Bits PWM Auto-Shutdown (P1RSEN = 1, Requirements ..................................................379 Auto-Restart Enabled) .....................................190 Parallel Slave Port Requirements ............................372 PWM Direction Change ...........................................187 PLL Clock ................................................................365 PWM Direction Change at Near Program Memory Write Requirements ....................369 100% Duty Cycle .............................................187 Reset, Watchdog Timer, Oscillator Start-up PWM Output ............................................................174 Timer, Power-up Timer and Brown-out Repeated Start Condition .........................................228 Reset Requirements ........................................370 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer0 and Timer1 External Clock Timer (OST) and Power-up Timer (PWRT) .....370 Requirements ..................................................371 Send Break Character Sequence ............................254 Top-of-Stack Access ..........................................................63 Slave Synchronization .............................................199 TRISE Register Slow Rise Time (MCLR Tied to VDD, PSPMODE Bit ..........................................................148 VDD Rise > TPWRT) ............................................51 TSTFSZ ...........................................................................333 SPI Mode (Master Mode) .........................................198 Two-Speed Start-up .................................................281, 289 SPI Mode (Slave Mode, CKE = 0) ...........................200 Two-Word Instructions SPI Mode (Slave Mode, CKE = 1) ...........................200 Example Cases ..........................................................67 Synchronous Reception (Master Mode, SREN) ......257 TXSTAx Register Synchronous Transmission ......................................255 BRGH Bit .................................................................243 Synchronous Transmission (Through TXEN) ..........256 U Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 .......................50 Unused I/Os .......................................................................30 Time-out Sequence on Power-up V (MCLR Not Tied to VDD), Case 2 .......................51 Time-out Sequence on Power-up VDDCORE/VCAP Pin ..........................................................288 (MCLR Tied to VDD, VDD Rise < TPWRT) ...........50 Voltage Reference Specifications ....................................361 Timer0 and Timer1 External Clock ..........................371 Voltage Regulator (On-Chip) ...........................................288 Transition for Entry to Idle Mode ................................44 W Transition for Entry to SEC_RUN Mode ....................41 Transition for Entry to Sleep Mode ............................43 Watchdog Timer (WDT) ...........................................281, 287 Transition for Two-Speed Start-up Associated Registers ...............................................287 (INTRC to HSPLL) ...........................................289 Control Register .......................................................287 Transition for Wake From Idle to Run Mode ..............44 During Oscillator Failure ..........................................290 Transition for Wake From Sleep (HSPLL) .................43 Programming Considerations ..................................287 Transition From RC_RUN Mode to WCOL ......................................................227, 228, 229, 232 PRI_RUN Mode .................................................42 WCOL Status Flag ...................................227, 228, 229, 232 Transition from SEC_RUN Mode to WWW Address ................................................................405 PRI_RUN Mode (HSPLL) ..................................41 WWW, On-Line Support ......................................................4 Transition to RC_RUN Mode .....................................42 X Timing Diagrams and Specifications XORLW ............................................................................333 AC Characteristics XORWF ...........................................................................334 Internal RC Accuracy .......................................365 DS39663F-page 404 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS39663F-page 405
PIC18F87J10 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F87J10 Family Literature Number: DS39663F Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39663F-page 406 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18F86J10-I/PT 301 = Industrial temp., Range TQFP package, QTP pattern #301. b) PIC18F65J15T-I/PT = Tape and reel, Industrial temp., TQFP package. Device PIC18F65J10/65J15/66J10/66J15/67J10(1), PIC18F85J10/85J15/86J10/86J15/87J10(1), PIC18F65J10/65J15/66J10/66J15/67J10T(2), PIC18F85J10/85J15/86J10/86J15/87J10T(2) Temperature Range I = -40°C to +85°C (Industrial) Package PT = TQFP (Thin Quad Flatpack) Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) Note1: F = Standard Voltage Range 2: T = in tape and reel © 2009 Microchip Technology Inc. DS39663F-page 407
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