PIC18F6520/8520/6620/ 8620/6720/8720 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D High-Performance RISC CPU: Analog Features: • C compiler optimized architecture/instruction set: • 10-bit, up to 16-channel Analog-to-Digital - Source code compatible with the PIC16 and Converter (A/D): PIC17 instruction sets - Conversion available during Sleep • Linear program memory addressing to 128 Kbytes • Programmable 16-level Low-Voltage Detection • Linear data memory addressing to 3840bytes (LVD) module: • 1Kbyte of data EEPROM - Supports interrupt on Low-Voltage Detection • Up to 10 MIPs operation: • Programmable Brown-out Reset (PBOR) - DC – 40 MHz osc./clock input • Dual analog comparators: - 4 MHz – 10 MHz osc./clock input with PLL active - Programmable input/output configuration • 16-bit wide instructions, 8-bit wide data path Special Microcontroller Features: • Priority levels for interrupts • 100,000 erase/write cycle Enhanced Flash • 31-level, software accessible hardware stack program memory typical • 8 x 8 Single Cycle Hardware Multiplier • 1,000,000 erase/write cycle Data EEPROM External Memory Interface memory typical (PIC18F8X20 Devices Only): • 1 second programming time • Flash/Data EEPROM Retention: > 40 years • Address capability of up to 2Mbytes • 16-bit interface • Self-reprogrammable under software control • Power-on Reset (POR), Power-up Timer (PWRT) Peripheral Features: and Oscillator Start-up Timer (OST) • High current sink/source 25 mA/25 mA • Watchdog Timer (WDT) with its own On-Chip • Four external interrupt pins RC Oscillator for reliable operation • Timer0 module: 8-bit/16-bit timer/counter • Programmable code protection • Timer1 module: 16-bit timer/counter • Power saving Sleep mode • Timer2 module: 8-bit timer/counter • Selectable oscillator options including: • Timer3 module: 16-bit timer/counter - 4X Phase Lock Loop (of primary oscillator) • Timer4 module: 8-bit timer/counter - Secondary Oscillator (32 kHz) clock input • Secondary oscillator clock option – Timer1/Timer3 • In-Circuit Serial Programming™ (ICSP™) via • Five Capture/Compare/PWM (CCP) modules: two pins - Capture is 16-bit, max. resolution 6.25 ns (TCY/16) • MPLAB® In-Circuit Debug (ICD) via two pins - Compare is 16-bit, max. resolution 100 ns (TCY) CMOS Technology: - PWM output: PWM resolution is 1 to 10-bit • Low-power, high-speed Flash technology • Master Synchronous Serial Port (MSSP) module with two modes of operation: • Fully static design - 3-wire SPI (supports all 4 SPI modes) • Wide operating voltage range (2.0V to 5.5V) - I2C™ Master and Slave mode • Industrial and Extended temperature ranges • Two Addressable USART modules: - Supports RS-485 and RS-232 • Parallel Slave Port (PSP) module Program Memory Data Memory 10-bit MSSP Max CCP Timers Ext Device Bytes #I Snsintrgulec-tWioonrsd (SbRytAeMs) E(EbPyRteOs)M I/O (Ac/hD) (PWM) SPI MaI2sCter USART 8-bit/16-bit Bus (FMOHSzC) PIC18F6520 32K 16384 2048 1024 52 12 5 Y Y 2 2/3 N 40 PIC18F6620 64K 32768 3840 1024 52 12 5 Y Y 2 2/3 N 25 PIC18F6720 128K 65536 3840 1024 52 12 5 Y Y 2 2/3 N 25 PIC18F8520 32K 16384 2048 1024 68 16 5 Y Y 2 2/3 Y 40 PIC18F8620 64K 32768 3840 1024 68 16 5 Y Y 2 2/3 Y 25 PIC18F8720 128K 65536 3840 1024 68 16 5 Y Y 2 2/3 Y 25  2003-2013 Microchip Technology Inc. DS39609C-page 1

PIC18F6520/8520/6620/8620/6720/8720 Pin Diagrams 64-Pin TQFP 1) (2 0 1 2 3 4 5 6 7 P P P P P P P P P S C S S S S S S S S C C P P P P P P P P E2/ E3 E4 E5 E6 E7/ D0/ DD SS D1/ D2/ D3/ D4/ D5/ D6/ D7/ R R R R R R R V V R R R R R R R 4 3 2 1 0 9 8 7 6 5 4 3 2 10 9 6 6 6 6 6 5 5 5 5 5 5 5 5 55 4 RE1/WR 1 48 RB0/INT0 RE0/RD 2 47 RB1/INT1 RG0/CCP3 3 46 RB2/INT2 RG1/TX2/CK2 4 45 RB3/INT3 RG2/RX2/DT2 5 44 RB4/KBI0 RG3/CCP4 6 43 RB5/KBI1/PGM MCLR/VPP 7 PIC18F6520 42 RB6/KBI2/PGC RG4/CCP5 8 PIC18F6620 41 VSS VSS 9 40 OSC2/CLKO/RA6 PIC18F6720 VDD 10 39 OSC1/CLKI RF7/SS 11 38 VDD RF6/AN11 12 37 RB7/KBI3/PGD RF5/AN10/CVREF 13 36 RC5/SDO RF4/AN9 14 35 RC4/SDI/SDA RF3/AN8 15 34 RC3/SCK/SCL RF2/AN7/C1OUT 16 33 RC2/CCP1 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 RF1/AN6/C2OUT RF0/AN5 AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0 VSS VDD RA5/AN4/LVDIN RA4/T0CKI(1)C1/T1OSI/CCP2 C0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 R R Note 1: CCP2 is multiplexed with RC1 when CCP2MX is set. DS39609C-page 2  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 Pin Diagrams (Continued) 80-Pin TQFP 3) (2)15(3)0 (3)1(3)2(3)3(3)4(3)5(3)6(3)7 (0 D D D D D D D DD 1 A A A A A A A AA A17 A16CS/AD AD11 AD12 AD13 AD14CCP2/ PSP0/ PSP1/ PSP2/ PSP3/ PSP4/ PSP5/ PSP6/PSP7/ALE OE H1/ H0/E2/ E3/ E4/ E5/ E6/E7/ D0/ DD SS D1/ D2/ D3/ D4/ D5/ D6/D7/J0/ J1/ R RR R R R RR RV V R R R R R RRR R 0 9 8 76 5 43 2 109 87 65 4 32 1 8 7 7 77 7 77 7 776 66 66 6 66 6 RH2/A18 1 60 RJ2/WRL RH3/A19 2 59 RJ3/WRH RE1/WR/AD9(3) 3 58 RB0/INT0 RE0/RD/AD8(3) 4 57 RB1/INT1 RG0/CCP3 5 56 RB2/INT2 RG1/TX2/CK2 6 55 RB3/INT3/CCP2(1) RG2/RX2/DT2 7 54 RB4/KBI0 RG3/CCP4 8 53 RB5/KBI1/PGM MCLR/VPP 9 PIC18F8520 52 RB6/KBI2/PGC RG4/CCP5 10 PIC18F8620 51 VSS VSS 11 50 OSC2/CLKO/RA6 VDD 12 PIC18F8720 49 OSC1/CLKI RF7/SS 13 48 VDD RF6/AN11 14 47 RB7/KBI3/PGD RF5/AN10/CVREF 15 46 RC5/SDO RF4/AN9 16 45 RC4/SDI/SDA RF3/AN8 17 44 RC3/SCK/SCL RF2/AN7/C1OUT 18 43 RC2/CCP1 RH7/AN15 19 42 RJ7/UB RH6/AN14 20 41 RJ6/LB 1 2 3 45 6 7 8 9 01 2 34 5 6 7 8 90 2 2 2 22 2 2 2 2 33 3 33 3 3 3 3 34 RH5/AN13RH4/AN12 RF1/AN6/C2OUT RF0/AN5 AVDD AVSSRA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0VSS VDD RA5/AN4/LVDIN RA4/T0CKI(1)C1/T1OSI/CCP2 C0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 RJ4/BA0RJ5/CE R R Note 1: CCP2 is multiplexed with RC1 when CCP2MX is set. 2: CCP2 is multiplexed by default with RE7 when the device is configured in Microcontroller mode. 3: PSP is available only in Microcontroller mode.  2003-2013 Microchip Technology Inc. DS39609C-page 3

PIC18F6520/8520/6620/8620/6720/8720 Table of Contents 1.0 Device Overview..........................................................................................................................................................................7 2.0 Oscillator Configurations............................................................................................................................................................21 3.0 Reset..........................................................................................................................................................................................29 4.0 Memory Organization.................................................................................................................................................................39 5.0 Flash Program Memory..............................................................................................................................................................61 6.0 External Memory Interface.........................................................................................................................................................71 7.0 Data EEPROM Memory.............................................................................................................................................................79 8.0 8 X 8 Hardware Multiplier...........................................................................................................................................................85 9.0 Interrupts....................................................................................................................................................................................87 10.0 I/O Ports...................................................................................................................................................................................103 11.0 Timer0 Module.........................................................................................................................................................................131 12.0 Timer1 Module.........................................................................................................................................................................135 13.0 Timer2 Module.........................................................................................................................................................................141 14.0 Timer3 Module.........................................................................................................................................................................143 15.0 Timer4 Module.........................................................................................................................................................................147 16.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................149 17.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................157 18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)..............................................................197 19.0 10-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................213 20.0 Comparator Module..................................................................................................................................................................223 21.0 Comparator Voltage Reference Module...................................................................................................................................229 22.0 Low-Voltage Detect..................................................................................................................................................................233 23.0 Special Features of the CPU....................................................................................................................................................239 24.0 Instruction Set Summary..........................................................................................................................................................259 25.0 Development Support...............................................................................................................................................................301 26.0 Electrical Characteristics..........................................................................................................................................................305 27.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................341 28.0 Packaging Information..............................................................................................................................................................355 Appendix A: Revision History.............................................................................................................................................................361 Appendix B: Device Differences.........................................................................................................................................................361 Appendix C: Conversion Considerations...........................................................................................................................................362 Appendix D: Migration from Mid-range to Enhanced Devices...........................................................................................................362 Appendix E: Migration from High-end to Enhanced Devices.............................................................................................................363 The Microchip Web Site.....................................................................................................................................................................375 Customer Change Notification Service..............................................................................................................................................375 Customer Support..............................................................................................................................................................................375 Reader Response..............................................................................................................................................................................376 PIC18F6520/8520/6620/8620/6720/8720 Product Identification System..........................................................................................377 DS39609C-page 4  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2003-2013 Microchip Technology Inc. DS39609C-page 5

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 6  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 1.0 DEVICE OVERVIEW With the addition of new operating modes, the External Memory Interface offers many new options, including: This document contains device specific information for • Operating the microcontroller entirely from external the following devices: memory • PIC18F6520 • PIC18F8520 • Using combinations of on-chip and external • PIC18F6620 • PIC18F8620 memory, up to the 2-Mbyte limit • Using external Flash memory for reprogrammable • PIC18F6720 • PIC18F8720 application code, or large data tables This family offers the same advantages of all PIC18 • Using external RAM devices for storing large microcontrollers – namely, high computational amounts of variable data performance at an economical price – with the addition of high endurance Enhanced Flash program memory. The 1.1.3 EASY MIGRATION PIC18FXX20 family also provides an enhanced range of Regardless of the memory size, all devices share the program memory options and versatile analog features same rich set of peripherals, allowing for a smooth that make it ideal for complex, high-performance migration path as applications grow and evolve. applications. The consistent pinout scheme used throughout the 1.1 Key Features entire family also aids in migrating to the next larger device. This is true when moving between the 64-pin 1.1.1 EXPANDED MEMORY members, between the 80-pin members, or even jumping from 64-pin to 80-pin devices. The PIC18FXX20 family introduces the widest range of on-chip, Enhanced Flash program memory available 1.1.4 OTHER SPECIAL FEATURES on PIC® microcontrollers – up to 128Kbyte (or 65,536 words), the largest ever offered by Microchip. For users • Communications: The PIC18FXX20 family incorporates a range of serial communications with more modest code requirements, the family also includes members with 32Kbyte or 64Kbyte. peripherals, including 2 independent USARTs and a Master SSP module, capable of both SPI and Other memory features are: I2C (Master and Slave) modes of operation. For • Data RAM and Data EEPROM: The PIC18F8X20 devices, one of the general purpose PIC18FXX20 family also provides plenty of room I/O ports can be reconfigured as an 8-bit Parallel for application data. Depending on the device, Slave Port for direct processor-to-processor either 2048 or 3840bytes of data RAM are communications. available. All devices have 1024bytes of data • CCP Modules: All devices in the family EEPROM for long-term retention of nonvolatile incorporate five Capture/Compare/PWM modules data. to maximize flexibility in control applications. Up • Memory Endurance: The Enhanced Flash cells to four different time bases may be used to for both program memory and data EEPROM are perform several different operations at once. rated to last for many thousands of erase/write • Analog Features: All devices in the family cycles – up to 100,000 for program memory and feature 10-bit A/D converters, with up to 16 input 1,000,000 for EEPROM. Data retention without channels, as well as the ability to perform refresh is conservatively estimated to be greater conversions during Sleep mode. Also included than 40 years. are dual analog comparators with programmable input and output configuration, a programmable 1.1.2 EXTERNAL MEMORY INTERFACE Low-Voltage Detect module and a programmable In the event that 128Kbytes of program memory is Brown-out Reset module. inadequate for an application, the PIC18F8X20 • Self-programmability: These devices can write members of the family also implement an External to their own program memory spaces under inter- Memory Interface. This allows the controller’s internal nal software control. By using a bootloader routine program counter to address a memory space of up to located in the protected Boot Block at the top of 2Mbytes, permitting a level of data access that few program memory, it becomes possible to create 8-bit devices can claim. an application that can update itself in the field.  2003-2013 Microchip Technology Inc. DS39609C-page 7

PIC18F6520/8520/6620/8620/6720/8720 1.2 Details on Individual Family 3. A/D channels (12 for PIC18F6X20 devices, Members 16 for PIC18F8X20) 4. I/O pins (52 on PIC18F6X20 devices, 68 on The PIC18FXX20 devices are available in 64-pin and PIC18F8X20) 80-pin packages. They are differentiated from each 5. External program memory interface (present other in five ways: only on PIC18F8X20 devices) 1. Flash program memory (32Kbytes for All other features for devices in the PIC18FXX20 family PIC18FX520 devices, 64Kbytes for are identical. These are summarized in Table1-1. PIC18FX620 devices and 128Kbytes for PIC18FX720 devices) Block diagrams of the PIC18F6X20 and PIC18F8X20 devices are provided in Figure1-1 and Figure1-2, 2. Data RAM (2048 bytes for PIC18FX520 respectively. The pinouts for these device families are devices, 3840 bytes for PIC18FX620 and listed in Table1-2. PIC18FX720 devices) TABLE 1-1: PIC18FXX20 DEVICE FEATURES Features PIC18F6520 PIC18F6620 PIC18F6720 PIC18F8520 PIC18F8620 PIC18F8720 Operating Frequency DC – 40 MHz DC – 25 MHz DC – 25 MHz DC – 40 MHz DC – 25 MHz DC – 25 MHz Program Memory 32K 64K 128K 32K 64K 128K (Bytes) Program Memory 16384 32768 65536 16384 32768 65536 (Instructions) Data Memory 2048 3840 3840 2048 3840 3840 (Bytes) Data EEPROM 1024 1024 1024 1024 1024 1024 Memory (Bytes) External Memory No No No Yes Yes Yes Interface Interrupt Sources 17 17 17 18 18 18 I/O Ports Ports A, B, C, Ports A, B, C, D, Ports A, B, C, D, Ports A, B, C, Ports A, B, C, Ports A, B, C, D, E, F, G E, F, G E, F, G D, E, F, G, H, J D, E, F, G, H, J D, E, F, G, H, J Timers 5 5 5 5 5 5 Capture/Compare/ 5 5 5 5 5 5 PWM Modules Serial Communications MSSP, MSSP, MSSP, MSSP, MSSP, MSSP, Addressable Addressable Addressable Addressable Addressable Addressable USART (2) USART (2) USART (2) USART (2) USART (2) USART (2) Parallel Communications PSP PSP PSP PSP PSP PSP 10-bit Analog-to-Digital 12 input 12 input 12 input 16 input 16 input 16 input Module channels channels channels channels channels channels Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET RESET RESET RESET RESET RESET Instruction, Instruction, Instruction, Instruction, Instruction, Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST) Programmable Yes Yes Yes Yes Yes Yes Low-Voltage Detect Programmable Yes Yes Yes Yes Yes Yes Brown-out Reset Instruction Set 77 Instructions 77 Instructions 77 Instructions 77 Instructions 77 Instructions 77 Instructions Package 64-pin TQFP 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP DS39609C-page 8  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 1-1: PIC18F6X20 BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0 RA1/AN1 Table Pointer<21> Data Latch 21 RA2/AN2/VREF- 8 8 RA3/AN3/VREF+ Data RAM RA4/T0CKI 21 inc/dec logic RA5/AN4/LVDIN Address Latch RA6 21 PCLAT U PCLATH 12 PORTB RB0/INT0 Address<12> PCU PCH PCL RB1/INT1 Program Counter 4 12 4 RB2/INT2 RB3/INT3 Address Latch BSR FSR0 Bank0, F RB4/KBI0 Program Memory 31 Level Stack FSR1 RB5/KBI1/PGM FSR2 12 RB6/KBI2/PGC RB7/KBI3/PGD Data Latch inc/dec Decode logic PORTC Table Latch RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 16 8 RC2/CCP1 ROM Latch RC3/SCK/SCL RC4/SDI/SDA RC5/SDO IR RC6/TX1/CK1 RC7/RX1/DT1 8 PORTD PRODH PRODL RD7/PSP7:RD0/PSP0 Instruction 8 x 8 Multiply Decode & Control 3 8 PORTE RE0/RD BITOP WREG RE1/WR OSC2/CLKO PoTwimere-rup 8 8 8 RE2/CS OSC1/CLKI RE3 Timing Oscillator 8 RE4 Generation Start-up Timer RE5 Power-on ALU<8> RE6 Reset RE7/CCP2 Watchdog 8 PORTF Timer Precision RF0/AN5 Band Gap Brown-out RF1/AN6/C2OUT Reference Reset RF2/AN7/C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CVREF MCLR/VPP VDD, VSS RF6/AN11 RF7/SS PORTG Synchronous Data RG0/CCP3 Serial Port USART1 USART2 EEPROM RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4 RG4/CCP5 BOR Timer0 Timer1 Timer2 Timer3 Timer4 LVD 10-bit Comparator CCP1 CCP2 CCP3 CCP4 CCP5 A/D  2003-2013 Microchip Technology Inc. DS39609C-page 9

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 1-2: PIC18F8X20 BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0 RA1/AN1 Table Pointer<21> Data Latch RA2/AN2/VREF- 21 RA3/AN3/VREF+ 8 8 Data RAM RA4/T0CKI 21 inc/dec logic RA5/AN4/LVDIN RA6 Address Latch PORTB e 21 PCLAT U PCLATH 12 RB0/INT0 erfac PCU PCH PCL Address<12> RRBB12//IINNTT12 ystem Bus Int PArodgdrraems sM Leamtcohry Pr3o1g Lraemve Cl Sotuanctker 4BSR 1FFF2SSSRRR012 B4ank01, F2 RRRRRBBBBB65743/////KKKKINBBBBTIIII21330////PPPCGGGCCMDP2 S Data Latch PORTC inc/dec RC0/T1OSO/T13CKI Decode logic RC1/T1OSI/CCP2 Table Latch RC2/CCP1 RC3/SCK/SCL 16 8 RC4/SDI/SDA ROM Latch RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1 IR AD15:AD0,A19:A16(1) PORTD 8 RD7/PSP7/AD7: RD0/PSP0/AD0 PRODH PRODL PORTE RE0/RD/AD8 IDnCsetcoroundctrteoio l&n 3 8 x 8 Multiply 8 RREE21//CWSR/A/ADD190 RE3/AD11 BITOP WREG RE4/AD12 Power-up 8 8 8 RE5/AD13 OSC2/CLKO Timer RE6/AD14 OSC1/CLKI Timing Oscillator 8 RE7/CCP2/AD15 Generation Start-up Timer PORTF Power-on ALU<8> RF0/AN5 RF1/AN6/C2OUT Reset RF2/AN7/C1OUT Watchdog 8 RF3/AN8 Timer Precision RF4/AN9 Band Gap Brown-out RF5/AN10/CVREF Reference Reset RF6/AN11 RF7/SS PORTG RG0/CCP3 MCLR/VPP VDD, VSS RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4 RG4/CCP5 PORTH RH3/AD19:RH0/AD16 Synchronous Data Serial Port USART1 USART2 EEPROM RH7/AN15:RH4/AN12 PORTJ RJ0/ALE RJ1/OE BOR RJ2/WRL LVD Timer0 Timer1 Timer2 Timer3 Timer4 RJ3/WRH RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB 10-bit Comparator CCP1 CCP2 CCP3 CCP4 CCP5 A/D Note 1: External memory interface pins are physically multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16). DS39609C-page 10  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 T ABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type PIC18F6X20 PIC18F8X20 MCLR/VPP 7 9 Master Clear (input) or programming voltage (output). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. OSC1/CLKI 39 49 Oscillator crystal or external clock input. OSC1 I CMOS/ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. CLKI I CMOS External clock source input. Always associated with pin function OSC1 (seeOSC1/CLKI, OSC2/CLKO pins). OSC2/CLKO/RA6 40 50 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller). 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X20 devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices. 6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSP modes. See parameter D001A for details.  2003-2013 Microchip Technology Inc. DS39609C-page 11

PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PIC18F6X20 PIC18F8X20 PORTA is a bidirectional I/O port. RA0/AN0 24 30 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 23 29 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF- 22 28 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (Low) input. RA3/AN3/VREF+ 21 27 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (High) input. RA4/T0CKI 28 34 RA4 I/O ST/OD Digital I/O – Open-drain when configured as output. T0CKI I ST Timer0 external clock input. RA5/AN4/LVDIN 27 33 RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. LVDIN I Analog Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller). 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X20 devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices. 6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSP modes. See parameter D001A for details. DS39609C-page 12  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PIC18F6X20 PIC18F8X20 PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 48 58 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. RB1/INT1 47 57 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. RB2/INT2 46 56 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. RB3/INT3/CCP2 45 55 RB3 I/O TTL Digital I/O. INT3 I/O ST External interrupt 3. CCP2(1) I/O ST Capture2 input, Compare2 output, PWM2 output. RB4/KBI0 44 54 RB4 I/O TTL Digital I/O. KBI0 I ST Interrupt-on-change pin. RB5/KBI1/PGM 43 53 RB5 I/O TTL Digital I/O. KBI1 I ST Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP Programming enable pin. RB6/KBI2/PGC 42 52 RB6 I/O TTL Digital I/O. KBI2 I ST Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock. RB7/KBI3/PGD 37 47 RB7 I/O TTL Digital I/O. KBI3 I/O ST Interrupt-on-change pin. PGD In-Circuit Debugger and ICSP programming data. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller). 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X20 devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices. 6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSP modes. See parameter D001A for details.  2003-2013 Microchip Technology Inc. DS39609C-page 13

PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PIC18F6X20 PIC18F8X20 PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 30 36 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 29 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(2) I/O ST Capture2 input/Compare2 output/ PWM2 output. RC2/CCP1 33 43 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 34 44 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C mode. RC4/SDI/SDA 35 45 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O ST I2C data I/O. RC5/SDO 36 46 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX1/CK1 31 37 RC6 I/O ST Digital I/O. TX1 O — USART 1 asynchronous transmit. CK1 I/O ST USART 1 synchronous clock (see RX1/DT1). RC7/RX1/DT1 32 38 RC7 I/O ST Digital I/O. RX1 I ST USART 1 asynchronous receive. DT1 I/O ST USART 1 synchronous data (see TX1/CK1). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller). 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X20 devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices. 6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSP modes. See parameter D001A for details. DS39609C-page 14  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PIC18F6X20 PIC18F8X20 PORTD is a bidirectional I/O port. These pins have TTL input buffers when external memory is enabled. RD0/PSP0/AD0 58 72 RD0 I/O ST Digital I/O. PSP0 I/O TTL Parallel Slave Port data. AD0(3) I/O TTL External memory address/data 0. RD1/PSP1/AD1 55 69 RD1 I/O ST Digital I/O. PSP1 I/O TTL Parallel Slave Port data. AD1(3) I/O TTL External memory address/data 1. RD2/PSP2/AD2 54 68 RD2 I/O ST Digital I/O. PSP2 I/O TTL Parallel Slave Port data. AD2(3) I/O TTL External memory address/data 2. RD3/PSP3/AD3 53 67 RD3 I/O ST Digital I/O. PSP3 I/O TTL Parallel Slave Port data. AD3(3) I/O TTL External memory address/data 3. RD4/PSP4/AD4 52 66 RD4 I/O ST Digital I/O. PSP4 I/O TTL Parallel Slave Port data. AD4(3) I/O TTL External memory address/data 4. RD5/PSP5/AD5 51 65 RD5 I/O ST Digital I/O. PSP5 I/O TTL Parallel Slave Port data. AD5(3) I/O TTL External memory address/data 5. RD6/PSP6/AD6 50 64 RD6 I/O ST Digital I/O. PSP6 I/O TTL Parallel Slave Port data. AD6(3) I/O TTL External memory address/data 6. RD7/PSP7/AD7 49 63 RD7 I/O ST Digital I/O. PSP7 I/O TTL Parallel Slave Port data. AD7(3) I/O TTL External memory address/data 7. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller). 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X20 devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices. 6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSP modes. See parameter D001A for details.  2003-2013 Microchip Technology Inc. DS39609C-page 15

PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PIC18F6X20 PIC18F8X20 PORTE is a bidirectional I/O port. RE0/RD/AD8 2 4 RE0 I/O ST Digital I/O. RD I TTL Read control for Parallel Slave Port (seeWR and CS pins). AD8(3) I/O TTL External memory address/data 8. RE1/WR/AD9 1 3 RE1 I/O ST Digital I/O. WR I TTL Write control for Parallel Slave Port (seeCS and RD pins). AD9(3) I/O TTL External memory address/data 9. RE2/CS/AD10 64 78 RE2 I/O ST Digital I/O. CS I TTL Chip select control for Parallel Slave Port (see RD and WR). AD10(3) I/O TTL External memory address/data 10. RE3/AD11 63 77 RE3 I/O ST Digital I/O. AD11(3) I/O TTL External memory address/data 11. RE4/AD12 62 76 RE4 I/O ST Digital I/O. AD12 I/O TTL External memory address/data 12. RE5/AD13 61 75 RE5 I/O ST Digital I/O. AD13(3) I/O TTL External memory address/data 13. RE6/AD14 60 74 RE6 I/O ST Digital I/O. AD14(3) I/O TTL External memory address/data 14. RE7/CCP2/AD15 59 73 RE7 I/O ST Digital I/O. CCP2(1,4) I/O ST Capture2 input/Compare2 output/ PWM2 output. AD15(3) I/O TTL External memory address/data 15. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller). 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X20 devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices. 6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSP modes. See parameter D001A for details. DS39609C-page 16  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PIC18F6X20 PIC18F8X20 PORTF is a bidirectional I/O port. RF0/AN5 18 24 RF0 I/O ST Digital I/O. AN5 I Analog Analog input 5. RF1/AN6/C2OUT 17 23 RF1 I/O ST Digital I/O. AN6 I Analog Analog input 6. C2OUT O ST Comparator 2 output. RF2/AN7/C1OUT 16 18 RF2 I/O ST Digital I/O. AN7 I Analog Analog input 7. C1OUT O ST Comparator 1 output. RF3/AN8 15 17 RF1 I/O ST Digital I/O. AN8 I Analog Analog input 8. RF4/AN9 14 16 RF1 I/O ST Digital I/O. AN9 I Analog Analog input 9. RF5/AN10/CVREF 13 15 RF1 I/O ST Digital I/O. AN10 I Analog Analog input 10. CVREF O Analog Comparator VREF output. RF6/AN11 12 14 RF6 I/O ST Digital I/O. AN11 I Analog Analog input 11. RF7/SS 11 13 RF7 I/O ST Digital I/O. SS I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller). 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X20 devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices. 6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSP modes. See parameter D001A for details.  2003-2013 Microchip Technology Inc. DS39609C-page 17

PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PIC18F6X20 PIC18F8X20 PORTG is a bidirectional I/O port. RG0/CCP3 3 5 RG0 I/O ST Digital I/O. CCP3 I/O ST Capture3 input/Compare3 output/ PWM3 output. RG1/TX2/CK2 4 6 RG1 I/O ST Digital I/O. TX2 O — USART 2 asynchronous transmit. CK2 I/O ST USART 2 synchronous clock (see RX2/DT2). RG2/RX2/DT2 5 7 RG2 I/O ST Digital I/O. RX2 I ST USART 2 asynchronous receive. DT2 I/O ST USART 2 synchronous data (see TX2/CK2). RG3/CCP4 6 8 RG3 I/O ST Digital I/O. CCP4 I/O ST Capture4 input/Compare4 output/ PWM4 output. RG4/CCP5 8 10 RG4 I/O ST Digital I/O. CCP5 I/O ST Capture5 input/Compare5 output/ PWM5 output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller). 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X20 devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices. 6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSP modes. See parameter D001A for details. DS39609C-page 18  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PIC18F6X20 PIC18F8X20 PORTH is a bidirectional I/O port(5). RH0/A16 — 79 RH0 I/O ST Digital I/O. A16 O TTL External memory address 16. RH1/A17 — 80 RH1 I/O ST Digital I/O. A17 O TTL External memory address 17. RH2/A18 — 1 RH2 I/O ST Digital I/O. A18 O TTL External memory address 18. RH3/A19 — 2 RH3 I/O ST Digital I/O. A19 O TTL External memory address 19. RH4/AN12 — 22 RH4 I/O ST Digital I/O. AN12 I Analog Analog input 12. RH5/AN13 — 21 RH5 I/O ST Digital I/O. AN13 I Analog Analog input 13. RH6/AN14 — 20 RH6 I/O ST Digital I/O. AN14 I Analog Analog input 14. RH7/AN15 — 19 RH7 I/O ST Digital I/O. AN15 I Analog Analog input 15. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller). 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X20 devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices. 6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSP modes. See parameter D001A for details.  2003-2013 Microchip Technology Inc. DS39609C-page 19

PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PIC18F6X20 PIC18F8X20 PORTJ is a bidirectional I/O port(5). RJ0/ALE — 62 RJ0 I/O ST Digital I/O. ALE O TTL External memory address latch enable. RJ1/OE — 61 RJ1 I/O ST Digital I/O. OE O TTL External memory output enable. RJ2/WRL — 60 RJ2 I/O ST Digital I/O. WRL O TTL External memory write low control. RJ3/WRH — 59 RJ3 I/O ST Digital I/O. WRH O TTL External memory write high control. RJ4/BA0 — 39 RJ4 I/O ST Digital I/O. BA0 O TTL External memory Byte Address 0 control. RJ5/CE — 40 RJ5 I/O ST Digital I/O. CE O TTL External memory chip enable control. RJ6/LB — 41 RJ6 I/O ST Digital I/O. LB O TTL External memory low byte select. RJ7/UB — 42 RJ7 I/O ST Digital I/O. UB O TTL External memory high byte select. VSS 9, 25, 11, 31, P — Ground reference for logic and I/O pins. 41, 56 51, 70 VDD 10, 26, 12, 32, P — Positive supply for logic and I/O pins. 38, 57 48, 71 AVSS(6) 20 26 P — Ground reference for analog modules. AVDD(6) 19 25 P — Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller). 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X20 devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices. 6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of the part in user or ICSP modes. See parameter D001A for details. DS39609C-page 20  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 2.0 OSCILLATOR TABLE 2-1: CAPACITOR SELECTION FOR CONFIGURATIONS CERAMIC RESONATORS Ranges Tested: 2.1 Oscillator Types Mode Freq C1 C2 The PIC18FXX20 devices can be operated in eight XT 455 kHz 68-100 pF 68-100 pF different oscillator modes. The user can program three 2.0 MHz 15-68 pF 15-68 pF configuration bits (FOSC2, FOSC1 and FOSC0) to 4.0 MHz 15-68 pF 15-68 pF select one of these eight modes: HS 8.0 MHz 10-68 pF 10-68 pF 1. LP Low-Power Crystal 16.0 MHz 10-22 pF 10-22 pF 2. XT Crystal/Resonator These values are for design guidance only. 3. HS High-Speed Crystal/Resonator See notes following this table. 4. HS+PLL High-Speed Crystal/Resonator Resonators Used: with PLL enabled 2.0 MHz Murata Erie CSA2.00MG  0.5% 5. RC External Resistor/Capacitor 4.0 MHz Murata Erie CSA4.00MG  0.5% 6. RCIO External Resistor/Capacitor with 8.0 MHz Murata Erie CSA8.00MT  0.5% I/O pin enabled 16.0 MHz Murata Erie CSA16.00MX  0.5% 7. EC External Clock All resonators used did not have built-in capacitors. 8. ECIO External Clock with I/O pin enabled Note1: Higher capacitance increases the stability 2.2 Crystal Oscillator/Ceramic of the oscillator, but also increases the Resonators start-up time. In XT, LP, HS or HS+PLL Oscillator modes, a crystal or 2: When operating below 3V VDD, or when using certain ceramic resonators at any ceramic resonator is connected to the OSC1 and voltage, it may be necessary to use high OSC2 pins to establish oscillation. Figure2-1 shows gain HS mode, try a lower frequency the pin connections. resonator, or switch to a crystal oscillator. The PIC18FXX20 oscillator design requires the use of 3: Since each resonator/crystal has its own a parallel cut crystal. characteristics, the user should consult Note: Use of a series cut crystal may give a fre- the resonator/crystal manufacturer for quency out of the crystal manufacturer’s appropriate values of external specifications. components, or verify oscillator performance. FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP CONFIGURATION) C1(1) OSC1 To Internal XTAL (3) Logic RF Sleep RS(2) C2(1) OSC2 PIC18FXX20 Note 1: See Table2-1 and Table2-2 for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the oscillator mode chosen.  2003-2013 Microchip Technology Inc. DS39609C-page 21

PIC18F6520/8520/6620/8620/6720/8720 TABLE 2-2: CAPACITOR SELECTION FOR FIGURE 2-2: EXTERNAL CLOCK INPUT CRYSTAL OSCILLATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) Ranges Tested: Mode Freq C1 C2 Clock from OSC1 LP 32 kHz Ext. System PIC18FXX20 15-22 pF 15-22 pF 200 kHz Open OSC2 XT 1 MHz 15-22 pF 15-22 pF 4 MHz HS 4 MHz 2.3 RC Oscillator 8 MHz 15-22 pF 15-22 pF For timing insensitive applications, the “RC” and 20 MHz “RCIO” device options offer additional cost savings. Capacitor values are for design guidance only. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) val- These capacitors were tested with the above crystal ues and the operating temperature. In addition to this, frequencies for basic start-up and operation. These the oscillator frequency will vary from unit to unit, due values are not optimized. to normal process parameter variation. Furthermore, Different capacitor values may be required to produce the difference in lead frame capacitance between pack- acceptable oscillator operation. The user should test age types will also affect the oscillation frequency, the performance of the oscillator over the expected especially for low CEXT values. The user also needs to VDD and temperature range for the application. take into account variation due to tolerance of external R and C components used. Figure2-3 shows how the See the notes following this table for additional R/C combination is connected. information. In the RC Oscillator mode, the oscillator frequency Note1: Higher capacitance increases the stability divided by 4 is available on the OSC2 pin. This signal of the oscillator, but also increases the may be used for test purposes or to synchronize other start-up time. logic. 2: When operating below 3V VDD, or when FIGURE 2-3: RC OSCILLATOR MODE using certain ceramic resonators at any voltage, it may be necessary to use the VDD HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its REXT owncharacteristics, the user should Internal OSC1 consult the resonator/crystal manufac- Clock turer forappropriate values of external CEXT components, or verify oscillator performance. VSS PIC18FXX20 OSC2/CLKO 4: RS may be required to avoid overdriving FOSC/4 crystals with low drive level specification. Recommended values: 3 k  REXT  100 k 5: Always verify oscillator performance over CEXT > 20 pF the VDD and temperature range that is expected for the application. The RCIO Oscillator mode functions like the RC mode, except that the OSC2 pin becomes an additional An external clock source may also be connected to the general purpose I/O pin. The I/O pin becomes bit 6 of OSC1 pin in the HS, XT and LP modes, as shown in PORTA (RA6). Figure2-2. DS39609C-page 22  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 2.4 External Clock Input FIGURE 2-5: EXTERNAL CLOCK INPUT OPERATION The EC and ECIO Oscillator modes require an external (ECIO CONFIGURATION) clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is a maximum Clock from OSC1 1.5 s start-up required after a Power-on Reset, or Ext. System PIC18FXX20 wake-up from Sleep mode. RA6 I/O (OSC2) In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other 2.5 HS/PLL logic. Figure2-4 shows the pin connections for the EC Oscillator mode. A Phase Locked Loop circuit (PLL) is provided as a programmable option for users that want to multiply the FIGURE 2-4: EXTERNAL CLOCK INPUT frequency of the incoming crystal oscillator signal by 4. OPERATION For an input clock frequency of 10 MHz, the internal (EC CONFIGURATION) clock frequency will be multiplied to 40 MHz. This is useful for customers who are concerned with EMI due to high-frequency crystals. Clock from OSC1 The PLL is one of the modes of the FOSC<2:0> config- Ext. System PIC18FXX20 uration bits. The oscillator mode is specified during FOSC/4 OSC2 device programming. The PLL can only be enabled when the oscillator con- The ECIO Oscillator mode functions like the EC mode, figuration bits are programmed for HS mode. If they are except that the OSC2 pin becomes an additional gen- programmed for any other mode, the PLL is not eral purpose I/O pin. The I/O pin becomes bit 6 of enabled and the system clock will come directly from PORTA (RA6). Figure2-5 shows the pin connections OSC1. Also, PLL operation cannot be changed “on- for the ECIO Oscillator mode. the-fly”. To enable or disable it, the controller must either cycle through a Power-on Reset, or switch the clock source from the main oscillator to the Timer1 oscillator and back again. See Section2.6 “Oscillator Switching Feature” for details on oscillator switching. A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out that is called TPLL. FIGURE 2-6: PLL BLOCK DIAGRAM (from Configuration HS Osc bit Register) PLL Enable Phase OSC2 Comparator FIN Loop VCO Crystal FOUT Filter Osc SYSCLK X OSC1 Divide by 4 U M  2003-2013 Microchip Technology Inc. DS39609C-page 23

PIC18F6520/8520/6620/8620/6720/8720 2.6 Oscillator Switching Feature execution mode. Figure2-7 shows a block diagram of the system clock sources. The clock switching feature The PIC18FXX20 devices include a feature that allows is enabled by programming the Oscillator Switching the system clock source to be switched from the main Enable (OSCSEN) bit in Configuration Register 1H to a oscillator to an alternate low-frequency clock source. ‘0’. Clock switching is disabled in an erased device. For the PIC18FXX20 devices, this alternate clock See Section12.0 “Timer1 Module” for further details source is the Timer1 oscillator. If a low-frequency of the Timer1 oscillator. See Section23.0 “Special crystal (32 kHz, for example) has been attached to the Features of the CPU” for Configuration register Timer1 oscillator pins and the Timer1 oscillator has details. been enabled, the device can switch to a low-power FIGURE 2-7: DEVICE CLOCK SOURCES PIC18FXX20 Main Oscillator OSC2 TOSC/4 4 x PLL Sleep OSC1 TOSC M TSCLK U Timer1 Oscillator X TT1P T1OSO T1OSCEN Clock Enable Source T1OSI Oscillator Clock Source Option for other Modules DS39609C-page 24  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 2.6.1 SYSTEM CLOCK SWITCH BIT Note: The Timer1 oscillator must be enabled The system clock source switching is performed under and operating to switch the system clock software control. The system clock switch bit, SCS source. The Timer1 oscillator is enabled (OSCCON<0>), controls the clock switching. When the by setting the T1OSCEN bit in the Timer1 SCS bit is ‘0’, the system clock source comes from the Control register (T1CON). If the Timer1 main oscillator that is selected by the FOSC configura- oscillator is not enabled, then any write to tion bits in Configuration Register 1H. When the SCS the SCS bit will be ignored (SCS bit forced bit is set, the system clock source will come from the cleared) and the main oscillator will Timer1 oscillator. The SCS bit is cleared on all forms of continue to be the system clock source. Reset. REGISTER 2-1: OSCCON REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 — — — — — — — SCS bit 7 bit 0 bit 7-1 Unimplemented: Read as ‘0’ bit 0 SCS: System Clock Switch bit When OSCSEN Configuration bit = 0 and T1OSCEN bit is set: 1 = Switch to Timer1 oscillator/clock pin 0 = Use primary oscillator/clock input pin When OSCSEN and T1OSCEN are in other states: Bit is forced clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 25

PIC18F6520/8520/6620/8620/6720/8720 2.6.2 OSCILLATOR TRANSITIONS A timing diagram indicating the transition from the main oscillator to the Timer1 oscillator is shown in Figure2-8. PIC18FXX20 devices contain circuitry to prevent The Timer1 oscillator is assumed to be running all the “glitches” when switching between oscillator sources. time. After the SCS bit is set, the processor is frozen at Essentially, the circuitry waits for eight rising edges of the next occurring Q1 cycle. After eight synchronization the clock source that the processor is switching to. This cycles are counted from the Timer1 oscillator, operation ensures that the new clock source is stable and that its resumes. No additional delays are required after the pulse width will not be less than the shortest pulse synchronization cycles. width of the two clock sources. FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 TT1P T1OSI 1 2 3 4 5 6 7 8 TSCS OSC1 Internal TOSC System Clock TDLY SCS (OSCCON<0>) Program PC PC + 2 PC + 4 Counter Note1:Delay on internal system clock is eight oscillator cycles for synchronization. The sequence of events that takes place when switch- If the main oscillator is configured for an external ing from the Timer1 oscillator to the main oscillator will crystal (HS, XT, LP), then the transition will take place depend on the mode of the main oscillator. In addition after an oscillator start-up time (TOST) has occurred. A to eight clock cycles of the main oscillator, additional timing diagram, indicating the transition from the delays may take place. Timer1 oscillator to the main oscillator for HS, XT and LP modes, is shown in Figure2-9. FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP) Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 TT1P T1OSI OSC1 1 2 3 4 5 6 7 8 TOST TSCS OSC2 Internal TOSC System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 6 Note1:TOST = 1024 TOSC (drawing not to scale). DS39609C-page 26  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 If the main oscillator is configured for HS-PLL mode, an frequency. A timing diagram, indicating the transition oscillator start-up time (TOST), plus an additional PLL from the Timer1 oscillator to the main oscillator for time-out (TPLL), will occur. The PLL time-out is typically HS-PLL mode, is shown in Figure2-10. 2 ms and allows the PLL to lock to the main oscillator FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL) Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 TOST TPLL OSC2 TOSC TSCS PLL Clock Input 1 2 3 4 5 6 7 8 Internal System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 4 Note1:TOST = 1024 TOSC (drawing not to scale). If the main oscillator is configured in the RC, RCIO, EC indicating the transition from the Timer1 oscillator to the or ECIO modes, there is no oscillator start-up time-out. main oscillator for RC, RCIO, EC and ECIO modes, is Operation will resume after eight cycles of the main shown in Figure2-11. oscillator have been counted. A timing diagram, FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC) Q3 Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI TOSC OSC1 1 2 3 4 5 6 7 8 OSC2 Internal System Clock SCS (OSCCON<0>) TSCS Program Counter PC PC + 2 PC + 4 Note1:RC Oscillator mode assumed.  2003-2013 Microchip Technology Inc. DS39609C-page 27

PIC18F6520/8520/6620/8620/6720/8720 2.7 Effects of Sleep Mode on the 2.8 Power-up Delays On-Chip Oscillator Power up delays are controlled by two timers so that no When the device executes a SLEEP instruction, the on- external Reset circuitry is required for most chip clocks and oscillator are turned off and the device applications. The delays ensure that the device is kept is held at the beginning of an instruction cycle (Q1 in Reset until the device power supply and clock are state). With the oscillator off, the OSC1 and OSC2 stable. For additional information on Reset operation, signals will stop oscillating. Since all the transistor see Section3.0 “Reset”. switching currents have been removed, Sleep mode The first timer is the Power-up Timer (PWRT), which achieves the lowest current consumption of the device optionally provides a fixed delay of 72 ms (nominal) on (only leakage currents). Enabling any on-chip feature power-up only (POR and BOR). The second timer is that will operate during Sleep will increase the current the Oscillator Start-up Timer (OST), intended to keep consumed during Sleep. The user can wake from the chip in Reset until the crystal oscillator is stable. Sleep through external Reset, Watchdog Timer Reset With the PLL enabled (HS/PLL Oscillator mode), the or through an interrupt. time-out sequence following a Power-on Reset is differ- ent from other oscillator modes. The time-out sequence is as follows: First, the PWRT time-out is invoked after a POR time delay has expired. Then, the Oscillator Start-up Timer (OST) is invoked. However, this is still not a sufficient amount of time to allow the PLL to lock at high frequencies. The PWRT timer is used to provide an additional fixed 2 ms (nominal) time-out to allow the PLL ample time to lock to the incoming clock frequency. TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC Floating, external resistor should pull high At logic low RCIO Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating Configured as PORTA, bit 6 EC Floating At logic low LP, XT and HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table3-1 in Section3.0 “Reset” for time-outs due to Sleep and MCLR Reset. DS39609C-page 28  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 3.0 RESET Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal The PIC18FXX20 devices differentiate between operation. Status bits from the RCON register, RI, TO, various kinds of Reset: PD, POR and BOR, are set or cleared differently in a) Power-on Reset (POR) different Reset situations, as indicated in Table3-2. These bits are used in software to determine the nature b) MCLR Reset during normal operation of the Reset. See Table3-3 for a full description of the c) MCLR Reset during Sleep Reset states of all registers. d) Watchdog Timer (WDT) Reset (during normal A simplified block diagram of the On-Chip Reset Circuit operation) is shown in Figure3-1. e) Programmable Brown-out Reset (PBOR) The Enhanced MCU devices have a MCLR noise filter f) RESET Instruction in the MCLR Reset path. The filter will detect and g) Stack Full Reset ignore small pulses. The MCLR pin is not driven low by h) Stack Underflow Reset any internal Resets, including the WDT. Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” on Power-on Reset, MCLR, WDT Reset, Brown- out Reset, MCLR Reset during Sleep and by the RESET instruction. FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESETInstruction Stack Stack Full/Underflow Reset Pointer External Reset WDT MCLR Time-out WDT Reset Module Sleep VDD Rise Power-on Reset Detect VDD Brown-out Reset S BOREN OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1 PWRT On-chip RC OSC(1) 10-bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table3-1 for time-out situations.  2003-2013 Microchip Technology Inc. DS39609C-page 29

PIC18F6520/8520/6620/8620/6720/8720 3.1 Power-on Reset (POR) 3.3 Oscillator Start-up Timer (OST) A Power-on Reset pulse is generated on-chip when The Oscillator Start-up Timer (OST) provides 1024 VDD rise is detected. To take advantage of the POR oscillator cycles (from OSC1 input) delay after the circuitry, tie the MCLR pin through a 1k to 10k PWRT delay is over (parameter #32). This ensures that resistor to VDD. This will eliminate external RC the crystal oscillator or resonator has started and components usually needed to create a Power-on stabilized. Reset delay. A minimum rise rate for VDD is specified The OST time-out is invoked only for XT, LP and HS (parameter D004). For a slow rise time, see Figure3-2. modes and only on Power-on Reset, or wake-up from When the device starts normal operation (i.e., exits the Sleep. Reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to 3.4 PLL Lock Time-out ensure operation. If these conditions are not met, the device must be held in Reset until the operating With the PLL enabled, the time-out sequence following conditions are met. a Power-on Reset is different from other oscillator modes. A portion of the Power-up Timer is used to FIGURE 3-2: EXTERNAL POWER-ON provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock RESET CIRCUIT (FOR time-out (TPLL) is typically 2 ms and follows the SLOW VDD POWER-UP) oscillator start-up time-out. VDD 3.5 Brown-out Reset (BOR) A configuration bit, BOREN, can disable (if clear/ D R programmed), or enable (if set) the Brown-out Reset R1 MCLR circuitry. If VDD falls below parameter D005 for greater than parameter #35, the brown-out situation will reset C PIC18FXX20 the chip. A Reset may not occur if VDD falls below parameter D005 for less than parameter #35. The chip will remain in Brown-out Reset until VDD rises above BVDD. If the Power-up Timer is enabled, it will be invoked after VDD rises above BVDD; it then will keep Note 1: External Power-on Reset circuit is required the chip in Reset for an additional time delay (parame- only if the VDD power-up slope is too slow. ter #33). If VDD drops below BVDD while the Power-up The diode D helps discharge the capacitor Timer is running, the chip will go back into a Brown-out quickly when VDD powers down. Reset and the Power-up Timer will be initialized. Once 2: R < 40 k is recommended to make sure that VDD rises above BVDD, the Power-up Timer will the voltage drop across R does not violate execute the additional time delay. the device’s electrical specification. 3: R1 = 1k to 10k will limit any current flow- 3.6 Time-out Sequence ing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown due to On power-up, the time-out sequence is as follows: Electrostatic Discharge (ESD) or Electrical First, PWRT time-out is invoked after the POR time Overstress (EOS). delay has expired. Then, OST is activated. The total time-out will vary based on oscillator configuration and 3.2 Power-up Timer (PWRT) the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. The Power-up Timer provides a fixed nominal time-out Figures3-3 through3-7 depict time-out sequences on (parameter #33) only on power-up from the POR. The power-up. Power-up Timer operates on an internal RC oscillator. Since the time-outs occur from the POR pulse, the The chip is kept in Reset as long as the PWRT is active. time-outs will expire if MCLR is kept low long enough. The PWRT’s time delay allows VDD to rise to an accept- Bringing MCLR high will begin execution immediately able level. A configuration bit is provided to enable/ (Figure3-5). This is useful for testing purposes, or to disable the PWRT. synchronize more than one PIC18FXX20 device The power-up time delay will vary from chip-to-chip due operating in parallel. to VDD, temperature and process variation. See DC Table3-2 shows the Reset conditions for some Special parameter #33 for details. Function Registers, while Table3-3 shows the Reset conditions for all of the registers. DS39609C-page 30  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) Wake-up from Oscillator Brown-out Sleep or Configuration PWRTE = 0 PWRTE = 1 Oscillator Switch HS with PLL enabled(1) 72 ms + 1024 TOSC 1024 TOSC 72 ms(2) + 1024 TOSC 1024 TOSC + 2 ms + 2ms + 2 ms + 2ms HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms(2) + 1024 TOSC 1024 TOSC EC 72 ms 1.5 s 72 ms(2) 1.5 s(3) External RC 72 ms — 72 ms(2) — Note 1: 2 ms is the nominal time required for the 4xPLL to lock. 2: 72 ms is the nominal power-up timer delay, if implemented. 3: 1.5 s is the recovery time from Sleep. There is no recovery time from oscillator switch. REGISTER 3-1: RCON REGISTER BITS AND POSITIONS R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IPEN — — RI TO PD POR BOR bit 7 bit 0 Note1: Refer to Section4.14 “RCON Register” for bit definitions. TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program RCON Condition RI TO PD POR BOR STKFUL STKUNF Counter Register Power-on Reset 0000h 0--1 1100 1 1 1 0 0 u u MCLR Reset during normal 0000h 0--u uuuu u u u u u u u operation Software Reset during normal 0000h 0--0 uuuu 0 u u u u u u operation Stack Full Reset during normal 0000h 0--u uu11 u u u u u u 1 operation Stack Underflow Reset during 0000h 0--u uu11 u u u u u 1 u normal operation MCLR Reset during Sleep 0000h 0--u 10uu u 1 0 u u u u WDT Reset 0000h 0--u 01uu 1 0 1 u u u u WDT Wake-up PC + 2 u--u 00uu u 0 0 u u u u Brown-out Reset 0000h 0--1 11u0 1 1 1 1 0 u u Interrupt wake-up from Sleep PC + 2(1) u--u 00uu u 1 0 u u u u Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h).  2003-2013 Microchip Technology Inc. DS39609C-page 31

PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TOSU PIC18F6X20 PIC18F8X20 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu(3) TOSL PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu(3) STKPTR PIC18F6X20 PIC18F8X20 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU PIC18F6X20 PIC18F8X20 ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu PCL PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F6X20 PIC18F8X20 0000 000x 0000 000u uuuu uuuu(1) INTCON2 PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu(1) INTCON3 PIC18F6X20 PIC18F8X20 1100 0000 1100 0000 uuuu uuuu(1) INDF0 PIC18F6X20 PIC18F8X20 N/A N/A N/A POSTINC0 PIC18F6X20 PIC18F8X20 N/A N/A N/A POSTDEC0 PIC18F6X20 PIC18F8X20 N/A N/A N/A PREINC0 PIC18F6X20 PIC18F8X20 N/A N/A N/A PLUSW0 PIC18F6X20 PIC18F8X20 N/A N/A N/A FSR0H PIC18F6X20 PIC18F8X20 ---- xxxx ---- uuuu ---- uuuu FSR0L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F6X20 PIC18F8X20 N/A N/A N/A POSTINC1 PIC18F6X20 PIC18F8X20 N/A N/A N/A POSTDEC1 PIC18F6X20 PIC18F8X20 N/A N/A N/A PREINC1 PIC18F6X20 PIC18F8X20 N/A N/A N/A PLUSW1 PIC18F6X20 PIC18F8X20 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’. DS39609C-page 32  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets FSR1H PIC18F6X20 PIC18F8X20 ---- xxxx ---- uuuu ---- uuuu FSR1L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F6X20 PIC18F8X20 ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F6X20 PIC18F8X20 N/A N/A N/A POSTINC2 PIC18F6X20 PIC18F8X20 N/A N/A N/A POSTDEC2 PIC18F6X20 PIC18F8X20 N/A N/A N/A PREINC2 PIC18F6X20 PIC18F8X20 N/A N/A N/A PLUSW2 PIC18F6X20 PIC18F8X20 N/A N/A N/A FSR2H PIC18F6X20 PIC18F8X20 ---- xxxx ---- uuuu ---- uuuu FSR2L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F6X20 PIC18F8X20 ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F6X20 PIC18F8X20 0000 0000 uuuu uuuu uuuu uuuu TMR0L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F6X20 PIC18F8X20 ---- ---0 ---- ---0 ---- ---u LVDCON PIC18F6X20 PIC18F8X20 --00 0101 --00 0101 --uu uuuu WDTCON PIC18F6X20 PIC18F8X20 ---- ---0 ---- ---0 ---- ---u RCON(4) PIC18F6X20 PIC18F8X20 0--q 11qq 0--q qquu u--u qquu TMR1H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F6X20 PIC18F8X20 0-00 0000 u-uu uuuu u-uu uuuu TMR2 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 1111 1111 T2CON PIC18F6X20 PIC18F8X20 -000 0000 -000 0000 -uuu uuuu SSPBUF PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu SSPSTAT PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu SSPCON1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu SSPCON2 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.  2003-2013 Microchip Technology Inc. DS39609C-page 33

PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets ADRESH PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu ADCON1 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu ADCON2 PIC18F6X20 PIC18F8X20 0--- -000 0--- -000 u--- -uuu CCPR1H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu CCPR2H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu CCPR3H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu CCPR3L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu CCP3CON PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu CVRCON PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu CMCON PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu TMR3H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F6X20 PIC18F8X20 0000 0000 uuuu uuuu uuuu uuuu PSPCON PIC18F6X20 PIC18F8X20 0000 ---- 0000 ---- uuuu ---- SPBRG1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu RCREG1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu TXREG1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu TXSTA1 PIC18F6X20 PIC18F8X20 0000 -010 0000 -010 uuuu -uuu RCSTA1 PIC18F6X20 PIC18F8X20 0000 000x 0000 000x uuuu uuuu EEADRH PIC18F6X20 PIC18F8X20 ---- --00 ---- --00 ---- --uu EEADR PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu EEDATA PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu EECON2 PIC18F6X20 PIC18F8X20 ---- ---- ---- ---- ---- ---- EECON1 PIC18F6X20 PIC18F8X20 xx-0 x000 uu-0 u000 uu-0 u000 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’. DS39609C-page 34  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets IPR3 PIC18F6X20 PIC18F8X20 --11 1111 --11 1111 --uu uuuu PIR3 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu PIE3 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu IPR2 PIC18F6X20 PIC18F8X20 -1-1 1111 -1-1 1111 -u-u uuuu PIR2 PIC18F6X20 PIC18F8X20 -0-0 0000 -0-0 0000 -u-u uuuu(1) PIE2 PIC18F6X20 PIC18F8X20 -0-0 0000 -0-0 0000 -u-u uuuu IPR1 PIC18F6X20 PIC18F8X20 0111 1111 0111 1111 uuuu uuuu PIR1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu(1) PIE1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu MEMCON PIC18F6X20 PIC18F8X20 0-00 --00 0-00 --00 u-uu --uu TRISJ PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu TRISH PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu TRISG PIC18F6X20 PIC18F8X20 ---1 1111 ---1 1111 ---u uuuu TRISF PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu TRISE PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu TRISD PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu TRISA(5,6) PIC18F6X20 PIC18F8X20 -111 1111(5) -111 1111(5) -uuu uuuu(5) LATJ PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu LATH PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu LATG PIC18F6X20 PIC18F8X20 ---x xxxx ---u uuuu ---u uuuu LATF PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu LATE PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu LATD PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu LATC PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5,6) PIC18F6X20 PIC18F8X20 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.  2003-2013 Microchip Technology Inc. DS39609C-page 35

PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets PORTJ PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu PORTH PIC18F6X20 PIC18F8X20 0000 xxxx 0000 uuuu uuuu uuuu PORTG PIC18F6X20 PIC18F8X20 ---x xxxx uuuu uuuu ---u uuuu PORTF PIC18F6X20 PIC18F8X20 x000 0000 u000 0000 u000 0000 PORTE PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu PORTD PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5,6) PIC18F6X20 PIC18F8X20 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5) TMR4 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu PR4 PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu T4CON PIC18F6X20 PIC18F8X20 -000 0000 -000 0000 -uuu uuuu CCPR4H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu CCPR4L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu CCP4CON PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu CCPR5H PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu CCPR5L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu CCP5CON PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu SPBRG2 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu RCREG2 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu TXREG2 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu TXSTA2 PIC18F6X20 PIC18F8X20 0000 -010 0000 -010 uuuu -uuu RCSTA2 PIC18F6X20 PIC18F8X20 0000 000x 0000 000x uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’. DS39609C-page 36  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA 1 k RESISTOR) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  2003-2013 Microchip Technology Inc. DS39609C-page 37

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kRESISTOR) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD VIA 1 kRESISTOR) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL  2 ms max. First three stages of the PWRT timer. DS39609C-page 38  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 4.0 MEMORY ORGANIZATION 4.1.1 PIC18F8X20 PROGRAM MEMORY MODES There are three memory blocks in PIC18FXX20 devices. They are: PIC18F8X20 devices differ significantly from their PIC18 predecessors in their utilization of program • Program Memory memory. In addition to available on-chip Flash program • Data RAM memory, these controllers can also address up to • Data EEPROM 2Mbytes of external program memory through the External Memory Interface. There are four distinct Data and program memory use separate busses, operating modes available to the controllers: which allows for concurrent access of these blocks. Additional detailed information for Flash program • Microprocessor (MP) memory and data EEPROM is provided in Section5.0 • Microprocessor with Boot Block (MPBB) “Flash Program Memory” and Section7.0 “Data • Extended Microcontroller (EMC) EEPROM Memory”, respectively. • Microcontroller (MC) In addition to on-chip Flash, the PIC18F8X20 devices The Program Memory mode is determined by setting are also capable of accessing external program mem- the two Least Significant bits of the CONFIG3L config- ory through an external memory bus. Depending on the uration byte, as shown in Register4-1. (See also selected operating mode (discussed in Section4.1.1 Section23.1 “Configuration Bits” for additional “PIC18F8X20 Program Memory Modes”), the con- details on the device configuration bits.) trollers may access either internal or external program memory exclusively, or both internal and external mem- The Program Memory modes operate as follows: ory in selected blocks. Additional information on the • The Microprocessor Mode permits access only External Memory Interface is provided in Section6.0 to external program memory; the contents of the “External Memory Interface”. on-chip Flash memory are ignored. The 21-bit program counter permits access to a 2-Mbyte 4.1 Program Memory Organization linear program memory space. • The Microprocessor with Boot Block Mode A 21-bit program counter is capable of addressing the accesses on-chip Flash memory from addresses 2-Mbyte program memory space. Accessing a location 000000h to 0007FFh for PIC18F8520 devices between the physically implemented memory and the and from 000000h to 0001FFh for PIC18F8620 2-Mbyte address will cause a read of all ‘0’s (a NOP and PIC18F8720 devices. Above this, external instruction). program memory is accessed all the way up to Devices in the PIC18FXX20 family can be divided into the 2-Mbyte limit. Program execution automati- three groups, based on program memory size. The cally switches between the two memories, as PIC18FX520 devices (PIC18F6520 and PIC18F8520) required. have 32Kbytes of on-chip Flash memory, equivalent to • The Microcontroller Mode accesses only on- 16,384 single-word instructions. The PIC18FX620 chip Flash memory. Attempts to read above the devices (PIC18F6620 and PIC18F8620) have physical limit of the on-chip Flash (7FFFh for the 64Kbytes of on-chip Flash memory, equivalent to PIC18F8520, 0FFFFh for the PIC18F8620, 32,768 single-word instructions. Finally, the 1FFFFh for the PIC18F8720) causes a read of all PIC18FX720 devices (PIC18F6720 and PIC18F8720) ‘0’s (a NOP instruction). The Microcontroller mode have 128Kbytes of on-chip Flash memory, equivalent is also the only operating mode available to to 65,536 single-word instructions. PIC18F6X20 devices. For all devices, the Reset vector address is at 0000h • The Extended Microcontroller Mode allows and the interrupt vector addresses are at 0008h and access to both internal and external program 0018h. memories as a single block. The device can The program memory maps for all of the PIC18FXX20 access its entire on-chip Flash memory; above devices are compared in Figure4-1. this, the device accesses external program memory up to the 2-Mbyte program space limit. As with Boot Block mode, execution automatically switches between the two memories, as required. In all modes, the microcontroller has complete access to data RAM and EEPROM. Figure4-2 compares the memory maps of the different Program Memory modes. The differences between on- chip and external memory access limitations are more fully explained in Table4-1.  2003-2013 Microchip Technology Inc. DS39609C-page 39

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-1: INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18FXX20 DEVICES PC<20:0> CALL,RCALL,RETURN 21 RETFIE,RETLW Stack Level 1    Stack Level 31 000000h 000000h 000000h Reset Vector 000008h 000008h 000008h High Priority Interrupt Vector 000018h 000018h 000018h Low Priority Interrupt Vector On-Chip Flash Program Memory 007FFFh On-Chip Flash Program Memory 008000h On-Chip Flash Program Memory ce 00FFFFh a p 010000h S y or m e M er s U 01FFFFh 020000h Read ‘0’ Read ‘0’ Read ‘0’ 1FFFFFh 1FFFFFh 1FFFFFh 200000h 200000h 200000h PIC18FX520 PIC18FX620 PIC18FX720 (32Kbyte) (64Kbyte) (128Kbyte) Note: Size of memory regions not to scale. TABLE 4-1: MEMORY ACCESS FOR PIC18F8X20 PROGRAM MEMORY MODES Internal Program Memory External Program Memory Operating Mode Execution Table Read Execution Table Read Table Write To Table Write To From From From From Microprocessor No Access No Access No Access Yes Yes Yes Microprocessor Yes Yes Yes Yes Yes Yes with Boot Block Microcontroller Yes Yes Yes No Access No Access No Access Extended Yes Yes Yes Yes Yes Yes Microcontroller DS39609C-page 40  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 4-1: CONFIG3L CONFIGURATION BYTE R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT — — — — — PM1 PM0 bit 7 bit 0 bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections unavailable, device will not wait 0 = Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>) bit 6-2 Unimplemented: Read as ‘0’ bit 1-0 PM1:PM0: Processor Data Memory Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode 01 = Microcontroller with Boot Block mode 00 = Extended Microcontroller mode Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value after erase ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown FIGURE 4-2: MEMORY MAPS FOR PIC18F8X20 PROGRAM MEMORY MODES Microprocessor Extended Microprocessor Microcontroller with Boot Block Microcontroller Mode (MP) Mode (MC) Mode (MPBB) Mode (EMC) 000000h On-Chip 000000h 000000h 000000h Program On-Chip On-Chip On-Chip Memory Program Program Program (No Memory Memory Memory access) n Boot Boundary Boundary o Boot+1 Boundary+1 Boundary+1 uti ec External x ace E PMreomgroarmy External R e‘0a’sds External p S Program Program m Memory Memory a gr o Pr 1FFFFFh 1FFFFFh 1FFFFFh 1FFFFFh External On-Chip External On-Chip On-Chip External On-Chip Memory Flash Memory Flash Flash Memory Flash Boundary Values for Microprocessor with Boot Block, Microcontroller and Extended Microcontroller modes(1) Available Device Boot Boot+1 Boundary Boundary+1 Memory Mode(s) PIC18F6520 0007FFh 000800h 007FFFh 008000h MC PIC18F6620 0001FFh 000200h 00FFFFh 010000h MC PIC18F6720 0001FFh 000200h 01FFFFh 020000h MC PIC18F8520 0007FFh 000800h 007FFFh 008000h MP, MPBB, MC, EMC PIC18F8620 0001FFh 000200h 00FFFFh 010000h MP, MPBB, MC, EMC PIC18F8720 0001FFh 000200h 01FFFFh 020000h MP, MPBB, MC, EMC Note1: PIC18F6X20 devices are included here for completeness, to show the boundaries of their Boot Blocks and program memory spaces.  2003-2013 Microchip Technology Inc. DS39609C-page 41

PIC18F6520/8520/6620/8620/6720/8720 4.2 Return Address Stack 4.2.2 RETURN STACK POINTER (STKPTR) The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC The STKPTR register contains the stack pointer value, (Program Counter) is pushed onto the stack when a the STKFUL (Stack Full) status bit and the STKUNF CALL or RCALL instruction is executed, or an interrupt (Stack Underflow) status bits. Register4-2 shows the is Acknowledged. The PC value is pulled off the stack STKPTR register. The value of the stack pointer can be on a RETURN, RETLW or a RETFIE instruction. PCLATU 0 through 31. The stack pointer increments when val- and PCLATH are not affected by any of the RETURN or ues are pushed onto the stack and decrements when CALL instructions. values are popped off the stack. At Reset, the stack pointer value will be ‘0’. The user may read and write The stack operates as a 31-word by 21-bit RAM and a the stack pointer value. This feature can be used by a 5-bit stack pointer, with the stack pointer initialized to Real-Time Operating System for return stack 00000b after all Resets. There is no RAM associated maintenance. with stack pointer 00000b. This is only a Reset value. During a CALL type instruction, causing a push onto the After the PC is pushed onto the stack 31 times (without stack, the stack pointer is first incremented and the popping any values off the stack), the STKFUL bit is RAM location pointed to by the stack pointer is written set. The STKFUL bit can only be cleared in software or with the contents of the PC. During a RETURN type by a POR. instruction, causing a pop from the stack, the contents The action that takes place when the stack becomes of the RAM location pointed to by the STKPTR are full, depends on the state of the STVREN (Stack Over- transferred to the PC and then the stack pointer is flow Reset Enable) configuration bit. Refer to decremented. Section24.0 “Instruction Set Summary” for a The stack space is not part of either program or data description of the device configuration bits. If STVREN space. The stack pointer is readable and writable and is set (default), the 31st push will push the (PC + 2) the address on the top of the stack is readable and writ- value onto the stack, set the STKFUL bit and reset the able through SFR registers. Data can also be pushed device. The STKFUL bit will remain set and the stack to, or popped from the stack using the top-of-stack pointer will be set to ‘0’. SFRs. Status bits indicate if the stack pointer is at, or If STVREN is cleared, the STKFUL bit will be set on the beyond the 31 levels provided. 31st push and the stack pointer will increment to 31. Any additional pushes will not overwrite the 31st push 4.2.1 TOP-OF-STACK ACCESS and STKPTR will remain at 31. The top of the stack is readable and writable. Three When the stack has been popped enough times to register locations, TOSU, TOSH and TOSL, hold the unload the stack, the next pop will return a value of zero contents of the stack location pointed to by the to the PC and sets the STKUNF bit, while the stack STKPTR register. This allows users to implement a pointer remains at ‘0’. The STKUNF bit will remain set software stack if necessary. After a CALL, RCALL or until cleared in software or a POR occurs. interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These Note: Returning a value of zero to the PC on an values can be placed on a user defined software stack. underflow has the effect of vectoring the At return time, the software can replace the TOSU, program to the Reset vector, where the TOSH and TOSL and do a return. stack conditions can be verified and appropriate actions can be taken. The user must disable the global interrupt enable bits during this time to prevent inadvertent stack operations. DS39609C-page 42  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 4-2: STKPTR REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note1: Bit 7 and bit 6 can only be cleared in user software or by a POR. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown FIGURE 4-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU TOSH TOSL STKPTR<4:0> 0x00 0x1A 0x34 00010 00011 Top-of-Stack 0x001A34 00010 0x000D58 00001 00000 4.2.3 PUSH AND POP INSTRUCTIONS 4.2.4 STACK FULL/UNDERFLOW RESETS Since the Top-of-Stack (TOS) is readable and writable, These Resets are enabled by programming the the ability to push values onto the stack and pull values STVREN configuration bit. When the STVREN bit is off the stack, without disturbing normal program disabled, a full or underflow condition will set the execution, is a desirable option. To push the current PC appropriate STKFUL or STKUNF bit, but not cause a value onto the stack, a PUSH instruction can be device Reset. When the STVREN bit is enabled, a full executed. This will increment the stack pointer and load or underflow condition will set the appropriate STKFUL the current PC value onto the stack. TOSU, TOSH and or STKUNF bit and then cause a device Reset. The TOSL can then be modified to place a return address STKFUL or STKUNF bits are only cleared by the user on the stack. software or a POR Reset. The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value.  2003-2013 Microchip Technology Inc. DS39609C-page 43

PIC18F6520/8520/6620/8620/6720/8720 4.3 Fast Register Stack 4.4 PCL, PCLATH and PCLATU A “fast interrupt return” option is available for interrupts. The program counter (PC) specifies the address of the A Fast Register Stack is provided for the Status, WREG instruction to fetch for execution. The PC is 21 bits and BSR registers and is only one in depth. The stack wide. The low byte is called the PCL register; this reg- is not readable or writable and is loaded with the ister is readable and writable. The high byte is called current value of the corresponding register when the the PCH register. This register contains the PC<15:8> processor vectors for an interrupt. The values in the bits and is not directly readable or writable; updates to registers are then loaded back into the working regis- the PCH register may be performed through the ters, if the FAST RETURN instruction is used to return PCLATH register. The upper byte is called PCU. This from the interrupt. register contains the PC<20:16> bits and is not directly readable or writable; updates to the PCU register may A low or high priority interrupt source will push values be performed through the PCLATU register. into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be The PC addresses bytes in the program memory. To used reliably for low priority interrupts. If a high priority prevent the PC from becoming misaligned with word interrupt occurs while servicing a low priority interrupt, instructions, the LSB of the PCL is fixed to a value of the stack register values stored by the low priority ‘0’. The PC increments by 2 to address sequential interrupt will be overwritten. instructions in the program memory. If high priority interrupts are not disabled during low The CALL, RCALL, GOTO and program branch priority interrupts, users must save the key registers in instructions write to the program counter directly. For software during a low priority interrupt. these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. If no interrupts are used, the fast register stack can be used to restore the Status, WREG and BSR registers at The contents of PCLATH and PCLATU will be trans- the end of a subroutine call. To use the fast register ferred to the program counter by an operation that stack for a subroutine call, a FAST CALL instruction writes PCL. Similarly, the upper two bytes of the must be executed. program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful Example4-1 shows a source code example that uses for computed offsets to the PC (see Section4.8.1 the fast register stack. “Computed GOTO”). EXAMPLE 4-1: FAST REGISTER STACK 4.5 Clocking Scheme/Instruction CODE EXAMPLE Cycle CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER The clock input (from OSC1) is internally divided by ;STACK four to generate four non-overlapping quadrature  clocks, namely Q1, Q2, Q3 and Q4. Internally, the  program counter (PC) is incremented every Q1, the SUB1  instruction is fetched from the program memory and  latched into the instruction register in Q4. The instruc-  tion is decoded and executed during the following Q1 RETURN FAST ;RESTORE VALUES SAVED through Q4. The clocks and instruction execution flow ;IN FAST REGISTER STACK are shown in Figure4-4. FIGURE 4-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC+2 PC+4 OSC2/CLKO (RC mode) Execute INST (PC-2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+2) Fetch INST (PC+4) DS39609C-page 44  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 4.6 Instruction Flow/Pipelining A fetch cycle begins with the program counter (PC) incrementing in Q1. An “Instruction Cycle” consists of four Q cycles (Q1, In the execution cycle, the fetched instruction is latched Q2, Q3 and Q4). The instruction fetch and execute are into the “Instruction Register” (IR) in cycle Q1. This pipelined, such that fetch takes one instruction cycle, instruction is then decoded and executed during the while decode and execute takes another instruction Q2, Q3 and Q4 cycles. Data memory is read during Q2 cycle. However, due to the pipelining, each instruction (operand read) and written during Q4 (destination effectively executes in one cycle. If an instruction write). causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example4-2). EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 4.7 Instructions in Program Memory word boundaries, the data contained in the instruction is a word address. The word address is written to The program memory is addressed in bytes. Instruc- PC<20:1>, which accesses the desired byte address in tions are stored as two bytes or four bytes in program program memory. Instruction #2 in Figure4-5 shows memory. The Least Significant Byte of an instruction how the instruction “GOTO 000006h” is encoded in the word is always stored in a program memory location program memory. Program branch instructions, which with an even address (LSB = 0). Figure4-5 shows an encode a relative address offset, operate in the same example of how instruction words are stored in the pro- manner. The offset value stored in a branch instruction gram memory. To maintain alignment with instruction represents the number of single-word instructions that boundaries, the PC increments in steps of 2 and the the PC will be offset by. Section24.0 “Instruction Set LSB will always read ‘0’ (see Section4.4 “PCL, Summary” provides further details of the instruction PCLATH and PCLATU”). set. The CALL and GOTO instructions have an absolute program memory address embedded into the instruction. Since instructions are always stored on FIGURE 4-5: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0  Program Memory 000000h Byte Locations  000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 000006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h  2003-2013 Microchip Technology Inc. DS39609C-page 45

PIC18F6520/8520/6620/8620/6720/8720 4.7.1 TWO-WORD INSTRUCTIONS word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is The PIC18FXX20 devices have four two-word instruc- necessary when the two-word instruction is preceded tions: MOVFF, CALL, GOTO and LFSR. The second word by a conditional instruction that changes the PC. A pro- of these instructions has the 4 MSBs set to ‘1’s and is gram example that demonstrates this concept is shown a special kind of NOP instruction. The lower 12 bits of in Example4-3. Refer to Section24.0 “Instruction the second word contain data to be used by the instruc- Set Summary” for further details of the instruction set. tion. If the first word of the instruction is executed, the data in the second word is accessed. If the second EXAMPLE 4-3: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction 1111 0100 0101 0110 ; 2nd operand holds address of REG2 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes 1111 0100 0101 0110 ; 2nd operand becomes NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code 4.8 Look-up Tables 4.8.2 TABLE READS/TABLE WRITES Look-up tables are implemented two ways. These are: A better method of storing data in program memory allows 2 bytes of data to be stored in each instruction • Computed GOTO location. • Table Reads Look-up table data may be stored 2 bytes per program 4.8.1 COMPUTED GOTO word by using table reads and writes. The Table Pointer (TBLPTR) specifies the byte address and the Table A computed GOTO is accomplished by adding an offset Latch (TABLAT) contains the data that is read from, or to the program counter (ADDWF PCL). written to program memory. Data is transferred to/from A look-up table can be formed with an ADDWF PCL program memory, one byte at a time. instruction and a group of RETLW 0xnn instructions. A description of the table read/table write operation is WREG is loaded with an offset into the table before shown in Section5.0 “Flash Program Memory”. executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions, that returns the value 0xnn to the calling function. The offset value (value in WREG) specifies the number of bytes that the program counter should advance. In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. DS39609C-page 46  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 4.9 Data Memory Organization 4.9.1 GENERAL PURPOSE REGISTER FILE The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, The register file can be accessed either directly or indi- allowing up to 4096 bytes of data memory. The data rectly. Indirect addressing operates using a File Select memory map is in turn divided into 16 banks of Register and corresponding Indirect File Operand. The 256bytes each. The lower 4 bits of the Bank Select operation of indirect addressing is shown in Register (BSR<3:0>) select which bank will be Section4.12 “Indirect Addressing, INDF and FSR accessed. The upper 4 bits of the BSR are not Registers”. implemented. Enhanced MCU devices may have banked memory in The data memory space contains both Special Func- the GPR area. GPRs are not initialized by a Power-on tion Registers (SFR) and General Purpose Registers Reset and are unchanged on all other Resets. (GPR). The SFRs are used for control and status of the Data RAM is available for use as General Purpose controller and peripheral functions, while GPRs are Registers by all instructions. The top section of Bank 15 used for data storage and scratch pad operations in the (F60h to FFFh) contains SFRs. All other banks of data user’s application. The SFRs start at the last location of memory contain GPR registers, starting with Bank 0. Bank 15 (0FFFh) and extend downwards. Any remain- ing space beyond the SFRs in the Bank may be imple- 4.9.2 SPECIAL FUNCTION REGISTERS mented as GPRs. GPRs start at the first location of The Special Function Registers (SFRs) are registers Bank 0 and grow upwards. Any read of an used by the CPU and peripheral modules for controlling unimplemented location will read as ‘0’s. the desired operation of the device. These registers are PIC18FX520 devices have 2048bytes of data RAM, implemented as static RAM. A list of these registers is extending from Bank 0 to Bank 7 (000h through 7FFh). given in Table4-2 and Table4-3. PIC18FX620 and PIC18FX720 devices have The SFRs can be classified into two sets: those asso- 3840bytes of data RAM, extending from Bank 0 to ciated with the “core” function and those related to the Bank 14 (000h through EFFh). The organization of the peripheral functions. Those registers related to the data memory space for these devices is shown in “core” are described in this section, while those related Figure4-6 and Figure4-7. to the operation of the peripheral features are The entire data memory may be accessed directly or described in the section of that peripheral feature. The indirectly. Direct addressing may require the use of the SFRs are typically distributed among the peripherals BSR register. Indirect addressing requires the use of a whose functions they control. File Select Register (FSRn) and a corresponding Indi- The unused SFR locations are unimplemented and rect File Operand (INDFn). Each FSR holds a 12-bit read as ‘0’s. The addresses for the SFRs are listed in address value that can be used to access any location Table4-2. in the data memory map without banking. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect addressing, or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section4.10 “Access Bank” provides a detailed description of the Access RAM.  2003-2013 Microchip Technology Inc. DS39609C-page 47

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-6: DATA MEMORY MAP FOR PIC18FX520 DEVICES BSR<3:0> Data Memory Map 000h = 0000 00h Access RAM 05Fh Bank 0 060h GPRs FFh 0FFh 00h 100h = 0001 GPRs Bank 1 FFh 1FFh 200h = 0010 00h Bank 2 GPRs FFh 2FFh = 0011 00h 300h Bank 3   to GPRs  Bank 6 = 0110 Access Bank FFh 6FFh 00h = 0111 00h 700h Access RAM Low 5Fh Bank 7 GPRs 60h Access RAM High FFh 7FFh (SFRs) 800h FFh = 1000  Bank 8 Unused, When a = 0, to Read as ‘0’  the BSR is ignored and the Bank 14  Access Bank is used. The first 96 bytes are General Purpose RAM (from Bank 0). = 1110 The second 160 bytes are Special Function Registers EFFh (from Bank 15). 00h F00h = 1111 Unused F5Fh Bank 15 F60h FFh SFRs FFFh When a = 1, the BSR is used to specify the RAM location that the instruction uses. DS39609C-page 48  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-7: DATA MEMORY MAP FOR PIC18FX620 AND PIC18FX720 DEVICES BSR<3:0> Data Memory Map 000h = 0000 00h Access RAM 05Fh Bank 0 060h GPRs FFh 0FFh 00h 100h = 0001 GPRs Bank 1 FFh 1FFh 200h = 0010 00h Bank 2 GPRs FFh 2FFh 00h 300h = 0011 Bank 3 GPRs FFh 3FFh 400h = 0100 Bank 4 GPRs Access Bank 4FFh 00h = 0101 500h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh  Bank 5 to  Bank 13  GPRs When a = 0, the BSR is ignored and the = 1101 Access Bank is used. The first 96 bytes are General DFFh Purpose RAM (from Bank 0). = 1110 00h E00h The second 160 bytes are Bank 14 GPRs Special Function Registers FFh EFFh (from Bank 15). 00h F00h = 1111 Unused F5Fh Bank 15 F60h FFh SFRs FFFh When a = 1, the BSR is used to specify the RAM location that the instruction uses.  2003-2013 Microchip Technology Inc. DS39609C-page 49

PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(3) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H F9Ch MEMCON(2) FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh —(1) FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ FF9h PCL FD9h FSR2L FB9h CCPR3H F99h TRISH FF8h TBLPTRU FD8h STATUS FB8h CCPR3L F98h TRISG FF7h TBLPTRH FD7h TMR0H FB7h CCP3CON F97h TRISF FF6h TBLPTRL FD6h TMR0L FB6h —(1) F96h TRISE FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD FF4h PRODH FD4h —(1) FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH FEFh INDF0(3) FCFh TMR1H FAFh SPBRG1 F8Fh LATG FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG1 F8Eh LATF FEDh POSTDEC0(3) FCDh T1CON FADh TXREG1 F8Dh LATE FECh PREINC0(3) FCCh TMR2 FACh TXSTA1 F8Ch LATD FEBh PLUSW0(3) FCBh PR2 FABh RCSTA1 F8Bh LATC FEAh FSR0H FCAh T2CON FAAh EEADRH F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h PORTJ FE7h INDF1(3) FC7h SSPSTAT FA7h EECON2 F87h PORTH FE6h POSTINC1(3) FC6h SSPCON1 FA6h EECON1 F86h PORTG FE5h POSTDEC1(3) FC5h SSPCON2 FA5h IPR3 F85h PORTF FE4h PREINC1(3) FC4h ADRESH FA4h PIR3 F84h PORTE FE3h PLUSW1(3) FC3h ADRESL FA3h PIE3 F83h PORTD FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: Unimplemented registers are read as ‘0’. 2: This register is unused on PIC18F6X20 devices. Always maintain this register clear. 3: This is not a physical register. DS39609C-page 50  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name Address Name Address Name Address Name F7Fh —(1) F5Fh —(1) F3Fh —(1) F1Fh —(1) F7Eh —(1) F5Eh —(1) F3Eh —(1) F1Eh —(1) F7Dh —(1) F5Dh —(1) F3Dh —(1) F1Dh —(1) F7Ch —(1) F5Ch —(1) F3Ch —(1) F1Ch —(1) F7Bh —(1) F5Bh —(1) F3Bh —(1) F1Bh —(1) F7Ah —(1) F5Ah —(1) F3Ah —(1) F1Ah —(1) F79h —(1) F59h —(1) F39h —(1) F19h —(1) F78h TMR4 F58h —(1) F38h —(1) F18h —(1) F77h PR4 F57h —(1) F37h —(1) F17h —(1) F76h T4CON F56h —(1) F36h —(1) F16h —(1) F75h CCPR4H F55h —(1) F35h —(1) F15h —(1) F74h CCPR4L F54h —(1) F34h —(1) F14h —(1) F73h CCP4CON F53h —(1) F33h —(1) F13h —(1) F72h CCPR5H F52h —(1) F32h —(1) F12h —(1) F71h CCPR5L F51h —(1) F31h —(1) F11h —(1) F70h CCP5CON F50h —(1) F30h —(1) F10h —(1) F6Fh SPBRG2 F4Fh —(1) F2Fh —(1) F0Fh —(1) F6Eh RCREG2 F4Eh —(1) F2Eh —(1) F0Eh —(1) F6Dh TXREG2 F4Dh —(1) F2Dh —(1) F0Dh —(1) F6Ch TXSTA2 F4Ch —(1) F2Ch —(1) F0Ch —(1) F6Bh RCSTA2 F4Bh —(1) F2Bh —(1) F0Bh —(1) F6Ah —(1) F4Ah —(1) F2Ah —(1) F0Ah —(1) F69h —(1) F49h —(1) F29h —(1) F09h —(1) F68h —(1) F48h —(1) F28h —(1) F08h —(1) F67h —(1) F47h —(1) F27h —(1) F07h —(1) F66h —(1) F46h —(1) F26h —(1) F06h —(1) F65h —(1) F45h —(1) F25h —(1) F05h —(1) F64h —(1) F44h —(1) F24h —(1) F04h —(1) F63h —(1) F43h —(1) F23h —(1) F03h —(1) F62h —(1) F42h —(1) F22h —(1) F02h —(1) F61h —(1) F41h —(1) F21h —(1) F01h —(1) F60h —(1) F40h —(1) F20h —(1) F00h —(1) Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X20 devices. 3: This is not a physical register.  2003-2013 Microchip Technology Inc. DS39609C-page 51

PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: REGISTER FILE SUMMARY Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 32, 42 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 32, 42 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 32, 42 STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 32, 43 PCLATU — — bit 21 Holding Register for PC<20:16> --10 0000 32, 44 PCLATH Holding Register for PC<15:8> 0000 0000 32, 44 PCL PC Low Byte (PC<7:0>) 0000 0000 32, 44 TBLPTRU — — bit 21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 32, 64 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 32, 64 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 32, 64 TABLAT Program Memory Table Latch 0000 0000 32, 64 PRODH Product Register High Byte xxxx xxxx 32, 85 PRODL Product Register Low Byte xxxx xxxx 32, 85 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 32, 89 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 32, 90 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 32, 91 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) n/a 57 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented n/a 57 (not a physical register) POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented n/a 57 (not a physical register) PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) n/a 57 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented n/a 57 (not a physical register) – value of FSR0 offset by value in WREG FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 32, 57 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 32, 57 WREG Working Register xxxx xxxx 32 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) n/a 57 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented n/a 57 (not a physical register) POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented n/a 57 (not a physical register) PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented n/a 57 (not a physical register) PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented n/a 57 (not a physical register) – value of FSR1 offset by value in WREG FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 33, 57 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 33, 57 BSR — — — — Bank Select Register ---- 0000 33, 56 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) n/a 57 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented n/a 57 (not a physical register) POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented n/a 57 (not a physical register) Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X20 devices; always maintain these clear. DS39609C-page 52  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented n/a 57 (not a physical register) PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented n/a 57 (not a physical register) – value of FSR2 offset by value in WREG FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 33, 57 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 33, 57 STATUS — — — N OV Z DC C ---x xxxx 33, 59 TMR0H Timer0 Register High Byte 0000 0000 33, 133 TMR0L Timer0 Register Low Byte xxxx xxxx 33, 133 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 33, 131 OSCCON — — — — — — — SCS ---- ---0 25, 33 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 33, 235 WDTCON — — — — — — — SWDTE ---- ---0 33, 250 RCON IPEN — — RI TO PD POR BOR 0--1 11qq 33, 60, 101 TMR1H Timer1 Register High Byte xxxx xxxx 33, 135 TMR1L Timer1 Register Low Byte xxxx xxxx 33, 135 T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 33, 135 TMR2 Timer2 Register 0000 0000 33, 141 PR2 Timer2 Period Register 1111 1111 33, 142 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 33, 141 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 33, 157 SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 33, 166 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 33, 158 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 33, 168 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 33, 169 ADRESH A/D Result Register High Byte xxxx xxxx 34, 215 ADRESL A/D Result Register Low Byte xxxx xxxx 34, 215 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 34, 213 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 34, 214 ADCON2 ADFM — — — — ADCS2 ADCS1 ADCS0 0--- -000 34, 215 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 34, 151, 152 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 34, 151, 152 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 34, 149 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 34, 151, 152 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 34, 151, 152 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 34, 149 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X20 devices; always maintain these clear.  2003-2013 Microchip Technology Inc. DS39609C-page 53

PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx 34, 151, 152 CCPR3L Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 34, 151, 152 CCP3CON — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 34, 149 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 34, 229 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 34, 223 TMR3H Timer3 Register High Byte xxxx xxxx 34, 143 TMR3L Timer3 Register Low Byte xxxx xxxx 34, 143 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 34, 143 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 34, 129 SPBRG1 USART1 Baud Rate Generator 0000 0000 34, 205 RCREG1 USART1 Receive Register 0000 0000 34, 206 TXREG1 USART1 Transmit Register 0000 0000 34, 204 TXSTA1 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 34, 198 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 34, 199 EEADRH — — — — — — EE Adr Register High ---- --00 34, 79 EEADR Data EEPROM Address Register 0000 0000 34, 79 EEDATA Data EEPROM Data Register 0000 0000 34, 79 EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 34, 79 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 34, 80 IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 35, 100 PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 35, 94 PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 35, 97 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 35, 99 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 35, 93 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 35, 96 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 35, 98 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 35, 92 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 35, 95 MEMCON(3) EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 35, 71 TRISJ(3) Data Direction Control Register for PORTJ 1111 1111 35, 125 TRISH(3) Data Direction Control Register for PORTH 1111 1111 35, 122 TRISG — — — Data Direction Control Register for PORTG ---1 1111 35, 120 TRISF Data Direction Control Register for PORTF 1111 1111 35, 117 TRISE Data Direction Control Register for PORTE 1111 1111 35, 114 TRISD Data Direction Control Register for PORTD 1111 1111 35, 111 TRISC Data Direction Control Register for PORTC 1111 1111 35, 109 TRISB Data Direction Control Register for PORTB 1111 1111 35, 106 TRISA — TRISA6(1) Data Direction Control Register for PORTA -111 1111 35, 103 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X20 devices; always maintain these clear. DS39609C-page 54  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: LATJ(3) Read PORTJ Data Latch, Write PORTJ Data Latch xxxx xxxx 35, 125 LATH(3) Read PORTH Data Latch, Write PORTH Data Latch xxxx xxxx 35, 122 LATG — — — Read PORTG Data Latch, Write PORTG Data Latch ---x xxxx 35, 120 LATF Read PORTF Data Latch, Write PORTF Data Latch xxxx xxxx 35, 117 LATE Read PORTE Data Latch, Write PORTE Data Latch xxxx xxxx 35, 114 LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 35, 111 LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 35, 109 LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 35, 106 LATA — LATA6(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 35, 103 PORTJ(3) Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 36, 125 PORTH(3) Read PORTH pins, Write PORTH Data Latch xxxx xxxx 36, 122 PORTG — — — Read PORTG pins, Write PORTG Data Latch ---x xxxx 36, 120 PORTF Read PORTF pins, Write PORTF Data Latch xxxx xxxx 36, 117 PORTE Read PORTE pins, Write PORTE Data Latch xxxx xxxx 36, 114 PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 36, 111 PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 36, 109 PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 36, 106 PORTA — RA6(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 36, 103 TMR4 Timer4 Register 0000 0000 36, 148 PR4 Timer4 Period Register 1111 1111 36, 148 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 36, 147 CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 36, 151, 152 CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 36, 151, 152 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 0000 0000 36, 149 CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 36, 151, 152 CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 36, 151, 152 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 0000 0000 36, 149 SPBRG2 USART2 Baud Rate Generator 0000 0000 36, 205 RCREG2 USART2 Receive Register 0000 0000 36, 206 TXREG2 USART2 Transmit Register 0000 0000 36, 204 TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 36, 198 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 36, 199 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X20 devices; always maintain these clear.  2003-2013 Microchip Technology Inc. DS39609C-page 55

PIC18F6520/8520/6620/8620/6720/8720 4.10 Access Bank 4.11 Bank Select Register (BSR) The Access Bank is an architectural enhancement, The need for a large general purpose memory space which is very useful for C compiler code optimization. dictates a RAM banking scheme. The data memory is The techniques used by the C compiler may also be partitioned into sixteen banks. When using direct useful for programs written in assembly. addressing, the BSR should be configured for the desired bank. This data memory region can be used for: BSR<3:0> holds the upper 4 bits of the 12-bit RAM • Intermediate computational values address. The BSR<7:4> bits will always read ‘0’s and • Local variables of subroutines writes will have no effect. • Faster context saving/switching of variables A MOVLB instruction has been provided in the • Common variables instruction set to assist in selecting banks. • Faster evaluation/control of SFRs (no banking) If the currently selected bank is not implemented, any The Access Bank is comprised of the upper 160 bytes read will return all ‘0’s and all writes are ignored. The in Bank 15 (SFRs) and the lower 96 bytes in Bank 0. Status register bits will be set/cleared as appropriate for These two sections will be referred to as Access RAM the instruction performed. High and Access RAM Low, respectively. Figure4-7 Each Bank extends up to FFh (256 bytes). All data indicates the Access RAM areas. memory is implemented as static RAM. A bit in the instruction word specifies if the operation is A MOVFF instruction ignores the BSR, since the 12-bit to occur in the bank specified by the BSR register or in addresses are embedded into the instruction word. the Access Bank. This bit is denoted by the ‘a’ bit (for access bit). Section4.12 “Indirect Addressing, INDF and FSR Registers” provides a description of indirect address- When forced in the Access Bank (a = 0), the last ing, which allows linear addressing of the entire RAM address in Access RAM Low is followed by the first space. address in Access RAM High. Access RAM High maps the Special Function Registers, so that these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits. FIGURE 4-8: DIRECT ADDRESSING Direct Addressing BSR<3:0> 7 From Opcode(3) 0 Bank Select(2) Location Select(3) 00h 01h 0Eh 0Fh 000h 100h E00h F00h Data Memory(1) 0FFh 1FFh EFFh FFFh Bank 0 Bank 1 Bank 14 Bank 15 Note 1: For register file map detail, see Table4-2. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS39609C-page 56  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 4.12 Indirect Addressing, INDF and the data from the address pointed to by FSR Registers FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. Indirect addressing is a mode of addressing data mem- If INDF0, INDF1 or INDF2 are read indirectly via an ory, where the data memory address in the instruction FSR, all ‘0’s are read (zero bit is set). Similarly, if is not fixed. An FSR register is used as a pointer to the INDF0, INDF1 or INDF2 are written to indirectly, the data memory location that is to be read or written. Since operation will be equivalent to a NOP instruction and the this pointer is in RAM, the contents can be modified by Status bits are not affected. the program. This can be useful for data tables in the data memory and for software stacks. Figure4-9 4.12.1 INDIRECT ADDRESSING shows the operation of indirect addressing. This shows OPERATION the moving of the value to the data memory address, specified by the value of the FSR register. Each FSR register has an INDF register associated with it, plus four additional register addresses. Perform- Indirect addressing is possible by using one of the ing an operation on one of these five registers INDF registers. Any instruction using the INDF register determines how the FSR will be modified during actually accesses the register pointed to by the File indirect addressing. Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0), will read 00h. Writing to the INDF When data access is done to one of the five INDFn register indirectly, results in a no operation. The FSR locations, the address selected will configure the FSRn register contains a 12-bit address, which is shown in register to: Figure4-10. • Do nothing to FSRn after an indirect access The INDFn register is not a physical register. Address- (no change) – INDFn. ing INDFn actually addresses the register whose • Auto-decrement FSRn after an indirect access address is contained in the FSRn register (FSRn is a (post-decrement) – POSTDECn. pointer). This is indirect addressing. • Auto-increment FSRn after an indirect access Example4-4 shows a simple use of indirect addressing (post-increment) – POSTINCn. to clear the RAM in Bank 1 (locations 100h-1FFh) in a • Auto-increment FSRn before an indirect access minimum number of instructions. (pre-increment) – PREINCn. • Use the value in the WREG register as an offset EXAMPLE 4-4: HOW TO CLEAR RAM to FSRn. Do not modify the value of the WREG or (BANK 1) USING the FSRn register after an indirect access INDIRECT ADDRESSING (no change) – PLUSWn. LFSR FSR0 ,0x100 ; When using the auto-increment or auto-decrement NEXT CLRF POSTINC0 ; Clear INDF features, the effect on the FSR is not reflected in the ; register and Status register. For example, if the indirect address ; inc pointer causes the FSR to equal ‘0’, the Z bit will not be set. BTFSS FSR0H, 1 ; All done with ; Bank 1? Incrementing or decrementing an FSR affects all 12 GOTO NEXT ; NO, clear next bits. That is, when FSRnL overflows from an increment, CONTINUE ; YES, continue FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a There are three indirect addressing registers. To stack pointer, in addition to its uses for table operations address the entire data memory space (4096 bytes), in data memory. these registers are 12 bits wide. To store the 12 bits of addressing information, two 8-bit registers are Each FSR has an address associated with it that required. These indirect addressing registers are: performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the 1. FSR0: composed of FSR0H:FSR0L FSRn is configured to add the signed value in the 2. FSR1: composed of FSR1H:FSR1L WREG register and the value in FSR to form the 3. FSR2: composed of FSR2H:FSR2L address before an indirect access. The FSR value is not changed. In addition, there are registers INDF0, INDF1 and INDF2, which are not physically implemented. Reading If an FSR register contains a value that points to one of or writing to these registers activates indirect address- the INDFn, an indirect read will read 00h (zero bit is ing, with the value in the corresponding FSR register set), while an indirect write will be equivalent to a NOP being the address of the data. If an instruction writes a (Status bits are not affected). value to INDF0, the value will be written to the address If an indirect addressing operation is done where the tar- pointed to by FSR0H:FSR0L. A read from INDF1 reads get address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or post-increment/ decrement functions.  2003-2013 Microchip Technology Inc. DS39609C-page 57

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-9: INDIRECT ADDRESSING OPERATION 0h RAM Instruction Executed Opcode Address FFFh 12 File Address = Access of an Indirect Addressing Register BSR<3:0> 12 12 Instruction Fetched 4 8 Opcode File FSR FIGURE 4-10: INDIRECT ADDRESSING Indirect Addressing 11 FSR Register 0 Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table4-2. DS39609C-page 58  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 4.13 Status Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as The Status register, shown in Register4-3, contains the 000u u1uu (where u = unchanged). arithmetic status of the ALU. The Status register can be It is recommended, therefore, that only BCF, BSF, the destination for any instruction, as with any other reg- SWAPF, MOVFF and MOVWF instructions are used to alter ister. If the Status register is the destination for an the Status register, because these instructions do not instruction that affects the Z, DC, C, OV or N bits, then affect the Z, C, DC, OV or N bits from the Status regis- the write to these five bits is disabled. These bits are set ter. For other instructions not affecting any status bits, or cleared according to the device logic. Therefore, the see Table24-1. result of an instruction with the Status register as destination may be different than intended. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. REGISTER 4-3: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. bit 0 C: Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 59

PIC18F6520/8520/6620/8620/6720/8720 4.14 RCON Register Note1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit The Reset Control (RCON) register contains flag bits is ‘1’ on a Power-on Reset. After a Brown- that allow differentiation between the sources of a out Reset has occurred, the BOR bit will device Reset. These flags include the TO, PD, POR, be cleared and must be set by firmware to BOR and RI bits. This register is readable and writable. indicate the occurrence of the next Brown-out Reset. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. REGISTER 4-4: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 60  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 5.0 FLASH PROGRAM MEMORY The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table The Flash program memory is readable, writable and writes move data between these two memory spaces erasable, during normal operation over the entire VDD through an 8-bit register (TABLAT). range. Table read operations retrieve data from program mem- A read from program memory is executed on one byte ory and place it into the data RAM space. Figure 5-1 at a time. A write to program memory is executed on shows the operation of a table read with program blocks of 8 bytes at a time. Program memory is erased memory and data RAM. in blocks of 64 bytes at a time. A bulk erase operation Table write operations store data from the data memory may not be issued from user code. space into holding registers in program memory. The Writing or erasing program memory will cease procedure to write the contents of the holding registers instruction fetches until the operation is complete. The into program memory is detailed in Section5.5 program memory cannot be accessed during the write “Writing to Flash Program Memory”. Figure 5-2 or erase, therefore, code cannot execute. An internal shows the operation of a table write with program programming timer terminates program memory writes memory and data RAM. and erases. Table operations work with byte entities. A table block A value written to program memory does not need to be containing data, rather than program instructions, is not a valid instruction. Executing a program memory required to be word aligned. Therefore, a table block location that forms an invalid instruction results in a can start and end at any byte address. If a table write is NOP. being used to write executable code into program memory, program instructions will need to be word 5.1 Table Reads and Table Writes aligned. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: • Table Read (TBLRD) • Table Write (TBLWT) FIGURE 5-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory.  2003-2013 Microchip Technology Inc. DS39609C-page 61

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 5-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in Section5.5 “Writing to Flash Program Memory”. 5.2 Control Registers The FREE bit, when set, will allow a program memory erase operation. When the FREE bit is set, the erase Several control registers are used in conjunction with operation is initiated on the next WR command. When the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled. • EECON1 register The WREN bit, when set, will allow a write operation. • EECON2 register On power-up, the WREN bit is clear. The WRERR bit is • TABLAT register set when a write operation is interrupted by a MCLR • TBLPTR registers Reset, or a WDT Time-out Reset during normal opera- tion. In these situations, the user can check the 5.2.1 EECON1 AND EECON2 REGISTERS WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EECON1 is the control register for memory accesses. EEADR), due to Reset values of zero. EECON2 is not a physical register. Reading EECON2 The WR control bit, initiates write operations. The bit will read all ‘0’s. The EECON2 register is used cannot be cleared, only set, in software; it is cleared in exclusively in the memory write and erase sequences. hardware at the completion of the write operation. The Control bit EEPGD determines if the access will be a inability to clear the WR bit in software prevents the program or data EEPROM memory access. When accidental or premature termination of a write clear, any subsequent operations will operate on the operation. data EEPROM memory. When set, any subsequent operations will operate on the program memory. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must Control bit CFGS determines if the access will be to the be cleared in software. configuration/calibration registers, or to program memory/data EEPROM memory. When set, subse- quent operations will operate on configuration regis- ters, regardless of EEPGD (see Section23.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD. DS39609C-page 62  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 5-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 63

PIC18F6520/8520/6620/8620/6720/8720 5.2.2 TABLAT – TABLE LATCH REGISTER 5.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the SFR space. The Table Latch is used to hold Flash program memory. 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the Table memory and data RAM. Pointer determine which byte is read from program memory into TABLAT. 5.2.3 TBLPTR – TABLE POINTER REGISTER When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight The Table Pointer (TBLPTR) addresses a byte within program memory holding registers is written to. When the program memory. The TBLPTR is comprised of the timed write to program memory (long write) begins, three SFR registers: Table Pointer Upper Byte, Table the 19 MSbs of the Table Pointer, TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<21:3>), will determine which program mem- (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- ory block of 8 bytes is written to. For more detail, see ters join to form a 22-bit wide pointer. The low-order 21 Section5.5 “Writing to Flash Program Memory”. bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to When an erase of program memory is executed, the the Device ID, the User ID and the configuration bits. 16MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least The Table Pointer, TBLPTR, is used by the TBLRD and Significant bits (TBLPTR<5:0>) are ignored. TBLWT instructions. These instructions can update the TBLPTR in one of four ways, based on the table oper- Figure 5-3 describes the relevant boundaries of ation. These operations are shown in Table5-1. These TBLPTR based on Flash program memory operations. operations on the TBLPTR only affect the low-order 21 bits. TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 5-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE – TBLPTR<20:6> WRITE – TBLPTR<21:3> READ – TBLPTR<21:0> DS39609C-page 64  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 5.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure 5-4 shows the interface between the internal program memory and the TABLAT. FIGURE 5-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 5-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVFW TABLAT, W ; get data MOVWF WORD_ODD  2003-2013 Microchip Technology Inc. DS39609C-page 65

PIC18F6520/8520/6620/8620/6720/8720 5.4 Erasing Flash Program Memory 5.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through The sequence of events for erasing a block of internal ICSP control, can larger blocks of program memory be program memory location is: bulk erased. Word erase in the Flash array is not 1. Load Table Pointer with address of row being supported. erased. When initiating an erase sequence from the micro- 2. Set the EECON1 register for the erase controller itself, a block of 64 bytes of program memory operation: is erased. The Most Significant 16 bits of the • set EEPGD bit to point to program memory; TBLPTR<21:6> point to the block being erased. • clear the CFGS bit to access program TBLPTR<5:0> are ignored. memory; The EECON1 register commands the erase operation. • set WREN bit to enable writes; The EEPGD bit must be set to point to the Flash pro- • set FREE bit to enable the erase. gram memory. The WREN bit must be set to enable 3. Disable interrupts. write operations. The FREE bit is set to select an erase 4. Write 55h to EECON2. operation. 5. Write AAh to EECON2. For protection, the write initiate sequence for EECON2 6. Set the WR bit. This will begin the row erase must be used. cycle. A long write is necessary for erasing the internal Flash. 7. The CPU will stall for duration of the erase Instruction execution is halted while in a long write (about 2ms using internal timer). cycle. The long write will be terminated by the internal 8. Execute a NOP. programming timer. 9. Re-enable interrupts. EXAMPLE 5-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55H Required MOVLW AAh Sequence MOVWF EECON2 ; write AAH BSF EECON1, WR ; start erase (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts DS39609C-page 66  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 5.5 Writing to Flash Program Memory the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to The minimum programming block is 4 words or 8 bytes. start the programming operation with a long write. Word or byte programming is not supported. The long write is necessary for programming the inter- Table writes are used internally to load the holding reg- nal Flash. Instruction execution is halted while in a long isters needed to program the Flash memory. There are write cycle. The long write will be terminated by the 8 holding registers used by the table writes for internal programming timer. programming. The EEPROM on-chip timer controls the write time. Since the Table Latch (TABLAT) is only a single byte, The write/erase voltages are generated by an on-chip the TBLWT instruction has to be executed 8 times for charge pump, rated to operate over the voltage range each programming operation. All of the table write of the device for byte or word operations. operations will essentially be short writes, because only FIGURE 5-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxxx7 Holding Register Holding Register Holding Register Holding Register Program Memory 5.5.1 FLASH PROGRAM MEMORY 9. Write 55h to EECON2. WRITE SEQUENCE 10. Write AAh to EECON2. The sequence of events for programming an internal 11. Set the WR bit. This will begin the write cycle. program memory location should be: 12. The CPU will stall for duration of the write (about 2ms using internal timer). 1. Read 64 bytes into RAM. 13. Execute a NOP. 2. Update data values in RAM as necessary. 14. Re-enable interrupts. 3. Load Table Pointer with address being erased. 15. Repeat steps 6-14 seven times, to write 4. Do the row erase procedure. 64bytes. 5. Load Table Pointer with address of first byte 16. Verify the memory (table read). being written. 6. Write the first 8 bytes into the holding registers This procedure will require about 18ms to update one with auto-increment. row of 64 bytes of memory. An example of the required code is given in Example5-3. 7. Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory Note: Before setting the WR bit, the Table • clear the CFGS bit to access program Pointer address needs to be within the memory intended address range of the eight bytes • set WREN to enable byte writes in the holding register. 8. Disable interrupts.  2003-2013 Microchip Technology Inc. DS39609C-page 67

PIC18F6520/8520/6620/8620/6720/8720 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D’64 ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55H Required MOVLW AAh Sequence MOVWF EECON2 ; write AAH BSF EECON1, WR ; start erase (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement WRITE_BUFFER_BACK MOVLW 8 ; number of write buffer groups of 8 bytes MOVWF COUNTER_HI MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L PROGRAM_LOOP MOVLW 8 ; number of bytes in holding register MOVWF COUNTER WRITE_WORD_TO_HREGS MOVFF POSTINC0, WREG ; get low byte of buffer data ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_WORD_TO_HREGS DS39609C-page 68  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55H Required MOVLW AAh Sequence MOVWF EECON2 ; write AAH BSF EECON1, WR ; start program (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts DECFSZ COUNTER_HI ; loop until done BRA PROGRAM_LOOP BCF EECON1, WREN ; disable write to memory 5.5.2 WRITE VERIFY 5.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the mem- To protect against spurious writes to Flash program ory should be verified against the original value. This memory, the write initiate sequence must also be should be used in applications where excessive writes followed. See Section23.0 “Special Features of the can stress bits near the specification limit. CPU” for more detail. 5.5.3 UNEXPECTED TERMINATION OF 5.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section23.0 “Special Features of the CPU” for details on code protection of Flash program memory. location just programmed should be verified and repro- grammed if needed. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location. TABLE 5-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte --00 0000 --00 0000 (TBLPTR<20:16>) TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000 TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000 TABLAT Program Memory Table Latch 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 0000 0000 0000 EECON2 EEPROM Control Register 2 (not a physical register) — — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000 Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.  2003-2013 Microchip Technology Inc. DS39609C-page 69

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 70  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 6.0 EXTERNAL MEMORY 6.1 Program Memory Modes and the INTERFACE External Memory Interface As previously noted, PIC18F8X20 controllers are Note: The External Memory Interface is not capable of operating in any one of four program implemented on PIC18F6X20 (64-pin) memory modes, using combinations of on-chip and devices. external program memory. The functions of the multi- The External Memory Interface is a feature of the plexed port pins depend on the program memory PIC18F8X20 devices that allows the controller to mode selected, as well as the setting of the EBDIS bit. access external memory devices (such as Flash, In Microprocessor Mode, the external bus is always EPROM, SRAM, etc.) as program or data memory. active and the port pins have only the external bus The physical implementation of the interface uses 27 function. pins. These pins are reserved for external address/data In Microcontroller Mode, the bus is not active and bus functions; they are multiplexed with I/O port pins on the pins have their port functions only. Writes to the four ports. Three I/O ports are multiplexed with the MEMCOM register are not permitted. address/data bus, while the fourth port is multiplexed In Microprocessor with Boot Block or Extended with the bus control signals. The I/O port functions are Microcontroller Mode, the external program memory enabled when the EBDIS bit in the MEMCON register bus shares I/O port functions on the pins. When the is set (see Register6-1). A list of the multiplexed pins device is fetching or doing table read/table write and their functions is provided in Table6-1. operations on the external program memory space, the As implemented in the PIC18F8X20 devices, the pins will have the external bus function. If the device is interface operates in a similar manner to the external fetching and accessing internal program memory loca- memory interface introduced on PIC18C601/801 tions only, the EBDIS control bit will change the pins microcontrollers. The most notable difference is that from external memory to I/O port functions. When the interface on PIC18F8X20 devices only operates in EBDIS=0, the pins function as the external bus. 16-bit modes. The 8-bit mode is not supported. When EBDIS=1, the pins function as I/Oports. For a more complete discussion of the operating modes Note: Maximum FOSC for the PIC18FX520 is that use the external memory interface, refer to limited to 25 MHz when using the external Section4.1.1 “PIC18F8X20 Program Memory memory interface. Modes”. REGISTER 6-1: MEMCON REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EBDIS — WAIT1 WAIT0 — — WM1 WM0 bit7 bit0 bit 7 EBDIS: External Bus Disable bit 1 = External system bus disabled, all external bus drivers are mapped as I/O ports 0 = External system bus enabled and I/O ports are disabled bit 6 Unimplemented: Read as ‘0’ bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 WM<1:0>: TBLWRT Operation with 16-bit Bus bits 1x = Word Write mode: TABLAT<0> and TABLAT<1> word output, WRH active when TABLAT<1> written 01 = Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB) will activate 00 = Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 71

PIC18F6520/8520/6620/8620/6720/8720 If the device fetches or accesses external memory When the device is executing out of internal memory while EBDIS = 1, the pins will switch to external bus. If (EBDIS = 0) in Microprocessor with Boot Block mode, the EBDIS bit is set by a program executing from or Extended Microcontroller mode, the control signals external memory, the action of setting the bit will be will NOT be active. They will go to a state where the delayed until the program branches into the internal AD<15:0> and A<19:16> are tri-state; the CE, OE, memory. At that time, the pins will change from WRH, WRL, UB and LB signals are ‘1’ and ALE and external bus to I/O ports. BA0 are ‘0’. TABLE 6-1: PIC18F8X20 EXTERNAL BUS – I/O PORT FUNCTIONS Name Port Bit Function RD0/AD0 PORTD bit 0 Input/Output or System Bus Address bit 0 or Data bit 0. RD1/AD1 PORTD bit 1 Input/Output or System Bus Address bit 1 or Data bit 1. RD2/AD2 PORTD bit 2 Input/Output or System Bus Address bit 2 or Data bit 2. RD3/AD3 PORTD bit 3 Input/Output or System Bus Address bit 3 or Data bit 3. RD4/AD4 PORTD bit 4 Input/Output or System Bus Address bit 4 or Data bit 4. RD5/AD5 PORTD bit 5 Input/Output or System Bus Address bit 5 or Data bit 5. RD6/AD6 PORTD bit 6 Input/Output or System Bus Address bit 6 or Data bit 6. RD7/AD7 PORTD bit 7 Input/Output or System Bus Address bit 7 or Data bit 7. RE0/AD8 PORTE bit 0 Input/Output or System Bus Address bit 8 or Data bit 8. RE1/AD9 PORTE bit 1 Input/Output or System Bus Address bit 9 or Data bit 9. RE2/AD10 PORTE bit 2 Input/Output or System Bus Address bit 10 or Data bit 10. RE3/AD11 PORTE bit 3 Input/Output or System Bus Address bit 11 or Data bit 11. RE4/AD12 PORTE bit 4 Input/Output or System Bus Address bit 12 or Data bit 12. RE5/AD13 PORTE bit 5 Input/Output or System Bus Address bit 13 or Data bit 13. RE6/AD14 PORTE bit 6 Input/Output or System Bus Address bit 14 or Data bit 14. RE7/AD15 PORTE bit 7 Input/Output or System Bus Address bit 15 or Data bit 15. RH0/A16 PORTH bit 0 Input/Output or System Bus Address bit 16. RH1/A17 PORTH bit 1 Input/Output or System Bus Address bit 17. RH2/A18 PORTH bit 2 Input/Output or System Bus Address bit 18. RH3/A19 PORTH bit 3 Input/Output or System Bus Address bit 19. RJ0/ALE PORTJ bit 0 Input/Output or System Bus Address Latch Enable (ALE) Control pin. RJ1/OE PORTJ bit 1 Input/Output or System Bus Output Enable (OE) Control pin. RJ2/WRL PORTJ bit 2 Input/Output or System Bus Write Low (WRL) Control pin. RJ3/WRH PORTJ bit 3 Input/Output or System Bus Write High (WRH) Control pin. RJ4/BA0 PORTJ bit 4 Input/Output or System Bus Byte Address bit 0. RJ5/CE PORTJ bit 5 Input/Output or System Bus Chip Enable (CE) Control pin. RJ6/LB PORTJ bit 6 Input/Output or System Bus Lower Byte Enable (LB) Control pin. RJ7/UB PORTJ bit 7 Input/Output or System Bus Upper Byte Enable (UB) Control pin. DS39609C-page 72  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 6.2 16-bit Mode In Byte Select mode, JEDEC standard Flash memories will require BA0 for the byte address line and one I/O The External Memory Interface implemented in line to select between Byte and Word mode. The other PIC18F8X20 devices operates only in 16-bit mode. 16-bit modes do not need BA0. JEDEC standard static The mode selection is not software configurable, but is RAM memories will use the UB or LB signals for byte programmed via the configuration bits. selection. The WM<1:0> bits in the MEMCON register determine 6.2.1 16-BIT BYTE WRITE MODE three types of connections in 16-bit mode. They are referred to as: Figure6-1 shows an example of 16-bit Byte Write • 16-bit Byte Write mode for PIC18F8X20 devices. This mode is used for two separate 8-bit memories connected for 16-bit oper- • 16-bit Word Write ation. This generally includes basic EPROM and Flash • 16-bit Byte Select devices. It allows table writes to byte-wide external These three different configurations allow the designer memories. maximum flexibility in using 8-bit and 16-bit memory During a TBLWT instruction cycle, the TABLAT data is devices. presented on the upper and lower bytes of the For all 16-bit modes, the Address Latch Enable (ALE) AD15:AD0 bus. The appropriate WRH or WRL control pin indicates that the address bits A<15:0> are line is strobed on the LSb of the TBLPTR. available on the External Memory Interface bus. Following the address latch, the Output Enable signal (OE) will enable both bytes of program memory at once to form a 16-bit instruction word. The Chip Enable signal (CE) is active at any time that the microcontroller accesses external memory, whether reading or writing; it is inactive (asserted high) whenever the device is in Sleep mode. FIGURE 6-1: 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18F8X20 (MSB) (LSB) A<19:0> AD<7:0> 373 A<x:0> A<x:0> D<15:8> D<7:0> D<7:0> D<7:0> CE CE AD<15:8> 373 OE WR(1) OE WR(1) ALE A<19:16> CE OE WRH WRL Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section5.1 “Table Reads and Table Writes”.  2003-2013 Microchip Technology Inc. DS39609C-page 73

PIC18F6520/8520/6620/8620/6720/8720 6.2.2 16-BIT WORD WRITE MODE During a TBLWT cycle to an odd address (TBLPTR<0> = 1), the TABLAT data is presented on Figure6-2 shows an example of 16-bit Word Write the upper byte of the AD15:AD0 bus. The contents of mode for PIC18F8X20 devices. This mode is used for the holding latch are presented on the lower byte of the word-wide memories, which includes some of the AD15:AD0 bus. EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit The WRH signal is strobed for each write cycle; the memory and table writes to any type of word-wide WRL pin is unused. The signal on the BA0 pin indicates external memories. This method makes a distinction the LSb of TBLPTR, but it is left unconnected. Instead, between TBLWT cycles to even or odd addresses. the UB and LB signals are active to select both bytes. The obvious limitation to this method is that the table During a TBLWT cycle to an even address write must be done in pairs on a specific word boundary (TBLPTR<0>=0), the TABLAT data is transferred to a to correctly write a word location. holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. No write signals are activated. FIGURE 6-2: 16-BIT WORD WRITE MODE EXAMPLE PIC18F8X20 AD<7:0> 373 A<20:1> A<x:0> JEDEC Word EPROM Memory D<15:0> D<15:0> CE OE WR(1) AD<15:8> 373 ALE A<19:16> CE OE WRH Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section5.1 “Table Reads and Table Writes”. DS39609C-page 74  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 6.2.3 16-BIT BYTE SELECT MODE Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC Figure6-3 shows an example of 16-bit Byte Select standard Flash memories require that a controller I/O mode for PIC18F8X20 devices. This mode allows table port pin be connected to the memory’s BYTE/WORD write operations to word-wide external memories with pin to provide the select signal. They also use the BA0 byte selection capability. This generally includes both signal from the controller as a byte address. JEDEC word-wide Flash and SRAM devices. standard static RAM memories, on the other hand, use During a TBLWT cycle, the TABLAT data is presented the UB or LB signals to select the byte. on the upper and lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle; the WRL pin is not used. The BA0 or UB/LB signals are used to select the byte to be written, based on the Least Significant bit of the TBLPTR register. FIGURE 6-3: 16-BIT BYTE SELECT MODE EXAMPLE PIC18F8X20 A<20:1> AD<7:0> 373 A<x:1> JEDEC Word Flash Memory D<15:0> D<15:0> AD<15:8> 138 CE 373 A0 ALE BYTE/WORD OE WR(1) A<19:16> OE WRH WRL A<20:1> A<x:1> JEDEC Word BA0 SRAM Memory I/O D<15:0> CE D<15:0> LB LB UB UB OE WR(1) Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section5.1 “Table Reads and Table Writes”.  2003-2013 Microchip Technology Inc. DS39609C-page 75

PIC18F6520/8520/6620/8620/6720/8720 6.2.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure6-4 through Figure6-6. FIGURE 6-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE) Apparent Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q4 Q4 Q4 Actual Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 00h 0Ch AD<15:0> 3AABh 0E55h CF33h 9256h BA0 ALE OE WRH ‘1’ ‘1’ WRL ‘1’ ‘1’ CE ‘0’ ‘0’ 1 TCY Wait Memory Opcode Fetch Table Read Cycle MOVLW 55h of 92h from 007556h from 199E67h Instruction Execution TBLRD Cycle 1 TBLRD Cycle 2 FIGURE 6-5: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:0> CF33h 9256h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction INST(PC-2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW Execution DS39609C-page 76  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 6-6: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:0> 3AAAh 0003h 3AABh 0E55h CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction INST(PC-2) SLEEP Execution  2003-2013 Microchip Technology Inc. DS39609C-page 77

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 78  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 7.0 DATA EEPROM MEMORY 7.1 EEADR and EEADRH The data EEPROM is readable and writable during The address register pair can address up to a maxi- normal operation over the entire VDD range. The data mum of 1024 bytes of data EEPROM. The two Most memory is not directly mapped in the register file Significant bits of the address are stored in EEADRH, space. Instead, it is indirectly addressed through the while the remaining eight Least Significant bits are Special Function Registers (SFR). stored in EEADR. The six Most Significant bits of EEADRH are unused and are read as ‘0’. There are five SFRs used to read and write the program and data EEPROM memory. These registers 7.2 EECON1 and EECON2 Registers are: • EECON1 EECON1 is the control register for EEPROM memory • EECON2 accesses. • EEDATA EECON2 is not a physical register. Reading EECON2 • EEADRH will read all ‘0’s. The EECON2 register is used exclusively in the EEPROM write sequence. • EEADR Control bits, RD and WR, initiate read and write opera- The EEPROM data memory allows byte read and write. tions, respectively. These bits cannot be cleared, only When interfacing to the data memory block, EEDATA set, in software. They are cleared in hardware at the holds the 8-bit data for read/write. EEADR and completion of the read or write operation. The inability EEADRH hold the address of the EEPROM location to clear the WR bit in software prevents the accidental being accessed. These devices have 1024 bytes of or premature termination of a write operation. data EEPROM with an address range from 00h to 3FFh. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is The EEPROM data memory is rated for high erase/ set when a write operation is interrupted by a MCLR write cycles. A byte write automatically erases the loca- Reset or a WDT Time-out Reset during normal opera- tion and writes the new data (erase-before-write). The tion. In these situations, the user can check the write time is controlled by an on-chip timer. The write WRERR bit and rewrite the location. It is necessary to time will vary with voltage and temperature, as well as reload the data and address registers (EEDATA and from chip to chip. Please refer to parameter D122 (see EEADR) due to the Reset condition forcing the Section26.0 “Electrical Characteristics”) for exact contents of the registers to zero. limits. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in software.  2003-2013 Microchip Technology Inc. DS39609C-page 79

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 7-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed programming in normal operation) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 80  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 7.3 Reading the Data EEPROM control bit (EECON1<6>) and then set the RD control Memory bit (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register To read a data memory location, the user must write the can be read by the next instruction. EEDATA will hold address to the EEADRH:EEADR register pair, clear the this value until another read operation, or until it is EEPGD control bit (EECON1<7>), clear the CFGS written to by the user (during a write operation). EXAMPLE 7-1: DATA EEPROM READ MOVLW DATA_EE_ADDRH ; MOVWF EEADRH ; Upper bits of Data Memory Address to read MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Lower bits of Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA 7.4 Writing to the Data EEPROM should be kept clear at all times, except when updating Memory the EEPROM. The WREN bit is not cleared byhardware To write an EEPROM data location, the address must After a write sequence has been initiated, EECON1, first be written to the EEADRH:EEADR register pair EEADRH, EEADR and EEDATA cannot be modified. and the data written to the EEDATA register. Then the The WR bit will be inhibited from being set unless the sequence in Example7-2 must be followed to initiate WREN bit is set. Both WR and WREN cannot be set the write cycle. with the same instruction. The write will not initiate if the above sequence is not At the completion of the write cycle, the WR bit is exactly followed (write 55h to EECON2, write AAh to cleared in hardware and the EEPROM Write Complete EECON2, then set WR bit) for each byte. It is strongly Interrupt Flag bit (EEIF) is set. The user may either recommended that interrupts be disabled during this enable this interrupt, or poll this bit. EEIF must be codesegment. cleared by software. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit EXAMPLE 7-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDRH ; MOVWF EEADRH ; Upper bits of Data Memory Address to write MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Lower bits of Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1,EEPGD ; Point to DATA memory BCF EECON1,CFGS ; Access EEPROM BSF EECON1,WREN ; Enable writes BCF INTCON,GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW AAh ; MOVWF EECON2 ; Write AAh BSF EECON1,WR ; Set WR bit to begin write BSF INTCON,GIE ; Enable Interrupts ; User code execution BCF EECON1,WREN ; Disable writes on write complete (EEIF set)  2003-2013 Microchip Technology Inc. DS39609C-page 81

PIC18F6520/8520/6620/8620/6720/8720 7.5 Write Verify 7.8 Using the Data EEPROM Depending on the application, good programming The data EEPROM is a high endurance, byte address- practice may dictate that the value written to the mem- able array that has been optimized for the storage of ory should be verified against the original value. This frequently changing information (e.g., program vari- should be used in applications where excessive writes ables or other data that are updated often). Frequently can stress bits near the specification limit. changing values will typically be updated more often than specification D124. If this is not the case, an array 7.6 Protection Against Spurious Write refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, There are conditions when the user may not want to calibration, etc.) should be stored in Flash program write to the data EEPROM memory. To protect against memory. spurious EEPROM writes, various mechanisms have A simple data EEPROM refresh routine is shown in been built-in. On power-up, the WREN bit is cleared. Example7-3. Also, the Power-up Timer (72 ms duration) prevents EEPROMwrite. Note: If data EEPROM is only used to store constants and/or data that changes rarely, The write initiate sequence and the WREN bit together an array refresh is likely not required. See help prevent an accidental write during brown-out, specification D124. power glitch, or software malfunction. 7.7 Operation During Code-Protect Data EEPROM memory has its own code-protect mechanism. External read and write operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect configuration bit. Refer to Section23.0 “Special Features of the CPU” for additional information. EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE CLRF EEADR ; Start at address 0 CLRF EEADRH ; BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes Loop ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW AAh ; MOVWF EECON2 ; Write AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA Loop ; Not zero, do it again INCFSZ EEADRH, F ; Increment the high address BRA Loop ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts DS39609C-page 82  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 EEADRH — — — — — — EE Addr Register High ---- --00 ---- --00 EEADR EEPROM Address Register 0000 0000 0000 0000 EEDATA EEPROM Data Register 0000 0000 0000 0000 EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---- EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000 Legend: x = unknown, u = unchanged, r = reserved, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.  2003-2013 Microchip Technology Inc. DS39609C-page 83

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 84  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 8.0 8 X 8 HARDWARE MULTIPLIER 8.2 Operation Example8-1 shows the sequence to do an 8 x 8 8.1 Introduction unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in An 8 x 8 hardware multiplier is included in the ALU of the WREG register. the PIC18FXX20 devices. By making the multiply a hardware operation, it completes in a single instruction Example8-2 shows the sequence to do an 8 x 8 signed cycle. This is an unsigned multiply that gives a 16-bit multiply. To account for the sign bits of the arguments, result. The result is stored in the 16-bit product register each argument’s Most Significant bit (MSb) is tested pair (PRODH:PRODL). The multiplier does not affect and the appropriate subtractions are done. any flags in the ALUSTA register. EXAMPLE 8-1: 8 x 8 UNSIGNED Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: MULTIPLY ROUTINE MOVF ARG1, W ; • Higher computational throughput MULWF ARG2 ; ARG1 * ARG2 -> • Reduces code size requirements for multiply ; PRODH:PRODL algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY Processors. ROUTINE Table8-1 shows a performance comparison between MOVF ARG1, W ; enhanced devices using the single-cycle hardware MULWF ARG2 ; ARG1 * ARG2 -> multiply and performing the same function without the ; PRODH:PRODL BTFSC ARG2, SB ; Test Sign Bit hardware multiply. SUBWF PRODH, F ; PRODH = PRODH ; - ARG1 MOVF ARG2, W ; BTFSC ARG1, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 TABLE 8-1: PERFORMANCE COMPARISON Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 s 27.6 s 69 s 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 s Without hardware multiply 33 91 9.1 s 36.4 s 91 s 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 s 6 s Without hardware multiply 21 242 24.2 s 96.8 s 242 s 16 x 16 unsigned Hardware multiply 28 28 2.8 s 11.2 s 28 s Without hardware multiply 52 254 25.4 s 102.6 s 254 s 16 x 16 signed Hardware multiply 35 40 4.0 s 16.0 s 40 s  2003-2013 Microchip Technology Inc. DS39609C-page 85

PIC18F6520/8520/6620/8620/6720/8720 Example8-3 shows the sequence to do a 16 x 16 EQUATION 8-2: 16 x 16 SIGNED unsigned multiply. Equation8-1 shows the algorithm MULTIPLICATION that is used. The 32-bit result is stored in four registers, ALGORITHM RES3:RES0. RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L EQUATION 8-1: 16 x 16 UNSIGNED = (ARG1H  ARG2H  216) + MULTIPLICATION (ARG1H  ARG2L  28) + ALGORITHM (ARG1L  ARG2H  28) + (ARG1L  ARG2L) + RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L (-1  ARG2H<7>  ARG1H:ARG1L  216) + = (ARG1H  ARG2H  216) + (-1  ARG1H<7>  ARG2H:ARG2L  216) (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + (ARG1L  ARG2L) EXAMPLE 8-4: 16 x 16 SIGNED MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 8-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES1 ; MULWF ARG2L ; ARG1L * ARG2L -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES1 ; MOVF ARG1H, W MOVFF PRODL, RES0 ; MULWF ARG2H ; ARG1H * ARG2H -> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1L, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1L * ARG2H -> ; ; PRODH:PRODL MOVF ARG1L, W MOVF PRODL, W ; MULWF ARG2H ; ARG1L * ARG2H -> ADDWF RES1, F ; Add cross ; PRODH:PRODL MOVF PRODH, W ; products MOVF PRODL, W ; ADDWFC RES2, F ; ADDWF RES1, F ; Add cross CLRF WREG ; MOVF PRODH, W ; products ADDWFC RES3, F ; ADDWFC RES2, F ; ; CLRF WREG ; MOVF ARG1H, W ; ADDWFC RES3, F ; MULWF ARG2L ; ARG1H * ARG2L -> ; ; PRODH:PRODL MOVF ARG1H, W ; MOVF PRODL, W ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWF RES1, F ; Add cross ; PRODH:PRODL MOVF PRODH, W ; products MOVF PRODL, W ; ADDWFC RES2, F ; ADDWF RES1, F ; Add cross CLRF WREG ; MOVF PRODH, W ; products ADDWFC RES3, F ; ADDWFC RES2, F ; ; CLRF WREG ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? ADDWFC RES3, F ; BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L, W ; SUBWF RES2 ; Example8-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation8-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers, ; RES3:RES0. To account for the sign bits of the argu- SIGN_ARG1 BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? ments, each argument pairs’ Most Significant bit (MSb) BRA CONT_CODE ; no, done is tested and the appropriate subtractions are done. MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS39609C-page 86  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 9.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are The PIC18FXX20 devices have multiple interrupt compatible with PIC® mid-range devices. In Compati- sources and an interrupt priority feature that allows bility mode, the interrupt priority bits for each source each interrupt source to be assigned a high or a low have no effect. INTCON<6> is the PEIE bit, which priority level. The high priority interrupt vector is at enables/disables all peripheral interrupt sources. 000008h, while the low priority interrupt vector is at INTCON<7> is the GIE bit, which enables/disables all 000018h. High priority interrupt events will override any interrupt sources. All interrupts branch to address low priority interrupts that may be in progress. 000008h in Compatibility mode. There are thirteen registers which are used to control When an interrupt is responded to, the Global Interrupt interrupt operation. They are: Enable bit is cleared to disable further interrupts. If the • RCON IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. • INTCON High priority interrupt sources can interrupt a low • INTCON2 priority interrupt. • INTCON3 The return address is pushed onto the stack and the • PIR1, PIR2, PIR3 PC is loaded with the interrupt vector address • PIE1, PIE2, PIE3 (000008h or 000018h). Once in the Interrupt Service • IPR1, IPR2, IPR3 Routine, the source(s) of the interrupt can be deter- It is recommended that the Microchip header files, mined by polling the interrupt flag bits. The interrupt supplied with MPLAB® IDE, be used for the symbolic bit flag bits must be cleared in software before re-enabling names in these registers. This allows the assembler/ interrupts to avoid recursive interrupts. compiler to automatically take care of the placement of The “return from interrupt” instruction, RETFIE, exits these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL Each interrupt source has three bits to control its if priority levels are used), which re-enables interrupts. operation. The functions of these bits are: For external interrupt events, such as the INT pins or • Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. • Enable bit that allows program execution to Individual interrupt flag bits are set, regardless of the branch to the interrupt vector address when the status of their corresponding enable bit or the GIE bit. flag bit is set • Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set. Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared. When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. Individual interrupts can be disabled through their corresponding enable bits.  2003-2013 Microchip Technology Inc. DS39609C-page 87

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 9-1: INTERRUPT LOGIC Wake-up if in Sleep mode TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Interrupt to CPU INT1IF Vector to Location INT1IE Peripheral Interrupt Flag bit INT1IP 0008h Peripheral Interrupt Enable bit INT2IF Peripheral Interrupt Priority bit INT2IE INT2IP GIEH/GIE TMR1IF TMR1IE TMR1IP IPEN XXXXIF IPEN XXXXIE GIEL/PEIE XXXXIP IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Interrupt to CPU TMR0IF Vector to Location TMR0IE 0018h TMR1IF TMR0IP TMR1IE TMR1IP RBIF RBIE XXXXIF RBIP GIEL/PEIE XXXXIE XXXXIP GIE/GEIH INT1IF Additional Peripheral Interrupts INT1IE INT1IP INT2IF INT2IE INT2IP DS39609C-page 88  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 9.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers, which contain various enable, priority and enable bit. User software should ensure flag bits. the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 9-1: INTCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN (RCON<7>) = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN (RCON<7>) = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN (RCON<7>) = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN (RCON<7>) = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 89

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39609C-page 90  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-3: INTCON3 REGISTER R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2003-2013 Microchip Technology Inc. DS39609C-page 91

PIC18F6520/8520/6620/8620/6720/8720 9.2 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the global peripheral interrupts. Due to the number of peripheral enable bit, GIE (INTCON<7>). interrupt sources, there are three Peripheral Interrupt Flag Registers (PIR1, PIR2 and PIR3). 2: User software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: USART1 Receive Interrupt Flag bit 1 = The USART1 receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART1 receive buffer is empty bit 4 TX1IF: USART Transmit Interrupt Flag bit 1 = The USART1 transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART1 transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note1: Enabled only in Microcontroller mode for PIC18F8X20 devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 92  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIF: Comparator Interrupt Flag bit 1 = The comparator input has changed (must be cleared in software) 0 = The comparator input has not changed bit 5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete, or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred while the SSP module (configured in I2C Master mode) was transmitting (must be cleared in software) 0 = No bus collision occurred bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low-Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 or TMR3 register capture occurred (must be cleared in software) 0 = No TMR1 or TMR3 register capture occurred Compare mode: 1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 93

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 bit 7- 6 Unimplemented: Read as ‘0’ bit 5 RC2IF: USART2 Receive Interrupt Flag bit 1 = The USART2 receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART2 receive buffer is empty bit 4 TX2IF: USART2 Transmit Interrupt Flag bit 1 = The USART2 transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART2 transmit buffer is full bit 3 TMR4IF: TMR3 Overflow Interrupt Flag bit 1 = TMR4 register overflowed (must be cleared in software) 0 = TMR4 register did not overflow bit 2-0 CCPxIF: CCPx Interrupt Flag bit (CCP Modules 3, 4 and 5) Capture mode: 1 = A TMR1 or TMR3 register capture occurred (must be cleared in software) 0 = No TMR1 or TMR3 register capture occurred Compare mode: 1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 94  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: USART1 Receive Interrupt Enable bit 1 = Enables the USART1 receive interrupt 0 = Disables the USART1 receive interrupt bit 4 TX1IE: USART1 Transmit Interrupt Enable bit 1 = Enables the USART1 transmit interrupt 0 = Disables the USART1 transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note1: Enabled only in Microcontroller mode for PIC18F8X20 devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 95

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enables the write operation interrupt 0 = Disables the write operation interrupt bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enables the bus collision interrupt 0 = Disables the bus collision interrupt bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enables the Low-Voltage Detect interrupt 0 = Disables the Low-Voltage Detect interrupt bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 96  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IE: USART2 Receive Interrupt Enable bit 1 = Enables the USART2 receive interrupt 0 = Disables the USART2 receive interrupt bit 4 TX2IE: USART2 Transmit Interrupt Enable bit 1 = Enables the USART2 transmit interrupt 0 = Disables the USART2 transmit interrupt bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 match interrupt 0 = Disables the TMR4 to PR4 match interrupt bit 2-0 CCPxIE: CCPx Interrupt Enable bit (CCP Modules 3, 4 and 5) 1 = Enables the CCPx interrupt 0 = Disables the CCPx interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 97

PIC18F6520/8520/6620/8620/6720/8720 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority Registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: USART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: USART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note1: Enabled only in Microcontroller mode for PIC18F8X20 devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 98  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 99

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: USART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: USART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 2-0 CCPxIP: CCPx Interrupt Priority bit (CCP Modules 3, 4 and 5) 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 100  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 9.5 RCON Register The RCON register contains the IPEN bit, which is used to enable prioritized interrupts. The functions of the other bits in this register are discussed in more detail in Section4.14 “RCON Register”. REGISTER 9-13: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16 Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register4-4. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register4-4. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register4-4. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register4-4. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register4-4. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 101

PIC18F6520/8520/6620/8620/6720/8720 9.6 INT0 Interrupt 9.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, In 8-bit mode (which is the default), an overflow in the RB2/INT2 and RB3/INT3 pins are edge-triggered: TMR0 register (FFh 00h) will set flag bit TMR0IF. In either rising, if the corresponding INTEDGx bit is set in 16-bit mode, an overflow in the TMR0H:TMR0L regis- the INTCON2 register, or falling, if the INTEDGx bit is ters (FFFFh 0000h) will set flag bit TMR0IF. The clear. When a valid edge appears on the RBx/INTx pin, interrupt can be enabled/disabled by setting/clearing the corresponding flag bit, INTxF, is set. This interrupt enable bit, TMR0IE (INTCON<5>). Interrupt priority for can be disabled by clearing the corresponding enable Timer0 is determined by the value contained in the bit, INTxE. Flag bit, INTxF, must be cleared in software interrupt priority bit, TMR0IP (INTCON2<2>). See in the Interrupt Service Routine before re-enabling the Section11.0 “Timer0 Module” for further details on interrupt. All external interrupts (INT0, INT1, INT2 and the Timer0 module. INT3) can wake-up the processor from Sleep if bit INTxIE was set prior to going into Sleep. If the Global 9.8 PORTB Interrupt-on-Change Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled The interrupt priority for INT, INT2 and INT3 is deter- by setting/clearing enable bit, RBIE (INTCON<3>). mined by the value contained in the interrupt priority Interrupt priority for PORTB interrupt-on-change is bits: INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) determined by the value contained in the interrupt and INT3IP (INTCON2<1>). There is no priority bit priority bit, RBIP (INTCON2<0>). associated with INT0; it is always a high priority interrupt source. 9.9 Context Saving During Interrupts During an interrupt, the return PC value is saved on the stack. Additionally, the WREG, Status and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section4.3 “Fast Register Stack”), the user may need to save the WREG, Status and BSR registers in software. Depending on the user’s application, other registers may also need to be saved. Example9-1 saves and restores the WREG, Status and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS39609C-page 102  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 10.0 I/O PORTS 10.1 PORTA, TRISA and LATA Registers Depending on the device selected, there are either seven or nine I/O ports available on PIC18FXX20 PORTA is a 7-bit wide, bidirectional port. The corre- devices. Some of their pins are multiplexed with one or sponding data direction register is TRISA. Setting a more alternate functions from the other peripheral fea- TRISA bit (= 1) will make the corresponding PORTA pin tures on the device. In general, when a peripheral is an input (i.e., put the corresponding output driver in a enabled, that pin may not be used as a general high-impedance mode). Clearing a TRISA bit (= 0) will purpose I/O pin. make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Each port has three registers for its operation. These registers are: Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. • TRIS register (data direction register) • PORT register (reads the levels on the pins of the The Data Latch register (LATA) is also memory device) mapped. Read-modify-write operations on the LATA • LAT register (output latch) register, read and write the latched output value for PORTA. The Data Latch (LAT register) is useful for read-modify- write operations on the value that the I/O pins are The RA4 pin is multiplexed with the Timer0 module driving. clock input to become the RA4/T0CKI pin. The RA4/ T0CKI pin is a Schmitt Trigger input and an open-drain A simplified version of a generic I/O port and its output. All other RA port pins have TTL input levels and operation is shown in Figure10-1. full CMOS output drivers. The RA6 pin is only enabled as a general I/O pin in FIGURE 10-1: SIMPLIFIED BLOCK ECIO and RCIO Oscillator modes. DIAGRAM OF PORT/LAT/ TRIS OPERATION The other PORTA pins are multiplexed with analog inputs and the analog VREF+ and VREF- inputs. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control RD LAT Register 1). TRIS Note: On a Power-on Reset, RA5 and RA3:RA0 D Q are configured as analog inputs and read as ‘0’. RA6 and RA4 are configured as WR LAT + WR Port CK digital inputs. The TRISA register controls the direction of the RA Data Latch pins, even when they are being used as analog inputs. Data Bus The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. RD Port I/O pin EXAMPLE 10-1: INITIALIZING PORTA CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW 0x0F ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs  2003-2013 Microchip Technology Inc. DS39609C-page 103

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-2: BLOCK DIAGRAM OF FIGURE 10-3: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS RA4/T0CKI PIN RD LATA RD LATA Data Bus Data D Q Bus D Q WorR LATA VDD WorR LATA PORTA CK Q P PORTA CK Q I/O pin(1) N Data Latch Data Latch D Q N I/O pin(1) D Q VSS WR TRISA WR TRISA CK Q Schmitt CK Q VSS Trigger Analog TRIS Latch Input TRIS Latch Input Mode Buffer RD TRISA RD TRISA TTL Input Buffer Q D Q D ENEN EN RD PORTA RD PORTA TMR0 Clock Input To A/D Converter and LVD Modules Note1: I/O pins have protection diodes to VDD and VSS. Note1: I/O pins have protection diodes to VDD and VSS. FIGURE 10-4: BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O) ECRA6 or RCRA6 Enable DataBus RD LATA D Q VDD WR LATA orPORTA CK Q P Data Latch N I/O pin(1) D Q WR TRISA CK Q VSS TRIS Latch TTL RD TRISA Input Buffer ECRA6 or RCRA6 Enable Q D EN RD PORTA Note1: I/O pins have protection diodes to VDD and VSS. DS39609C-page 104  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit 0 TTL Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF- bit 2 TTL Input/output or analog input or VREF-. RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+. RA4/T0CKI bit 4 ST Input/output or external clock input for Timer0. Output is open-drain type. RA5/AN4/LVDIN bit 5 TTL Input/output or slave select input for synchronous serial port or analog input, or Low-Voltage Detect input. OSC2/CLKO/RA6 bit 6 TTL OSC2 or clock output, or I/O pin. Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 -u0u 0000 LATA — LATA Data Output Register -xxx xxxx -uuu uuuu TRISA — PORTA Data Direction Register -111 1111 -111 1111 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.  2003-2013 Microchip Technology Inc. DS39609C-page 105

PIC18F6520/8520/6620/8620/6720/8720 10.2 PORTB, TRISB and LATB A mismatch condition will continue to set flag bit, RBIF. Registers Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. PORTB is an 8-bit wide, bidirectional port. The corre- The interrupt-on-change feature is recommended for sponding data direction register is TRISB. Setting a wake-up on key depression operation and operations TRISB bit (= 1) will make the corresponding PORTB where PORTB is only used for the interrupt-on-change pin an input (i.e., put the corresponding output driver in feature. Polling of PORTB is not recommended while a high-impedance mode). Clearing a TRISB bit (= 0) using the interrupt-on-change feature. will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). RB3 can be configured by the configuration bit CCP2MX, as the alternate peripheral pin for the CCP2 The Data Latch register (LATB) is also memory module. This is only available when the device is mapped. Read-modify-write operations on the LATB configured in Microprocessor, Microprocessor with register, read and write the latched output value for Boot Block, or Extended Microcontroller operating PORTB. modes. EXAMPLE 10-2: INITIALIZING PORTB The RB5 pin is used as the LVP programming pin. When the LVP configuration bit is programmed, this pin CLRF PORTB ; Initialize PORTB by loses the I/O function and become a programming test ; clearing output function. ; data latches CLRF LATB ; Alternate method Note: When LVP is enabled, the weak pull-up on ; to clear output RB5 is disabled. ; data latches MOVLW 0xCF ; Value used to FIGURE 10-5: BLOCK DIAGRAM OF ; initialize data ; direction RB7:RB4 PINS MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs VDD ; RB<7:6> as inputs RBPU(2) Weak P Pull-up Data Latch Each of the PORTB pins has a weak internal pull-up. A Data Bus D Q single control bit can turn on all the pull-ups. This is WR LATB I/O pin(1) performed by clearing bit RBPU (INTCON2<7>). The orPORTB CK weak pull-up is automatically turned off when the port TRIS Latch pin is configured as an output. The pull-ups are D Q disabled on a Power-on Reset. WR TRISB TTL CK Note: On a Power-on Reset, these pins are Input Buffer ST configured as digital inputs. Buffer RD TRISB Four of the PORTB pins (RB3:RB0) are the external interrupt pins, INT3 through INT0. In order to use these pins as external interrupts, the corresponding TRISB RD LATB bit must be set to ‘1’. Latch The other four PORTB pins (RB7:RB4) have an inter- Q D rupt-on-change feature. Only pins configured as inputs RD PORTB EN Q1 can cause this interrupt to occur (i.e., any RB7:RB4 pin Set RBIF configured as an output is excluded from the interrupt- on-change comparison). The input pins (of RB7:RB4) Q D are compared with the old value latched on the last RD PORTB read of PORTB. The “mismatch” outputs of RB7:RB4 From other EN are OR’ed together to generate the RB Port Change RB7:RB4 pins Q3 Interrupt with Flag bit, RBIF (INTCON<0>). RB7:RB5 in Serial Programming Mode This interrupt can wake the device from Sleep. The Note1: I/O pins have diode protection to VDD and VSS. user, in the Interrupt Service Routine, can clear the 2: To enable weak pull-ups, set the appropriate TRIS bit(s) interrupt in the following manner: and clear the RBPU bit (INTCON2<7>). a) Any read or write of PORTB (except with the MOVFF instruction). This will end the mismatch condition. b) Clear flag bit RBIF. DS39609C-page 106  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-6: BLOCK DIAGRAM OF RB2:RB0 PINS VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D Q I/O pin(1) WR Port CK TRIS Latch D Q TTL Input WR TRIS CK Buffer RD TRIS Q D RD Port EN INTx Schmitt Trigger RD Port Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). FIGURE 10-7: BLOCK DIAGRAM OF RB3 PIN VDD RBPU(2) Weak CCP2MX P Pull-up CCP Output(3) 1 VDD P Enable(3) 0 CCP Output Data Latch Data Bus I/O pin(1) D Q WR LATB or WR PORTB N CK TRIS Latch VSS D TTL WR TRISB Input CK Q Buffer RD TRISB RD LATB Q D RD PORTB EN RD PORTB CCP2 or INT3 Schmitt Trigger Buffer CCP2MX = 0 Note 1: I/O pin has diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.  2003-2013 Microchip Technology Inc. DS39609C-page 107

PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT0 bit 0 TTL/ST(1) Input/output pin or external interrupt input 0. Internal software programmable weak pull-up. RB1/INT1 bit 1 TTL/ST(1) Input/output pin or external interrupt input 1. Internal software programmable weak pull-up. RB2/INT2 bit 2 TTL/ST(1) Input/output pin or external interrupt input 2. Internal software programmable weak pull-up. RB3/INT3/CCP2(3) bit 3 TTL/ST(4) Input/output pin or external interrupt input 3. Capture2 input/Compare2 output/PWM output (when CCP2MX configuration bit is enabled, all PIC18F8X20 operating modes except Microcontroller mode). Internal software programmable weak pull-up. RB4/KBI0 bit 4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5/KBI1/PGM bit 5 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Low-voltage ICSP enable pin. RB6/KBI2/PGC bit 6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. RB7/KBI3/PGD bit 7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: RC1 is the alternate assignment for CCP2 when CCP2MX is not set (all operating modes except Microcontroller mode). 4: This buffer is a Schmitt Trigger input when configured as the CCP2 input. TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu LATB LATB Data Output Register xxxx xxxx uuuu uuuu TRISB PORTB Data Direction Register 1111 1111 1111 1111 INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 GIEH GIEL INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 1111 1111 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 1100 0000 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS39609C-page 108  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 10.3 PORTC, TRISC and LATC The pin override value is not loaded into the TRIS Registers register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides. PORTC is an 8-bit wide, bidirectional port. The corre- RC1 is normally configured by configuration bit, sponding data direction register is TRISC. Setting a CCP2MX, as the default peripheral pin of the CCP2 TRISC bit (= 1) will make the corresponding PORTC module (default/erased state, CCP2MX = 1). pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) EXAMPLE 10-3: INITIALIZING PORTC will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). CLRF PORTC ; Initialize PORTC by ; clearing output The Data Latch register (LATC) is also memory ; data latches mapped. Read-modify-write operations on the LATC CLRF LATC ; Alternate method register, read and write the latched output value for ; to clear output PORTC. ; data latches MOVLW 0xCF ; Value used to PORTC is multiplexed with several peripheral functions ; initialize data (Table10-5). PORTC pins have Schmitt Trigger input ; direction buffers. MOVWF TRISC ; Set RC<3:0> as inputs When enabling peripheral functions, care should be ; RC<5:4> as outputs taken in defining TRIS bits for each PORTC pin. Some ; RC<7:6> as inputs peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Note: On a Power-on Reset, these pins are configured as digital inputs. FIGURE 10-8: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) PORTC/Peripheral Out Select Peripheral Data Out 0 VDD P RD LATC 1 Data Bus D Q WR LATC or I/O pin(1) CK Q WR PORTC Data Latch N TRIS OVERRIDE D Q Pin Override Peripheral WR TRISC TRIS VSS CK Q Override RC0 Yes Timer1 Osc for Logic Timer1/Timer3 TRIS Latch RC1 Yes Timer1 Osc for Timer1/Timer3, RD TRISC Schmitt CCP2 I/O Peripheral Output Trigger RC2 Yes CCP1 I/O Enable(2) Q D RC3 Yes SPI/I2C Master Clock EN RC4 Yes I2C Data Out RD PORTC RC5 Yes SPI Data Out Peripheral Data In RC6 Yes USART1 Async Xmit, Sync Clock Note 1: I/O pins have diode protection to VDD and VSS. RC7 Yes USART1 Sync 2: Peripheral Output Enable is only active if Peripheral Select is active. Data Out  2003-2013 Microchip Technology Inc. DS39609C-page 109

PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T13CKI bit 0 ST Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock input. RC1/T1OSI/CCP2(1) bit 1 ST Input/output port pin, Timer1 oscillator input or Capture2 input/ Compare2 output/PWM output (when CCP2MX configuration bit is disabled). RC2/CCP1 bit 2 ST Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit 4 ST RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode). RC5/SDO bit 5 ST Input/output port pin or synchronous serial port data output. RC6/TX1/CK1 bit 6 ST Input/output port pin, addressable USART1 asynchronous transmit or addressable USART1 synchronous clock. RC7/RX1/DT1 bit 7 ST Input/output port pin, addressable USART1 asynchronous receive or addressable USART1 synchronous data. Legend: ST = Schmitt Trigger input Note 1: RB3 is the alternate assignment for CCP2 when CCP2MX is set. TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu LATC LATC Data Output Register xxxx xxxx uuuu uuuu TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged DS39609C-page 110  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 10.4 PORTD, TRISD and LATD PORTD can also be configured as an 8-bit wide micro- Registers processor port (Parallel Slave Port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input PORTD is an 8-bit wide, bidirectional port. The corre- buffers are TTL. See Section10.10 “Parallel Slave sponding data direction register is TRISD. Setting a Port” for additional information on the Parallel Slave TRISD bit (= 1) will make the corresponding PORTD Port (PSP). pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) EXAMPLE 10-4: INITIALIZING PORTD will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). CLRF PORTD ; Initialize PORTD by ; clearing output The Data Latch register (LATD) is also memory ; data latches mapped. Read-modify-write operations on the LATD CLRF LATD ; Alternate method register, read and write the latched output value for ; to clear output PORTD. ; data latches MOVLW 0xCF ; Value used to PORTD is an 8-bit port with Schmitt Trigger input buff- ; initialize data ers. Each pin is individually configurable as an input or ; direction output. MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs Note: On a Power-on Reset, these pins are ; RD<7:6> as inputs configured as digital inputs. PORTD is multiplexed with the system bus as the external memory interface; I/O port functions are only available when the system bus is disabled, by setting the EBDIS bit in the MEMCOM register (MEMCON<7>). When operating as the external mem- ory interface, PORTD is the low-order byte of the multiplexed address/data bus (AD7:AD0). FIGURE 10-9: PORTD BLOCK DIAGRAM IN I/O PORT MODE PORTD/CCP1 Select PSPMODE RD LATD DataBus D Q VDD WR LATD orPORTD CK Q P Data Latch D Q I/O pin(1) WR TRISD CK Q 0 N TRIS Latch PSP Write 1 VSS TTL Buffer RD TRISD 1 Q D 0 RD PORTD 0 ENEN Schmitt Trigger Input Buffer PSP Read 1 Note1: I/O pins have diode protection to VDD and VSS.  2003-2013 Microchip Technology Inc. DS39609C-page 111

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTD RD LATD I/O pin(1) Data Bus D Q Port 0 WR LATD Data 1 orPORTD CK Data Latch D Q WR TRISD TTL CK Input Buffer TRIS Latch RD TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to VDD and VSS. DS39609C-page 112  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0/AD0 bit 0 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0. RD1/PSP1/AD1 bit 1 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1. RD2/PSP2/AD2 bit 2 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 2 or address/data bus bit 2. RD3/PSP3/AD3 bit 3 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 3 or address/data bus bit 3. RD4/PSP4/AD4 bit 4 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 4 or address/data bus bit 4. RD5/PSP5/AD5 bit 5 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 5 or address/data bus bit 5. RD6/PSP6/AD6 bit 6 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 6 or address/data bus bit 6. RD7/PSP7/AD7 bit 7 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 7 or address/data bus bit 7. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode. TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu LATD LATD Data Output Register xxxx xxxx uuuu uuuu TRISD PORTD Data Direction Register 1111 1111 1111 1111 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ---- MEMCON EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0-00 --00 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.  2003-2013 Microchip Technology Inc. DS39609C-page 113

PIC18F6520/8520/6620/8620/6720/8720 10.5 PORTE, TRISE and LATE When the Parallel Slave Port is active, three PORTE Registers pins (RE0/RD/AD8, RE1/WR/AD9 and RE2/CS/AD10) function as its control inputs. This automatically occurs PORTE is an 8-bit wide, bidirectional port. The corre- when the PSPMODE bit (PSPCON<4>) is set. Users sponding data direction register is TRISE. Setting a must also make certain that bits TRISE<2:0> are set to TRISE bit (= 1) will make the corresponding PORTE configure the pins as digital inputs and the ADCON1 pin an input (i.e., put the corresponding output driver in register is configured for digital I/O. The PORTE PSP a high-impedance mode). Clearing a TRISE bit (= 0) control functions are summarized in Table10-9. will make the corresponding PORTE pin an output (i.e., Pin RE7 can be configured as the alternate peripheral put the contents of the output latch on the selected pin). pin for CCP module 2 when the device is operating in Read-modify-write operations on the LATE register, Microcontroller mode. This is done by clearing the read and write the latched output value for PORTE. configuration bit, CCP2MX, in configuration register, PORTE is an 8-bit port with Schmitt Trigger input buff- CONFIG3H (CONFIG3H<0>). ers. Each pin is individually configurable as an input or Note: For PIC18F8X20 (80-pin) devices operat- output. PORTE is multiplexed with the CCP module ing in Extended Microcontroller mode, (Table10-9). PORTE defaults to the system bus on On PIC18F8X20 devices, PORTE is also multiplexed Power-on Reset. with the system bus as the external memory interface; the I/O bus is available only when the system bus is EXAMPLE 10-5: INITIALIZING PORTE disabled, by setting the EBDIS bit in the MEMCON CLRF PORTE ; Initialize PORTE by register (MEMCON<7>). If the device is configured in ; clearing output Microprocessor or Extended Microcontroller mode, ; data latches then the PORTE<7:0> becomes the high byte of the CLRF LATE ; Alternate method address/data bus for the external program memory ; to clear output interface. In Microcontroller mode, the PORTE<2:0> ; data latches pins become the control inputs for the Parallel Slave MOVLW 0x03 ; Value used to Port when bit PSPMODE (PSPCON<4>) is set. (Refer ; initialize data ; direction to Section4.1.1 “PIC18F8X20 Program Memory MOVWF TRISE ; Set RE1:RE0 as inputs Modes” for more information on program memory ; RE7:RE2 as outputs modes.) DS39609C-page 114  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-11: PORTE BLOCK DIAGRAM IN I/O MODE Peripheral Out Select Peripheral Data Out 0 VDD P RD LATE 1 I/O pin(1) Data Bus D Q WR LATE or WR PORTE CK Q Data Latch N D Q TRIS OVERRIDE VSS WR TRISE TRIS CK Q Pin Override Peripheral Override TRIS Latch RE0 Yes External Bus RE1 Yes External Bus RD TRISE Schmitt RE2 Yes External Bus Peripheral Enable Trigger RE3 Yes External Bus Q D RE4 Yes External Bus RE5 Yes External Bus EN RE6 Yes External Bus RD PORTE RE7 Yes External Bus Peripheral Data In Note 1: I/O pins have diode protection to VDD and VSS. FIGURE 10-12: PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTE RD LATE I/O pin(1) Data Bus D Q Port 0 WR LATE Data 1 orPORTE CK Data Latch D Q WR TRISE TTL CK Input Buffer TRIS Latch RD TRISE Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to VDD and VSS.  2003-2013 Microchip Technology Inc. DS39609C-page 115

PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/RD/AD8 bit 0 ST/TTL(1) Input/output port pin, read control for Parallel Slave Port or address/data bit 8 For RD (PSP Control mode): 1 = Not a read operation 0 = Read operation, reads PORTD register (if chip selected) RE1/WR/AD9 bit 1 ST/TTL(1) Input/output port pin, write control for Parallel Slave Port or address/data bit 9 For WR (PSP Control mode): 1 = Not a write operation 0 = Write operation, writes PORTD register (if chip selected) RE2/CS/AD10 bit 2 ST/TTL(1) Input/output port pin, chip select control for Parallel Slave Port or address/data bit 10 For CS (PSP Control mode): 1 = Device is not selected 0 = Device is selected RE3/AD11 bit 3 ST/TTL(1) Input/output port pin or address/data bit 11. RE4/AD12 bit 4 ST/TTL(1) Input/output port pin or address/data bit 12. RE5/AD13 bit 5 ST/TTL(1) Input/output port pin or address/data bit 13. RE6/AD14 bit 6 ST/TTL(1) Input/output port pin or address/data bit 14. RE7/CCP2/AD15 bit 7 ST/TTL(1) Input/output port pin, Capture2 input/Compare2 output/PWM output (PIC18F8X20 devices in Microcontroller mode only) or address/data bit 15. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O or CCP mode and TTL buffers when in System Bus or PSP Control mode. TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TRISE PORTE Data Direction Control Register 1111 1111 1111 1111 PORTE Read PORTE pin/Write PORTE Data Latch xxxx xxxx uuuu uuuu LATE Read PORTE Data Latch/Write PORTE Data Latch xxxx xxxx uuuu uuuu MEMCON EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0000 --00 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ---- Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTE. DS39609C-page 116  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 10.6 PORTF, LATF and TRISF Registers EXAMPLE 10-6: INITIALIZING PORTF CLRF PORTF ; Initialize PORTF by PORTF is an 8-bit wide, bidirectional port. The corre- ; clearing output sponding data direction register is TRISF. Setting a ; data latches TRISF bit (= 1) will make the corresponding PORTF pin CLRF LATF ; Alternate method an input (i.e., put the corresponding output driver in a ; to clear output high-impedance mode). Clearing a TRISF bit (= 0) will ; data latches make the corresponding PORTF pin an output (i.e., put MOVLW 0x07 ; the contents of the output latch on the selected pin). MOVWF CMCON ; Turn off comparators MOVLW 0x0F ; Read-modify-write operations on the LATF register, MOVWF ADCON1 ; Set PORTF as digital I/O read and write the latched output value for PORTF. MOVLW 0xCF ; Value used to ; initialize data PORTF is multiplexed with several analog peripheral ; direction functions, including the A/D converter inputs and MOVWF TRISF ; Set RF3:RF0 as inputs comparator inputs, outputs and voltage reference. ; RF5:RF4 as outputs Note1: On a Power-on Reset, the RF6:RF0 pins ; RF7:RF6 as inputs are configured as inputs and read as ‘0’. 2: To configure PORTF as digital I/O, turn off comparators and set ADCON1 value. FIGURE 10-13: PORTF RF1/AN6/C2OUT, RF2/AN7/C1OUT PINS BLOCK DIAGRAM Port/Comparator Select Comparator Data Out 0 VDD P 1 RD LATF Data Bus D Q WR LATF I/O pin or CK Q WR PORTF Data Latch N D Q WR TRISF VSS CK Q TRIS Latch Analog Input Mode RD TRISF Schmitt Trigger Q D EN RD PORTF To A/D Converter Note 1: I/O pins have diode protection to VDD and VSS.  2003-2013 Microchip Technology Inc. DS39609C-page 117

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-14: RF6:RF3 AND RF0 PINS FIGURE 10-15: RF7 PIN BLOCK BLOCK DIAGRAM DIAGRAM RD LATF RD LATF Data DBuasta Bus D Q D Q WR LATF WR LATFor I/O pin or VDD WR PORTF CK WR PORTF CK Q P Data Latch Data Latch D Q D Q N I/O pin Schmitt WR TRISF Trigger CK Input WR TRISF CK Q VSS TRIS Latch Buffer TTL Analog Input TRIS Latch IMnpoudet Buffer RD TRISF RD TRISF ST Input Q D Buffer Q D ENEN EN RD PORTF RD PORTF SS Input To A/D Converter or Comparator Input Note 1: I/O pins have diode protection to VDD and VSS. Note: I/O pins have diode protection to VDD and VSS. DS39609C-page 118  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-11: PORTF FUNCTIONS Name Bit# Buffer Type Function RF0/AN5 bit 0 ST Input/output port pin or analog input. RF1/AN6/C2OUT bit 1 ST Input/output port pin, analog input or comparator 2 output. RF2/AN7/C1OUT bit 2 ST Input/output port pin, analog input or comparator 1 output. RF3/AN8 bit 3 ST Input/output port pin or analog input/comparator input. RF4/AN9 bit 4 ST Input/output port pin or analog input/comparator input. RF5/AN10/CVREF bit 5 ST Input/output port pin, analog input/comparator input or comparator reference output. RF6/AN11 bit 6 ST Input/output port pin or analog input/comparator input. RF7/SS bit 7 ST/TTL Input/output port pin or slave select pin for synchronous serial port. Legend: ST = Schmitt Trigger input, TTL = TTL input TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TRISF PORTF Data Direction Control Register 1111 1111 1111 1111 PORTF Read PORTF pin/Write PORTF Data Latch xxxx xxxx uuuu uuuu LATF Read PORTF Data Latch/Write PORTF Data Latch 0000 0000 uuuu uuuu ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTF.  2003-2013 Microchip Technology Inc. DS39609C-page 119

PIC18F6520/8520/6620/8620/6720/8720 10.7 PORTG, TRISG and LATG make a pin an input. The user should refer to the Registers corresponding peripheral section for the correct TRIS bit settings. PORTG is a 5-bit wide, bidirectional port. The corre- Note: On a Power-on Reset, these pins are sponding data direction register is TRISG. Setting a configured as digital inputs. TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in The pin override value is not loaded into the TRIS reg- a high-impedance mode). Clearing a TRISG bit (= 0) ister. This allows read-modify-write of the TRIS register, will make the corresponding PORTC pin an output (i.e., without concern due to peripheral overrides. put the contents of the output latch on the selected pin). The Data Latch register (LATG) is also memory EXAMPLE 10-7: INITIALIZING PORTG mapped. Read-modify-write operations on the LATG CLRF PORTG ; Initialize PORTG by register, read and write the latched output value for ; clearing output PORTG. ; data latches CLRF LATG ; Alternate method PORTG is multiplexed with both CCP and USART ; to clear output functions (Table10-13). PORTG pins have Schmitt ; data latches Trigger input buffers. MOVLW 0x04 ; Value used to When enabling peripheral functions, care should be ; initialize data ; direction taken in defining TRIS bits for each PORTG pin. Some MOVWF TRISG ; Set RG1:RG0 as outputs peripherals override the TRIS bit to make a pin an ; RG2 as input output, while other peripherals override the TRIS bit to ; RG4:RG3 as inputs FIGURE 10-16: PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) PORTG/Peripheral Out Select Peripheral Data Out 0 VDD P RD LATG 1 Data Bus D Q WR LATG or I/O pin(1) CK Q WR PORTG Data Latch N D Q WR TRISG CK Q OTvRerIrSide VSS Logic TRIS Latch RD TRISG Schmitt Peripheral Output Trigger TRIS OVERRIDE Enable(2) Q D Pin Override Peripheral RG0 Yes CCP3 I/O EN RD PORTG RG1 Yes USART1 Async Xmit, Sync Clock Peripheral Data In RG2 Yes USART1 Async Rcv, Sync Data Out Note 1: I/O pins have diode protection to VDD and VSS. RG3 Yes CCP4 I/O 2: Peripheral Output Enable is only active if Peripheral Select is active. RG4 Yes CCP5 I/O DS39609C-page 120  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-13: PORTG FUNCTIONS Name Bit# Buffer Type Function RG0/CCP3 bit 0 ST Input/output port pin or Capture3 input/Compare3 output/PWM3 output. RG1/TX2/CK2 bit 1 ST Input/output port pin, addressable USART2 asynchronous transmit or addressable USART2 synchronous clock. RG2/RX2/DT2 bit 2 ST Input/output port pin, addressable USART2 asynchronous receive or addressable USART2 synchronous data. RG3/CCP4 bit 3 ST Input/output port pin or Capture4 input/Compare4 output/PWM4 output. RG4/CCP5 bit 4 ST Input/output port pin or Capture5 input/Compare5 output/PWM5 output. Legend: ST = Schmitt Trigger input TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTG — — — Read PORTF pin/Write PORTF Data Latch ---x xxxx ---u uuuu LATG — — — LATG Data Output Register ---x xxxx ---u uuuu TRISG — — — Data Direction Control Register for PORTG ---1 1111 ---1 1111 Legend: x = unknown, u = unchanged  2003-2013 Microchip Technology Inc. DS39609C-page 121

PIC18F6520/8520/6620/8620/6720/8720 10.8 PORTH, LATH and TRISH FIGURE 10-17: RH3:RH0 PINS BLOCK Registers DIAGRAM IN I/O MODE Note: PORTH is available only on PIC18F8X20 devices. RD LATH PORTH is an 8-bit wide, bidirectional I/O port. The cor- Data Bus responding data direction register is TRISH. Setting a D Q TRISH bit (= 1) will make the corresponding PORTH I/O pin(1) WR LATH pin an input (i.e., put the corresponding output driver in CK or a high-impedance mode). Clearing a TRISH bit (= 0) PORTH Data Latch will make the corresponding PORTH pin an output (i.e., put the contents of the output latch on the selected pin). D Q Read-modify-write operations on the LATH register, WR TRISH Schmitt read and write the latched output value for PORTH. CK Trigger Input TRIS Latch Pins RH7:RH4 are multiplexed with analog inputs Buffer AN15:AN12. Pins RH3:RH0 are multiplexed with the RD TRISH system bus as the external memory interface; they are the high-order address bits, A19:A16. By default, pins RH7:RH4 are enabled as A/D inputs and pins RH3:RH0 are enabled as the system address bus. Q D Register ADCON1 configures RH7:RH4 as I/O or A/D inputs. Register MEMCON configures RH3:RH0 as I/O ENEN or system bus pins. RD PORTH Note1: On Power-on Reset, PORTH pins RH7:RH4 default to A/D inputs and read Note 1: I/O pins have diode protection to VDD and VSS. as ‘0’. 2: On Power-on Reset, PORTH pins FIGURE 10-18: RH7:RH4 PINS BLOCK RH3:RH0 default to system bus signals. DIAGRAM IN I/O MODE EXAMPLE 10-8: INITIALIZING PORTH RD LATH CLRF PORTH ; Initialize PORTH by ; clearing output Data Bus ; data latches D Q CLRF LATH ; Alternate method I/O pin(1) ; to clear output WR LATH CK ; data latches or MOVLW 0Fh ; PORTH Data Latch MOVWF ADCON1 ; D Q MOVLW 0CFh ; Value used to Schmitt ; initialize data Trigger ; direction WR TRISH CK Input Buffer MOVWF TRISH ; Set RH3:RH0 as inputs TRIS Latch ; RH5:RH4 as outputs ; RH7:RH6 as inputs RD TRISH Q D ENEN RD PORTH To A/D Converter Note 1: I/O pins have diode protection to VDD and VSS. DS39609C-page 122  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-19: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTH RD LATD I/O pin(1) Data Bus Port D Q 0 Data WR LATH 1 or CK PORTH Data Latch D Q WR TRISH TTL CK Input Buffer TRIS Latch RD TRISH External Enable System Bus Address Out Control Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to VDD and VSS.  2003-2013 Microchip Technology Inc. DS39609C-page 123

PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-15: PORTH FUNCTIONS Name Bit# Buffer Type Function RH0/A16 bit 0 ST/TTL(1) Input/output port pin or address bit 16 for external memory interface. RH1/A17 bit 1 ST/TTL(1) Input/output port pin or address bit 17 for external memory interface. RH2/A18 bit 2 ST/TTL(1) Input/output port pin or address bit 18 for external memory interface. RH3/A19 bit 3 ST/TTL(1) Input/output port pin or address bit 19 for external memory interface. RH4/AN12 bit 4 ST Input/output port pin or analog input channel 12. RH5/AN13 bit 5 ST Input/output port pin or analog input channel 13. RH6/AN14 bit 6 ST Input/output port pin or analog input channel 14. RH7/AN15 bit 7 ST Input/output port pin or analog input channel 15. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode. TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TRISH PORTH Data Direction Control Register 1111 1111 1111 1111 PORTH Read PORTH pin/Write PORTH Data Latch xxxx xxxx uuuu uuuu LATH Read PORTH Data Latch/Write PORTH Data Latch xxxx xxxx uuuu uuuu ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 MEMCON EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0-00 --00 Legend: x = unknown, u = unchanged, – = unimplemented. Shaded cells are not used by PORTH. DS39609C-page 124  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 10.9 PORTJ, TRISJ and LATJ FIGURE 10-20: PORTJ BLOCK DIAGRAM Registers IN I/O MODE Note: PORTJ is available only on PIC18F8X20 devices. RD LATJ PORTJ is an 8-bit wide, bidirectional port. The corre- Data Bus sponding data direction register is TRISJ. Setting a D Q TRISJ bit (= 1) will make the corresponding PORTJ pin I/O pin(1) WR LATJ an input (i.e., put the corresponding output driver in a CK or high-impedance mode). Clearing a TRISJ bit (= 0) will PORTJ Data Latch make the corresponding PORTJ pin an output (i.e., put the contents of the output latch on the selected pin). D Q Schmitt The Data Latch register (LATJ) is also memory WR TRISJ Trigger mapped. Read-modify-write operations on the LATJ CK Input register, read and write the latched output value for TRIS Latch Buffer PORTJ. RD TRISJ PORTJ is multiplexed with the system bus as the exter- nal memory interface; I/O port functions are only avail- able when the system bus is disabled. When operating as the external memory interface, PORTJ provides the Q D control signal to external memory devices. The RJ5 pin is not multiplexed with any system bus functions. ENEN RD PORTJ When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTJ pin. Some peripherals override the TRIS bit to make a pin an Note 1: I/O pins have diode protection to VDD and VSS. output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corre- sponding peripheral section for the correct TRIS bit settings. Note: On a Power-on Reset, these pins are configured as digital inputs. The pin override value is not loaded into the TRIS reg- ister. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides. EXAMPLE 10-9: INITIALIZING PORTJ CLRF PORTJ ; Initialize PORTG by ; clearing output ; data latches CLRF LATJ ; Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs  2003-2013 Microchip Technology Inc. DS39609C-page 125

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-21: RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTJ RD LATJ I/O pin(1) Data Bus Port D Q 0 Data WR LATJ 1 CK or PORTJ Data Latch D Q WR TRISJ CK TRIS Latch RD TRISJ Control Out System Bus External Enable Control Drive System Note 1: I/O pins have diode protection to VDD and VSS. FIGURE 10-22: RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTJ RD LATJ I/O pin(1) Data Bus Port D Q 0 Data 1 WR LATJ CK or PORTJ Data Latch D Q WR TRISJ CK TRIS Latch RD TRISJ UB/LB Out WM = 01 System Bus Control Drive System Note 1: I/O pins have diode protection to VDD and VSS. DS39609C-page 126  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-17: PORTJ FUNCTIONS Name Bit# Buffer Type Function RJ0/ALE bit 0 ST Input/output port pin or address latch enable control for external memory interface. RJ1/OE bit 1 ST Input/output port pin or output enable control for external memory interface. RJ2/WRL bit 2 ST Input/output port pin or write low byte control for external memory interface. RJ3/WRH bit 3 ST Input/output port pin or write high byte control for external memory interface. RJ4/BA0 bit 4 ST Input/output port pin or byte address 0 control for external memory interface. RJ5/CE bit 5 ST Input/output port pin or chip enable control for external memory interface. RJ6/LB bit 6 ST Input/output port pin or lower byte select control for external memory interface. RJ7/UB bit 7 ST Input/output port pin or upper byte select control for external memory interface. Legend: ST = Schmitt Trigger input TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTJ Read PORTJ pin/Write PORTJ Data Latch xxxx xxxx uuuu uuuu LATJ LATJ Data Output Register xxxx xxxx uuuu uuuu TRISJ Data Direction Control Register for PORTJ 1111 1111 1111 1111 Legend: x = unknown, u = unchanged  2003-2013 Microchip Technology Inc. DS39609C-page 127

PIC18F6520/8520/6620/8620/6720/8720 10.10 Parallel Slave Port FIGURE 10-23: PORTD AND PORTE BLOCK DIAGRAM PORTD also operates as an 8-bit wide Parallel Slave (PARALLEL SLAVE PORT) Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set. It is asynchronously readable and writable by the external world through the Data Bus D Q RD control input pin, RE0/RD/AD8 and the WR control input pin, RE1/WR/AD9. RDx WR LATD CK pin or Note: For PIC18F8X20 devices, the Parallel PORTD Data Latch TTL Slave Port is available only in Microcontroller mode. Q D The PSP can directly interface to an 8-bit micro- processor data bus. The external microprocessor can RD PORTD ENEN read or write the PORTD latch as an 8-bit latch. Setting TRIS Latch bit PSPMODE enables port pin RE0/RD/AD8 to be the RD input, RE1/WR/AD9 to be the WR input and RE2/ CS/AD10 to be the CS (Chip Select) input. For this RD LATD functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits, One bit of PORTD PCFG2:PCFG0 (ADCON1<2:0>), must be set which will configure pins RE2:RE0 as digital I/O. Set Interrupt Flag A write to the PSP occurs when both the CS and WR PSPIF (PIR1<7>) lines are first detected low. A read from the PSP occurs when both the CS and RD lines are first detected low. The PORTE I/O pins become control inputs for the microprocessor port when bit PSPMODE (PSPCON<4>) is set. In this mode, the user must make Read sure that the TRISE<2:0> bits are set (pins are config- TTL RD ured as digital inputs) and the ADCON1 is configured Chip Select for digital I/O. In this mode, the input buffers are TTL. TTL CS Write TTL WR Note: I/O pin has protection diodes to VDD and VSS. DS39609C-page 128  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 10-1: PSPCON REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown FIGURE 10-24: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF  2003-2013 Microchip Technology Inc. DS39609C-page 129

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-25: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu LATD LATD Data Output bits xxxx xxxx uuuu uuuu TRISD PORTD Data Direction bits 1111 1111 1111 1111 PORTE — — — — — Read PORTE pin/ 0000 0000 0000 0000 Write PORTE Data Latch LATE — — — — — LATE Data Output bits xxxx xxxx uuuu uuuu TRISE — — — — — PORTE Data Direction bits 1111 1111 1111 1111 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ---- INTCON GIE/ PEIE/ TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 GIEH GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices. DS39609C-page 130  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 11.0 TIMER0 MODULE Figure11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure11-2 shows a The Timer0 module has the following features: simplified block diagram of the Timer0 module in 16-bit • Software selectable as an 8-bit or mode. 16-bit timer/counter The T0CON register (Register11-1) is a readable and • Readable and writable writable register that controls all the aspects of Timer0, • Dedicated 8-bit software programmable prescaler including the prescale selection. • Clock source selectable to be external or internal • Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode • Edge select for external clock REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 131

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 0 Sync with 1 Internal TMR0 Clocks RA4/T0CKI pin Programmable 1 Prescaler T0SE (2 TCY delay) 3 PSA Set Interrupt T0PS2, T0PS1, T0PS0 Flag bit TMR0IF T0CS on Overflow Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE FOSC/4 0 0 Sync with Set Interrupt 1 ICntleocrnkasl TMR0L HTigMh RB0yte Flag bit TMR0IF RA4/T0CKI Programmable 1 on Overflow pin T0SE Prescaler (2 TCY delay) 8 3 PSA Read TMR0L T0PS2, T0PS1, T0PS0 Write TMR0L T0CS 8 8 TMR0H 8 Data Bus<7:0> Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39609C-page 132  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 11.1 Timer0 Operation 11.2.1 SWITCHING PRESCALER ASSIGNMENT Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software Timer mode is selected by clearing the T0CS bit. In control, (i.e., it can be changed “on-the-fly” during Timer mode, the Timer0 module will increment every program execution). instruction cycle (without prescaler). If the TMR0 regis- ter is written, the increment is inhibited for the following 11.3 Timer0 Interrupt two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The TMR0 interrupt is generated when the TMR0 Counter mode is selected by setting the T0CS bit. In register overflows from FFh to 00h in 8-bit mode, or Counter mode, Timer0 will increment, either on every FFFFh to 0000h in 16-bit mode. This overflow sets the rising or falling edge of pin RA4/T0CKI. The increment- TMR0IF bit. The interrupt can be masked by clearing ing edge is determined by the Timer0 Source Edge the TMR0IE bit. The TMR0IF bit must be cleared in Select bit (T0SE). Clearing the T0SE bit selects the software by the Timer0 module Interrupt Service rising edge. Restrictions on the external clock input are Routine before re-enabling this interrupt. The TMR0 discussed below. interrupt cannot awaken the processor from Sleep, since the timer is shut-off during Sleep. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure 11.4 16-Bit Mode Timer Reads the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual and Writes incrementing of Timer0 after synchronization. TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the 11.2 Prescaler high byte of Timer0 (refer to Figure11-2). The high byte An 8-bit counter is available as a prescaler for the Timer0 of the Timer0 counter/timer is not directly readable nor module. The prescaler is not readable or writable. writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This pro- The PSA and T0PS2:T0PS0 bits determine the vides the ability to read all 16 bits of Timer0 without prescaler assignment and prescale ratio. having to verify that the read of the high and low byte Clearing bit PSA will assign the prescaler to the Timer0 were valid, due to a rollover between successive reads module. When the prescaler is assigned to the Timer0 of the high and low byte. module, prescale values of 1:2, 1:4, ..., 1:256 are A write to the high byte of Timer0 must also take place selectable. through the TMR0H Buffer register. Timer0 high byte is When assigned to the Timer0 module, all instructions updated with the contents of TMR0H when a write writing to the TMR0 register (e.g., CLRF TMR0, MOVWF occurs to TMR0L. This allows all 16 bits of Timer0 to be TMR0, BSF TMR0, x, ..., etc.) will clear the prescaler updated at once. count. Note: Writing to TMR0 when the prescaler is assigned to Timer0, will clear the prescaler count, but will not change the prescaler assignment. TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TMR0L Timer0 Module Low Byte Register xxxx xxxx uuuu uuuu TMR0H Timer0 Module High Byte Register 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111 TRISA — PORTA Data Direction Register -111 1111 -111 1111 Legend: x = unknown, u = unchanged, – = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.  2003-2013 Microchip Technology Inc. DS39609C-page 133

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 134  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 12.0 TIMER1 MODULE Register12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 The Timer1 module timer/counter has the following module and contains the Timer1 Oscillator Enable bit features: (T1OSCEN). Timer1 can be enabled or disabled by • 16-bit timer/counter setting or clearing control bit, TMR1ON (T1CON<0>). (two 8-bit registers: TMR1H and TMR1L) Timer1 can also be used to provide Real-Time Clock • Readable and writable (both registers) (RTC) functionality to applications, with only a minimal • Internal or external clock select addition of external components and code overhead. • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module special event trigger Figure12-1 is a simplified block diagram of the Timer1 module. REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 Unimplemented: Read as ‘0’ bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 135

PIC18F6520/8520/6620/8620/6720/8720 12.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruc- tion cycle. When TMR1CS = 1, Timer1 increments on Timer1 can operate in one of these modes: every rising edge of the external clock input or the • As a timer Timer1 oscillator, if enabled. • As a synchronous counter When the Timer1 oscillator is enabled (T1OSCEN is • As an asynchronous counter set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. That is, the TRISC<1:0> value is The operating mode is determined by the clock select ignored and the pins are read as ‘0’. bit, TMR1CS (T1CON<1>). Timer1 also has an internal “Reset input”. This Resetcan be generated by the CCP module (seeSection16.0 “Capture/Compare/PWM (CCP) Modules”). FIGURE 12-1: TIMER1 BLOCK DIAGRAM CCP Special Event Trigger TMR1IF Overflow Interrupt TMR1 0 Synchronized Flag Bit CLR Clock Input TMR1H TMR1L 1 TMR1ON On/Off T1SYNC T1OSC T1OSO/T13CKI 1 T1OSCEN Prescaler Synchronize T1OSI EOnsaciblllaetor(1) IFnOteSrCn/a4l 0 1, 2, 4, 8 det Clock 2 Sleep Input T1CKPS1:T1CKPS0 TMR1CS Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR1H 8 8 Write TMR1L CCP Special Event Trigger Read TMR1L TOInMvteeRrrrf1uloIpFwt 8 Timer 1 TMR1 CLR 0 SyCnlocchkro Innipzuetd Flag bit High Byte TMR1L 1 TMR1ON On/Off T1SYNC T1OSC T1OSO/T13CKI 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 TMR1CS Sleep Input T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS39609C-page 136  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 12.2 Timer1 Oscillator 12.2.1 LOW-POWER TIMER1 OPTION (PIC18FX520 DEVICES ONLY) A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by The Timer1 oscillator for PIC18LFX520 devices incor- setting control bit, T1OSCEN (T1CON<3>). The oscil- porates a low-power feature, which allows the oscillator lator is a low-power oscillator, rated up to 200 kHz. It to automatically reduce its power consumption when will continue to run during Sleep. It is primarily intended the microcontroller is in Sleep mode. for a 32 kHz crystal. The circuit for a typical LP oscilla- As high noise environments may cause excessive tor is shown in Figure12-3. Table12-1 shows the oscillator instability in Sleep mode, this option is best capacitor selection for the Timer1 oscillator. suited for low noise applications where power The user must provide a software time delay to ensure conservation is an important design consideration. Due proper start-up of the Timer1 oscillator to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. FIGURE 12-3: EXTERNAL The oscillator circuit, shown in Figure12-3, should be COMPONENTS FOR THE located as close as possible to the microcontroller. TIMER1 LP OSCILLATOR There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. C1 PIC18FXX20 If a high-speed circuit must be located near the oscilla- 33 pF T1OSI tor (such as the CCP1 pin in output compare or PWM mode, or the primary oscillator using the OSC2 pin), a XTAL grounded guard ring around the oscillator circuit, as 32.768 kHz shown in Figure12-4, may be helpful when used on a single-sided PCB or in addition to a ground plane. T1OSO C2 FIGURE 12-4: OSCILLATOR CIRCUIT 33 pF WITH GROUNDED Note: See the Notes with Table12-1 for additional GUARD RING information about capacitor selection. VDD TABLE 12-1: CAPACITOR SELECTION VSS FOR THE ALTERNATE OSCILLATOR OSC1 Osc Type Freq C1 C2 OSC2 LP 32 kHz TBD(1) TBD(1) Crystal to be Tested: RC0 32.768 kHz Epson C-001R32.768K-A  20 PPM RC1 Note1: Microchip suggests 33pF as a starting point in validating the oscillator circuit. RC2 2: Higher capacitance increases the stability Note: Not drawn to scale. of the oscillator, but also increases the start-up time. Note: PIC18FX620/X720 devices have the 3: Since each resonator/crystal has its own standard Timer1 oscillator permanently characteristics, the user should consult selected. PIC18LFX620/X720 devices the resonator/crystal manufacturer for have the low-power Timer1 oscillator appropriate values of external permanently selected. components. 4: Capacitor values are for design guidance only.  2003-2013 Microchip Technology Inc. DS39609C-page 137

PIC18F6520/8520/6620/8620/6720/8720 12.3 Timer1 Interrupt 12.6 Using Timer1 as a Real-Time Clock The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Adding an external LP oscillator to Timer1 (such as the TMR1 interrupt, if enabled, is generated on overflow, one described in Section12.2 “Timer1 Oscillator”) which is latched in interrupt flag bit, TMR1IF gives users the option to include RTC functionality to (PIR1<0>). This interrupt can be enabled/disabled by their applications. This is accomplished with an inex- setting/clearing TMR1 Interrupt Enable bit, TMR1IE pensive watch crystal to provide an accurate time base (PIE1<0>). and several lines of application code to calculate the time. When operating in Sleep mode and using a 12.4 Resetting Timer1 Using a CCP battery or supercapacitor as a power source, it can Trigger Output completely eliminate the need for a separate RTC device and battery backup. If the CCP module is configured in Compare mode The application code routine, RTCisr, shown in to generate a “special event trigger” Example12-1, demonstrates a simple method to incre- (CCP1M3:CCP1M0=1011), this signal will reset ment a counter at one-second intervals using an Timer1 and start an A/D conversion (if the A/D module Interrupt Service Routine. Incrementing the TMR1 is enabled). register pair to overflow, triggers the interrupt and calls Note: The special event triggers from the CCP1 the routine, which increments the seconds counter by module will not set interrupt flag bit one; additional counters for minutes and hours are TMR1IF (PIR1<0>). incremented as the previous counter overflow. Timer1 must be configured for either Timer or Synchro- Since the register pair is 16 bits wide, counting up to nized Counter mode to take advantage of this feature. overflow the register directly from a 32.768kHz clock If Timer1 is running in Asynchronous Counter mode, would take 2 seconds. To force the overflow at the this Reset operation may not work. required one-second intervals, it is necessary to preload it; the simplest method is to set the MSb of In the event that a write to Timer1 coincides with a TMR1H with a BSF instruction. Note that the TMR1L special event trigger from CCP1, the write will take register is never preloaded or altered; doing so may precedence. introduce cumulative error over many cycles. In this mode of operation, the CCPR1H:CCPR1L For this method to be accurate, Timer1 must operate in register pair effectively becomes the period register for Asynchronous mode and the Timer1 overflow interrupt Timer1. must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be 12.5 Timer1 16-Bit Read/Write Mode enabled and running at all times. Timer1 can be configured for 16-bit reads and writes (see Figure12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid, due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writ- able in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. DS39609C-page 138  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 0x80 ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1OSC ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done MOVLW .01 ; Reset hours to 1 MOVWF hours RETURN ; Done TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.  2003-2013 Microchip Technology Inc. DS39609C-page 139

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 140  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 13.0 TIMER2 MODULE 13.1 Timer2 Operation The Timer2 module timer has the following features: Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is • 8-bit timer (TMR2 register) readable and writable and is cleared on any device • 8-bit period register (PR2) Reset. The input clock (FOSC/4) has a prescale option • Readable and writable (both registers) of 1:1, 1:4 or 1:16, selected by control bits, • Software programmable prescaler (1:1, 1:4, 1:16) T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out- • Software programmable postscaler (1:1 to 1:16) put of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a • Interrupt on TMR2 match of PR2 TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)). • SSP module optional use of TMR2 output to generate clock shift The prescaler and postscaler counters are cleared when any of the following occurs: Timer2 has a control register shown in Register13-1. Timer2 can be shut-off by clearing control bit, TMR2ON • a write to the TMR2 register (T2CON<2>), to minimize power consumption. • a write to the T2CON register Figure13-1 is a simplified block diagram of the Timer2 • any device Reset (Power-on Reset, MCLR Reset, module. Register13-1 shows the Timer2 Control regis- Watchdog Timer Reset or Brown-out Reset) ter. The prescaler and postscaler selection of Timer2 TMR2 is not cleared when T2CON is written. are controlled by this register. REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 141

PIC18F6520/8520/6620/8620/6720/8720 13.2 Timer2 Interrupt 13.3 Output of TMR2 The Timer2 module has an 8-bit period register, PR2. The output of TMR2 (before the postscaler) is fed to the Timer2 increments from 00h until it matches PR2 and synchronous serial port module, which optionally uses then resets to 00h on the next increment cycle. PR2 is it to generate the shift clock. a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 Output(1) bit TMR2IF Prescaler Reset FOSC/4 TMR2 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T2CKPS1:T2CKPS0 PR2 4 T2OUTPS3:T2OUTPS0 Note 1: TMR2 register output can be software selected by the SSP module as a baud clock. TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 TMR2 Timer2 Module Register 0000 0000 0000 0000 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. DS39609C-page 142  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 14.0 TIMER3 MODULE Figure14-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following Register14-1 shows the Timer3 Control register. This features: register controls the operating mode of the Timer3 • 16-bit timer/counter module and sets the CCP clock source. (two 8-bit registers; TMR3H and TMR3L) Register12-1 shows the Timer1 Control register. This • Readable and writable (both registers) register controls the operating mode of the Timer1 • Internal or external clock select module, as well as contains the Timer1 Oscillator • Interrupt-on-overflow from FFFFh to 0000h Enable bit (T1OSCEN), which can be a clock source for • Reset from CCP module trigger Timer3. REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 11 = Timer3 and Timer4 are the clock sources for CCP1 through CCP5 10 = Timer3 and Timer4 are the clock sources for CCP3 through CCP5; Timer1 and Timer2 are the clock sources for CCP1 and CCP2 01 = Timer3 and Timer4 are the clock sources for CCP2 through CCP5; Timer1 and Timer2 are the clock sources for CCP1 00 = Timer1 and Timer2 are the clock sources for CCP1 through CCP5 bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 143

PIC18F6520/8520/6620/8620/6720/8720 14.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruc- tion cycle. When TMR3CS = 1, Timer3 increments on Timer3 can operate in one of these modes: every rising edge of the Timer1 external clock input or • As a timer the Timer1 oscillator, if enabled. • As a synchronous counter When the Timer1 oscillator is enabled (T1OSCEN is • As an asynchronous counter set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. That is, the TRISC<1:0> value is The operating mode is determined by the clock select ignored and the pins are read as ‘0’. bit, TMR3CS (T3CON<1>). Timer3 also has an internal “Reset input”. This Reset can be generated by the CCP module (see Section14.0 “Timer3 Module”). FIGURE 14-1: TIMER3 BLOCK DIAGRAM CCP Special Trigger TMR3IF T3CCPx Overflow Interrupt Synchronized 0 Flag bit CLR Clock Input TMR3H TMR3L 1 TMR3ON On/Off T3SYNC T1OSO/ T1OSC (3) 1 T13CKI Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 TMR3CS Sleep Input T3CKPS1:T3CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 14-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR3H 8 8 Write TMR3L Read TMR3L CCP Special Trigger Set TMR3IF Flag bit 8 TMR3 T3CCPx 0 Synchronized on Overflow Timer3 CLR Clock Input High Byte TMR3L 1 To Timer1 Clock Input TMR3ON On/Off T3SYNC T1OSC T1OSO/ 1 T13CKI Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 Sleep Input T3CKPS1:T3CKPS0 TMR3CS Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS39609C-page 144  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 14.2 Timer1 Oscillator 14.4 Resetting Timer3 Using a CCP Trigger Output The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting If the CCP module is configured in Compare mode the T1OSCEN (T1CON<3>) bit. The oscillator is a low- to generate a “special event trigger” power oscillator rated up to 200 kHz. See Section12.0 (CCP1M3:CCP1M0=1011), this signal will reset “Timer1 Module” for further details. Timer3. Note: The special event triggers from the CCP 14.3 Timer3 Interrupt module will not set interrupt flag bit, The TMR3 register pair (TMR3H:TMR3L) increments TMR3IF (PIR1<0>). from 0000h to FFFFh and rolls over to 0000h. The Timer3 must be configured for either Timer or Synchro- TMR3 interrupt, if enabled, is generated on overflow, nized Counter mode to take advantage of this feature. which is latched in interrupt flag bit, TMR3IF If Timer3 is running in Asynchronous Counter mode, (PIR2<1>). This interrupt can be enabled/disabled by this Reset operation may not work. In the event that a setting/clearing TMR3 Interrupt Enable bit, TMR3IE write to Timer3 coincides with a special event trigger (PIE2<1>). from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer3. TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR2 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000 PIE2 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000 IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.  2003-2013 Microchip Technology Inc. DS39609C-page 145

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 146  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 15.0 TIMER4 MODULE 15.1 Timer4 Operation The Timer4 module timer has the following features: Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is • 8-bit timer (TMR4 register) readable and writable and is cleared on any device • 8-bit period register (PR4) Reset. The input clock (FOSC/4) has a prescale option • Readable and writable (both registers) of 1:1, 1:4 or 1:16, selected by control bits • Software programmable prescaler (1:1, 1:4, 1:16) T4CKPS1:T4CKPS0 (T4CON<1:0>). The match out- • Software programmable postscaler (1:1 to 1:16) put of TMR4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a • Interrupt on TMR4 match of PR4 TMR4 interrupt, latched in flag bit, TMR4IF (PIR3<3>). Timer4 has a control register shown in Register15-1. The prescaler and postscaler counters are cleared Timer4 can be shut-off by clearing control bit, TMR4ON when any of the following occurs: (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 are also • a write to the TMR4 register controlled by this register. Figure15-1 is a simplified • a write to the T4CON register block diagram of the Timer4 module. • any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR4 is not cleared when T4CON is written. REGISTER 15-1: T4CON: TIMER4 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 T4OUTPS3:T4OUTPS0: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off bit 1-0 T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 147

PIC18F6520/8520/6620/8620/6720/8720 15.2 Timer4 Interrupt 15.3 Output of TMR4 The Timer4 module has an 8-bit period register, PR4, The output of TMR4 (before the postscaler) is used which is both readable and writable. Timer4 increments only as a PWM time base for the CCP modules. It is not from 00h until it matches PR4 and then resets to 00h on used as a baud rate clock for the MSSP, as is the the next increment cycle. The PR4 register is initialized Timer2 output. to FFh upon Reset. FIGURE 15-1: TIMER4 BLOCK DIAGRAM Sets Flag TMR4 Output(1) bit TMR4IF Prescaler Reset FOSC/4 TMR4 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T4CKPS1:T4CKPS0 PR4 4 T4OUTPS3:T4OUTPS0 TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --00 0000 PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 TMR4 Timer4 Module Register 0000 0000 0000 0000 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000 PR4 Timer4 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module. DS39609C-page 148  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 16.0 CAPTURE/COMPARE/PWM For the sake of clarity, CCP module operation in the (CCP) MODULES following sections is described with respect to CCP1. The descriptions can be applied (with the exception of The PIC18FXX20 devices all have five CCP (Capture/ the special event triggers) to any of the modules. Compare/PWM) modules. Each module contains a Note: Throughout this section, references to 16-bit register, which can operate as a 16-bit Capture register and bit names that may be associ- register, a 16-bit Compare register or a Pulse Width ated with a specific CCP module are Modulation (PWM) Master/Slave Duty Cycle register. referred to generically by the use of ‘x’ or Table16-1 shows the timer resources of the CCP ‘y’ in place of the specific module number. module modes. Thus, “CCPxCON” might refer to the The operation of all CCP modules are identical, with control register for CCP1, CCP2, CCP3, the exception of the special event trigger present on CCP4 or CCP5. CCP1 and CCP2. REGISTER 16-1: CCPxCON REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCP Module x Mode Select bits 0000 =Capture/Compare/PWM disabled (resets CCPx module) 0001 =Reserved 0010 =Compare mode, toggle output on match (CCPxIF bit is set) 0011 =Reserved 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, Initialize CCP pin Low; on compare match, force CCP pin High (CCPIF bit is set) 1001 =Compare mode, Initialize CCP pin High; on compare match, force CCP pin Low (CCPIF bit is set) 1010 =Compare mode, Generate software interrupt on compare match (CCPIF bit is set, (CCP pin is unaffected) 1011 =Compare mode, trigger special event (CCPIF bit is set): For CCP1 and CCP2: Timer1 or Timer3 is reset on event. For all other modules: CCPx pin is unaffected and is configured as an I/O port (same as CCPxM<3:0> = 1010, above). 11xx =PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 149

PIC18F6520/8520/6620/8620/6720/8720 16.1 CCP Module Configuration TABLE 16-1: CCP MODE – TIMER RESOURCE Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a CCP Mode Timer Resource data register (CCPRx). The data register, in turn, is Capture Timer1 or Timer3 comprised of two 8-bit registers: CCPRxL (low byte) Compare Timer1 or Timer3 and CCPRxH (high byte). All registers are both PWM Timer2 or Timer4 readable and writable. The assignment of a particular timer to a module is 16.1.1 CCP MODULES AND TIMER determined by the Timer-to-CCP Enable bits in the RESOURCES T3CON register (Register14-1). Depending on the The CCP modules utilize Timers 1, 2, 3 or 4, depending configuration selected, up to four timers may be active on the mode selected. Timer1 and Timer3 are available at once, with modules in the same configuration to modules in Capture or Compare modes, while (Capture/Compare or PWM) sharing timer resources. Timer2 and Timer4 are available for modules in PWM The possible configurations are shown in Figure16-1. mode. FIGURE 16-1: CCP AND TIMER INTERCONNECT CONFIGURATIONS T3CCP<2:1>=00 T3CCP<2:1>=01 T3CCP<2:1>=10 T3CCP<2:1>=11 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 CCP1 CCP1 CCP1 CCP1 CCP2 CCP2 CCP2 CCP2 CCP3 CCP3 CCP3 CCP3 CCP4 CCP4 CCP4 CCP4 CCP5 CCP5 CCP5 CCP5 TMR2 TMR4 TMR2 TMR4 TMR2 TMR4 TMR2 TMR4 Timer1 is used for all Capture Timer1 and Timer2 are used Timer1 and Timer2 are used Timer3 is used for all Capture and Compare operations for for Capture and Compare or for Capture and Compare or and Compare operations for all CCP modules. Timer2 is PWM operations for CCP1 PWM operations for CCP1 all CCP modules. Timer4 is used for PWM operations for only (depending on selected and CCP2 only (depending on used for PWM operations for all CCP modules. Modules mode). the mode selected for each all CCP modules. Modules may share either timer All other modules use either module). Both modules may may share either timer resource as a common time use a timer as a common time resource as a common time Timer3 or Timer4. Modules base. may share either timer base if they are both in base. Timer3 and Timer4 are not resource as a common time Capture/Compare or PWM Timer1 and Timer2 are not modes. available. base, if they are in Capture/ available. Compare or PWM modes. The other modules use either Timer3 or Timer4. Modules may share either timer resource as a common time base if they are in Capture/ Compare or PWM modes. DS39609C-page 150  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 16.2 Capture Mode 16.2.3 SOFTWARE INTERRUPT In Capture mode, CCPR1H:CCPR1L captures the 16-bit When the Capture mode is changed, a false capture value of the TMR1 or TMR3 registers when an event interrupt may be generated. The user should keep bit occurs on pin RC2/CCP1. An event is defined as one of CCP1IE (PIE1<2>) clear to avoid false interrupts and the following: should clear the flag bit, CCP1IF, following any such change in operating mode. • every falling edge • every rising edge 16.2.4 CCP PRESCALER • every 4th rising edge There are four prescaler settings, specified by bits • every 16th rising edge CCP1M3:CCP1M0. Whenever the CCP module is The event is selected by control bits, CCP1M3:CCP1M0 turned off or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any (CCP1CON<3:0>). When a capture is made, the inter- Reset will clear the prescaler counter. rupt request flag bit, CCP1IF (PIR1<2>), is set; it must be cleared in software. If another capture occurs before Switching from one capture prescaler to another may the value in register CCPR1 is read, the old captured generate an interrupt. Also, the prescaler counter will value is overwritten by the new captured value. not be cleared, therefore, the first capture may be from a non-zero prescaler. Example16-1 shows the 16.2.1 CCP PIN CONFIGURATION recommended method for switching between capture In Capture mode, the RC2/CCP1 pin should be prescalers. This example also clears the prescaler configured as an input by setting the TRISC<2> bit. counter and will not generate the “false” interrupt. Note: If the RC2/CCP1 is configured as an out- EXAMPLE 16-1: CHANGING BETWEEN put, a write to the port can cause a capture CAPTURE PRESCALERS condition. CLRF CCP1CON, F ; Turn CCP module off 16.2.2 TIMER1/TIMER3 MODE SELECTION MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode The timers that are to be used with the capture feature ; value and CCP ON (Timer1 and/or Timer3) must be running in Timer mode, MOVWF CCP1CON ; Load CCP1CON with or Synchronized Counter mode. In Asynchronous ; this value Counter mode, the capture operation may not work. The timer to be used with each CCP module is selected in the T3CON register (see Section16.1.1 “CCP Modules and Timer Resources”). FIGURE 16-2: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set Flag bit CCP1IF T3CCP2 TMR3 Prescaler Enable  1, 4, 16 CCP1 pin CCPR1H CCPR1L TMR1 and T3CCP2 Enable Edge Detect TMR1H TMR1L CCP1CON<3:0> Q’s  2003-2013 Microchip Technology Inc. DS39609C-page 151

PIC18F6520/8520/6620/8620/6720/8720 16.3 Compare Mode 16.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is Timer1 and/or Timer3 must be running in Timer mode, constantly compared against either the TMR1 register or Synchronized Counter mode, if the CCP module is pair value or the TMR3 register pair value. When a using the compare feature. In Asynchronous Counter match occurs, the CCP1 pin: mode, the compare operation may not work. • is driven High 16.3.3 SOFTWARE INTERRUPT MODE • is driven Low When generate software interrupt is chosen, the CCP1 • toggles output (high-to-low or low-to-high) pin is not affected. Only a CCP interrupt is generated (if • remains unchanged enabled). The action on the pin is based on the value of control 16.3.4 SPECIAL EVENT TRIGGER bits, CCP1M3:CCP1M0. At the same time, interrupt flag bit CCP1IF (CCP2IF) is set. In this mode, an internal hardware trigger is generated, which may be used to initiate an action. 16.3.1 CCP PIN CONFIGURATION The special event trigger output of either CCP1 or The user must configure the CCPx pin as an output by CCP2, resets the TMR1 or TMR3 register pair, depend- clearing the appropriate TRIS bit. ing on which timer resource is currently selected. This allows the CCPR1 register to effectively be a 16-bit Note: Clearing the CCP1CON register will force programmable period register for Timer1 or Timer3. the RC2/CCP1 compare output latch to the default low level. This is not the The CCP2 Special Event Trigger will also start an A/D PORTC I/O data latch. conversion if the A/D module is enabled. Note: The special event trigger from the CCP2 module will not set the Timer1 or Timer3 interrupt flag bits. FIGURE 16-3: COMPARE MODE OPERATION BLOCK DIAGRAM For CCP1 and CCP2 only, the Special Event Trigger will: Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion (CCP2 only) Special Event Trigger Set Flag bit CCP1IF CCPR1H CCPR1L Q S Output RC2/CCP1 pin R Logic Match Comparator TRISC<2> Output Enable CCP1CON<3:0> T3CCP2 0 1 Mode Select TMR1H TMR1L TMR3H TMR3L DS39609C-page 152  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 RCON IPEN — — RI TO PD POR BOR 0--1 11qq 0--q qquu PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 PIR2 — CMIE — EEIE BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000 PIE2 — CMIF — EEIF BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 ---1 1111 PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu TMR3H Timer3 Register High Byte xxxx xxxx uuuu uuuu TMR3L Timer3 Register Low Byte xxxx xxxx uuuu uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu CCPRxL(1) Capture/Compare/PWM Register x (LSB) xxxx xxxx uuuu uuuu CCPRxH(1) Capture/Compare/PWM Register x (MSB) xxxx xxxx uuuu uuuu CCPxCON(1) — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Compare, Timer1 or Timer3. Note 1: Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module (CCP1 through CCP5). Bit assignments and Reset values for all registers of the same generic name are identical.  2003-2013 Microchip Technology Inc. DS39609C-page 153

PIC18F6520/8520/6620/8620/6720/8720 16.4 PWM Mode 16.4.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCP1 pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the the CCP1 pin is multiplexed with the PORTC data latch, following formula: the TRISC<2> bit must be cleared to make the CCP1 pin an output. EQUATION 16-1: Note: Clearing the CCP1CON register will force PWM Period = (PR2) + 1] • 4 • TOSC • the CCP1 PWM output latch to the default (TMR2 Prescale Value) low level. This is not the PORTC I/O data latch. PWM frequency is defined as 1/[PWM period]. Figure16-4 shows a simplified block diagram of the When TMR2 is equal to PR2, the following three events CCP module in PWM mode. occur on the next increment cycle: For a step-by-step procedure on how to set up the CCP • TMR2 is cleared module for PWM operation, see Section16.4.3 • The CCP1 pin is set (exception: if PWM duty “Setup for PWM Operation”. cycle=0%, the CCP1 pin will not be set) • The PWM duty cycle is latched from CCPR1L into FIGURE 16-4: SIMPLIFIED PWM BLOCK CCPR1H DIAGRAM Note: The Timer2 and Timer4 postscalers (see CCP1CON<5:4> Section13.0 “Timer2 Module”) are not Duty Cycle Registers used in the determination of the PWM CCPR1L frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. CCPR1H (Slave) 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the Comparator R Q CCPR1L register and to the CCP1CON<5:4> bits. Up RC2/CCP1 to 10-bit resolution is available. The CCPR1L contains TMR2 (Note 1) the eight MSbs and the CCP1CON<5:4> contains the S two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is Comparator TRISC<2> used to calculate the PWM duty cycle in time: Clear Timer, CCP1 pin and latch D.C. PR2 EQUATION 16-2: Note 1: 8-bit timer is concatenated with 2-bit internal Q PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • clock or 2bits of the prescaler to create 10-bit TOSC • (TMR2 Prescale Value) time base. CCPR1L and CCP1CON<5:4> can be written to at any A PWM output (Figure16-5) has a time base (period) time, but the duty cycle value is not latched into and a time that the output stays high (duty cycle). CCPR1H until after a match between PR2 and TMR2 Thefrequency of the PWM is the inverse of the period occurs (i.e., the period is complete). In PWM mode, (1/period). CCPR1H is a read-only register. FIGURE 16-5: PWM OUTPUT The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This Period doublebuffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, con- catenated with an internal 2-bit Q clock or 2 bits of the Duty Cycle TMR2 prescaler, the CCP1 pin is cleared. TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 DS39609C-page 154  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 The maximum PWM resolution (bits) for a given PWM 16.4.3 SETUP FOR PWM OPERATION frequency is given by the equation: The following steps should be taken when configuring the CCP module for PWM operation: EQUATION 16-3: 1. Set the PWM period by writing to the PR2 log--F---O----S---C--- register. FPWM PWM Resolution (max) = -----------------------------bits 2. Set the PWM duty cycle by writing to the log2 CCPR1L register and CCP1CON<5:4> bits. 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. Note: If the PWM duty cycle value is longer than 4. Set the TMR2 prescale value and enable Timer2 the PWM period, the CCP1 pin will not be by writing to T2CON. cleared. 5. Configure the CCP1 module for PWM operation. TABLE 16-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 14  10 12  10 10 8 7 6.58 TABLE 16-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 RCON IPEN — — RI TO PD POR BOR 0--1 11qq 0--q qquu PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 PIR2 — CMIE — EEIE BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000 PIE2 — CMIF — EEIF BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 ---1 1111 PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 TMR2 Timer2 Module Register 0000 0000 0000 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu TMR4 Timer4 Register 0000 0000 uuuu uuuu PR4 Timer4 Period Register 1111 1111 uuuu uuuu T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 uuuu uuuu CCPRxL(1) Capture/Compare/PWM Register x (LSB) xxxx xxxx uuuu uuuu CCPRxH(1) Capture/Compare/PWM Register x (MSB) xxxx xxxx uuuu uuuu CCPxCON(1) — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2, or Timer4. Note 1: Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module (CCP1 through CCP5). Bit assignments and Reset values for all registers of the same generic name are identical.  2003-2013 Microchip Technology Inc. DS39609C-page 155

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 156  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.0 MASTER SYNCHRONOUS 17.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, 17.1 Master SSP (MSSP) Module typically three pins are used: Overview • Serial Data Out (SDO) – RC5/SDO • Serial Data In (SDI) – RC4/SDI/SDA The Master Synchronous Serial Port (MSSP) module is • Serial Clock (SCK) – RC3/SCK/SCL a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral Additionally, a fourth pin may be used when in a Slave devices may be serial EEPROMs, shift registers, dis- mode of operation: play drivers, A/D converters, etc. The MSSP module • Slave Select (SS) – RF7/SS can operate in one of two modes: Figure17-1 shows the block diagram of the MSSP • Serial Peripheral Interface (SPI) module when operating in SPI mode. • Inter-Integrated Circuit (I2C) - Full Master mode FIGURE 17-1: MSSP BLOCK DIAGRAM - Slave mode (with general address call) (SPIMODE) The I2C interface supports the following modes in Internal hardware: Data Bus • Master mode Read Write • Multi-Master mode SSPBUF reg • Slave mode 17.2 Control Registers RC4/SDI/SDA The MSSP module has three associated registers. SSPSR reg These include a status register (SSPSTAT) and two RC5/SDO bit0 Shift Clock control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly, depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual RF7/SS SS Control sections. Enable Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE ( ) RC3/SCK/ 4 TMR2 Output SCL 2 2 Edge Select Prescaler TOSC 4, 16, 64 Data to TX/RX in SSPSR TRIS bit  2003-2013 Microchip Technology Inc. DS39609C-page 157

PIC18F6520/8520/6620/8620/6720/8720 17.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes The MSSP module has four registers for SPI mode are written to or read from. operation. These are: In receive operations, SSPSR and SSPBUF together • MSSP Control Register 1 (SSPCON1) create a double-buffered receiver. When SSPSR • MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF • Serial Receive/Transmit Buffer (SSPBUF) and the SSPIF interrupt is set. • MSSP Shift Register (SSPSR) – Not directly During transmission, the SSPBUF is not double- accessible buffered. A write to SSPBUF will write to both SSPBUF SSPCON1 and SSPSTAT are the control and status and SSPSR. registers in SPI mode operation. The SSPCON1 regis- ter is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>). bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write bit information Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 158  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow Note: In Master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by writing to the SSPBUF register. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved, or implemented in I2C mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 159

PIC18F6520/8520/6620/8620/6720/8720 17.3.2 OPERATION reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data When initializing the SPI, several options need to be will be ignored and the Write Collision detect bit, WCOL specified. This is done by programming the appropriate (SSPCON1<7>), will be set. User software must clear control bits (SSPCON1<5:0> and SSPSTAT<7:6>). the WCOL bit so that it can be determined if the follow- These control bits allow the following to be specified: ing write(s) to the SSPBUF register completed • Master mode (SCK is the clock output) successfully. • Slave mode (SCK is the clock input) When the application software is expecting to receive • Clock Polarity (Idle state of SCK) valid data, the SSPBUF should be read before the next • Data input sample phase (middle or end of data byte of data to transfer is written to the SSPBUF. Buffer output time) Full bit, BF (SSPSTAT<0>), indicates when SSPBUF • Clock edge (output data on rising/falling edge of has been loaded with the received data (transmission SCK) is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a • Clock Rate (Master mode only) transmitter. Generally, the MSSP interrupt is used to • Slave Select mode (Slave mode only) determine when the transmission/reception has com- The MSSP consists of a Transmit/Receive Shift Regis- pleted. The SSPBUF must be read and/or written. If the ter (SSPSR) and a Buffer register (SSPBUF). The interrupt method is not going to be used, then software SSPSR shifts the data in and out of the device, MSb polling can be done to ensure that a write collision does first. The SSPBUF holds the data that was written to the not occur. Example17-1 shows the loading of the SSPSR until the received data is ready. Once the 8 bits SSPBUF (SSPSR) for data transmission. of data have been received, that byte is moved to the The SSPSR is not directly readable or writable and can SSPBUF register. Then, the Buffer Full detect bit, BF only be accessed by addressing the SSPBUF register. (SSPSTAT<0>) and the interrupt flag bit, SSPIF, are Additionally, the MSSP Status register (SSPSTAT) set. This double-buffering of the received data indicates the various status conditions. (SSPBUF) allows the next byte to start reception before EQUATION 17-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to transmit DS39609C-page 160  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.3.3 ENABLING SPI I/O 17.3.4 TYPICAL CONNECTION To enable the serial port, SSP Enable bit, SSPEN Figure17-2 shows a typical connection between two (SSPCON1<5>), must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1) SPI mode, clear the SSPEN bit, reinitialize the initiates the data transfer by sending the SCK signal. SSPCON registers and then set the SSPEN bit. This Data is shifted out of both shift registers on their pro- configures the SDI, SDO, SCK and SS pins as serial grammed clock edge and latched on the opposite edge port pins. For the pins to behave as the serial port func- of the clock. Both processors should be programmed to tion, some must have their data direction bits (in the the same Clock Polarity (CKP), then both controllers TRIS register) appropriately programmed as follows: would send and receive data at the same time. Whether the data is meaningful (or dummy data) • SDI is automatically controlled by the SPI module depends on the application software. This leads to • SDO must have TRISC<5> bit cleared three scenarios for data transmission: • SCK (Master mode) must have TRISC<3> bit • Master sends data–Slave sends dummy data cleared • Master sends data–Slave sends data • SCK (Slave mode) must have TRISC<3> bit set • Master sends dummy data–Slave sends data • SS must have TRISF<7> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 17-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2  2003-2013 Microchip Technology Inc. DS39609C-page 161

PIC18F6520/8520/6620/8620/6720/8720 17.3.5 MASTER MODE Figure17-3, Figure17-5 and Figure17-6, where the MSB is transmitted first. In Master mode, the SPI clock The master can initiate the data transfer at any time rate (bit rate) is user-programmable to be one of the because it controls the SCK. The master determines following: when the slave (Processor 2, Figure17-2) is to broadcast data by the software protocol. • FOSC/4 (or TCY) In Master mode, the data is transmitted/received as • FOSC/16 (or 4 • TCY) soon as the SSPBUF register is written to. If the SPI is • FOSC/64 (or 16 • TCY) only going to receive, the SDO output could be dis- • Timer2 output/2 abled (programmed as an input). The SSPSR register This allows a maximum data rate (at 40MHz) of will continue to shift in the signal present on the SDI pin 10.00Mbps. at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as Figure17-3 shows the waveforms for Master mode. if a normal received byte (interrupts and status bits When the CKE bit is set, the SDO data is valid before appropriately set). This could be useful in receiver there is a clock edge on SCK. The change of the input applications as a “Line Activity Monitor” mode. sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received The clock polarity is selected by appropriately program- data is shown. ming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication, as shown in FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 cycle SSPSR to after Q2 SSPBUF DS39609C-page 162  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.3.6 SLAVE MODE longer driven, even if in the middle of a transmitted byteand becomes a floating output. External pull-up/ In Slave mode, the data is transmitted and received as pull-down resistors may be desirable, depending on the the external clock pulses appear on SCK. When the application. last bit is latched, the SSPIF interrupt flag bit is set. Note 1: When the SPI is in Slave mode with SS pin While in Slave mode, the external clock is supplied by control enabled (SSPCON<3:0> = 0100), the external clock source on the SCK pin. This external the SPI module will reset if the SS pin is set clock must meet the minimum high and low times as specified in the electrical specifications. to VDD. 2: If the SPI is used in Slave mode with CKE While in Sleep mode, the slave can transmit/receive set, then the SS pin control must be data. When a byte is received, the device will wake-up enabled. from Sleep. When the SPI module resets, the bit counter is forced 17.3.7 SLAVE SELECT to ‘0’. This can be done by either forcing the SS pin to SYNCHRONIZATION a high level or clearing the SSPEN bit. The SS pin allows a Synchronous Slave mode. The To emulate two-wire communication, the SDO pin can SPI must be in Slave mode with SS pin control enabled be connected to the SDI pin. When the SPI needs to (SSPCON1<3:0> = 04h). The pin must not be driven operate as a receiver, the SDO pin can be configured low for the SS pin to function as an input. The Data as an input. This disables transmissions from the SDO. Latch must be high. When the SS pin is low, transmis- The SDI can always be left as an input (SDI function), sion and reception are enabled and the SDO pin is since it cannot create a bus conflict. driven. When the SS pin goes high, the SDO pin is no FIGURE 17-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle SSPSR to after Q2 SSPBUF  2003-2013 Microchip Technology Inc. DS39609C-page 163

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle SSPSR to after Q2 SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle after Q2 SSPSR to SSPBUF DS39609C-page 164  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.3.8 SLEEP OPERATION 17.3.10 BUS MODE COMPATIBILITY In Master mode, all module clocks are halted and the Table17-1 shows the compatibility between the transmission/reception will remain in that state until the standard SPI modes and the states of the CKP and device wakes from Sleep. After the device returns to CKE control bits. normal mode, the module will continue to transmit/ receive data. TABLE 17-1: SPI BUS MODES In Slave mode, the SPI Transmit/Receive Shift register Control Bits State Standard SPI Mode operates asynchronously to the device. This allows the Terminology device to be placed in Sleep mode and data to be CKP CKE shifted into the SPI Transmit/Receive Shift register. 0, 0 0 1 When all 8 bits have been received, the MSSP interrupt 0, 1 0 0 flag bit will be set and if enabled, will wake the device from Sleep. 1, 0 1 1 1, 1 1 0 17.3.9 EFFECTS OF A RESET There is also an SMP bit, which controls when the data A Reset disables the MSSP module and terminates the is sampled. current transfer. TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 uuuu uuuu SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.  2003-2013 Microchip Technology Inc. DS39609C-page 165

PIC18F6520/8520/6620/8620/6720/8720 17.4 I2C Mode 17.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call sup- These are: port) and provides interrupts on Start and Stop bits in • MSSP Control Register 1 (SSPCON1) hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPCON2) function). The MSSP module implements the standard • MSSP Status Register (SSPSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer (SSPBUF) addressing. • MSSP Shift Register (SSPSR) – Not directly Two pins are used for data transfer: accessible • Serial clock (SCL) – RC3/SCK/SCL • MSSP Address Register (SSPADD) • Serial data (SDA) – RC4/SDI/SDA SSPCON, SSPCON2 and SSPSTAT are the control The user must configure these pins as inputs or outputs and status registers in I2C mode operation. The through the TRISC<4:3> bits. SSPCON and SSPCON2 registers are readable and writable. The lower six bits of the SSPSTAT are FIGURE 17-7: MSSP BLOCK DIAGRAM read-only. The upper two bits of the SSPSTAT are (I2C MODE) read/write. SSPSR is the shift register used for shifting data in or Internal out. SSPBUF is the buffer register to which data bytes Data Bus are written to or read from. Read Write SSPADD register holds the slave device address when the SSP is configured in I2C Slave mode. When RC3/SCK/SCL SSPBUF reg the SSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Shift Generator reload value. Clock In receive operations, SSPSR and SSPBUF together, SSPSR reg create a double-buffered receiver. When SSPSR RC4/ MSb LSb receives a complete byte, it is transferred to SSPBUF SDI/ SDA and the SSPIF interrupt is set. Match Detect Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPADD reg Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT reg) DS39609C-page 166  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high-speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 3 S: Start bit 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 2 R/W: Read/Write bit Information (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in active mode. bit 1 UA: Update Address bit (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPBUF is full 0 = SSPBUF is empty In Receive mode: 1 = SSPBUF is full (does not include the ACK and Stop bits) 0 = SSPBUF is empty (does not include the ACK and Stop bits) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 167

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as input or output. bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 168  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enabled/Stretch Enabled bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled) 0 = Clock stretching is disabled Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 169

PIC18F6520/8520/6620/8620/6720/8720 17.4.2 OPERATION 17.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPCON<5>). a Start condition to occur. Following the Start condition, The SSPCON1 register allows control of the I2C oper- the 8 bits are shifted into the SSPSR register. All incom- ing bits are sampled with the rising edge of the clock ation. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The • I2C Master mode, clock = (FOSC/4) x (SSPADD + 1) address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address), with Start and 1. The SSPSR register value is loaded into the Stop bit interrupts enabled SSPBUF register. • I2C Slave mode (10-bit address), with Start and 2. The Buffer Full bit BF is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is 4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is Idle set (interrupt is generated, if enabled) on the Selection of any I2C mode, with the SSPEN bit set, falling edge of the ninth SCL pulse. forces the SCL and SDA pins to be open-drain, pro- In 10-bit Address mode, two address bytes need to be vided these pins are programmed to inputs by setting received by the slave. The five Most Significant bits the appropriate TRISC bits. To ensure proper operation (MSbs) of the first address byte specify if this is a 10-bit of the module, pull-up resistors must be provided address. Bit R/W (SSPSTAT<2>) must specify a write externally to the SCL and SDA pins. so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal 17.4.3 SLAVE MODE ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two In Slave mode, the SCL and SDA pins must be config- MSbs of the address. The sequence of events for ured as inputs (TRISC<4:3> set). The MSSP module 10-bit address is as follows, with steps 7 through 9 for will override the input state with the output data when the slave-transmitter: required (slave-transmitter). 1. Receive first (high) byte of address (bits SSPIF, The I2C Slave mode hardware will always generate an BF and bit UA (SSPSTAT<1>) are set). interrupt on an address match. Through the mode 2. Update the SSPADD register with second (low) select bits, the user can also choose to interrupt on byte of address (clears bit UA and releases the Start and Stop bits SCL line). When an address is matched or the data transfer after 3. Read the SSPBUF register (clears bit BF) and an address match is received, the hardware automati- clear flag bit SSPIF. cally will generate the Acknowledge (ACK) pulse and 4. Receive second (low) byte of address (bits load the SSPBUF register with the received value SSPIF, BF and UA are set). currently in the SSPSR register. 5. Update the SSPADD register with the first (high) Any combination of the following conditions will cause byte of address. If match releases SCL line, this the MSSP module not to give this ACK pulse: will clear bit UA. • The Buffer Full bit BF (SSPSTAT<0>) was set 6. Read the SSPBUF register (clears bit BF) and before the transfer was received. clear flag bit SSPIF. • The overflow bit SSPOV (SSPCON<6>) was set 7. Receive Repeated Start condition. before the transfer was received. 8. Receive first (high) byte of address (bits SSPIF and BF are set). In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The 9. Read the SSPBUF register (clears bit BF) and BF bit is cleared by reading the SSPBUF register, while clear flag bit SSPIF. bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter #100 and parameter #101. DS39609C-page 170  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.4.3.2 Reception 17.4.3.3 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPSTAT register is set. The received address is the SSPBUF register and the SDA line is held low loaded into the SSPBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin RC3/SCK/SCL is held low, regardless of SEN (see Section17.4.4 “Clock When the address byte overflow condition exists, then Stretching”, for more detail). By stretching the clock, the no Acknowledge (ACK) pulse is given. An overflow the master will be unable to assert another clock pulse condition is defined as either bit BF (SSPSTAT<0>) is until the slave is done preparing the transmit data. The set, or bit SSPOV (SSPCON1<6>) is set. transmit data must be loaded into the SSPBUF register, An MSSP interrupt is generated for each data transfer which also loads the SSPSR register. Then pin RC3/ byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- SCK/SCL should be enabled by setting bit CKP ware. The SSPSTAT register is used to determine the (SSPCON1<4>). The eight data bits are shifted out on status of the byte. the falling edge of the SCL input. This ensures that the If SEN is enabled (SSPCON1<0>=1), RC3/SCK/SCL SDA signal is valid during the SCL high time will be held low (clock stretch) following each data (Figure17-9). transfer. The clock must be released by setting bit The ACK pulse from the master-receiver is latched on CKP(SSPCON<4>). See Section17.4.4 “Clock the rising edge of the ninth SCL input pulse. If the SDA Stretching” for more detail. line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT regis- ter) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse.  2003-2013 Microchip Technology Inc. DS39609C-page 171

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-8: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e Receiving D6D5D4 234 Cleared in softwarSSPBUF is read 7 D 1 K 9 0= AC W 8 R/ A1 7 2 0) A 6 = ddress A3 5 n SEN A e Receiving A5A4 34 0set to ‘’ wh e ot r A6 2 s n e o A7 1 0>) ON<6>) (CKP d SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP DS39609C-page 172  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-9: I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S ACK 9 PIF I S D0 8 m S o ata D1 7 Fr D Transmitting D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software KP is set in software C D7 1 R ACK 9 PIF IS S D0 8 m S o 1 Fr D 7 a g Dat D2 6 ware Transmittin D6D5D4D3 2345 Cleared in software SSPBUF is written in soft CKP is set in software D7 1 PIF S SCL held lowwhile CPUresponds to S K C A 9 1 = W 8 R/ 1 A 7 2 ess A 6 Addr A3 5 g eivin A4 4 ec R A5 3 A6A7 12 Data in sampled >) 0>) 3 < < T 1 A R T DA CL S SPIF (PI F (SSPS KP S S S B C  2003-2013 Microchip Technology Inc. DS39609C-page 173

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-10: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 untilD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPADD is updated with highbyte of address d low SPAD D7 1 Clock is helupdate of Staken place ACK0 89 Clock is held low untilupdate of SSPADD has taken place Receive First Byte of AddressReceive Second Byte of Address0R/W = ACK11110A9A8A7A6A5A4A3A2A1A 1234567891234567 Cleared in softwareCleared in software AT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag PCON<6>) AT<1>) UA is set indicating thatCleared by hardwarethe SSPADD needs to bewhen SSPADD is updatedupdatedwith low byte of address UA is set indicating thatSSPADD needs to beupdated 00(CKP does not reset to ‘’ when SEN = ) SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C DS39609C-page 174  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-11: I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCL low w Clock is held low untilupdate of SSPADD has Clock is held low untiltaken place1CKP is set to ‘’ Receive First Byte of AddressTransmitting Data Byte1R/W = ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPBUFWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPADD has taken place 0W = Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address UA is set indicating thatSSPADD needs to beupdated R/e First Byte of Address 110A9A8 345678 SSPBUF is written withcontents of SSPSR UA is set indicating thatthe SSPADD needs to beupdated Receiv 11 12 AT<0>) AT<1>) ON<4>) SDA SCLS SSPIF (PIR1<3>) BF (SSPST UA (SSPST CKP (SSPC  2003-2013 Microchip Technology Inc. DS39609C-page 175

PIC18F6520/8520/6620/8620/6720/8720 17.4.4 CLOCK STRETCHING 17.4.4.3 Clock Stretching for 7-bit Slave Transmit Mode Both 7- and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. 7-bit Slave Transmit mode implements clock stretching The SEN bit (SSPCON2<0>) allows clock stretching to by clearing the CKP bit after the falling edge of the ninth clock, if the BF bit is clear. This occurs, be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data regardless of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line 17.4.4.1 Clock Stretching for 7-bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPBUF before the master device can In 7-bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure17-9). ninth clock at the end of the ACK sequence, if the BF Note1: If the user loads the contents of SSPBUF, bit is set, the CKP bit in the SSPCON1 register is setting the BF bit before the falling edge of automatically cleared, forcing the SCL output to be the ninth clock, the CKP bit will not be held low. The CKP being cleared to ‘0’ will assert the cleared and clock stretching will not occur. SCL line low. The CKP bit must be set in the user’s 2: The CKP bit can be set in software, ISR before reception is allowed to continue. By holding regardless of the state of the BF bit. the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the 17.4.4.4 Clock Stretching for 10-bit Slave master device can initiate another receive sequence. Transmit Mode This will prevent buffer overruns from occurring (see Figure17-13). In 10-bit Slave Transmit mode, clock stretching is con- trolled during the first two address sequences by the Note1: If the user reads the contents of the state of the UA bit, just as it is in 10-bit Slave Receive SSPBUF before the falling edge of the mode. The first two addresses are followed by a third ninth clock, thus clearing the BF bit, the address sequence, which contains the high-order bits CKP bit will not be cleared and clock of the 10-bit address and the R/W bit set to ‘1’. After stretching will not occur. the third address sequence is performed, the UA bit is 2: The CKP bit can be set in software, not set, the module is now configured in Transmit regardless of the state of the BF bit. The mode and clock stretching is controlled as in 7-bit user should be careful to clear the BF bit Slave Transmit mode (see Figure17-11). in the ISR before the next receive sequence, in order to prevent an overflow condition. 17.4.4.2 Clock Stretching for 10-bit Slave Receive Mode (SEN = 1) In 10-bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence, as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39609C-page 176  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.4.4.5 Clock Synchronization and already asserted the SCL line. The SCL output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This When the CKP bit is cleared, the SCL output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, clearing the CKP bit will not assert the minimum high time requirement for SCL (see SCL output low until the SCL output is already sam- Figure17-12). pled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX-1 SCL Master device CKP asserts clock Master device deasserts clock WR SSPCON  2003-2013 Microchip Technology Inc. DS39609C-page 177

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-13: I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lo1because ACK = ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 e Clock is held low until1CKP is set to ‘’ ACK D0D7D6 8912 CKPwritten1to ‘’ insoftwarBF is set after falling edge of the 9th clock,0CKP is reset to ‘’ andclock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be reset0to ‘’ and no clockstretching will occur S K 9 0 C = A W 8 R/ A1 7 2 A 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 A6 2 >) A7 1 <6 0>) ON SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP DS39609C-page 178  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-14: I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) w ent. Clock is not held lo1because ACK = ACK D0 89P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not s 1 D 7 e ck is held low until1P is set to ‘’ Receive Data Byte ACKD7D6D5D4D3D2 9123456 Cleared in softwar 1CKP written to ‘’in software Clock is held low untilupdate of SSPADD has Clotaken placeCK Receive Data Byte D7D6D5D4D3D1D0D2 12345786 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with highbyte of address after falling edgeof ninth clock Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set K C 9 A Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of Address0W = A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address after falling edgeof ninth clock UA is set indicating thatSSPADD needs to beupdated Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set Receive First Byte of AddressR/ 1110A9A8 2345678 Cleared in software >) SSPBUF is written withcontents of SSPSR N<6>) >) UA is set indicating thatthe SSPADD needs to beupdated 1 1 AT<0 PCO AT<1 SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C  2003-2013 Microchip Technology Inc. DS39609C-page 179

PIC18F6520/8520/6620/8620/6720/8720 17.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the The addressing procedure for the I2C bus is such that SSPIF interrupt flag bit is set. the first byte after the Start condition usually deter- mines which device will be the slave addressed by the When the interrupt is serviced, the source for the inter- master. The exception is the general call address, rupt can be checked by reading the contents of the which can address all devices. When this address is SSPBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device specific or a general call address. Acknowledge. In 10-bit mode, the SSPADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is configured in 10-bit Address mode, then the second The general call address is recognized when the Gen- half of the address is not necessary, the UA bit will not eral Call Enable bit (GCEN) is enabled (SSPCON2<7> be set and the slave will begin receiving data after the set). Following a Start bit detect, 8 bits are shifted into Acknowledge (Figure17-15). the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 17-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’ DS39609C-page 180  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPCON1 and by setting the of events. For instance, the user is not SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and are manipulated by the MSSP hardware. immediately write the SSPBUF register to initiate transmission before the Start condi- Master mode of operation is supported by interrupt tion is complete. In this case, the SSPBUF generation on the detection of the Start and Stop will not be written to and the WCOL bit will conditions. The Stop (P) and Start (S) bits are cleared be set, indicating that a write to the from a Reset, or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is SSPBUF did not occur. set or the bus is Idle, with both the S and P bits clear. In Firmware Controlled Master mode, user code The following events will cause SSP Interrupt Flag bit, conducts all I2C bus operations based on Start and SSPIF, to be set (SSP interrupt if enabled): Stop bit conditions. • Start Condition Once Master mode is enabled, the user has six • Stop Condition options. • Data Transfer Byte Transmitted/received 1. Assert a Start condition on SDA and SCL. • Acknowledge Transmit 2. Assert a Repeated Start condition on SDA and • Repeated Start SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. 2 FIGURE 17-16: MSSP BLOCK DIAGRAM (I C MASTER MODE) Internal SSPM3:SSPM0 Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock ct e SSPSR Detce) MSb LSb L ur e Oo abl WCk s SCL Receive En StAarcGtk bneiont,we Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT) Clock Arbitration Set SSPIF, BCLIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV  2003-2013 Microchip Technology Inc. DS39609C-page 181

PIC18F6520/8520/6620/8620/6720/8720 17.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start enable bit, SEN (SSPCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDA, while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPCON2 register (SSPCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. bit. In Master Receive mode, the first byte transmitted con- 7. The user loads the SSPBUF with eight bits of tains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDA pin until all 8 bits are logic ‘1’. Thus, the first byte transmitted is a 7-bit slave transmitted. address followed by a ‘1’ to indicate receive bit. Serial 9. The MSSP module shifts in the ACK bit from the data is received via SDA, while SCL outputs the serial slave device and writes its value into the clock. Serial data is received 8 bits at a time. After each SSPCON2 register (SSPCON2<6>). byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and 10. The MSSP module generates an interrupt at the end of transmission. end of the ninth clock cycle by setting the SSPIF bit. The Baud Rate Generator used for the SPI mode 11. The user generates a Stop condition by setting operation is used to set the SCL clock frequency for either 100kHz, 400kHz or 1MHz I2C operation. See the Stop enable bit PEN (SSPCON2<2>). Section17.4.7 “Baud Rate Generator”, for more 12. Interrupt is generated once the Stop condition is information. complete. DS39609C-page 182  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.4.7 BAUD RATE GENERATOR Once the given operation is complete (i.e., transmis- In I2C Master mode, the Baud Rate Generator (BRG) sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin reload value is placed in the lower 7 bits of the will remain in its last state. SSPADD register (Figure17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically Table 15-3 demonstrates clock rates based on begin counting. The BRG counts down to ‘0’ and stops instruction cycles and the BRG value loaded into until another reload has taken place. The BRG count is SSPADD. decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. FIGURE 17-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 Reload Reload SCL Control CLKO BRG Down Counter FOSC/4 TABLE 17-3: I2C CLOCK RATE W/BRG FSCL FCY FCY*2 BRG VALUE (2 rollovers of BRG) 10 MHz 20 MHz 19h 400 kHz(1) 10 MHz 20 MHz 20h 312.5 kHz 10 MHz 20 MHz 3Fh 100 kHz 4 MHz 8 MHz 0Ah 400 kHz(1) 4 MHz 8 MHz 0Dh 308 kHz 4 MHz 8 MHz 28h 100 kHz 1 MHz 2 MHz 03h 333 kHz(1) 1 MHz 2 MHz 0Ah 100 kHz 1 MHz 2 MHz 00h 1 MHz(1) Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application.  2003-2013 Microchip Technology Inc. DS39609C-page 183

PIC18F6520/8520/6620/8620/6720/8720 17.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCL high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count, in the deasserts the SCL pin (SCL allowed to float high). event that the clock is held low by an external device When the SCL pin is allowed to float high, the Baud (Figure 15-18). Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 17-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload DS39609C-page 184  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.4.8 I2C MASTER MODE START 17.4.8.1 WCOL Status Flag CONDITION TIMING If the user writes the SSPBUF when a Start sequence To initiate a Start condition, the user sets the Start Con- is in progress, the WCOL is set and the contents of the dition Enable bit, SEN (SSPCON2<0>). If the SDA and buffer are unchanged (the write doesn’t occur). SCL pins are sampled high, the Baud Rate Generator Note: Because queueing of events is not is reloaded with the contents of SSPADD<6:0> and allowed, writing to the lower 5 bits of starts its count. If SCL and SDA are both sampled high SSPCON2 is disabled until the Start when the Baud Rate Generator times out (TBRG), the condition is complete. SDA pin is driven low. The action of the SDA being driven low, while SCL is high, is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the con- tents of SSPADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note: If at the beginning of the Start condition, the SDA and SCL pins are already sam- pled low, or if during the Start condition the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. FIGURE 17-19: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st bit 2nd bit SDA TBRG SCL TBRG S  2003-2013 Microchip Technology Inc. DS39609C-page 185

PIC18F6520/8520/6620/8620/6720/8720 17.4.9 I2C MASTER MODE REPEATED Immediately following the setting of the SSPIF bit, the START CONDITION TIMING user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. A Repeated Start condition occurs when the RSEN bit After the first eight bits are transmitted and an ACK is (SSPCON2<1>) is programmed high and the I2C logic received, the user may then transmit an additional eight module is in the Idle state. When the RSEN bit is set, bits of address (10-bit mode) or eight bits of data (7-bit the SCL pin is asserted low. When the SCL pin is sam- mode). pled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The 17.4.9.1 WCOL Status Flag SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Genera- If the user writes the SSPBUF when a Repeated Start tor times out, if SDA is sampled high, the SCL pin will sequence is in progress, the WCOL is set and the be deasserted (brought high). When SCL is sampled contents of the buffer are unchanged (the write does high, the Baud Rate Generator is reloaded with the not occur). contents of SSPADD<6:0> and begins counting. SDA Note: Because queueing of events is not and SCL must be sampled high for one TBRG. This allowed, writing of the lower 5 bits of action is then followed by assertion of the SDA pin SSPCON2 is disabled until the Repeated (SDA = 0) for one TBRG, while SCL is high. Following Start condition is complete. this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. Note1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. FIGURE 17-20: REPEAT START CONDITION WAVEFORM S bit set by hardware (SSPSTAT<3>) Write to SSPCON2 SDA = 1, occurs here. At completion of Start bit, SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change). and sets SSPIF TBRG TBRG TBRG 1st bit SDA Falling edge of ninth clock Write to SSPBUF occurs here End of Xmit TBRG SCL TBRG RSEN bit set Sr = Repeated Start DS39609C-page 186  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.4.10 I2C MASTER MODE 17.4.10.3 ACKSTAT Status Flag TRANSMISSION In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is Transmission of a data byte, a 7-bit address, or the cleared when the slave has sent an Acknowledge other half of a 10-bit address is accomplished by simply (ACK=0) and is set when the slave does not Acknowl- writing a value to the SSPBUF register. This action will edge (ACK = 1). A slave sends an Acknowledge when set the Buffer Full flag bit, BF and allow the Baud Rate it has recognized its address (including a general call), Generator to begin counting and start the next trans- or when the slave has properly received its data. mission. Each bit of address/data will be shifted out 17.4.11 I2C MASTER MODE RECEPTION onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter Master mode reception is enabled by programming the #106). SCL is held low for one Baud Rate Generator Receive Enable bit, RCEN (SSPCON2<3>). rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification Note: The MSSP module must be in an Idle state parameter #107). When the SCL pin is released high, it before the RCEN bit is set, or the RCEN is held that way for TBRG. The data on the SDA pin bit will be disregarded. must remain stable for that duration and some hold The Baud Rate Generator begins counting and on each time, after the next falling edge of SCL. After the eighth rollover, the state of the SCL pin changes (high-to-low/ bit is shifted out (the falling edge of the eighth clock), low-to-high) and data is shifted into the SSPSR. After the BF flag is cleared and the master releases SDA. the falling edge of the eighth clock, the receive enable This allows the slave device being addressed to flag is automatically cleared, the contents of the respond with an ACK bit during the ninth bit time if an SSPSR are loaded into the SSPBUF, the BF flag bit is address match occurred, or if data was received prop- set, the SSPIF flag bit is set and the Baud Rate Gener- erly. The status of ACK is written into the ACKDT bit on ator is suspended from counting, holding SCL low. The the falling edge of the ninth clock. If the master receives MSSP is now in Idle state, awaiting the next command. an Acknowledge, the Acknowledge Status bit, When the buffer is read by the CPU, the BF flag bit is ACKSTAT, is cleared. If not, the bit is set. After the ninth automatically cleared. The user can then send an clock, the SSPIF bit is set and the master clock (Baud Acknowledge bit at the end of reception by setting the Rate Generator) is suspended until the next data byte Acknowledge Sequence Enable bit, ACKEN is loaded into the SSPBUF, leaving SCL low and SDA (SSPCON2<4>). unchanged (Figure17-21). 17.4.11.1 BF Status Flag After the write to the SSPBUF, each address bit will be shifted out on the falling edge of SCL, until all seven In receive operation, the BF bit is set when an address address bits and the R/W bit are completed. On the fall- or data byte is loaded into SSPBUF from SSPSR. It is ing edge of the eighth clock, the master will deassert cleared when the SSPBUF register is read. the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the 17.4.11.2 SSPOV Status Flag master will sample the SDA pin to see if the address In receive operation, the SSPOV bit is set when 8 bits was recognized by a slave. The status of the ACK bit is are received into the SSPSR and the BF flag bit is loaded into the ACKSTAT status bit (SSPCON2<6>). already set from a previous reception. Following the falling edge of the ninth clock transmis- sion of the address, the SSPIF is set, the BF flag is 17.4.11.3 WCOL Status Flag cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, holding SCL If the user writes the SSPBUF when a receive is low and allowing SDA to float. already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer 17.4.10.1 BF Status Flag are unchanged (the write doesn’t occur). In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 17.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software.  2003-2013 Microchip Technology Inc. DS39609C-page 187

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-21: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A > slave, clear ACKSTAT bit SSPCON2<6 Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1D0 2345678 Cleared in software service routinefrom SSP interrupt SSPBUF is written in software From D7 1 w SPIF o S 0= SCL held lwhile CPUsponds to CK re 0W = A W, 9 ware R/ A1 ss and R/ 78 d by hard ave A2 ddre 6 eare 1PCON2<0> SEN = ,dition begins 0SEN = Transmit Address to Sl A7A6A5A4A3 SSPBUF written with 7-bit astart transmit 12345 Cleared in software SSPBUF written After Start condition, SEN cl Sn Write SStart co S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W DS39609C-page 188  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-22: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start Acknowledge sequence0SDA = ACKDT (SSPCON2<5>) = Set ACKEN, start Acknowledge sequenceACK from Masterer configured as a receiver10SDA = ACKDT = SDA = ACKDT = 1ogramming SSPCON2<3> (RCEN = )1PEN bit = 1RCEN = RCEN clearedRCEN clearedwritten hereStart next receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK Bus masterACK is not sentterminatestransfer678998756512343124PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Mastby pr ACK from Slave 1R/W = A1ACK 798 1Write to SSPCON2<0>(SEN = ),begin Start Condition 0SEN = Write to SSPBUF occurs hereStart XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 631245SCLS SSPIF Cleared in software01SDA = , SCL = while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN  2003-2013 Microchip Technology Inc. DS39609C-page 189

PIC18F6520/8520/6620/8620/6720/8720 17.4.12 ACKNOWLEDGE SEQUENCE 17.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/ (SSPCON2<4>). When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge pulled low and the contents of the Acknowledge data bit of the ninth clock. When the PEN bit is set, the master are presented on the SDA pin. If the user wishes to gen- will assert the SDA line low. When the SDA line is sam- erate an Acknowledge, then the ACKDT bit should be pled low, the Baud Rate Generator is reloaded and cleared. If not, the user should set the ACKDT bit before counts down to ‘0’. When the Baud Rate Generator starting an Acknowledge sequence. The Baud Rate times out, the SCL pin will be brought high and one Generator then counts for one rollover period (TBRG) TBRG (Baud Rate Generator rollover count) later, the and the SCL pin is deasserted (pulled high). When the SDA pin will be deasserted. When the SDA pin is sam- SCL pin is sampled high (clock arbitration), the Baud pled high while SCL is high, the P bit (SSPSTAT<4>) is Rate Generator counts for TBRG. The SCL pin is then set. A TBRG later, the PEN bit is cleared and the SSPIF pulled low. Following this, the ACKEN bit is automatically bit is set (Figure17-24). cleared, the Baud Rate Generator is turned off and the 17.4.13.1 WCOL Status Flag MSSP module then goes into Idle mode (Figure17-23). If the user writes the SSPBUF when a Stop sequence 17.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the occur). contents of the buffer are unchanged (the write doesn’t occur). FIGURE 17-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared Write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in SSPIF set at the end Cleared in software of receive software SSPIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 17-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2 SCL = 1 for TBRG, followed by SDA = 1 for TBRG Set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS39609C-page 190  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.4.14 SLEEP OPERATION 17.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 17.4.15 EFFECT OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0, 17.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure17-25). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit (SSPSTAT<4>) is set, or the SSPBUF can be written to. When the user services the bus is idle with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the SSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be moni- If a Start, Repeated Start, Stop, or Acknowledge condi- tored for arbitration, to see if the signal level is the tion was in progress when the bus collision occurred, expected output level. This check is performed in the condition is aborted, the SDA and SCL lines are hardware, with the result placed in the BCLIF bit. deasserted and the respective control bits in the SSPCON2 register are cleared. When the user ser- The states where arbitration can be lost are: vices the bus collision Interrupt Service Routine and if • Address Transfer the I2C bus is free, the user can resume communication • Data Transfer by asserting a Start condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determi- nation of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE SDA line pulled low Sample SDA. While SCL is high, Data changes by another source data doesn’t match what is driven while SCL = 0 by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF  2003-2013 Microchip Technology Inc. DS39609C-page 191

PIC18F6520/8520/6620/8620/6720/8720 17.4.17.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure17-28). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure17-26). counts down to ‘0’ and during this time, if the SCL pin b) SCL is sampled low before SDA is asserted low is sampled as ‘0’, a bus collision does not occur. At the (Figure17-27). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a factor pins are monitored. during a Start condition is that no two bus masters can assert a Start condition at the If the SDA pin is already low, or the SCL pin is already exact same time. Therefore, one master low, then all of the following occur: will always assert SDA before the other. • the Start condition is aborted, This condition does not cause a bus colli- • the BCLIF flag is set and sion because the two masters must be • the MSSP module is reset to its Idle state allowed to arbitrate the first address fol- (Figure17-26). lowing the Start condition. If the address is The Start condition begins with the SDA and SCL pins the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded from SSPADD<6:0> Start or Stop conditions. and counts down to ‘0’. If the SCL pin is sampled low while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 17-26: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software DS39609C-page 192  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG Time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1 Interrupts cleared Set SSPIF in software  2003-2013 Microchip Technology Inc. DS39609C-page 193

PIC18F6520/8520/6620/8620/6720/8720 17.4.17.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure17-29). If SDA is sampled high, the BRG is reloaded and begins During a Repeated Start condition, a bus collision counting. If SDA goes from high-to-low before the BRG occurs if: times out, no bus collision occurs because no two a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time. from low level to high level. If SCL goes from high-to-low before the BRG times out b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision indicating that another master is attempting to occurs. In this case, another master is attempting to transmit a data ‘1’. transmit a data ‘1’ during the Repeated Start condition, When the user deasserts SDA and the pin is allowed to Figure17-30. float high, the BRG is loaded with SSPADD<6:0> and If, at the end of the BRG time-out, both SCL and SDA counts down to ‘0’. The SCL pin is then deasserted and are still high, the SDA pin is driven low and the BRG is when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 17-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S ‘0’ SSPIF ‘0’ FIGURE 17-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF Set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN ‘0’ S SSPIF DS39609C-page 194  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 17.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<6:0> a) After the SDA pin has been deasserted and and counts down to ‘0’. After the BRG times out, SDA allowed to float high, SDA is sampled low after is sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure17-31). If the SCL pin is low before SDA goes high. sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure17-32). FIGURE 17-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 17-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’  2003-2013 Microchip Technology Inc. DS39609C-page 195

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 196  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 18.0 ADDRESSABLE UNIVERSAL Register18-1 shows the layout of the Transmit Status SYNCHRONOUS and Control registers (TXSTAx) and Register18-2 shows the layout of the Receive Status and Control ASYNCHRONOUS RECEIVER registers (RCSTAx). USART1 and USART2 each have TRANSMITTER (USART) their own independent and distinct pairs of transmit and receive control registers, which are identical to each The Universal Synchronous Asynchronous Receiver other apart from their names. Similarly, each USART Transmitter (USART) module (also known as a Serial has its own distinct set of transmit, receive and baud Communications Interface or SCI) is one of the two rate registers. types of serial I/O modules available on PIC18FXX20 devices. Each device has two USARTs, which can be Note: Throughout this section, references to configured independently of each other. Each can be register and bit names that may be associ- configured as a full-duplex asynchronous system that ated with a specific USART module are can communicate with peripheral devices, such as referred to generically by the use of ‘x’ in CRT terminals and personal computers, or as a half- place of the specific module number. duplex synchronous system that can communicate Thus, “RCSTAx” might refer to the receive with peripheral devices, such as A/D or D/A integrated status register for either USART1 or circuits, serial EEPROMs, etc. USART2. The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) The pins of USART1 and USART2 are multiplexed with the functions of PORTC (RC6/TX1/CK1 and RC7/RX1/ DT1) and PORTG (RG1/TX2/CK2 and RG2/RX2/DT2), respectively. In order to configure these pins as a USART: • For USART1: - bit SPEN (RCSTA1<7>) must be set (= 1) - bit TRISC<7> must be set (= 1) - bit TRISC<6> must be cleared (= 0) for Asynchronous and Synchronous Master modes - bit TRISC<6> must be set (= 1) for Synchronous Slave mode • For USART2: - bit SPEN (RCSTA2<7>) must be set (= 1) - bit TRISG<2> must be set (= 1) - bit TRISG<1> must be cleared (= 0) for Asynchronous and Synchronous Master modes - bit TRISC<6> must be set (= 1) for Synchronous Slave mode  2003-2013 Microchip Technology Inc. DS39609C-page 197

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 18-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as ‘0’ bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 198  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 18-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 199

PIC18F6520/8520/6620/8620/6720/8720 18.1 USART Baud Rate Generator Example18-1 shows the calculation of the baud rate (BRG) error for the following conditions: • FOSC = 16 MHz The BRG supports both the Asynchronous and • Desired Baud Rate = 9600 Synchronous modes of the USARTs. It is a dedicated 8-bit Baud Rate Generator. The SPBRG register • BRGH = 0 controls the period of a free running 8-bit timer. In Asyn- • SYNC = 0 chronous mode, bit BRGH (TXSTAx<2>) also controls It may be advantageous to use the high baud rate the baud rate. In Synchronous mode, bit BRGH is (BRGH = 1) even for slower baud clocks. This is ignored. Table18-1 shows the formula for computation because the equation in Example18-1 can reduce the of the baud rate for different USART modes, which only baud rate error in some cases. apply in Master mode (internal clock). Writing a new value to the SPBRGx register causes the Given the desired baud rate and FOSC, the nearest BRG timer to be reset (or cleared). This ensures the integer value for the SPBRGx register can be calcu- BRG does not wait for a timer overflow before lated using the formula in Table18-1. From this, the outputting the new baud rate. error in baud rate can be determined. 18.1.1 SAMPLING The data on the RXx pin (either RC7/RX1/DT1 or RG2/ RX2/DT2) is sampled three times by a majority detect circuit to determine if a high or a low level is present at the pin. EXAMPLE 18-1: CALCULATING BAUD RATE ERROR Desired Baud Rate = FOSC/(64 (X + 1)) Solving for X: X = ((FOSC/Desired Baud Rate)/64 ) – 1 X = ((16000000/9600)/64) – 1 X = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate) Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 18-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64(X + 1)) Baud Rate = FOSC/(16(X + 1)) 1 (Synchronous) Baud Rate = FOSC/(4(X + 1)) N/A Legend: X = value in SPBRGx (0 to 255) TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TXSTAx CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRGx Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’ indicates the particular module. Bit names and Reset values are identical between modules. DS39609C-page 200  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 18-3: BAUD RATES FOR SYNCHRONOUS MODE FOSC = 40 MHz 33 MHz 25 MHz 20 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG % % % % (Kbps) value value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - NA - - NA - - 19.2 NA - - NA - - NA - - NA - - 76.8 76.92 +0.16 129 77.10 +0.39 106 77.16 +0.47 80 76.92 +0.16 64 96 96.15 +0.16 103 95.93 -0.07 85 96.15 +0.16 64 96.15 +0.16 51 300 303.03 +1.01 32 294.64 -1.79 27 297.62 -0.79 20 294.12 -1.96 16 500 500 0 19 485.30 -2.94 16 480.77 -3.85 12 500 0 9 HIGH 10000 - 0 8250 - 0 6250 - 0 5000 - 0 LOW 39.06 - 255 32.23 - 255 24.41 - 255 19.53 - 255 FOSC = 16 MHz 10 MHz 7.15909 MHz 5.0688 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG % % % % (Kbps) value value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - 9.62 +0.23 185 9.60 0 131 19.2 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 19.20 0 65 76.8 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 74.54 -2.94 16 96 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 97.48 +1.54 12 300 307.70 +2.56 12 312.50 +4.17 7 298.35 -0.57 5 316.80 +5.60 3 500 500 0 7 500 0 4 447.44 -10.51 3 422.40 -15.52 2 HIGH 4000 - 0 2500 - 0 1789.80 - 0 1267.20 - 0 LOW 15.63 - 255 9.77 - 255 6.99 - 255 4.95 - 255 FOSC = 4 MHz 3.579545 MHz 1 MHz 32.768 kHz BAUD RATE SPBRG SPBRG SPBRG SPBRG % % % % (Kbps) value value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) (decimal) 0.3 NA - - NA - - NA - - 0.30 +1.14 26 1.2 NA - - NA - - 1.20 +0.16 207 1.17 -2.48 6 2.4 NA - - NA - - 2.40 +0.16 103 2.73 +13.78 2 9.6 9.62 +0.16 103 9.62 +0.23 92 9.62 +0.16 25 8.20 -14.67 0 19.2 19.23 +0.16 51 19.04 -0.83 46 19.23 +0.16 12 NA - - 76.8 76.92 +0.16 12 74.57 -2.90 11 83.33 +8.51 2 NA - - 96 1000 +4.17 9 99.43 +3.57 8 83.33 -13.19 2 NA - - 300 333.33 +11.11 2 298.30 -0.57 2 250 -16.67 0 NA - - 500 500 0 1 447.44 -10.51 1 NA - - NA - - HIGH 1000 - 0 894.89 - 0 250 - 0 8.20 - 0 LOW 3.91 - 255 3.50 - 255 0.98 - 255 0.03 - 255  2003-2013 Microchip Technology Inc. DS39609C-page 201

PIC18F6520/8520/6620/8620/6720/8720 TABLE 18-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 40 MHz 33 MHz 25 MHz 20 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG % % % % (Kbps) value value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - 2.40 -0.07 214 2.40 -0.15 162 2.40 +0.16 129 9.6 9.62 +0.16 64 9.55 -0.54 53 9.53 -0.76 40 9.47 -1.36 32 19.2 18.94 -1.36 32 19.10 -0.54 26 19.53 +1.73 19 19.53 +1.73 15 76.8 78.13 +1.73 7 73.66 -4.09 6 78.13 +1.73 4 78.13 +1.73 3 96 89.29 -6.99 6 103.13 +7.42 4 97.66 +1.73 3 104.17 +8.51 2 300 312.50 +4.17 1 257.81 -14.06 1 NA - - 312.50 +4.17 0 500 625 +25.00 0 NA - - NA - - NA - - HIGH 625 - 0 515.63 - 0 390.63 - 0 312.50 - 0 LOW 2.44 - 255 2.01 - 255 1.53 - 255 1.22 - 255 FOSC = 16 MHz 10 MHz 7.15909 MHz 5.0688 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG % % % % (Kbps) value value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 1.20 +0.16 207 1.20 +0.16 129 1.20 +0.23 92 1.20 0 65 2.4 2.40 +0.16 103 2.40 +0.16 64 2.38 -0.83 46 2.40 0 32 9.6 9.62 +0.16 25 9.77 +1.73 15 9.32 -2.90 11 9.90 +3.13 7 19.2 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 19.80 +3.13 3 76.8 83.33 +8.51 2 78.13 +1.73 1 111.86 +45.65 0 79.20 +3.13 0 96 83.33 -13.19 2 78.13 -18.62 1 NA - - NA - - 300 250 -16.67 0 156.25 -47.92 0 NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 250 - 0 156.25 - 0 111.86 - 0 79.20 - 0 LOW 0.98 - 255 0.61 - 255 0.44 - 255 0.31 - 255 FOSC = 4 MHz 3.579545 MHz 1 MHz 32.768 kHz BAUD RATE SPBRG SPBRG SPBRG SPBRG % % % % (Kbps) value value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) (decimal) 0.3 0.30 -0.16 207 0.30 +0.23 185 0.30 +0.16 51 0.26 -14.67 1 1.2 1.20 +1.67 51 1.19 -0.83 46 1.20 +0.16 12 NA - - 2.4 2.40 +1.67 25 2.43 +1.32 22 2.23 -6.99 6 NA - - 9.6 8.93 -6.99 6 9.32 -2.90 5 7.81 -18.62 1 NA - - 19.2 20.83 +8.51 2 18.64 -2.90 2 15.63 -18.62 0 NA - - 76.8 62.50 -18.62 0 55.93 -27.17 0 NA - - NA - - 96 NA - - NA - - NA - - NA - - 300 NA - - NA - - NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 62.50 - 0 55.93 - 0 15.63 - 0 0.51 - 0 LOW 0.24 - 255 0.22 - 255 0.06 - 255 0.002 - 255 DS39609C-page 202  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 40 MHz 33 MHz 25 MHz 20 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG % % % % (Kbps) value value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - 9.60 -0.07 214 9.59 -0.15 162 9.62 +0.16 129 19.2 19.23 +0.16 129 19.28 +0.39 106 19.30 +0.47 80 19.23 +0.16 64 76.8 75.76 -1.36 32 76.39 -0.54 26 78.13 +1.73 19 78.13 +1.73 15 96 96.15 +0.16 25 98.21 +2.31 20 97.66 +1.73 15 96.15 +0.16 12 300 312.50 +4.17 7 294.64 -1.79 6 312.50 +4.17 4 312.50 +4.17 3 500 500 0 4 515.63 +3.13 3 520.83 +4.17 2 416.67 -16.67 2 HIGH 2500 - 0 2062.50 - 0 1562.50 - 0 1250 - 0 LOW 9.77 - 255 8,06 - 255 6.10 - 255 4.88 - 255 FOSC = 16 MHz 10 MHz 7.15909 MHz 5.0688 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG % % % % (Kbps) value value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - 2.41 +0.23 185 2.40 0 131 9.6 9.62 +0.16 103 9.62 +0.16 64 9.52 -0.83 46 9.60 0 32 19.2 19.23 +0.16 51 18.94 -1.36 32 19.45 +1.32 22 18.64 -2.94 16 76.8 76.92 +0.16 12 78.13 +1.73 7 74.57 -2.90 5 79.20 +3.13 3 96 100 +4.17 9 89.29 -6.99 6 89.49 -6.78 4 105.60 +10.00 2 300 333.33 +11.11 2 312.50 +4.17 1 447.44 +49.15 0 316.80 +5.60 0 500 500 0 1 625 +25.00 0 447.44 -10.51 0 NA - - HIGH 1000 - 0 625 - 0 447.44 - 0 316.80 - 0 LOW 3.91 - 255 2.44 - 255 1.75 - 255 1.24 - 255 FOSC = 4 MHz 3.579545 MHz 1 MHz 32.768 kHz BAUD RATE SPBRG SPBRG SPBRG SPBRG % % % % (Kbps) value value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) (decimal) 0.3 NA - - NA - - 0.30 +0.16 207 0.29 -2.48 6 1.2 1.20 +0.16 207 1.20 +0.23 185 1.20 +0.16 51 1.02 -14.67 1 2.4 2.40 +0.16 103 2.41 +0.23 92 2.40 +0.16 25 2.05 -14.67 0 9.6 9.62 +0.16 25 9.73 +1.32 22 8.93 -6.99 6 NA - - 19.2 19.23 +0.16 12 18.64 -2.90 11 20.83 +8.51 2 NA - - 76.8 NA - - 74.57 -2.90 2 62.50 -18.62 0 NA - - 96 NA - - 111.86 +16.52 1 NA - - NA - - 300 NA - - 223.72 -25.43 0 NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 250 - 0 55.93 - 0 62.50 - 0 2.05 - 0 LOW 0.98 - 255 0.22 - 255 0.24 - 255 0.008 - 255  2003-2013 Microchip Technology Inc. DS39609C-page 203

PIC18F6520/8520/6620/8620/6720/8720 18.2 USART Asynchronous Mode PIR3<4> for USART2), is set. This interrupt can be enabled/disabled by setting/clearing enable bit, TXxIE In this mode, the USARTs use standard Non-Return-to- (PIE1<4> for USART1, PIE<4> for USART2). Flag bit Zero (NRZ) format (one Start bit, eight or nine data bits TXxIF will be set, regardless of the state of enable bit and one Stop bit). The most common data format is TXxIE and cannot be cleared in software. It will reset 8bits. An on-chip dedicated 8-bit Baud Rate Generator only when new data is loaded into the TXREGx register. can be used to derive standard baud rate frequencies While flag bit TXIF indicates the status of the TXREGx from the oscillator. The USART transmits and receives register, another bit, TRMT (TXSTAx<1>), shows the the LSb first. The USART’s transmitter and receiver are status of the TSR register. Status bit TRMT is a read-only functionally independent, but use the same data format bit, which is set when the TSR register is empty. No and baud rate. The Baud Rate Generator produces a interrupt logic is tied to this bit, so the user has to poll this clock, either 16 or 64 times the bit shift rate, depending bit in order to determine if the TSR register is empty. on bit BRGH (TXSTAx<2>). Parity is not supported by the hardware, but can be implemented in software (and Note1: The TSR register is not mapped in data stored as the ninth data bit). Asynchronous mode is memory, so it is not available to the user. stopped during Sleep. 2: Flag bit TXIF is set when enable bit TXEN Asynchronous mode is selected by clearing bit SYNC is set. (TXSTAx<4>). To set up an Asynchronous Transmission: The USART Asynchronous module consists of the 1. Initialize the SPBRGx register for the appropri- following important elements: ate baud rate. If a high-speed baud rate is • Baud Rate Generator desired, set bit BRGH (Section18.1 “USART Baud Rate Generator (BRG)”). • Sampling Circuit 2. Enable the asynchronous serial port by clearing • Asynchronous Transmitter bit SYNC and setting bit SPEN. • Asynchronous Receiver 3. If interrupts are desired, set enable bit TXxIE in 18.2.1 USART ASYNCHRONOUS the appropriate PIE register. TRANSMITTER 4. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. The USART transmitter block diagram is shown in 5. Enable the transmission by setting bit TXEN, Figure18-1. The heart of the transmitter is the Transmit which will also set bit TXxIF. (Serial) Shift Register (TSR). The shift register obtains 6. If 9-bit transmission is selected, the ninth bit its data from the Read/Write Transmit Buffer register, should be loaded in bit TX9D. TXREGx. The TXREGx register is loaded with data in software. The TSR register is not loaded until the Stop 7. Load data to the TXREGx register (starts bit has been transmitted from the previous load. As transmission). soon as the Stop bit is transmitted, the TSR is loaded Note: TXIF is not cleared immediately upon with new data from the TXREGx register (if available). loading data into the transmit buffer Once the TXREGx register transfers the data to the TXREG. The flag bit becomes valid in the TSR register (occurs in one TCY), the TXREGx register second instruction cycle following the load is empty and flag bit, TXx1IF (PIR1<4> for USART1, instruction. FIGURE 18-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8)  0 Pin Buffer and Control TSR Register TX pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D DS39609C-page 204  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 18-2: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX1/CK1 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 18-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) RC6/TX1/CK1 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit (Interrupt Reg. Flag) Word 1 Word 2 TRMT bit Word 1 Word 2 Reg(T. rEamnspmtyi tF Slahgif)t Transmit Shift Reg. Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 RCSTAx(1) SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x TXREGx(1) USART Transmit Register 0000 0000 0000 0000 TXSTAx(1) CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRGx(1) Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’ indicates the particular module. Bit names and Reset values are identical between modules.  2003-2013 Microchip Technology Inc. DS39609C-page 205

PIC18F6520/8520/6620/8620/6720/8720 18.2.2 USART ASYNCHRONOUS 18.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The USART receiver block diagram is shown in This mode would typically be used in RS-485 systems. Figure18-4. The data is received on the pin (RC7/RX1/ To set up an Asynchronous Reception with Address DT1 or RG2/RX2/DT2) and drives the data recovery Detect Enable: block. The data recovery block is actually a high-speed 1. Initialize the SPBRGx register for the appropri- shifter operating at 16 times the baud rate, whereas the ate baud rate. If a high-speed baud rate is main receive serial shifter operates at the bit rate or at required, set the BRGH bit. FOSC. This mode would typically be used in RS-232 2. Enable the asynchronous serial port by clearing systems. the SYNC bit and setting the SPEN bit. To set up an Asynchronous Reception: 3. If interrupts are required, set the RCEN bit and 1. Initialize the SPBRG register for the appropriate select the desired priority level with the RCIP bit. baud rate. If a high-speed baud rate is desired, 4. Set the RX9 bit to enable 9-bit reception. set bit BRGH (Section18.1 “USART Baud 5. Set the ADDEN bit to enable address detect. Rate Generator (BRG)”). 6. Enable reception by setting the CREN bit. 2. Enable the asynchronous serial port by clearing 7. The RCxIF bit will be set when reception is bit SYNC and setting bit SPEN. complete. The interrupt will be Acknowledged if 3. If interrupts are desired, set enable bit RCxIE. the RCxIE and GIE bits are set. 4. If 9-bit reception is desired, set bit RX9. 8. Read the RCSTAx register to determine if any 5. Enable the reception by setting bit CREN. error occurred during reception, as well as read 6. Flag bit RCxIF will be set when reception is com- bit 9 of data (if applicable). plete and an interrupt will be generated if enable 9. Read RCREGx to determine if the device is bit RCxIE was set. being addressed. 7. Read the RCSTAx register to get the ninth bit (if 10. If any error occurred, clear the CREN bit. enabled) and determine if any error occurred 11. If the device has been addressed, clear the during reception. ADDEN bit to allow all received data into the 8. Read the 8-bit received data by reading the receive buffer and interrupt the CPU. RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 18-4: USART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK  64 MSb RSR Register LSb SPBRG or  16 Stop (8) 7  1 0 Start Baud Rate Generator RX9 RX pin Pin Buffer Data and Control Recovery RX9D RCREG Register FIFO SPEN 8 Interrupt RCIF Data Bus RCIE DS39609C-page 206  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 18-5: ASYNCHRONOUS RECEPTION RX (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. TABLE 18-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 GIEH GIEL PIR1 PSPIF ADIF RC1IF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RC1IE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RC1IP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 RCSTAx(1) SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x RCREGx(1) USART Receive Register 0000 0000 0000 0000 TXSTAx(1) CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRGx(1) Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’ indicates the particular module. Bit names and Reset values are identical between modules.  2003-2013 Microchip Technology Inc. DS39609C-page 207

PIC18F6520/8520/6620/8620/6720/8720 18.3 USART Synchronous Master set, regardless of the state of enable bit TXxIE and can- Mode not be cleared in software. It will reset only when new data is loaded into the TXREGx register. While flag bit In Synchronous Master mode, the data is transmitted in TXxIF indicates the status of the TXREGx register, a half-duplex manner (i.e., transmission and reception another bit TRMT (TXSTAx<1>) shows the status of the do not occur at the same time). When transmitting data, TSR register. TRMT is a read-only bit, which is set the reception is inhibited and vice versa. Synchronous when the TSR is empty. No interrupt logic is tied to this mode is entered by setting bit SYNC (TXSTAx<4>). In bit, so the user has to poll this bit in order to determine addition, enable bit SPEN (RCSTAx<7>) is set in order if the TSR register is empty. The TSR is not mapped in to configure the appropriate I/O pins to CK (clock) and data memory, so it is not available to the user. DT (data) lines, respectively. The Master mode indi- To set up a Synchronous Master Transmission: cates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit 1. Initialize the SPBRG register for the appropriate CSRC (TXSTAx<7>). baud rate (Section18.1 “USART Baud Rate Generator (BRG)”). 18.3.1 USART SYNCHRONOUS MASTER 2. Enable the synchronous master serial port by TRANSMISSION setting bits SYNC, SPEN and CSRC. The USART transmitter block diagram is shown in 3. If interrupts are desired, set enable bit TXxIE in Figure18-1. The heart of the transmitter is the Transmit the appropriate PIE register. (Serial) Shift Register (TSR). The shift register obtains 4. If 9-bit transmission is desired, set bit TX9. its data from the Read/Write Transmit Buffer register, 5. Enable the transmission by setting bit TXEN. TXREG. The TXREGx register is loaded with data in 6. If 9-bit transmission is selected, the ninth bit software. The TSR register is not loaded until the last should be loaded in bit TX9D. bit has been transmitted from the previous load. As 7. Start transmission by loading data to the soon as the last bit is transmitted, the TSR is loaded TXREGx register. with new data from the TXREGx (if available). Once the TXREGx register transfers the data to the TSR register Note: TXIF is not cleared immediately upon (occurs in one TCYCLE), the TXREGx is empty and loading data into the transmit buffer interrupt bit TXxIF (PIR1<4> for USART1, PIR3<4> for TXREG. The flag bit becomes valid in the USART2) is set. The interrupt can be enabled/disabled second instruction cycle following the load by setting/clearing enable bit TXxIE (PIE1<4> for instruction. USART1, PIE3<4> for USART2). Flag bit TXxIF will be TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 RCSTAx(1) SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x TXREGx(1) USART Transmit Register 0000 0000 0000 0000 TXSTAx(1) CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRGx(1) Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’ indicates the particular module. Bit names and Reset values are identical between modules. DS39609C-page 208  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 18-6: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX1/CK1 pin Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMTTR bMitT ‘1’ ‘1’ TXEN bit Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words. FIGURE 18-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG reg TXIF bit TRMT bit TXEN bit  2003-2013 Microchip Technology Inc. DS39609C-page 209

PIC18F6520/8520/6620/8620/6720/8720 18.3.2 USART SYNCHRONOUS MASTER 4. If interrupts are desired, set enable bit RCxIE in RECEPTION the appropriate PIE register. 5. If 9-bit reception is desired, set bit RX9. Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN 6. If a single reception is required, set bit SREN. (RCSTAx<5>) or enable bit CREN (RCSTAx<4>). Data For continuous reception, set bit CREN. is sampled on the RXx pin (RC7/RX1/DT1 or RG2/RX2/ 7. Interrupt flag bit RCxIF will be set when DT2) on the falling edge of the clock. If enable bit SREN reception is complete and an interrupt will be is set, only a single word is received. If enable bit CREN generated if the enable bit RCxIE was set. is set, the reception is continuous until CREN is cleared. 8. Read the RCSTAx register to get the ninth bit (if If both bits are set, then CREN takes precedence. enabled) and determine if any error occurred To set up a Synchronous Master Reception: during reception. 9. Read the 8-bit received data by reading the 1. Initialize the SPBRGx register for the appropri- RCREGx register. ate baud rate (Section18.1 “USART Baud Rate Generator (BRG)”). 10. If any error occurred, clear the error by clearing bit CREN. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are 3. Ensure bits CREN and SREN are clear. set. TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 RCSTAx(1) SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x RCREGx(1) USART Receive Register 0000 0000 0000 0000 TXSTAx(1) CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRGx(1) Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’ indicates the particular module. Bit names and Reset values are identical between modules. FIGURE 18-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX1/CK1 pin Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. DS39609C-page 210  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 18.4 USART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by Synchronous Slave mode differs from the Master mode setting bits SYNC and SPEN and clearing bit in the fact that the shift clock is supplied externally at CSRC. the TXx pin (RC6/TX1/CK1 or RG1/TX2/CK2), instead of being supplied internally in Master mode. TRISC<6> 2. Clear bits CREN and SREN. must be set for this mode. This allows the device to 3. If interrupts are desired, set enable bit TXxIE. transfer or receive data while in Sleep mode. Slave 4. If 9-bit transmission is desired, set bit TX9. mode is entered by clearing bit CSRC (TXSTAx<7>). 5. Enable the transmission by setting enable bit TXEN. 18.4.1 USART SYNCHRONOUS SLAVE 6. If 9-bit transmission is selected, the ninth bit TRANSMIT should be loaded in bit TX9D. The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the modes are identical, except in the case of the Sleep TXREGx register. mode. 8. If using interrupts, ensure that the GIE and PEIE If two words are written to the TXREG and then the bits in the INTCON register (INTCON<7:6>) are SLEEP instruction is executed, the following will occur: set. a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in TXREG register. c) Flag bit TXxIF will not be set. d) When the first word has been shifted out of TSR, the TXREGx register will transfer the second word to the TSR and flag bit TXxIF will now be set. e) If enable bit TXxIE is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 GIEH GIEL PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 RCSTAx(1) SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x TXREGx(1) USART Transmit Register 0000 0000 0000 0000 TXSTAx(1) CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRGx(1) Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’ indicates the particular module. Bit names and Reset values are identical between modules.  2003-2013 Microchip Technology Inc. DS39609C-page 211

PIC18F6520/8520/6620/8620/6720/8720 18.4.2 USART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits SYNC and SPEN and clearing bit modes is identical, except in the case of the Sleep CSRC. mode and bit SREN, which is a “don’t care” in Slave 2. If interrupts are desired, set enable bit RCxIE. mode. 3. If 9-bit reception is desired, set bit RX9. If receive is enabled by setting bit CREN prior to the 4. To enable reception, set enable bit CREN. SLEEP instruction, then a word may be received during 5. Flag bit RCxIF will be set when reception is Sleep. On completely receiving the word, the RSR reg- complete. An interrupt will be generated if ister will transfer the data to the RCREG register and if enable bit RCxIE was set. enable bit RCxIE bit is set, the interrupt generated will 6. Read the RCSTAx register to get the ninth bit (if wake the chip from Sleep. If the global interrupt is enabled) and determine if any error occurred enabled, the program will branch to the interrupt vector. during reception. 7. Read the 8-bit received data by reading the RCREGx register. 8. If any error occurred, clear the error by clearing bit CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 GIEH GIEL PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000 PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000 IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111 RCSTAx(1) SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x RCREGx(1) USART Receive Register 0000 0000 0000 0000 TXSTAx(1) CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRGx(1) Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’ indicates the particular module. Bit names and Reset values are identical between modules. DS39609C-page 212  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 19.0 10-BIT ANALOG-TO-DIGITAL The module has five registers: CONVERTER (A/D) MODULE • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) The analog-to-digital (A/D) converter module has 12 • A/D Control Register 0 (ADCON0) inputs for the PIC18F6X20 devices and 16 for the PIC18F8X20 devices. This module allows conversion • A/D Control Register 1 (ADCON1) of an analog input signal to a corresponding 10-bit • A/D Control Register 2 (ADCON2) digital number. The ADCON0 register, shown in Register19-1, con- trols the operation of the A/D module. The ADCON1 register, shown in Register19-2, configures the func- tions of the port pins. The ADCON2 register, shown in Register19-3, configures the A/D clock source and justification. REGISTER 19-1: ADCON0 REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12)(1) 1101 = Channel 13 (AN13)(1) 1110 = Channel 14 (AN14)(1) 1111 = Channel 15 (AN15)(1) Note1: These channels are not available on the PIC18F6X20 (64-pin) devices. bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion, which is automatically cleared by hardware when the A/D conversion is complete) 0 = A/D conversion not in progress bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 213

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 19-2: ADCON1 REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits: VCFG1 A/D VREF+ A/D VREF- VCFG0 00 AVDD AVSS 01 External VREF+ AVSS 10 AVDD External VREF- 11 External VREF+ External VREF- bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits: PPCCFFGG30 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 0000 A A A A A A A A A A A A A A A A 0001 D D A A A A A A A A A A A A A A 0010 D D D A A A A A A A A A A A A A 0011 D D D D A A A A A A A A A A A A 0100 D D D D D A A A A A A A A A A A 0101 D D D D D D A A A A A A A A A A 0110 D D D D D D D A A A A A A A A A 0111 D D D D D D D D A A A A A A A A 1000 D D D D D D D D D A A A A A A A 1001 D D D D D D D D D D A A A A A A 1010 D D D D D D D D D D D A A A A A 1011 D D D D D D D D D D D D A A A A 1100 D D D D D D D D D D D D D A A A 1101 D D D D D D D D D D D D D D A A 1110 D D D D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D D D D A = Analog input D = Digital I/O Note: Shaded cells indicate A/D channels available only on PIC18F8X20 devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 214  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 19-3: ADCON2 REGISTER R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 ADFM — — — — ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6-3 Unimplemented: Read as ‘0’ bit 2-0 ADCS1:ADCS0: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from an RC oscillator = 1 MHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock derived from an RC oscillator = 1 MHz max) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown The analog reference voltage is software selectable to Each port pin associated with the A/D converter can be either the device’s positive and negative supply voltage configured as an analog input (RA3 can also be a (VDD and VSS), or the voltage level on the RA3/AN3/ voltage reference), or as a digital I/O. The ADRESH VREF+ pin and RA2/AN2/VREF- pin. and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the The A/D converter has a unique feature of being able result is loaded into the ADRESH/ADRESL registers, to operate while the device is in Sleep mode. To oper- the GO/DONE bit (ADCON0 register) is cleared and ate in Sleep, the A/D conversion clock must be derived A/D interrupt flag bit, ADIF, is set. The block diagram of from the A/D’s internal RC oscillator. the A/D module is shown in Figure19-1. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion is aborted.  2003-2013 Microchip Technology Inc. DS39609C-page 215

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 19-1: A/D BLOCK DIAGRAM CHS3:CHS0 1111 AN15(1) 1110 AN14(1) 1101 AN13(1) 1100 AN12(1) 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7 0110 AN6 0101 AN5 0100 AN4 VAIN 0011 10-bit (Input Voltage) AN3 Converter A/D 0010 AN2 0001 VCFG1:VCFG0 AN1 0000 AN0 VDD VREF+ Reference Voltage VREF- VSS Note1: Channels AN15 through AN12 are not available on PIC18F6X20 devices. 2: I/O pins have diode protection to VDD and VSS. DS39609C-page 216  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 The value in the ADRESH/ADRESL registers is not 2. Configure A/D interrupt (if desired): modified for a Power-on Reset. The ADRESH/ • Clear ADIF bit ADRESL registers will contain unknown data after a • Set ADIE bit Power-on Reset. • Set GIE bit After the A/D module has been configured as desired, 3. Wait the required acquisition time. the selected channel must be acquired before the con- 4. Start conversion: version is started. The analog input channels must • Set GO/DONE bit (ADCON0 register) have their corresponding TRIS bits selected as an 5. Wait for A/D conversion to complete, by either: input. To determine acquisition time, see Section19.1 “A/D Acquisition Requirements”. After this acquisi- • Polling for the GO/DONE bit to be cleared tion time has elapsed, the A/D conversion can be OR started. • Waiting for the A/D interrupt The following steps should be followed to do an A/D 6. Read A/D Result registers (ADRESH:ADRESL); conversion: clear bit ADIF, if required. 7. For the next conversion, go to step 1 or step 2, 1. Configure the A/D module: as required. The A/D conversion time per bit is • Configure analog pins, voltage reference and defined as TAD. A minimum wait of 2 TAD is digital I/O (ADCON1) required before the next acquisition starts. • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON2) • Turn on A/D module (ADCON0) FIGURE 19-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC 1k SS RSS VAIN C5 PpIFN VT = 0.6V ±IL E5A0K0A nGAE CHOLD = 120 pF VSS Legend: CPIN = input capacitance 6V VT = threshold voltage 5V ILEAKAGE = leakage current at the pin due to VDD 4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) RSS = sampling switch resistance 5 6 7 8 9 10 11 Sampling Switch (k)  2003-2013 Microchip Technology Inc. DS39609C-page 217

PIC18F6520/8520/6620/8620/6720/8720 19.1 A/D Acquisition Requirements Example19-1 shows the calculation of the minimum required acquisition time, TACQ. This calculation is For the A/D converter to meet its specified accuracy, based on the following application system the charge holding capacitor (CHOLD) must be allowed assumptions: to fully charge to the input channel voltage level. The analog input model is shown in Figure19-2. The CHOLD = 120 pF Rs = 2.5 k source impedance (RS) and the internal sampling Conversion Error  1/2 LSb switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling VDD = 5V  Rss = 7 k Temperature = 50C (system max.) switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage VHOLD = 0V @ time = 0 at the analog input (due to pin leakage current). The Note: When using external voltage references with maximum recommended impedance for analog the A/D converter, the source impedance of sources is 2.5 k. After the analog input channel is the external voltage references must be less selected (changed), this acquisition must be done than 20 to obtain the A/D performance before the conversion can be started. specified in parameters A01-A06. Higher Note: When the conversion is started, the reference source impedances will increase holding capacitor is disconnected from the both offset and gain errors. Resistive voltage input pin. dividers will not provide a sufficiently low source impedance. To calculate the minimum acquisition time, Equation19-1 may be used. This equation assumes To maintain the best possible performance in that 1/2 LSb error is used (1024 steps for the A/D). The A/D conversions, external VREF inputs should 1/2 LSb error is the maximum error allowed for the A/D be buffered with an operational amplifier or to meet its specified resolution. other low output impedance circuit. If deviating from the operating conditions specified for parameters A03-A06, the effect of parameter A50 (VREF input current) must be considered. EQUATION 19-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 19-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) (cid:129) (1 – e(-Tc/CHOLD(RIC + RSS + RS))) or TC = -(120 pF)(1 k + RSS + RS) ln(1/2047) EXAMPLE 19-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF Temperature coefficient is only required for temperatures > 25C. TACQ = 2 s + TC + [(Temp – 25C)(0.05 s/C)] TC = -CHOLD (RIC + RSS + RS) ln(1/2047) -120 pF (1 k + 7 k + 2.5 k) ln(0.0004885) -120 pF (10.5 k) ln(0.0004885) -1.26 s (-7.6241) 9.61 s TACQ = 2 s + 9.61 s + [(50C – 25C)(0.05 s/C)] 11.61 s + 1.25 s 12.86 s DS39609C-page 218  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 19.2 Selecting the A/D 19.3 Configuring Analog Port Pins Conversion Clock The ADCON1, TRISA, TRISF and TRISH registers The A/D conversion time per bit is defined as TAD. The control the operation of the A/D port pins. The port pins A/D conversion requires 12 TAD per 10-bit conversion. needed as analog inputs must have their correspond- The source of the A/D conversion clock is software ing TRIS bits set (input). If the TRIS bit is cleared selectable. There are seven possible options for TAD: (output), the digital output level (VOH or VOL) will be converted. • 2 TOSC The A/D operation is independent of the state of the • 4 TOSC CHS3:CHS0 bits and the TRIS bits. • 8 TOSC • 16 TOSC Note1: When reading the port register, all pins configured as analog input channels will • 32 TOSC read as cleared (a low level). Pins config- • 64 TOSC ured as digital inputs will convert as an • Internal RC oscillator analog input. Analog levels on a digitally For correct A/D conversions, the A/D conversion clock configured input will not affect the (TAD) must be selected to ensure a minimum TAD time conversion accuracy. of 1.6 s. 2: Analog levels on any pin defined as a dig- Table19-1 shows the resultant TAD times derived from ital input may cause the input buffer to the device operating frequencies and the A/D clock consume current out of the device’s source selected. specification limits. TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS2:ADCS0 PIC18FXX20 PIC18LFXX20 2 TOSC 000 1.25 MHz 666 kHz 4 TOSC 100 2.50 MHz 1.33 MHz 8 TOSC 001 5.00 MHz 2.67 MHz 16 TOSC 101 10.0 MHz 5.33 MHz 32 TOSC 010 20.0 MHz 10.67 MHz 64 TOSC 110 40.0 MHz 21.33 MHz RC x11 — —  2003-2013 Microchip Technology Inc. DS39609C-page 219

PIC18F6520/8520/6620/8620/6720/8720 19.4 A/D Conversions 19.5 Use of the CCP2 Trigger Figure19-3 shows the operation of the A/D converter An A/D conversion can be started by the “special event after the GO bit has been set. Clearing the GO/DONE trigger” of the CCP2 module. This requires that the bit during a conversion will abort the current conver- CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- sion. The A/D Result register pair will NOT be updated grammed as ‘1011’ and that the A/D module is enabled with the partially completed A/D conversion sample. (ADON bit is set). When the trigger occurs, the GO/ That is, the ADRESH:ADRESL registers will continue DONE bit will be set, starting the A/D conversion and to contain the value of the last completed conversion the Timer1 (or Timer3) counter will be reset to zero. (or the last value written to the ADRESH:ADRESL reg- Timer1 (or Timer3) is reset to automatically repeat the isters). After the A/D conversion is aborted, a 2 TAD wait A/D acquisition period with minimal software overhead is required before the next acquisition is started. After (moving ADRESH/ADRESL to the desired location). this 2 TAD wait, acquisition on the selected channel is The appropriate analog input channel must be selected automatically started. and the minimum acquisition done before the “special event trigger” sets the GO/DONE bit (starts a Note: The GO/DONE bit should NOT be set in conversion). the same instruction that turns on the A/D. If the A/D module is not enabled (ADON is cleared), the “special event trigger” will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter. FIGURE 19-3: A/D CONVERSION TAD CYCLES TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS39609C-page 220  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 19-2: SUMMARY OF A/D REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000 PIE2 — CMIE — — BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000 IPR2 — CMIP — — BCLIP LVDIP TMR3IP CCP2IP -0-- 0000 -0-- 0000 ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu ADCON0 — — CHS3 CHS3 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 ADCON2 ADFM — — — — ADCS2 ADCS1 ADCS0 0--- -000 0--- -000 PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 TRISA — PORTA Data Direction Register --11 1111 --11 1111 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 x000 0000 u000 0000 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx uuuu uuuu TRISF PORTF Data Direction Control Register 1111 1111 1111 1111 PORTH(1) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 0000 xxxx 0000 xxxx LATH(1) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx uuuu uuuu TRISH(1) PORTH Data Direction Control Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: Only available on PIC18F8X20 devices.  2003-2013 Microchip Technology Inc. DS39609C-page 221

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 222  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 20.0 COMPARATOR MODULE The CMCON register, shown as Register20-1, con- trols the comparator input and output multiplexers. A The comparator module contains two analog compara- block diagram of the various comparator configurations tors. The inputs to the comparators are multiplexed is shown in Figure20-1. with the RF1 through RF6 pins. The on-chip voltage ref- erence (Section21.0 “Comparator Voltage Reference Module”) can also be an input to the comparators. REGISTER 20-1: CMCON REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RF5/AN10 C2 VIN- connects to RF3/AN8 0 = C1 VIN- connects to RF6/AN11 C2 VIN- connects to RF4/AN9 bit 2-0 CM2:CM0: Comparator Mode bits Figure20-1 shows the Comparator modes and the CM2:CM0 bit settings. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 223

PIC18F6520/8520/6620/8620/6720/8720 20.1 Comparator Configuration be valid for the specified mode change delay shown in the Electrical Specifications (Section26.0 “Electrical There are eight modes of operation for the compara- Characteristics”). tors. The CMCON register is used to select these modes. Figure20-1 shows the eight possible modes. Note: Comparator interrupts should be disabled The TRISF register controls the data direction of the during a Comparator mode change. comparator pins for each mode. If the Comparator Otherwise, a false interrupt may occur. mode is changed, the comparator output level may not FIGURE 20-1: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) Comparators Off CM2:CM0 = 000 CM2:CM0 = 111 RF6/AN11 A VIN- RF6/AN11 D VIN- RF5/AN10 A VIN+ C1 Off (Read as ‘0’) RF5/AN10 D VIN+ C1 Off (Read as ‘0’) RF4/AN9 A VIN- RF4/AN9 D VIN- RF3/AN8 A VIN+ C2 Off (Read as ‘0’) RF3/AN8 D VIN+ C2 Off (Read as ‘0’) Two Independent Comparators with Outputs Two Independent Comparators CM2:CM0 = 011 CM2:CM0 = 010 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10 A VIN+ C1 C1OUT RF5/AN10 A VIN+ C1 C1OUT RF2/AN7/C1OUT RF4/AN9 A VIN- RF4/AN9 A VIN- RF3/AN8 A VIN+ C2 C2OUT RF3/AN8 A VIN+ C2 C2OUT RF1/AN6/C2OUT Two Common Reference Comparators Two Common Reference Comparators with Outputs CM2:CM0 = 100 CM2:CM0 = 101 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10 A VIN+ C1 C1OUT RF5/AN10 A VIN+ C1 C1OUT RF2/AN7/C1OUT RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF1/AN6/C2OUT One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM2:CM0 = 001 CM2:CM0 = 110 RF6/AN11 A VIN- RF6/AN11 A CIS = 0 VIN- RF5/AN10 A VIN+ C1 C1OUT RF5/AN10 A CIS = 1 VIN+ C1 C1OUT RF2/AN7/C1OUT A RF4/AN9 CIS = 0 VIN- RF4/AN9 D VIN- RF3/AN8 A CIS = 1 VIN+ C2 C2OUT RF3/AN8 D VIN+ C2 Off (Read as ‘0’) CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch DS39609C-page 224  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 20.2 Comparator Operation 20.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure20-2, along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference for the compara- the digital output. When the analog input at VIN+ is less tors. Section21.0 “Comparator Voltage Reference than the analog input VIN-, the output of the comparator Module” contains a detailed description of the compar- is a digital low level. When the analog input at VIN+ is ator voltage reference module that provides this signal. greater than the analog input VIN-, the output of the The internal reference signal is used when comparators comparator is a digital high level. The shaded areas of are in mode CM<2:0>=110 (Figure20-1). In this the output of the comparator in Figure20-2 represent mode, the internal voltage reference is applied to the the uncertainty, due to input offsets and response time. VIN+ pin of both comparators. 20.3 Comparator Reference 20.4 Comparator Response Time An external or internal reference signal may be used, Response time is the minimum time, after selecting a depending on the comparator operating mode. The new reference voltage or input source, before the com- analog signal present at VIN- is compared to the signal parator output has a valid level. If the internal reference at VIN+ and the digital output of the comparator is is changed, the maximum delay of the internal voltage adjusted accordingly (Figure20-2). reference must be considered when using the compar- ator outputs. Otherwise, the maximum delay of the comparators should be used (Section26.0 “Electrical FIGURE 20-2: SINGLE COMPARATOR Characteristics”). 20.5 Comparator Outputs VIN+ + Output VIN- – The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RF1 and RF2 I/O pins. When enabled, multiplexors in the output path of the RF1 and RF2 pins will switch and the output of each pin will be the unsynchronized output of the com- VIVNI-N– parator. The uncertainty of each of the comparators is related to the input offset voltage and the response time VIVNIN++ given in the specifications. Figure20-3 shows the comparator output block diagram. The TRISF bits will still function as an output enable/ OOuuttppuutt disable for the RF1 and RF2 pins while in this mode. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>). 20.3.1 EXTERNAL REFERENCE SIGNAL Note1: When reading the port register, all pins configured as analog inputs will read as a When external voltage references are used, the ‘0’. Pins configured as digital inputs will comparator module can be configured to have the com- convert an analog input, according to the parators operate from the same, or different reference Schmitt Trigger input specification. sources. However, threshold detector applications may require the same reference. The reference signal must 2: Analog levels on any pin defined as a dig- be between VSS and VDD and can be applied to either ital input may cause the input buffer to pin of the comparator(s). consume more current than is specified.  2003-2013 Microchip Technology Inc. DS39609C-page 225

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 20-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port pins MULTIPLEX + - CxINV To RF1 or RF2 pin Bus Q D Data Read CMCON EN Set CMIF Q D bit From Other EN Comparator CL Read CMCON Reset 20.6 Comparator Interrupts Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a The comparator interrupt flag is set whenever there is read operation is being executed (start of a change in the output value of either comparator. the Q2 cycle), then the CMIF (PIR Software will need to maintain information about the registers) interrupt flag may not get set. status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF The user, in the Interrupt Service Routine, can clear the bit (PIR registers) is the Comparator Interrupt Flag. The interrupt in the following manner: CMIF bit must be reset by clearing ‘0’. Since it is also a) Any read or write of CMCON will end the possible to write a ‘1’ to this register, a simulated mismatch condition. interrupt may be initiated. b) Clear flag bit CMIF. The CMIE bit (PIE registers) and the PEIE bit (INTCON A mismatch condition will continue to set flag bit CMIF. register) must be set to enable the interrupt. In addition, Reading CMCON will end the mismatch condition and the GIE bit must also be set. If any of these bits are allow flag bit CMIF to be cleared. clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. DS39609C-page 226  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 20.7 Comparator Operation 20.9 Analog Input Connection During Sleep Considerations When a comparator is active and the device is placed A simplified circuit for an analog input is shown in in Sleep mode, the comparator remains active and the Figure20-4. Since the analog pins are connected to a interrupt is functional, if enabled. This interrupt will digital output, they have reverse biased diodes to VDD wake-up the device from Sleep mode, when enabled. and VSS. The analog input, therefore, must be between While the comparator is powered up, higher Sleep VSS and VDD. If the input voltage deviates from this currents than shown in the power-down current range by more than 0.6V in either direction, one of the specification will occur. Each operational comparator diodes is forward biased and a latch-up condition may will consume additional current, as shown in the com- occur. A maximum source impedance of 10k is parator specifications. To minimize power consumption recommended for the analog sources. Any external while in Sleep mode, turn off the comparators component connected to an analog input pin, such as (CM<2:0>=111) before entering Sleep. If the device a capacitor or a Zener diode, should have very little wakes up from Sleep, the contents of the CMCON leakage current. register are not affected. 20.8 Effects of a Reset A device Reset forces the CMCON register to its Reset state, causing the comparator module to be in the Com- parator Reset mode, CM<2:0>=000. This ensures that all potential inputs are analog inputs. Device cur- rent is minimized when analog inputs are present at Reset time. The comparators will be powered down during the Reset interval. FIGURE 20-4: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L5E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage  2003-2013 Microchip Technology Inc. DS39609C-page 227

PIC18F6520/8520/6620/8620/6720/8720 TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR Resets CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 GIEH GIEL PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000 PIE2 — CMIE — — BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000 IPR2 — CMIP — — BCLIP LVDIP TMR3IP CCP2IP -1-- 1111 -1-- 1111 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 x000 0000 u000 0000 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx uuuu uuuu TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. DS39609C-page 228  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 21.0 COMPARATOR VOLTAGE 21.1 Configuring the Comparator REFERENCE MODULE Voltage Reference The comparator voltage reference is a 16-tap resistor The comparator voltage reference can output 16 distinct ladder network that provides a selectable voltage refer- voltage levels for each range. The equations used to ence. The resistor ladder is segmented to provide two calculate the output of the comparator voltage reference ranges of CVREF values and has a power-down function are as follows: to conserve power when the reference is not being used. If CVRR = 1: The CVRCON register controls the operation of the CVREF=(CVR<3:0>/24) x CVRSRC reference as shown in Register21-1. The block diagram If CVRR = 0: is given in Figure21-1. CVREF=(CVRSRCx1/4)+(CVR<3:0>/32)xCVRSRC The comparator reference supply voltage can come The settling time of the comparator voltage reference from either VDD or VSS, or the external VREF+ and must be considered when changing the CVREF output VREF- that are multiplexed with RA3 and RA2. The (Section26.0 “Electrical Characteristics”). comparator reference supply voltage is controlled by the CVRSS bit. Note: In order to select external VREF+ and VREF- supply voltages, the Voltage Reference Con- figuration bits (VCFG1:VCFG0) of the ADCON1 register must be set appropriately. REGISTER 21-1: CVRCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0.00 CVRSRC to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit(2) 1 = Comparator reference source CVRSRC = VREF+ – VREF- 0 = Comparator reference source CVRSRC = VDD – VSS bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0  VR3:VR0  15) When CVRR = 1: CVREF = (CVR<3:0>/24)  (CVRSRC) When CVRR = 0: CVREF = 1/4  (CVRSRC) + (CVR3:CVR0/32)  (CVRSRC) Note1: If enabled for output, RF5 must also be configured as an input by setting TRISF<5> to ‘1’. 2: In order to select external VREF+ and VREF- supply voltages, the Voltage Reference Configuration bits (VCFG1:VCFG0) of the ADCON1 register must be set appropriately. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 229

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM VDD VREF+ CVRSS = 0 CVRSS = 1 16 Stages CVREN 8R R R R R CVRR 8R CVRSS = 0 CVRSS = 1 VREF- CVR3 CVREF 16-1 Analog Mux (From CVRCON<3:0>) CVR0 Note: R is defined in Section26.0 “Electrical Characteristics”. 21.2 Voltage Reference Accuracy/Error 21.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RA2 pin by clearing (Figure21-1) keep CVREF from approaching the refer- bit CVROE (CVRCON<6>) and selects the high- ence source rails. The voltage reference is derived voltage range by clearing bit CVRR (CVRCON<5>). from the reference source; therefore, the CVREF output The VRSS value select bits, CVRCON<3:0>, are also changes with fluctuations in that source. The tested cleared. absolute accuracy of the voltage reference can be found in Section26.0 “Electrical Characteristics”. 21.5 Connection Considerations 21.3 Operation During Sleep The voltage reference module operates independently of the comparator module. The output of the reference When the device wakes up from Sleep through an generator may be connected to the RF5 pin if the interrupt or a Watchdog Timer time-out, the contents of TRISF<5> bit is set and the CVROE bit is set. Enabling the CVRCON register are not affected. To minimize the voltage reference output onto the RF5 pin, current consumption in Sleep mode, the voltage configured as a digital input, will increase current reference should be disabled. consumption. Connecting RF5 as a digital output with VRSS enabled will also increase current consumption. The RF5 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage refer- ence output for external connections to VREF. Figure21-2 shows an example buffering technique. DS39609C-page 230  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE R(1) RF5 CVREF + Module CVREF Output – Voltage Reference Output Impedance Note 1: R is dependent upon the Comparator Voltage Reference Configuration bits CVRCON<3:0> and CVRCON<5>. TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR Resets CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.  2003-2013 Microchip Technology Inc. DS39609C-page 231

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 232  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 22.0 LOW-VOLTAGE DETECT The Low-Voltage Detect circuitry is completely under software control. This allows the circuitry to be “turned In many applications, the ability to determine if the off” by the software, which minimizes the current device voltage (VDD) is below a specified voltage level consumption for the device. is a desirable feature. A window of operation for the Figure22-1 shows a possible application voltage curve application can be created, where the application soft- (typically for batteries). Over time, the device voltage ware can do “housekeeping tasks” before the device decreases. When the device voltage equals voltage VA, voltage exits the valid operating range. This can be the LVD logic generates an interrupt. This occurs at done using the Low-Voltage Detect module. time TA. The application software then has the time, This module is a software programmable circuitry, until the device voltage is no longer in valid operating where a device voltage trip point can be specified. range, to shut down the system. Voltage point VB is the When the voltage of the device becomes lower then the minimum valid operating voltage specification. This specified point, an interrupt flag is set. If the interrupt is occurs at time TB. The difference TB – TA is the total enabled, the program execution will branch to the inter- time for shutdown. rupt vector address and the software can then respond to that interrupt source. FIGURE 22-1: TYPICAL LOW-VOLTAGE DETECT APPLICATION VA VB e g a t Vol Legend: VA = LVD trip point VB = Minimum valid device operating voltage Time TA TB The block diagram for the LVD module is shown in supply voltage is equal to the trip point, the voltage Figure22-2. A comparator uses an internally gener- tapped off of the resistor array is equal to the 1.2V ated reference voltage as the set point. When the internal reference voltage generated by the voltage ref- selected tap output of the device voltage crosses the erence module. The comparator then generates an set point (is lower than), the LVDIF bit is set. interrupt signal, setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Each node in the resistor divider represents a “trip Figure22-2). The trip point is selected by programming point” voltage. The “trip point” voltage is the minimum the LVDL3:LVDL0 bits (LVDCON<3:0>). supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the  2003-2013 Microchip Technology Inc. DS39609C-page 233

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 22-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM VDD LVDIN LVD3:LVD0 LVDCON Register X U M 1 o LVDIF 6 t 1 LVDEN Internally Generated Reference Voltage (Parameter #D423) The LVD module has an additional feature that allows LVDIN (Figure22-3). This gives users flexibility the user to supply the trip voltage to the module from because it allows them to configure the Low-Voltage an external source. This mode is enabled when bits Detect interrupt to occur at any voltage in the valid LVDL3:LVDL0 are set to ‘1111’. In this state, the com- operating range. parator input is multiplexed from the external input pin, FIGURE 22-3: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM VDD VDD LVD3:LVD0 LVDCON Register LVDIN UX LVDEN Externally Generated M Trip Point 1 o LVD 6 t 1 VxEN BODEN EN BGAP DS39609C-page 234  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 22.1 Control Register The Low-Voltage Detect Control register controls the operation of the Low-Voltage Detect circuitry. REGISTER 22-1: LVDCON REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled bit 4 LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits(2) 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.64V 1101 = 4.33V 1100 = 4.13V 1011 = 3.92V 1010 = 3.72V 1001 = 3.61V 1000 = 3.41V 0111 = 3.1V 0110 = 2.89V 0101 = 2.78V 0100 = 2.58V 0011 = 2.47V 0010 = 2.27V 0001 = 2.06V 0000 = Reserved Note1: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device are not tested. 2: Typical values shown, see parameter D420 in Table26-3 for more information. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS39609C-page 235

PIC18F6520/8520/6620/8620/6720/8720 22.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, 1. Write the value to the LVDL3:LVDL0 bits the voltage normally decreases relatively slowly. This (LVDCON register), which selects the desired means that the LVD module does not need to be con- LVD trip point. stantly operating. To decrease the current require- ments, the LVD circuitry only needs to be enabled for 2. Ensure that LVD interrupts are disabled (the short periods, where the voltage is checked. After LVDIE bit is cleared or the GIE bit is cleared). doing the check, the LVD module may be disabled. 3. Enable the LVD module (set the LVDEN bit in the LVDCON register). Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has 4. Wait for the LVD module to stabilize (the IRVST stabilized, all status flags may be cleared. The module bit to become set). will then indicate the proper state of the system. 5. Clear the LVD interrupt flag, which may have falsely become set, until the LVD module has stabilized (clear the LVDIF bit). 6. Enable the LVD interrupt (set the LVDIE and the GIE bits). Figure22-4 shows typical waveforms that the LVD module may be used to detect. FIGURE 22-4: LOW-VOLTAGE DETECT WAVEFORMS CASE 1: LVDIF may not be set VDD VLVD LVDIF Enable LVD Internally Generated TIVRST Reference Stable LVDIF cleared in software CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated TIVRST Reference Stable LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists DS39609C-page 236  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 22.2.1 REFERENCE VOLTAGE SET POINT 22.3 Operation During Sleep The internal reference voltage of the LVD module, When enabled, the LVD circuitry continues to operate specified in electrical specification parameter #D423, during Sleep. If the device voltage crosses the trip may be used by other internal circuitry (the point, the LVDIF bit will be set and the device will wake- Programmable Brown-out Reset). If these circuits are up from Sleep. Device execution will continue from the disabled (lower current consumption), the reference interrupt vector address if interrupts have been globally voltage circuit requires a time to become stable before a enabled. low-voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is 22.4 Effects of a Reset specified in electrical specification parameter #36. The low-voltage interrupt flag will not be enabled until a stable A device Reset forces all registers to their Reset state. reference voltage is reached. Refer to the waveform in This forces the LVD module to be turned off. Figure22-4. 22.2.2 CURRENT CONSUMPTION When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static cur- rent. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B.  2003-2013 Microchip Technology Inc. DS39609C-page 237

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 238  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 23.0 SPECIAL FEATURES OF THE 23.1 Configuration Bits CPU The configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select vari- There are several features intended to maximize sys- ous device configurations. These bits are mapped, tem reliability, minimize cost through elimination of starting at program memory location 300000h. external components, provide power saving operating modes and offer code protection. These are: The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the • Oscillator Selection configuration memory space (300000h through • Reset 3FFFFFh), which can only be accessed using table - Power-on Reset (POR) reads and table writes. - Power-up Timer (PWRT) Programming the configuration registers is done in a - Oscillator Start-up Timer (OST) manner similar to programming the Flash memory. The - Brown-out Reset (BOR) EECON1 register WR bit starts a self-timed write to the • Interrupts configuration register. In normal operation mode, a • Watchdog Timer (WDT) TBLWT instruction with the TBLPTR pointed to the configuration register sets up the address and the data • Sleep for the configuration register write. Setting the WR bit • Code Protection starts a long write to the configuration register. The • ID Locations configuration registers are written a byte at a time. To • In-Circuit Serial Programming write or erase a configuration cell, a TBLWT instruction can write a ‘1’ or a ‘0’ into the cell. All PIC18FXX20 devices have a Watchdog Timer, which is permanently enabled via the configuration bits, or software controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay on power-up only, designed to keep the part in Reset while the power supply stabilizes. With these two timers on-chip, most applications need no external Reset circuitry. Sleep mode is designed to offer a very low current power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits is used to select various options.  2003-2013 Microchip Technology Inc. DS39609C-page 239

PIC18F6520/8520/6620/8620/6720/8720 TABLE 23-1: CONFIGURATION BITS AND DEVICE IDS Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300001h CONFIG1H — — OSCSEN — — FOSC2 FOSC1 FOSC0 --1- -111 300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN ---- 1111 300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111 300004h(1) CONFIG3L WAIT — — — — — PM1 PM0 1--- --11 300005h CONFIG3H — — — — — — r(3) CCP2MX ---- --11 300006h CONFIG4L DEBUG — — — — LVP — STVREN 1--- -1-1 300008h CONFIG5L CP7(2) CP6(2) CP5(2) CP4(2) CP3 CP2 CP1 CP0 1111 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L WRT7(2) WRT6(2) WRT5(2) WRT4(2) WRT3 WRT2 WRT1 WRT0 1111 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L EBTR7(2) EBTR6(2) EBTR5(2) EBTR4(2) EBTR3 EBTR2 EBTR1 EBTR0 1111 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 (4) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0110 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition, r = reserved. Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18F6X20 devices; maintain this bit set. 2: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set. 3: Unimplemented in PIC18FX620 and PIC18FX720 devices; maintain this bit set. 4: See Register23-13 for DEVID1 values. REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-0 U-0 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 — — OSCSEN — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 OSCSEN: Oscillator System Clock Switch Enable bit 1 = Oscillator system clock switch option is disabled (main oscillator is source) 0 = Timer1 Oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 FOSC2:FOSC0: Oscillator Selection bits 111 = RC oscillator w/ OSC2 configured as RA6 110 = HS oscillator with PLL enabled; clock frequency = (4 x FOSC) 101 = EC oscillator w/ OSC2 configured as RA6 100 = EC oscillator w/ OSC2 configured as divide-by-4 clock output 011 = RC oscillator w/ OSC2 configured as divide-by-4 clock output 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS39609C-page 240  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOREN PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.5V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 1 BOREN: Brown-out Reset Enable bit 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 0 PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-1 WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state  2003-2013 Microchip Technology Inc. DS39609C-page 241

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1) R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT — — — — — PM1 PM0 bit 7 bit 0 bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections unavailable for table reads and table writes 0 = Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits (MEMCOM<5:4>) bit 6-2 Unimplemented: Read as ‘0’ bit 1-0 PM1:PM0: Processor Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode 01 = Microprocessor with Boot Block mode 00 = Extended Microcontroller mode Note1: This register is unimplemented in PIC18F6X20 devices; maintain these bits set. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 23-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 — — — — — — r(1) CCP2MX bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 Reserved: Read as unknown(1) bit 0 CCP2MX: CCP2 Mux bit In Microcontroller mode: 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RE7 In Microprocessor, Microprocessor with Boot Block and Extended Microcontroller modes (PIC18F8X20 devices only): 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 Note1: Unimplemented in PIC18FX620 and PIC18FX720 devices; read as ‘0’. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS39609C-page 242  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG — — — — LVP — STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. 0 = Background debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug. bit 6-3 Unimplemented: Read as ‘0’ bit 2 LVP: Low-Voltage ICSP Enable bit 1 = Low-voltage ICSP enabled 0 = Low-voltage ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state  2003-2013 Microchip Technology Inc. DS39609C-page 243

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP7(1) CP6(1) CP5(1) CP4(1) CP3 CP2 CP1 CP0 bit 7 bit 0 bit 7 CP7: Code Protection bit(1) 1 = Block 7 (01C000-01FFFFh) not code-protected 0 = Block 7 (01C000-01FFFFh) code-protected bit 6 CP6: Code Protection bit(1) 1 = Block 6 (018000-01BFFFh) not code-protected 0 = Block 6 (018000-01BFFFh) code-protected bit 5 CP5: Code Protection bit(1) 1 = Block 5 (014000-017FFFh) not code-protected 0 = Block 5 (014000-017FFFh) code-protected bit 4 CP4: Code Protection bit(1) 1 = Block 4 (010000-013FFFh) not code-protected 0 = Block 4 (010000-013FFFh) code-protected bit 3 CP3: Code Protection bit For PIC18FX520 devices: 1 = Block 3 (006000-007FFFh) not code-protected 0 = Block 3 (006000-007FFFh) code-protected For PIC18FX620 and PIC18FX720 devices: 1 = Block 3 (00C000-00FFFFh) not code-protected 0 = Block 3 (00C000-00FFFFh) code-protected bit 2 CP2: Code Protection bit For PIC18FX520 devices: 1 = Block 2 (004000-005FFFh) not code-protected 0 = Block 2 (004000-005FFFh) code-protected For PIC18FX620 and PIC18FX720 devices: 1 = Block 2 (008000-00BFFFh) not code-protected 0 = Block 2 (008000-00BFFFh) code-protected bit 1 CP1: Code Protection bit For PIC18FX520 devices: 1 = Block 1 (002000-003FFFh) not code-protected 0 = Block 1 (002000-003FFFh) code-protected For PIC18FX620 and PIC18FX720 devices: 1 = Block 1 (004000-007FFFh) not code-protected 0 = Block 1 (004000-007FFFh) code-protected bit 0 CP0: Code Protection bit For PIC18FX520 devices: 1 = Block 0 (000800-001FFFh) not code-protected 0 = Block 0 (000800-001FFFh) code-protected For PIC18FX620 and PIC18FX720 devices: 1 = Block 0 (000200-003FFFh) not code-protected 0 = Block 0 (000200-003FFFh) code-protected Note1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS39609C-page 244  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit For PIC18FX520 devices: 1 = Boot Block (000000-0007FFh) not code-protected 0 = Boot Block (000000-0007FFh) code-protected For PIC18FX620 and PIC18FX720 devices: 1 = Boot Block (000000-0001FFh) not code-protected 0 = Boot Block (000000-0001FFh) code-protected bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state  2003-2013 Microchip Technology Inc. DS39609C-page 245

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 WRT7(1) WRT6(1) WRT5(1) WRT4(1) WRT3 WRT2 WRT1 WRT0 bit 7 bit 0 bit 7 WR7: Write Protection bit(1) 1 = Block 7 (01C000-01FFFFh) not write-protected 0 = Block 7 (01C000-01FFFFh) write-protected bit 6 WR6: Write Protection bit(1) 1 = Block 6 (018000-01BFFFh) not write-protected 0 = Block 6 (018000-01BFFFh) write-protected bit 5 WR5: Write Protection bit(1) 1 = Block 5 (014000-017FFFh) not write-protected 0 = Block 5 (014000-017FFFh) write-protected bit 4 WR4: Write Protection bit(1) 1 = Block 4 (010000-013FFFh) not write-protected 0 = Block 4 (010000-013FFFh) write-protected bit 3 WR3: Write Protection bit For PIC18FX520 devices: 1 = Block 3 (006000-007FFFh) not write-protected 0 = Block 3 (006000-007FFFh) write-protected For PIC18FX620 and PIC18FX720 devices: 1 = Block 3 (00C000-00FFFFh) not write-protected 0 = Block 3 (00C000-00FFFFh) write-protected bit 2 WR2: Write Protection bit For PIC18FX520 devices: 1 = Block 2 (004000-005FFFh) not write-protected 0 = Block 2 (004000-005FFFh) write-protected For PIC18FX620 and PIC18FX720 devices: 1 = Block 2 (008000-00BFFFh) not write-protected 0 = Block 2 (008000-00BFFFh) write-protected bit 1 WR1: Write Protection bit For PIC18FX520 devices: 1 = Block 1 (002000-003FFFh) not write-protected 0 = Block 1 (002000-003FFFh) write-protected For PIC18FX620 and PIC18FX720 devices: 1 = Block 1 (004000-007FFFh) not write-protected 0 = Block 1 (004000-007FFFh) write-protected bit 0 WR0: Write Protection bit For PIC18FX520 devices: 1 = Block 0 (000800-001FFFh) not write-protected 0 = Block 0 (000800-001FFFh) write-protected For PIC18FX620 and PIC18FX720 devices: 1 = Block 0 (000200-003FFFh) not write-protected 0 = Block 0 (000200-003FFFh) write-protected Note1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS39609C-page 246  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/P-1 R/P-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit For PIC18FX520 devices: 1 = Boot Block (000000-0007FFh) not write-protected 0 = Boot Block (000000-0007FFh) write-protected For PIC18FX620 and PIC18FX720 devices: 1 = Boot Block (000000-0001FFh) not write-protected 0 = Boot Block (000000-0001FFh) write-protected bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected Note1: This bit is read-only and cannot be changed in user mode. bit 4-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state  2003-2013 Microchip Technology Inc. DS39609C-page 247

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 EBTR7(1) EBTR6(1) EBTR5(1) EBTR4(1) EBTR3 EBTR2 EBTR1 EBTR0 bit 7 bit 0 bit 7 EBTR7: Table Read Protection bit(1) 1 = Block 3 (01C000-01FFFFh) not protected from table reads executed in other blocks 0 = Block 3 (01C000-01FFFFh) protected from table reads executed in other blocks bit 6 EBTR6: Table Read Protection bit(1) 1 = Block 2 (018000-01BFFFh) not protected from table reads executed in other blocks 0 = Block 2 (018000-01BFFFh) protected from table reads executed in other blocks bit 5 EBTR5: Table Read Protection bit(1) 1 = Block 1 (014000-017FFFh) not protected from table reads executed in other blocks 0 = Block 1 (014000-017FFFh) protected from table reads executed in other blocks bit 4 EBTR4: Table Read Protection bit(1) 1 = Block 0 (010000-013FFFh) not protected from table reads executed in other blocks 0 = Block 0 (010000-013FFFh) protected from table reads executed in other blocks bit 3 EBTR3: Table Read Protection bit For PIC18FX520 devices: 1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks 0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks For PIC18FX620 and PIC18FX720 devices: 1 = Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks 0 = Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit For PIC18FX520 devices: 1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks 0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks For PIC18FX620 and PIC18FX720 devices: 1 = Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks 0 = Block 2 (008000-00BFFFh) protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit For PIC18FX520 devices: 1 = Block 1 (002000-003FFFh) not protected from table reads executed in other blocks 0 = Block 1 (002000-003FFFh) protected from table reads executed in other blocks For PIC18FX620 and PIC18FX720 devices: 1 = Block 1 (004000-007FFFh) not protected from table reads executed in other blocks 0 = Block 1 (004000-007FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit For PIC18FX520 devices: 1 = Block 0 (000800-001FFFh) not protected from table reads executed in other blocks 0 = Block 0 (000800-001FFFh) protected from table reads executed in other blocks For PIC18FX620 and PIC18FX720 devices: 1 = Block 0 (000200-003FFFh) not protected from table reads executed in other blocks 0 = Block 0 (000200-003FFFh) protected from table reads executed in other blocks Note1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS39609C-page 248  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/P-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit For PIC18FX520 devices: 1 = Boot Block (000000-0007FFh) not protected from table reads executed in other blocks 0 = Boot Block (000000-0007FFh) protected from table reads executed in other blocks For PIC18FX620 and PIC18FX720 devices: 1 = Boot Block (000000-0001FFh) not protected from table reads executed in other blocks 0 = Boot Block (000000-0001FFh) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 23-13: DEVICE ID REGISTER 1 FOR PIC18FXX20 DEVICES (ADDRESS 3FFFFEh) R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F8720 001 = PIC18F6720 010 = PIC18F8620 011 = PIC18F6620 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 23-14: DEVICE ID REGISTER 2 FOR PIC18FXX20 DEVICES (ADDRESS 3FFFFFh) R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state  2003-2013 Microchip Technology Inc. DS39609C-page 249

PIC18F6520/8520/6620/8620/6720/8720 23.2 Watchdog Timer (WDT) The WDT time-out period values may be found in the Electrical Specifications section under parameter #31. The Watchdog Timer is a free running, on-chip RC Values for the WDT postscaler may be assigned using oscillator, which does not require any external com- the configuration bits. ponents. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the Note1: The CLRWDT and SLEEP instructions WDT will run, even if the clock on the OSC1/CLKI and clear the WDT and the postscaler, if OSC2/CLKO/RA6 pins of the device has been stopped, assigned to the WDT and prevent it from for example, by execution of a SLEEP instruction. timing out and generating a device Reset condition. During normal operation, a WDT time-out generates a device Reset (Watchdog Timer Reset). If the device is 2: When a CLRWDT instruction is executed in Sleep mode, a WDT time-out causes the device to and the postscaler is assigned to the wake-up and continue with normal operation (Watch- WDT, the postscaler count will be cleared, dog Timer wake-up). The TO bit in the RCON register but the postscaler assignment is not will be cleared upon a WDT time-out. changed. The Watchdog Timer is enabled/disabled by a device 23.2.1 CONTROL REGISTER configuration bit. If the WDT is enabled, software exe- cution may not disable this function. When the WDTEN Register23-15 shows the WDTCON register. This is a configuration bit is cleared, the SWDTEN bit enables/ readable and writable register, which contains a control disables the operation of the WDT. bit that allows software to override the WDT enable configuration bit, only when the configuration bit has disabled the WDT. REGISTER 23-15: WDTCON REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN bit 7 bit 0 bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit 1 =Watchdog Timer is on 0 =Watchdog Timer is turned off if the WDTEN configuration bit in the configuration register = 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39609C-page 250  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 23.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming by the value written to the CONFIG2H Configuration register. FIGURE 23-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 8 8-to-1 MUX WDTPS2:WDTPS0 WDTEN SWDTEN bit Configuration bit WDT Time-out Note: WDPS2:WDPS0 are bits in register CONFIG2H. TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONFIG2H — — — — WDTPS2 WDTPS2 WDTPS0 WDTEN RCON IPEN — — RI TO PD POR BOR WDTCON — — — — — — — SWDTEN Legend: Shaded cells are not used by the Watchdog Timer.  2003-2013 Microchip Technology Inc. DS39609C-page 251

PIC18F6520/8520/6620/8620/6720/8720 23.3 Power-down Mode (Sleep) External MCLR Reset will cause a device Reset. All other events are considered a continuation of program Power-down mode is entered by executing a SLEEP execution and will cause a “wake-up”. The TO and PD instruction. bits in the RCON register can be used to determine the If enabled, the Watchdog Timer will be cleared, but cause of the device Reset. The PD bit, which is set on keeps running, the PD bit (RCON<3>) is cleared, the power-up, is cleared when Sleep is invoked. The TO bit TO (RCON<4>) bit is set and the oscillator driver is is cleared if a WDT time-out occurred (and caused turned off. The I/O ports maintain the status they had wake-up). before the SLEEP instruction was executed (driving When the SLEEP instruction is being executed, the next high, low or high-impedance). instruction (PC + 2) is prefetched. For the device to For lowest current consumption in this mode, place all wake-up through an interrupt event, the corresponding I/O pins at either VDD or VSS, ensure no external cir- interrupt enable bit must be set (enabled). Wake-up is cuitry is drawing current from the I/O pin, power-down regardless of the state of the GIE bit. If the GIE bit is the A/D and disable external clocks. Pull all I/O pins clear (disabled), the device continues execution at the that are high-impedance inputs, high or low externally, instruction after the SLEEP instruction. If the GIE bit is to avoid switching currents caused by floating inputs. set (enabled), the device executes the instruction after The T0CKI input should also be at VDD or VSS for low- the SLEEP instruction and then branches to the inter- est current consumption. The contribution from on-chip rupt address. In cases where the execution of the pull-ups on PORTB should be considered. instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The MCLR pin must be at a logic high level (VIHMC). 23.3.2 WAKE-UP USING INTERRUPTS 23.3.1 WAKE-UP FROM SLEEP When global interrupts are disabled (GIE cleared) and The device can wake-up from Sleep through one of the any interrupt source has both its interrupt enable bit following events: and interrupt flag bit set, one of the following will occur: 1. External Reset input on MCLR pin. • If an interrupt condition (interrupt flag bit and 2. Watchdog Timer Wake-up (if WDT was interrupt enable bits are set) occurs before the enabled). execution of a SLEEP instruction, the SLEEP 3. Interrupt from INT pin, RB port change or a instruction will complete as a NOP. Therefore, the peripheral interrupt. WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be The following peripheral interrupts can wake the device cleared. from Sleep: • If the interrupt condition occurs during or after 1. PSP read or write. the execution of a SLEEP instruction, the device 2. TMR1 interrupt. Timer1 must be operating as an will immediately wake-up from Sleep. The SLEEP asynchronous counter. instruction will be completely executed before the 3. TMR3 interrupt. Timer3 must be operating as an wake-up. Therefore, the WDT and WDT asynchronous counter. postscaler will be cleared, the TO bit will be set 4. CCP Capture mode interrupt. and the PD bit will be cleared. 5. Special event trigger (Timer1 in Asynchronous Even if the flag bits were checked before executing a mode using an external clock). SLEEP instruction, it may be possible for flag bits to 6. MSSP (Start/Stop) bit detect interrupt. become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test 7. MSSP transmit or receive in Slave mode (SPI/I2C). the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. 8. USART RX or TX (Synchronous Slave mode). 9. A/D conversion (when A/D clock source is RC). To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. 10. EEPROM write operation complete. 11. LVD interrupt. Other peripherals cannot generate interrupts, since during Sleep, no on-chip clocks are present. DS39609C-page 252  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 23-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKO(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency(3) GIEH bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC PC PC+2 PC+4 PC+4 PC + 4 0008h 000Ah Instruction Fetched Inst(PC) = Sleep Inst(PC + 2) Inst(PC + 4) Inst(0008h) Inst(000Ah) InEsxteruccuttieodn Inst(PC - 1) Sleep Inst(PC + 2) Dummy Cycle Dummy Cycle Inst(0008h) Note 1: XT, HS or LP Oscillator mode assumed. 2: GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. 3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes. 4: CLKO is not available in these oscillator modes, but shown here for timing reference. 23.4 Program Verification and In the PIC18FXX20 family, the block size varies with Code Protection the size of the user program memory. For PIC18FX520 devices, program memory is divided into four blocks of The overall structure of the code protection on the 8 Kbytes each. The first block is further divided into a PIC18 Flash devices differs significantly from other boot block of 2Kbytes and a second block (Block 0) of PIC® devices. The user program memory is divided on 6Kbytes, for a total of five blocks. The organization of binary boundaries into individual blocks, each of which the blocks and their associated code protection bits are has three separate code protection bits associated with shown in Figure23-3. it: For PIC18FX620 and PIC18FX720 devices, program • Code-Protect bit (CPn) memory is divided into blocks of 16 Kbytes. The first • Write-Protect bit (WRTn) block is further divided into a boot block of 512 bytes • External Block Table Read bit (EBTRn) and a second block (Block 0) of 15.5 Kbytes, for a total of nine blocks. This produces five blocks for 64-Kbyte The code protection bits are located in Configuration devices and nine for 128-Kbyte devices. The organiza- Registers 5L through 7H. Their locations within the tion of the blocks and their associated code protection registers are summarized in Table23-3. bits are shown in Figure23-4. TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L CP7(1) CP6(1) CP5(1) CP4(1) CP3 CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L WRT7(1) WRT6(1) WRT5(1) WRT4(1) WRT3 WRT2 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L EBTR7(1) EBTR6(1) EBTR5(1) EBTR4(1) EBTR3 EBTR2 EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices.  2003-2013 Microchip Technology Inc. DS39609C-page 253

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 23-3: CODE-PROTECTED PROGRAM MEMORY FOR PIC18FX520 DEVICES Address Block Code Protection 32Kbytes Range Controlled By: 000000h Boot Block CPB, WRTB, EBTRB 0007FFh 000800h Block 0 CP0, WRT0, EBTR0 001FFFh 002000h Block 1 CP1, WRT1, EBTR1 003FFFh 004000h Block 2 CP2, WRT2, EBTR2 005FFFh 006000h Block 3 CP3, WRT3, EBTR3 007FFFh 008000h Unimplemented Read ‘0’s 1FFFFFh FIGURE 23-4: CODE-PROTECTED PROGRAM MEMORY FOR PIC18FX620/X720 DEVICES MEMORY SIZE/DEVICE Block Code Protection 64Kbytes 128Kbytes Address Controlled By: (PIC18FX620) (PIC18FX720) Range 000000h Boot Block Boot Block CPB, WRTB, EBTRB 0001FFh 000200h Block 0 Block 0 CP0, WRT0, EBTR0 003FFFh 004000h Block 1 Block 1 CP1, WRT1, EBTR1 007FFFh 008000h Block 2 Block 2 CP2, WRT2, EBTR2 00BFFFh 00C000h Block 3 Block 3 CP3, WRT3, EBTR3 00FFFFh 010000h Block 4 CP4, WRT4, EBTR4 013FFFh 014000h Block 5 CP5, WRT5, EBTR5 Unimplemented 017FFFh Read ‘0’s 018000h Block 6 CP6, WRT6, EBTR6 01BFFFh 01C000h Block 7 CP7, WRT7, EBTR7 01FFFFh DS39609C-page 254  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 23.4.1 PROGRAM MEMORY side of that block is not allowed to read and will result CODE PROTECTION in reading ‘0’s. Figures23-5 through23-7 illustrate table write and table read protection using devices with The user memory may be read to, or written from, any a 16-Kbyte block size as the models. The principles location using the table read and table write instruc- illustrated are identical for devices with an 8-Kbyte tions. The device ID may be read with table reads. The block size. configuration registers may be read and written with the table read and table write instructions. Note: Code protection bits may only be written to a ‘0’ from a ‘1’ state. It is not possible to In user mode, the CPn bits have no direct effect. CPn write a ‘1’ to a bit in the ‘0’ state. Code pro- bits inhibit external reads and writes. A block of user tection bits are only set to ‘1’ by a full chip memory may be protected from table writes if the erase or block erase function. The full chip WRTn configuration bit is ‘0’. The EBTRn bits control erase and block erase functions can only table reads. For a block of user memory with the be initiated via ICSP or an external EBTRn bit set to ‘0’, a table read instruction that programmer. executes from within that block is allowed to read. A table read instruction that executes from a location out- FIGURE 23-5: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0001FFh 000200h TBLPTR = 000FFFh WRT0, EBTR0 = 01 PC = 003FFEh TBLWT * 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h PC = 008FFEh TBLWT * WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table writes disabled to Block n whenever WRTn = 0.  2003-2013 Microchip Technology Inc. DS39609C-page 255

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 23-6: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0001FFh 000200h TBLPTR = 000FFFh WRT0, EBTR0 = 10 003FFFh 004000h PC = 004FFEh TBLRD * WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Block n are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. FIGURE 23-7: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0001FFh 000200h TBLPTR = 000FFFh WRT0, EBTR0 = 10 PC = 003FFEh TBLRD * 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: Table reads permitted within Block n, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. DS39609C-page 256  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 23.4.2 DATA EEPROM TABLE 23-4: DEBUGGER RESOURCES CODE PROTECTION I/O pins RB6, RB7 The entire data EEPROM is protected from external Stack 2 levels reads and writes by two bits: CPD and WRTD. CPD Program Memory Last 576 bytes inhibits external reads and writes of data EEPROM. Data Memory Last 10 bytes WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM, To use the In-Circuit Debugger function of the micro- controller, the design must implement In-Circuit Serial regardless of the protection bit settings. Programming connections to MCLR/VPP, VDD, GND, 23.4.3 CONFIGURATION REGISTER RB7 and RB6. This will interface to the In-Circuit PROTECTION Debugger module available from Microchip or one of the third party development tool companies. The configuration registers can be write-protected. The WRTC bit controls protection of the configuration regis- 23.8 Low-Voltage ICSP Programming ters. In user mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external The LVP bit in the CONFIG4L Configuration register programmer. enables Low-Voltage ICSP Programming. This mode allows the microcontroller to be programmed via ICSP 23.5 ID Locations using a VDD source in the operating voltage range. This only means that VPP does not have to be brought to Eight memory locations (200000h-200007h) are VIHH, but can instead be left at the normal operating designated as ID locations, where the user can store voltage. In this mode, the RB5/PGM pin is dedicated to checksum or other code identification numbers. These the programming function and ceases to be a general locations are accessible during normal execution purpose I/O pin. During programming, VDD is applied to through the TBLRD and TBLWT instructions or during the MCLR/VPP pin. To enter Programming mode, VDD program/verify. The ID locations can be read when the must be applied to the RB5/PGM pin, provided the LVP device is code-protected. bit is set. The LVP bit defaults to a ‘1’ from the factory. 23.6 In-Circuit Serial Programming Note1: The High-Voltage Programming mode is always available, regardless of the state PIC18FX520/X620/X720 microcontrollers can be seri- of the LVP bit, by applying VIHH to the ally programmed while in the end application circuit. MCLR pin. This is simply done with two lines for clock and data 2: While in Low-Voltage ICSP mode, the and three other lines for power, ground and the RB5 pin can no longer be used as a programming voltage. This allows customers to manu- general purpose I/O pin and should be facture boards with unprogrammed devices and then held low during normal operation. program the microcontroller just before shipping the product. This also allows the most recent firmware or a 3: When using Low-Voltage ICSP Program- custom firmware to be programmed. ming (LVP) and the pull-ups on PORTB are enabled, bit 5 in the TRISB register must be Note: When performing In-Circuit Serial cleared to disable the pull-up on RB5 and Programming, verify that power is con- ensure the proper operation of the device. nected to all VDD and AVDD pins of the If Low-Voltage Programming mode is not used, the LVP microcontroller and that all VSS and AVSS bit can be programmed to a ‘0’ and RB5/PGM becomes pins are grounded. a digital I/O pin. However, the LVP bit may only be programmed when programming is entered with VIHH 23.7 In-Circuit Debugger on MCLR/VPP. It should be noted that once the LVP bit is programmed When the DEBUG bit in the CONFIG4L Configuration to ‘0’, only the High-Voltage Programming mode is register is programmed to a ‘0’, the In-Circuit Debugger available and only High-Voltage Programming mode functionality is enabled. This function allows simple debugging functions when used with MPLAB® IDE. can be used to program the device. When the microcontroller has this feature enabled, When using Low-Voltage ICSP Programming, the part some of the resources are not available for general must be supplied 4.5V to 5.5V if a bulk erase will be use. Table23-4 shows which features are consumed executed. This includes reprogramming of the code- by the background debugger. protect bits from an on state to an off state. For all other cases of Low-Voltage ICSP, the part may be programmed at the normal operating voltage. This means unique user IDs or user code can be reprogrammed or added.  2003-2013 Microchip Technology Inc. DS39609C-page 257

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 258  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 24.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: The PIC18 instruction set adds many enhancements to • A literal value to be loaded into a file register the previous PIC MCU instruction sets, while maintain- (specified by ‘k’) ing an easy migration from these PIC MCU instruction sets. • The desired FSR register to load the literal value into (specified by ‘f’) Most instructions are a single program memory word • No operand required (16 bits), but there are three instructions that require (specified by ‘—’) two program memory locations. The control instructions may use some of the following Each single-word instruction is a 16-bit word divided operands: into an opcode, which specifies the instruction type and one or more operands, which further specify the • A program memory address (specified by ‘n’) operation of the instruction. • The mode of the CALL or RETURN instructions The instruction set is highly orthogonal and is grouped (specified by ‘s’) into four basic categories: • The mode of the table read and table write instructions (specified by ‘m’) • Byte-oriented operations • No operand required • Bit-oriented operations (specified by ‘—’) • Literal operations All instructions are a single word, except for three • Control operations double-word instructions. These three instructions The PIC18 instruction set summary in Table24-1 lists were made double-word instructions so that all the byte-oriented, bit-oriented, literal and control required information is available in these 32 bits. In the operations. Table24-1 shows the opcode field second word, the 4 MSbs are ‘1’s. If this second word descriptions. is executed as an instruction (by itself), it will execute Most byte-oriented instructions have three operands: as a NOP. 1. The file register (specified by ‘f’) All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the 2. The destination of the result program counter is changed as a result of the instruc- (specified by ‘d’) tion. In these cases, the execution takes two instruction 3. The accessed memory cycles, with the additional instruction cycle(s) executed (specified by ‘a’) as a NOP. The file register designator ‘f’ specifies which file The double-word instructions execute in two instruction register is to be used by the instruction. cycles. The destination designator ‘d’ specifies where the One instruction cycle consists of four oscillator periods. result of the operation is to be placed. If ‘d’ is zero, the Thus, for an oscillator frequency of 4 MHz, the normal result is placed in the WREG register. If ‘d’ is one, the instruction execution time is 1 s. If a conditional test is result is placed in the file register specified in the true, or the program counter is changed as a result of instruction. an instruction, the instruction execution time is 2 s. All bit-oriented instructions have three operands: Two-word branch instructions (if true) would take 3 s. 1. The file register (specified by ‘f’) Figure24-1 shows the general formats that the 2. The bit in the file register instructions can have. (specified by ‘b’) All examples use the format ‘nnh’ to represent a hexa- 3. The accessed memory decimal number, where ‘h’ signifies a hexadecimal (specified by ‘a’) digit. The bit field designator ‘b’ selects the number of the bit The Instruction Set Summary, shown in Table24-1, affected by the operation, while the file register desig- lists the instructions recognized by the Microchip nator ‘f’ represents the number of the file in which the Assembler (MPASMTM). bit is located. Section24.1 “Instruction Set” provides a description of each instruction.  2003-2013 Microchip Technology Inc. DS39609C-page 259

PIC18F6520/8520/6620/8620/6720/8720 TABLE 24-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination either the WREG register or the specified register file location. f 8-bit Register file address (0x00 to 0xFF). fs 12-bit Register file address (0x000 to 0xFFF). This is the source address. fd 12-bit Register file address (0x000 to 0xFFF). This is the destination address. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No Change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions, or the direct address for Call/ Branch and Return instructions. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) u Unused or Unchanged. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TOS Top-of-Stack. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. GIE Global Interrupt Enable bit. WDT Watchdog Timer. TO Time-out bit. PD Power-down bit. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. [ ] Optional. ( ) Contents.  Assigned to. < > Register bit field.  In the set of. italics User defined term (font is courier). DS39609C-page 260  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 0x7F k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC  2003-2013 Microchip Technology Inc. DS39609C-page 261

PIC18F6520/8520/6620/8620/6720/8720 TABLE 24-1: PIC18FXXXX INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF f , f Movef (source) to 1st word 2 1100 ffff ffff ffff None s d s f (destination) 2nd word 1111 ffff ffff ffff d MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N 1, 2 RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N 1, 2 RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N 1, 2 borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N 1, 2 borrow SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39609C-page 262  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 24-1: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call subroutine1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software device Reset 1 0000 0000 1111 1111 All RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated.  2003-2013 Microchip Technology Inc. DS39609C-page 263

PIC18F6520/8520/6620/8620/6720/8720 TABLE 24-1: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit)2nd word 2 1110 1110 00ff kkkk None to FSRx 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY  PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 (5) 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39609C-page 264  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 24.1 Instruction Set ADDLW ADD literal to W ADDWF ADD W to f Syntax: [ label ] ADDLW k Syntax: [ label ] ADDWF f [,d [,a] f [,d [,a] Operands: 0  k  255 Operands: 0  f  255 Operation: (W) + k  W d  [0,1] a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f)  dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the 8-bit literal ‘k’ and the result is Encoding: 0010 01da ffff ffff placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). If ‘a’ is ‘0’, the Access Q Cycle Activity: Bank will be selected. If ‘a’ is ‘1’, Q1 Q2 Q3 Q4 the BSR is used. Decode Read Process Write to W Words: 1 literal ‘k’ Data Cycles: 1 Q Cycle Activity: Example: ADDLW 0x15 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write to W = 0x10 register ‘f’ Data destination After Instruction W = 0x25 Example: ADDWF REG, 0, 0 Before Instruction W = 0x17 REG = 0xC2 After Instruction W = 0xD9 REG = 0xC2  2003-2013 Microchip Technology Inc. DS39609C-page 265

PIC18F6520/8520/6620/8620/6720/8720 ADDWFC ADD W and Carry bit to f ANDLW AND literal with W Syntax: [ label ] ADDWFC f [,d [,a] Syntax: [ label ] ANDLW k Operands: 0  f  255 Operands: 0  k  255 d [0,1] Operation: (W) .AND. k  W a [0,1] Status Affected: N, Z Operation: (W) + (f) + (C)  dest Encoding: 0000 1011 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are AND’ed with Encoding: 0010 00da ffff ffff the 8-bit literal ‘k’. The result is Description: Add W, the Carry flag and data placed in W. memory location ‘f’. If ‘d’ is ‘0’, the Words: 1 result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory Cycles: 1 location ‘f’. If ‘a’ is ‘0’, the Access Q Cycle Activity: Bank will be selected. If ‘a’ is ‘1’, the Q1 Q2 Q3 Q4 BSR will not be overridden. Decode Read literal Process Write to W Words: 1 ‘k’ Data Cycles: 1 Example: ANDLW 0x5F Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 Decode Read Process Write to W = 0xA3 register ‘f’ Data destination After Instruction W = 0x03 Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 0x02 W = 0x4D After Instruction Carry bit = 0 REG = 0x02 W = 0x50 DS39609C-page 266  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 ANDWF AND W with f BC Branch if Carry Syntax: [ label ] ANDWF f [,d [,a] Syntax: [ label ] BC n Operands: 0  f  255 Operands: -128  n  127 d [0,1] Operation: if Carry bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: (W) .AND. (f)  dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ‘1’, then the Description: The contents of W are AND’ed with program will branch. register ‘f’. If ‘d’ is ‘0’, the result is The 2’s complement number ‘2n’ is stored in W. If ‘d’ is ‘1’, the result is added to the PC. Since the PC will stored back in register ‘f’ (default). have incremented to fetch the next If ‘a’ is ‘0’, the Access Bank will be instruction, the new address will be selected. If ‘a’ is ‘1’, the BSR will PC+2+2n. This instruction is then not be overridden (default). a two-cycle instruction. Words: 1 Words: 1 Cycles: 1 Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 If Jump: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read literal Process Write to PC ‘n’ Data Example: ANDWF REG, 0, 0 No No No No operation operation operation operation Before Instruction If No Jump: W = 0x17 Q1 Q2 Q3 Q4 REG = 0xC2 Decode Read literal Process No After Instruction ‘n’ Data operation W = 0x02 REG = 0xC2 Example: HERE BC 5 Before Instruction PC = address (HERE) After Instruction If Carry = 1; PC = address (HERE+12) If Carry = 0; PC = address (HERE+2)  2003-2013 Microchip Technology Inc. DS39609C-page 267

PIC18F6520/8520/6620/8620/6720/8720 BCF Bit Clear f BN Branch if Negative Syntax: [ label ] BCF f,b[,a] Syntax: [ label ] BN n Operands: 0  f  255 Operands: -128  n  127 0  b  7 Operation: if Negative bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: 0  f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ program will branch. is ‘0’, the Access Bank will be The 2’s complement number ‘2n’ is selected, overriding the BSR value. added to the PC. Since the PC will If ‘a’ = 1, then the bank will be have incremented to fetch the next selected as per the BSR value instruction, the new address will be (default). PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: If Jump: Decode Read Process Write register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Example: BCF FLAG_REG, 7, 0 ‘n’ Data No No No No Before Instruction operation operation operation operation FLAG_REG = 0xC7 If No Jump: After Instruction Q1 Q2 Q3 Q4 FLAG_REG = 0x47 Decode Read literal Process No ‘n’ Data operation Example: HERE BN Jump Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE+2) DS39609C-page 268  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC n Syntax: [ label ] BNN n Operands: -128  n  127 Operands: -128  n  127 Operation: if Carry bit is ‘0’ Operation: if Negative bit is ‘0’ (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the Description: If the Negative bit is ‘0’, then the program will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will added to the PC. Since the PC will have incremented to fetch the next have incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then PC+2+2n. This instruction is then a two-cycle instruction. a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE+2) PC = address (HERE+2)  2003-2013 Microchip Technology Inc. DS39609C-page 269

PIC18F6520/8520/6620/8620/6720/8720 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV n Syntax: [ label ] BNZ n Operands: -128  n  127 Operands: -128  n  127 Operation: if Overflow bit is ‘0’ Operation: if Zero bit is ‘0’ (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will added to the PC. Since the PC will have incremented to fetch the next have incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then PC+2+2n. This instruction is then a two-cycle instruction. a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE+2) PC = address (HERE+2) DS39609C-page 270  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA n Syntax: [ label ] BSF f,b[,a] Operands: -1024  n  1023 Operands: 0  f  255 0  b  7 Operation: (PC) + 2 + 2n  PC a [0,1] Status Affected: None Operation: 1  f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number Encoding: 1000 bbba ffff ffff ‘2n’ to the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’, instruction, the new address will be Access Bank will be selected, PC+2+2n. This instruction is a overriding the BSR value. If ‘a’ = 1, two-cycle instruction. then the bank will be selected as per the BSR value. Words: 1 Words: 1 Cycles: 2 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process Write to PC Q1 Q2 Q3 Q4 ‘n’ Data Decode Read Process Write No No No No register ‘f’ Data register ‘f’ operation operation operation operation Example: BSF FLAG_REG, 7, 1 Example: HERE BRA Jump Before Instruction FLAG_REG = 0x0A Before Instruction After Instruction PC = address (HERE) FLAG_REG = 0x8A After Instruction PC = address (Jump)  2003-2013 Microchip Technology Inc. DS39609C-page 271

PIC18F6520/8520/6620/8620/6720/8720 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0  f  255 Operands: 0  f  255 0  b  7 0  b < 7 a [0,1] a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. next instruction is skipped. If bit ‘b’ is ‘0’, then the next If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction fetched during the current instruction execution is discarded instruction execution is discarded and a NOP is executed instead, and a NOP is executed instead, making this a two-cycle instruction. If making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected ‘a’ = 1, then the bank will be selected as per the BSR value (default). as per the BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39609C-page 272  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV n Operands: 0  f  255 Operands: -128  n  127 0  b < 7 Operation: if Overflow bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: (f<b>)  f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. If ‘a’ is ‘0’, the Access Bank The 2’s complement number ‘2n’ is will be selected, overriding the BSR added to the PC. Since the PC will value. If ‘a’ = 1, then the bank will be have incremented to fetch the next selected as per the BSR value instruction, the new address will be (default). PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: If Jump: Decode Read Process Write register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Example: BTG PORTC, 4, 0 ‘n’ Data No No No No Before Instruction: operation operation operation operation PORTC = 0111 0101 [0x75] If No Jump: After Instruction: Q1 Q2 Q3 Q4 PORTC = 0110 0101 [0x65] Decode Read literal Process No ‘n’ Data operation Example: HERE BOV Jump Before Instruction PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE+2)  2003-2013 Microchip Technology Inc. DS39609C-page 273

PIC18F6520/8520/6620/8620/6720/8720 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ n Syntax: [ label ] CALL k [,s] Operands: -128  n  127 Operands: 0  k  1048575 s [0,1] Operation: if Zero bit is ‘1’ (PC) + 2 + 2n  PC Operation: (PC) + 4  TOS, k  PC<20:1>, Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (W)  WS, Description: If the Zero bit is ‘1’, then the (STATUS)  STATUSS, program will branch. (BSR)  BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will Encoding: have incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 PC+2+2n. This instruction is then 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 a two-cycle instruction. Description: Subroutine call of entire 2-Mbyte memory range. First, return Words: 1 address (PC+ 4) is pushed onto the Cycles: 1(2) return stack. If ‘s’ = 1, the W, Q Cycle Activity: Status and BSR registers are also If Jump: pushed into their respective shadow registers, WS, STATUSS Q1 Q2 Q3 Q4 and BSRS. If ‘s’ = 0, no update Decode Read literal Process Write to PC occurs (default). Then, the 20-bit ‘n’ Data value ‘k’ is loaded into PC<20:1>. No No No No CALL is a two-cycle instruction. operation operation operation operation If No Jump: Words: 2 Q1 Q2 Q3 Q4 Cycles: 2 Decode Read literal Process No Q Cycle Activity: ‘n’ Data operation Q1 Q2 Q3 Q4 Decode Read literal Push PC to Read literal Example: HERE BZ Jump ‘k’<7:0> stack ‘k’<19:8>, Before Instruction Write to PC PC = address (HERE) No No No No After Instruction operation operation operation operation If Zero = 1; PC = address (Jump) Example: HERE CALL THERE,1 If Zero = 0; PC = address (HERE+2) Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39609C-page 274  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRF f [,a] Syntax: [ label ] CLRWDT Operands: 0  f  255 Operands: None a [0,1] Operation: 000h  WDT, Operation: 000h  f 000h  WDT postscaler, 1  Z 1  TO, 1  PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Description: CLRWDT instruction resets the Bank will be selected, overriding Watchdog Timer. It also resets the the BSR value. If ‘a’ = 1, then the postscaler of the WDT. Status bits bank will be selected as per the TO and PD are set. BSR value (default). Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode No Process No Decode Read Process Write operation Data operation register ‘f’ Data register ‘f’ Example: CLRWDT Example: CLRF FLAG_REG,1 Before Instruction Before Instruction WDT Counter = ? FLAG_REG = 0x5A After Instruction After Instruction WDT Counter = 0x00 FLAG_REG = 0x00 WDT Postscaler = 0 TO = 1 PD = 1  2003-2013 Microchip Technology Inc. DS39609C-page 275

PIC18F6520/8520/6620/8620/6720/8720 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: [ label ] COMF f [,d [,a] Syntax: [ label ] CPFSEQ f [,a] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W), Operation: (f)  dest skip if (f) = (W) (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are com- plemented. If ‘d’ is ‘0’, the result is Description: Compares the contents of data stored in W. If ‘d’ is ‘1’, the result is memory location ‘f’ to the contents stored back in register ‘f’ (default). of W by performing an unsigned If ‘a’ is ‘0’, the Access Bank will be subtraction. selected, overriding the BSR value. If ‘f’ = W, then the fetched If ‘a’ = 1, then the bank will be instruction is discarded and a NOP selected as per the BSR value is executed instead, making this a (default). two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, Words: 1 overriding the BSR value. If ‘a’ = 1, Cycles: 1 then the bank will be selected as Q Cycle Activity: per the BSR value (default). Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1(2) register ‘f’ Data destination Note: 3 cycles if skip and followed Example: COMF REG, 0, 0 by a 2-word instruction. Before Instruction Q Cycle Activity: REG = 0x13 Q1 Q2 Q3 Q4 After Instruction Decode Read Process No REG = 0x13 register ‘f’ Data operation W = 0xEC If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG  W; PC = Address (NEQUAL) DS39609C-page 276  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: [ label ] CPFSGT f [,a] Syntax: [ label ] CPFSLT f [,a] Operands: 0  f  255 Operands: 0  f  255 a  [0,1] a  [0,1] Operation: (f) W), Operation: (f) –W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data Description: Compares the contents of data memory location ‘f’ to the contents memory location ‘f’ to the contents of W by performing an unsigned of W by performing an unsigned subtraction. subtraction. If the contents of ‘f’ are greater than If the contents of ‘f’ are less than the contents of WREG, then the the contents of W, then the fetched fetched instruction is discarded and instruction is discarded and a NOP a NOP is executed instead, making is executed instead, making this a this a two-cycle instruction. If ‘a’ is two-cycle instruction. If ‘a’ is ‘0’, the ‘0’, the Access Bank will be Access Bank will be selected. If ‘a’ selected, overriding the BSR value. is ‘1’, the BSR will not be If ‘a’ = 1, then the bank will be overridden (default). selected as per the BSR value Words: 1 (default). Cycles: 1(2) Words: 1 Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed Q Cycle Activity: by a 2-word instruction. Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process No Q1 Q2 Q3 Q4 register ‘f’ Data operation Decode Read Process No If skip: register ‘f’ Data operation Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSLT REG, 1 NLESS : Example: HERE CPFSGT REG, 0 LESS : NGREATER : Before Instruction GREATER : PC = Address (HERE) Before Instruction W = ? PC = Address (HERE) After Instruction W = ? If REG < W; After Instruction PC = Address (LESS) If REG  W; If REG  W; PC = Address (NLESS) PC = Address (GREATER) If REG  W; PC = Address (NGREATER)  2003-2013 Microchip Technology Inc. DS39609C-page 277

PIC18F6520/8520/6620/8620/6720/8720 DAW Decimal Adjust W Register DECF Decrement f Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a] Operands: None Operands: 0  f  255 d  [0,1] Operation: If [W<3:0> >9] or [DC = 1] then a  [0,1] (W<3:0>) + 6  W<3:0>; else Operation: (f) – 1  dest (W<3:0>)  W<3:0>; Status Affected: C, DC, N, OV, Z If [W<7:4> >9] or [C = 1] then Encoding: 0000 01da ffff ffff (W<7:4>) + 6  W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, else the result is stored in W. If ‘d’ is ‘1’, (W<7:4>)  W<7:4>; the result is stored back in register Status Affected: C ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding Encoding: 0000 0000 0000 0111 the BSR value. If ‘a’ = 1, then the Description: DAW adjusts the eight-bit value in bank will be selected as per the W, resulting from the earlier BSR value (default). addition of two variables (each in Words: 1 packed BCD format) and produces a correct packed BCD result. Cycles: 1 Words: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write Example: DECF CNT, 1, 0 register W Data W Before Instruction CNT = 0x01 Example1: DAW Z = 0 Before Instruction After Instruction W = 0xA5 CNT = 0x00 C = 0 Z = 1 DC = 0 After Instruction W = 0x05 C = 1 DC = 0 Example 2: Before Instruction W = 0xCE C = 0 DC = 0 After Instruction W = 0x34 C = 1 DC = 0 DS39609C-page 278  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ f [,d [,a] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – 1  dest, Operation: (f) – 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ is placed back in register ‘f’ (default). (default). If the result is ‘0’, the next If the result is not ‘0’, the next instruction which is already fetched instruction which is already fetched is discarded and a NOP is executed is discarded and a NOP is executed instead, making it a two-cycle instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the the BSR value. If ‘a’ = 1, then the bank will be selected as per the bank will be selected as per the BSR value (default). BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 Example: HERE DCFSNZ TEMP, 1, 0 GOTO LOOP ZERO : CONTINUE NZERO : Before Instruction Before Instruction PC = Address (HERE) TEMP = ? After Instruction After Instruction CNT = CNT - 1 TEMP = TEMP - 1, If CNT = 0; If TEMP = 0; PC = Address (CONTINUE) PC = Address (ZERO) If CNT  0; If TEMP  0; PC = Address (HERE+2) PC = Address (NZERO)  2003-2013 Microchip Technology Inc. DS39609C-page 279

PIC18F6520/8520/6620/8620/6720/8720 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] GOTO k Syntax: [ label ] INCF f [,d [,a] Operands: 0  k  1048575 Operands: 0  f  255 d  [0,1] Operation: k  PC<20:1> a  [0,1] Status Affected: None Operation: (f) + 1  dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 Encoding: 0010 10da ffff ffff Description: GOTO allows an unconditional Description: The contents of register ‘f’ are branch anywhere within the entire incremented. If ‘d’ is ‘0’, the result 2-Mbyte memory range. The 20-bit is placed in W. If ‘d’ is ‘1’, the result value ‘k’ is loaded into PC<20:1>. is placed back in register ‘f’ GOTO is always a two-cycle (default). If ‘a’ is ‘0’, the Access instruction. Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the Words: 2 bank will be selected as per the Cycles: 2 BSR value (default). Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal No Read literal Q Cycle Activity: ‘k’<7:0> operation ’k’<19:8>, Write to PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write to operation operation operation operation register ‘f’ Data destination Example: GOTO THERE Example: INCF CNT, 1, 0 After Instruction Before Instruction PC = Address (THERE) CNT = 0xFF Z = 0 C = ? DC = ? After Instruction CNT = 0x00 Z = 1 C = 1 DC = 1 DS39609C-page 280  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: [ label ] INCFSZ f [,d [,a] Syntax: [ label ] INFSNZ f [,d [,a] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) + 1  dest, Operation: (f) + 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0011 11da ffff ffff Encoding: 0100 10da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ is placed back in register ‘f’ (default). (default). If the result is ‘0’, the next If the result is not ‘0’, the next instruction which is already fetched instruction which is already fetched is discarded and a NOP is executed is discarded and a NOP is executed instead, making it a two-cycle instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the the BSR value. If ‘a’ = 1, then the bank will be selected as per the bank will be selected as per the BSR value (default). BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG  0; PC = Address (ZERO) PC = Address (NZERO) If CNT  0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO)  2003-2013 Microchip Technology Inc. DS39609C-page 281

PIC18F6520/8520/6620/8620/6720/8720 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: [ label ] IORLW k Syntax: [ label ] IORWF f [,d [,a] Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) .OR. k  W a  [0,1] Status Affected: N, Z Operation: (W) .OR. (f)  dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are OR’ed with Encoding: 0001 00da ffff ffff the eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If Words: 1 ‘d’ is ‘1’, the result is placed back in Cycles: 1 register ‘f’ (default). If ‘a’ is ‘0’, the Q Cycle Activity: Access Bank will be selected, over- Q1 Q2 Q3 Q4 riding the BSR value. If ‘a’ = 1, then the bank will be selected as per the Decode Read Process Write to W BSR value (default). literal ‘k’ Data Words: 1 Example: IORLW 0x35 Cycles: 1 Before Instruction Q Cycle Activity: W = 0x9A Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to register ‘f’ Data destination W = 0xBF Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93 DS39609C-page 282  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 LFSR Load FSR MOVF Move f Syntax: [ label ] LFSR f,k Syntax: [ label ] MOVF f [,d [,a] Operands: 0  f  2 Operands: 0  f  255 0  k  4095 d  [0,1] a  [0,1] Operation: k  FSRf Operation: f  dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k7kkk kkkk Encoding: 0101 00da ffff ffff Description: The 12-bit literal ‘k’ is loaded into Description: The contents of register ‘f’ are the File Select Register pointed moved to a destination dependent to by ‘f’. upon the status of ‘d’. If ‘d’ is ‘0’, the Words: 2 result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ Cycles: 2 (default). Location ‘f’ can be Q Cycle Activity: anywhere in the 256-byte bank. If Q1 Q2 Q3 Q4 ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. Decode Read literal Process Write literal ‘k’ MSB Data ‘k’ MSB to If ‘a’ = 1, then the bank will be FSRfH selected as per the BSR value Decode Read literal Process Write literal (default). ‘k’ LSB Data ‘k’ to FSRfL Words: 1 Cycles: 1 Example: LFSR 2, 0x3AB Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 FSR2H = 0x03 FSR2L = 0xAB Decode Read Process Write W register ‘f’ Data Example: MOVF REG, 0, 0 Before Instruction REG = 0x22 W = 0xFF After Instruction REG = 0x22 W = 0x22  2003-2013 Microchip Technology Inc. DS39609C-page 283

PIC18F6520/8520/6620/8620/6720/8720 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: [ label ] MOVFF f ,f Syntax: [ label ] MOVLB k s d Operands: 0  f  4095 Operands: 0  k  255 s 0  f  4095 d Operation: k  BSR Operation: (f )  f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The 8-bit literal ‘k’ is loaded into 1st word (source) 1100 ffff ffff ffffs the Bank Select Register (BSR). 2nd word (destin.) 1111 ffff ffff ffffd Words: 1 Description: The contents of source register ‘f ’ s are moved to destination register Cycles: 1 ‘fd’. Location of source ‘fs’ can be Q Cycle Activity: anywhere in the 4096-byte data Q1 Q2 Q3 Q4 space (000h to FFFh) and location Decode Read literal Process Write of destination ‘f ’ can also be d ‘k’ Data literal ‘k’ to anywhere from 000h to FFFh. BSR Either source or destination can be W (a useful special situation). Example: MOVLB 5 MOVFF is particularly useful for transferring a data memory location Before Instruction to a peripheral register (such as the BSR register = 0x02 transmit buffer or an I/O port). After Instruction The MOVFF instruction cannot use BSR register = 0x05 the PCL, TOSU, TOSH or TOSL as the destination register. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation, operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 0x33 REG2 = 0x11 After Instruction REG1 = 0x33, REG2 = 0x33 DS39609C-page 284  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 MOVLW Move literal to W MOVWF Move W to f Syntax: [ label ] MOVLW k Syntax: [ label ] MOVWF f [,a] Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: k  W Operation: (W)  f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Location ‘f’ can be anywhere in the Words: 1 256-byte bank. If ‘a’ is ‘0’, the Cycles: 1 Access Bank will be selected, Q Cycle Activity: overriding the BSR value. If ‘a’ = 1, then the bank will be selected as Q1 Q2 Q3 Q4 per the BSR value (default). Decode Read Process Write to W literal ‘k’ Data Words: 1 Cycles: 1 Example: MOVLW 0x5A Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = 0x5A Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 0x4F REG = 0xFF After Instruction W = 0x4F REG = 0x4F  2003-2013 Microchip Technology Inc. DS39609C-page 285

PIC18F6520/8520/6620/8620/6720/8720 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: [ label ] MULLW k Syntax: [ label ] MULWF f [,a] Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: (W) x k  PRODH:PRODL Operation: (W) x (f)  PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents Description An unsigned multiplication is of W and the 8-bit literal ‘k’. The carried out between the contents 16-bit result is placed in of W and the register file location PRODH:PRODL register pair. ‘f’. The 16-bit result is stored in PRODH contains the high byte. the PRODH:PRODL register W is unchanged. pair. PRODH contains the high None of the status flags are byte. affected. Both W and ‘f’ are unchanged. Note that neither overflow nor None of the status flags are carry is possible in this affected. operation. A zero result is Note that neither overflow nor possible but not detected. carry is possible in this operation. A zero result is Words: 1 possible but not detected. If ‘a’ is Cycles: 1 ‘0’, the Access Bank will be Q Cycle Activity: selected, overriding the BSR value. If ‘a’= 1, then the bank will Q1 Q2 Q3 Q4 be selected as per the BSR Decode Read Process Write value (default). literal ‘k’ Data registers PRODH: Words: 1 PRODL Cycles: 1 Q Cycle Activity: Example: MULLW 0xC4 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write W = 0xE2 register ‘f’ Data registers PRODH = ? PRODH: PRODL = ? PRODL After Instruction W = 0xE2 Example: MULWF REG, 1 PRODH = 0xAD PRODL = 0x08 Before Instruction W = 0xC4 REG = 0xB5 PRODH = ? PRODL = ? After Instruction W = 0xC4 REG = 0xB5 PRODH = 0x8A PRODL = 0x94 DS39609C-page 286  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 NEGF Negate f NOP No Operation Syntax: [ label ] NEGF f [,a] Syntax: [ label ] NOP Operands: 0  f  255 Operands: None a  [0,1] Operation: No operation Operation: (f) + 1  f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in Words: 1 the data memory location ‘f’. If ‘a’ is Cycles: 1 ‘0’, the Access Bank will be selected, overriding the BSR value. Q Cycle Activity: If ‘a’ = 1, then the bank will be Q1 Q2 Q3 Q4 selected as per the BSR value. Decode No No No Words: 1 operation operation operation Cycles: 1 Example: Q Cycle Activity: Q1 Q2 Q3 Q4 None. Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [0x3A] After Instruction REG = 1100 0110 [0xC6]  2003-2013 Microchip Technology Inc. DS39609C-page 287

PIC18F6520/8520/6620/8620/6720/8720 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] POP Syntax: [ label ] PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC+2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the Description: The PC+2 is pushed onto the top of return stack and is discarded. The the return stack. The previous TOS TOS value then becomes the value is pushed down on the stack. previous value that was pushed This instruction allows onto the return stack. implementing a software stack by This instruction is provided to modifying TOS and then pushing it enable the user to properly manage onto the return stack. the return stack to incorporate a Words: 1 software stack. Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode PUSH PC+2 No No Q1 Q2 Q3 Q4 onto return operation operation Decode No POP TOS No stack operation value operation Example: PUSH Example: POP Before Instruction GOTO NEW TOS = 00345Ah Before Instruction PC = 000124h TOS = 0031A2h Stack (1 level down) = 014332h After Instruction PC = 000126h After Instruction TOS = 000126h Stack (1 level down) = 00345Ah TOS = 014332h PC = NEW DS39609C-page 288  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 RCALL Relative Call RESET Reset Syntax: [ label ] RCALL n Syntax: [ label ] RESET Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, Operation: Reset all registers and flags that (PC) + 2 + 2n  PC are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to Description: This instruction provides a way to 1K from the current location. First, execute a MCLR Reset in software. return address (PC+2) is pushed Words: 1 onto the stack. Then, add the 2’s complement number ‘2n’ to the PC. Cycles: 1 Since the PC will have incremented Q Cycle Activity: to fetch the next instruction, the Q1 Q2 Q3 Q4 new address will be PC+2+2n. This Decode Start No No instruction is a two-cycle Reset operation operation instruction. Words: 1 Example: RESET Cycles: 2 After Instruction Q Cycle Activity: Registers= Reset Value Flags* = Reset Value Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC ‘n’ Data Push PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE+2)  2003-2013 Microchip Technology Inc. DS39609C-page 289

PIC18F6520/8520/6620/8620/6720/8720 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: [ label ] RETFIE [s] Syntax: [ label ] RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, Operation: k  W, 1  GIE/GIEH or PEIE/GIEL, (TOS)  PC, if s = 1 PCLATU, PCLATH are unchanged (WS)  W, Status Affected: None (STATUSS)  STATUS, (BSRS)  BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’. The program counter is loaded Status Affected: GIE/GIEH, PEIE/GIEL. from the top of the stack (the return Encoding: 0000 0000 0001 000s address). The high address latch Description: Return from Interrupt. Stack is (PCLATH) remains unchanged. popped and Top-of-Stack (TOS) is Words: 1 loaded into the PC. Interrupts are enabled by setting either the high Cycles: 2 or low priority global interrupt Q Cycle Activity: enable bit. If ‘s’ = 1, the contents of Q1 Q2 Q3 Q4 the shadow registers, WS, Decode Read Process Pop PC STATUSS and BSRS, are loaded literal ‘k’ Data from stack, into their corresponding registers, Write to W W, Status and BSR. If ‘s’ = 0, no No No No No update of these registers occurs operation operation operation operation (default). Words: 1 Example: Cycles: 2 CALL TABLE ; W contains table ; offset value Q Cycle Activity: ; W now has Q1 Q2 Q3 Q4 ; table value : Decode No No Pop PC TABLE operation operation from stack ADDWF PCL ; W = offset Set GIEH or RETLW k0 ; Begin table GIEL RETLW k1 ; No No No No : operation operation operation operation : RETLW kn ; End of table Example: RETFIE 1 Before Instruction After Interrupt W = 0x07 PC = TOS After Instruction W = WS BSR = BSRS W = value of kn STATUS = STATUSS GIE/GIEH, PEIE/GIEL = 1 DS39609C-page 290  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] RETURN [s] Syntax: [ label ] RLCF f [,d [,a] Operands: s  [0,1] Operands: 0  f  255 d  [0,1] Operation: (TOS)  PC, a  [0,1] if s = 1 (WS)  W, Operation: (f<n>)  dest<n+1>, (STATUSS)  STATUS, (f<7>)  C, (BSRS)  BSR, (C)  dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are Description: Return from subroutine. The stack rotated one bit to the left through is popped and the top of the stack the Carry flag. If ‘d’ is ‘0’, the result (TOS) is loaded into the program is placed in W. If ‘d’ is ‘1’, the result counter. If ‘s’ = 1, the contents of is stored back in register ‘f’ the shadow registers, WS, (default). If ‘a’ is ‘0’, the Access STATUSS and BSRS, are loaded Bank will be selected, overriding into their corresponding registers, the BSR value. If ‘a’ = 1, then the W, Status and BSR. If ‘s’ = 0, no bank will be selected as per the update of these registers occurs BSR value (default). (default). C register f Words: 1 Words: 1 Cycles: 2 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode No Process Pop PC Q1 Q2 Q3 Q4 operation Data from stack Decode Read Process Write to No No No No register ‘f’ Data destination operation operation operation operation Example: RLCF REG, 0, 0 Before Instruction Example: RETURN REG = 1110 0110 C = 0 After Interrupt After Instruction PC = TOS REG = 1110 0110 W = 1100 1100 C = 1  2003-2013 Microchip Technology Inc. DS39609C-page 291

PIC18F6520/8520/6620/8620/6720/8720 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] RLNCF f [,d [,a] Syntax: [ label ] RRCF f [,d [,a] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f<n>)  dest<n+1>, Operation: (f<n>)  dest<n-1>, (f<7>)  dest<0> (f<0>)  C, (C)  dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, Description: The contents of register ‘f’ are the result is placed in W. If ‘d’ is ‘1’, rotated one bit to the right through the result is stored back in register the Carry flag. If ‘d’ is ‘0’, the result ‘f’ (default). If ‘a’ is ‘0’, the Access is placed in W. If ‘d’ is ‘1’, the result Bank will be selected, overriding is placed back in register ‘f’ the BSR value. If ‘a’ is ‘1’, then the (default). If ‘a’ is ‘0’, the Access bank will be selected as per the Bank will be selected, overriding BSR value (default). the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the register f BSR value (default). Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to Example: RLNCF REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39609C-page 292  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] RRNCF f [,d [,a] Syntax: [ label ] SETF f [,a] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a [0,1] a  [0,1] Operation: FFh  f Operation: (f<n>)  dest<n-1>, Status Affected: None (f<0>)  dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified Encoding: 0100 00da ffff ffff register are set to FFh. If ‘a’ is ‘0’, Description: The contents of register ‘f’ are the Access Bank will be selected, rotated one bit to the right. If ‘d’ is overriding the BSR value. If ‘a’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, then the bank will be selected ‘1’, the result is placed back in as per the BSR value (default). register ‘f’ (default). If ‘a’ is ‘0’, the Words: 1 Access Bank will be selected, overriding the BSR value. If ‘a’ is Cycles: 1 ‘1’, then the bank will be selected Q Cycle Activity: as per the BSR value (default). Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction REG = 0x5A Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to REG = 0xFF register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111  2003-2013 Microchip Technology Inc. DS39609C-page 293

PIC18F6520/8520/6620/8620/6720/8720 SLEEP Enter SLEEP mode SUBFWB Subtract f from W with borrow Syntax: [ label ] SLEEP Syntax: [ label ] SUBFWB f [,d [,a] Operands: None Operands: 0 f 255 d  [0,1] Operation: 00h  WDT, a  [0,1] 0  WDT postscaler, 1  TO, Operation: (W) – (f) – (C) dest 0  PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit method). If ‘d’ is ‘0’, the result is (TO) is set. Watchdog Timer and stored in W. If ‘d’ is ‘1’, the result is its postscaler are cleared. stored in register ‘f’ (default). If ‘a’ is The processor is put into Sleep ‘0’, the Access Bank will be mode with the oscillator stopped. selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be Words: 1 selected as per the BSR value Cycles: 1 (default). Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode No Process Go to Q Cycle Activity: operation Data Sleep Q1 Q2 Q3 Q4 Example: SLEEP Decode Read Process Write to register ‘f’ Data destination Before Instruction TO = ? Example 1: SUBFWB REG, 1, 0 PD = ? Before Instruction After Instruction REG = 3 TO = 1 † W = 2 C = 1 PD = 0 After Instruction † If WDT causes wake-up, this bit is cleared. REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39609C-page 294  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF f [,d [,a] Operands: 0 k 255 Operands: 0 f 255 d  [0,1] Operation: k – (W) W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, Words: 1 the result is stored in W. If ‘d’ is Cycles: 1 ‘1’, the result is stored back in Q Cycle Activity: register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, Q1 Q2 Q3 Q4 overriding the BSR value. If ‘a’ is Decode Read Process Write to W ‘1’, then the bank will be selected literal ‘k’ Data as per the BSR value (default). Example 1: SUBLW 0x02 Words: 1 Before Instruction Cycles: 1 W = 1 C = ? Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = 1 Decode Read Process Write to C = 1 ; result is positive Z = 0 register ‘f’ Data destination N = 0 Example 1: SUBWF REG, 1, 0 Example 2: SUBLW 0x02 Before Instruction Before Instruction REG = 3 W = 2 W = 2 C = ? C = ? After Instruction After Instruction W = 0 REG = 1 C = 1 ; result is zero W = 2 Z = 1 C = 1 ; result is positive N = 0 Z = 0 N = 0 Example 3: SUBLW 0x02 Example 2: SUBWF REG, 0, 0 Before Instruction Before Instruction W = 3 C = ? REG = 2 W = 2 After Instruction C = ? W = FF ; (2’s complement) After Instruction C = 0 ; result is negative Z = 0 REG = 2 N = 1 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1  2003-2013 Microchip Technology Inc. DS39609C-page 295

PIC18F6520/8520/6620/8620/6720/8720 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: [ label ] SUBWFB f [,d [,a] Syntax: [ label ] SWAPF f [,d [,a] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: (f<3:0>)  dest<7:4>, (f<7:4>)  dest<3:0> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0101 10da ffff ffff Encoding: 0011 10da ffff ffff Description: Subtract W and the Carry flag (borrow) from register ‘f’ (2’s com- Description: The upper and lower nibbles of plement method). If ‘d’ is ‘0’, the register ‘f’ are exchanged. If ‘d’ is result is stored in W. If ‘d’ is ‘1’, the ‘0’, the result is placed in W. If ‘d’ is result is stored back in register ‘f’ ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the Bank will be selected, overriding BSR value. If ‘a’ is ‘1’, then the bank the BSR value. If ‘a’ is ‘1’, then the will be selected as per the BSR bank will be selected as per the value (default). BSR value (default). Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination Example 1: SUBWFB REG, 1, 0 Example: SWAPF REG, 1, 0 Before Instruction Before Instruction REG = 0x19 (0001 1001) W = 0x0D (0000 1101) REG = 0x53 C = 1 After Instruction After Instruction REG = 0x35 REG = 0x0C (0000 1011) W = 0x0D (0000 1101) C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 0x1B (0001 1011) W = 0x1A (0001 1010) C = 0 After Instruction REG = 0x1B (0001 1011) W = 0x00 C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 0x03 (0000 0011) W = 0x0E (0000 1101) C = 1 After Instruction REG = 0xF5 (1111 0100) ; [2’s comp] W = 0x0E (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39609C-page 296  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TBLRD Table Read TBLRD Table Read (Continued) Syntax: [ label ] TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 0x55 Operation: if TBLRD *, TBLPTR = 0x00A356 (Prog Mem (TBLPTR))  TABLAT; MEMORY(0x00A356) = 0x34 TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 0x34 (Prog Mem (TBLPTR))  TABLAT; TBLPTR = 0x00A357 (TBLPTR) + 1  TBLPTR; Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR))  TABLAT; Before Instruction (TBLPTR) – 1  TBLPTR; TABLAT = 0xAA if TBLRD +*, TBLPTR = 0x01A357 (TBLPTR) + 1  TBLPTR; MEMORY(0x01A357) = 0x12 (Prog Mem (TBLPTR))  TABLAT; MEMORY(0x01A358) = 0x34 After Instruction Status Affected:None TABLAT = 0x34 Encoding: 0000 0000 0000 10nn TBLPTR = 0x01A358 nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the Program Memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write TABLAT) Memory)  2003-2013 Microchip Technology Inc. DS39609C-page 297

PIC18F6520/8520/6620/8620/6720/8720 TBLWT Table Write TBLWT Table Write (Continued) Syntax: [ label ] TBLWT ( *; *+; *-; +*) Words: 1 Operands: None Cycles: 2 Operation: if TBLWT*, Q Cycle Activity: (TABLAT)  Holding Register; Q1 Q2 Q3 Q4 TBLPTR – No Change; if TBLWT*+, Decode No No No (TABLAT)  Holding Register; operation operation operation (TBLPTR) + 1  TBLPTR; No No No No if TBLWT*-, operation operation operation operation (TABLAT)  Holding Register; (Read (Write to (TBLPTR) – 1  TBLPTR; TABLAT) Holding if TBLWT+*, Register ) (TBLPTR) + 1  TBLPTR; (TABLAT)  Holding Register; Example 1: TBLWT *+; Status Affected: None Before Instruction Encoding: 0000 0000 0000 11nn TABLAT = 0x55 nn=0 * TBLPTR = 0x00A356 =1 *+ HOLDING REGISTER =2 *- (0x00A356) = 0xFF =3 +* After Instructions (table write completion) Description: This instruction uses the 3 LSBs of TABLAT = 0x55 TBLPTR = 0x00A357 TBLPTR to determine which of the HOLDING REGISTER 8 holding registers the TABLAT is (0x00A356) = 0x55 written to. The holding registers are Example 2: TBLWT +*; used to program the contents of Program Memory (P.M.). (Refer Before Instruction to Section5.0 “Flash Program TABLAT = 0x34 TBLPTR = 0x01389A Memory” for additional details on HOLDING REGISTER programming Flash memory.) (0x01389A) = 0xFF HOLDING REGISTER The TBLPTR (a 21-bit pointer) points (0x01389B) = 0xFF to each byte in the Program Memory. After Instruction (table write completion) TBLPTR has a 2-Mbyte address TABLAT = 0x34 range. The LSb of the TBLPTR TBLPTR = 0x01389B selects which byte of the program HOLDING REGISTER (0x01389A) = 0xFF memory location to access. HOLDING REGISTER TBLPTR[0] = 0:Least Significant (0x01389B) = 0x34 Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment DS39609C-page 298  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0  f  255 Operands: 0 k 255 a  [0,1] Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XOR’ed Description: If ‘f’ = 0, the next instruction, with the 8-bit literal ‘k’. The result fetched during the current is placed in W. instruction execution is discarded Words: 1 and a NOP is executed, making this a two-cycle instruction. If ‘a’ is ‘0’, Cycles: 1 the Access Bank will be selected, Q Cycle Activity: overriding the BSR value. If ‘a’ is Q1 Q2 Q3 Q4 ‘1’, then the bank will be selected Decode Read Process Write to W as per the BSR value (default). literal ‘k’ Data Words: 1 Cycles: 1(2) Example: XORLW 0xAF Note: 3 cycles if skip and followed Before Instruction by a 2-word instruction. W = 0xB5 Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = 0x1A Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 0x00, PC = Address (ZERO) If CNT  0x00, PC = Address (NZERO)  2003-2013 Microchip Technology Inc. DS39609C-page 299

PIC18F6520/8520/6620/8620/6720/8720 XORWF Exclusive OR W with f Syntax: [ label ] XORWF f [,d [,a] Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 DS39609C-page 300  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 25.0 DEVELOPMENT SUPPORT 25.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C® for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2003-2013 Microchip Technology Inc. DS39609C-page 301

PIC18F6520/8520/6620/8620/6720/8720 25.2 MPLAB C Compilers for Various 25.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 25.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 25.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 25.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS39609C-page 302  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 25.7 MPLAB SIM Software Simulator 25.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 25.10 PICkit 3 In-Circuit Debugger/ Programmer and 25.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2003-2013 Microchip Technology Inc. DS39609C-page 303

PIC18F6520/8520/6620/8620/6720/8720 25.11 PICkit 2 Development 25.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 25.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39609C-page 304  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 26.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Voltage on RA4 with respect to Vss...............................................................................................................0V to +8.5V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)20mA Output clamp current, IOK (VO < 0 or VO > VDD)20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk byall ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2003-2013 Microchip Technology Inc. DS39609C-page 305

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-1: PIC18F6520/8520 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V 5.0V PIC18FX520 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V FMAX (Extended) FMAX Frequency FMAX = 40 MHz for PIC18F6520/8520 in Microcontroller mode. FMAX (Extended) = 25 MHz for PIC18F6520/8520 in modes other than Microcontroller mode. FIGURE 26-2: PIC18LF6520/8520 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LFX520 4.5V e g 4.2V 4.0V a t l o 3.5V V 3.0V 2.5V 2.0V 4 MHz FMAX Frequency For PIC18F6520/8520 in Microcontroller mode: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN  4.2V; FMAX = 40 MHz, if VDDAPPMIN > 4.2V. For PIC18F8X8X in modes other than Microcontroller mode: FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN  4.2V; FMAX = 25 MHz, if VDDAPPMIN > 4.2V. Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. DS39609C-page 306  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-3: PIC18F6620/6720/8620/8720 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V 5.0V PIC18FX620/X720 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V FMAX (Extended) FMAX Frequency FMAX = 25 MHz in Microcontroller mode. FMAX (Extended) = 16 MHz for PIC18F6520/8520 in modes other than Microcontroller mode. FIGURE 26-4: PIC18LF6620/6720/8620/8720 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LFX620/X720 4.5V e g 4.2V 4.0V a t l o 3.5V V 3.0V 2.5V 2.0V 4 MHz FMAX Frequency In Microcontroller mode: FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN  4.2V; FMAX = 25 MHz, if VDDAPPMIN > 4.2V. In modes other than Microcontroller mode: FMAX = (5.45 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN  4.2V; FMAX = 16 MHz, if VDDAPPMIN > 4.2V. Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.  2003-2013 Microchip Technology Inc. DS39609C-page 307

PIC18F6520/8520/6620/8620/6720/8720 26.1 DC Characteristics: Supply Voltage PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6520/8520/6620/8620/6720/8720 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage PIC18LFXX20 2.0 — 5.5 V HS, XT, RC and LP Oscillator mode PIC18FXX20 4.2 — 5.5 V D001A AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See section on Power-on Reset for details to ensure internal Power-on Reset signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See section on Power-on Reset for details to ensure internal Power-on Reset signal D005 VBOR Brown-out Reset Voltage BORV1:BORV0 = 11 N/A — N/A V Reserved BORV1:BORV0 = 10 2.64 — 2.92 V BORV1:BORV0 = 01 4.11 — 4.55 V BORV1:BORV0 = 00 4.41 — 4.87 V Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. DS39609C-page 308  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6520/8520/6620/8620/6720/8720 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Power-down Current (IPD)(1) PIC18LFXX20 0.2 1 A -40°C VDD = 2.0V, 0.2 1 A +25°C (Sleep mode) 1.2 5 A +85°C PIC18LFXX20 0.4 1 A -40°C VDD = 3.0V, 0.4 1 A +25°C (Sleep mode) 1.8 8 A +85°C All devices 0.7 2 A -40°C VDD = 5.0V, 0.7 2 A +25°C (Sleep mode) 3.0 15 A +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.  2003-2013 Microchip Technology Inc. DS39609C-page 309

PIC18F6520/8520/6620/8620/6720/8720 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued) PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6520/8520/6620/8620/6720/8720 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LFXX20 165 350 A -40°C 165 350 A +25°C VDD = 2.0V 170 350 A +85°C PIC18LFXX20 360 750 A -40°C FOSC = 1MHZ, 340 750 A +25°C VDD = 3.0V EC oscillator 300 750 A +85°C All devices 800 1700 A -40°C 730 1700 A +25°C VDD = 5.0V 700 1700 A +85°C PIC18LFXX20 600 1200 A -40°C 600 1200 A +25°C VDD = 2.0V 640 1300 A +85°C PIC18LFXX20 1000 2500 A -40°C FOSC = 4MHz, 1000 2500 A +25°C VDD = 3.0V EC oscillator 1000 2500 A +85°C All devices 2.2 5.0 mA -40°C 2.1 5.0 mA +25°C VDD = 5.0V 2.0 5.0 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. DS39609C-page 310  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued) PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6520/8520/6620/8620/6720/8720 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18FX620, PIC18FX720 9.3 15 mA -40°C 9.5 15 mA +25°C VDD = 4.2V 10 15 mA +85°C FOSC = 25MHZ, PIC18FX620, PIC18FX720 11.8 20 mA -40°C EC oscillator 12 20 mA +25°C VDD = 5.0V 12 20 mA +85°C PIC18FX520 16 20 mA -40°C 16 20 mA +25°C VDD = 4.2V 16 20 mA +85°C FOSC = 40MHZ, PIC18FX520 19 25 mA -40°C EC oscillator 19 25 mA +25°C VDD = 5.0V 19 25 mA +85°C D014 PIC18FX620/X720 15 55 A -40°C to +85°C VDD = 2.0V FOSC = 32kHz, Timer1 as clock PIC18LF8520 13 18 A -40°C to +85°C VDD = 2.0V FOSC = 32kHz, 20 35 A -40°C to +85°C VDD = 3.0V Timer1 as clock 50 85 A -40°C to +85°C VDD = 5.0V PIC18FXX20 — 200 A -40°C to +85°C VDD = 4.2V FOSC = 32kHz, — 250 A -40°C to +125°C VDD = 4.2V Timer1 as clock Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.  2003-2013 Microchip Technology Inc. DS39609C-page 311

PIC18F6520/8520/6620/8620/6720/8720 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued) PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6520/8520/6620/8620/6720/8720 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) D022 Watchdog Timer <1 2.0 A -40C (IWDT) <1 1.5 A +25C VDD = 2.0V <1 3 A +85C 3 10 A -40C 2.5 6 A +25C VDD = 3.0V 3 15 A +85C 15 25 A -40C 12 20 A +25C VDD = 5.0V 12 40 A +85C D022A Brown-out Reset 35 50 A -40C to +85C VDD = 3.0V (IBOR) 45 65 A -40C to +85C VDD = 5.0V D022B Low-Voltage Detect 33 45 A -40C to +85C VDD = 2.0V (ILVD) 35 50 A -40C to +85C VDD = 3.0V 45 65 A -40C to +85C VDD = 5.0V D025 Timer1 Oscillator 5.2 30 A +25C VDD = 2.0V (IOSCB) PIC18LF8720/8620 5.2 40 A -40C to +85C VDD = 2.0V 32kHz on Timer1 6.5 50 A -40C to +125C VDD = 4.2V PIC18F8520/8620/8720 6.5 40 A +25C 6.5 50 A -40C to +85C VDD = 4.2V 32kHz on Timer1 6.5 65 A -40C to +125C PIC18LF8520 1.8 2.2 A +25C VDD = 2.0V 2.9 3.8 A -40C to +85C VDD = 3.0V 32kHz on Timer1 3.4 7.0 A -40C to +125C VDD = 5.0V D026 A/D Converter <1 2 A +25C VDD = 2.0V (IAD) <1 2 A +25C VDD = 3.0V A/D on, not converting. Device is in Sleep. <1 2 A +25C VDD = 5.0V Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. DS39609C-page 312  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 26.3 DC Characteristics: PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended Param Sym Characteristic Min Max Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS 0.15 VDD V VDD < 4.5V D030A — 0.8 V 4.5V  VDD 5.5V D031 with Schmitt Trigger buffer VSS 0.2 VDD V RC3 and RC4 VSS 0.3 VDD V D032 MCLR VSS 0.2 VDD V D032A OSC1 (in XT, HS and LP modes) VSS 0.2 VDD V and T1OSI D033 OSC1 (in RC and EC mode)(1) VSS 0.2 VDD V VIH Input High Voltage I/O ports: D040 with TTL buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V D040A 2.0 VDD V 4.5V  VDD 5.5V D041 with Schmitt Trigger buffer 0.8 VDD VDD V RC3 and RC4 0.7 VDD VDD V D042 MCLR, OSC1 (EC mode) 0.8 VDD VDD V D042A OSC1 and T1OSI 1.6 VDD V LP, XT, HS, HSPLL modes(1) D043 OSC1 (RC mode)(1) 0.9 VDD VDD V IIL Input Leakage Current(2,3) D060 I/O ports — 1 A VSS VPIN VDD, Pin at high-impedance D061 MCLR — 5 A VSS VPIN VDD D063 OSC1 — 5 A VSS VPIN VDD IPU Weak Pull-up Current D070 IPURB PORTB weak pull-up current 50 400 A VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested.  2003-2013 Microchip Technology Inc. DS39609C-page 313

PIC18F6520/8520/6620/8620/6720/8720 26.3 DC Characteristics: PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended Param Sym Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D080A — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC mode) -40C to +85C D083A — 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C VOH Output High Voltage(3) D090 I/O ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D090A VDD – 0.7 — V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, (RC mode) -40C to +85C D092A VDD – 0.7 — V IOH = -1.0 mA, VDD = 4.5V, -40C to +125C D150 VOD Open-Drain High Voltage — 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 — 50 pF To meet the AC Timing (in RC mode) Specifications D102 CB SCL, SDA — 400 pF In I2C mode Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. DS39609C-page 314  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-1: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB 300 TRESP Response Time(1) — 150 400 ns PIC18FXX20 300A 600 ns PIC18LFXX20 301 TMC2OV Comparator Mode Change to — — 10 s Output Valid Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 26-2: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/4 LSb Low Range (VRR = 1) — — 1/2 LSb High Range (VRR = 0) D312 VRUR Unit Resistor Value (R) — 2k —  310 TSET Settling Time(1) — — 10 s Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.  2003-2013 Microchip Technology Inc. DS39609C-page 315

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-5: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be VLVD cleared in software) (LVDIF set by hardware) LVDIF TABLE 26-3: LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. D420 LVD Voltage on VDD LVV = 0001 1.96 2.06 2.16 V Transition high-to-low LVV = 0010 2.16 2.27 2.38 V LVV = 0011 2.35 2.47 2.59 V LVV = 0100 2.45 2.58 2.71 V LVV = 0101 2.64 2.78 2.92 V LVV = 0110 2.75 2.89 3.03 V LVV = 0111 2.95 3.1 3.26 V LVV = 1000 3.24 3.41 3.58 V LVV = 1001 3.43 3.61 3.79 V LVV = 1010 3.53 3.72 3.91 V LVV = 1011 3.72 3.92 4.12 V LVV = 1100 3.92 4.13 4.34 V LVV = 1101 4.11 4.33 4.55 V LVV = 1110 4.41 4.64 4.87 V D423 VBG Band Gap Reference Voltage Value — 1.22 — V † Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization. DS39609C-page 316  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-4: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC Characteristics Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Internal Program Memory Programming Specifications (Note 1) D110 VPP Voltage on MCLR/VPP pin 9.00 — 13.25 V (Note 2) D112 IPP Current into MCLR/VPP pin — — 5 A D113 IDDP Supply Current during — — 10 mA Programming Data EEPROM Memory D120 ED Cell Endurance 100K 1M — E/W -40C to +85C D120A ED Cell Endurance 10K 100K — E/W +85C to +125C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year -40C to +85C (Note 3) D123A TRETD Characteristic Retention 100 — — Year 25C (Note 3) Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40C to +85C D130A EP Cell Endurance 1000 10K — E/W +85C to +125C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP port D132A VIW VDD for Externally Timed Erase 4.5 — 5.5 V Using ICSP port or Write D132B VPEW VDD for Self-Timed Write VMIN — 5.5 V VMIN = Minimum operating voltage D133 TIE ICSP Block Erase Cycle Time — 5 — ms VDD > 4.5V D133A TIW ICSP Erase or Write Cycle Time 1 — — ms VDD > 4.5V (externally timed) D133A TIW Self-Timed Write Cycle Time — 2.5 — ms D134 TRETD Characteristic Retention 40 — — Year -40C to +85C (Note 3) D134A TRETD Characteristic Retention 100 — — Year 25C (Note 3) † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: The pin may be kept in this range at times other than programming, but it is not recommended. 3: Retention time is valid, provided no other specifications are violated.  2003-2013 Microchip Technology Inc. DS39609C-page 317

PIC18F6520/8520/6620/8620/6720/8720 26.4 AC (Timing) Characteristics 26.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-Impedance) V Valid L Low Z High-Impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS39609C-page 318  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 26.4.2 TIMING CONDITIONS The temperature and voltages specified in Table26-5 apply to all timing specifications unless otherwise noted. Figure26-6 specifies the load conditions for the timing specifications. TABLE 26-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA +85°C for industrial -40°C  TA +125°C for extended AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section26.1 and Section26.3. LC parts operate for industrial temperatures only. FIGURE 26-6: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports  2003-2013 Microchip Technology Inc. DS39609C-page 319

PIC18F6520/8520/6620/8620/6720/8720 26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-7: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 25 MHz EC, ECIO, PIC18FX620/X720 (-40°C to +85°C) DC 40 MHz EC, ECIO, PIC18FX520 (-40°C to +85°C) DC 25 MHz EC, ECIO, PIC18FX520 using external memory interface (-40°C to +85°C) Oscillator Frequency(1) DC 4 MHz RC oscillator 0.1 4 MHz XT oscillator 4 25 MHz HS oscillator 4 10 MHz HS + PLL oscillator, PIC18FX520 6 6.25 MHz HS + PLL oscillator, PIC18FX520 using external memory interface 4 6.25 MHz HS + PLL oscillator, PIC18FX620/X720 5 200 kHz LP Oscillator mode 1 TOSC External CLKI Period(1) 25 — ns EC, ECIO, PIC18FX620/X720 (-40°C to +85°C) 160 — ns EC, ECIO, PIC18FX520 (-40°C to +85°C) Oscillator Period(1) 250 — ns RC oscillator 250 10,000 ns XT oscillator 25 250 ns HS oscillator 100 250 ns HS + PLL oscillator, PIC18FX520 100 160 ns HS + PLL oscillator, PIC18FX620/X720 25 — s LP oscillator 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC 3 TOSL, External Clock in (OSC1) 30 — ns XT oscillator TOSH High or Low Time 2.5 — s LP oscillator 10 — ns HS oscillator 4 TOSR, External Clock in (OSC1) Rise — 20 ns XT oscillator TOSF or Fall Time — 50 ns LP oscillator — 7.5 ns HS oscillator Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS39609C-page 320  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Param Sym Characteristic Min Typ† Max Units Conditions No. — FOSC Oscillator Frequency Range 4 — 10 MHz HS mode — FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode — t PLL Start-up Time (Lock Time) — — 2 ms rc — CLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 26-8: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure26-6 for load conditions.  2003-2013 Microchip Technology Inc. DS39609C-page 321

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-8: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1  to CLKO  — 75 200 ns (Note 1) 11 TOSH2CKH OSC1  to CLKO  — 75 200 ns (Note 1) 12 TCKR CLKO Rise Time — 35 100 ns (Note 1) 13 TCKF CLKO Fall Time — 35 100 ns (Note 1) 14 TCKL2IOV CLKO  to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TIOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns (Note 1) 16 TCKH2IOI Port In Hold after CLKO  0 — — ns (Note 1) 17 TOSH2IOV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1  (Q2 cycle) to Port PIC18FXX20 100 — — ns 18A Input Invalid (I/O in hold time) PIC18LFXX20 200 — — ns VDD = 2.0V 19 TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 0 — — ns 20 TIOR Port Output Rise Time PIC18FXX20 — 10 25 ns 20A PIC18LFXX20 — — 60 ns VDD = 2.0V 21 TIOF Port Output Fall Time PIC18FXX20 — 10 25 ns 21A PIC18LFXX20 — — 60 ns VDD = 2.0V 22† TINP INT pin High or Low Time TCY — — ns 23† TRBP RB7:RB4 Change INT High or Low Time TCY — — ns 24† TRCP RC7:RC4 Change INT High or Low Time 20 — — ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. FIGURE 26-9: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1(1) A<19:16> Address Address BA0 AD<15:0> Address Data from External Address 150 160 163 151 162 161 155 166 167 168 ALE 164 169 171 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated. Note 1: Maximum speed of FOSC is 25 MHz for external program memory read. DS39609C-page 322  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-9: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristics Min Typ Max Units No. 150 TADV2ALL Address Out Valid to ALE (address 0.25 TCY – 10 — — ns setup time) 151 TALL2ADL ALE  to Address Out Invalid (address hold time) 5 — — ns 155 TALL2OEL ALE to OE  10 0.125 TCY — ns 160 TADZ2OEL AD high-Z to OE (bus release to OE) 0 — — ns 161 TOEH2ADD OE  to AD Driven 0.125 TCY – 5 — — ns 162 TADV2OEH LS Data Valid before OE (data setup time) 20 — — ns 163 TOEH2ADL OE  to Data In Invalid (data hold time) 0 — — ns 164 TALH2ALL ALE Pulse Width — 0.25 TCY — ns 165 TOEL2OEH OE Pulse Width 0.5 TCY – 5 0.5 TCY — ns 166 TALH2ALH ALE  to ALE  (cycle time) — TCY — ns 167 TACC Address Valid to Data Valid 0.75 TCY – 25 — — ns 168 TOE OE  to Data Valid — 0.5 TCY – 25 ns 169 TALL2OEH ALE to OE  0.625 TCY – 10 — 0.625 TCY + 10 ns 171 TALH2CSL Chip Enable Active to ALE  — — 10 ns 171A TUBL2OEH AD Valid to Chip Enable Active 0.25 TCY – 20 — — ns FIGURE 26-10: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1(1) A<19:16> Address Address BA0 166 AD<15:0> Address Data Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157 157A UB or LB Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated. Note 1: Maximum speed of FOSC is 25 MHz for external program memory read.  2003-2013 Microchip Technology Inc. DS39609C-page 323

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param Symbol Characteristics Min Typ Max Units No. 150 TADV2ALL Address Out Valid to ALE (address setup time) 0.25 TCY – 10 — — ns 151 TALL2ADL ALE  to Address Out Invalid (address hold time) 5 — — ns 153 TWRH2ADL WRn  to Data Out Invalid (data hold time) 5 — — ns 154 TWRL WRn Pulse Width 0.5 TCY – 5 0.5 TCY — ns 156 TADV2WRH Data Valid before WRn (data setup time) 0.5 TCY – 10 — — ns 157 TBSV2WRL Byte Select Valid before WRn (byte select setup 0.25 TCY — — ns time) 157A TWRH2BSI WRn  to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 — — ns 166 TALH2ALH ALE  to ALE  (cycle time) — TCY — ns 171 TALH2CSL Chip Enable Active to ALE  — — 10 ns 171A TUBL2OEH AD Valid to Chip Enable Active 0.25 TCY – 20 — — ns FIGURE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure26-6 for load conditions. DS39609C-page 324  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-12: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference 36 Voltage Stable TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDT Watchdog Timer Time-out Period (no 7 18 33 ms postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 28 72 132 ms 34 TIOZ I/O High-Impedance from MCLR Low — 2 — s or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — s VDD  BVDD (see D005) 36 TIVRST Time for Internal Reference — 20 50 s Voltage to become stable 37 TLVD Low-Voltage Detect Pulse Width 200 — — s VDD  VLVD FIGURE 26-13: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure26-6 for load conditions.  2003-2013 Microchip Technology Inc. DS39609C-page 325

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20 ns or TCY + 40 value N (1, 2, 4,..., 256) 45 TT1H T13CKI Synchronous, no prescaler 0.5 TCY + 20 — ns High Time Synchronous, PIC18FXX20 10 — ns with prescaler PIC18LFXX20 25 — ns Asynchronous PIC18FXX20 30 — ns PIC18LFXX20 50 — ns 46 TT1L T13CKI Synchronous, no prescaler 0.5 TCY + 5 — ns Low Time Synchronous, PIC18FXX20 10 — ns with prescaler PIC18LFXX20 25 — ns Asynchronous PIC18FXX20 30 — ns PIC18LFXX20 TBD TBD ns 47 TT1P T13CKI Synchronous Greater of: — ns N = prescale Input Period 20 ns or TCY + 40 value (1, 2, 4, 8) N Asynchronous 60 — ns FT1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 TCKE2TMRI Delay from External T13CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment FIGURE 26-14: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure26-6 for load conditions. DS39609C-page 326  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With PIC18FXX20 10 — ns prescaler PIC18LFXX20 20 — ns 51 TCCH CCPx Input High No prescaler 0.5 TCY + 20 — ns Time With PIC18FXX20 10 — ns prescaler PIC18LFXX20 20 — ns 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TCCR CCPx Output Rise Time PIC18FXX20 — 25 ns PIC18LFXX20 — 45 ns VDD = 2.0V 54 TCCF CCPx Output Fall Time PIC18FXX20 — 25 ns PIC18LFXX20 — 45 ns VDD = 2.0V FIGURE 26-15: PARALLEL SLAVE PORT TIMING (PIC18F8X20) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure26-6 for load conditions.  2003-2013 Microchip Technology Inc. DS39609C-page 327

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8X20) Param Symbol Characteristic Min Max Units Conditions No. 62 TDTV2WRH Data In Valid before WR  or CS  20 — ns (setup time) 25 — ns Extended Temp. range 63 TWRH2DTI WR  or CS  to Data–In PIC18FXX20 20 — ns Invalid (hold time) PIC18LFXX20 35 — ns VDD = 2.0V 64 TRDL2DTV RD  and CS  to Data–Out Valid — 80 ns — 90 ns Extended Temp. range 65 TRDH2DTI RD  or CS  to Data–Out Invalid 10 30 ns 66 TIBFINH Inhibit of the IBF flag bit being cleared from — 3 TCY WR  or CS  FIGURE 26-16: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure26-6 for load conditions. DS39609C-page 328  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input TCY — ns TSSL2SCL 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns (Slave mode) 71A Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXX20 — 25 ns PIC18LFXX20 — 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 78 TSCR SCK Output Rise Time PIC18FXX20 — 25 ns (Master mode) PIC18LFXX20 — 45 ns VDD = 2.0V 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after SCK PIC18FXX20 — 50 ns TSCL2DOV Edge PIC18LFXX20 — 100 ns VDD = 2.0V Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. FIGURE 26-17: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure26-6 for load conditions.  2003-2013 Microchip Technology Inc. DS39609C-page 329

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns (Slave mode) 71A Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXX20 — 25 ns PIC18LFXX20 — 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 78 TSCR SCK Output Rise Time PIC18FXX20 — 25 ns (Master mode) PIC18LFXX20 — 45 ns VDD = 2.0V 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after SCK PIC18FXX20 — 50 ns TSCL2DOV Edge PIC18LFXX20 — 100 ns VDD = 2.0V 81 TDOV2SCH, SDO Data Output Setup to SCK Edge TCY — ns TDOV2SCL Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. FIGURE 26-18: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure26-6 for load conditions. DS39609C-page 330  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input TCY — ns TSSL2SCL 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns (Slave mode) 71A Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXX20 — 25 ns PIC18LFXX20 — 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 77 TSSH2DOZ SS  to SDO Output High-Impedance 10 50 ns 78 TSCR SCK Output Rise Time (Master mode) PIC18FXX20 — 25 ns PIC18LFXX20 — 45 ns VDD = 2.0V 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXX20 — 50 ns TSCL2DOV PIC18LFXX20 — 100 ns VDD = 2.0V 83 TSCH2SSH, SS  after SCK Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. FIGURE 26-19: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure26-6 for load conditions.  2003-2013 Microchip Technology Inc. DS39609C-page 331

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input TCY — ns TSSL2SCL 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns (Slave mode) 71A Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXX20 — 25 ns PIC18LFXX20 — 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 77 TSSH2DOZ SS  to SDO Output High-Impedance 10 50 ns 78 TSCR SCK Output Rise Time PIC18FXX20 — 25 ns (Master mode) PIC18LFXX20 — 45 ns VDD = 2.0V 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after SCK PIC18FXX20 — 50 ns TSCL2DOV Edge PIC18LFXX20 — 100 ns VDD = 2.0V 82 TSSL2DOV SDO Data Output Valid after SS  PIC18FXX20 — 50 ns Edge PIC18LFXX20 — 100 ns VDD = 2.0V 83 TSCH2SSH, SS  after SCK Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. FIGURE 26-20: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure26-6 for load conditions. DS39609C-page 332  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-19: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 26-21: I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure26-6 for load conditions.  2003-2013 Microchip Technology Inc. DS39609C-page 333

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-20: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s SSP module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — s PIC18FXX20 must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s PIC18FXX20 must operate at a minimum of 10 MHz SSP module 1.5 TCY — 102 TR SDA and SCL Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 91 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time 400 kHz mode 0.6 — s clock pulse is generated 106 THD:DAT Data Input Hold 100 kHz mode 0 — ns Time 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup 100 kHz mode 250 — ns (Note 2) Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 109 TAA Output Valid from 100 kHz mode — 3500 ns (Note 1) Clock 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT=1000+250=1250ns (according to the standard mode I2C bus specification), before the SCL line is released. DS39609C-page 334  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-22: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure26-6 for load conditions. TABLE 26-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins. FIGURE 26-23: MASTER SSP I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure26-6 for load conditions.  2003-2013 Microchip Technology Inc. DS39609C-page 335

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-22: MASTER SSP I2C BUS DATA REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 1 MHz mode(1) TBD — ns 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) TBD — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free before a new transmission 400 kHz mode 1.3 — ms can start 1 MHz mode(1) TBD — ms D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter #102 + parameter #107=1000+250=1250ns (for 100 kHz mode), before the SCL line is released. DS39609C-page 336  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-24: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX1/CK1 pin 121 121 RC7/RX1/DT1 pin 120 122 Note: Refer to Figure26-6 for load conditions. TABLE 26-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid PIC18FXX20 — 40 ns PIC18LFXX20 — 100 ns VDD = 2.0V 121 TCKRF Clock Out Rise Time and Fall Time PIC18FXX20 — 20 ns (Master mode) PIC18LFXX20 — 50 ns VDD = 2.0V 122 TDTRF Data Out Rise Time and Fall Time PIC18FXX20 — 20 ns PIC18LFXX20 — 50 ns VDD = 2.0V FIGURE 26-25: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX1/CK1 pin 125 RC7/RX1/DT1 pin 126 Note: Refer to Figure26-6 for load conditions. TABLE 26-24: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Hold before CK  (DT hold time) 10 — ns 126 TCKL2DTL Data Hold after CK  (DT hold time) 15 — ns  2003-2013 Microchip Technology Inc. DS39609C-page 337

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-25: A/D CONVERTER CHARACTERISTICS: PIC18FXX20 (INDUSTRIAL, EXTENDED) PIC18LFXX20 (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD = 5.0V A04 EDL Differential Linearity Error — — <±1 LSb VREF = VDD = 5.0V A05 EG Gain Error — — <±1 LSb VREF = VDD = 5.0V A06 EOFF Offset Error — — <±1.5 LSb VREF = VDD = 5.0V A10 — Monotonicity guaranteed(2) — VSS  VAIN  VREF A20 VREF Reference Voltage 1.8V — — V VDD < 3.0V A20A (VREFH – VREFL) 3V — — V VDD  3.0V A21 VREFH Reference Voltage High AVSS — AVDD + 0.3V V A22 VREFL Reference Voltage Low AVSS – 0.3V(5) — VREFH V A25 VAIN Analog Input Voltage AVSS – 0.3V(5) — AVDD + 0.3V(5) V VDD  2.5V (Note 3) A30 ZAIN Recommended Impedance of — — 2.5 k (Note 4) Analog Voltage Source A50 IREF VREF Input Current (Note 1) — — 5 A During VAIN acquisition. — — 150 A During A/D conversion cycle. Note 1: Vss  VAIN  VREF 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: For VDD < 2.5V, VAIN should be limited to <.5 VDD. 4: Maximum allowed impedance for analog voltage source is 10 k. This requires higher acquisition times. 5: IVDD – AVDDI must be <3.0V and IAVSS – VSSI must be <0.3V. FIGURE 26-26: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. DS39609C-page 338  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-26: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period PIC18FXX20 1.6 20(5) s TOSC based, VREF  3.0V PIC18LFXX20 3.0 20(5) s TOSC based, VREF full range PIC18FXX20 2.0 6.0 s A/D RC mode PIC18LFXX20 3.0 9.0 s A/D RC mode 131 TCNV Conversion Time 11 12 TAD (not including acquisition time) (Note 1) 132 TACQ Acquisition Time (Note 3) 15 — s -40C  Temp  +125C 10 — s 0C  Temp  +125C 135 TSWC Switching Time from Convert  Sample — (Note 4) 136 TAMP Amplifier Settling Time (Note 2) 1 — s This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). Note 1: ADRES register may be read on the following TCY cycle. 2: See Section19.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input voltage has changed more than 1 LSb. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50. 4: On the next Q4 cycle of the device clock. 5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.  2003-2013 Microchip Technology Inc. DS39609C-page 339

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 340  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 27.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean+3) or (mean–‘ 3) respectively, where  is a standard deviation, over the whole temperature range. FIGURE 27-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) 20 18 Typical: statistical mean @ 25°C 16 Maximum: mean + 3 (-40°C to +125°C) 5.5V Minimum: mean – 3 (-40°C to +125°C) 14 5.0V 12 4.5V A) (mD 10 4.0V D I 3.5V 8 6 3.0V 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) FIGURE 27-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) INDUSTRIAL 20 5.5V 18 Typical: statistical mean @ 25°C 16 Maximum: mean + 3 (-40°C to +85°C) 5.0V Minimum: mean – 3 (-40°C to +85°C) 4.5V 14 12 4.0V A) (mD 10 3.5V D I 8 3.0V 6 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz)  2003-2013 Microchip Technology Inc. DS39609C-page 341

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-3: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) EXTENDED 20 5.5V 18 Typical: statistical mean @ 25°C 5.0V Maximum: mean + 3 (-40°C to +125°C) 16 Minimum: mean – 3 (-40°C to +125°C) 4.5V 14 4.0V 12 A) (mD 10 3.5V D I 8 3.0V 6 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) FIGURE 27-4: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE) 20 18 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 16 Minimum: mean – 3 (-40°C to +125°C) 5.5V 14 5.0V 12 4.5V A) m (D 10 4.0V D I 8 3.5V 6 3.0V 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) DS39609C-page 342  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-5: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) INDUSTRIAL 20 18 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) 16 Minimum: mean – 3 (-40°C to +85°C) 5.0V 14 4.5V 12 4.0V A) m (D 10 3.5V D I 8 3.0V 6 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) FIGURE 27-6: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) EXTENDED 20 5.5V 18 Typical: statistical mean @ 25°C 16 Maximum: mean + 3 (-40°C to +125°C) 5.0V Minimum: mean – 3 (-40°C to +125°C) 4.5V 14 12 4.0V A) m (D 10 3.5V D I 8 3.0V 6 4 2.5V 2 2.0V 0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 FOSC (MHz)  2003-2013 Microchip Technology Inc. DS39609C-page 343

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-7: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.0 5.5V A) 5.0V (uD 1.5 D I 4.5V 4.0V 1.0 3.5V 3.0V 2.5V 0.5 2.0V 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 27-8: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) INDUSTRIAL 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 5.5V 2.0 5.0V A) 4.5V (uD 1.5 ID 4.0V 3.5V 1.0 3.0V 2.5V 2.0V 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) DS39609C-page 344  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-9: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 100 90 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 80 Minimum: mean – 3 (-40°C to +125°C) 5.5V 70 5.0V 60 4.5V A) (uD 50 4.0V D I 3.5V 40 3.0V 30 2.5V 2.0V 20 10 0 0 10 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 27-10: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) INDUSTRIAL 120 Typical: statistical mean @ 25°C 100 Maximum: mean + 3 (-40°C to +85°C) 5.5V Minimum: mean – 3 (-40°C to +85°C) 5.0V 80 4.5V A) 4.0V (uD 60 ID 3.5V 3.0V 40 2.5V 2.0V 20 0 0 10 20 30 40 50 60 70 80 90 100 FOSC (kHz)  2003-2013 Microchip Technology Inc. DS39609C-page 345

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-11: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) EXTENDED 300 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 5.5V 250 Minimum: mean – 3 (-40°C to +125°C) 5.0V 200 4.5V 4.0V A) (uD 150 3.5V D I 3.0V 2.5V 100 2.0V 50 0 0 10 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 27-12: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 18 Typical: statistical mean @ 25°C 16 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.5V 14 5.0V 12 4.5V A) 10 4.0V m (D ID 8 3.5V 6 3.0V 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) DS39609C-page 346  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-13: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 18 5.5V Typical: statistical mean @ 25°C 16 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.0V 14 4.5V 12 4.0V mA) 10 3.5V (D ID 8 6 3.0V 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) FIGURE 27-14: MAXIMUM IPD vs. VDD OVER TEMPERATURE 100 Max (-40°C:+125°C) 10 Max (-40°C:+85°C) A) (uD 1 TMyapxiicmalu:m: smtaetaisnt i+ca 3l m (e-4a0n° @C t2o5 +°C125°C) P I Minimum: mean – 3 (-40°C to +125°C) 0.1 Typ (25°C) 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2003-2013 Microchip Technology Inc. DS39609C-page 347

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-15: TYPICAL AND MAXIMUM IPD vs. VDD OVER TEMPERATURE (TIMER1 AS MAIN OSCILLATOR, 32.768kHz, C1 AND C2 = 47 pF) 1000 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 100 (uA)D (-40°CM:+a1x25°C) (-40°CM:a+x85°C) P I 10 Typ (25°C) 1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-16: TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED) 1000 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) Max (-40°C:+125°C) 100 Max (-40°C:+85°C) A) (uD 10 P I Typ (25°C) 1 0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39609C-page 348  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-17: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 0.55 Typical: statistical mean @ 25°C 0.50 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.45 0.40 5.5V 0.35 5.0V A) 0.30 m 4.5V (D D 0.25 I 4.0V 0.20 3.5V 0.15 3.0V 0.10 2.5V 0.05 2.0V 0.00 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz) FIGURE 27-18: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 0.55 Typical: statistical mean @ 25°C 0.50 Maximum: mean + 3 (-40°C to +125°C) 5.5V Minimum: mean – 3 (-40°C to +125°C) 5.0V 0.45 0.40 4.5V 0.35 A) 0.30 m 4.0V (D D 0.25 I 3.5V 0.20 0.15 3.0V 2.5V 0.10 2.0V 0.05 0.00 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz)  2003-2013 Microchip Technology Inc. DS39609C-page 349

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-19: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) (PIC18F8520 DEVICES ONLY) 30 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 25 Minimum: mean – 3 (-40°C to +125°C) 5.5V 20 5.0V mA) 4.5V (D 15 4.2V D I 4.0V 10 3.5V 5 3.0V 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 27-20: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) INDUSTRIAL (PIC18F8520 DEVICES ONLY) 30 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 5.5V 25 5.0V 20 4.5V 4.2V A) (mD 15 4.0V D I 3.5V 10 3.0V 5 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) DS39609C-page 350  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-21: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EXTENDED (PIC18F8520 DEVICES ONLY) 20 Typical: statistical mean @ 25°C 18 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 16 5.5V 14 5.0V 12 A) 4.5V m (D 10 4.2V D I 4.0V 8 3.5V 6 3.0V 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) FIGURE 27-22: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE) (PIC18F8520 DEVICES ONLY) 30 27 Typical: statistical mean @ 25°C 24 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.5V 21 5.0V 18 A) 4.5V m (D 15 4.2V D I 4.0V 12 9 3.5V 6 3.0V 3 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz)  2003-2013 Microchip Technology Inc. DS39609C-page 351

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-23: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) INDUSTRIAL (PIC18F8520 DEVICES ONLY) 30 27 5.5V Typical: statistical mean @ 25°C 24 Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 5.0V 21 4.5V 18 4.2V A) m 4.0V (D 15 D I 12 3.5V 9 6 3.0V 3 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 27-24: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) EXTENDED (PIC18F8520 DEVICES ONLY) 20 18 Typical: statistical mean @ 25°C 16 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.5V 14 5.0V 12 A) 4.5V (mD 10 4.2V D 4.0V I 8 3.5V 3.0V 6 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) DS39609C-page 352  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-25: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C) 4 3.5 --4400C°C SB) 3 L arity ( +2255C°C e 2.5 n nli No +8855C°C al 2 gr e nt al or I 1.5 nti e er Diff 1 0.5 1+2152C5°C 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD and VREFH (V) FIGURE 27-26: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40C TO +125C) 3 2.5 B) S L y ( arilt 2 e n nli o N al 1.5 gr e nt or I MMaaxx ((--4400°CC t oto 1 +2152C5)°C) al nti 1 e er TTyypp ((+2255C°)C) Diff 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V)  2003-2013 Microchip Technology Inc. DS39609C-page 353

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 354  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX PIC18F6620 XXXXXXXXXX -I/PT e3 XXXXXXXXXX 0410017 YYWWNNN 80-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX PIC18F8720 XXXXXXXXXXXX -E/PT e3 XXXXXXXXXXXX 0410017 YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2003-2013 Microchip Technology Inc. DS39609C-page 355

PIC18F6520/8520/6620/8620/6720/8720 28.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:27)(cid:28)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 E e E1 N b NOTE1 123 NOTE2 α A c φ A2 β A1 L L1 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 ;(cid:5) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)/(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)@/1 DS39609C-page 356  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2013 Microchip Technology Inc. DS39609C-page 357

PIC18F6520/8520/6620/8620/6720/8720 )(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 E e E1 b N NOTE1 123 NOTE2 α A c φ β A1 A2 L L1 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 @(cid:4) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)/(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)(cid:6)(cid:17)1 DS39609C-page 358  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2013 Microchip Technology Inc. DS39609C-page 359

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 360  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (January 2003) The differences between the devices listed in this data Original data sheet for the PIC18FXX20 family which sheet are shown in TableB-1. includes PIC18F6520, PIC18F6620, PIC18F6720, PIC18F8520, PIC18F8620 and PIC18F8720 devices. This data sheet is based on the previous PIC18FXX20 Data Sheet (DS39580). Revision B (January 2004) This revision includes the DC and AC Characteristics Graphs and Tables. The Electrical Specifications in Section26.0 “Electrical Characteristics” have been updated and there have been minor corrections to the data sheet text. Revision C (November 2011) This revision updated Section28.0 “Packaging Infor- mation”. TABLE B-1: DEVICE DIFFERENCES Feature PIC18F6520 PIC18F6620 PIC18F6720 PIC18F8520 PIC18F8620 PIC18F8720 On-Chip Program Memory 32 64 128 32 64 128 (Kbytes) Data Memory (bytes) 2048 3840 3840 2048 3840 3840 Boot Block (bytes) 2048 512 512 2048 512 512 Timer1 Low-Power Option Yes No No Yes No No I/O Ports Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, D, E, F, G D, E, F, G D, E, F, G D, E, F, G, H, J D, E, F, G, H, J D, E, F, G, H, J A/D Channels 12 12 12 16 16 16 External Memory Interface No No No Yes Yes Yes Maximum Operating 40 25 25 40 25 25 Frequency (MHz) Package Types 64-pin TQFP 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP  2003-2013 Microchip Technology Inc. DS39609C-page 361

PIC18F6520/8520/6620/8620/6720/8720 APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM CONSIDERATIONS MID-RANGE TO ENHANCED DEVICES This appendix discusses the considerations for converting from previous versions of a device to the A detailed discussion of the differences between the ones listed in this data sheet. Typically, these changes mid-range MCU devices (i.e., PIC16CXXX) and the are due to the differences in the process technology enhanced devices (i.e., PIC18FXXX) is provided in used. An example of this type of conversion is from a AN716, “Migrating Designs from PIC16C74A/74B to PIC17C756 to a PIC18F8720. PIC18C442”. The changes discussed, while device Not Currently Available specific, are generally applicable to all mid-range to enhanced device migrations. This Application Note is available as Literature Number DS00716. DS39609C-page 362  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 APPENDIX E: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and dif- ferences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXXX) is provided in AN726, “PIC17CXXX to PIC18CXXX Migration”. This Application Note is available as Literature Number DS00726.  2003-2013 Microchip Technology Inc. DS39609C-page 363

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 364  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 INDEX A Baud Rate Generator ..............................................183 Capture Mode Operation .........................................151 A/D ...................................................................................213 Comparator Analog Input Model ..............................227 A/D Converter Interrupt, Configuring .......................217 Comparator I/O Operating Modes (Diagram) ..........224 Acquisition Requirements ........................................218 Comparator Output ..................................................226 Acquisition Time .......................................................218 Comparator Voltage Reference ...............................230 ADCON0 Register ....................................................213 Compare Mode Operation .......................................152 ADCON1 Register ....................................................213 Low-Voltage Detect (LVD) .......................................234 ADCON2 Register ....................................................213 Low-Voltage Detect (LVD) with External Input ........234 ADRESH Register ............................................213, 215 MSSP (I2C Master Mode) ........................................181 ADRESL Register ............................................213, 215 MSSP (I2C Mode) ....................................................166 Analog Port Pins ......................................................128 MSSP (SPI Mode) ...................................................157 Analog Port Pins, Configuring ..................................219 On-Chip Reset Circuit ................................................29 Associated Register Summary .................................221 PIC18F6X20 Architecture ............................................9 Calculating Minimum Required Acquisition Time (Exam- PIC18F8X20 Architecture ..........................................10 ple) ...................................................................218 PLL ............................................................................23 CCP2 Trigger ...........................................................220 PORT/LAT/TRIS Operation .....................................103 Configuring the Module ............................................217 PORTA Conversion Clock (Tad) ...........................................219 RA3:RA0 and RA5 Pins ...................................104 Conversion Requirements .......................................339 RA4/T0CKI Pin ................................................104 Conversion Status (GO/DONE Bit) ..........................215 RA6 Pin (as I/O) ..............................................104 Conversion Tad Cycles ............................................220 PORTB Conversions .............................................................220 RB2:RB0 Pins ..................................................107 Converter Characteristics ........................................338 RB3 Pin ...........................................................107 Equations .................................................................218 RB7:RB4 Pins ..................................................106 Minimum Charging Time ..........................................218 PORTC (Peripheral Output Override) ......................109 Special Event Trigger (CCP) ....................................152 PORTD and PORTE Special Event Trigger (CCP2) ..................................220 Parallel Slave Port ...........................................128 Tad vs. Device Operating Frequencies (Table) .......219 PORTD in I/O Port Mode .........................................111 Absolute Maximum Ratings .............................................305 PORTD in System Bus Mode ..................................112 AC (Timing) Characteristics .............................................318 PORTE in I/O Mode .................................................115 Load Conditions for Device Timing Specifications ...319 PORTE in System Bus Mode ..................................115 Parameter Symbology .............................................318 PORTF Temperature and Voltage Specifications .................319 RF1/AN6/C2OUT and RF2/AN5/C1OUT Pins .117 Timing Conditions ....................................................319 RF6/RF3 and RF0 Pins ...................................118 ACKSTAT Status Flag .....................................................187 RF7 Pin ...........................................................118 ADCON0 Register ............................................................213 PORTG (Peripheral Output Override) .....................120 GO/DONE Bit ...........................................................215 PORTH ADCON1 Register ............................................................213 ADCON2 Register ............................................................213 RH3:RH0 Pins in System Bus Mode .......123 ADDLW ............................................................................265 RH3:RH0 Pins in I/O Mode ..............................122 Addressable Universal Synchronous Asynchronous Receiver RH7:RH4 Pins in I/O Mode ..............................122 Transmitter (USART) ...............................................197 PORTJ ADDWF ............................................................................265 RJ4:RJ0 Pins in System Bus Mode .................126 ADDWFC .........................................................................266 RJ7:RJ6 Pins in System Bus Mode .................126 ADRESH Register ....................................................213, 215 PORTJ in I/O Mode .................................................125 ADRESL Register ....................................................213, 215 PWM Operation (Simplified) ....................................154 Analog-to-Digital Converter. See A/D. Reads from Flash Program Memory .........................65 ANDLW ............................................................................266 Single Comparator ...................................................225 ANDWF ............................................................................267 Table Read Operation ...............................................61 Assembler Table Write Operation ...............................................62 MPASM Assembler ..................................................302 Table Writes to Flash Program Memory ....................67 B Timer0 in 16-bit Mode ..............................................132 Baud Rate Generator .......................................................183 Timer0 in 8-bit Mode ................................................132 BC ....................................................................................267 Timer1 .....................................................................136 BCF ..................................................................................268 Timer1 (16-bit R/W Mode) .......................................136 BF Status Flag .................................................................187 Timer2 .....................................................................142 Block Diagrams Timer3 .....................................................................144 16-bit Byte Select Mode .............................................75 Timer3 in 16-bit R/W Mode ......................................144 16-bit Byte Write Mode ..............................................73 Timer4 .....................................................................148 16-bit Word Write Mode .............................................74 USART Receive ......................................................206 A/D ...........................................................................216 USART Transmit .....................................................204 Analog Input Model ..................................................217 Voltage Reference Output Buffer Example .............231  2003-2013 Microchip Technology Inc. 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PIC18F6520/8520/6620/8620/6720/8720 Watchdog Timer .......................................................251 Loading the SSPBUF (SSPSR) Register .................160 BN ....................................................................................268 Reading a Flash Program Memory Word ..................65 BNC ..................................................................................269 Saving Status, WREG and BSR Registers in RAM .102 BNN ..................................................................................269 Writing to Flash Program Memory .......................68–69 BNOV ...............................................................................270 Code Protection ...............................................................239 BNZ ..................................................................................270 COMF ..............................................................................276 BOR. See Brown-out Reset. Comparator ......................................................................223 BOV ..................................................................................273 Analog Input Connection Considerations ................227 BRA ..................................................................................271 Associated Registers ...............................................228 BRG. See Baud Rate Generator. Configuration ...........................................................224 Brown-out Reset (BOR) .....................................................30 Effects of a Reset ....................................................227 BSF ..................................................................................271 Interrupts .................................................................226 BTFSC .............................................................................272 Operation .................................................................225 BTFSS ..............................................................................272 Operation During Sleep ...........................................227 BTG ..................................................................................273 Outputs ....................................................................225 BZ .....................................................................................274 Reference ................................................................225 External Signal ................................................225 C Internal Signal ..................................................225 C Compilers Response Time ........................................................225 MPLAB C18 .............................................................302 Comparator Specifications ...............................................315 CALL ................................................................................274 Comparator Voltage Reference .......................................229 Capture (CCP Module) .....................................................151 Accuracy and Error ..................................................230 Associated Registers ...............................................153 Associated Registers ...............................................231 CCP Pin Configuration .............................................151 Configuring ..............................................................229 CCPR1H:CCPR1L Registers ...................................151 Connection Considerations ......................................230 Software Interrupt ....................................................151 Effects of a Reset ....................................................230 Timer1/Timer3 Mode Selection ................................151 Operation During Sleep ...........................................230 Capture/Compare/PWM (CCP) ........................................149 Compare (CCP Module) ..................................................152 Capture Mode. See Capture. Associated Registers ...............................................153 CCP Mode and Timer Resources ............................150 CCP Pin Configuration .............................................152 CCPRxH Register ....................................................150 CCPR1 Register ......................................................152 CCPRxL Register .....................................................150 Software Interrupt ....................................................152 Compare Mode. See Compare. Special Event Trigger ..............................138, 145, 152 Interconnect Configurations .....................................150 Timer1/Timer3 Mode Selection ................................152 Module Configuration ...............................................150 Compare (CCP2 Module) PWM Mode. See PWM. Special Event Trigger ..............................................220 Capture/Compare/PWM Requirements (All CCP Modules) ... Configuration Bits ............................................................239 327 Context Saving During Interrupts .....................................102 CLKO and I/O Timing Requirements .......................322, 323 Control Registers Clocking Scheme/Instruction Cycle ....................................44 EECON1 and EECON2 .............................................62 CLRF ................................................................................275 TABLAT (Table Latch) Register .................................64 CLRWDT ..........................................................................275 TBLPTR (Table Pointer) Register ..............................64 Code Examples Conversion Considerations ..............................................362 16 x 16 Signed Multiply Routine ................................86 CPFSEQ ..........................................................................276 16 x 16 Unsigned Multiply Routine ............................86 CPFSGT ..........................................................................277 8 x 8 Signed Multiply Routine ....................................85 CPFSLT ...........................................................................277 8 x 8 Unsigned Multiply Routine ................................85 Customer Change Notification Service ............................375 Changing Between Capture Prescalers ...................151 Customer Notification Service .........................................375 Data EEPROM Read .................................................81 Customer Support ............................................................375 Data EEPROM Refresh Routine ................................82 D Data EEPROM Write .................................................81 Erasing a Flash Program Memory Row .....................66 Data EEPROM Memory Fast Register Stack ....................................................44 Associated Registers .................................................83 How to Clear RAM (Bank 1) Using Indirect Addressing . EEADR Register ........................................................79 57 EEADRH Register .....................................................79 Implementing a Real-Time Clock using a Timer1 Inter- EECON1 Register ......................................................79 rupt Service ......................................................139 EECON2 Register ......................................................79 Initializing PORTA ....................................................103 Operation During Code-Protect .................................82 Initializing PORTB ....................................................106 Protection Against Spurious Write .............................82 Initializing PORTC ....................................................109 Reading .....................................................................81 Initializing PORTD ....................................................111 Using .........................................................................82 Initializing PORTE ....................................................114 Write Verify ................................................................82 Initializing PORTF ....................................................117 Writing .......................................................................81 Initializing PORTG ...................................................120 Data Memory .....................................................................47 Initializing PORTH ....................................................122 General Purpose Registers .......................................47 Initializing PORTJ ....................................................125 Map for PIC18FX520 Devices ...................................48 DS39609C-page 366  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 Map for PIC18FX620/X720 Devices ..........................49 Operation ...................................................................85 Special Function Registers ........................................47 Performance Comparison ..........................................85 DAW .................................................................................278 HS/PLL ..............................................................................23 DC and AC Characteristics I Graphs and Tables ..................................................341 DC Characteristics I/O Ports ..........................................................................103 PIC18FXX20 (Industrial and Extended), PIC18LFXX20 I2C Bus Data Requirements (Slave Mode) ......................334 (Industrial) ........................................................313 I2C Bus Start/Stop Bits Requirements (Slave Mode) .......333 Power-Down and Supply Current ............................309 I2C Mode Supply Voltage .........................................................308 General Call Address Support .................................180 DCFSNZ ..........................................................................279 Master Mode DECF ...............................................................................278 Operation .........................................................182 DECFSZ ...........................................................................279 Read/Write Bit Information (R/W Bit) ...............170, 171 Development Support ......................................................301 Serial Clock (RC3/SCK/SCL) ..................................171 Device Differences ...........................................................361 ID Locations .............................................................239, 257 Direct Addressing ...............................................................58 INCF ................................................................................280 Direct Addressing .......................................................56 INCFSZ ............................................................................281 In-Circuit Debugger ..........................................................257 E Resources (Table) ...................................................257 Electrical Characteristics ..................................................305 In-Circuit Serial Programming (ICSP) ......................239, 257 Errata ...................................................................................5 Indirect Addressing ............................................................58 Example SPI Mode Requirements (Master Mode, CKE = 0) . INDF and FSR Registers ...........................................57 329 Operation ...................................................................57 Example SPI Mode Requirements (Master Mode, CKE = 1) . Indirect Addressing Operation ...........................................58 330 Indirect File Operand .........................................................47 Example SPI Mode Requirements (Slave Mode, CKE = 0) ... INFSNZ ............................................................................281 331 Instruction Cycle ................................................................44 Example SPI Slave Mode Requirements (CKE = 1) ........332 Instruction Flow/Pipelining .................................................45 Extended Microcontroller Mode .........................................71 Instruction Format ............................................................261 External Clock Timing Requirements ...............................320 Instruction Set ..................................................................259 External Memory Interface .................................................71 ADDLW ....................................................................265 16-bit Byte Select Mode .............................................75 ADDWF ...................................................................265 16-bit Byte Write Mode ..............................................73 ADDWFC .................................................................266 16-bit Mode ................................................................73 ANDLW ....................................................................266 16-bit Mode Timing ....................................................76 ANDWF ...................................................................267 16-bit Word Write Mode .............................................74 BC ............................................................................267 PIC18F8X20 External Bus - I/O Port Functions .........72 BCF .........................................................................268 Program Memory Modes and External Memory Interface BN ............................................................................268 ............................................................................71 BNC .........................................................................269 BNN .........................................................................269 F BNOV ......................................................................270 Firmware Instructions .......................................................259 BNZ .........................................................................270 Flash Program Memory .....................................................61 BOV .........................................................................273 Associated Registers .................................................69 BRA .........................................................................271 Control Registers .......................................................62 BSF ..........................................................................271 Erase Sequence ........................................................66 BTFSC .....................................................................272 Erasing .......................................................................66 BTFSS .....................................................................272 Operation During Code-Protect .................................69 BTG .........................................................................273 Reading ......................................................................65 BZ ............................................................................274 Table Pointer CALL ........................................................................274 Boundaries Based on Operation ........................64 CLRF .......................................................................275 Table Pointer Boundaries ..........................................64 CLRWDT .................................................................275 Table Reads and Table Writes ..................................61 COMF ......................................................................276 Write Sequence .........................................................67 CPFSEQ ..................................................................276 Writing To ...................................................................67 CPFSGT ..................................................................277 Protection Against Spurious Writes ...................69 CPFSLT ...................................................................277 Unexpected Termination ....................................69 DAW ........................................................................278 Write Verify ........................................................69 DCFSNZ ..................................................................279 DECF .......................................................................278 G DECFSZ ..................................................................279 General Call Address Support .........................................180 GOTO ......................................................................280 GOTO ..............................................................................280 INCF ........................................................................280 H INCFSZ ....................................................................281 INFSNZ ....................................................................281 Hardware Multiplier ............................................................85 IORLW .....................................................................282 Introduction ................................................................85 IORWF .....................................................................282  2003-2013 Microchip Technology Inc. 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PIC18F6520/8520/6620/8620/6720/8720 LFSR ........................................................................283 Easy Migration .............................................................7 MOVF .......................................................................283 Expanded Memory .......................................................7 MOVFF ....................................................................284 External Memory Interface ...........................................7 MOVLB ....................................................................284 Other Special Features ................................................7 MOVLW ...................................................................285 L MOVWF ...................................................................285 MULLW ....................................................................286 LFSR ................................................................................283 MULWF ....................................................................286 Low-Voltage Detect .........................................................233 NEGF .......................................................................287 Characteristics .........................................................316 NOP .........................................................................287 Converter Characteristics ........................................316 POP .........................................................................288 Effects of a Reset ....................................................237 PUSH .......................................................................288 Operation .................................................................236 RCALL .....................................................................289 Current Consumption ......................................237 RESET .....................................................................289 During Sleep ....................................................237 RETFIE ....................................................................290 Reference Voltage Set Point ...........................237 RETLW ....................................................................290 Typical Application ...................................................233 RETURN ..................................................................291 Low-Voltage ICSP Programming .....................................257 RLCF ........................................................................291 LVD. See Low-Voltage Detect. ........................................233 RLNCF .....................................................................292 M RRCF .......................................................................292 RRNCF ....................................................................293 Master SSP (MSSP) Module SETF ........................................................................293 Overview ..................................................................157 SLEEP .....................................................................294 Master SSP I2C Bus Data Requirements ........................336 SUBFWB ..................................................................294 Master SSP I2C Bus Start/Stop Bits Requirements .........335 SUBLW ....................................................................295 Master Synchronous Serial Port (MSSP). See MSSP. SUBWF ....................................................................295 Master Synchronous Serial Port. See MSSP SUBWFB ..................................................................296 Memory Organization SWAPF ....................................................................296 Data Memory .............................................................47 TBLRD .....................................................................297 Memory Programming Requirements ..............................317 TBLWT .....................................................................298 Microchip Internet Web Site .............................................375 TSTFSZ ...................................................................299 Microcontroller Mode .........................................................71 XORLW ....................................................................299 Microprocessor Mode ........................................................71 XORWF ....................................................................300 Microprocessor with Boot Block Mode ...............................71 Summary Table ........................................................262 Migration from High-End to Enhanced Devices ...............363 INT Interrupt (RB0/INT). See Interrupt Sources Migration from Mid-Range to Enhanced Devices ............362 INTCON Registers .............................................................89 MOVF ..............................................................................283 Inter-Integrated Circuit. See I2C MOVFF ............................................................................284 Internet Address ...............................................................375 MOVLB ............................................................................284 Interrupt Sources ..............................................................239 MOVLW ...........................................................................285 A/D Conversion Complete .......................................217 MOVWF ...........................................................................285 Capture Complete (CCP) .........................................151 MPLAB ASM30 Assembler, Linker, Librarian ..................302 Compare Complete (CCP) .......................................152 MPLAB Integrated Development Environment Software .301 INT0 .........................................................................102 MPLAB PM3 Device Programmer ...................................304 Interrupt-on-Change (RB7:RB4) ..............................106 MPLAB REAL ICE In-Circuit Emulator System ...............303 PORTB, Interrupt-on-Change ..................................102 MPLINK Object Linker/MPLIB Object Librarian ...............302 RB0/INT Pin, External ..............................................102 MSSP ...............................................................................157 TMR0 .......................................................................102 ACK Pulse .......................................................170, 171 TMR0 Overflow ........................................................133 Clock Stretching .......................................................176 TMR1 Overflow ................................................135, 138 10-bit Slave Receive Mode (SEN = 1) .............176 TMR2 to PR2 Match ................................................142 10-bit Slave Transmit Mode .............................176 TMR2 to PR2 Match (PWM) ............................141, 154 7-bit Slave Receive Mode (SEN = 1) ...............176 TMR3 Overflow ................................................143, 145 7-bit Slave Transmit Mode ...............................176 TMR4 to PR4 Match ................................................148 Clock Synchronization and the CKP bit ...................177 TMR4 to PR4 Match (PWM) ....................................147 Control Registers (general) ......................................157 Interrupts ............................................................................87 Enabling SPI I/O ......................................................161 Control Registers .......................................................89 I2C Mode .................................................................166 Enable Registers ........................................................95 Acknowledge Sequence Timing ......................190 Flag Registers ............................................................92 Baud Rate Generator ......................................183 Logic ..........................................................................88 Bus Collision Priority Registers ........................................................98 During a Repeated Start Condition ..........194 Reset Control Registers ...........................................101 Bus Collision During a Start Condition ............192 IORLW .............................................................................282 Bus Collision During a Stop Condition .............195 IORWF .............................................................................282 Clock Arbitration ..............................................184 IPR Registers .....................................................................98 Effect of a Reset ..............................................191 I2C Clock Rate w/BRG ....................................183 K Master Mode ....................................................181 Key Features Reception ................................................187 DS39609C-page 368  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 Repeated Start Timing .............................186 RE1/WR/AN6 Pin ....................................................128 Master Mode Start Condition ...........................185 RE2/CS/AN7 Pin .....................................................128 Master Mode Transmission .............................187 Read Waveforms .....................................................130 Multi-Master Communication, Bus Collision and Ar- Select (PSPMODE Bit) ....................................111, 128 bitration ....................................................191 Write Waveforms .....................................................129 Multi-Master Mode ...........................................191 Parallel Slave Port Requirements (PIC18F8X20) ............328 Registers ..........................................................166 PIE Registers .....................................................................95 Sleep Operation ...............................................191 Pin Functions Stop Condition Timing .....................................190 AVDD ..........................................................................20 I2C Mode. See I2C AVSS ..........................................................................20 Module Operation ....................................................170 MCLR/VPP .................................................................11 Operation .................................................................160 OSC1/CLKI ................................................................11 Slave Mode ..............................................................170 OSC2/CLKO/RA6 ......................................................11 Addressing .......................................................170 RA0/AN0 ....................................................................12 Reception .........................................................171 RA1/AN1 ....................................................................12 Transmission ...................................................171 RA2/AN2/VREF- .........................................................12 SPI RA3/AN3/VREF+ ........................................................12 Master Mode ....................................................162 RA4/T0CKI ................................................................12 SPI Clock .........................................................162 RA5/AN4/LVDIN ........................................................12 SPI Master Mode .....................................................162 RA6 ............................................................................12 SPI Mode .................................................................157 RB0/INT0 ...................................................................13 SPI Mode. See SPI RB1/INT1 ...................................................................13 SPI Slave Mode .......................................................163 RB2/INT2 ...................................................................13 Select Synchronization ....................................163 RB3/INT3/CCP2 ........................................................13 SSPBUF Register ....................................................162 RB4/KBI0 ...................................................................13 SSPSR Register ......................................................162 RB5/KBI1/PGM ..........................................................13 Typical Connection ..................................................161 RB6/KBI2/PGC ..........................................................13 MSSP Module RB7/KBI3/PGD ..........................................................13 SPI Master./Slave Connection .................................161 RC0/T1OSO/T13CKI .................................................14 MULLW ............................................................................286 RC1/T1OSI/CCP2 .....................................................14 MULWF ............................................................................286 RC2/CCP1 .................................................................14 RC3/SCK/SCL ...........................................................14 N RC4/SDI/SDA ............................................................14 NEGF ...............................................................................287 RC5/SDO ...................................................................14 NOP .................................................................................287 RC6/TX1/CK1 ............................................................14 RC7/RX1/DT1 ............................................................14 O RD0/PSP0/AD0 .........................................................15 Opcode Field Descriptions ...............................................260 RD1/PSP1/AD1 .........................................................15 OPTION_REG Register RD2/PSP2/AD2 .........................................................15 PSA Bit .....................................................................133 RD3/PSP3/AD3 .........................................................15 T0CS Bit ...................................................................133 RD4/PSP4/AD4 .........................................................15 T0PS2:T0PS0 Bits ...................................................133 RD5/PSP5/AD5 .........................................................15 T0SE Bit ...................................................................133 RD6/PSP6/AD6 .........................................................15 Oscillator Configuration ......................................................21 RD7/PSP7/AD7 .........................................................15 EC ..............................................................................21 RE0/RD/AD8 .............................................................16 ECIO ..........................................................................21 RE1/WR/AD9 .............................................................16 HS ..............................................................................21 RE2/CS/AD10 ............................................................16 HS + PLL ...................................................................21 RE3/AD11 ..................................................................16 LP ...............................................................................21 RE4/AD12 ..................................................................16 RC ..............................................................................21 RE5/AD13 ..................................................................16 RCIO ..........................................................................21 RE6/AD14 ..................................................................16 XT ..............................................................................21 RE7/CCP2/AD15 .......................................................16 Oscillator Selection ..........................................................239 RF0/AN5 ....................................................................17 Oscillator Switching Feature ..............................................24 RF1/AN6/C2OUT .......................................................17 Oscillator Transitions .................................................26 RF2/AN7/C1OUT .......................................................17 System Clock Switch Bit ............................................25 RF3/AN8 ....................................................................17 Oscillator, Timer1 .............................................135, 137, 145 RF4/AN9 ....................................................................17 Oscillator, Timer3 .............................................................143 RF5/AN10/CVREF ......................................................17 Oscillator, WDT ................................................................250 RF6/AN11 ..................................................................17 P RF7/SS ......................................................................17 RG0/CCP3 .................................................................18 Packaging Information .....................................................355 RG1/TX2/CK2 ............................................................18 Details ......................................................................356 RG2/RX2/DT2 ...........................................................18 Marking ....................................................................355 RG3/CCP4 .................................................................18 Parallel Slave Port (PSP) .........................................111, 128 RG4/CCP5 .................................................................18 Associated Registers ...............................................130 RH0/A16 ....................................................................19 RE0/RD/AN5 Pin ......................................................128  2003-2013 Microchip Technology Inc. DS39609C-page 369

PIC18F6520/8520/6620/8620/6720/8720 RH1/A17 ....................................................................19 PORTF Register ......................................................117 RH2/A18 ....................................................................19 TRISF Register ........................................................117 RH3/A19 ....................................................................19 PORTG RH4/AN12 ..................................................................19 Associated Registers ...............................................121 RH5/AN13 ..................................................................19 Functions .................................................................121 RH6/AN14 ..................................................................19 LATG Register .........................................................120 RH7/AN15 ..................................................................19 PORTG Register ......................................................120 RJ0/ALE .....................................................................20 TRISG Register ...............................................120, 197 RJ1/OE ......................................................................20 PORTH RJ2/WRL ....................................................................20 Associated Registers ...............................................124 RJ3/WRH ...................................................................20 Functions .................................................................124 RJ4/BA0 .....................................................................20 LATH Register .........................................................122 RJ5/CE .......................................................................20 PORTH Register ......................................................122 RJ6/LB .......................................................................20 TRISH Register ........................................................122 RJ7/UB .......................................................................20 PORTJ VDD .............................................................................20 Associated Registers ...............................................127 VSS .............................................................................20 Functions .................................................................127 PIR Registers .....................................................................92 LATJ Register ..........................................................125 PLL Clock Timing Specifications ......................................321 PORTJ Register .......................................................125 PLL Lock Time-out .............................................................30 TRISJ Register ........................................................125 Pointer, FSR .......................................................................57 Postscaler, WDT POP ..................................................................................288 Assignment (PSA Bit) ..............................................133 POR. See Power-on Reset. Rate Select (T0PS2:T0PS0 Bits) .............................133 PORTA Switching Between Timer0 and WDT ......................133 Associated Registers ...............................................105 Power-down Mode. See Sleep. Functions .................................................................105 Power-on Reset (POR) ......................................................30 LATA Register ..........................................................103 Oscillator Start-up Timer (OST) .................................30 PORTA Register ......................................................103 Power-up Timer (PWRT) ...........................................30 TRISA Register ........................................................103 Time-out Sequence ...................................................30 PORTB Prescaler, Capture ...........................................................151 Associated Registers ...............................................108 Prescaler, Timer0 ............................................................133 Functions .................................................................108 Assignment (PSA Bit) ..............................................133 LATB Register ..........................................................106 Rate Select (T0PS2:T0PS0 Bits) .............................133 PORTB Register ......................................................106 Switching Between Timer0 and WDT ......................133 RB0/INT Pin, External ..............................................102 Prescaler, Timer2 ............................................................154 TRISB Register ........................................................106 Product Identification System ..........................................377 PORTC Program Counter Associated Registers ...............................................110 PCL, PCLATH and PCLATU Registers .....................44 Functions .................................................................110 Program Memory ...............................................................39 LATC Register .........................................................109 Access for PIC18F8X20 Program Memory Modes ....40 PORTC Register ......................................................109 Instructions ................................................................45 RC3/SCK/SCL Pin ...................................................171 Interrupt Vector ..........................................................39 TRISC Register ................................................109, 197 Map and Stack for PIC18FXX20 ................................40 PORTD .............................................................................128 Maps for PIC18F8X20 Program Memory Modes .......41 Associated Registers ...............................................113 PIC18F8X20 Modes ..................................................39 Functions .................................................................113 Reset Vector ..............................................................39 LATD Register .........................................................111 Program Memory Write Timing Requirements ................324 Parallel Slave Port (PSP) Function ..........................111 Program Verification and Code Protection ......................253 PORTD Register ......................................................111 Associated Registers ...............................................253 TRISD Register ........................................................111 Configuration Register Protection ............................257 PORTE Data EEPROM Code Protection ..............................257 Analog Port Pins ......................................................128 Memory Code Protection .........................................255 Associated Registers ...............................................116 Programming, Device Instructions ...................................259 Functions .................................................................116 PSP.See Parallel Slave Port. LATE Register ..........................................................114 Pulse Width Modulation. See PWM (CCP Module). PORTE Register ......................................................114 PUSH ...............................................................................288 PSP Mode Select (PSPMODE Bit) ..................111, 128 PWM (CCP Module) ........................................................154 RE0/RD/AN5 Pin ......................................................128 Associated Registers ...............................................155 RE1/WR/AN6 Pin .....................................................128 CCPR1H:CCPR1L Registers ...................................154 RE2/CS/AN7 Pin ......................................................128 Duty Cycle ...............................................................154 TRISE Register ........................................................114 Example Frequencies/Resolutions ..........................155 PORTF Period ......................................................................154 Associated Registers ...............................................119 Setup for PWM Operation ........................................155 Functions .................................................................119 TMR2 to PR2 Match ........................................141, 154 LATF Register ..........................................................117 TMR4 to PR4 Match ................................................147 DS39609C-page 370  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 Q Brown-out Reset (BOR) ...........................................239 MCLR Reset ..............................................................29 Q Clock ............................................................................154 MCLR Reset during Sleep .........................................29 R Oscillator Start-up Timer (OST) ...............................239 RAM. See Data Memory Power-on Reset (POR) ......................................29, 239 RC Oscillator ......................................................................22 Power-up Timer (PWRT) .........................................239 RCALL .............................................................................289 Programmable Brown-out Reset (PBOR) ..................29 RCON Registers ..............................................................101 Reset Instruction ........................................................29 RCSTA Register Stack Full Reset ........................................................29 SPEN Bit ..................................................................197 Stack Underflow Reset ..............................................29 Reader Response ............................................................376 Watchdog Timer (WDT) Reset ..................................29 Register File .......................................................................47 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Registers Timer and Brown-out Reset Requirements .............325 ADCON0 (A/D Control 0) .........................................213 RETFIE ............................................................................290 RETLW ............................................................................290 ADCON1 (A/D Control 1) .........................................214 ADCON2 (A/D Control 2) .........................................215 RETURN ..........................................................................291 CCPxCON (Capture/Compare/PWM Control) .........149 Return Address Stack CMCON (Comparator Control) ................................223 and Associated Registers ..........................................43 CONFIG1H (Configuration 1 High) ..........................240 Revision History ...............................................................361 CONFIG2H (Configuration 2 High) ..........................241 RLCF ...............................................................................291 CONFIG2L (Configuration 2 Low) ............................241 RLNCF .............................................................................292 CONFIG3H (Configuration 3 High) ..........................242 RRCF ...............................................................................292 CONFIG3L (Configuration 3 Low) ............................242 RRNCF ............................................................................293 CONFIG3L (Configuration Byte) ................................41 S CONFIG4L (Configuration 4 Low) ............................243 SCI. See USART CONFIG5H (Configuration 5 High) ..........................245 SCK .................................................................................157 CONFIG5L (Configuration 5 Low) ............................244 SDI ...................................................................................157 CONFIG6H (Configuration 6 High) ..........................247 SDO .................................................................................157 CONFIG6L (Configuration 6 Low) ............................246 Serial Clock, SCK ............................................................157 CONFIG7H (Configuration 7 High) ..........................249 Serial Communication Interface. See USART. CONFIG7L (Configuration 7 Low) ............................248 Serial Data In, SDI ...........................................................157 CVRCON (Comparator Voltage Reference Control) 229 Serial Data Out, SDO ......................................................157 Device ID 1 ..............................................................249 Serial Peripheral Interface. See SPI Device ID 2 ..............................................................249 SETF ...............................................................................293 EECON1 (Data EEPROM Control 1) ...................63, 80 Slave Select, SS ..............................................................157 INTCON (Interrupt Control) ........................................89 SLEEP .............................................................................294 INTCON2 (Interrupt Control 2) ...................................90 Sleep .......................................................................239, 252 INTCON3 (Interrupt Control 3) ...................................91 Software Simulator (MPLAB SIM) ...................................303 IPR1 (Peripheral Interrupt Priority 1) ..........................98 Special Event Trigger. See Compare IPR2 (Peripheral Interrupt Priority 2) ..........................99 Special Features of the CPU ...........................................239 IPR3 (Peripheral Interrupt Priority 3) ........................100 Configuration Registers ...................................240–249 LVDCON (Low-Voltage Detect Control) ...................235 Special Function Registers ................................................47 MEMCON (Memory Control) ......................................71 Map ............................................................................50 OSCCON ...................................................................25 SPI PIE1 (Peripheral Interrupt Enable 1) ..........................95 Serial Clock .............................................................157 PIE2 (Peripheral Interrupt Enable 2) ..........................96 Serial Data In ...........................................................157 PIE3 (Peripheral Interrupt Enable 3) ..........................97 Serial Data Out ........................................................157 PIR1 (Peripheral Interrupt Request 1) .......................92 Slave Select .............................................................157 PIR2 (Peripheral Interrupt Request 2) .......................93 SPI Mode .................................................................157 PIR3 (Peripheral Interrupt Request 3) .......................94 SPI Master/Slave Connection ..........................................161 PSPCON (Parallel Slave Port Control) Register ......129 SPI Module RCON ........................................................................31 Associated Registers ...............................................165 RCON (Reset Control) .......................................60, 101 Bus Mode Compatibility ...........................................165 RCSTAx (Receive Status and Control) ....................199 SSPCON2 (MSSP Control 2, I2C Mode) .................169 Effects of a Reset ....................................................165 SSPSTAT (MSSP Status, I2C Mode) .......................167 Master/Slave Connection ........................................161 Slave Mode ..............................................................163 SSPSTAT (MSSP Status, SPI Mode) ......................158 Sleep Operation .......................................................165 Statis ..........................................................................59 SS ....................................................................................157 STKPTR (Stack Pointer) ............................................43 SSP Summary ..............................................................52–55 TMR2 Output for Clock Shift ............................141, 142 T1CON (Timer 1 Control) .........................................135 TMR4 Output for Clock Shift ....................................148 T3CON (Timer3 Control) ..........................................143 SSPOV Status Flag .........................................................187 TXSTAx (Transmit Status and Control) ...................198 SSPSTAT Register WDTCON (Watchdog Timer Control) ......................250 R/W Bit ............................................................170, 171 RESET .............................................................................289 Status Bits Reset ..........................................................................29, 239 Significance and Initialization Condition for RCON Reg-  2003-2013 Microchip Technology Inc. DS39609C-page 371

PIC18F6520/8520/6620/8620/6720/8720 ister ....................................................................31 Bus Collision During a Repeated Start Condition (Case SUBFWB ..........................................................................294 2) .....................................................................194 SUBLW ............................................................................295 Bus Collision During a Stop Condition (Case 1) ......195 SUBWF ............................................................................295 Bus Collision During a Stop Condition (Case 2) ......195 SUBWFB ..........................................................................296 Bus Collision During Start Condition (SCL = 0) .......193 SWAPF ............................................................................296 Bus Collision During Start Condition (SDA only) .....192 Bus Collision for Transmit and Acknowledge ..........191 T Capture/Compare/PWM (All CCP Modules) ............326 Table Pointer Operations (table) ........................................64 CLKO and I/O ..........................................................321 TBLRD .............................................................................297 Clock Synchronization .............................................177 TBLWT .............................................................................298 Clock/Instruction Cycle ..............................................44 Time-out in Various Situations ...........................................31 Example SPI Master Mode (CKE = 0) .....................328 Timer0 ..............................................................................131 Example SPI Master Mode (CKE = 1) .....................329 16-bit Mode Timer Reads and Writes ......................133 Example SPI Slave Mode (CKE = 0) .......................330 Associated Registers ...............................................133 Example SPI Slave Mode (CKE = 1) .......................331 Clock Source Edge Select (T0SE Bit) ......................133 External Clock (All Modes except PLL) ...................320 Clock Source Select (T0CS Bit) ...............................133 External Memory Bus for Sleep (Microprocessor Mode) Operation .................................................................133 77 Overflow Interrupt ....................................................133 External Memory Bus for TBLRD (Extended Microcon- Prescaler. See Prescaler, Timer0 troller Mode) ......................................................76 Timer0 and Timer1 External Clock Requirements ...........326 External Memory Bus for TBLRD (Microprocessor Mode) Timer1 ..............................................................................135 ............................................................................76 16-bit Read/Write Mode ...........................................138 I2C Bus Data ............................................................333 Associated Registers ...............................................139 I2C Bus Start/Stop Bits ............................................332 Operation .................................................................136 I2C Master Mode (7 or 10-bit Transmission) ............188 Oscillator ..........................................................135, 137 I2C Master Mode (7-bit Reception) ..........................189 Overflow Interrupt ............................................135, 138 I2C Master Mode First Start Bit Timing ....................185 Special Event Trigger (CCP) ............................138, 152 I2C Slave Mode (10-bit Reception, SEN = 0) ..........174 TMR1H Register ......................................................135 I2C Slave Mode (10-bit Reception, SEN = 1) ..........179 TMR1L Register .......................................................135 I2C Slave Mode (10-bit Transmission) .....................175 Use as a Real-Time Clock .......................................138 I2C Slave Mode (7-bit Reception, SEN = 0) ............172 Timer2 ..............................................................................141 I2C Slave Mode (7-bit Reception, SEN = 1) ............178 Associated Registers ...............................................142 I2C Slave Mode (7-bit Transmission) .......................173 Operation .................................................................141 Low-Voltage Detect .................................................236 Postscaler. See Postscaler, Timer2 Master SSP I2C Bus Data ........................................335 PR2 Register ....................................................141, 154 Master SSP I2C Bus Start/Stop Bits ........................335 Prescaler. See Prescaler, Timer2 Parallel Slave Port (PIC18F8X20) ...........................327 SSP Clock Shift ................................................141, 142 Program Memory Read ...........................................322 TMR2 Register .........................................................141 Program Memory Write ............................................323 TMR2 to PR2 Match Interrupt ..................141, 142, 154 PWM Output ............................................................154 Timer3 ..............................................................................143 Repeat Start Condition ............................................186 Associated Registers ...............................................145 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer Operation .................................................................144 (OST) and Power-up Timer (PWRT) ...............324 Oscillator ..........................................................143, 145 Slave Mode General Call Address Sequence (7 or 10-bit Overflow Interrupt ............................................143, 145 Address Mode) ................................................180 Special Event Trigger (CCP) ....................................145 Slave Synchronization .............................................163 TMR3H Register ......................................................143 Slow Rise Time (MCLR Tied to VDD via 1 kOhm Resistor) TMR3L Register .......................................................143 ............................................................................38 Timer4 ..............................................................................147 SPI Mode (Master Mode) .........................................162 Associated Registers ...............................................148 SPI Mode (Slave Mode with CKE = 0) .....................164 Operation .................................................................147 SPI Mode (Slave Mode with CKE = 1) .....................164 Postscaler. See Postscaler, Timer4 Stop Condition Receive or Transmit Mode ..............190 PR4 Register ............................................................147 Synchronous Reception (Master Mode, SREN) ......210 Prescaler. See Prescaler, Timer4 Synchronous Transmission .....................................209 SSP Clock Shift ........................................................148 Synchronous Transmission (Through TXEN) ..........209 TMR4 Register .........................................................147 Time-out Sequence on POR w/PLL Enabled (MCLR Tied TMR4 to PR4 Match Interrupt ..........................147, 148 to VDD via 1 kOhm Resistor) .............................38 Timing Diagrams Time-out Sequence on Power-up (MCLR Not Tied to A/D Conversion ........................................................338 VDD) Acknowledge Sequence ..........................................190 Case 1 ...............................................................37 Baud Rate Generator with Clock Arbitration ............184 Case 2 ...............................................................37 BRG Reset Due to SDA Arbitration During Start Condi- Time-out Sequence on Power-up (MCLR Tied to VDD via tion ...................................................................193 1 kOhm Resistor) ...............................................37 Brown-out Reset (BOR) ...........................................325 Timer0 and Timer1 External Clock ..........................325 Bus Collision During a Repeated Start Condition (Case Timing for Transition Between Timer1 and OSC1 (HS 1) ......................................................................194 DS39609C-page 372  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 with PLL) ............................................................27 Time-out Period .......................................................250 Transition Between Timer1 and OSC1 (HS, XT, LP) .26 WCOL ..............................................................................185 Transition Between Timer1 and OSC1 (RC, EC) .......27 WCOL Status Flag ...................................185, 186, 187, 190 Transition from OSC1 to Timer1 Oscillator ................26 WDT Postscaler ...............................................................250 USART Asynchronous Reception ............................207 WWW Address ................................................................375 USART Asynchronous Transmission .......................205 WWW, On-Line Support ......................................................5 USART Asynchronous Transmission (Back to Back) .... X 205 USART Synchronous Receive ( Master/Slave) .......337 XORLW ...........................................................................299 USART SynchronousTransmission (Master/Slave) .337 XORWF ...........................................................................300 Wake-up from Sleep via Interrupt ............................253 TRISE Register PSPMODE Bit ..................................................111, 128 TSTFSZ ...........................................................................299 Two-Word Instructions Example Cases ..........................................................46 TXSTA Register BRGH Bit .................................................................200 U Universal Synchronous Asynchronous Receiver Transmitter. See USART USART Asynchronous Mode ................................................204 Associated Registers, Receive ........................207 Associated Registers, Transmit .......................205 Receiver ...........................................................206 Setting up 9-bit Mode with Address Detect ......206 Transmitter .......................................................204 Baud Rate Generator (BRG) ....................................200 Associated Registers .......................................200 Baud Rate Error, Calculating ...........................200 Baud Rate Formula ..........................................200 Baud Rates for Asynchronous Mode (BRGH = 0) . 202 Baud Rates for Asynchronous Mode (BRGH = 1) . 203 Baud Rates for Synchronous Mode .................201 High Baud Rate Select (BRGH Bit) .................200 Sampling ..........................................................200 Serial Port Enable (SPEN Bit) ..................................197 Synchronous Master Mode ......................................208 Associated Registers, Reception .....................210 Associated Registers, Transmit .......................208 Reception .........................................................210 Transmission ...................................................208 Synchronous Slave Mode ........................................211 Associated Registers, Receive ........................212 Associated Registers, Transmit .......................211 Reception .........................................................212 Transmission ...................................................211 USART Synchronous Receive Requirements .................337 USART Synchronous Transmission Requirements .........337 V Voltage Reference Specifications ....................................315 W Wake-up from Sleep ................................................239, 252 Using Interrupts ........................................................252 Watchdog Timer (WDT) ...........................................239, 250 Associated Registers ...............................................251 Control Register .......................................................250 Postscaler ................................................................251 Programming Considerations ..................................250 RC Oscillator ............................................................250  2003-2013 Microchip Technology Inc. DS39609C-page 373

PIC18F6520/8520/6620/8620/6720/8720 DS39609C-page 374  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or field application engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2003-2013 Microchip Technology Inc. DS39609C-page 375

PIC18F6520/8520/6620/8620/6720/8720 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F6520/8520/6620/8620/6720/8720 Literature Number: DS39609C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39609C-page 376  2003-2013 Microchip Technology Inc.

PIC18F6520/8520/6620/8620/6720/8720 PIC18F6520/8520/6620/8620/6720/8720 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.  X /XX XXX Examples: Device Temperature Package Pattern a) PIC18LF6620-I/PT 301 = Industrial temp., Range TQFP package, Extended VDD limits, QTP pattern #301. b) PIC18F8720-I/PT = Industrial temp., Device PIC18F6520/8520/6620/8620/6720/8720(1), TQFP package, normal VDD limits. PIC18F6520/8520/6620/8620/6720/8720T(2); c) PIC18F8620-E/PT = Extended temp., VDD range 4.2V to 5.5V TQFP package, standard VDD limits. PIC18LF6520/8520/6620/8620/6720/8720(1), PIC18LF6520/8520/6620/8620/6720/8720T(2); VDD range 2.0V to 5.5V Temperature I = -40C to +85C (Industrial) Range E = -40C to +125C (Extended) Note 1: F = Standard Voltage Range LF = Extended Voltage Range Package PT = TQFP (Thin Quad Flatpack) 2: T = in tape and reel Pattern QTP, SQTP, Code or Special Requirements (blank otherwise)  2003-2013 Microchip Technology Inc. DS39609C-page 377

PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 378  2003-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2003-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769423 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2003-2013 Microchip Technology Inc. DS39609C-page 379

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18LF8520-I/PTG PIC18LF6720T-I/PT PIC18F6720T-I/PT PIC18F6620T-I/PT PIC18F8720T-E/PT PIC18LF8520T-I/PT PIC18F8620T-E/PT PIC18LF6520T-I/PTG PIC18LF6620T-I/PT PIC18LF8620T-I/PT PIC18F8520-I/PTG PIC18F6520T-I/PTG PIC18F6520T-E/PT PIC18LF6620-I/PT PIC18LF6720-I/PT PIC18LF6520- I/PT PIC18F8620T-I/PT PIC18F8620-E/PT PIC18F8520-E/PT PIC18F8720-E/PT PIC18F8720T-I/PT PIC18F6620- E/PT PIC18F6520-E/PT PIC18F6720-E/PT PIC18LF8620-I/PT PIC18LF8520-I/PT PIC18F8520T-I/PT PIC18F8520- I/PT PIC18F8620-I/PT PIC18F8720-I/PT PIC18F6620-I/PT PIC18F6720-I/PT PIC18F6520-I/PT PIC18F6720T-E/PT PIC18LF8520T-I/PTG PIC18LF8720T-I/PT PIC18LF8720-I/PT PIC18LF6520-I/PTG PIC18F6520T-I/PT PIC18F8520T-E/PT PIC18F6520-I/PTG PIC18LF6520T-I/PT PIC18F8520T-I/PTG