PIC18F87K22 FAMILY 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash MCUs with 12-Bit A/D and XLP Technology Low-Power Features: Special Microcontroller Features: • Power-Managed modes: • Operating Voltage Range: 1.8V to 5.5V - Run: CPU on, peripherals on • On-Chip 3.3V Regulator - Idle: CPU off, peripherals on • Operating Speed up to 64MHz - Sleep: CPU off, peripherals off • Up to 128Kbytes On-Chip Flash Program • Two-Speed Oscillator Start-up Memory • Fail-Safe Clock Monitor • Data EEPROM of 1,024 Bytes • Power-Saving Peripheral Module Disable (PMD) • 4K x 8 General Purpose Registers (SRAM) • Ultra Low-Power Wake-up • 10,000 Erase/Write Cycle Flash Program • Fast Wake-up, 1s Typical Memory, Minimum • Low-Power WDT, 300nA Typical • 1,000,000 Erase/write Cycle Data EEPROM Memory, Typical • Ultra Low 50nA Input Leakage • Flash Retention: 40 Years, Minimum • Run mode Currents Down to 5.5 A, Typical • Three Internal Oscillators: LF-INTRC (31kHz), • Idle mode Currents Down to 1.7 A Typical MF-INTOSC (500kHz) and HF-INTOSC • Sleep mode Currents Down to Very Low 20 nA, (16MHz) Typical • Self-Programmable under Software Control • RTCC Current Downs to Very Low 700 nA, • Priority Levels for Interrupts Typical • 8 x 8 Single-Cycle Hardware Multiplier • Extended Watchdog Timer (WDT): - Programmable period from 4ms to 4,194s (about 70 minutes) • In-Circuit Serial Programming™ (ICSP™) via Two Pins • In-Circuit Debug via Two Pins • Programmable: - BOR - LVD Device (FbylPatserohsg)ra#Im nSs iMntrgeulmce-toWiorynosrd ( SbyRDtAaetsMa) MEe(EbmPyoRterOys)M I/O 1(A2c-/hBD)i t (EPCCWCCPMP/) SMPSISPMaI2sCter EUSART omparators Timers8/16-Bit xternal Bus CTMU RTCC C E PIC18F65K22 32K 16,383 2K 1K 53 16 5/3 2 Y Y 2 3 4/4 N Y Y PIC18F66K22 64K 32,768 4K 1K 53 16 7/3 2 Y Y 2 3 6/5 N Y Y PIC18F67K22 128K 65,536 4K 1K 53 16 7/3 2 Y Y 2 3 6/5 N Y Y PIC18F85K22 32K 16,383 2K 1K 69 24 5/3 2 Y Y 2 3 4/4 Y Y Y PIC18F86K22 64K 32,768 4K 1K 69 24 7/3 2 Y Y 2 3 6/5 Y Y Y PIC18F87K22 128K 65,536 4K 1K 69 24 7/3 2 Y Y 2 3 6/5 Y Y Y  2009-2018 Microchip Technology Inc. DS30009960F-page 1

PIC18F87K22 FAMILY Peripheral Highlights: • Charge Time Measurement Unit (CTMU): • Up to Ten CCP/ECCP modules: - Capacitance measurement for mTouch® sensing solution - Up to seven Capture/Compare/PWM (CCP) modules - Time measurement with 1 ns typical resolution - Three Enhanced Capture/Compare/PWM (ECCP) modules - Integrated temperature sensor • Up to Eleven 8/16-Bit Timer/Counter modules: • High-Current Sink/Source 25 mA/25 mA - Timer0 – 8/16-bit timer/counter with 8-bit (PORTB and PORTC) programmable prescaler • Up to Four External Interrupts - Timer1,3 – 16-bit timer/counter • Two Master Synchronous Serial Port (MSSP) - Timer2,4,6,8 – 8-bit timer/counter modules: - Timer5,7 – 16-bit timer/counter for 64k and - 3/4-wire SPI (supports all four SPI modes) 128k parts - I2C Master and Slave modes - Timer10,12 – 8-bit timer/counter for 64k and • Two Enhanced Addressable USART modules: 128k parts - LIN/J2602 support • Three Analog Comparators - Auto-Baud Detect (ABD) • Configurable Reference Clock Output • 12-Bit A/D Converter with up to 24 Channels: • Hardware Real-Time Clock and Calendar (RTCC) - Auto-acquisition and Sleep operation module with Clock, Calendar and Alarm Functions - Differential input mode of operation • Integrated Voltage Reference DS30009960F-page 2  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY Pin Diagrams – PIC18F6XK22 64-Pin TQFP, QFN (2)S/P2B/CCP10(2)3C/CCP9/REF0 3B/CCP8 1C/CCP7 1B/CCP6 CCP2/P2A SP0/CTPLS SP1/T5CKI/T7G SP2 SP3 SP4/SDO2 SP5/SDI2/SDA2 SP6/SCK2/SCL2 SP7/SS2 C P P P P E P P P P P P P P E2/ E3/ E4/ E5/ E6/ E7/ D0/ DD SS D1/ D2/ D3/ D4/ D5/ D6/ D7/ R R R R R R R V V R R R R R R R 64636261 6059 58575655 54535251 5049 RE1/WR/P2C 1 48 RB0/INT0/FLT0 RE0/RD/P2D 2 47 RB1/INT1 RG0/ECCP3/P3A 3 46 RB2/INT2/CTED1 RG1/TX2/CK2/AN19/C3OUT 4 45 RB3/INT3/CTED2/ECCP2(1)/PA2 RG2/RX2/DT2/AN18/C3INA 5 44 RB4/KBI0 RG3/CCP4/AN17/P3D/C3INB 6 43 RB5/KBI1/T3CKI/T1G MCLR/RG5 7 PIC18F65K22 42 RB6/KBI2/PGC RG4/RTCC/T7CKI(2)/T5G/CCP5/AN16/P1D/C3INC 8 PIC18F66K22 41 VSS VSS 9 PIC18F67K22 40 OSC2/CLKO/RA6 VDDCORE/VCAP 10 39 OSC1/CLKI/RA7 RF7/AN5/SS1 11 38 VDD RF6/AN11/C1INA 12 37 RB7/KBI3/PGD RF5/AN10/CVREF/C1INB 13 36 RC5/SDO1 RF4/AN9/C2INA 14 35 RC4/SDI1/SDA1 RF3/AN8/C2INB/CTMUI 15 34 RC3/SCK1/SCL1 RF2/AN7/C1OUT 16 33 RC2/ECCP1/P1A 17181920212223242526 2728 2930 31 32 N6/C2OUT/CTDIN ENVREG AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0/ULPWU VSS VDD 1CKI/T3G/HLVDIN RA4/T0CKI(1)SCI/ECCP2/P2A C0/SOSCO/SCLKI RC6/TX1/CK1 RC7/RX1/DT1 A T O R 1/ 4/ S RF 5/AN RC1/ A R Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting and whether the device is in Microcontroller or Extended Microcontroller mode. 2: Not available on the PIC18F65K22 and PIC18F85K22 devices.  2009-2018 Microchip Technology Inc. DS30009960F-page 3

PIC18F87K22 FAMILY Pin Diagrams – PIC18F8XK22 80-Pin TQFP 1 1 H1/AN22/A17H0/AN23/A16(2)E2/P2B/CCP10/CS/AD10(2,3)/E3/P3C/CCP9REF0/AD(3)/AD12E4/P3B/CCP8(3)E5/P1C/CCP7/AD13(3)E6/P1B/CCP6/AD14E7/ECCP2/P2A/AD15D0/PSP0/CTPLS/AD0 DD SSD1/T5CKI/T7G/PSP1/AD1D2/PSP2/AD2D3/PSP3/AD3D4/SDO2/PSP4/AD4D5/SDI2/SDA2/PSP5/AD5D6/SCK2/SCL2/PSP6/AD6D7/SS2/PSP7/AD7J0/ALEJ1/OE RRRRRRRRRVVRRRRRRRRR 8079787776757473727170696867666564636261 RH2/AN21/A18 1 60 RJ2/WRL RH3/AN20/A19 2 59 RJ3/WRH RE1/P2C/WR/AD9 3 58 RB0/INT0/FLT0 RE0/P2D/RD/AD8 4 57 RB1/INT1 RG0/ECCP3/P3A 5 56 RB2/INT2/CTED1 RG1/TX2/CK2/AN19/C3OUT 6 55 RB3/INT3/CTED2/ECCP2(1)/P2A RG2/RX2/DT2/AN18/C3INA 7 54 RB4/KBI0 RG3/CCP4/AN17/P3D/C3INB 8 53 RB5/KBI1/T3CKI/T1G MCLR/RG5 9 PIC18F85K22 52 RB6/KBI2/PGC RG4/RTCC/T7CKI(2)/T5G/CCP5/AN16/P1D/C3INC 10 PIC18F86K22 51 VSS VSS 11 PIC18F87K22 50 OSC2/CLKO/RA6 VDDCORE/VCAP 12 49 OSC1/CLKI/RA7 RF7/AN5/SS1 13 48 VDD RF6/AN11/C1INA 14 47 RB7/KBI3/PGD RF5/AN10/C1INB 15 46 RC5/SDO1 RF4/AN9/C2INA 16 45 RC4/SDI1/SDA1 RF3/AN8/C2INB/CTMUI 17 44 RC3/SCK1/SCL1 RF2/AN7/C1OUT 18 43 RC2/ECCP1/P1A RH7/CCP6(3)/P1B/AN15 19 42 RJ7/UB RH6/CCP7(3)/P1C/AN14/C1INC 20 41 RJ6/LB 2122232425262728293031323334353637383940 (3)CP8/P3B/AN13/C2IND(2,3)P9/P3C/AN12/C2INCRF1/AN6/C2OUT/CTDINENVREGAVDDAVSSRA3/AN3/V+REFRA2/AN2/V-REF RA1/AN1RA0/AN0/ULPWUVSSVDD AN4/T1CKI/T3G/HLVDINRA4/T0CKIRC1/SOSC/ECCP2/P2ARC0/SOSCO/SCKLIRC6/TX1/CK1RC7/RX1/DT1RJ4/BA0RJ5/CE CC 5/ H5/4/C RA RH R Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting and whether the device is in Microcontroller or Extended Microcontroller mode. 2: Not available on the PIC18F65K22 and PIC18F85K22 devices. 3: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 4  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY Table of Contents 1.0 Device Overview..........................................................................................................................................................................7 2.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers.........................................................................................35 3.0 Oscillator Configurations............................................................................................................................................................40 4.0 Power-Managed Modes.............................................................................................................................................................54 5.0 Reset..........................................................................................................................................................................................69 6.0 Memory Organization.................................................................................................................................................................83 7.0 Flash Program Memory............................................................................................................................................................107 8.0 External Memory Bus...............................................................................................................................................................117 9.0 Data EEPROM Memory...........................................................................................................................................................128 10.0 8 x 8 Hardware Multiplier..........................................................................................................................................................134 11.0 Interrupts..................................................................................................................................................................................136 12.0 I/O Ports...................................................................................................................................................................................160 13.0 Timer0 Module.........................................................................................................................................................................187 14.0 Timer1 Module.........................................................................................................................................................................190 15.0 Timer2 Module.........................................................................................................................................................................202 16.0 Timer3/5/7 Modules..................................................................................................................................................................204 17.0 Timer4/6/8/10/12 Modules........................................................................................................................................................216 18.0 Real-Time Clock and Calendar (RTCC)...................................................................................................................................219 19.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................236 20.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................249 21.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................272 22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................318 23.0 12-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................342 24.0 Comparator Module..................................................................................................................................................................358 25.0 Comparator Voltage Reference Module...................................................................................................................................366 26.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................369 27.0 Charge Time Measurement Unit (CTMU)................................................................................................................................375 28.0 Special Features of the CPU....................................................................................................................................................392 29.0 Instruction Set Summary..........................................................................................................................................................419 30.0 Development Support...............................................................................................................................................................469 31.0 Electrical Characteristics..........................................................................................................................................................473 32.0 Packaging Information..............................................................................................................................................................515 Appendix A: Revision History.............................................................................................................................................................523 Appendix B: Migration From PIC18F87J11 and PIC18F8722 to PIC18F87K22................................................................................524 The Microchip WebSite......................................................................................................................................................................525 Customer Change Notification Service..............................................................................................................................................525 Customer Support..............................................................................................................................................................................525  2009-2018 Microchip Technology Inc. DS30009960F-page 5

PIC18F87K22 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS30009960F-page 6  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 1.0 DEVICE OVERVIEW • An internal oscillator block that provides a 16 MHz clock (±2% accuracy) and an INTRC source This document contains device-specific information for (approximately 31kHz, stable over temperature the following devices: and VDD) • PIC18F65K22 • PIC18F85K22 - Operates as HF-INTOSC or MF-INTOSC • PIC18F66K22 • PIC18F86K22 when block selected for 16MHz or 500kHz • PIC18F67K22 • PIC18F87K22 - Frees the two oscillator pins for use as additional general purpose I/O This family combines the traditional advantages of all PIC18 microcontrollers – namely, high computational The internal oscillator block provides a stable reference performance and a rich feature set – with an extremely source that gives the family additional features for competitive price point. These features make the robust operation: PIC18F87K22 family a logical choice for many • Fail-Safe Clock Monitor: This option constantly high-performance applications where price is a primary monitors the main clock source against a reference consideration. signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the 1.1 Core Features internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.1 XLP TECHNOLOGY • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source All of the devices in the PIC18F87K22 family incorpo- from Power-on Reset, or wake-up from Sleep rate a range of features that can significantly reduce mode, until the primary clock source is available. power consumption during operation. Key items include: • Alternate Run Modes: By clocking the controller 1.1.3 MEMORY OPTIONS from the Timer1 source or the Internal RC oscilla- The PIC18F87K22 family provides ample room for tor, power consumption during code execution application code, from 32Kbytes to 128Kbytes of code can be reduced. space. The Flash cells for program memory are rated • Multiple Idle Modes: The controller can also run to last up to 10,000 erase/write cycles. Data retention with its CPU core disabled but the peripherals still without refresh is conservatively estimated to be active. In these states, power consumption can be greater than 40 years. reduced even further. The Flash program memory is readable and writable. • On-the-Fly Mode Switching: The power-managed During normal operation, the PIC18F87K22 family also modes are invoked by user code during operation, provides plenty of room for dynamic application data allowing the user to incorporate power-saving ideas with up to 3,862bytes of data RAM. into their application’s software design. • XLP: An extra low-power Sleep, BOR, RTCC and 1.1.4 EXTERNAL MEMORY BUS Watchdog Timer Should 128Kbytes of memory be inadequate for an 1.1.2 OSCILLATOR OPTIONS AND application, the 80-pin members of the PIC18F87K22 family have an External Memory Bus (EMB) enabling FEATURES the controller’s internal Program Counter to address a All of the devices in the PIC18F87K22 family offer memory space of up to 2Mbytes. This is a level of data different oscillator options, allowing users a range of access that few 8-bit devices can claim and enables: choices in developing application hardware. These • Using combinations of on-chip and external include: memory of up to 2 Mbytes • External Resistor/Capacitor (RC); RA6 available • Using external Flash memory for reprogrammable • External Resistor/Capacitor with Clock Out application code or large data tables (RCIO) • Using external RAM devices for storing large • Three External Clock modes: amounts of variable data - External Clock (EC); RA6 available - External Clock with Clock Out (ECIO) 1.1.5 EXTENDED INSTRUCTION SET - External Crystal (XT, HS, LP) The PIC18F87K22 family implements the optional • A Phase Lock Loop (PLL) frequency multiplier, extension to the PIC18 instruction set, adding eight available to the External Oscillator modes, which new instructions and an Indexed Addressing mode. allows clock speeds of up to 64MHz. PLL can Enabled as a device configuration option, the extension also be used with the internal oscillator. has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as ‘C’.  2009-2018 Microchip Technology Inc. DS30009960F-page 7

PIC18F87K22 FAMILY 1.1.6 EASY MIGRATION • 12-Bit A/D Converter: The PIC18F87K22 family has differential ADC. It incorporates program- All devices share the same rich set of peripherals mable acquisition time, allowing for a channel to except that the devices with 32 Kbytes of program be selected and a conversion to be initiated memory (PIC18F65K22 and PIC18F85K22) have two without waiting for a sampling period, and thus, less CCPs and three less timers. This provides a reducing code overhead. smooth migration path within the device family as applications evolve and grow. • Charge Time Measurement Unit (CTMU): The CTMU is a flexible analog module that provides The consistent pinout scheme, used throughout the accurate differential time measurement between entire family, also aids in migrating to the next larger pulse sources, as well as asynchronous pulse device. This is true when moving between the 64-pin generation. members, between the 80-pin members, or even • Together with other on-chip analog modules, the jumping from 64-pin to 80-pin devices. CTMU can precisely measure time, measure All of the devices in the family share the same rich set capacitance or relative changes in capacitance, or of peripherals, except for those with 32 Kbytes of generate output pulses that are independent of program memory (PIC18F65K22 and PIC18F85K22). the system clock. Those devices have two less CCPs and three less • LP Watchdog Timer (WDT): This enhanced timers. version incorporates a 22-bit prescaler, allowing The PIC18F87K22 family is also largely pin compatible an extended time-out range that is stable across with other PIC18 families, such as the PIC18F8720 and operating voltage and temperature. See PIC18F8722 and the PIC18F85J11. This allows a new Section31.0 “Electrical Characteristics” for dimension to the evolution of applications, allowing time-out periods. developers to select different price points within • Real-Time Clock and Calendar Module Microchip’s PIC18 portfolio, while maintaining a similar (RTCC): The RTCC module is intended for appli- feature set. cations requiring that accurate time be maintained for extended periods of time with minimum to no 1.2 Other Special Features intervention from the CPU. • The module is a 100-year clock and calendar with • Communications: The PIC18F87K22 family automatic leap year detection. The range of the incorporates a range of serial communication clock is from 00:00:00 (midnight) on January 1, peripherals, including two Enhanced USARTs 2000 to 23:59:59 on December 31, 2099. (EUSART) that support LIN/J2602, and two Master SSP modules, capable of both SPI and I2C (Master and Slave) modes of operation. • CCP Modules: PIC18F87K22 family devices incorporate up to seven Capture/Compare/PWM (CCP) modules. Up to six different time bases can be used to perform several different operations at once. • ECCP Modules: The PIC18F87K22 family has three Enhanced CCP (ECCP) modules to maximize flexibility in control applications: - Up to eight different time bases for performing several different operations at once - Up to four PWM outputs for each module, for a total of 12 PWMs - Other beneficial features, such as polarity selection, programmable dead time, auto-shutdown and restart, and Half-Bridge and Full-Bridge Output modes DS30009960F-page 8  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 1.3 Details on Individual Family • CCP modules: Members - PIC18FX5K22 (PIC18F65K22 and PIC18F85K22) – five CCP modules Devices in the PIC18F87K22 family are available in - PIC18FX6K22 and PIC18FX7K22 64-pin and 80-pin packages. Block diagrams for the (PIC18F66K22, PIC18F86K22, two groups are shown in Figure1-1 and Figure1-2. PIC18F67K22, and PIC18F87K22) – The devices are differentiated from each other in these seven CCP modules ways: • Timer modules: • Flash Program Memory: - PIC18FX5K22 (PIC18F65K22 and PIC18F85K22) – Four 8-bit timer/counters - PIC18FX5K22 (PIC18F65K22 and and four 16-bit timer/counters PIC18F85K22) – 32 Kbytes - PIC18FX6K22 and PIC18FX7K22 - PIC18FX6K22 (PIC18F66K22 and (PIC18F66K22, PIC18F86K22, PIC18F86K22) – 64 Kbytes PIC18F67K22, and PIC18F87K22) – Six 8-bit - PIC18FX7K22 (PIC18F67K22 and timer/counters and five 16-bit timer/counters PIC18F87K22) – 128 Kbytes • A/D Channels: • Data RAM: - PIC18F6XK22 (64-pin devices) – 24 channels - All devices except PIC18FX5K22 – 4 Kbytes - PIC18F8XK22 (80-pin devices) – 16 channels - PIC18FX5K22 – 2 Kbytes All other features for devices in this family are identical. • I/O Ports: These are summarized in Table1-1 and Table1-2. - PIC18F6XK22 (64-pin devices) – seven bidirectional ports The pinouts for all devices are listed in Table1-3 and Table1-4. - PIC18F8XK22 (80-pin devices) – nine bidirectional ports  2009-2018 Microchip Technology Inc. DS30009960F-page 9

PIC18F87K22 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F6XK22 (64-PIN DEVICES) Features PIC18F65K22 PIC18F66K22 PIC18F67K22 Operating Frequency DC – 64 MHz Program Memory (Bytes) 32K 64K 128K Program Memory (Instructions) 16,384 32,768 65,536 Data Memory (Bytes) 2K 4K 4K Interrupt Sources 42 48 I/O Ports Ports A, B, C, D, E, F, G Parallel Communications Parallel Slave Port (PSP) Timers 8 11 Comparators 3 CTMU Yes RTCC Yes Capture/Compare/PWM (CCP) Modules 5 7 7 Enhanced CCP (ECCP) Modules 3 Serial Communications Two MSSPs and two Enhanced USARTs (EUSART) 12-Bit Analog-to-Digital Module 16 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 64-Pin QFN, 64-Pin TQFP TABLE 1-2: DEVICE FEATURES FOR THE PIC18F8XK22 (80-PIN DEVICES) Features PIC18F85K22 PIC18F86K22 PIC18F87K22 Operating Frequency DC – 64 MHz 32K 64K 128K Program Memory (Bytes) (Up to 2Mbytes with Extended Memory) Program Memory (Instructions) 16,384 32,768 65,536 Data Memory (Bytes) 2K 4K 4K Interrupt Sources 42 48 I/O Ports Ports A, B, C, D, E, F, G, H, J Parallel Communications Parallel Slave Port (PSP) Timers 8 11 Comparators 3 CTMU Yes RTCC Yes Capture/Compare/PWM (CCP) Modules 5 7 7 Enhanced CCP (ECCP) Modules 3 Serial Communications Two MSSPs and 2 Enhanced USARTs (EUSART) 12-Bit Analog-to-Digital Module 24 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 80-Pin TQFP DS30009960F-page 10  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 1-1: PIC18F6XK22 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch inc/dec logic 8 8 RA0:RA7(1,2) Data Memory (2/4 Kbytes) 21 PCLAT U PCLATH 20 Address Latch PCU PCH PCL Program Counter 12 PORTB Data Address<12> RB0:RB7(1) 31-Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank FSR1 Data Latch FSR2 12 PORTC inc/dec RC0:RC7(1) 8 logic Table Latch Address ROM Latch Instruction Bus <16> Decode PORTD IR RD0:RD7(1) 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL PORTE RE0: RE7(1) 8 x 8 Multiply OSC2/CLKO GeTnimeriantgion Power-up 3 8 OSC1/CLKI Timer BITOP W OIsNcTilRlaCtor StaOrts-cuipll aTtiomrer 8 8 8 16 MHz Oscillator Power-on 8 8 PORTF Reset RF1:RF7(1) Precision ALU<8> Band Gap Watchdog Reference Timer 8 ENVREG BOR and Voltage LVD Regulator PORTG RG0:RG5(1) VDDCORE/VCAP VDD,VSS MCLR Timer Timer ADC Comparator Timer0 Timer1 2/4/6/8/10(3)/12(3) 3/5/7(3) CTMU 12-Bit 1/2/3 CCP ECCP 4/5/6/7/8/9(3)/10(3) 1/2/3 EUSART1 EUSART2 RTCC MSSP1/2 Note 1: See Table1-3 for I/O port pin descriptions. 2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section3.0 “Oscillator Configurations”. 3: Unimplemented on the PIC18F65K22.  2009-2018 Microchip Technology Inc. DS30009960F-page 11

PIC18F87K22 FAMILY FIGURE 1-2: PIC18F8XK22 (80-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch inc/dec logic 8 8 RA0:RA7(1,2) Data Memory (2/4 Kbytes) 21 PCLAT U PCLATH 20 Address Latch PCU PCH PCL PORTB Program Counter 12 RB0:RB7(1) Data Address<12> 31-Level Stack Address Latch 4 12 4 BSR Access PORTC ace Program Memory STKPTR FFSSRR01 Bank RC0:RC7(1) nterf Data Latch FSR2 12 s I u B m inc/dec yste 8 Table Latch logic PORTD S RD0:RD7(1) Address ROM Latch Decode Instruction Bus <16> PORTE IR AD15:0, A19:16 RE0:RE7(1) (Multiplexed with PORTD, PORTE and PORTH) 8 Instruction State Machine Decode and Control Signals Control PORTF PRODH PRODL RF1:RF7(1) 8 x 8 Multiply Timing Power-up 3 8 OSC2/CLKO Generation OSC1/CLKI Timer BITOP W PORTG OIsNcTilRlaCtor StaOrts-cuipll aTtiomrer 8 8 8 RG0:RG5(1) 16 MHz Oscillator Power-on 8 8 Reset BParencdi sGioanp Watchdog ALU<8> PORTH Reference Timer 8 RH0:RH7(1) ENVREG BOR and Voltage Regulator LVD PORTJ VDDCORE/VCAP VDD,VSS MCLR RJ0:RJ7(1) Timer Timer ADC Comparator Timer0 Timer1 2/4/6/8/10(3)/12(3) 3/5/7(3) CTMU 12-Bit 1/2/3 CCP ECCP 4/5/6/7/8/9(3)/10(3) 1/2/3 EUSART1 EUSART2 RTCC MSSP1/2 Note 1: See Table1-3 for I/O port pin descriptions. 2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section3.0 “Oscillator Configurations” for more information. 3: Unimplemented on the PIC18F85K22. DS30009960F-page 12  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type QFN/TQFP 7 Master Clear (input) or programming voltage (input). MCLR/RG5 MCLR I ST This pin is an active-low Reset to the device. RG5 I ST General purpose, input only pin. OSC1/CLKI/RA7 39 Oscillator crystal or external clock input. OSC1 I CMOS Oscillator crystal input. CLKI I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 40 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>).  2009-2018 Microchip Technology Inc. DS30009960F-page 13

PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type QFN/TQFP PORTA is a bidirectional I/O port. RA0/AN0/ULPWU 24 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. ULPWU I Analog Ultra Low-Power Wake-up input. RA1/AN1 23 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF- 22 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 21 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 28 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4/T1CKI/T3G/ 27 HLVDIN RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. T1CKI I ST Timer1 clock input. T3G I ST Timer3 external clock gate input. HLVDIN I Analog High/Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 14  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type QFN/TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLTO 48 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. FLT0 I ST Enhanced PWM Fault input for ECCP1/2/3. RB1/INT1 47 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. RB2/INT2/CTED1 46 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. CTED1 I ST CTMU Edge 1 input. RB3/INT3/CTED2/ 45 ECCP2/P2A RB3 I/O TTL Digital I/O. INT3 I ST External Interrupt 3. CTED2 I ST CTMU Edge 2 input. ECCP2 I/O ST Capture 2 input/Compare 2 output/PWM2. P2A O — Enhanced PWM2 Output A. RB4/KBI0 44 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1/T3CKI/T1G 43 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. T3CKI I ST Timer3 clock input. T1G I ST Timer1 external clock gate input. RB6/KBI2/PGC 42 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 37 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>).  2009-2018 Microchip Technology Inc. DS30009960F-page 15

PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type QFN/TQFP PORTC is a bidirectional I/O port. RC0/SOSCO/SCLKI 30 RC0 I/O ST Digital I/O. SOSCO O — SOSC oscillator output. SCLKI I ST Digital SOSC input. RC1/SOSCI/ECCP2/P2A 29 RC1 I/O ST Digital I/O. SOSCI I CMOS SOSC oscillator input. ECCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A O — Enhanced PWM2 Output A. RC2/ECCP1/P1A 33 RC2 I/O ST Digital I/O. ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O — Enhanced PWM1 Output A. RC3/SCK1/SCL1 34 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1(4) I/O I2C Synchronous serial clock input/output for I2C mode. RC4/SDI1/SDA1 35 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1(4) I/O I2C I2C data I/O. RC5/SDO1 36 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. RC6/TX1/CK1 31 RC6 I/O ST Digital I/O. TX1 O — EUSART asynchronous transmit. CK1 I/O ST EUSART synchronous clock (see related RX1/DT1). RC7/RX1/DT1 32 RC7 I/O ST Digital I/O. RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data (see related TX1/CK1). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 16  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type QFN/TQFP PORTD is a bidirectional I/O port. RD0/PSP0/CTPLS 58 RD0 I/O ST Digital I/O. PSP0 I/O TTL Parallel Slave Port data. CTPLS O — CTMU pulse generator output. RD1/PSP1/T5CKI/T7G 55 RD1 I/O ST Digital I/O. PSP1 I/O TTL Parallel Slave Port. T5CKI I ST Timer5 clock input. T7G I ST Timer7 external clock gate input. RD2/PSP2 54 RD2 I/O ST Digital I/O. PSP2 O TTL Parallel Slave Port. RD3/PSP3 53 RD3 I/O ST Digital I/O. PSP3 I/O TTL Parallel Slave Port. RD4/PSP4/SDO2 52 RD4 I/O ST Digital I/O. PSP4 I/O TTL Parallel Slave Port. SDO2 O — SPI data out. RD5/PSP5/SDI2/SDA2 51 RD5 I/O ST Digital I/O. PSP5 I/O TTL Parallel Slave Port. SDI2 I ST SPI data in. SDA2 I/O I2C I2C data I/O. RD6/PSP6/SCK2/SCL2 50 RD6 I/O ST Digital I/O. PSP6 I/O TTL Parallel Slave Port. SCK2 I/O ST Synchronous serial clock. SCL2(4) I/O I2C Synchronous serial clock I/O for I2C mode. RD7/PSP7/SS2 49 RD7 I/O ST Digital I/O. PSP7 I/O TTL Parallel Slave Port. SS2 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>).  2009-2018 Microchip Technology Inc. DS30009960F-page 17

PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type QFN/TQFP PORTE is a bidirectional I/O port. RE0/RD/P2D 2 RE0 I/O ST Digital I/O. RD I TTL Parallel Slave Port read strobe. P2D O — EECP2 PWM Output D. RE1/WR/P2C 1 RE1 I/O ST Digital I/O. WR I TTL Parallel Slave Port write strobe. P2C O — ECCP2 PWM Output C. RE2/CS/P2B/CCP10 64 RE2 I/O ST Digital I/O. CS I TTL Parallel Slave Port chip select. P2B O — ECCP2 PWM Output B. CCP10(3) I/O S/T Capture 10 input/Compare 10 output/PWM10 output. RE3/P3C/CCP9/REFO 63 RE3 I/O ST Digital I/O. P3C O — ECCP3 PWM Output C. CCP9(3,4) I/O S/T Capture 9 input/Compare 9 output/PWM9 output. REFO O — Reference clock out. RE4/P3B/CCP8 62 RE4 I/O ST Digital I/O. P3B O — ECCP3 PWM Output B. CCP8(4) I/O S/T Capture 8 input/Compare 8 output/PWM8 output. RE5/P1C/CCP7 61 RE5 I/O ST Digital I/O. P1C O — ECCP1 PWM Output C. CCP7(4) I/O S/T Capture 7 input/Compare 7 output/PWM7 output. RE6/P1B/CCP6 60 RE6 I/O ST Digital I/O. P1B O — ECCP1 PWM Output B. CCP6(4 I/O S/T Capture 6 input/Compare 6 output/PWM6 output. RE7/ECCP2/P2A 59 RE7 I/O ST Digital I/O. ECCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A O — ECCP2 PWM Output A. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 18  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type QFN/TQFP PORTF is a bidirectional I/O port. RF1/AN6/C2OUT/CTDIN 17 RF1 I/O ST Digital I/O. AN6 I Analog Analog Input 6. C2OUT O — Comparator 2 output. CTDIN I ST CTMU pulse delay input. RF2/AN7/C1OUT 16 RF2 I/O ST Digital I/O. AN7 I Analog Analog Input 7. C1OUT O — Comparator 1 output. RF3/AN8/C2INB/CTMUI 15 RF3 I/O ST Digital I/O. AN8 I Analog Analog Input 8. C2INB I Analog Comparator 2 Input B. CTMUI O — CTMU pulse generator charger for the C2INB comparator input. RF4/AN9/C2INA 14 RF4 I/O ST Digital I/O. AN9 I Analog Analog Input 9. C2INA I Analog Comparator 2 Input A. RF5/AN10/CVREF/C1INB 13 RF5 I/O ST Digital I/O. AN10 I Analog Analog Input 10. CVREF O Analog Comparator reference voltage output. C1INB I Analog Comparator 1 Input B. RF6/AN11/C1INA 12 RF6 I/O ST Digital I/O. AN11 I Analog Analog Input 11. C1INA I Analog Comparator 1 Input A. RF7/AN5/SS1 11 RF7 I/O ST Digital I/O. AN5 O Analog Analog Input 5. SS1 I TTL SPI1 slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>).  2009-2018 Microchip Technology Inc. DS30009960F-page 19

PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type QFN/TQFP PORTG is a bidirectional I/O port. RG0/ECCP3/P3A 3 RG0 I/O ST Digital I/O. ECCP3 I/O ST Capture 3 input/Compare 3 output/PWM3 output. P3A O — ECCP3 PWM Output A. RG1/TX2/CK2/AN19/ 4 C3OUT RG1 I/O ST Digital I/O. TX2 O — EUSART asynchronous transmit. CK2 I/O ST EUSART synchronous clock (see related RX2/DT2). AN19 I Analog Analog Input 19. C3OUT O — Comparator 3 output. RG2/RX2/DT2/AN18/ 5 C3INA RG2 I/O ST Digital I/O. RX2 I ST EUSART asynchronous receive. DT2 I/O ST EUSART synchronous data (see related TX2/CK2). AN18 I Analog Analog Input 18. C3INA I Analog Comparator 3 Input A. RG3/CCP4/AN17/P3D/ 6 C3INB RG3 I/O ST Digital I/O. CCP4 I/O S/T Capture 4 input/Compare 4 output/PWM4 output. AN17 I Analog Analog Input 18. P3D O — ECCP3 PWM Output D. C3INB I Analog Comparator 3 Input B. RG4/RTCC/T7CKI/T5G/ 8 CCP5/AN16/P1D/C3INC RG4 I/O ST Digital I/O. RTCC O — RTCC output T7CKI(3) I ST Timer7 clock input. T5G I ST Timer5 external clock gate input. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM5 output. AN16 I Analog Analog Input 16. P1D O — ECCP1 PWM Output D. C3INC I Analog Comparator 3 Input C. RG5 7 See the MCLR/RG5 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 20  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type QFN/TQFP VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins. VDD 26, 38, 57 P — Positive supply for logic and I/O pins. AVSS 20 P — Ground reference for analog modules. AVDD 19 P — Positive supply for analog modules. ENVREG 18 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP 10 Core logic power or external filter capacitor connection. VDDCORE VCAP P — External filter capacitor connection (regulator enabled/disabled). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>).  2009-2018 Microchip Technology Inc. DS30009960F-page 21

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type TQFP 9 Master Clear (input) or programming voltage (input). MCLR/RG5 RG5 I ST This pin is an active-low Reset to the device. MCLR I ST General purpose, input only pin. OSC1/CLKI/RA7 49 Oscillator crystal or external clock input. OSC1 I CMOS Oscillator crystal input. CLKI I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 50 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 22  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTA is a bidirectional I/O port. RA0/AN0/ULPWU 30 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. ULPWU I Analog Ultra Low-Power Wake-up input. RA1/AN1 29 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF- 28 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 27 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 34 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4/T1CKI/ 33 T3G/HLVDIN RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. T1CKI I ST Timer1 clock input. T3G I ST Timer3 external clock gate input. HLVDIN I Analog High/Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>).  2009-2018 Microchip Technology Inc. DS30009960F-page 23

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 58 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. FLT0 I ST Enhanced PWM Fault input for ECCP1/2/3. RB1/INT1 57 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. RB2/INT2/CTED1 56 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. CTED1 I ST CTMU Edge 1 input. RB3/INT3/CTED2/ 55 ECCP2/P2A RB3 I/O TTL Digital I/O. INT3 I ST External Interrupt 3. CTED2 I ST CTMU Edge 2 input. ECCP2 I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A O ST Enhanced PWM2 Output A. RB4/KBI0 54 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1/T3CKI/T1G 53 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. T3CKI I ST Timer3 clock input. T1G I ST Timer1 external clock gate input. RB6/KBI2/PGC 52 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 47 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 24  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTC is a bidirectional I/O port. RC0/SOSCO/SCKLI 36 RC0 I/O ST Digital I/O. SOSCO O — SOSC oscillator output. SCKLI I ST Digital SOSC input. RC1/SOSCI/ECCP2/P2A 35 RC1 I/O ST Digital I/O. SOSCI I CMOS SOSC oscillator input. ECCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A O — Enhanced PWM2 Output A. RC2/ECCP1/P1A 43 RC2 I/O ST Digital I/O. ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O — Enhanced PWM1 Output A. RC3/SCK1/SCL1 44 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O I2C Synchronous serial clock input/output for I2C mode. RC4/SDI1/SDA1 45 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O I2C I2C data I/O. RC5/SDO1 46 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. RC6/TX1/CK1 37 RC6 I/O ST Digital I/O. TX1 O — EUSART asynchronous transmit. CK1 I/O ST EUSART synchronous clock (see related RX1/DT1). RC7/RX1/DT1 38 RC7 I/O ST Digital I/O. RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data (see related TX1/CK1). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>).  2009-2018 Microchip Technology Inc. DS30009960F-page 25

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTD is a bidirectional I/O port. RD0/PSP0/CTPLS/AD0 72 RD0 I/O ST Digital I/O PSP0(4) I/O TTL Parallel Slave Port data CTPLS O ST CTMU pulse generator output AD0 I/O TTL External Memory Address/Data 0 RD1/T5CKI/T7G/PSP1/AD1 69 RD1 I/O ST Digital I/O T5CKI I ST Timer5 clock input T7G I ST Timer7 external clock gate input PSP1(4) I/O TTL Parallel Slave Port data AD1 I/O TTL External Memory Address/Data 1 RD2/PSP2/AD2 68 RD2 I/O ST Digital I/O. PSP2(4) I/O TTL Parallel Slave Port data. AD2 I/O TTL External Memory Address/Data 2. RD3/PSP3/AD3 67 RD3 I/O ST Digital I/O. PSP3(4) I/O TTL Parallel Slave Port data. AD3 I/O TTL External Memory Address/Data 3. RD4/SDO2/PSP4/AD4 66 RD4 I/O ST Digital I/O. SDO2 O — SPI data out. PSP4(4) I/O TTL Parallel Slave Port data. AD4 I/O TTL External Memory Address/Data 4. RD5/SDI2/SDA2/PSP5/ 65 AD5 RD5 I/O ST Digital I/O. SDI2 I ST SPI data in. SDA2 I/O I2C I2C data I/O. PSP5(4) I/O TTL Parallel Slave Port data. AD5 I/O TTL External Memory Address/Data 5. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 26  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP RD6/SCK2/SCL2/PSP6/ 64 AD6 RD6 I/O ST Digital I/O. SCK2 I/O ST Synchronous serial clock input/output for SPI mode. SCL2 I/O I2C Synchronous serial clock input/output for I2C mode. PSP6(4) I/O TTL Parallel Slave Port data. AD6 I/O TTL External Memory Address/Data 6. RD7/SS2/PSP7/AD7 63 RD7 I/O ST Digital I/O. SS2 I TTL SPI slave select input. PSP7(4) I/O TTL Parallel Slave Port data. AD7 I/O TTL External Memory Address/Data 7. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>).  2009-2018 Microchip Technology Inc. DS30009960F-page 27

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTE is a bidirectional I/O port. RE0/P2D/RD/AD8 4 RE0 I/O ST Digital I/O. P2D O — ECCP2 PWM Output D. RD(4) I TTL Parallel Slave Port read strobe. AD8 I/O TTL External Memory Address/Data 8. RE1/P2C/WR/AD9 3 RE1 I/O ST Digital I/O. P2C O — ECCP2 PWM Output C. WR(4) I TTL Parallel Slave Port write strobe. AD9 I/O TTL External Memory Address/Data 9. RE2/P2B/CCP10/CS/ 78 AD10 RE2 I/O ST Digital I/O. P2B O ST ECCP2 PWM Output B. CCP10(3) I/O ST Capture 10 input/Compare 10 output/PWM10 output. CS(4) I TTL Parallel Slave Port chip select. AD10 I/O TTL External Memory Address/Data 10. RE3/P3C/CCP9/REFO 77 AD11 RE3 I/O ST Digital I/O. P3C O — ECCP3 PWM Output C. CCP9(3,5) I/O S/T Capture 9 input/Compare 9 output/PWM9 output. REFO O — Reference clock out. AD11 I/O TTL External Memory Address/Data 11. RE4/P3B/CCP8/AD12 76 RE4 I/O ST Digital I/O. P3B O — ECCP4 PWM Output B. CCP8(5) I/O ST Capture 8 input/Compare 8 output/PWM8 output. AD12 I/O TTL External Memory Address/Data 12. RE5/P1C/CCP7/AD13 75 RE5 I/O ST Digital I/O. P1C O — ECCP1 PWM Output C. CCP7(5) I/O ST Capture 7 input/Compare 7 output/PWM7 output. AD13 I/O TTL External Memory Address/Data 13. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 28  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP RE6/P1B/CCP6/AD14 74 RE6 I/O ST Digital I/O. P1B O — ECCP1 PWM Output B. CCP6(5) I/O ST Capture 6 input/Compare 6 output/PWM6 output. AD14 I/O ST External Memory Address/Data 14. RE7/ECCP2/P2A/AD15 73 RE7 I/O ST Digital I/O. ECCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. P2A O — ECCP2 PWM Output A. AD15 I/O ST External Memory Address/Data 15. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>).  2009-2018 Microchip Technology Inc. DS30009960F-page 29

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTF is a bidirectional I/O port. RF1/AN6/C2OUT/CTDIN 23 RF1 I/O ST Digital I/O. AN6 I Analog Analog Input 6. C2OUT O — Comparator 2 output. CTDIN I ST CTMU pulse delay input. RF2/AN7/C1OUT 18 RF2 I/O ST Digital I/O. AN7 I Analog Analog Input 7. C1OUT O — Comparator 1 output. RF3/AN8/C2INB/CTMUI 17 RF3 I/O ST Digital I/O. AN8 I Analog Analog Input 8. C2INB I Analog Comparator 2 Input B. CTMUI O — CTMU pulse generator charger for the C2INB comparator input. RF4/AN9/C2INA 16 RF4 I/O ST Digital I/O. AN9 I Analog Analog Input 9. C2INA I Analog Comparator 2 Input A. RF5/AN10/C1INB 15 RF5 I/O ST Digital I/O. AN10 I Analog Analog Input 10. C1INB I Analog Comparator 1 Input B. RF6/AN11/C1INA 14 RF6 I/O ST Digital I/O. AN11 I Analog Analog Input 11. C1INA I Analog Comparator 1 Input A. RF7/AN5/SS1 13 RF7 I/O ST Digital I/O. AN5 O Analog Analog Input 5. SS1 I ST SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 30  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTG is a bidirectional I/O port. RG0/ECCP3/P3A 5 RG0 I/O ST Digital I/O. ECCP3 I/O ST Capture 3 input/Compare 3 output/PWM3 output. P3A O — ECCP3 PWM Output A. RG1/TX2/CK2/AN19/ 6 C3OUT RG1 I/O ST Digital I/O. TX2 O — EUSART asynchronous transmit. CK2 I/O ST EUSART synchronous clock (see related RX2/DT2). AN19 I Analog Analog Input 19. C3OUT O — Comparator 3 output. RG2/RX2/DT2/AN18/ 7 C3INA RG2 I/O ST Digital I/O. RX2 I ST EUSART asynchronous receive. DT2 I/O ST EUSART synchronous data (see related TX2/CK2). AN18 I Analog Analog Input 18. C3INA I Analog Comparator 3 Input A. RG3/CCP4/AN17/P3D/ 8 C3INB RG3 I/O ST Digital I/O. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM4 output. AN17 I Analog Analog Input 17. P3D O — ECCP3 PWM Output D. C3INB I Analog Comparator 3 Input B. RG4/RTCC/T7CKI/T5G/ 10 CCP5/AN16/P1D/C3INC RG4 I/O ST Digital I/O. RTCC O — RTCC output. T7CKI(3) I ST Timer7 clock input. T5G I ST Timer5 external clock gate input. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM5 output. AN16 I Analog Analog Input 16. P1D O — ECCP1 PWM Output D. C3INC I Analog Comparator 3 Input C. RG5 9 See the MCLR/RG5 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>).  2009-2018 Microchip Technology Inc. DS30009960F-page 31

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTH is a bidirectional I/O port. RH0/AN23/A16 79 RH0 I/O ST Digital I/O. AN23 I Analog Analog Input 23. A16 I/O TTL External Memory Address/Data 16. RH1/AN22/A17 80 RH1 I/O ST Digital I/O. AN22 I Analog Analog Input 22. A17 I/O TTL External Address/Data 17. RH2/AN21/A18 1 RH2 I/O ST Digital I/O. AN21 I Analog Analog Input 21. A18 I/O TTL External Address/Data 18. RH3/AN20/A19 2 RH3 I/O ST Digital I/O. AN20 I Analog Analog Input 20. A19 I/O TTL External Address/Data 19. RH4/CCP9/P3C/AN12/ 22 C2INC RH4 I/O ST Digital I/O. CCP9(3,5) I/O ST Capture 9 input/Compare 9 output/PWM9 output. P3C O — ECCP3 PWM Output C. AN12 I Analog Analog Input 12. C2INC I Analog Comparator 2 Input C. RH5/CCP8/P3B/AN13/ 21 C2IND RH5 I/O ST Digital I/O. CCP8(5) I/O ST Capture 8 input/Compare 8 output/PWM8 output. P3B O — ECCP3 PWM Output B. AN13 I Analog Analog Input 13. C2IND I Analog Comparator 1 Input D. RH6/CCP7/P1C/AN14/ 20 C1INC RH6 I/O ST Digital I/O. CCP7(5) I/O ST Capture 7 input/Compare 7 output/PWM7 output. P1C O — ECCP1 PWM Output C. AN14 I Analog Analog Input 14. C1INC I Analog Comparator 1 Input C. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 32  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP RH7/CCP6/P1B/AN15 19 RH7 I/O ST Digital I/O. CCP6(5) I/O ST Capture 6 input/Compare 6 output/PWM6 output. P1B O — ECCP1 PWM Output B. AN15 I Analog Analog Input 15. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>).  2009-2018 Microchip Technology Inc. DS30009960F-page 33

PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTJ is a bidirectional I/O port. RJ0/ALE 62 RJ0 I/O ST Digital I/O. ALE O — External memory address latch enable. RJ1/OE 61 RJ1 I/O ST Digital I/O. OE O — External memory output enable. RJ2/WRL 60 RJ2 I/O ST Digital I/O. WRL O — External memory write low control. RJ3/WRH 59 RJ3 I/O ST Digital I/O. WRH O — External memory high control. RJ4/BA0 39 RJ4 I/O ST Digital I/O. BA0 O — External Memory Byte Address 0 control RJ5/CE 40 RJ5 I/O ST Digital I/O CE O — External memory chip enable control. RJ6/LB 41 RJ6 I/O ST Digital I/O. LB O — External memory low byte control. RJ7/UB 42 RJ7 I/O ST Digital I/O. UB O — External memory high byte control. VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins. VDD 32, 48, 71 P — Positive supply for logic and I/O pins. AVSS 26 P — Ground reference for analog modules. AVDD 25 P — Positive supply for analog modules. ENVREG 24 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP 12 Core logic power or external filter capacitor connection. VDDCORE VCAP P — External filter capacitor connection (regulator enabled/disabled). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) I2C = I2C/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS30009960F-page 34  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH PIC18FXXKXX MINIMUM CONNECTIONS MICROCONTROLLERS C2(2) 2.1 Basic Connection Requirements VDD Getting started with the PIC18F87K22 family family of R1 DD SS (1)(1) 8-bit microcontrollers requires attention to a minimal R2 V V set of device pin connections before proceeding with MCLR ENVREG development. VCAP/VDDCORE C1 The following pins must always be connected: C7(2) PIC18FXXKXX • All VDD and VSS pins (see Section2.2 “Power Supply Pins”) VSS VDD C6(2) C3(2) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S VSS D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(2) C4(2) • ENVREG (if implemented) and VCAP/VDDCORE pins (see Section2.4 “Voltage Regulator Pins (ENVREG and VCAP/VDDCORE)”) Key (all values are recommendations): These pins must also be connected if they are being C1 through C6: 0.1 F, 20V ceramic used in the end application: R1: 10 kΩ • PGC/PGD pins used for In-Circuit Serial R2: 100Ω to 470Ω Programming™ (ICSP™) and debugging purposes Note 1: See Section2.4 “Voltage Regulator Pins (see Section2.5 “ICSP Pins”) (ENVREG and VCAP/VDDCORE)” for • OSCI and OSCO pins when an external oscillator explanation of ENVREG pin connections. source is used 2: The example shown is for a PIC18F device (see Section2.6 “External Oscillator Pins”) with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; Additionally, the following pins may be required: adjust the number of decoupling capacitors • VREF+/VREF- pins are used when external voltage appropriately. reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1.  2009-2018 Microchip Technology Inc. DS30009960F-page 35

PIC18F87K22 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: Device Reset, and Device Programming The use of decoupling capacitors on every pair of and Debugging. If programming and debugging are power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct AVSS, is required. connection to VDD may be all that is required. The Consider the following criteria when using decoupling addition of other components, to help increase the capacitors: application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical • Value and type of capacitor: A 0.1 F (100 nF), configuration is shown in Figure2-1. Other circuit 10-20V capacitor is recommended. The capacitor designs may be implemented, depending on the should be a low-ESR device, with a resonance application’s requirements. frequency in the range of 200MHz and higher. Ceramic capacitors are recommended. During programming and debugging, the resistance • Placement on the printed circuit board: The and capacitance that can be added to the pin must be considered. Device programmers and debuggers decoupling capacitors should be placed as close drive the MCLR pin. Consequently, specific voltage to the pins as possible. It is recommended to place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the capacitor can be placed on another layer on the application and PCB requirements. For example, it is PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated length from the pin to the capacitor is no greater from the MCLR pin during programming and than 0.25inch (6mm). debugging operations by using a jumper (Figure2-2). • Handling high-frequency noise: If the board is The jumper is replaced for normal run-time experiencing high-frequency noise (upward of operations. tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling Any components associated with the MCLR pin capacitor. The value of the second capacitor can should be placed within 0.25 inch (6mm) of the pin. be in the range of 0.01F to 0.001F. Place this second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN capacitor. In high-speed circuit designs, consider CONNECTIONS implementing a decade pair of capacitances as close to the power and ground pins as possible VDD (e.g., 0.1F in parallel with 0.001F). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the JP PIC18FXXKXX decoupling capacitors are first in the power chain. Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R1 10k is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10k. Ensure that the On boards with power traces running longer than MCLR pin VIH and VIL specifications are met. sixinches in length, it is suggested to use a tank capac- 2: R2470 will limit any current flowing into itor for integrated circuits, including microcontrollers, to MCLR from the external capacitor, C, in the supply a local power source. The value of the tank event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical capacitor should be determined based on the trace Overstress (EOS). Ensure that the MCLR pin resistance that connects the power supply source to VIH and VIL specifications are met. the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7F to 47F. DS30009960F-page 36  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 2.4 Voltage Regulator Pins (ENVREG Some PIC18FXXKXX families, or some devices within and VCAP/VDDCORE) a family, do not provide the option of enabling or disabling the on-chip voltage regulator: The on-chip voltage regulator enable pin, ENVREG, • Some devices (with the name, PIC18LFXXKXX) must always be connected directly to either a supply permanently disable the voltage regulator. voltage or to ground. Tying ENVREG to VDD enables These devices do not have the ENVREG pin and the regulator, while tying it to ground disables the require a 0.1 F capacitor on the VCAP/VDDCORE regulator. Refer to Section28.3 “On-Chip Voltage pin. The VDD level of these devices must comply Regulator” for details on connecting and using the with the “voltage regulator disabled” specification on-chip regulator. for Parameter D001, in Section31.0 “Electrical When the regulator is enabled, a low-ESR (<5Ω) Characteristics”. capacitor is required on the VCAP/VDDCORE pin to • Some devices permanently enable the voltage stabilize the voltage regulator output voltage. The regulator. VCAP/VDDCORE pin must not be connected to VDD and These devices also do not have the ENVREG pin. must use a capacitor of 10 µF connected to ground. The The 10 F capacitor is still required on the type can be ceramic or tantalum. Suitable examples of VCAP/VDDCORE pin. capacitors are shown in Table2-1. Capacitors with equivalent specifications can be used. FIGURE 2-3: FREQUENCY vs. ESR Designers may use Figure2-3 to evaluate ESR PERFORMANCE FOR equivalence of candidate devices. SUGGESTED VCAP It is recommended that the trace length not exceed 10 0.25inch (6mm). Refer to Section31.0 “Electrical Characteristics” for additional information. 1 When the regulator is disabled, the VCAP/VDDCORE pin must only be tied to a 0.1 F capacitor. Refer to ) Section28.3 “On-Chip Voltage Regulator” for infor- R ( 0.1 mation on VDD and VDDCORE. ES 0.01 0.001 0.01 0.1 1 10 100 1000 10,000 Frequency (MHz) Note: Typical data measurement at 25°C, 0V DC bias. . TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Nominal Make Part # Base Tolerance Rated Voltage Temp. Range Capacitance TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC  2009-2018 Microchip Technology Inc. DS30009960F-page 37

PIC18F87K22 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC FIGURE 2-4: DC BIAS VOLTAGE vs. CAPACITORS CAPACITANCE CHARACTERISTICS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic %) 10 e ( 0 capacitors very attractive in many types of applications. ng-10 16V Capacitor ha-20 Ceramic capacitors are suitable for use with the inter- C-30 nal voltage regulator of this microcontroller. However, ance --5400 10V Capacitor some care is needed in selecting the capacitor to cit-60 ensure that it maintains sufficient capacitance over the Capa--8700 6.3V Capacitor intended operating range of the application. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage (VDC) Typical low-cost, 10 F ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial toler- When selecting a ceramic capacitor to be used with the ance specifications for these types of capacitors are internal voltage regulator, it is suggested to select a often specified as ±10% to ±20% (X5R and X7R), or high-voltage rating, so that the operating voltage is a -20%/+80% (Y5V). However, the effective capacitance small percentage of the maximum rated capacitor volt- that these capacitors provide in an application circuit will age. For example, choose a ceramic capacitor rated at also vary based on additional factors, such as the 16V for the 2.5V core voltage. Suggested capacitors applied DC bias voltage and the temperature. The total are shown in Table2-1. in-circuit tolerance is, therefore, much wider than the initial tolerance specification. 2.5 ICSP Pins The X5R and X7R capacitors typically exhibit satisfac- The PGC and PGD pins are used for In-Circuit Serial tory temperature stability (ex: ±15% over a wide Programming™ (ICSP™) and debugging purposes. It temperature range, but consult the manufacturer’s data is recommended to keep the trace length between the sheets for exact specifications). However, Y5V capaci- ICSP connector and the ICSP pins on the device as tors typically have extreme temperature tolerance short as possible. If the ICSP connector is expected to specifications of +22%/-82%. Due to the extreme experience an ESD event, a series resistor is recom- temperature tolerance, a 10 F nominal rated Y5V type mended, with the value in the range of a few tens of capacitor may not deliver enough total capacitance to ohms, not to exceed 100Ω. meet minimum internal voltage regulator stability and Pull-up resistors, series diodes and capacitors on the transient response requirements. Therefore, Y5V PGC and PGD pins are not recommended as they will capacitors are not recommended for use with the interfere with the programmer/debugger communica- internal regulator if the application must operate over a tions to the device. If such discrete components are an wide temperature range. application requirement, they should be removed from In addition to temperature tolerance, the effective the circuit during programming and debugging. Alter- capacitance of large value ceramic capacitors can vary natively, refer to the AC/DC characteristics and timing substantially, based on the amount of DC voltage requirements information in the respective device applied to the capacitor. This effect can be very signifi- Flash programming specification for information on cant, but is often overlooked or is not always capacitive loading limits, and pin input voltage high documented. (VIH) and input low (VIL) requirements. A typical DC bias voltage vs. capacitance graph for For device emulation, ensure that the “Communication X7R type and Y5V type capacitors is shown in Channel Select” (i.e., PGCx/PGDx pins), programmed Figure2-4. into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section30.0 “Development Support”. DS30009960F-page 38  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: SUGGESTED PLACEMENT OF THE Many microcontrollers have options for at least two OSCILLATOR CIRCUIT oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Single-Sided and In-Line Layouts: Section3.0 “Oscillator Configurations” for details). Copper Pour Primary Oscillator The oscillator circuit should be placed on the same (tied to ground) Crystal side of the board as the device. Place the oscillator DEVICE PINS circuit close to the respective oscillator pins with no more than 0.5inch (12mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Primary OSC1 Oscillator of the board. C1 ` OSC2 Use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. The C2 GND grounded copper pour should be routed directly to the ` MCU ground. Do not run any signal traces or power T1OSO traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board T1OS I Timer1 Oscillator where the crystal is placed. Crystal ` Layout suggestions are shown in Figure 2-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With T1 Oscillator: C1 T1 Oscillator: C2 fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts: ground layer. In all cases, the guard trace(s) must be returned to ground. Top Layer Copper Pour (tied to ground) In planning the application’s routing and I/O assign- ments, ensure that adjacent port pins, and other Bottom Layer signals in close proximity to the oscillator, are benign Copper Pour (i.e., free of high frequencies, short rise and fall times, (tied to ground) and other similar noise). OSCO For additional information and design guidance on oscillator circuits, please refer to these Microchip C2 Application Notes, available at the corporate web site Oscillator (www.microchip.com): GND Crystal • AN826, “Crystal Oscillator Basics and Crystal C1 Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” OSCI • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” 2.7 Unused I/Os DEVICE PINS Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the output to logic low.  2009-2018 Microchip Technology Inc. DS30009960F-page 39

PIC18F87K22 FAMILY 3.0 OSCILLATOR To optimize power consumption when using EC/HS/ CONFIGURATIONS XT/LP/RC as the primary oscillator, the frequency input range can be configured to yield an optimized power bias: 3.1 Oscillator Types • Low-Power Bias – External frequency less than The PIC18F87K22 family of devices can be operated in 160kHz the following oscillator modes: • Medium Power Bias – External frequency • EC External clock, RA6 available between 160kHz and 16MHz • ECIO External clock, clock out RA6 (FOSC/4 • High-Power Bias – External frequency greater on RA6) than 16MHz • HS High-Speed Crystal/Resonator All of these modes are selected by the user by • XT Crystal/Resonator programming the FOSC<3:0> Configuration bits • LP Low-Power Crystal (CONFIG1H<3:0>). In addition, PIC18F87K22 family • RC External Resistor/Capacitor, RA6 devices can switch between different clock sources, available either under software control or, under certain condi- tions, automatically. This allows for additional power • RCIO External Resistor/Capacitor, clock out savings by managing device clock speed in real time RA6 (FOSC/4 on RA6) without resetting the application. The clock sources for • INTIO2 Internal Oscillator with I/O on RA6 and the PIC18F87K22 family of devices are shown in RA7 Figure3-1. • INTIO1 Internal Oscillator with FOSC/4 output on For the HS and EC mode, there are additional power RA6 and I/O on RA7 modes of operation – depending on the frequency of There is also an option for running the 4xPLL on any of operation. the clock sources in the input frequency range of 4 to HS1 is the Medium Power mode with a frequency 16MHz. range of 4MHz to 16MHz. HS2 is the High-Power The PLL is enabled by setting the PLLCFG bit (CON- mode, where the oscillator frequency can go from FIG1H<4>) or the PLLEN bit (OSCTUNE<6>). 16MHz to 25MHz. HS1 and HS2 are achieved by set- For the EC and HS mode, the PLLEN (software) or ting the CONFIG1H<3:0> correctly. (For details, see PLLCFG (CONFIG) bit can be used to enable the PLL. Register28-2 on page 395.) For the INTIOx modes (HF-INTOSC): EC mode has these modes of operation: • Only the PLLEN can enable the PLL (PLLCFG is • EC1 – For low power with a frequency range up to ignored). 160kHz • When the oscillator is configured for the internal • EC2 – Medium power with a frequency range of oscillator (FOSC<3:0>= 100x), the PLL can be 160kHz to 16MHz enabled only when the HF-INTOSC frequency is • EC3 – High power with a frequency range of 8 or 16MHz. 16MHz to 64MHz When the RA6 and RA7 pins are not used for an oscil- EC1, EC2 and EC3 are achieved by setting the CON- lator function or CLKOUT function, they are available FIG1H<3:0> correctly. (For details, see Register28-2 as general purpose I/Os. on page 395.) Table3-1 shows the HS and EC modes’ frequency range and FOSC<3:0> settings. DS30009960F-page 40  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 3-1: HS, EC, XT, LP AND RC MODES: RANGES AND SETTINGS Mode Frequency Range FOSC<3:0> Setting EC1 (low power) 1101 DC-160kHz (EC1 & EC1IO) 1100 EC2 (medium power) 1011 160kHz-16MHz (EC2 & EC2IO) 1010 EC3 (high power) 0101 16MHz-64MHz (EC3 & EC3IO) 0100 HS1 (medium power) 4MHz-16MHz 0011 HS2 (high power) 16MHz-25MHz 0010 XT 100kHz-4MHz 0001 LP 31.25kHz 0000 RC (External) 0-4MHz 001x 100x INTIO 32KHz-16MHz (and OSCCON, OSCCON2) FIGURE 3-1: PIC18F87K22 FAMILY CLOCK DIAGRAM SOSCO SOSCI OSC2 UX 4x PLL MUX Mux Peripherals M CPU OSC1 PLLEN FOSC<3:0> and PLLCFG IDLEN 16 MHz 16 MHz 111 8 MHz 8 MHz 110 Clock Control SCS<1:0> 4 MHz 4 MHz er 101 H1F63 I1MN kTHHOzz StoC ostscal 5210 MM0 HHkzzHz 50120 MMkHHHzzz 100101 MUX FOSC<3:0> P 010 250 kHz 250 kHz 001 31 kHz 31 kHz 000 X M5F03 0I1N k kTHHOzz StoC stscaler 352105 00k HkkHHzzz MU MUX IRCF<2:0> o P INTSRC MFIOSEL LF INTOSC 31 kHz 31 kHz  2009-2018 Microchip Technology Inc. DS30009960F-page 41

PIC18F87K22 FAMILY 3.2 Control Registers The OSCTUNE register (Register3-3) controls the tuning and operation of the internal oscillator block. It also The OSCCON register (Register3-1) controls the main implements the PLLEN bit which controls the operation of aspects of the device clock’s operation. It selects the the Phase Locked Loop (PLL) (see Section3.5.3 “PLL oscillator type to be used, which of the power-managed Frequency Multiplier”). modes to invoke and the output frequency of the INTOSC source. It also provides status on the oscillators. REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) R/W-0 R/W-1 R/W-1 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2(2) IRCF1(2) IRCF0(2) OSTS HFIOFS SCS1(4) SCS0(4) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters an Idle mode when a SLEEP instruction is executed 0 = Device enters Sleep mode when a SLEEP instruction is executed bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits(2) 111 = HF-INTOSC output frequency is used (16MHz) 110 = HF-INTOSC/2 output frequency is used (8MHz, default) 101 = HF-INTOSC/4 output frequency is used (4MHz) 100 = HF-INTOSC/8 output frequency is used (2MHz) 011 = HF-INTOSC/16 output frequency is used (1MHz) If INTSRC = 0 and MFIOSEL = 0:(3,5) 010 = HF-INTOSC/32 output frequency is used (500kHz) 001 = HF-INTOSC/64 output frequency is used (250kHz) 000 = LF-INTOSC output frequency is used (31.25kHz) If INTSRC = 1 and MFIOSEL = 0:(3,5) 010 = HF-INTOSC/32 output frequency is used (500kHz) 001 = HF-INTOSC/64 output frequency is used (250kHz) 000 = HF-INTOSC/512 output frequency is used (31.25kHz) If INTSRC = 0 and MFIOSEL = 1:(3,5) 010 = MF-INTOSC output frequency is used (500kHz) 001 = MF-INTOSC/2 output frequency is used (250kHz) 000 = LF-INTOSC output frequency is used (31.25kHz)(6) If INTSRC = 1 and MFIOSEL = 1:(3,5) 010 = MF-INTOSC output frequency is used (500kHz) 001 = MF-INTOSC/2 output frequency is used (250kHz) 000 = MF-INTOSC/16 output frequency is used (31.25kHz) bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit(1) 1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running, as defined by FOSC<3:0> 0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready – device is running from internal oscillator (HF-INTOSC, MF-INTOSC or LF-INTOSC) Note 1: The Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>). 2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. 3: Source selected by the INTSRC bit (OSCTUNE<7>). 4: Modifying these bits will cause an immediate clock source switch. 5: INTSRC= OSCTUNE<7> and MFIOSEL= OSCCON2<0>. 6: Lowest power option for an internal source. DS30009960F-page 42  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) bit 2 HFIOFS: INTOSC Frequency Stable bit 1 = HF-INTOSC oscillator frequency is stable 0 = HF-INTOSC oscillator frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits(4) 1x = Internal oscillator block (LF-INTOSC, MF-INTOSC or HF-INTOSC) 01 = SOSC oscillator 00 = Default primary oscillator (OSC1/OSC2 or HF-INTOSC with or without PLL; defined by the FOSC<3:0> Configuration bits, CONFIG1H<3:0>.) Note 1: The Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>). 2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. 3: Source selected by the INTSRC bit (OSCTUNE<7>). 4: Modifying these bits will cause an immediate clock source switch. 5: INTSRC= OSCTUNE<7> and MFIOSEL= OSCCON2<0>. 6: Lowest power option for an internal source. REGISTER 3-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 U-0 R-0 U-0 U-0 R/W-0 U-0 R-x R/W-0 — SOSCRUN — — SOSCGO — MFIOFS MFIOSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from a secondary SOSC 0 = System clock comes from an oscillator other than SOSC bit 5-4 Unimplemented: Read as ‘0’ bit 3 SOSCGO: Oscillator Start Control bit 1 = Oscillator is running, even if no other sources are requesting it 0 = Oscillator is shut off if no other sources are requesting it (When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect.) bit 2 Unimplemented: Read as ‘0’ bit 1 MFIOFS: MF-INTOSC Frequency Stable bit 1 = MF-INTOSC is stable 0 = MF-INTOSC is not stable bit 0 MFIOSEL: MF-INTOSC Select bit 1 = MF-INTOSC is used in place of HF-INTOSC frequencies of 500kHz, 250kHz and 31.25kHz 0 = MF-INTOSC is not used  2009-2018 Microchip Technology Inc. DS30009960F-page 43

PIC18F87K22 FAMILY REGISTER 3-3: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock derived from 16MHz INTOSC source (divide-by-512 enabled, HF-INTOSC) 0 = 31kHz device clock derived from INTRC 31kHz oscillator (LF-INTOSC) bit 6 PLLEN: Frequency Multiplier PLL Enable bit 1 = PLL is enabled 0 = PLL is disabled bit 5-0 TUN<5:0>: Fast RC Oscillator (INTOSC) Frequency Tuning bits 011111 = Maximum frequency • • • • 000001 000000 = Center frequency; fast RC oscillator is running at the calibrated frequency 111111 • • • • 100000 = Minimum frequency DS30009960F-page 44  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 3.3 Clock Sources and In addition to being a primary clock source in some Oscillator Switching circumstances, the internal oscillator is available as a power-managed mode clock source. The LF-INTOSC Essentially, PIC18F87K22 family devices have these source is also used as the clock source for several independent clock sources: special features, such as the WDT and Fail-Safe Clock • Primary oscillators Monitor. The internal oscillator block is discussed in • Secondary oscillators more detail in Section3.6 “Internal Oscillator • Internal oscillator Block”. The primary oscillators can be thought of as the main The PIC18F87K22 family includes features that allow device oscillators. These are any external oscillators the device clock source to be switched from the main connected to the OSC1 and OSC2 pins, and include oscillator, chosen by device configuration, to one of the the External Crystal and Resonator modes and the alternate clock sources. When an alternate clock External Clock modes. If selected by the FOSC<3:0> source is enabled, various power-managed operating Configuration bits (CONFIG1H<3:0>), the internal modes are available. oscillator block may be considered a primary oscillator. 3.3.1 OSC1/OSC2 OSCILLATOR The internal oscillator block can be one of the following: The OSC1/OSC2 oscillator block is used to provide the • 31kHz LF-INTRC source oscillator modes and frequency ranges: • 31kHz to 500kHz MF-INTOSC source • 31kHz to 16MHz HF-INTOSC source Mode Design Operating Frequency The particular mode is defined by the FOSC LP 31.25-100kHz Configuration bits. The details of these modes are XT 100kHz to 4MHz covered in Section3.5 “External Oscillator Modes”. HS 4MHz to 25MHz The secondary oscillators are external clock EC 0 to 64MHz (external clock) sources that are not connected to the OSC1 or OSC2 pin. These sources may continue to operate, even EXTRC 0 to 4MHz (external RC) after the controller is placed in a power-managed The crystal-based oscillators (XT, HS and LP) have a mode. PIC18F87K22 family devices offer the SOSC built-in start-up time. The operation of the EC and (Timer1/3/5/7) oscillator as a secondary oscillator EXTRC clocks is immediate. source. This oscillator, in all power-managed modes, is often the time base for functions, such as a Real-Time 3.3.2 CLOCK SOURCE SELECTION Clock (RTC). The System Clock Select bits, SCS<1:0> The SOSC can be enabled from any peripheral that (OSCCON2<1:0>), select the clock source. The avail- requests it. There are eight ways the SOSC can be able clock sources are the primary clock defined by the enabled: if the SOSC is selected as the source by any FOSC<3:0> Configuration bits, the secondary clock of the odd timers, which is done by each respective (SOSC oscillator) and the internal oscillator. The clock SOSCEN bit (TxCON<3>), if the SOSC is selected as source changes after one or more of the bits is written the RTCC source by the RTCOSC Configuration bit to, following a brief clock transition interval. (CONFIG3L<1>), if the SOSC is selected as the CPU The OSTS (OSCCON<3>) and SOSCRUN clock source by the SCS bits (OSCCON<1:0>) or if the (OSCCON<6>) bits indicate which clock source is SOSCGO bit is set (OSCCON2<3>). The SOSCGO bit currently providing the device clock. The OSTS bit is used to warm up the SOSC so that it is ready before indicates that the Oscillator Start-up Timer (OST) has any peripheral requests it. timed out and the primary clock is providing the device The secondary oscillator has three Run modes. The clock in primary clock modes. The SOSCRUN bit indi- SOSCSEL<1:0> bits (CONFIG1L<4:3>) decide the cates when the SOSC oscillator (from Timer1/3/5/7) is SOSC mode of operation: providing the device clock in secondary clock modes. • 11 = High-power SOSC circuit In power-managed modes, only one of these bits will be set at any time. If neither of these bits is set, the • 10 = Digital (SCLKI) mode INTRC is providing the clock, or the internal oscillator • 01 = Low-power SOSC circuit has just started and is not yet stable. If a secondary oscillator is not desired and digital I/O on The IDLEN bit (OSCCON<7>) determines if the device port pins, RC0 and RC1, is needed, the SOSCSEL bits goes into Sleep mode or one of the Idle modes when must be set to Digital mode. the SLEEP instruction is executed.  2009-2018 Microchip Technology Inc. DS30009960F-page 45

PIC18F87K22 FAMILY The use of the flag and control bits in the OSCCON 3.4 RC Oscillator register is discussed in more detail in Section4.0 “Power-Managed Modes”. For timing-insensitive applications, the RC and RCIO Oscillator modes offer additional cost savings. The Note 1: The Timer1/3/5/7 oscillator must be actual oscillator frequency is a function of several enabled to select the secondary clock factors: source. The Timerx oscillator is enabled by • Supply Voltage setting the SOSCEN bit in the Timerx Con- • Values of the External Resistor (REXT) and trol register (TxCON<3>). If the Timerx Capacitor (CEXT) oscillator is not enabled, then any attempt • Operating Temperature to select a secondary clock source when executing a SLEEP instruction will be Given the same device, operating voltage and tem- ignored. perature, and component values, there will also be unit 2: It is recommended that the Timerx to unit frequency variations. These are due to factors, oscillator be operating and stable before such as: executing the SLEEP instruction or a very • Normal manufacturing variation long delay may occur while the Timerx • Difference in lead frame capacitance between oscillator starts. package types (especially for low CEXT values) • Variations within the tolerance of limits of REXT 3.3.2.1 System Clock Selection and Device and CEXT Resets In the RC Oscillator mode, the oscillator frequency, Since the SCS bits are cleared on all forms of Reset, divided by 4, is available on the OSC2 pin. This signal this means the primary oscillator, defined by the may be used for test purposes or to synchronize other FOSC<3:0> Configuration bits, is used as the primary logic. Figure3-2 shows how the R/C combination is clock source on device Resets. This could either be the connected. internal oscillator block by itself, or one of the other primary clock source (HS, EC, XT, LP, External RC and FIGURE 3-2: RC OSCILLATOR MODE PLL-Enabled modes). VDD In those cases when the internal oscillator block, with- out PLL, is the default clock on Reset, the Fast RC REXT oscillator (INTOSC) will be used as the device clock Internal OSC1 source. It will initially start at 8MHz; the postscaler Clock selection that corresponds to the Reset value of the CEXT IRCF<2:0> bits (‘110’). PIC18F87K22 VSS Regardless of which primary oscillator is selected, OSC2/CLKO INTRC will always be enabled on device power-up. It FOSC/4 serves as the clock source until the device has loaded its configuration values from memory. It is at this point Recommended values: 3 k  REXT  100 k 20 pF CEXT  300 pF that the FOSC Configuration bits are read and the oscillator selection of the operational mode is made. The RCIO Oscillator mode (Figure3-3) functions like Note that either the primary clock source or the internal the RC mode, except that the OSC2 pin becomes an oscillator will have two bit setting options for the possible additional general purpose I/O pin. The I/O pin values of the SCS<1:0> bits, at any given time. becomes bit 6 of PORTA (RA6). 3.3.3 OSCILLATOR TRANSITIONS FIGURE 3-3: RCIO OSCILLATOR MODE PIC18F87K22 family devices contain circuitry to VDD prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs REXT during the clock switch. The length of this pause is the Internal OSC1 sum of two cycles of the old clock source and three to Clock four cycles of the new clock source. This formula CEXT assumes that the new clock source is stable. PIC18F87K22 Clock transitions are discussed in greater detail in VSS RA6 I/O (OSC2) Section4.1.2 “Entering Power-Managed Modes”. Recommended values: 3 k  REXT  100 k 20 pF CEXT  300 pF DS30009960F-page 46  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 3.5 External Oscillator Modes TABLE 3-3: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR 3.5.1 CRYSTAL OSCILLATOR/CERAMIC Typical Capacitor Values RESONATORS (HS MODES) Crystal Tested: Osc Type In HS or HSPLL Oscillator modes, a crystal or ceramic Freq. resonator is connected to the OSC1 and OSC2 pins to C1 C2 establish oscillation. Figure3-4 shows the pin HS 4 MHz 27 pF 27 pF connections. 8 MHz 22 pF 22 pF The oscillator design requires the use of a crystal rated 20 MHz 15 pF 15 pF for parallel resonant operation. Capacitor values are for design guidance only. Note: Use of a crystal rated for series resonant Different capacitor values may be required to produce operation may give a frequency out of the acceptable oscillator operation. The user should test crystal manufacturer’s specifications. the performance of the oscillator over the expected VDD and temperature range for the application. TABLE 3-2: CAPACITOR SELECTION FOR Refer to the Microchip application notes cited in CERAMIC RESONATORS Table3-2 for oscillator-specific information. Also see the notes following this table for additional Typical Capacitor Values Used: information. Mode Freq. OSC1 OSC2 HS 8.0 MHz 27 pF 27 pF Note1: Higher capacitance increases the stability 16.0 MHz 22 pF 22 pF of the oscillator but also increases the Capacitor values are for design guidance only. start-up time. Different capacitor values may be required to produce 2: Since each resonator/crystal has its own acceptable oscillator operation. The user should test characteristics, the user should consult the performance of the oscillator over the expected the resonator/crystal manufacturer for VDD and temperature range for the application. Refer appropriate values of external to the following application notes for oscillator-specific components. information: 3: Rs may be required to avoid overdriving • AN588, “PIC® Microcontroller Oscillator Design crystals with a low drive level specification. Guide” 4: Always verify oscillator performance over • AN826, “Crystal Oscillator Basics and Crystal the VDD and temperature range that is Selection for rfPIC® and PIC® Devices” expected for the application. • AN849, “Basic PIC® Oscillator Design” • AN943, “Practical PIC® Oscillator Analysis and FIGURE 3-4: CRYSTAL/CERAMIC Design” RESONATOR OPERATION • AN949, “Making Your Oscillator Work” (HS OR HSPLL See the notes following Table3-3 for additional CONFIGURATION) information. C1(1) OSC1 To Internal XTAL RF(3) Logic OSC2 Sleep C2(1) RS(2) PIC18F87K22 Note 1: See Table3-2 and Table3-3 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the oscillator mode chosen.  2009-2018 Microchip Technology Inc. DS30009960F-page 47

PIC18F87K22 FAMILY 3.5.2 EXTERNAL CLOCK INPUT 3.5.3.1 HSPLL and ECPLL Modes (EC MODES) The HSPLL and ECPLL modes provide the ability to The EC and ECPLL Oscillator modes require an selectively run the device at four times the external external clock source to be connected to the OSC1 pin. oscillating source to produce frequencies up to There is no oscillator start-up time required after a 64MHz. Power-on Reset or after an exit from Sleep mode. The PLL is enabled by setting the PLLEN bit In the EC Oscillator mode, the oscillator frequency, (OSCTUNE<6>) or the PLLCFG bit (CONFIG1H<4>). divided by 4, is available on the OSC2 pin. This signal The PLLEN bit provides a software control for the PLL, may be used for test purposes or to synchronize other even if PLLCFG is set to ‘0’. The PLL is enabled only logic. Figure3-5 shows the pin connections for the EC when the HS or EC oscillator frequency is within the Oscillator mode. 4MHz to16 MHz input range. This enables additional flexibility for controlling the FIGURE 3-5: EXTERNAL CLOCK application’s clock speed in software. The PLLEN INPUT OPERATION should be enabled in HS or EC Oscillator mode only if (EC CONFIGURATION) the input frequency is in the range of 4MHz-16MHz. FIGURE 3-7: PLL BLOCK DIAGRAM Clock from OSC1/CLKI Ext. System PIC18F87K22 PLLCFG (CONFIG1H<4>) PLL Enable (OSCTUNE) FOSC/4 OSC2/CLKO OSC2 An external clock source may also be connected to the Phase OSC1 pin in HS mode, as shown in Figure3-6. In this HS or EC FIN Comparator configuration, the divide-by-4 output on OSC2 is not OSC1 Mode FOUT available. Current consumption in this configuration will be somewhat higher than EC mode, as the internal Loop oscillator’s feedback circuitry will be enabled (in EC Filter mode, the feedback circuit is disabled). FIGURE 3-6: EXTERNAL CLOCK INPUT 4 VCO SYSCLK OPERATION (HS OSC X U CONFIGURATION) M Clock from OSC1 Ext. System PIC18F87K22 3.5.3.2 PLL and HF-INTOSC (HS Mode) Open OSC2 The PLL is available to the internal oscillator block when the internal oscillator block is configured as the primary clock source. In this configuration, the PLL is enabled in software and generates a clock output of up 3.5.3 PLL FREQUENCY MULTIPLIER to 64MHz. A Phase Locked Loop (PLL) circuit is provided as an The operation of INTOSC with the PLL is described in option for users who want to use a lower frequency Section3.6.2 “INTPLL Modes”. Care should be taken oscillator circuit, or to clock the device up to its highest that the PLL is enabled only if the HF-INTOSC rated frequency from a crystal oscillator. This may be postscaler is configured for 8MHz or 16MHz. useful for customers who are concerned with EMI due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator. DS30009960F-page 48  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 3.6 Internal Oscillator Block FIGURE 3-8: INTIO1 OSCILLATOR MODE The PIC18F87K22 family of devices includes an internal oscillator block which generates two different clock RA7 I/O (OSC1) signals. Either clock can be used as the microcontroller’s PIC18F87K22 clock source, which may eliminate the need for an external oscillator circuit on the OSC1 and/or OSC2 pins. FOSC/4 OSC2 The internal oscillator consists of three blocks, depending on the frequency of operation. They are HF-INTOSC, MF-INTOSC and LF-INTRC. FIGURE 3-9: INTIO2 OSCILLATOR MODE In HF-INTOSC mode, the internal oscillator can provide a frequency ranging from 31kHz to 16MHz, with the postscaler deciding the selected frequency RA7 I/O (OSC1) (IRCF<2:0>). PIC18F87K22 The INTSRC bit (OSCTUNE<7>) and MFIOSEL bit RA6 I/O (OSC2) (OSCCON2<0>) also decide which INTOSC provides the lower frequency (500kHz to 31KHz). For the HF-INTOSC to provide these frequencies, INTSRC= 1 and MFIOSEL = 0. 3.6.2 INTPLL MODES In HF-INTOSC, the postscaler (IRCF<2:0>) provides the The 4x Phase Lock Loop (PLL) can be used with the frequency range of 31kHz to 16MHz. If HF-INTOSC is HF-INTOSC to produce faster device clock speeds used with the PLL, the input frequency to the PLL should than are normally possible with the internal oscillator be 8 MHz or 16 MHz (IRCF<2:0>=111 or 110). sources. When enabled, the PLL produces a clock For MF-INTOSC mode to provide a frequency range of speed of 32MHz or 64MHz. 500kHz to 31kHz, INTSRC = 1 and MFIOSEL = 1. The postscaler (IRCF<2:0>), in this mode, provides the PLL operation is controlled through software. The frequency range of 31kHz to 500kHz. control bit, PLLEN (OSCTUNE<6>), is used to enable or disable its operation. Additionally, the PLL will only func- The LF-INTRC can provide only 31kHz if INTSRC = 0. tion when the selected HF-INTOSC frequency is either The LF-INTRC provides 31kHz and is enabled if it is 8MHz or 16 MHz (OSCCON<6:4> = 111 or 110). selected as the device clock source. The mode is Like the INTIO modes, there are two distinct INTPLL enabled automatically when any of the following are modes available: enabled: • Power-up Timer • In INTPLL1 mode, the OSC2 pin outputs FOSC/4, • Fail-Safe Clock Monitor while OSC1 functions as RA7 for digital input and output. Externally, this is identical in appearance • Watchdog Timer to INTIO1 (Figure3-8). • Two-Speed Start-up • In INTPLL2 mode, OSC1 functions as RA7 and These features are discussed in greater detail in OSC2 functions as RA6, both for digital input and Section28.0 “Special Features of the CPU”. output. Externally, this is identical to INTIO2 The clock source frequency (HF-INTOSC, MF-INTOSC (Figure3-9). or LF-INTRC direct) is selected by configuring the IRCF bits of the OSCCON register, as well the INTSRC and MFIOSEL bits. The default frequency on device Resets is 8MHz. 3.6.1 INTIO MODES Using the internal oscillator as the clock source elimi- nates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct oscillator configurations, which are determined by the FOSC Configuration bits, are available: • In INTIO1 mode, the OSC2 pin (RA6) outputs FOSC/4, while OSC1 functions as RA7 (see Figure3-8) for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6 (see Figure3-9). Both are available as digital input and output ports.  2009-2018 Microchip Technology Inc. DS30009960F-page 49

PIC18F87K22 FAMILY 3.6.3 INTERNAL OSCILLATOR OUTPUT 3.6.4.3 Compensating with the CCP Module FREQUENCY AND TUNING in Capture Mode The internal oscillator block is calibrated at the factory A CCP module can use free-running Timer1 (or Tim- to produce an INTOSC output frequency of 16MHz. It er3), clocked by the internal oscillator block and an can be adjusted in the user’s application by writing to external event with a known period (i.e., AC power TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE frequency). The time of the first event is captured in the register (Register3-3). CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the When the OSCTUNE register is modified, the INTOSC time of the first event is subtracted from the time of the (HF-INTOSC and MF-INTOSC) frequency will begin second event. Since the period of the external event is shifting to the new frequency. The oscillator will require known, the time difference between events can be some time to stabilize. Code execution continues calculated. during this shift and there is no indication that the shift has occurred. If the measured time is much greater than the calculated time, the internal oscillator block is running The LF-INTOSC oscillator operates independently of too fast. To compensate, decrement the OSCTUNE the HF-INTOSC or the MF-INTOSC source. Any register. If the measured time is much less than the changes in the HF-INTOSC or the MF-INTOSC source, calculated time, the internal oscillator block is running across voltage and temperature, are not necessarily too slow. To compensate, increment the OSCTUNE reflected by changes in LF-INTOSC or vice versa. The register. frequency of LF-INTOSC is not affected by OSCTUNE. 3.6.5 LFINTOSC OPERATION IN SLEEP 3.6.4 INTOSC FREQUENCY DRIFT When the Watchdog Timer (WDT) or Real-Time Clock The INTOSC frequency may drift as VDD or tempera- and Calendar (RTCC) modules are enabled and ture changes, and can affect the controller operation in configured to use the LFINTOSC, the LFINTOSC will a variety of ways. It is possible to adjust the INTOSC continue to run when the device is in Sleep, unlike frequency by modifying the value in the OSCTUNE other internal clock sources. register. Depending on the device, this may have no effect on the LF-INTOSC clock source frequency. While in Sleep, the LFINTOSC has two power modes, a High-Power and a Low-Power mode, controlled by Tuning INTOSC requires knowing when to make the the INTOSCSEL bit in the CONFIG1L Configuration adjustment, in which direction it should be made, and in Word. The High-Power mode is the same as the some cases, how large a change is needed. Three LFINTOSC while the part is awake and conforms to the compensation techniques are shown here. specifications outlined for that oscillator. The Low- 3.6.4.1 Compensating with the EUSART Power mode consumes less current, but has a much lower accuracy and is not recommended for An adjustment may be required when the EUSART timing-sensitive applications. begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indi- 3.7 Reference Clock Output cate that the device clock frequency is too high. To adjust for this, decrement the value in OSCTUNE to reduce the In addition to the FOSC/4 clock output, in certain clock frequency. On the other hand, errors in data may oscillator modes, the device clock in the PIC18F87K22 suggest that the clock speed is too low. To compensate, family can also be configured to provide a reference increment OSCTUNE to increase the clock frequency. clock output signal to a port pin. This feature is avail- able in all oscillator configurations and allows the user 3.6.4.2 Compensating with the Timers to select a greater range of clock submultiples to drive This technique compares device clock speed to some external devices in the application. reference clock. Two timers may be used; one timer is This reference clock output is controlled by the clocked by the peripheral clock, while the other is clocked REFOCON register (Register3-4). Setting the ROON by a fixed reference source, such as the SOSC oscillator. bit (REFOCON<7>) makes the clock signal available Both timers are cleared, but the timer clocked by the on the REFO (RE3) pin. The RODIV<3:0> bits enable reference source generates interrupts. When an inter- the selection of 16 different clock divider options. rupt occurs, the internally clocked timer is read and The ROSSLP and ROSEL bits (REFOCON<5:4>) con- both timers are cleared. If the internally clocked timer trol the availability of the reference output during Sleep value is much greater than expected, then the internal mode. The ROSEL bit determines if the oscillator on oscillator block is running too fast. To adjust for this, OSC1 and OSC2, or the current system clock source, decrement the OSCTUNE register. is used for the reference clock output. The ROSSLP bit determines if the reference source is available on RE3 when the device is in Sleep mode. DS30009960F-page 50  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for an EC or HS mode. If not, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches.  2009-2018 Microchip Technology Inc. DS30009960F-page 51

PIC18F87K22 FAMILY REGISTER 3-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL(1) RODIV3 RODIV2 RODIV1 RODIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output is available on REFO pin 0 = Reference oscillator output is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 4 ROSEL: Reference Oscillator Source Select bit(1) 1 = Primary oscillator (EC or HS) is used as the base clock 0 = System clock is used as the base clock; base clock reflects any clock switching of the device bit 3-0 RODIV<3:0>: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value Note 1: For ROSEL (REVOCON<4>), the primary oscillator is available only when configured as the default via the FOSC settings. This is regardless of whether the device is in Sleep mode. DS30009960F-page 52  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 3.8 Effects of Power-Managed Modes Real-Time Clock (RTC). Other features may be operat- on the Various Clock Sources ing that do not require a device clock source (i.e., MSSP slave, INTx pins and others). Peripherals that When PRI_IDLE mode is selected, the designated pri- may add significant current consumption are listed in mary oscillator continues to run without interruption. Section31.2 “DC Characteristics: Power-Down and For all other power-managed modes, the oscillator Supply Current PIC18F87K22 Family (Industrial/ using the OSC1 pin is disabled. The OSC1 pin (and Extended)”. OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_I- 3.9 Power-up Delays DLE), the SOSC oscillator is operating and providing Power-up delays are controlled by two timers, so that the device clock. The SOSC oscillator may also run in no external Reset circuitry is required for most applica- all power-managed modes if required to clock SOSC. tions. The delays ensure that the device is kept in In RC_RUN and RC_IDLE modes, the internal Reset until the device power supply is stable under nor- oscillator provides the device clock source. The 31kHz mal circumstances and the primary clock is operating LF-INTOSC output can be used directly to provide the and stable. For additional information on power-up clock and may be enabled to support various special delays, see Section5.6 “Power-up Timer (PWRT)”. features, regardless of the power-managed mode (see The first timer is the Power-up Timer (PWRT), which Section28.2 “Watchdog Timer (WDT)” through provides a fixed delay on a power-up time of about Section28.5 “Fail-Safe Clock Monitor” for more 1ms (Parameter 33, Table31-14). information on WDT, Fail-Safe Clock Monitor and Two-Speed Start-up). The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the If Sleep mode is selected, all clock sources are crystal oscillator is stable (HS, XT or LP modes). The stopped. Since all the transistor switching currents OST does this by counting 1,024 oscillator cycles have been stopped, Sleep mode achieves the lowest before allowing the oscillator to clock the device. current consumption of the device (only leakage currents). There is a delay of interval, TCSD (Parameter 38, Table31-14), following POR, while the controller Enabling any on-chip feature that will operate during becomes ready to execute instructions. Sleep will increase the current consumed during Sleep. The INTOSC is required to support WDT operation. The SOSC oscillator may be operating to support a TABLE 3-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output) HS, HSPLL Feedback inverter is disabled at quiescent Feedback inverter is disabled at quiescent voltage level voltage level INTOSC, INTPLL1/2 I/O pin, RA6, direction is controlled by I/O pin, RA6, direction is controlled by TRISA<6> TRISA<7> Note: See Section5.0 “Reset” for time-outs due to Sleep and MCLR Reset.  2009-2018 Microchip Technology Inc. DS30009960F-page 53

PIC18F87K22 FAMILY 4.0 POWER-MANAGED MODES The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the The PIC18F87K22 family of devices offers a total of clock source. The individual modes, bit settings, clock seven operating modes for more efficient power man- sources and affected modules are summarized in agement. These modes provide a variety of options for Table4-1. selective power conservation in applications where resources may be limited (such as battery-powered 4.1.1 CLOCK SOURCES devices). The SCS<1:0> bits select one of three clock sources There are three categories of power-managed mode: for power-managed modes. Those sources are: • Run modes • The primary clock as defined by the FOSC<3:0> • Idle modes Configuration bits • Sleep mode • The secondary clock (the SOSC oscillator) • The internal oscillator block (for LF-INTOSC There is an Ultra Low-Power Wake-up (ULPWU) for modes) waking from the Sleep mode. These categories define which portions of the device 4.1.2 ENTERING POWER-MANAGED are clocked, and sometimes, at what speed. The Run MODES and Idle modes may use any of the three available Switching from one power-managed mode to another clock sources (primary, secondary or internal oscillator begins by loading the OSCCON register. The block). The Sleep mode does not use a clock source. SCS<1:0> bits select the clock source and determine The ULPWU mode, on the RA0 pin, enables a slow fall- which Run or Idle mode is used. Changing these bits ing voltage to generate a wake-up, even from Sleep, causes an immediate switch to the new clock source, without excess current consumption. (See Section4.7 assuming that it is running. The switch may also be “Ultra Low-Power Wake-up”.) subject to clock transition delays. These considerations The power-managed modes include several power- are discussed in Section4.1.3 “Clock Transitions saving features offered on previous PIC® devices. One and Status Indicators” and subsequent sections. is the clock switching feature, offered in other PIC18 Entering the power-managed Idle or Sleep modes is devices. This feature allows the controller to use the triggered by the execution of a SLEEP instruction. The SOSC oscillator instead of the primary one. Another actual mode that results depends on the status of the power-saving feature is Sleep mode, offered by all PIC IDLEN bit. devices, where all device clocks are stopped. Depending on the current and impending mode, a change to a power-managed mode does not always 4.1 Selecting Power-Managed Modes require setting all of the previously discussed bits. Many Selecting a power-managed mode requires two transitions can be done by changing the oscillator select decisions: bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured as • Will the CPU be clocked or not desired, it may only be necessary to perform a SLEEP • What will be the clock source instruction to switch to the desired mode. TABLE 4-1: POWER-MANAGED MODES OSCCON Bits Module Clocking Mode Available Clock and Oscillator Source IDLEN<7>(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled Primary – XT, LP, HS, EC, RC and PLL modes. PRI_RUN N/A 00 Clocked Clocked This is the normal, Full-Power Execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – SOSC Oscillator RC_RUN N/A 1x Clocked Clocked Internal oscillator block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – SOSC oscillator RC_IDLE 1 1x Off Clocked Internal oscillator block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTOSC source. DS30009960F-page 54  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS 4.1.4 MULTIPLE SLEEP COMMANDS INDICATORS The power-managed mode that is invoked with the The length of the transition between clock sources is SLEEP instruction is determined by the setting of the the sum of two cycles of the old clock source and IDLEN bit at the time the instruction is executed. If three to four cycles of the new clock source. This for- another SLEEP instruction is executed, the device will mula assumes that the new clock source is stable. enter the power-managed mode specified by IDLEN at The HF-INTOSC and MF-INTOSC are termed as that time. If IDLEN has changed, the device will enter INTOSC in this chapter. the new power-managed mode specified by the new Three bits indicate the current clock source and its setting. status, as shown in Table4-2. The three bits are: 4.2 Run Modes • OSTS (OSCCON<3>) In the Run modes, clocks to both the core and • HFIOFS (OSCCON<2>) peripherals are active. The difference between these • SOSCRUN (OSCCON2<6>) modes is the clock source. TABLE 4-2: SYSTEM CLOCK INDICATOR 4.2.1 PRI_RUN MODE HFIOFS or The PRI_RUN mode is the normal, Full-Power Execu- Main Clock Source OSTS SOSCRUN MFIOFS tion mode of the microcontroller. This is also the default mode upon a device Reset, unless Two-Speed Start-up Primary Oscillator 1 0 0 is enabled. (For details, see Section28.4 “Two-Speed INTOSC (HF-INTOSC or 0 1 0 Start-up”.) In this mode, the OSTS bit is set. The MF-INTOSC) HFIOFS or MFIOFS bit may be set if the internal Secondary Oscillator 0 0 1 oscillator block is the primary clock source. (See MF-INTOSC or Section3.2 “Control Registers”.) HF-INTOSC as Primary 1 1 0 4.2.2 SEC_RUN MODE Clock Source LF-INTOSC is Running or The SEC_RUN mode is the compatible mode to the INTOSC is Not Yet Stable 0 0 0 “clock-switching” feature offered in other PIC18 devices. In this mode, the CPU and peripherals are When the OSTS bit is set, the primary clock is providing clocked from the SOSC oscillator. This enables lower the device clock. When the HFIOFS or MFIOFS bit is power consumption while retaining a high-accuracy set, the INTOSC output is providing a stable 16MHz clock source. clock source to a divider that actually drives the device clock. When the SOSCRUN bit is set, the SOSC oscil- SEC_RUN mode is entered by setting the SCS<1:0> lator is providing the clock. If none of these bits are set, bits to ‘01’. The device clock source is switched to the either the LF-INTOSC clock source is clocking the SOSC oscillator (see Figure4-1), the primary oscillator device or the INTOSC source is not yet stable. is shut down, the SOSCRUN bit (OSCCON2<6>) is set and the OSTS bit is cleared. If the internal oscillator block is configured as the primary clock source by the FOSC<3:0> Configuration Note: The SOSC oscillator can be enabled by bits (CONFIG1H<3:0>), then the OSTS and HFIOFS or setting the SOSCGO bit (OSCCON2<3>). MFIOFS bits can be set when in PRI_RUN or PRI_I- If this bit is set, the clock switch to the DLE modes. This indicates that the primary clock SEC_RUN mode can switch immediately (INTOSC output) is generating a stable 16MHz output. once SCS<1:0> are set to ‘01’. Entering another INTOSC power-managed mode at the same frequency would clear the OSTS bit. On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked Note1: Caution should be used when modifying from the SOSC oscillator while the primary clock is a single IRCF bit. At a lower VDD, it is started. When the primary clock becomes ready, a possible to select a higher clock speed clock switch back to the primary clock occurs (see than is supportable by that VDD. Improper Figure4-2). When the clock switch is complete, the device operation may result if the VDD/ SOSCRUN bit is cleared, the OSTS bit is set and the FOSC specifications are violated. primary clock is providing the clock. The IDLEN and 2: Executing a SLEEP instruction does not SCS bits are not affected by the wake-up and the necessarily place the device into Sleep SOSC oscillator continues to run. mode. It acts as the trigger to place the controller into either the Sleep mode or one of the Idle modes, depending on the setting of the IDLEN bit.  2009-2018 Microchip Technology Inc. DS30009960F-page 55

PIC18F87K22 FAMILY FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 SOSCI 1 2 3 n-1 n OSC1 Clock Transition(1) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 SOSC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> bits Changed OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS30009960F-page 56  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 4.2.3 RC_RUN MODE the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to In RC_RUN mode, the CPU and peripherals are immediately change the clock speed. clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is Note: Caution should be used when modifying a shut down. When using the LF-INTOSC source, this single IRCF bit. At a lower VDD, it is mode provides the best power conservation of all the possible to select a higher clock speed Run modes, while still executing code. It works well for than is supportable by that VDD. Improper user applications which are not highly timing-sensitive device operation may result if the VDD/ or do not require high-speed clocks at all times. FOSC specifications are violated. If the primary clock source is the internal oscillator If the IRCF bits and the INTSRC bit are all clear, the block – either LF-INTOSC or INTOSC (MF-INTOSC or INTOSC output (HF-INTOSC/MF-INTOSC) is not HF-INTOSC) – there are no distinguishable differences enabled and the HFIOFS and MFIOFS bits will remain between the PRI_RUN and RC_RUN modes during clear. There will be no indication of the current clock execution. Entering or exiting RC_RUN mode, how- source. The LF-INTOSC source is providing the device ever, causes a clock switch delay. Therefore, if the clocks. primary clock source is the internal oscillator block, If the IRCF bits are changed from all clear (thus, using RC_RUN mode is not recommended. enabling the INTOSC output), or if INTSRC or This mode is entered by setting the SCS1 bit to ‘1’. To MFIOSEL is set, the HFIOFS or MFIOFS bit is set after maintain software compatibility with future devices, it is the INTOSC output becomes stable. For details, see recommended that the SCS0 bit also be cleared, even Table4-3. though the bit is ignored. When the clock source is switched to the INTOSC multiplexer (see Figure4-3), TABLE 4-3: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS IRCF<2:0> INTSRC MFIOSEL Status of MFIOFS or HFIOFS when INTOSC is Stable 000 0 x MFIOFS = 0, HFIOFS = 0 and clock source is LF-INTOSC 000 1 0 MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC 000 1 1 MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC Non-Zero x 0 MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC Non-Zero x 1 MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC  2009-2018 Microchip Technology Inc. DS30009960F-page 57

PIC18F87K22 FAMILY Clocks to the device continue while the INTOSC source On transitions from RC_RUN mode to PRI_RUN mode, stabilizes after an interval of TIOBST (Parameter 39, the device continues to be clocked from the INTOSC Table31-14). multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the If the IRCF bits were previously at a non-zero value, or primary clock occurs (see Figure4-4). When the clock if INTSRC was set before setting SCS1 and the switch is complete, the HFIOFS or MFIOFS bit is INTOSC source was already stable, the HFIOFS or cleared, the OSTS bit is set and the primary clock is MFIOFS bit will remain set. providing the device clock. The IDLEN and SCS bits are not affected by the switch. The LF-INTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 LF-INTOSC 1 2 3 n-1 n OSC1 Clock Transition(1) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> bits Changed OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS30009960F-page 58  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 4.3 Sleep Mode 4.4 Idle Modes The power-managed Sleep mode in the PIC18F87K22 The Idle modes allow the controller’s CPU to be family of devices is identical to the legacy Sleep mode selectively shut down while the peripherals continue to offered in all other PIC devices. It is entered by clearing operate. Selecting a particular Idle mode allows users the IDLEN bit (the default state on device Reset) and to further manage power consumption. executing the SLEEP instruction. This shuts down the If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is selected oscillator (Figure4-5). All clock source status executed, the peripherals will be clocked from the clock bits are cleared. source selected using the SCS<1:0> bits. The CPU, Entering Sleep mode from any other mode does not however, will not be clocked. The clock source status bits require a clock switch. This is because no clocks are are not affected. This approach is a quick method to needed once the controller has entered Sleep. If the switch from a given Run mode to its corresponding Idle WDT is selected, the LF-INTOSC source will continue mode. to operate. If the SOSC oscillator is enabled, it will also If the WDT is selected, the LF-INTOSC source will continue to run. continue to operate. If the SOSC oscillator is enabled, When a wake event occurs in Sleep mode (by interrupt, it will also continue to run. Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only until the clock source selected by the SCS<1:0> bits exits from any of the Idle modes are by interrupt, WDT becomes ready (see Figure4-6). Alternately, the device time-out or a Reset. When a wake event occurs, CPU will be clocked from the internal oscillator block if either execution is delayed by an interval of TCSD the Two-Speed Start-up or the Fail-Safe Clock Monitor is (Parameter38, Table31-14) while it becomes ready to enabled (see Section28.0 “Special Features of the execute code. When the CPU begins executing code, CPU”). In either case, the OSTS bit is set when the it resumes with the same clock source for the current primary clock is providing the device clocks. The IDLEN Idle mode. For example, when waking from RC_IDLE and SCS bits are not affected by the wake-up. mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time- out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale.  2009-2018 Microchip Technology Inc. DS30009960F-page 59

PIC18F87K22 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes, in that it does not disable the primary device peripherals continue to be clocked from the SOSC clock. For timing-sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by set- the fastest resumption of device operation with its more ting the IDLEN bit and executing a SLEEP instruction. If accurate, primary clock source, since the clock source the device is in another Run mode, set the IDLEN bit does not have to “warm-up” or transition from another first, then set the SCS<1:0> bits to ‘01’ and execute oscillator. SLEEP. When the clock source is switched to the SOSC oscillator, the primary oscillator is shut down, the OSTS PRI_IDLE mode is entered from PRI_RUN mode by bit is cleared and the SOSCRUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then clear the SCS bits and execute SLEEP. be clocked from the SOSC oscillator. After an interval Although the CPU is disabled, the peripherals continue of TCSD following the wake event, the CPU begins to be clocked from the primary clock source specified executing code being clocked by the SOSC oscillator. by the FOSC<3:0> Configuration bits. The OSTS bit The IDLEN and SCS bits are not affected by the wake- remains set (see Figure4-7). up and the SOSC oscillator continues to run (see Figure4-8). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, TCSD (Parameter 39, Table31-14), is required between the wake event and the start of code execution. This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure4-8). FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event DS30009960F-page 60  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 4.4.3 RC_IDLE MODE 4.5 Selective Peripheral Module Control In RC_IDLE mode, the CPU is disabled but the periph- erals continue to be clocked from the internal oscillator Idle mode allows users to substantially reduce power block using the INTOSC multiplexer. This mode consumption by stopping the CPU clock. Even so, provides controllable power conservation during Idle peripheral modules still remain clocked, and thus, periods. consume power. There may be cases where the appli- From RC_RUN, this mode is entered by setting the cation needs what this mode does not provide: the IDLEN bit and executing a SLEEP instruction. If the allocation of power resources to the CPU processing device is in another Run mode, first set IDLEN, then set with minimal power consumption from the peripherals. the SCS1 bit and execute SLEEP. To maintain software PIC18F87K22 family devices address this requirement compatibility with future devices, it is recommended by allowing peripheral modules to be selectively that SCS0 also be cleared, though its value is ignored. disabled, reducing or eliminating their power The INTOSC multiplexer may be used to select a consumption. This can be done with two control bits: higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the • Peripheral Enable bit, generically named XXXEN – clock source is switched to the INTOSC multiplexer, the Located in the respective module’s main control primary oscillator is shut down and the OSTS bit is register cleared. • Peripheral Module Disable (PMD) bit, generically named, XXXMD – Located in one of the PMDx If the IRCF bits are set to any non-zero value, or the Control registers (PMD0, PMD1, PMD2 or PMD3) INTSRC/MFIOSEL bit is set, the INTOSC output is enabled. The HFIOFS/MFIOFS bits become set, after Disabling a module by clearing its XXXEN bit disables the INTOSC output becomes stable, after an interval of the module’s functionality, but leaves its registers TIOBST (Parameter38, Table31-14). (For information available to be read and written to. This reduces power on the HFIOFS/MFIOFS bits, see Table4-3.) consumption, but not by as much as the second approach. Clocks to the peripherals continue while the INTOSC source stabilizes. The HFIOFS/MFIOFS bits will Most peripheral modules have an enable bit. remain set if the IRCF bits were previously at a non- In contrast, setting the PMD bit for a module disables zero value or if INTSRC was set before the SLEEP all clock sources to that module, reducing its power instruction was executed and the INTOSC source was consumption to an absolute minimum. In this state, the already stable. If the IRCF bits and INTSRC are all control and status registers associated with the periph- clear, the INTOSC output will not be enabled, the eral are also disabled, so writes to those registers have HFIOFS/MFIOFS bits will remain clear and there will be no effect and read values are invalid. Many peripheral no indication of the current clock source. modules have a corresponding PMD bit. When a wake event occurs, the peripherals continue to There are four PMD registers in the PIC18F87K22 family be clocked from the INTOSC multiplexer. After a delay devices: PMD0, PMD1, PMD2 and PMD3. These of TCSD (Parameter 38, Table31-14) following the registers have bits associated with each module for wake event, the CPU begins executing code clocked disabling or enabling a particular peripheral. by the INTOSC multiplexer. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.  2009-2018 Microchip Technology Inc. DS30009960F-page 61

PIC18F87K22 FAMILY REGISTER 4-1: PMD3: PERIPHERAL MODULE DISABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP10MD(1) CCP9MD(1) CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD TMR12MD(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CCP10MD: PMD CCP10 Enable/Disable bit(1) 1 = Peripheral Module Disable (PMD) is enabled for CCP10, disabling all of its clock sources 0 = PMD is disabled for CCP10 bit 6 CCP9MD: PMD CCP9 Enable/Disable bit(1) 1 = Peripheral Module Disable (PMD) is enabled for CCP9, disabling all of its clock sources 0 = PMD is disabled for CCP9 bit 5 CCP8MD: PMD CCP8 Enable/Disable bit 1 = Peripheral Module Disable (PMD) is enabled for CCP8, disabling all of its clock sources 0 = PMD is disabled for CCP8 bit 4 CCP7MD: PMD CCP7 Enable/Disable bit 1 = Peripheral Module Disable (PMD) is enabled for CCP7, disabling all of its clock sources 0 = PMD is disabled for CCP7 bit 3 CCP6MD: PMD CCP6 Enable/Disable bit 1 = Peripheral Module Disable (PMD) is enabled for CCP6, disabling all of its clock sources 0 = PMD is disabled for CCP6 bit 2 CCP5MD: PMD CCP5 Enable/Disable bit 1 = Peripheral Module Disable (PMD) is enabled for CCP5, disabling all of its clock sources 0 = PMD is disabled for CCP5 bit 1 CCP4MD: PMD CCP4 Enable/Disable bit 1 = Peripheral Module Disable (PMD) is enabled for CCP4, disabling all of its clock sources 0 = PMD is disabled for CCP4 bit 0 TMR12MD: TMR12MD Disable bit(1) 1 = PMD is enabled and all TMR12MD clock sources are disabled 0 = PMD is disabled and TMR12MD is enabled Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). DS30009960F-page 62  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 4-2: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR10MD(1) TMR8MD TMR7MD(1) TMR6MD TMR5MD CMP3MD CMP2MD CMP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR10MD: TMR10MD Disable bit(1) 1 = Peripheral Module Disable (PMD) is enabled and all TMR10MD clock sources are disabled 0 = PMD is disabled and TMR10MD is enabled bit 6 TMR8MD: TMR8MD Disable bit 1 = PMD is enabled and all TMR8MD clock sources are disabled 0 = PMD is disabled and TMR8MD is enabled bit 5 TMR7MD: TMR7MD Disable bit(1) 1 = PMD is enabled and all TMR7MD clock sources are disabled 0 = PMD is disabled and TMR7MD is enabled bit 4 TMR6MD: TMR6MD Disable bit 1 = PMD is enabled and all TMR6MD clock sources are disabled 0 = PMD is disabled and TMR6MD is enabled bit 3 TMR5MD: TMR5MD Disable bit 1 = PMD is enabled and all TMR5MD clock sources are disabled 0 = PMD is disabled and TMR5MD is enabled bit 2 CMP3MD: PMD Comparator 3 Enable/Disable bit 1 = PMD is enabled for Comparator 3, disabling all of its clock sources 0 = PMD is disabled for Comparator 3 bit 1 CMP2MD: PMD Comparator 3 Enable/Disable bit 1 = PMD is enabled for Comparator 2, disabling all of its clock sources 0 = PMD is disabled for Comparator 2 bit 0 CMP1MD: PMD Comparator 3 Enable/Disable bit 1 = PMD is enabled for Comparator 1, disabling all of its clock sources 0 = PMD is disabled for Comparator 1 Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 63

PIC18F87K22 FAMILY REGISTER 4-3: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPMD CTMUMD RTCCMD(1) TMR4MD TMR3MD TMR2MD TMR1MD EMBMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPMD: Peripheral Module Disable (PMD) PSP Enable/Disable bit 1 = PMD is enabled for PSP, disabling all of its clock sources 0 = PMD is disabled for PSP bit 6 CTMUMD: PMD CTMU Enable/Disable bit 1 = PMD is enabled for CTMU, disabling all of its clock sources 0 = PMD is disabled for CTMU bit 5 RTCCMD: PMD RTCC Enable/Disable bit(1) 1 = PMD is enabled for RTCC, disabling all of its clock sources 0 = PMD is disabled for RTCC bit 4 TMR4MD: TMR4MD Disable bit 1 = PMD is enabled and all TMR4MD clock sources are disabled 0 = PMD is disabled and TMR4MD is enabled bit 3 TMR3MD: TMR3MD Disable bit 1 = PMD is enabled and all TMR3MD clock sources are disabled 0 = PMD is disabled and TMR3MD is enabled bit 2 TMR2MD: TMR2MD Disable bit 1 = PMD is enabled and all TMR2MD clock sources are disabled 0 = PMD is disabled and TMR2MD is enabled bit 1 TMR1MD: TMR1MD Disable bit 1 = PMD is enabled and all TMR1MD clock sources are disabled 0 = PMD is disabled and TMR1MD is enabled bit 0 EMBMD: PMD EMB Enable/Disable bit 1 = PMD is enabled for EMB, disabling all of its clock sources 0 = PMD is disabled for EMB Note 1: RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence. Refer to Section18.0 “Real-Time Clock and Calendar (RTCC)” for the unlock sequence (Example18-1). DS30009960F-page 64  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 4-4: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CCP3MD: PMD ECCP3 Enable/Disable bit 1 = Peripheral Module Disable (PMD) is enabled for ECCP3, disabling all of its clock sources 0 = PMD is disabled for ECCP3 bit 6 CCP2MD: PMD ECCP2 Enable/Disable bit 1 = PMD is enabled for ECCP2, disabling all of its clock sources 0 = PMD is disabled for ECCP2 bit 5 CCP1MD: PMD ECCP1 Enable/Disable bit 1 = PMD is enabled for ECCP1, disabling all of its clock sources 0 = PMD is disabled for ECCP1 bit 4 UART2MD: PMD UART2 Enable/Disable bit 1 = PMD is enabled for UART2, disabling all of its clock sources 0 = PMD is disabled for UART2 bit 3 UART1MD: PMD UART1 Enable/Disable bit 1 = PMD is enabled for UART1, disabling all of its clock sources 0 = PMD is disabled for UART1 bit 2 SSP2MD: PMD MSSP2 Enable/Disable bit 1 = PMD is enabled for MSSP2, disabling all of its clock sources 0 = PMD is disabled for MSSP2 bit 1 SSP1MD: PMD MSSP1 Enable/Disable bit 1 = PMD is enabled for MSSP1, disabling all of its clock sources 0 = PMD is disabled for MSSP1 bit 0 ADCMD: PMD Analog/Digital Converter PMD Enable/Disable bit 1 = PMD is enabled for the Analog/Digital Converter, disabling all of its clock sources 0 = PMD is disabled for the Analog/Digital Converter  2009-2018 Microchip Technology Inc. DS30009960F-page 65

PIC18F87K22 FAMILY 4.6 Exiting Idle and Sleep Modes 4.6.3 EXIT BY RESET An exit from Sleep mode or any of the Idle modes is Normally, the device is held in Reset by the Oscillator triggered by an interrupt, a Reset or a WDT time-out. Start-up Timer (OST) until the primary clock becomes This section discusses the triggers that cause exits ready. At that time, the OSTS bit is set and the device from power-managed modes. The clocking subsystem begins executing code. If the internal oscillator block is actions are discussed in each of the power-managed the new clock source, the HFIOFS/MFIOFS bits are set modes (see Section4.2 “Run Modes”, Section4.3 instead. “Sleep Mode” and Section4.4 “Idle Modes”). The exit delay time from Reset to the start of code execution depends on both the clock sources before 4.6.1 EXIT BY INTERRUPT and after the wake-up, and the type of oscillator if the Any of the available interrupt sources can cause the new clock source is the primary clock. Exit delays are device to exit from an Idle mode or Sleep mode to a summarized in Table4-4. Run mode. To enable this functionality, an interrupt Code execution can begin before the primary clock source must be enabled by setting its enable bit in one becomes ready. If either the Two-Speed Start-up (see of the INTCONx or PIEx registers. The exit sequence is Section28.4 “Two-Speed Start-up”) or Fail-Safe initiated when the corresponding interrupt flag bit is set. Clock Monitor (see Section28.5 “Fail-Safe Clock On all exits from Idle or Sleep modes by interrupt, code Monitor”) is enabled, the device may begin execution execution branches to the interrupt vector if the GIE/ as soon as the Reset source has cleared. Execution is GIEH bit (INTCON<7>) is set. Otherwise, code execu- clocked by the INTOSC multiplexer driven by the tion continues or resumes without branching (see internal oscillator block. Execution is clocked by the Section11.0 “Interrupts”). internal oscillator block until either the primary clock becomes ready or a power-managed mode is entered 4.6.2 EXIT BY WDT TIME-OUT before the primary clock becomes ready; the primary clock is then shut down. A WDT time-out will cause different actions depending on which power-managed mode the device is in when 4.6.4 EXIT WITHOUT AN OSCILLATOR the time-out occurs. START-UP DELAY If the device is not executing code (all Idle modes and Certain exits from power-managed modes do not Sleep mode), the time-out will result in an exit from the invoke the OST at all. The two cases are: power-managed mode (see Section4.2 “Run Modes” and Section4.3 “Sleep Mode”). If the device • When in PRI_IDLE mode, where the primary is executing code (all Run modes), the time-out will clock source is not stopped result in a WDT Reset (see Section28.2 “Watchdog • When the primary clock source is not any of the Timer (WDT)”). LP, XT, HS or HSPLL modes Executing a SLEEP or CLRWDT instruction clears the In these instances, the primary clock source either WDT timer and postscaler, loses the currently selected does not require an oscillator start-up delay, since it is clock source (if the Fail-Safe Clock Monitor is enabled) already running (PRI_IDLE), or normally does not and modifies the IRCF bits in the OSCCON register (if require an oscillator start-up delay (RC, EC and INTIO the internal oscillator block is the device clock source). Oscillator modes). However, a fixed delay of interval, TCSD, following the wake event, is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. DS30009960F-page 66  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 4.7 Ultra Low-Power Wake-up A series resistor, between RA0 and the external capac- itor, provides overcurrent protection for the RA0/AN0/ The Ultra Low-Power Wake-up (ULPWU) on pin, RA0, ULPWU pin and enables software calibration of the allows a slow falling voltage to generate an interrupt time-out (see Figure4-9). without excess current consumption. To use this feature: FIGURE 4-9: ULTRA LOW-POWER WAKE-UP INITIALIZATION 1. Charge the capacitor on RA0 by configuring the RA0 pin to an output and setting it to ‘1’. 2. Stop charging the capacitor by configuring RA0 RA0/AN0/ULPWU as an input. 3. Discharge the capacitor by setting the ULPEN and ULPSINK bits in the WDTCON register. 4. Configure Sleep mode. 5. Enter Sleep mode. When the voltage on RA0 drops below VIL, the device wakes up and executes the next instruction. This feature provides a low-power technique for periodically waking up the device from Sleep mode. The time-out is dependent on the discharge time of the RC circuit on RA0. A timer can be used to measure the charge time and When the ULPWU module wakes the device from discharge time of the capacitor. The charge time can Sleep mode, the ULPLVL bit (WDTCON<5>) is set. then be adjusted to provide the desired delay in Sleep. Software can check this bit upon wake-up to determine This technique compensates for the affects of tempera- the wake-up source. ture, voltage and component accuracy. The peripheral can also be configured as a simple Programmable See Example4-1 for initializing the ULPWU module. Low-Voltage Detect (LVD) or temperature sensor. EXAMPLE 4-1: ULTRA LOW-POWER Note: For more information, see AN879, “Using WAKE-UP INITIALIZATION the Microchip Ultra Low-Power Wake-up Module” (DS00879). //*************************** //Charge the capacitor on RA0 //*************************** TRISAbits.TRISA0 = 0; PORTAbits.RA0 = 1; for(i = 0; i < 10000; i++) Nop(); //***************************** //Stop Charging the capacitor //on RA0 //***************************** TRISAbits.TRISA0 = 1; //***************************** //Enable the Ultra Low Power //Wakeup module and allow //capacitor discharge //***************************** WDTCONbits.ULPEN = 1; WDTCONbits.ULPSINK = 1; //For Sleep OSCCONbits.IDLEN = 0; //Enter Sleep Mode // Sleep(); //for sleep, execution will //resume here  2009-2018 Microchip Technology Inc. DS30009960F-page 67

PIC18F87K22 FAMILY TABLE 4-4: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Power-Managed Clock Ready Clock Source(5) Exit Delay Mode Status Bits LP, XT, HS HSPLL OSTS EC, RC PRI_IDLE mode TCSD(1) HF-INTOSC(2) HFIOFS MF-INTOSC(2) MFIOFS LF-INTOSC None SEC_IDLE mode SOSC TCSD(1) SOSCRUN HF-INTOSC(2) HFIOFS RC_IDLE mode MF-INTOSC(2) TCSD(1) MFIOFS LF-INTOSC None LP, XT, HS TOST(3) HSPLL TOST + trc(3) OSTS EC, RC TCSD(1) Sleep mode HF-INTOSC(2) HFIOFS MF-INTOSC(2) TIOBST(4) MFIOFS LF-INTOSC None Note 1: TCSD (Parameter 38, Table31-14) is a required delay when waking from Sleep and all Idle modes, and runs concurrently with any other required delays (see Section4.4 “Idle Modes”). 2: Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz. 3: TOST is the Oscillator Start-up Timer (Parameter 32, Table31-14). TRC is the PLL Lock-out Timer (Parameter F12, Table31-8); it is also designated as TPLL. 4: Execution continues during TIOBST (Parameter 39, Table31-14), the INTOSC stabilization period. 5: The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>) and FOSC (CONFIG1H<3:0>) bits. DS30009960F-page 68  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 5.0 RESET 5.1 RCON Register The PIC18F87K22 family of devices differentiates Device Reset events are tracked through the RCON between various kinds of Reset: register (Register5-1). The lower five bits of the register indicate that a specific Reset event has a) Power-on Reset (POR) occurred. In most cases, these bits can only be set by b) MCLR Reset during normal operation the event and must be cleared by the application after c) MCLR Reset during power-managed modes the event. d) Watchdog Timer (WDT) Reset (during The state of these flag bits, taken together, can be read execution) to indicate the type of Reset that just occurred. This is e) Configuration Mismatch (CM) Reset described in more detail in Section5.7 “Reset State f) Brown-out Reset (BOR) of Registers”. g) RESET Instruction The RCON register also has a control bit for setting h) Stack Full Reset interrupt priority (IPEN). Interrupt priority is discussed i) Stack Underflow Reset in Section11.0 “Interrupts”. This section discusses Resets generated by MCLR, POR and BOR, and covers the operation of the various start-up timers. Stack Reset events are covered in Section6.1.3.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section28.2 “Watchdog Timer (WDT)”. A simplified block diagram of the on-chip Reset circuit is shown in Figure5-1. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Configuration Word Mismatch Stack Stack Full/Underflow Reset Pointer External Reset MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset S PWRT Chip_Reset R Q LF-INTOSC 11-Bit Ripple Counter  2009-2018 Microchip Technology Inc. DS30009960F-page 69

PIC18F87K22 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit If BOREN<1:0> = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN<1:0> = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration Mismatch Reset occurs) bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS30009960F-page 70  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 5.2 Master Clear (MCLR) In Zero-Power BOR (ZPBORMV), the module monitors the VDD voltage and re-arms the POR at about 2V. The MCLR pin provides a method for triggering a hard ZPBORMV does not cause a Reset, but re-arms the external Reset of the device. A Reset is generated by POR. holding the pin low. PIC18 extended microcontroller The BOR accuracy varies with its power level. The lower devices have a noise filter in the MCLR Reset path the power setting, the less accurate the BOR trip levels which detects and ignores small pulses. are. Therefore, the high-power BOR has the highest The MCLR pin is not driven low by any internal Resets, accuracy and the low-power BOR has the lowest including the WDT. accuracy. The trip levels (BVDD, Parameter D005), cur- rent consumption (Section31.2 “DC Characteristics: 5.3 Power-on Reset (POR) Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended)”) and time required A Power-on Reset condition is generated on-chip below BVDD (TBOR, Parameter 35) can all be found in whenever VDD rises above a certain threshold. This Section31.0 “Electrical Characteristics”. allows the device to start in the initialized state when VDD is adequate for operation. FIGURE 5-2: EXTERNAL POWER-ON To take advantage of the POR circuitry, tie the MCLR RESET CIRCUIT (FOR pin through a resistor (1k to 10k) to VDD. This will SLOW VDD POWER-UP) eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (Parameter D004). For a slow rise VDD VDD time, see Figure5-2. D R When the device starts normal operation (exiting the R1 Reset condition), device operating parameters (such MCLR as voltage, frequency and temperature) must be met to PIC18F87K22 ensure operation. If these conditions are not met, the C device must be held in Reset until the operating conditions are met. Note 1: External Power-on Reset circuit is required Power-on Reset events are captured by the POR bit only if the VDD power-up slope is too slow. (RCON<1>). The state of the bit is set to ‘0’ whenever The diode, D, helps discharge the capacitor a Power-on Reset occurs and does not change for any quickly when VDD powers down. other Reset event. POR is not reset to ‘1’ by any 2: R < 40k is recommended to make sure that hardware event. To capture multiple events, the user the voltage drop across R does not violate manually resets the bit to ‘1’ in software following any the device’s electrical specification. Power-on Reset. 3: R1  1 k will limit any current flowing into MCLR from external capacitor, C, in the event 5.4 Brown-out Reset (BOR) of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical The PIC18F87K22 family has four BOR Power modes: Overstress (EOS). • High-Power BOR 5.4.1 DETECTING BOR • Medium Power BOR • Low-Power BOR The BOR bit always resets to ‘0’ on any Brown-out • Zero-Power BOR Reset or Power-on Reset event. This makes it difficult to determine if a Brown-out Reset event has occurred Each power Mode is selected by the BORPWR<1:0> just by reading the state of BOR alone. A more reliable bits setting (CONFIG2L<6:5>). For low, medium and method is to simultaneously check the state of both high-power BOR, the module monitors the VDD depend- POR and BOR. This assumes that the POR bit is reset ing on the BORV<1:0> setting (CONFIG1L<3:2>). A to ‘1’ in software immediately after any Power-on Reset BOR event re-arms the Power-on Reset. It also causes event. If BOR is ‘0’ while POR is ‘1’, it can be reliably a Reset, depending on which of the trip levels has been assumed that a Brown-out Reset event has occurred. set: 1.8V, 2V, 2.7V or 3V. LP-BOR cannot be detected with the BOR bit in the BOR is enabled by the BOREN<1:0> bits (CON- RCON register. LP-BOR can rearm the POR and can FIG2L<2:1>) and the SBOREN bit (RCON<6>). Typical cause a Power-on Reset. power consumption is listed as ParameterD022A in Section31.0 “Electrical Characteristics”.  2009-2018 Microchip Technology Inc. DS30009960F-page 71

PIC18F87K22 FAMILY 5.5 Configuration Mismatch (CM) 5.6 Power-up Timer (PWRT) The Configuration Mismatch (CM) Reset is designed to PIC18F87K22 family devices incorporate an on-chip detect, and attempt to recover from, random, memory Power-up Timer (PWRT) to help regulate the Power-on corrupting events. These include Electrostatic Discharge Reset process. The PWRT is enabled by setting the (ESD) events that can cause widespread, single bit PWRTEN bit (CONFIG2L<0>). The main function is to changes throughout the device and result in catastrophic ensure that the device voltage is stable before code is failure. executed. In PIC18F87K22 family Flash devices, the device The Power-up Timer (PWRT) of the PIC18F87K22 Configuration registers (located in the configuration family devices is a 11-bit counter that uses the memory space) are continuously monitored during LF-INTOSC source as the clock input. operation by comparing their values to complimentary While the PWRT is counting, the device is held in shadow registers. If a mismatch is detected between Reset. the two sets of registers, a CM Reset automatically occurs. These events are captured by the CM bit The power-up time delay depends on the LF-INTOSC (RCON<5>). The state of the bit is set to ‘0’ whenever clock and will vary from chip-to-chip due to temperature a CM event occurs and does not change for any other and process variation. See DC Parameter33 for Reset event. details. A CM Reset behaves similarly to a Master Clear Reset, 5.6.1 TIME-OUT SEQUENCE RESET instruction, WDT time-out or Stack Event Reset. If enabled, the PWRT time-out is invoked after the POR As with all hard and power Reset events, the device pulse has cleared. The total time-out will vary based on Configuration Words are reloaded from the Flash the status of the PWRT. Figure5-3, Figure5-4, Configuration Words in program memory as the device Figure5-5 and Figure5-6 all depict time-out restarts. sequences on power-up with the Power-up Timer enabled. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the PWRT will expire. Bringing MCLR high will begin execution immediately (Figure5-5). This is useful for testing purposes or for synchronizing more than one PIC18 device operating in parallel. FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET DS30009960F-page 72  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET  2009-2018 Microchip Technology Inc. DS30009960F-page 73

PIC18F87K22 FAMILY 5.7 Reset State of Registers different Reset situations, as indicated in Table5-1. These bits are used in software to determine the nature Most registers are unaffected by a Reset. Their status of the Reset. is unknown on POR and unchanged by all other Table5-2 describes the Reset states for all of the Resets. The other registers are forced to a “Reset Special Function Registers. These are categorized by state” depending on the type of Reset that occurred. Power-on and Brown-out Resets, Master Clear and Most registers are not affected by a WDT wake-up, WDT Resets, and WDT wake-ups. since this is viewed as the resumption of normal operation. Status bits from the RCON register (CM, RI, TO, PD, POR and BOR) are set or cleared differently in TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter(1) CM RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET instruction 0000h u 0 u u u u u u Brown-out Reset 0000h 1 1 1 1 u 0 u u Configuration Mismatch Reset 0000h 0 u u u u u u u MCLR Reset during 0000h u u 1 u u u u u power-managed Run modes MCLR Reset during power- 0000h u u 1 0 u u u u managed Idle modes and Sleep mode MCLR Reset during full-power 0000h u u u u u u u u execution Stack Full Reset (STVREN = 1) 0000h u u u u u u 1 u Stack Underflow Reset 0000h u u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u u u u u u u 1 actual Reset, STVREN = 0) WDT time-out during full-power 0000h u u 0 u u u u u or power-managed Run modes WDT time-out during PC + 2 u u 0 0 u u u u power-managed Idle or Sleep modes Interrupt exit from PC + 2 u u u 0 u u u u power-managed modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). DS30009960F-page 74  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets TOSU PIC18F6XK22 PIC18F8XK22 ---0 0000 ---0 0000 ---0 uuuu(1) TOSH PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu(1) TOSL PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu(1) STKPTR PIC18F6XK22 PIC18F8XK22 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU PIC18F6XK22 PIC18F8XK22 ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu PCL PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F6XK22 PIC18F8XK22 --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F6XK22 PIC18F8XK22 0000 000x 0000 000u uuuu uuuu(3) INTCON2 PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu(3) INTCON3 PIC18F6XK22 PIC18F8XK22 1100 0000 1100 0000 uuuu uuuu(3) INDF0 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A POSTINC0 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A POSTDEC0 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A PREINC0 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A PLUSW0 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A FSR0H PIC18F6XK22 PIC18F8XK22 ---- 0000 ---- 0000 ---- uuuu FSR0L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A POSTINC1 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A POSTDEC1 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A PREINC1 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A PLUSW1 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A FSR1H PIC18F6XK22 PIC18F8XK22 ---- 0000 ---- 0000 ---- uuuu FSR1L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F6XK22 PIC18F8XK22 ---- 0000 ---- 0000 ---- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt, and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition.  2009-2018 Microchip Technology Inc. DS30009960F-page 75

PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets INDF2 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A POSTINC2 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A POSTDEC2 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A PREINC2 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A PLUSW2 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A FSR2H PIC18F6XK22 PIC18F8XK22 ---- xxxx ----uuuu ---- uuuu FSR2L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F6XK22 PIC18F8XK22 ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F6XK22 PIC18F8XK22 0000 0000 uuuu uuuu uuuu uuuu TMR0L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu SPBRGH1 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu OSCCON PIC18F6XK22 PIC18F8XK22 0110 q000 0110 q000 uuuu quuu IPR5 PIC18F65K22 PIC18F85K22 ---1 -111 ---1 -111 ---u -uuu PIC18F66K22 PIC18F86K22 IPR5 1000 0000 1000 0000 uuuu uuuu PIC18F67K22 PIC18F87K22 WDTCON PIC18F6XK22 PIC18F8XK22 0-x0 -000 0-x0 -000 u-uu -uuu RCON PIC18F6XK22 PIC18F8XK22 0111 11qq 0uqq qquu uuuu qquu TMR1H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F6XK22 PIC18F8XK22 0000 0000 uuuu uuuu uuuu uuuu TMR2 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu T2CON PIC18F6XK22 PIC18F8XK22 -000 0000 -000 0000 -uuu uuuu SSP1BUF PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu SSP1ADD PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu SSP1STAT PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu SSP1CON1 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu SSP1CON2 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu ADRESH PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F6XK22 PIC18F8XK22 -000 0000 -000 0000 -uuu uuuu ADCON1 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu ADCON2 PIC18F6XK22 PIC18F8XK22 0-00 0000 0-00 0000 u-uu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt, and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. DS30009960F-page 76  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets ECCP1AS PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu ECCP1DEL PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu CCPR1H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu PIR5 PIC18F65K22 PIC18F85K22 ---0 -000 ---0 -000 ---u -uuu PIC18F66K22 PIC18F86K22 PIR5 0000 0000 0000 0000 uuuu uuuu PIC18F67K22 PIC18F87K22 PIE5 PIC18F65K22 PIC18F85K22 ---0 0000 ---0 0000 ---u uuuu(1) PIC18F66K22 PIC18F86K22 PIE5 0000 000 0000 0000 uuuu uuuu(1) PIC18F67K22 PIC18F87K22 IPR4 PIC18F65K22 PIC18F85K22 --11 1111 --11 1111 --uu uuuu PIC18F66K22 PIC18F86K22 IPR4 1111 1111 1111 1111 uuuu uuuu PIC18F67K22 PIC18F87K22 PIR4 PIC18F65K22 PIC18F85K22 --00 0000 --00 0000 --uu uuuu(1) PIC18F66K22 PIC18F86K22 PIR4 0000 0000 0000 0000 uuuu uuuu(1) PIC18F67K22 PIC18F87K22 PIE4 PIC18F65K22 PIC18F85K22 --00 0000 --00 0000 --uu uuuu PIC18F66K22 PIC18F86K22 PIE4 0000 0000 0000 0000 uuuu uuuu PIC18F67K22 PIC18F87K22 CVRCON PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu CMSTAT PIC18F6XK22 PIC18F8XK22 xxx- ---- xxx- ---- uuu- ---- TMR3H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0x00 uuuu uuuu T3GCON PIC18F6XK22 PIC18F8XK22 0000 0x00 0000 0000 uuuu uuuu SPBRG1 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu RCREG1 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu TXREG1 PIC18F6XK22 PIC18F8XK22 xxxx xxxx xxxx xxxx uuuu uuuu TXSTA1 PIC18F6XK22 PIC18F8XK22 0000 0010 0000 0010 uuuu uuuu RCSTA1 PIC18F6XK22 PIC18F8XK22 0000 000x 0000 000x uuuu uuuu T1GCON PIC18F6XK22 PIC18F8XK22 0000 0x00 0000 0x00 uuuu -uuu IPR6 PIC18F6XK22 PIC18F8XK22 ---1 -111 ---1 -111 ---u -uuu HLVDCON PIC18F6XK22 PIC18F8XK22 0000 0101 0000 0101 uuuu uuuu PSPCON PIC18F6XK22 PIC18F8XK22 0000 ---- 0000 ---- uuuu ---- PIR6 PIC18F6XK22 PIC18F8XK22 ---0 -000 ---0 -000 ---u -uuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt, and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition.  2009-2018 Microchip Technology Inc. DS30009960F-page 77

PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets IPR3 PIC18F6XK22 PIC18F8XK22 1-11 1111 1-11 1111 u-uu uuuu PIR3 PIC18F6XK22 PIC18F8XK22 0-00 0000 0-00 0000 u-uu uuuu PIE3 PIC18F6XK22 PIC18F8XK22 0-00 0000 0-00 0000 u-uu uuuu IPR2 PIC18F6XK22 PIC18F8XK22 1-11 1111 1-11 1111 u-uu uuuu PIR2 PIC18F6XK22 PIC18F8XK22 0-10 0000 0-10 0000 u-uu uuuu PIE2 PIC18F6XK22 PIC18F8XK22 0-00 0000 0-00 0000 u-uu uuuu IPR1 PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu PIR1 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu PIE1 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu PSTR1CON PIC18F6XK22 PIC18F8XK22 00-0 0001 00-0 0001 uu-u uuuu OSCTUNE PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu TRISJ PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu TRISH PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu TRISG PIC18F6XK22 PIC18F8XK22 ---1 1111 ---1 1111 ---u uuuu TRISF PIC18F6XK22 PIC18F8XK22 1111 111- 1111 111- ---u uuuu TRISE PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu TRISD PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu TRISA PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu LATJ PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu LATH PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu LATG PIC18F6XK22 PIC18F8XK22 ---x xxxx ---u uuuu ---u uuuu LATF PIC18F6XK22 PIC18F8XK22 xxxx xxx- uuuu uuu- uuuu uuu- LATE PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu LATD PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu LATC PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu LATA PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu PORTJ PIC18F6XK22 PIC18F8XK22 xxxx xxxx xxxx xxxx uuuu uuuu PORTH PIC18F6XK22 PIC18F8XK22 xxxx xxxx xxxx xxxx uuuu uuuu PORTG PIC18F6XK22 PIC18F8XK22 --xx xxxx --xx xxxx --uu uuuu PORTF PIC18F6XK22 PIC18F8XK22 xxxx xxx- xxxx xxx- uuuu uuu- PORTE PIC18F6XK22 PIC18F8XK22 xxxx xxxx xxxx xxxx uuuu uuuu PORTD PIC18F6XK22 PIC18F8XK22 xxxx xxxx xxxx xxxx uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt, and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. DS30009960F-page 78  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets PORTC PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu PORTA PIC18F6XK22 PIC18F8XK22 xx0x 0000 uu0u 0000 uuuu uuuu EECON1 PIC18F6XK22 PIC18F8XK22 xx-0 x000 uu-0 u000 uu-u uuuu EECON2 PIC18F6XK22 PIC18F8XK22 ---- ---- ---- ---- ---- ---- TMR5H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu TMR5L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu T5CON PIC18F6XK22 PIC18F8XK22 0000 0000 uuuu uuuu uuuu uuuu T5GCON PIC18F6XK22 PIC18F8XK22 0000 0x00 uuuu uuuu uuuu uuuu CCPR4H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR4L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCP4CON PIC18F6XK22 PIC18F8XK22 --00 0000 --00 0000 --uu uuuu CCPR5H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR5L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCP5CON PIC18F6XK22 PIC18F8XK22 --00 0000 --00 0000 --uu uuuu CCPR6H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR6L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCP6CON PIC18F6XK22 PIC18F8XK22 --00 0000 --00 0000 --uu uuuu CCPR7H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR7L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCP7CON PIC18F6XK22 PIC18F8XK22 --00 0000 --00 0000 --uu uuuu TMR4 PIC18F6XK22 PIC18F8XK22 xxxx xxxx xxxx xxxx uuuu uuuu PR4 PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 1111 1111 T4CON PIC18F6XK22 PIC18F8XK22 -111 1111 -111 1111 -uuu uuuu SSP2BUF PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu SSP2ADD PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu SSP2STAT PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu SSP2CON1 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu SSP2CON2 PIC18F6XK22 PIC18F8XK22 0100 0000 0000 0000 uuuu uuuu BAUDCON1 PIC18F6XK22 PIC18F8XK22 0100 0-00 0100 0-00 uuuu u-uu OSCCON2 PIC18F6XK22 PIC18F8XK22 -0-- 0-x0 -0-- 0-u0 -u-- u-uu EEADRH PIC18F6XK22 PIC18F8XK22 ---- --00 ---- --00 ---- --uu EEADR PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu EEDATA PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu PIE6 PIC18F6XK22 PIC18F8XK22 ---0 -000 ---0 -000 ---u -uuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt, and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition.  2009-2018 Microchip Technology Inc. DS30009960F-page 79

PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets RTCCFG PIC18F6XK22 PIC18F8XK22 0-00 0000 u-uu uuuu u-uu uuuu RTCCAL PIC18F6XK22 PIC18F8XK22 0000 0000 uuuu uuuu uuuu uuuu RTCVALH PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu RTCVALL PIC18F6XK22 PIC18F8XK22 0000 0000 uuuu uuuu uuuu uuuu ALRMCFG PIC18F6XK22 PIC18F8XK22 0000 0000 uuuu uuuu uuuu uuuu ALRMRPT PIC18F6XK22 PIC18F8XK22 0000 0000 uuuu uuuu uuuu uuuu ALRMVALH PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu ALRMVALL PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CTMUCONH PIC18F6XK22 PIC18F8XK22 0-00 0000 0-00 0000 u-uu uuuu CTMUCONL PIC18F6XK22 PIC18F8XK22 0000 00xx 0000 00xx uuuu uuuu CTMUICONH PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu CM1CON PIC18F6XK22 PIC18F8XK22 0001 1111 0001 1111 uuuu uuuu PADCFG1 PIC18F6XK22 PIC18F8XK22 00-- -00- uu-- -uu- uu-- -uu- PADCFG1 PIC18F6XK22 PIC18F8XK22 000- -00- uuu- -uu- uuu- -uu- ECCP2AS PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu ECCP2DEL PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu ECCP3AS PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu ECCP3DEL PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu CCPR3H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR3L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCP3CON PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu CCPR8H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR8L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCP8CON PIC18F6XK22 PIC18F8XK22 --00 0000 --00 0000 --uu uuuu PIC18F66K22 PIC18F86K22 CCPR9H xxxx xxxx uuuu uuuu uuuu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 CCPR9L xxxx xxxx uuuu uuuu uuuu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 CCP9CON --00 0000 --00 0000 --uu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 CCPR10H xxxx xxxx uuuu uuuu uuuu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 CCPR10L xxxx xxxx uuuu uuuu uuuu uuuu PIC18F67K22 PIC18F87K22 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt, and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. DS30009960F-page 80  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets PIC18F66K22 PIC18F86K22 CCP10CON --00 0000 --00 0000 --uu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 TMR7H xxxx xxxx uuuu uuuu uuuu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 TMR7L xxxx xxxx uuuu uuuu uuuu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 T7CON 0000 0000 uuuu uuuu uuuu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 T7GCON 0000 0x00 0000 0x00 uuuu uuuu PIC18F67K22 PIC18F87K22 TMR6 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu PR6 PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu T6CON PIC18F6XK22 PIC18F8XK22 -000 0000 -000 0000 -uuu uuuu TMR8 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu PR8 PIC18F6XK22 PIC18F8XK22 1111 1111 1111 1111 uuuu uuuu T8CON PIC18F6XK22 PIC18F8XK22 -000 0000 -000 0000 -uuu uuuu PIC18F66K22 PIC18F86K22 TMR10 0000 0000 0000 0000 uuuu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 PR10 1111 1111 1111 1111 uuuu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 T10CON -000 0000 -000 0000 -uuu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 TMR12 0000 0000 0000 0000 uuuu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 PR12 1111 1111 1111 1111 uuuu uuuu PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 T12CON -000 0000 -000 0000 -uuu uuuu PIC18F67K22 PIC18F87K22 CM2CON PIC18F6XK22 PIC18F8XK22 0001 1111 0001 1111 uuuu uuuu CM3CON PIC18F6XK22 PIC18F8XK22 0001 1111 0001 1111 uuuu uuuu CCPTMRS0 PIC18F6XK22 PIC18F8XK22 0000 0000 uuuu uuuu uuuu uuuu CCPTMRS1 PIC18F6XK22 PIC18F8XK22 00-0 -000 uu-u -uuu uu-u -uuu PIC18F66K22 PIC18F86K22 CCPTMRS2 ---0 -000 ---u -uuu ---u -uuu PIC18F67K22 PIC18F87K22 CCPTMRS2 PIC18F65K22 PIC18F85K22 ---- --00 ---- --uu ---- --uu REFOCON PIC18F6XK22 PIC18F8XK22 0-00 0000 u-uu uuuu u-uu uuuu ODCON1 PIC18F6XK22 PIC18F8XK22 000- ---0 uuu- ---u uuu- ---u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt, and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition.  2009-2018 Microchip Technology Inc. DS30009960F-page 81

PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets PIC18F66K22 PIC18F86K22 ODCON2 0000 0000 uuuu uuuu uuuu uuuu PIC18F67K22 PIC18F87K22 ODCON2 PIC18F65K22 PIC18F85K22 --00 0000 --uu uuuu --uu uuuu ODCON3 PIC18F6XK22 PIC18F8XK22 00-- ---0 uu-- ---u uu-- ---u MEMCON PIC18F6XK22 PIC18F8XK22 0-00 --00 0-00 --00 u-uu --uu ANCON0 PIC18F6XK22 PIC18F8XK22 1111 1111 uuuu uuuu uuuu uuuu ANCON1 PIC18F6XK22 PIC18F8XK22 1111 1111 uuuu uuuu uuuu uuuu ANCON2 PIC18F6XK22 PIC18F8XK22 1111 1111 uuuu uuuu uuuu uuuu RCSTA2 PIC18F6XK22 PIC18F8XK22 0000 000x 0000 000x uuuu uuuu TXSTA2 PIC18F6XK22 PIC18F8XK22 0000 0010 0000 0010 uuuu uuuu BAUDCON2 PIC18F6XK22 PIC18F8XK22 0100 0-00 0100 0-00 uuuu u-uu SPBRGH2 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu SPBRG2 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu RCREG2 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu TXREG2 PIC18F6XK22 PIC18F8XK22 xxxx xxxx xxxx xxxx uuuu uuuu PSTR2CON PIC18F6XK22 PIC18F8XK22 00-0 0001 00-0 0001 uu-u uuuu PSTR3CON PIC18F6XK22 PIC18F8XK22 00-0 0001 00-0 0001 uu-u uuuu PMD0 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu PMD1 PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu PIC18F66K22 PIC18F86K22 PMD2 0000 0000 0000 0000 uuuu uuuu PIC18F67K22 PIC18F87K22 PMD2 PIC18F65K22 PIC18F85K22 -0-0 0000 -0-0 0000 -u-u uuuu PIC18F66K22 PIC18F86K22 PMD3 0000 0000 0000 0000 uuuu uuuu PIC18F67K22 PIC18F87K22 PMD3 PIC18F65K22 PIC18F85K22 --00 000- --00 000- --uu uuu- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt, and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. DS30009960F-page 82  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 6.0 MEMORY ORGANIZATION The data EEPROM, for practical purposes, can be regarded as a peripheral device because it is PIC18F87K22 family devices have these types of addressed and accessed through a set of control memory: registers. • Program Memory Additional detailed information on the operation of the • Data RAM Flash program memory is provided in Section7.0 • Data EEPROM “Flash Program Memory”. The data EEPROM is As Harvard architecture devices, the data and program discussed separately in Section9.0 “Data EEPROM memories use separate buses. This enables Memory”. concurrent access of the two memory spaces. FIGURE 6-1: MEMORY MAPS FOR PIC18F87K22 FAMILY DEVICES PC<20:0> 21 CALL, CALLW, RCALL, RETURN, RETFIE, RETLW, ADDULNK, SUBULNK Stack Level 1    Stack Level 31 PIC18FX5K22 PIC18FX6K22 PIC18FX7K22 000000h On-Chip On-Chip On-Chip Memory Memory Memory 007FFFh 00FFFFh e c a p S y or m e 01FFFFh M er s U Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ 1FFFFFh Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.  2009-2018 Microchip Technology Inc. DS30009960F-page 83

PIC18F87K22 FAMILY 6.1 Program Memory Organization FIGURE 6-2: HARD VECTOR FOR PIC18F87K22 FAMILY PIC18 microcontrollers implement a 21-bit Program DEVICES Counter that is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented Reset Vector 0000h memory and the 2-Mbyte address will return all ‘0’s (a High-Priority Interrupt Vector 0008h NOP instruction). The entire PIC18F87K22 family offers a range of Low-Priority Interrupt Vector 0018h on-chip Flash program memory sizes, from 32 Kbytes (up to 16,384 single-word instructions) to 128Kbytes (65,536 single-word instructions). • PIC18F65K22 and PIC18F85K22 – 32Kbytes of On-Chip Flash memory, storing up to 16,384 single-word Program Memory instructions • PIC18F66K22 and PIC18F86K22 – 64Kbytes of Flash memory, storing up to 32,768 single-word instructions • PIC18F67K22 and PIC18F87K22 – 128Kbytes of Flash memory, storing up to 65,536 single-word instructions The program memory maps for individual family members are shown in Figure6-1. 6.1.1 HARD MEMORY VECTORS Read ‘0’ All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the Program Counter returns on all device Resets; it is located at 0000h. 1FFFFFh PIC18 devices also have two interrupt vector Legend: (Top of Memory) represents upper boundary addresses for handling high-priority and low-priority of on-chip program memory space (see interrupts. The high-priority interrupt vector is located at Figure6-1 for device-specific values). 0008h and the low-priority interrupt vector is at 0018h. Shaded area represents unimplemented The locations of these vectors are shown, in relation to memory. Areas are not shown to scale. the program memory map, in Figure6-2. DS30009960F-page 84  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 6.1.2 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and contained in three separate 8-bit registers. the stack is readable and writable through the The low byte, known as the PCL register, is both Top-of-Stack Special Function Registers. Data can also readable and writable. The high byte, or PCH register, be pushed to, or popped from, the stack using these contains the PC<15:8> bits and is not directly readable registers. or writable. Updates to the PCH register are performed A CALL type instruction causes a push onto the stack. through the PCLATH register. The upper byte is called The Stack Pointer is first incremented and the location PCU. This register contains the PC<20:16> bits; it is pointed to by the Stack Pointer is written with the also not directly readable or writable. Updates to the contents of the PC (already pointing to the instruction PCU register are performed through the PCLATU following the CALL). A RETURN type instruction causes register. a pop from the stack. The contents of the location The contents of PCLATH and PCLATU are transferred pointed to by the STKPTR are transferred to the PC to the Program Counter by any operation that writes and then the Stack Pointer is decremented. PCL. Similarly, the upper two bytes of the Program The Stack Pointer is initialized to ‘00000’ after all Counter are transferred to PCLATH and PCLATU by an Resets. There is no RAM associated with the location operation that reads PCL. This is useful for computed corresponding to a Stack Pointer value of ‘00000’; this offsets to the PC (see Section6.1.5.1 “Computed is only a Reset value. Status bits indicate if the stack is GOTO”). full, has overflowed or has underflowed. The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word 6.1.3.1 Top-of-Stack Access instructions, the Least Significant bit of PCL is fixed to Only the top of the return address stack (TOS) is a value of ‘0’. The PC increments by two to address readable and writable. A set of three registers, sequential instructions in the program memory. TOSU:TOSH:TOSL, holds the contents of the stack The CALL, RCALL, GOTO and program branch location pointed to by the STKPTR register instructions write to the Program Counter directly. For (Figure6-3). This allows users to implement a software these instructions, the contents of PCLATH and stack, if necessary. After a CALL, RCALL or interrupt (or PCLATU are not transferred to the Program Counter. ADDULNK and SUBULNK instructions, if the extended instruction set is enabled), the software can read the 6.1.3 RETURN ADDRESS STACK pushed value by reading the TOSU:TOSH:TOSL regis- The return address stack enables execution of any ters. These values can be placed on a user-defined combination of up to 31 program calls and interrupts. software stack. At return time, the software can return The PC is pushed onto the stack when a CALL or these values to TOSU:TOSH:TOSL and do a return. RCALL instruction is executed or an interrupt is While accessing the stack, users must disable the Acknowledged. The PC value is pulled off the stack on Global Interrupt Enable bits to prevent inadvertent a RETURN, RETLW or a RETFIE instruction. The value stack corruption. also is pulled off the stack on ADDULNK and SUBULNK instructions, if the extended instruction set is enabled. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 6-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> Top-of-Stack Registers Stack Pointer 11111 TOSU TOSH TOSL 11110 STKPTR<4:0> 00h 1Ah 34h 11101 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000  2009-2018 Microchip Technology Inc. DS30009960F-page 85

PIC18F87K22 FAMILY 6.1.3.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The STKPTR register (Register6-1) contains the Stack to the PC and set the STKUNF bit while the Stack Pointer value, the STKFUL (Stack Full) status bit and Pointer remains at zero. The STKUNF bit will remain the STKUNF (Stack Underflow) status bits. The value set until cleared by software or until a POR occurs. of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System (RTOS) for return stack maintenance. not the same as a Reset as the contents of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is 6.1.3.3 PUSH and POP Instructions set. The STKFUL bit is cleared by software or by a POR. Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values What happens when the stack becomes full depends off of the stack, without disturbing normal program exe- on the state of the STVREN (Stack Overflow Reset cution, is a desirable feature. The PIC18 instruction set Enable) Configuration bit. (For a description of the includes two instructions, PUSH and POP, that permit device Configuration bits, see Section28.1 “Configu- the TOS to be manipulated under software control. ration Bits”.) If STVREN is set (default), the 31st push TOSU, TOSH and TOSL can be modified to place data will push the (PC + 2) value onto the stack, set the or a return address on the stack. STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push The POP instruction discards the current TOS by and the STKPTR will remain at 31. decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. REGISTER 6-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack has become full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow has occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. DS30009960F-page 86  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 6.1.3.4 Stack Full and Underflow Resets 6.1.5 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit There may be programming situations that require the (CONFIG4L<0>). When STVREN is set, a full or under- creation of data structures, or look-up tables, in flow condition will set the appropriate STKFUL or program memory. For PIC18 devices, look-up tables STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit, but not cause • Table Reads a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 6.1.5.1 Computed GOTO 6.1.4 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the Program Counter. An example is shown in A Fast Register Stack is provided for the STATUS, Example6-2. WREG and BSR registers to provide a “fast return” option for interrupts. This stack is only one level deep A look-up table can be formed with an ADDWF PCL and is neither readable nor writable. It is loaded with the instruction and a group of RETLW nn instructions. The current value of the corresponding register when the W register is loaded with an offset into the table before processor vectors for an interrupt. All interrupt sources executing a call to that table. The first instruction of the will push values into the Stack registers. The values in called routine is the ADDWF PCL instruction. The next the registers are then loaded back into the working instruction executed will be one of the RETLW nn registers if the RETFIE,FAST instruction is used to instructions that returns the value, ‘nn’, to the calling return from the interrupt. function. If both low and high-priority interrupts are enabled, the The offset value (in WREG) specifies the number of Stack registers cannot be used reliably to return from bytes that the Program Counter should advance and low-priority interrupts. If a high-priority interrupt occurs should be multiples of two (LSb = 0). while servicing a low-priority interrupt, the Stack In this method, only one data byte may be stored in register values stored by the low-priority interrupt will each instruction location and room on the return be overwritten. In these cases, users must save the key address stack is required. registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 6-2: COMPUTED GOTO USING Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE interrupts are used, the Fast Register Stack can be MOVF OFFSET, W used to restore the STATUS, WREG and BSR registers CALL TABLE at the end of a subroutine call. To use the Fast Register ORG nn00h Stack for a subroutine call, a CALL label,FAST TABLE ADDWF PCL instruction must be executed to save the STATUS, RETLW nnh WREG and BSR registers to the Fast Register Stack. A RETLW nnh RETURN,FAST instruction is then executed to restore RETLW nnh these registers from the Fast Register Stack. . . Example6-1 shows a source code example that uses . the Fast Register Stack during a subroutine call and return. 6.1.5.2 Table Reads EXAMPLE 6-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored, two bytes per ;STACK program word, while programming. The Table Pointer  (TBLPTR) specifies the byte address and the Table  Latch (TABLAT) contains the data that is read from the program memory. Data is transferred from program SUB1  memory, one byte at a time.  RETURN FAST ;RESTORE VALUES SAVED The table read operation is discussed further in ;IN FAST REGISTER STACK Section7.1 “Table Reads and Table Writes”.  2009-2018 Microchip Technology Inc. DS30009960F-page 87

PIC18F87K22 FAMILY 6.2 PIC18 Instruction Cycle 6.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles, Q1 6.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are pipe- The microcontroller clock input, whether from an lined in such a manner that a fetch takes one instruction internal or external source, is internally divided by four cycle, while the decode and execute take another to generate four non-overlapping, quadrature clocks instruction cycle. However, due to the pipelining, each (Q1, Q2, Q3 and Q4). Internally, the Program Counter instruction effectively executes in one cycle. If an is incremented on every Q1, with the instruction instruction (such as GOTO) causes the Program fetched from the program memory and latched into the Counter to change, two cycles are required to complete Instruction Register (IR) during Q4. the instruction. (See Example6-3.) The instruction is decoded and executed during the A fetch cycle begins with the Program Counter (PC) following Q1 through Q4. The clocks and instruction incrementing in Q1. execution flow are shown in Figure6-4. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS30009960F-page 88  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruc- tion. Since instructions are always stored on word The program memory is addressed in bytes. Instruc- boundaries, the data contained in the instruction is a tions are stored as two or four bytes in program word address. The word address is written to PC<20:1> memory. The Least Significant Byte of an instruction which accesses the desired byte address in program word is always stored in a program memory location memory. Instruction #2 in Figure6-5 shows how the with an even address (LSB = 0). To maintain alignment instruction, GOTO 0006h, is encoded in the program with instruction boundaries, the PC increments in steps memory. Program branch instructions, which encode a of two and the LSB will always read ‘0’ (see relative address offset, operate in the same manner. The Section6.1.2 “Program Counter”). offset value stored in a branch instruction represents the Figure6-5 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. For more details on the instruction set, see Section29.0 “Instruction Set Summary”. FIGURE 6-5: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0  Program Memory 000000h Byte Locations  000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 6.2.4 TWO-WORD INSTRUCTIONS used by the instruction sequence. If the first word is skipped, for some reason, and the second word is The standard PIC18 instruction set has four, two-word executed by itself, a NOP is executed instead. This is instructions: CALL, MOVFF, GOTO and LSFR. In all necessary for cases when the two-word instruction is cases, the second word of the instructions always has preceded by a conditional instruction that changes the ‘1111’ as its four Most Significant bits. The other 12 bits PC. Example6-4 shows how this works. are literal data, usually a data memory address. Note: For information on two-word instructions The use of ‘1111’ in the 4MSbs of an instruction in the extended instruction set, see specifies a special form of NOP. If the instruction is Section6.5 “Program Memory and the executed in proper sequence, immediately after the Extended Instruction Set”. first word, the data in the second word is accessed and EXAMPLE 6-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code  2009-2018 Microchip Technology Inc. DS30009960F-page 89

PIC18F87K22 FAMILY 6.3 Data Memory Organization 6.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make it possible for rapid access memory are changed when the PIC18 to any address. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section6.6 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit, 12-bit address, allowing up to 4,096bytes of data low-order address and a 4-bit Bank Pointer. memory. The memory space is divided into as many as Most instructions in the PIC18 instruction set make use 16 banks that contain 256bytes each. PIC18FX6K22 of the Bank Pointer, known as the Bank Select Register and PIC18FX7K22 devices implement all 16 complete (BSR). This SFR holds the four Most Significant bits of banks, for a total of 4Kbytes. PIC18FX5K22 devices a location’s address. The instruction itself includes the implement only the first eight complete banks, for a eight Least Significant bits. Only the four lower bits of total of 2Kbytes. the BSR are implemented (BSR<3:0>). The upper four Figure6-6 and Figure6-7 show the data memory bits are unused, always read as ‘0’ and cannot be organization for the devices. written to. The BSR can be loaded directly by using the MOVLB instruction. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The The value of the BSR indicates the bank in data SFRs are used for control and status of the controller memory. The eight bits in the instruction show the loca- and peripheral functions, while GPRs are used for data tion in the bank and can be thought of as an offset from storage and scratchpad operations in the user’s the bank’s lower boundary. The relationship between application. Any read of an unimplemented location will the BSR’s value and the bank division in data memory read as ‘0’s. is shown in Figure6-7. The instruction set and architecture allow operations Since up to 16 registers may share the same low-order across all banks. The entire data memory may be address, the user must always be careful to ensure that accessed by Direct, Indirect or Indexed Addressing the proper bank is selected before performing a data modes. Addressing modes are discussed later in this read or write. For example, writing what should be section. program data to an eight-bit address of F9h, while the BSR is 0Fh, will end up resetting the Program Counter. To ensure that commonly used registers (select SFRs and select GPRs) can be accessed in a single cycle, While any bank can be selected, only those banks that PIC18 devices implement an Access Bank. This is a are actually implemented can be read or written to. 256-byte memory space that provides fast access to Writes to unimplemented banks are ignored, while select SFRs and the lower portion of GPR Bank 0 with- reads from unimplemented banks will return ‘0’s. Even out using the Bank Select Register. For details on the so, the STATUS register will still be affected as if the Access RAM, see Section6.3.2 “Access Bank”. operation was successful. The data memory map in Figure6-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. When this instruction executes, it ignores the BSR completely. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. DS30009960F-page 90  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 6-6: DATA MEMORY MAP FOR PIC18FX5K22 AND PIC18FX7K22 DEVICES BSR<3:0> Data Memory Map 00h 000h Access RAM = 0000 05Fh When a = 0: Bank 0 060h GPR The BSR is ignored and the FFh 0FFh Access Bank is used. 00h 100h = 0001 Bank 1 GPR The first 96 bytes are general purpose RAM (from Bank 0). FFh 1FFh 00h 200h The second 160 bytes are = 0010 Special Function Registers Bank 2 GPR (from Bank 15). FFh 2FFh 00h 300h = 0011 Bank 3 GPR When a = 1: FFh 3FFh The BSR specifies the bank 00h 400h used by the instruction. = 0100 Bank 4 GPR FFh 4FFh 00h 500h = 0101 Bank 5 GPR FFh 5FFh 00h 600h = 0110 Bank 6 GPR FFh 6FFh = 0111 00h 700h Access Bank Bank 7 GPR 00h FFh 7FFh Access RAM Low 00h 800h 5Fh = 1000 Bank 8 GPR(2) Access RAM High 60h (SFRs) FFh 8FFh FFh = 1001 00h 900h Bank 9 GPR(2) FFh 9FFh = 1010 00h A00h Bank 10 GPR(2) FFh AFFh = 1011 00h B00h Bank 11 GPR(2) FFh BFFh = 1100 00h C00h Bank 12 GPR(2) FFh CFFh 00h D00h = 1101 Bank 13 GPR(2) FFh DFFh 00h E00h = 1110 Bank 14 GPR(2) FFh EFFh = 1111 00h GPR(1,2) F00h F5Fh Bank 15 SFR F60h FFh FFFh Note 1: Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. Users must always use the complete address, or load the proper BSR value, to access these registers. 2: These addresses are unused for devices with 32 Kbytes of program memory (PIC18FX5K22). For those devices, read these addresses at 00h.  2009-2018 Microchip Technology Inc. DS30009960F-page 91

PIC18F87K22 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 7 BSR(1) 0 000h Data Memory 00h 7 From Opcode(2) 0 Bank 0 0 0 0 0 0 0 1 0 11 11 11 11 11 11 11 11 FFh 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 6.3.2 ACCESS BANK however, the instruction is forced to use the Access Bank address map. In that case, the current value of While the use of the BSR, with an embedded 8-bit the BSR is ignored entirely. address, allows users to address the entire range of data memory, it also means that the user must ensure that the Using this “forced” addressing allows the instruction to correct bank is selected. If not, data may be read from, operate on a data address in a single cycle without or written to, the wrong location. This can be disastrous updating the BSR first. For 8-bit addresses of 60h and if a GPR is the intended target of an operation, but an above, this means that users can evaluate and operate SFR is written to instead. Verifying and/or changing the on SFRs more efficiently. The Access RAM below 60h BSR for each read or write to data memory can become is a good place for data values that the user might need very inefficient. to access rapidly, such as immediate computational results or common program variables. To streamline access for the most commonly used data memory locations, the data memory is configured with Access RAM also allows for faster and more code an Access Bank, which allows users to access a efficient context saving and switching of variables. mapped block of memory without specifying a BSR. The mapping of the Access Bank is slightly different The Access Bank consists of the first 96 bytes of when the extended instruction set is enabled (XINST memory (00h-5Fh) in Bank 0 and the last 160 bytes of Configuration bit = 1). This is discussed in more detail memory (60h-FFh) in Bank 15. The lower half is known in Section6.6.3 “Mapping the Access Bank in as the “Access RAM” and is composed of GPRs. The Indexed Literal Offset Mode”. upper half is where the device’s SFRs are mapped. These two areas are mapped contiguously in the 6.3.3 GENERAL PURPOSE Access Bank and can be addressed in a linear fashion REGISTER FILE by an eight-bit address (Figure6-6). PIC18 devices may have banked memory in the GPR The Access Bank is used by core PIC18 instructions area. This is data RAM which is available for use by all that include the Access RAM bit (the ‘a’ parameter in instructions. GPRs start at the bottom of Bank 0 the instruction). When ‘a’ is equal to ‘1’, the instruction (address 000h) and grow upwards towards the bottom of uses the BSR and the 8-bit address included in the the SFR area. GPRs are not initialized by a Power-on opcode for the data memory address. When ‘a’ is ‘0’, Reset and are unchanged on all other Resets. DS30009960F-page 92  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, The Special Function Registers (SFRs) are registers Resets and interrupts) and those related to the used by the CPU and peripheral modules for controlling peripheral functions. The Reset and Interrupt registers the desired operation of the device. These registers are are described in their respective chapters, while the implemented as static RAM. SFRs start at the top of ALU’s STATUS register is described later in this section. data memory (FFFh) and extend downward to occupy Registers related to the operation of the peripheral all of Bank 15 (F00h to FFFh) and the top part of features are described in the chapter for that peripheral. Bank14 (EF4h to EFFh). The SFRs are typically distributed among the A list of these registers is given in Table6-1 and peripherals whose functions they control. Unused SFR Table6-2. locations are unimplemented and read as ‘0’s. TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87K22 FAMILY Addr. Name Addr. Name Addr. Name Addr. Name Addr. Name Addr. Name(4) FFFh TOSU FDFh INDF2(1) FBFh ECCP1AS F9Fh IPR1 F7Fh EECON1 F5Fh RTCCFG FFEh TOSH FDEh POSTINC2(1) FBEh ECCP1DEL F9Eh PIR1 F7Eh EECON2 F5Eh RTCCAL FFDh TOSL FDDhPOSTDEC2(1) FBDh CCPR1H F9Dh PIE1 F7Dh TMR5H F5Dh RTCVALH FFCh STKPTR FDCh PREINC2(1) FBCh CCPR1L F9ChPSTR1CON F7Ch TMR5L F5Ch RTCVALL FFBh PCLATU FDBh PLUSW2(1) FBBh CCP1CON F9Bh OSCTUNE F7Bh T5CON F5Bh ALRMCFG FFAh PCLATH FDAh FSR2H FBAh PIR5 F9Ah TRISJ(2) F7Ah T5GCON F5Ah ALRMRPT FF9h PCL FD9h FSR2L FB9h PIE5 F99h TRISH(2) F79h CCPR4H F59h ALRMVALH FF8h TBLPTRU FD8h STATUS FB8h IPR4 F98h TRISG F78h CCPR4L F58h ALRMVALL FF7h TBLPTRH FD7h TMR0H FB7h PIR4 F97h TRISF F77h CCP4CON F57h CTMUCONH FF6h TBLPTRL FD6h TMR0L FB6h PIE4 F96h TRISE F76h CCPR5H F56h CTMUCONL FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD F75h CCPR5L F55h CTMUICONH FF4h PRODH FD4h SPBRGH1 FB4h CMSTAT F94h TRISC F74h CCP5CON F54h CM1CON FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h CCPR6H F53h PADCFG1 FF2h INTCON FD2h IPR5 FB2h TMR3L F92h TRISA F72h CCPR6L F52h ECCP2AS FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(2) F71h CCP6CON F51h ECCP2DEL FF0h INTCON3 FD0h RCON FB0h T3GCON F90h LATH(2) F70h CCPR7H F50h CCPR2H FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG F6Fh CCPR7L F4Fh CCPR2L FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF F6Eh CCP7CON F4Eh CCP2CON FEDhPOSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE F6Dh TMR4 F4Dh ECCP3AS FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD F6Ch PR4 F4Ch ECCP3DEL FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh T4CON F4Bh CCPR3H FEAh FSR0H FCAh T2CON FAAh T1GCON F8Ah LATB F6Ah SSP2BUF F4Ah CCPR3L FE9h FSR0L FC9h SSP1BUF FA9h IPR6 F89h LATA F69h SSP2ADD F49h CCP3CON FE8h WREG FC8h SSP1ADD FA8h HLVDCON F88h PORTJ(2) F68h SSP2STAT F48h CCPR8H FE7h INDF1(1) FC7h SSP1STAT FA7h PSPCON F87h PORTH(2) F67h SSP2CON1 F47h CCPR8L FE6h POSTINC1(1) FC6h SSP1CON1 FA6h PIR6 F86h PORTG F66h SSP2CON2 F46h CCP8CON FE5hPOSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h PORTF F65h BAUDCON1 F45h CCPR9H(3) FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h OSCCON2 F44h CCPR9L(3) FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h EEADRH F43h CCP9CON(3) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h EEADR F42h CCPR10H(3) FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h EEDATA F41h CCPR10L(3) FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h PIE6 F40h CCP10CON(3) Note 1: This is not a physical register. 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. 3: This register is not available on devices with a program memory of 32 Kbytes (PIC18FX5K22). 4: Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. To access these registers, users must always load the proper BSR value.  2009-2018 Microchip Technology Inc. DS30009960F-page 93

PIC18F87K22 FAMILY TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87K22 FAMILY (CONTINUED) Addr. Name Addr. Name Addr. Name Addr. Name Addr. Name Addr. Name(4) F3Fh TMR7H(3) F32h TMR12(3) F25h ANCON0 F18h PMD1 F3Eh TMR7L(3) F31h PR12(3) F24h ANCON1 F17h PMD2 F3Dh T7CON(3) F30h T12CON(3) F23h ANCON2 F16h PMD3 F3Ch T7GCON(3) F2Fh CM2CON F22h RCSTA2 F3Bh TMR6 F2Eh CM3CON F21h TXSTA2 F3Ah PR6 F2Dh CCPTMRS0 F20h BAUDCON2 F39H T6CON F2Ch CCPTMRS1 F1Fh SPBRGH2 F38h TMR8 F2Bh CCPTMRS2 F1Eh SPBRG2 F37h PR8 F2Ah REFOCON F1Dh RCREG2 F36h T8CON F29H ODCON1 F1Ch TXREG2 F35h TMR10(3) F28h ODCON2 F1Bh PSTR2CON F34h PR10(3) F27h ODCON3 F1Ah PSTR3CON F33h T10CON(3) F26h MEMCON(3) F19h PMD0 Note 1: This is not a physical register. 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. 3: This register is not available on devices with a program memory of 32 Kbytes (PIC18FX5K22). 4: Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. To access these registers, users must always load the proper BSR value. TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY Value on Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR FFFh TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 FFEh TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 FFDh TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 FFCh STKPTR STKFUL STKUNF — Return Stack Pointer uu-0 0000 FFBh PCLATU — — — Holding Register for PC<20:16> ---0 0000 FFAh PCLATH Holding Register for PC<15:8> 0000 0000 FF9h PCL PC Low Byte (PC<7:0>) 0000 0000 FF8h TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 FF7h TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 FF6h TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 FF5h TABLAT Program Memory Table Latch 0000 0000 FF4h PRODH Product Register High Byte xxxx xxxx FF3h PRODL Product Register Low Byte xxxx xxxx FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x FF1h INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 FF0h INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) ---- ---- FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) ---- ---- FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) ---- ---- FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) ---- ---- FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value ---- ---- of FSR0 offset by W FEAh FSR0H — — — — Indirect Data Memory Address Pointer 0 High ---- 0000 FE9h FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx FE8h WREG Working Register xxxx xxxx FE7h INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) ---- ---- Note1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). DS30009960F-page 94  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ---- FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) ---- ---- FE4h PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) ---- ---- FE3h PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value ---- ---- of FSR1 offset by W FE2h FSR1H — — — — Indirect Data Memory Address Pointer 1 High ---- xxxx FE1h FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx FE0h BSR — — — — Bank Select Register ---- 0000 FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) ---- ---- FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) ---- ---- FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) ---- ---- FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) ---- ---- FDBh PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value ---- ---- of FSR2 offset by W FDAh FSR2H — — — — Indirect Data Memory Address Pointer 2 High ---- xxxx FD9h FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx FD8h STATUS — — — N OV Z DC C ---x xxxx FD7h TMR0H Timer0 Register High Byte 0000 0000 FD6h TMR0L Timer0 Register Low Byte xxxx xxxx FD5h T0CON TMR0ON T08BIT T0CS T0SE PSA TOPS2 TOPS1 TOPS0 1111 1111 FD4h SPBRGH1 USART1 Baud Rate Generator High Byte 0000 0000 FD3h OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 0110 q000 FD2h IPR5 TMR7GIP(3) TMR12IP(3) TMR10IP(3) TMR8IP TMR7IP(3) TMR6IP TMR5IP TMR4IP 1111 1111 FD1h WDTCON REGSLP — ULPLVL SRETEN — ULPEN ULPSINK SWDTEN 0-x0 -000 FD0h RCON IPEN SBOREN CM RI TO PD POR BOR 0111 11qq FCFh TMR1H Timer1 Register High Byte xxxx xxxx FCEh TMR1L Timer1 Register Low Byte xxxx xxxx FCDh T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON 0000 0000 FCCh TMR2 Timer2 Register 0000 0000 FCBh PR2 Timer2 Period Register 1111 1111 FCAh T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 FC9h SSP1BUF MSSP Receive Buffer/Transmit Register xxxx xxxx FC8h SSP1ADD MSSP Address Register in I2C Slave Mode. SSP1 Baud Rate Reload Register in I2C Master Mode. 0000 0000 FC7h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 FC6h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 FC5h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 FC4h ADRESH A/D Result Register High Byte xxxx xxxx FC3h ADRESL A/D Result Register Low Byte xxxx xxxx FC2h ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON -000 0000 FC1h ADCON1 TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0 0000 0000 FC0h ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 FBFh ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 FBEh ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 FBDh CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx FBCh CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx FBBh CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 FBAh PIR5 TMR7GIF(3) TMR12IF(3) TMR10IF(3) TMR8IF TMR7IF(3) TMR6IF TMR5IF TMR4IF 0000 0000 FB9h PIE5 TMR7GIE(3) TMR12IE(3) TMR10IE(3) TMR8IE TMR7IE(3) TMR6IE TMR5IE TMR4IE 0000 0000 FB8h IPR4 CCP10IP(3) CCP9IP(3) CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP 1111 1111 FB7h PIR4 CCP10IF(3) CCP9IF(3) CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF 0000 0000 Note1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 95

PIC18F87K22 FAMILY TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR FB6h PIE4 CCP10IE(3) CCP9IE(3) CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE 0000 0000 FB5h CVRCON CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 0000 0000 FB4h CMSTAT CMP3OUT CMP2OUT CMP1OUT — — — — — xxx- ---- FB3h TMR3H Timer3 Register High Byte xxxx xxxx FB2h TMR3L Timer3 Register Low Byte xxxx xxxx FB1h T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16 TMR3ON 0000 0000 FB0h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS1 T3GSS0 0000 0x00 T3DONE FAFh SPBRG1 USART1 Baud Rate Generator 0000 0000 FAEh RCREG1 USART1 Receive Register 0000 0000 FADh TXREG1 USART1 Transmit Register xxxx xxxx FACh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 FABh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x FAAh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 0000 0x00 T1DONE FA9h IPR6 — — — EEIP — CMP3IP CMP2IP CMP1IP ---1 -111 FA8h HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 0000 FA7h PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- FA6h PIR6 — — — EEIF — CMP3IF CMP2IF CMP1IF ---0 -000 FA5h IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 1-11 1111 FA4h PIR3 TMR5GiF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 0-00 0000 FA3h PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 0-00 0000 FA2h IPR2 OSCFIP — SSP2IP BCL2IP BCL1IP HLVDIP TMR3IP TMR3GIP 1-11 1111 FA1h PIR2 OSCFIF — SSP2IF BCL2IF BCL1IF HLVDIF TMR3IF TMR3GIF 0-00 0000 FA0h PIE2 OSCFIE — SSP2IE BCL2IE BCL1IE HLVDIE TMR3IE TMR3GIE 0-00 0000 F9Fh IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP 1111 1111 F9Eh PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF 0000 0000 F9Dh PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE 0000 0000 F9Ch PSTR1CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 00-0 0001 F9Bh OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 F9Ah TRISJ(2) TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111 F99h TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111 F98h TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ---1 1111 F97h TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — 1111 111- F96h TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 — 1111 111- F95h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 F94h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 F92h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 F91h LATJ(2) LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx xxxx F90h LATH(2) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx F8Fh LATG — — — LATG4 LATG3 LATG2 LATG1 LATG0 ---x xxxx F8Eh LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 — xxxx xxx- F8Dh LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx F8Ch LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx F8Bh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx F89h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx F88h PORTJ(2) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx F87h PORTH(2) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 xxxx xxxx Note1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). DS30009960F-page 96  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR F86h PORTG — — RG5(1) RG4 RG3 RG2 RG1 RG0 --xx xxxx F85h PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — xxxx xxx- F84h PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx F83h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx F82h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx F80h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx F7Fh EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 F7Eh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- F7Dh TMR5H Timer5 Register High Byte xxxx xxxx F7Ch TMR5L Timer5 Register Low Byte xxxx xxxx F7Bh T5CON TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 SOSCEN T5SYNC RD16 TMR5ON 0000 0000 F7Ah T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/ T5GVAL T5GSS1 T5GSS0 0000 0x00 T5DONE F79h CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx F78h CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx F77h CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 F76h CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx F75h CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx F74h CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 F73h CCPR6H Capture/Compare/PWM Register 6 High Byte xxxx xxxx F72h CCPR6L Capture/Compare/PWM Register 6 Low Byte xxxx xxxx F71h CCP6CON — — DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0 --00 0000 F70h CCPR7H Capture/Compare/PWM Register 7 High Byte xxxx xxxx F6Fh CCPR7L Capture/Compare/PWM Register 7 Low Byte xxxx xxxx F6Eh CCP7CON — — DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0 --00 0000 F6Dh TMR4 Timer4 Register xxxx xxxx F6Ch PR4 Timer4 Period Register 1111 1111 F6Bh T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -111 1111 F6Ah SSP2BUF MSSP Receive Buffer/Transmit Register xxxx xxxx F69h SSP2ADD MSSP Address Register in I2C Slave Mode. MSSP1 Baud Rate Reload Register in I2C Master Mode. 0000 0000 F68h SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 F67h SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 F66h SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0100 0000 F65h BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 F64h OSCCON2 — SOSCRUN — — SOSCGO — MFIOFS MFIOSEL -0-- 0-x0 F63h EEADRH EEPROM Address Register High Byte 0000 0000 F62h EEADR EEPROM Address Register Low Byte 0000 0000 F61h EEDATA EEPROM Data Register 0000 0000 F60h PIE6 — — — EEIE — CMP3IE CMP2IE CMP1IE ---0 -000 F5Fh RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0-00 0000 F5Eh RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 0000 F5Dh RTCVALH RTCC Value High Register Window Based on RTCPTR<1:0> xxxx xxxx Note1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 97

PIC18F87K22 FAMILY TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR F5Ch RTCVALL RTCC Value Low Register Window Based on RTCPTR<1:0> 0000 0000 F5Bh ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000 0000 F5Ah ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 0000 F59h ALRMVALH Alarm Value High Register Window Based on APTR<1:0> xxxx xxxx F58h ALRMVALL Alarm Value Low Register Window Based on APTR<1:0> xxxx xxxx F57h CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 0-00 0000 F56h CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 0000 F55h CTMUICONH ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 0000 0000 F54h CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 F53h PADCFG1 RDPU REPU RJPU(2) — — RTSEC- RTSEC- — 000- -00- SEL1 SEL0 F52h ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 F51h ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 F50h CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx F4Fh CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx F4Eh CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 F4Dh ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 F4Ch ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 F4Bh CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx F4Ah CCPR3L Capture/Compare/PWM Register 3 Low Byte xxxx xxxx F49h CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 F48h CCPR8H Capture/Compare/PWM Register 8 High Byte xxxx xxxx F47h CCPR8L Capture/Compare/PWM Register 8 Low Byte xxxx xxxx F46h CCP8CON — — DC8B1 DC8B0 CCP8M3 CCP8M2 CCP8M1 CCP8M0 --00 0000 F45h CCPR9H(3) Capture/Compare/PWM Register 9 High Byte xxxx xxxx F44h CCPR9L(3) Capture/Compare/PWM Register 9 Low Byte xxxx xxxx F43h CCP9CON(3) — — DC9B1 DC9B0 CCP9M3 CCP9M2 CCP9M1 CCP9M0 --00 0000 F42h CCPR10H(3) Capture/Compare/PWM Register 10 High Byte xxxx xxxx F41h CCPR10L(3) Capture/Compare/PWM Register 10 Low Byte xxxx xxxx F40h CCP10CON(3) — — DC10B1 DC10B0 CCP10M3 CCP10M2 CCP10M1 CCP10M0 --00 0000 F3Fh TMR7H(3) Timer7 Register High Byte xxxx xxxx F3Eh TMR7L(3) Timer7 Register Low Byte 0000 0000 F3Dh T7CON(3) TMR7CS1 TMR7CS0 T7CKPS1 T7CKPS0 SOSCEN T7SYNC RD16 TMR7ON 0000 0000 F3Ch T7GCON(3) TMR7GE T7GPOL T7GTM T7GSPM T7GGO/ T7GVAL T7GSS1 T7GSS0 0000 0x00 T7DONE F3Bh TMR6 Timer6 Register 0000 0000 F3Ah PR6 Timer6 Period Register 1111 1111 F39h T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 -000 0000 F38h TMR8 Timer8 Register 0000 0000 F37h PR8 Timer8 Period Register 1111 1111 F36h T8CON — T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 TMR8ON T8CKPS1 T8CKPS0 -000 0000 F35h TMR10(3) TMR10 Register 0000 0000 F34h PR10(3) Timer10 Period Register 1111 1111 F33h T10CON(3) — T10OUTPS T10OUTPS T10OUTPS1 T10OUTPS TMR10ON T10CKPS1 T10CKPS0 -000 0000 3 2 0 F32h TMR12(3) TMR12 Register 0000 0000 F31h PR12(3) Timer12 Period Register 1111 1111 F30h T12CON(3) — T12OUTPS T12OUTPS T12OUTPS1 T12OUTPS TMR12ON T12CKPS1 T12CKPS0 -000 0000 3 2 0 F2Fh CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 Note1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). DS30009960F-page 98  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR F2Eh CM3CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 F2Dh CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 0000 0000 F2Ch CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0 00-0 -000 F2Bh CCPTMRS2 — — — C10TSEL0(3 — C9TSEL0(3) C8TSEL1 C8TSEL0 ---0 -000 ) F2Ah REFOCON ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 0-00 0000 F29h ODCON1 SSP1OD CCP2OD CCP1OD — — — — SSP2OD 000- ---0 F28h ODCON2 CCP10OD(3) CCP9OD(3) CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD 0000 0000 F27h ODCON3 U2OD U1OD — — — — — CTMUDS 00-- ---0 F26h MEMCON(2) EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 F25h ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 1111 1111 F24h ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 1111 1111 F23h ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 1111 1111 F22h RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x F21h TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 F20h BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 F1Fh SPBRGH2 USART2 Baud Rate Generator High Byte 0000 0000 F1Eh SPBRG2 USART2 Baud Rate Generator 0000 0000 F1Dh RCREG2 Receive Data FIFO 0000 0000 F1Ch TXREG2 Transmit Data FIFO xxxx xxxx F1Bh PSTR2CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 00-0 0001 F1Ah PSTR3CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 00-0 0001 F19h PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD 0000 0000 F18h PMD1 PSPMD CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD EMBMD 0000 0000 F17h PMD2 TMR10MD(3) TMR8MD TMR7MD(3) TMR6MD TMR5MD CMP3MD CMP2MD CMP1MD 0000 0000 F16h PMD3 CCP10MD(3) CCP9MD(3) CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD TMR12MD(3) 0000 0000 Note1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 99

PIC18F87K22 FAMILY 6.3.5 STATUS REGISTER It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions be used to The STATUS register, shown in Register6-2, contains alter the STATUS register because these instructions the arithmetic status of the ALU. The STATUS register do not affect the Z, C, DC, OV or N bits in the STATUS can be the operand for any instruction, as with any register. other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, For other instructions not affecting any Status bits, see the write to these five bits is disabled. the instruction set summaries in Table29-2 and Table29-3. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the Note: The C and DC bits operate, in subtraction, STATUS register as destination may be different than as borrow and digit borrow bits, respectively. intended. For example, CLRF STATUS will set the Z bit but leave the other bits unchanged. The STATUS register then reads back as ‘000u u1uu’. REGISTER 6-2: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the seven-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. 2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. DS30009960F-page 100  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 6.4 Data Addressing Modes of data RAM (see Section6.3.3 “General Purpose Register File”) or a location in the Access Bank (see Note: The execution of some instructions in the Section6.3.2 “Access Bank”). core PIC18 instruction set are changed The Access RAM bit, ‘a’, determines how the address when the PIC18 extended instruction set is is interpreted. When ‘a’ is ‘1’, the contents of the BSR enabled. For more information, see (Section6.3.1 “Bank Select Register”) are used with Section6.6 “Data Memory and the the address to determine the complete 12-bit address Extended Instruction Set”. of the register. When ‘a’ is ‘0’, the address is interpreted While the program memory can be addressed in only as being a register in the Access Bank. Addressing that one way, through the Program Counter, information in uses the Access RAM is sometimes also known as the data memory space can be addressed in several Direct Forced Addressing mode. ways. For most instructions, the addressing mode is A few instructions, such as MOVFF, include the entire fixed. Other instructions may use up to three modes, 12-bit address (either source or destination) in their depending on which operands are used and whether or opcodes. In these cases, the BSR is ignored entirely. not the extended instruction set is enabled. The destination of the operation’s results is determined The addressing modes are: by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are • Inherent stored back in the source register, overwriting its origi- nal contents. When ‘d’ is ‘0’, the results are stored in • Literal the W register. Instructions without the ‘d’ argument • Direct have a destination that is implicit in the instruction, • Indirect either the target register being operated on or the W An additional addressing mode, Indexed Literal Offset, register. is available when the extended instruction set is 6.4.3 INDIRECT ADDRESSING enabled (XINST Configuration bit = 1). For details on this mode’s operation, see Section6.6.1 “Indexed Indirect Addressing allows the user to access a location Addressing with Literal Offset”. in data memory without giving a fixed address in the instruction. This is done by using File Select Registers 6.4.1 INHERENT AND LITERAL (FSRs) as pointers to the locations to be read or written ADDRESSING to. Since the FSRs are themselves located in RAM as Many PIC18 control instructions do not need any Special Function Registers, they can also be directly argument at all. They either perform an operation that manipulated under program control. This makes FSRs globally affects the device or they operate implicitly on very useful in implementing data structures such as one register. This addressing mode is known as Inherent tables and arrays in data memory. Addressing. Examples of this mode include SLEEP, The registers for Indirect Addressing are also RESET and DAW. implemented with Indirect File Operands (INDFs) that Other instructions work in a similar way, but require an permit automatic manipulation of the pointer value with additional explicit argument in the opcode. This method auto-incrementing, auto-decrementing or offsetting is known as the Literal Addressing mode because the with another value. This allows for efficient code using instructions require some literal value as an argument. loops, such as the example of clearing an entire RAM Examples of this include ADDLW and MOVLW, which bank in Example6-5. It also enables users to perform respectively, add or move a literal value to the W Indexed Addressing and other Stack Pointer register. Other examples include CALL and GOTO, operations for program memory in data memory. which include a 20-bit program memory address. EXAMPLE 6-5: HOW TO CLEAR RAM 6.4.2 DIRECT ADDRESSING (BANK 1) USING INDIRECT ADDRESSING Direct Addressing specifies all or part of the source and/or destination address of the operation within the LFSR FSR0, 100h ; opcode itself. The options are specified by the NEXT CLRF POSTINC0 ; Clear INDF arguments accompanying the instruction. ; register then ; inc pointer In the core PIC18 instruction set, bit-oriented and BTFSS FSR0H, 1 ; All done with byte-oriented instructions use some version of Direct ; Bank1? Addressing by default. All of these instructions include BRA NEXT ; NO, clear next some 8-bit literal address as their Least Significant CONTINUE ; YES, continue Byte. This address specifies the instruction’s data source as either a register address in one of the banks  2009-2018 Microchip Technology Inc. DS30009960F-page 101

PIC18F87K22 FAMILY 6.4.3.1 FSR Registers and the mapped in the SFR space, but are not physically imple- INDF Operand mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. At the core of Indirect Addressing are three sets of A read from INDF1, for example, reads the data at the registers: FSR0, FSR1 and FSR2. Each represents a address indicated by FSR1H:FSR1L. pair of 8-bit registers: FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each Instructions that use the INDF registers as operands FSR pair holds a 12-bit value. This represents a value actually use the contents of their corresponding FSR as that can address the entire range of the data memory a pointer to the instruction’s target. The INDF operand in a linear fashion. The FSR register pairs, then, serve is just a convenient way of using the pointer. as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address, Indirect Addressing is accomplished with a set of Indi- data RAM banking is not necessary. Thus, the current rect File Operands, INDF0 through INDF2. These can contents of the BSR and the Access RAM bit have no be thought of as “virtual” registers. The operands are effect on determining the target address. FIGURE 6-8: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 Indirect Addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... x x x x 1 1 1 1 1 1 0 0 1 1 0 0 Bank 3 through Bank 13 ...to determine the data memory location to be used in that operation. E00h In this case, the FSR1 pair contains FCCh. This means the contents of Bank 14 location, FCCh, will be added to that F00h of the W register and stored back in Bank 15 FCCh. FFFh Data Memory DS30009960F-page 102  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 6.4.3.2 FSR Registers and POSTINC, 6.4.3.3 Operations by FSRs on FSRs POSTDEC, PREINC and PLUSW Indirect Addressing operations that target other FSRs In addition to the INDF operand, each FSR register pair or virtual registers represent special cases. For also has four additional indirect operands. Like INDF, example, using an FSR to point to one of the virtual these are “virtual” registers that cannot be indirectly registers will not result in successful operations. read or written to. Accessing these registers actually As a specific case, assume that the FSR0H:FSR0L accesses the associated FSR register pair, but also registers contain FE7h, the address of INDF1. performs a specific action on its stored value. Attempts to read the value of the INDF1, using INDF0 These operands are: as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as the operand, will result in a • POSTDEC – Accesses the FSR value, then NOP. automatically decrements it by ‘1’ afterwards • POSTINC – Accesses the FSR value, then On the other hand, using the virtual registers to write to automatically increments it by ‘1’ afterwards an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair, but without any • PREINC – Increments the FSR value by ‘1’, then incrementing or decrementing. Thus, writing to INDF2 uses it in the operation or POSTDEC2 will write the same value to the • PLUSW – Adds the signed value of the W register FSR2H:FSR2L. (range of -127 to 128) to that of the FSR and uses the new value in the operation Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct In this context, accessing an INDF register uses the operations. Users should proceed cautiously when value in the FSR registers without changing them. working on these registers, however, particularly if their Similarly, accessing a PLUSW register gives the FSR code uses Indirect Addressing. value, offset by the value in the W register, with neither value actually changed in the operation. Accessing the Similarly, operations by Indirect Addressing are gener- other virtual registers changes the value of the FSR ally permitted on all other SFRs. Users should exercise registers. the appropriate caution, so that they do not inadvertently change settings that might affect the operation of the Operations on the FSRs with POSTDEC, POSTINC device. and PREINC affect the entire register pair. Rollovers of the FSRnL register, from FFh to 00h, carry over to the 6.5 Program Memory and the FSRnH register. On the other hand, results of these Extended Instruction Set operations do not change the value of any flags in the STATUS register (for example, Z, N and OV bits). The operation of program memory is unaffected by the The PLUSW register can be used to implement a form use of the extended instruction set. of Indexed Addressing in the data memory space. By Enabling the extended instruction set adds five manipulating the value in the W register, users can additional two-word commands to the existing PIC18 reach addresses that are fixed offsets from pointer instruction set: ADDFSR, CALLW, MOVSF, MOVSS and addresses. In some applications, this can be used to SUBFSR. These instructions are executed as described implement some powerful program control structure, in Section6.2.4 “Two-Word Instructions”. such as software stacks, inside of data memory.  2009-2018 Microchip Technology Inc. DS30009960F-page 103

PIC18F87K22 FAMILY 6.6 Data Memory and the Extended Under these conditions, the file address of the Instruction Set instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing) or as Enabling the PIC18 extended instruction set (XINST an 8-bit address in the Access Bank. Instead, the value Configuration bit = 1) significantly changes certain is interpreted as an offset value to an Address Pointer aspects of data memory and its addressing. Using the specified by FSR2. The offset and the contents of FSR2 Access Bank for many of the core PIC18 instructions are added to obtain the target address of the operation. introduces a new addressing mode for the data memory space. This mode also alters the behavior of Indirect 6.6.2 INSTRUCTIONS AFFECTED BY Addressing using FSR2 and its associated operands. INDEXED LITERAL OFFSET MODE What does not change is just as important. The size of Any of the core PIC18 instructions that can use Direct the data memory space is unchanged, as well as its Addressing are potentially affected by the Indexed linear addressing. The SFR map remains the same. Literal Offset Addressing mode. This includes all Core PIC18 instructions can still operate in both Direct byte-oriented and bit-oriented instructions, or almost and Indirect Addressing mode. Inherent and literal one-half of the standard PIC18 instruction set. Instruc- instructions do not change at all. Indirect Addressing tions that only use Inherent or Literal Addressing with FSR0 and FSR1 also remains unchanged. modes are unaffected. Additionally, byte-oriented and bit-oriented instructions 6.6.1 INDEXED ADDRESSING WITH are not affected if they do not use the Access Bank LITERAL OFFSET (Access RAM bit = 1), or include a file address of 60h Enabling the PIC18 extended instruction set changes or above. Instructions meeting these criteria will the behavior of Indirect Addressing using the FSR2 continue to execute as before. A comparison of the register pair and its associated file operands. Under the different possible addressing modes when the proper conditions, instructions that use the Access extended instruction set is enabled is shown in Bank – that is, most bit-oriented and byte-oriented Figure6-9. instructions – can invoke a form of Indexed Addressing Those who desire to use byte-oriented or bit-oriented using an offset specified in the instruction. This special instructions in the Indexed Literal Offset mode should addressing mode is known as Indexed Addressing with note the changes to assembler syntax for this mode. Literal Offset or the Indexed Literal Offset mode. This is described in more detail in Section29.2.1 When using the extended instruction set, this “Extended Instruction Syntax”. addressing mode requires the following: • Use of the Access Bank (‘a’ = 0) • A file address argument that is less than or equal to 5Fh DS30009960F-page 104  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When a = 0 and f  60h: The instruction executes in 060h Direct Forced mode. ‘f’ is Bank 0 interpreted as a location in the 100h Access RAM, between 060h 00h and FFFh. This is the same as Bank 1 60h locations, F60h to FFFh through Bank 14 Valid range (Bank15), of data memory. for ‘f’ Locations below 060h are not FFh available in this addressing F00h Access RAM mode. Bank 15 F40h SFRs FFFh Data Memory When a = 0 and f5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 060h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F40h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When a = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 060h Direct mode (also known as Direct Long mode). ‘f’ is 100h interpreted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F40h SFRs FFFh Data Memory  2009-2018 Microchip Technology Inc. DS30009960F-page 105

PIC18F87K22 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN Remapping the Access Bank applies only to operations INDEXED LITERAL OFFSET MODE using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit = 1) will continue to use The use of Indexed Literal Offset Addressing mode Direct Addressing as before. Any Indirect or Indexed effectively changes how the lower part of Access RAM Addressing operation that explicitly uses any of the (00h to 5Fh) is mapped. Rather than containing just the indirect file operands (including FSR2) will continue to contents of the bottom part of Bank 0, this mode maps operate as standard Indirect Addressing. Any instruc- the contents from Bank 0 and a user-defined “window” tion that uses the Access Bank, but includes a register that can be located anywhere in the data memory address of greater than 05Fh, will use Direct space. Addressing and the normal Access Bank map. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the 6.6.4 BSR IN INDEXED LITERAL upper boundary is defined by FSR2 plus 95 (5Fh). OFFSET MODE Addresses in the Access RAM above 5Fh are mapped Although the Access Bank is remapped when the as previously described. (See Section6.3.2 “Access extended instruction set is enabled, the operation of the Bank”.) An example of Access Bank remapping in this BSR remains unchanged. Direct Addressing, using the addressing mode is shown in Figure6-10. BSR to select the data memory bank, operates in the same manner as previously described. FIGURE 6-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a Not Accessible FSR2H:FSR2L = 120h 05Fh Locations in the region Bank 0 from the FSR2 Pointer 100h (120h) to the pointer plus 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Access RAM (000h-05Fh). 200h Bank 1 “Window” 5Fh Special Function Registers 60h at F60h through FFFh are mapped to 60h through Bank 2 FFh, as usual. through SFRs Bank 0 addresses below Bank 14 5Fh are not available in FFh this mode. They can still Access Bank be addressed by using the F00h BSR. Bank 15 F60h SFRs FFFh Data Memory DS30009960F-page 106  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte • Table Read (TBLRD) at a time. For execution of a write to, or erasure of, • Table Write (TBLWT) program memory: The program memory space is 16 bits wide, while the • Memory of 32 Kbytes and 64 Kbytes (PIC18FX- data RAM space is eight bits wide. Table reads and 5K22 and PIC18FX6K22 devices) – Blocks of 64 table writes move data between these two memory bytes spaces through an eight-bit register (TABLAT). • Memory of 128 Kbytes (PIC18FX7K22 devices) – Table read operations retrieve data from program Blocks of 128 bytes memory and place it into the data RAM space. Writing or erasing program memory will cease Figure7-1 shows the operation of a table read with instruction fetches until the operation is complete. The program memory and data RAM. program memory cannot be accessed during the write Table write operations store data from the data memory or erase, therefore, code cannot execute. An internal space into holding registers in program memory. The programming timer terminates program memory writes procedure to write the contents of the holding registers and erases. into program memory is detailed in Section7.5 “Writing A value written to program memory does not need to be to Flash Program Memory”. Figure7-2 shows the a valid instruction. Executing a program memory operation of a table write with program memory and data location that forms an invalid instruction results in a RAM. NOP. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory.  2009-2018 Microchip Technology Inc. DS30009960F-page 107

PIC18F87K22 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers; the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section7.5 “Writing to Flash Program Memory”. 7.2 Control Registers The FREE bit, when set, allows a program memory erase operation. When FREE is set, the erase Several control registers are used in conjunction with operation is initiated on the next WR command. When the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled. • EECON1 register The WREN bit, when set, allows a write operation. On • EECON2 register power-up, the WREN bit is clear. The WRERR bit is set • TABLAT register in hardware when the WR bit is set and cleared when • TBLPTR registers the internal programming timer expires and the write operation is complete. 7.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is The EECON1 register (Register7-1) is the control read as ‘1’. This can indicate that a write register for memory accesses. The EECON2 register, operation was prematurely terminated by not a physical register, is used exclusively in the a Reset or a write operation was memory write and erase sequences. Reading attempted improperly. EECON2 will read all ‘0’s. The WR control bit initiates write operations. The bit The EEPGD control bit determines if the access is a cannot be cleared, only set, in software. It is cleared in program or data EEPROM memory access. When hardware at the completion of the write operation. clear, any subsequent operations operate on the data EEPROM memory. When set, any subsequent Note: The EEIF interrupt flag bit (PIR6<4>) is operations operate on the program memory. set when the write is complete. It must be The CFGS control bit determines if the access is to the cleared in software. Configuration/Calibration registers or to program memory/data EEPROM memory. When set, subsequent operations operate on Configuration registers regardless of EEPGD (see Section28.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD. DS30009960F-page 108  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. The RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition.  2009-2018 Microchip Technology Inc. DS30009960F-page 109

PIC18F87K22 FAMILY 7.2.2 TABLAT – TABLE LATCH REGISTER 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an eight-bit register The TBLPTR is used in reads, writes and erases of the mapped into the SFR space. The Table Latch register Flash program memory. is used to hold 8-bit data during data transfers between When a TBLRD is executed, all 22bits of the TBLPTR program memory and data RAM. determine which byte is read from program memory into the TABLAT. 7.2.3 TBLPTR – TABLE POINTER REGISTER When a TBLWT is executed, the six LSbs of the Table Pointer register (TBLPTR<5:0>) determine which of The Table Pointer (TBLPTR) register addresses a byte the 64 program memory holding registers is written to. within the program memory. The TBLPTR is comprised When the timed write to program memory begins (via of three SFR registers: Table Pointer Upper Byte, Table the WR bit), the 16 MSbs of the TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<21:6>) determine which program memory (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- block of 64 bytes is written to. For more detail, see ters join to form a 22-bit wide pointer. The low-order Section7.5 “Writing to Flash Program Memory”. 21bits allow the device to address up to 2Mbytes of program memory space. The 22nd bit allows access to When an erase of program memory is executed, the the Device ID, the User ID and the Configuration bits. 16MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least The Table Pointer register, TBLPTR, is used by the Significant bits (TBLPTR<5:0>) are ignored. TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways, based on the Figure7-3 describes the relevant boundaries of the table operation. These operations are shown in TBLPTR based on Flash program memory operations. Table7-1 and only affect the low-order 21bits. TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 TABLE ERASE/WRITE TABLE WRITE TBLPTR<21:6> TBLPTR<5:0> TABLE READ – TBLPTR<21:0> DS30009960F-page 110  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 7.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, the TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed, one byte words. The Least Significant bit of the address selects at a time. between the high and low bytes of the word. Figure7-4 shows the interface between the internal program memory and the TABLAT. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD BCF EECON1, CFGS ; point to Flash program memory BSF EECON1, EEPGD ; access Flash program memory MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVF WORD_ODD  2009-2018 Microchip Technology Inc. DS30009960F-page 111

PIC18F87K22 FAMILY 7.4 Erasing Flash Program Memory 7.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The erase blocks are: The sequence of events for erasing a block of internal • PIC18FX5K22 and PIC18FX6K22 – 32 words or program memory location is: 64bytes 1. Load the Table Pointer register with the address • PIC18FX7K22 – 64 words or 128bytes of the row to be erased. Word erase in the Flash array is not supported. 2. Set the EECON1 register for the erase operation: When initiating an erase sequence from the micro- • Set the EEPGD bit to point to program memory controller itself, a block of 64 or 128 bytes of program • Clear the CFGS bit to access program memory memory is erased. The Most Significant 16 bits of the • Set the WREN bit to enable writes TBLPTR<21:6> point to the block being erased. The TBLPTR<5:0> bits are ignored. • Set the FREE bit to enable the erase 3. Disable the interrupts. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash 4. Write 0x55 to EECON2. program memory. The WREN bit must be set to enable 5. Write 0xAA to EECON2. write operations. The FREE bit is set to select an erase 6. Set the WR bit. operation. This begins the row erase cycle. For protection, the write initiate sequence for EECON2 The CPU will stall for the duration of the erase must be used. for TIW. (See Parameter D133A.) A long write is necessary for erasing the internal Flash. 7. Re-enable interrupts. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 0x55 Sequence MOVWF EECON2 ; write 55h MOVLW 0xAA MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS30009960F-page 112  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 7.5 Writing to Flash Program Memory The long write is necessary for programming the internal Flash. Instruction execution is halted while in a The programming blocks are: long write cycle. The long write is terminated by the • PIC18FX5K22 and PIC18FX6K22 – 32 words or internal programming timer. 64bytes The EEPROM on-chip timer controls the write time. • PIC18FX7K22 – 64 words or 128bytes The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range Word or byte programming is not supported. of the device. Table writes are used internally to load the holding registers needed to program the Flash memory. The Note: The default value of the holding registers number of holding registers used for programming by on device Resets, and after write opera- the table writes are: tions, is FFh. A write of FFh to a holding register does not modify that byte. This • PIC18FX5K22 and PIC18FX6K22 – 64 means that individual bytes of program • PIC18FX7K22 – 128 memory may be modified, provided that Since the Table Latch (TABLAT) is only a single byte, the the change does not attempt to change TBLWT instruction may need to be executed 64times for any bit from a ‘0’ to a ‘1’. When modifying each programming operation. All of the table write oper- individual bytes, it is not necessary to load ations will essentially be short writes because only the all 64 or 128 holding registers before holding registers are written. At the end of updating the executing a write operation. 64 or 128 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxx3F Holding Register Holding Register Holding Register Holding Register Program Memory  2009-2018 Microchip Technology Inc. DS30009960F-page 113

PIC18F87K22 FAMILY 7.5.1 FLASH PROGRAM MEMORY WRITE An example of the required code is shown in SEQUENCE Example7-3. The sequence of events for programming an internal Note: Before setting the WR bit, the Table program memory location should be: Pointer address needs to be within the intended address range of the 64 or 1. Read the 64 or 128 bytes into RAM. 128bytes in the holding register. 2. Update the data values in RAM as necessary. 3. Load the Table Pointer register with the address being erased. Note: Self-write execution to Flash and 4. Execute the row erase procedure. EEPROM memory cannot be done while 5. Load the Table Pointer register with the address running in LP Oscillator mode (Low-Power of the first byte being written. mode). Therefore, executing a self-write will put the device into High-Power mode. 6. Write the 64 or 128 bytes into the holding registers with auto-increment. 7. Set the EECON1 register for the write operation: • Set the EEPGD bit to point to program memory • Clear the CFGS bit to access program memory • Set the WREN to enable byte writes 8. Disable the interrupts. 9. Write 0x55 to EECON2. 10. Write 0xAA to EECON2. 11. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write for TIW (see Parameter D133A). 12. Re-enable the interrupts. 13. Verify the memory (table read). DS30009960F-page 114  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW SIZE_OF_BLOCK ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 0x55 Required MOVWF EECON2 ; write 55h Sequence MOVLW 0xAA MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L WRITE_BUFFER_BACK MOVLW SIZE_OF_BLOCK ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS MOVFF POSTINC0, WREG ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_BYTE_TO_HREGS  2009-2018 Microchip Technology Inc. DS30009960F-page 115

PIC18F87K22 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 0x55 Required MOVWF EECON2 ; write 55h Sequence MOVLW 0xAA MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory 7.5.2 WRITE VERIFY 7.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the To protect against spurious writes to Flash program memory should be verified against the original value. memory, the write initiate sequence must also be This should be used in applications where excessive followed. See Section28.0 “Special Features of the writes can stress bits near the specification limit. CPU” for more details. 7.5.3 UNEXPECTED TERMINATION OF 7.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section28.6 “Program Verification and Code location just programmed should be verified and repro- Protection” for details on code protection of Flash grammed if needed. If the write operation is interrupted program memory. by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBLPTRU — — bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT Program Memory Table Latch INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS — FREE WRERR WREN WR RD IPR6 — — — EEIP — CMP3IP CMP2IP CMP1IP PIR6 — — — EEIF — CMP3IF CMP2IF CMP1IF PIE6 — — — EEIE — CMP3IE CMP2IE CMP1IE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits. DS30009960F-page 116  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 8.0 EXTERNAL MEMORY BUS The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE Note: The External Memory Bus is not and PORTH) are multiplexed with the address/data bus implemented on 64-pin devices. for a total of 20 available lines, while PORTJ is multiplexed with the bus control signals. The External Memory Bus (EMB) allows the device to A list of the pins and their functions is provided in access external memory devices (such as Flash, Table8-1. EPROM or SRAM) as program or data memory. It supports both 8 and 16-Bit Data Width modes and three address widths of up to 20 bits. TABLE 8-1: PIC18F87K22 FAMILY EXTERNAL BUS – I/O PORT FUNCTIONS Name Port Bit External Memory Bus Function RD0/AD0 PORTD 0 Address Bit 0 or Data Bit 0 RD1/AD1 PORTD 1 Address Bit 1 or Data Bit 1 RD2/AD2 PORTD 2 Address Bit 2 or Data Bit 2 RD3/AD3 PORTD 3 Address Bit 3 or Data Bit 3 RD4/AD4 PORTD 4 Address Bit 4 or Data Bit 4 RD5/AD5 PORTD 5 Address Bit 5 or Data Bit 5 RD6/AD6 PORTD 6 Address Bit 6 or Data Bit 6 RD7/AD7 PORTD 7 Address Bit 7 or Data Bit 7 RE0/AD8 PORTE 0 Address Bit 8 or Data Bit 8 RE1/AD9 PORTE 1 Address Bit 9 or Data Bit 9 RE2/AD10 PORTE 2 Address Bit 10 or Data Bit 10 RE3/AD11 PORTE 3 Address Bit 11 or Data Bit 11 RE4/AD12 PORTE 4 Address Bit 12 or Data Bit 12 RE5/AD13 PORTE 5 Address Bit 13 or Data Bit 13 RE6/AD14 PORTE 6 Address Bit 14 or Data Bit 14 RE7/AD15 PORTE 7 Address Bit 15 or Data Bit 15 RH0/A16 PORTH 0 Address Bit 16 RH1/A17 PORTH 1 Address Bit 17 RH2/A18 PORTH 2 Address Bit 18 RH3/A19 PORTH 3 Address Bit 19 RJ0/ALE PORTJ 0 Address Latch Enable (ALE) Control pin RJ1/OE PORTJ 1 Output Enable (OE) Control pin RJ2/WRL PORTJ 2 Write Low (WRL) Control pin RJ3/WRH PORTJ 3 Write High (WRH) Control pin RJ4/BA0 PORTJ 4 Byte Address Bit 0 (BA0) RJ5/CE PORTJ 5 Chip Enable (CE) Control pin RJ6/LB PORTJ 6 Lower Byte Enable (LB) Control pin RJ7/UB PORTJ 7 Upper Byte Enable (UB) Control pin Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins.  2009-2018 Microchip Technology Inc. DS30009960F-page 117

PIC18F87K22 FAMILY 8.1 External Memory Bus Control The operation of the EBDIS bit is also influenced by the program memory mode being used. This is discussed The operation of the interface is controlled by the in more detail in Section8.5 “Program Memory MEMCON register (Register8-1). This register is Modes and the External Memory Bus”. available in all program memory operating modes The WAIT bits allow for the addition of Wait states to except Microcontroller mode. In this mode, the register external memory operations. The use of these bits is is disabled and cannot be written to. discussed in Section8.3 “Wait States”. The EBDIS bit (MEMCON<7>) controls the operation The WM bits select the particular operating mode used of the bus and related port functions. Clearing EBDIS when the bus is operating in 16-Bit Data Width mode. enables the interface and disables the I/O functions of These bits are discussed in more detail in Section8.6 the ports, as well as any other functions multiplexed to “16-Bit Data Width Modes”. These bits have no effect those pins. Setting the bit enables the I/O ports and when an 8-Bit Data Width mode is selected. other functions, but allows the interface to override everything else on the pins when an external memory operation is required. By default, the external bus is always enabled and disables all other I/O. REGISTER 8-1: MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER(1) R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EBDIS — WAIT1 WAIT0 — — WM1 WM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EBDIS: External Bus Disable bit 1 = External bus is enabled when microcontroller accesses external memory; otherwise, all external bus drivers are mapped as I/O ports 0 = External bus is always enabled, I/O ports are disabled bit 6 Unimplemented: Read as ‘0’ bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 WM<1:0>: TBLWT Operation with 16-Bit Data Bus Width Select bits 1x = Word Write mode: TABLAT word output; WRH is active when TABLAT is written 01 = Byte Select mode: TABLAT data is copied on both MSB and LSB; WRH and (UB or LB) will activate 00 = Byte Write mode: TABLAT data is copied on both MSB and LSB; WRH or WRL will activate Note 1: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. DS30009960F-page 118  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 8.2 Address and Data Width 8.2.1 ADDRESS SHIFTING ON THE EXTERNAL BUS The PIC18F87K22 family of devices can be inde- pendently configured for different address and data By default, the address presented on the external bus widths on the same memory bus. Both address and is the value of the PC. In practical terms, this means data width are set by Configuration bits in the CON- that addresses in the external memory device, below FIG3L register. As Configuration bits, this means that the top of on-chip memory, are unavailable to the these options can only be configured by programming microcontroller. To access these physical locations, the the device and are not controllable in software. glue logic between the microcontroller and the external memory must somehow translate addresses. The BW bit selects an 8-bit or 16-bit data bus width. Setting this bit (default) selects a data width of 16 bits. To simplify the interface, the external bus offers an extension of Extended Microcontroller mode that The ABW<1:0> bits determine both the program mem- automatically performs address shifting. This feature is ory operating mode and the address bus width. The controlled by the EASHFT Configuration bit. Setting available options are 20-bit, 16-bit and 12-bit, as well this bit offsets addresses on the bus by the size of the as Microcontroller mode (external bus is disabled). microcontroller’s on-chip program memory and sets Selecting a 16-bit or 12-bit width makes a correspond- the bottom address at 0000h. This allows the device to ing number of high-order lines available for I/O use the entire range of physical addresses of the functions. These pins are no longer affected by the external memory. setting of the EBDIS bit. For example, selecting a 16-Bit Addressing mode (ABW<1:0>=01) disables 8.2.2 21-BIT ADDRESSING A<19:16> and allows PORTH<3:0> to function without As an extension of 20-bit address width operation, the interruptions from the bus. Using the smaller address External Memory Bus can also fully address a 2-Mbyte widths allows users to tailor the memory bus to the size memory space. This is done by using the Bus Address of the external memory space for a particular design Bit 0 (BA0) control line as the Least Significant bit of the while freeing up pins for dedicated I/O operation. address. The UB and LB control signals may also be Because the ABW bits have the effect of disabling pins used with certain memory devices to select the upper for memory bus operations, it is important to always and lower bytes within a 16-bit wide data word. select an address width at least equal to the data width. This addressing mode is available in both 8-Bit and If a 12-bit address width is used with a 16-bit data certain 16-Bit Data Width modes. Additional details are width, the upper four bits of data will not be available on provided in Section8.6.3 “16-Bit Byte Select Mode” the bus. and Section8.7 “8-Bit Data Width Mode”. All combinations of address and data widths require multiplexing of address and data information on the same lines. The address and data multiplexing, as well as I/O ports made available by the use of smaller address widths, are summarized in Table8-2. TABLE 8-2: ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS Multiplexed Data and Address Only Lines Ports Available Data Width Address Width Address Lines (and (and Corresponding for I/O Corresponding Ports) Ports) AD<11:8> PORTE<7:4>, 12-bit (PORTE<3:0>) All of PORTH AD<15:8> 16-bit AD<7:0> All of PORTH 8-bit (PORTE<7:0>) (PORTD<7:0>) A<19:16>, AD<15:8> 20-bit (PORTH<3:0>, — PORTE<7:0>) 16-bit AD<15:0> — All of PORTH 16-bit (PORTD<7:0>, A<19:16> 20-bit — PORTE<7:0>) (PORTH<3:0>)  2009-2018 Microchip Technology Inc. DS30009960F-page 119

PIC18F87K22 FAMILY 8.3 Wait States functions. When EBDIS = 0, the pins function as the external bus. When EBDIS = 1, the pins function as I/O While it may be assumed that external memory devices ports. will operate at the microcontroller clock rate, this is If the device fetches or accesses external memory often not the case. In fact, many devices require longer while EBDIS = 1, the pins will switch to the external times to write or retrieve data than the time allowed by bus. If the EBDIS bit is set by a program executing from the execution of table read or table write operations. external memory, the action of setting the bit will be To compensate for this, the External Memory Bus can delayed until the program branches into the internal be configured to add a fixed delay to each table opera- memory. At that time, the pins will change from external tion using the bus. Wait states are enabled by setting bus to I/O ports. the WAIT Configuration bit. When enabled, the amount If the device is executing out of internal memory when of delay is set by the WAIT<1:0> bits (MEMCON<5:4>). EBDIS = 0, the memory bus address/data and control The delay is based on multiples of microcontroller pins will not be active. They will go to a state where the instruction cycle time and is added following the active address/data pins are tri-state, the CE, OE, instruction cycle when the table operation is executed. WRH, WRL, UB and LB signals are ‘1’, and ALE and The range is from no delay to 3TCY (default value). BA0 are ‘0’. Note that only those pins associated with the current address width are forced to tri-state; the 8.4 Port Pin Weak Pull-ups other pins continue to function as I/O. In the case of With the exception of the upper address lines, 16-bit address width, for example, only AD<15:0> A<19:16>, the pins associated with the External Mem- (PORTD and PORTE) are affected; A<19:16> ory Bus are equipped with weak pull-ups. The pull-ups (PORTH<3:0>) continue to function as I/O. are controlled by the upper three bits of the PADCFG1 In all external memory modes, the bus takes priority register (PADCFG1<7:5>). They are named RDPU, over any other peripherals that may share pins with it. REPU and RJPU, and control pull-ups on PORTD, This includes the Parallel Master Port (PMP) and serial PORTE and PORTJ, respectively. Setting one of these communication modules which would otherwise take bits enables the corresponding pull-ups for that port. All priority over the I/O port. pull-ups are disabled by default on all device Resets. In Extended Microcontroller mode, the port pull-ups 8.6 16-Bit Data Width Modes can be useful in preserving the memory state on the In 16-Bit Data Width mode, the external memory external bus while the bus is temporarily disabled interface can be connected to external memories in (EBDIS = 1). three different configurations: 8.5 Program Memory Modes and the • 16-Bit Byte Write External Memory Bus • 16-Bit Word Write • 16-Bit Byte Select The PIC18F87K22 family of devices is capable of operating in one of two program memory modes, using The configuration to be used is determined by the combinations of on-chip and external program memory. WM<1:0> bits in the MEMCON register The functions of the multiplexed port pins depend on (MEMCON<1:0>). These three different configurations the program memory mode selected, as well as the allow the designer maximum flexibility in using both setting of the EBDIS bit. 8-bit and 16-bit devices with 16-bit data. In Microcontroller Mode, the bus is not active and the For all 16-bit modes, the Address Latch Enable (ALE) pins have their port functions only. Writes to the pin indicates that the Address bits, AD<15:0>, are MEMCOM register are not permitted. The Reset value available on the external memory interface bus. Follow- of EBDIS (‘0’) is ignored and the ABW pins behave as ing the address latch, the Output Enable (OE) signal I/O ports. will enable both bytes of program memory at once to form a 16-bit instruction word. The Chip Enable (CE In Extended Microcontroller Mode, the external signal) is active at any time that the microcontroller program memory bus shares I/O port functions on the accesses external memory, whether reading or writing; pins. When the device is fetching or doing table it is inactive (asserted high) whenever the device is in read/table write operations on the external program Sleep mode. memory space, the pins will have the external bus function. In Byte Select mode, JEDEC® standard Flash memo- ries will require BA0 for the byte address line and one If the device is fetching and accessing internal program I/O line to select between Byte and Word mode. The memory locations only, the EBDIS control bit will other 16-bit modes do not need BA0. JEDEC standard change the pins from external memory to I/O port static RAM memories will use the UB or LB signals for byte selection. DS30009960F-page 120  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 8.6.1 16-BIT BYTE WRITE MODE During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the Figure8-1 shows an example of 16-Bit Byte Write AD<15:0> bus. The appropriate WRH or WRL control mode for PIC18F87K22 family devices. This mode is line is strobed on the LSb of the TBLPTR. used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. FIGURE 8-1: 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18F87K22 (MSB) (LSB) A<19:0> AD<7:0> 373 A<x:0> A<x:0> D<15:8> D<7:0> D<7:0> D<7:0> CE CE AD<15:8> 373 OE WR(2) OE WR(2) ALE A<19:16>(1) CE OE WRH WRL Address Bus Data Bus Control Lines Note 1: Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”.  2009-2018 Microchip Technology Inc. DS30009960F-page 121

PIC18F87K22 FAMILY 8.6.2 16-BIT WORD WRITE MODE During a TBLWT cycle to an odd address (TBLPTR<0>= 1), the TABLAT data is presented on Figure8-2 shows an example of 16-Bit Word Write the upper byte of the AD<15:0> bus. The contents of mode for PIC18F87K22 family devices. This mode is the holding latch are presented on the lower byte of the used for word-wide memories, which includes some of AD<15:0> bus. the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of The WRH signal is strobed for each write cycle; the 16-bit memory, and table writes to any type of WRL pin is unused. The signal on the BA0 pin indicates word-wide external memories. This method makes a the LSb of the TBLPTR, but it is left unconnected. distinction between TBLWT cycles to even or odd Instead, the UB and LB signals are active to select both addresses. bytes. The obvious limitation to this method is that the table write must be done in pairs on a specific word During a TBLWT cycle to an even address boundary to correctly write a word location. (TBLPTR<0>= 0), the TABLAT data is transferred to a holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. No write signals are activated. FIGURE 8-2: 16-BIT WORD WRITE MODE EXAMPLE PIC18F87K22 AD<7:0> 373 A<20:1> A<x:0> JEDEC® Word EPROM Memory D<15:0> D<15:0> CE OE WR(2) AD<15:8> 373 ALE A<19:16>(1) CE OE WRH Address Bus Data Bus Control Lines Note 1: Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”. DS30009960F-page 122  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 8.6.3 16-BIT BYTE SELECT MODE Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC Figure8-3 shows an example of 16-Bit Byte Select standard Flash memories require that a controller I/O mode. This mode allows table write operations to port pin be connected to the memory’s BYTE/WORD word-wide external memories with byte selection pin to provide the select signal. They also use the BA0 capability. This generally includes both word-wide signal from the controller as a byte address. JEDEC Flash and SRAM devices. standard static RAM memories, on the other hand, use During a TBLWT cycle, the TABLAT data is presented the UB or LB signals to select the byte. on the upper and lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is not used. The BA0 or UB/LB signals are used to select the byte to be written, based on the Least Significant bit of the TBLPTR register. FIGURE 8-3: 16-BIT BYTE SELECT MODE EXAMPLE PIC18F87K22 A<20:1> AD<7:0> 373 A<x:1> JEDEC® Word Flash Memory D<15:0> D<15:0> 138(3) CE AD<15:8> 373 A0 ALE BYTE/WORD OE WR(1) A<19:16>(2) OE WRH WRL A<20:1> A<x:1> JEDEC® Word BA0 SRAM Memory I/O D<15:0> CE D<15:0> LB LB UB UB OE WR(1) Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”. 2: Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed.  2009-2018 Microchip Technology Inc. DS30009960F-page 123

PIC18F87K22 FAMILY 8.6.4 16-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure8-4 and Figure8-5. FIGURE 8-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:0> CF33h 9256h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW Execution FIGURE 8-5: EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:0> 3AAAh 0003h 3AABh 0E55h CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction Execution INST(PC – 2) SLEEP DS30009960F-page 124  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 8.7 8-Bit Data Width Mode will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the In 8-Bit Data Width mode, the External Memory Bus second byte will be enabled to form the 16-bit instruc- operates only in Multiplexed mode; that is, data shares tion word. The Least Significant bit of the address, BA0, the 8 Least Significant bits of the address bus. must be connected to the memory devices in this Figure8-6 shows an example of 8-Bit Multiplexed mode. The Chip Enable (CE) signal is active at any mode for PIC18F8XK22 devices. This mode is used for time that the microcontroller accesses external a single, 8-bit memory connected for 16-bit operation. memory, whether reading or writing. It is inactive The instructions will be fetched as two 8-bit bytes on a (asserted high) whenever the device is in Sleep mode. shared data/address bus. The two bytes are sequen- This generally includes basic EPROM and Flash tially fetched within one instruction cycle (TCY). devices. It allows table writes to byte-wide external Therefore, the designer must choose external memory memories. devices according to timing calculations based on During a TBLWT instruction cycle, the TABLAT data is 1/2TCY (2 times the instruction rate). For proper mem- presented on the upper and lower bytes of the ory speed selection, glue logic propagation delay times AD<15:0> bus. The appropriate level of the BA0 control must be considered, along with setup and hold times. line is strobed on the LSb of the TBLPTR. The Address Latch Enable (ALE) pin indicates that the Address bits, AD<15:0>, are available on the External Memory Bus interface. The Output Enable (OE) signal FIGURE 8-6: 8-BIT MULTIPLEXED MODE EXAMPLE D<7:0> PIC18F87K22 A<19:0> AD<7:0> 373 A<x:1> ALE D<15:8> A0 D<7:0> AD<15:8>(1) CE A<19:16>(1) OE WR(2) BA0 CE OE WRL Address Bus Data Bus Control Lines Note 1: Upper order address bits are only used for 20-bit address width. The upper AD byte is used for all address widths except 8-bit. 2: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”.  2009-2018 Microchip Technology Inc. DS30009960F-page 125

PIC18F87K22 FAMILY 8.7.1 8-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure8-7 and Figure8-8. FIGURE 8-7: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:8> CFh AD<7:0> 33h 92h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW Execution FIGURE 8-8: EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:8> 3Ah 3Ah AD<7:0> AAh 00h 03h ABh 0Eh 55h BA0 CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction Execution INST(PC – 2) SLEEP DS30009960F-page 126  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 8.8 Operation in Power-Managed In Sleep and Idle modes, the microcontroller core does Modes not need to access data; bus operations are suspended. The state of the external bus is frozen, with In alternate, power-managed Run modes, the external the address/data pins, and most of the control pins, bus continues to operate normally. If a clock source holding at the same state they were in when the mode with a lower speed is selected, bus operations will run was invoked. The only potential changes are to the CE, at that speed. In these cases, excessive access times LB and UB pins, which are held at logic high. for the external memory may result if Wait states have been enabled and added to external memory opera- tions. If operations in a lower power Run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. TABLE 8-3: REGISTERS ASSOCIATED WITH THE EXTERNAL MEMORY BUS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MEMCON(1) EBDIS — WAIT1 WAIT0 — — WM1 WM0 PADCFG1 RDPU REPU RJPU(1) — — RTSECSEL1 RTSECSEL0 — PMD1 PSPMD CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD EMBMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during External Memory Bus access. Note 1: Unimplemented in 64-pin devices (PIC18F6XK22), read as ‘0’.  2009-2018 Microchip Technology Inc. DS30009960F-page 127

PIC18F87K22 FAMILY 9.0 DATA EEPROM MEMORY 9.2 EECON1 and EECON2 Registers The data EEPROM is a nonvolatile memory array, Access to the data EEPROM is controlled by two separate from the data RAM and program memory, that registers: EECON1 and EECON2. These are the same is used for long-term storage of program data. It is not registers which control access to the program memory directly mapped in either the register file or program and are used in a similar manner for the data memory space, but is indirectly addressed through the EEPROM. Special Function Registers (SFRs). The EEPROM is The EECON1 register (Register9-1) is the control readable and writable during normal operation over the register for data and program memory access. Control entire VDD range. bit, EEPGD, determines if the access will be to program Five SFRs are used to read and write to the data memory or data EEPROM memory. When clear, EEPROM, as well as the program memory. They are: operations will access the data EEPROM memory. When set, program memory is accessed. • EECON1 • EECON2 Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data • EEDATA EEPROM memory. When set, subsequent operations • EEADR access Configuration registers. When CFGS is clear, • EEADRH the EEPGD bit selects either program Flash or data The data EEPROM allows byte read and write. When EEPROM memory. interfacing to the data memory block, EEDATA holds The WREN bit, when set, will allow a write operation. the 8-bit data for read/write and the EEADRH:EEADR On power-up, the WREN bit is clear. The WRERR bit is register pair holds the address of the EEPROM location set in hardware when the WREN bit is set, and cleared, being accessed. when the internal programming timer expires and the The EEPROM data memory is rated for high erase/write write operation is complete. cycle endurance. A byte write automatically erases the Note: During normal operation, the WRERR is location and writes the new data (erase-before-write). read as ‘1’. This can indicate that a write The write time is controlled by an on-chip timer; it will operation was prematurely terminated by vary with voltage and temperature, as well as from chip- a Reset or a write operation was to-chip. Please refer to Parameter D122 (Table31-1 in attempted improperly. Section31.0 “Electrical Characteristics”) for exact limits. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software. It is cleared in 9.1 EEADR and EEADRH Registers hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR6<4>) is The EEADRH:EEADR register pair is used to address set when the write is complete; it must be the data EEPROM for read and write operations. cleared in software. EEADRH holds the two MSbs of the address; the upper 6 bits are ignored. The 10-bit range of the pair can Control bits, RD and WR, start read and erase/write address a memory range of 1024 bytes (00h to 3FFh). operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section7.1 “Table Reads and Table Writes” regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. DS30009960F-page 128  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 9-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation has completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. The RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition.  2009-2018 Microchip Technology Inc. DS30009960F-page 129

PIC18F87K22 FAMILY 9.3 Reading the Data EEPROM After a write sequence has been initiated, EECON1, Memory EEADRH:EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the To read a data memory location, the user must write the WREN bit is set. The WREN bit must be set on a address to the EEADRH:EEADR register pair, clear the previous instruction. Both WR and WREN cannot be EEPGD control bit (EECON1<7>) and then set control set with the same instruction. bit, RD (EECON1<0>). The data is available in the At the completion of the write cycle, the WR bit is EEDATA register after one cycle; therefore, it can be cleared in hardware and the EEPROM Interrupt Flag bit read after one NOP instruction. EEDATA will hold this (EEIF) is set. The user may either enable this interrupt, value until another read operation or until it is written to or poll this bit. EEIF must be cleared by software. by the user (during a write operation). The basic process is shown in Example9-1. 9.5 Write Verify 9.4 Writing to the Data EEPROM Depending on the application, good programming practice may dictate that the value written to the Memory memory should be verified against the original value. To write an EEPROM data location, the address must This should be used in applications where excessive first be written to the EEADRH:EEADR register pair writes can stress bits near the specification limit. and the data written to the EEDATA register. The Note: Self-write execution to Flash and sequence in Example9-2 must be followed to initiate EEPROM memory cannot be done while the write cycle. running in LP Oscillator mode (Low-Power The write will not begin if this sequence is not exactly mode). Therefore, executing a self-write followed (write 0x55 to EECON2, write 0xAA to will put the device into High-Power mode. EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this codesegment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared byhardware. DS30009960F-page 130  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY EXAMPLE 9-1: DATA EEPROM READ MOVLW DATA_EE_ADDRH ; MOVWF EEADRH ; Upper bits of Data Memory Address to read MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Lower bits of Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read NOP MOVF EEDATA, W ; W = EEDATA EXAMPLE 9-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDRH ; MOVWF EEADRH ; Upper bits of Data Memory Address to write MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Lower bits of Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 0x55 ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0xAA ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete GOTO $-2 BSF INTCON, GIE ; Enable Interrupts ; User code execution BCF EECON1, WREN ; Disable writes on write complete (EEIF set)  2009-2018 Microchip Technology Inc. DS30009960F-page 131

PIC18F87K22 FAMILY 9.6 Operation During Code-Protect 9.8 Using the Data EEPROM Data EEPROM memory has its own code-protect bits in The data EEPROM is a high-endurance, byte address- the Configuration Words. External read and write able array that has been optimized for the storage of operations are disabled if code protection is enabled. frequently changing information (e.g., program variables or other data that is updated often). The microcontroller itself can both read and write to the Frequently changing values will typically be updated internal data EEPROM, regardless of the state of the more often than Specification D124. If this is the case, code-protect Configuration bit. Refer to Section28.0 an array refresh must be performed. For this reason, “Special Features of the CPU” for additional variables that change infrequently (such as constants, information. IDs, calibration, etc.) should be stored in Flash program memory. 9.7 Protection Against Spurious Write A simple data EEPROM refresh routine is shown in There are conditions when the device may not want to Example9-3. write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have Note: If data EEPROM is only used to store been implemented. On power-up, the WREN bit is constants and/or data that changes often, cleared. In addition, writes to the EEPROM are blocked an array refresh is likely not required. See during the Power-up Timer period (TPWRT, Specification D124. Parameter33 in Table31-14). The write initiate sequence, and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. EXAMPLE 9-3: DATA EEPROM REFRESH ROUTINE CLRF EEADR ; Start at address 0 CLRF EEADRH ; BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes LOOP ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 0x55 ; MOVWF EECON2 ; Write 55h MOVLW 0xAA ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA LOOP ; Not zero, do it again INCFSZ EEADRH, F ; Increment the high address BRA LOOP ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts DS30009960F-page 132  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 9-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF EEADRH EEPROM Address Register High Byte EEADR EEPROM Address Register Low Byte EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS — FREE WRERR WREN WR RD IPR6 — — — EEIP — CMP3IP CMP2IP CMP1IP PIR6 — — — EEIF — CMP3IF CMP2IF CMP1IF PIE6 — — — EEIE — CMP3IE CMP2IE CMP1IE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.  2009-2018 Microchip Technology Inc. DS30009960F-page 133

PIC18F87K22 FAMILY 10.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 10-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 10.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS EXAMPLE 10-2: 8 x 8 SIGNED MULTIPLY register. ROUTINE Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the MOVF ARG1, W advantages of higher computational throughput and MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit allows PIC18 devices to be used in many applications SUBWF PRODH, F ; PRODH = PRODH previously reserved for digital-signal processors. A ; - ARG1 comparison of various hardware and software multiply MOVF ARG2, W operations, along with the savings in memory and BTFSC ARG1, SB ; Test Sign Bit execution time, is shown in Table10-1. SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 10.2 Operation Example10-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example10-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 10-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 64 MHz @ 48 MHz @ 10 MHz @ 4 MHz Without Hardware Multiply 13 69 4.3 s 5.7 s 27.6 s 69 s 8 x 8 Unsigned Hardware Multiply 1 1 62.5 ns 83.3 ns 400 ns 1 s Without Hardware Multiply 33 91 5.6 s 7.5 s 36.4 s 91 s 8 x 8 Signed Hardware Multiply 6 6 375 ns 500 ns 2.4 s 6 s 16 x 16 Without Hardware Multiply 21 242 15.1 s 20.1 s 96.8 s 242 s Unsigned Hardware Multiply 28 28 1.7 s 2.3 s 11.2 s 28 s Without Hardware Multiply 52 254 15.8 s 21.2 s 101.6 s 254 s 16 x 16 Signed Hardware Multiply 35 40 2.5 s 3.3 s 16.0 s 40 s DS30009960F-page 134  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY Example10-3 shows the sequence to do a 16 x 16 EQUATION 10-2: 16 x 16 SIGNED unsigned multiplication. Equation10-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0= ARG1H:ARG1L  ARG2H:ARG2L = (ARG1H  ARG2H  216) + EQUATION 10-1: 16 x 16 UNSIGNED (ARG1H  ARG2L  28) + MULTIPLICATION (ARG1L  ARG2H  28) + ALGORITHM (ARG1L  ARG2L) + (-1  ARG2H<7>  ARG1H:ARG1L  216) + RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L (-1  ARG1H<7>  ARG2H:ARG2L  216) = (ARG1H  ARG2H  216) + (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + EXAMPLE 10-4: 16 x 16 SIGNED (ARG1L  ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 10-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL MOVF PRODL, W ; ; ADDWF RES1, F ; Add cross MOVF ARG1L, W MOVF PRODH, W ; products MULWF ARG2H ; ARG1L * ARG2H-> ADDWFC RES2, F ; ; PRODH:PRODL CLRF WREG ; MOVF PRODL, W ; ADDWFC RES3, F ; ADDWF RES1, F ; Add cross ; MOVF PRODH, W ; products MOVF ARG1H, W ; ADDWFC RES2, F ; MULWF ARG2L ; ARG1H * ARG2L -> CLRF WREG ; ; PRODH:PRODL ADDWFC RES3, F ; MOVF PRODL, W ; ; ADDWF RES1, F ; Add cross MOVF ARG1H, W ; MOVF PRODH, W ; products MULWF ARG2L ; ARG1H * ARG2L-> ADDWFC RES2, F ; ; PRODH:PRODL CLRF WREG ; MOVF PRODL, W ; ADDWFC RES3, F ; ADDWF RES1, F ; Add cross ; MOVF PRODH, W ; products BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? ADDWFC RES2, F ; BRA SIGN_ARG1 ; no, check ARG1 CLRF WREG ; MOVF ARG1L, W ; SUBWF RES2 ; ADDWFC RES3, F ; MOVF ARG1H, W ; SUBWFB RES3 ; SIGN_ARG1 Example10-4 shows the sequence to do a 16 x 16 BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? signed multiply. Equation10-2 shows the algorithm BRA CONT_CODE ; no, done used. The 32-bit result is stored in four registers MOVF ARG2L, W ; (RES3:RES0). To account for the sign bits of the SUBWF RES2 ; arguments, the MSb for each argument pair is tested MOVF ARG2H, W ; SUBWFB RES3 and the appropriate subtractions are done. ; CONT_CODE :  2009-2018 Microchip Technology Inc. DS30009960F-page 135

PIC18F87K22 FAMILY 11.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are Members of the PIC18F87K22 family of devices have compatible with PIC® mid-range devices. In multiple interrupt sources and an interrupt priority Compatibility mode, the interrupt priority bits for each feature that allows most interrupt sources to be source have no effect. INTCON<6> is the PEIE bit that assigned a high-priority level or a low-priority level. The enables/disables all peripheral interrupt sources. high-priority interrupt vector is at 0008h and the INTCON<7> is the GIE bit that enables/disables all low-priority interrupt vector is at 0018h. High-priority interrupt sources. All interrupts branch to address, interrupt events will interrupt any low-priority interrupts 0008h, in Compatibility mode. that may be in progress. When an interrupt is responded to, the Global Interrupt The registers for controlling interrupt operation are: Enable bit is cleared to disable further interrupts. If the • RCON IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. • INTCON High-priority interrupt sources can interrupt a • INTCON2 low-priority interrupt. Low-priority interrupts are not • INTCON3 processed while high-priority interrupts are in progress. • PIR1, PIR2, PIR3 The return address is pushed onto the stack and the • PIE1, PIE2, PIE3 PC is loaded with the interrupt vector address (0008h • IPR1, IPR2, IPR3 or 0018h). Once in the Interrupt Service Routine (ISR), the source(s) of the interrupt can be determined by poll- It is recommended that the Microchip header files supplied with MPLAB® IDE be used for the symbolic bit ing the interrupt flag bits. The interrupt flag bits must be names in these registers. This allows the cleared in software, before re-enabling interrupts, to assembler/compiler to automatically take care of the avoid recursive interrupts. placement of these bits within the specified register. The “return from interrupt” instruction, RETFIE, exits In general, interrupt sources have three bits to control the interrupt routine and sets the GIE bit (GIEH or GIEL their operation. They are: if priority levels are used) that re-enables interrupts. • Flag bit – Indicating that an interrupt event For external interrupt events, such as the INTx pins or occurred the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact • Enable bit – Enabling program execution to latency is the same for one or two-cycle instructions. branch to the interrupt vector address when the Individual interrupt flag bits are set regardless of the flag bit is set status of their corresponding enable bit or the GIE bit. • Priority bit – Specifying high priority or low priority Note: Do not use the MOVFF instruction to modify The interrupt priority feature is enabled by setting the any of the Interrupt Control registers while IPEN bit (RCON<7>). When interrupt priority is any interrupt is enabled. Doing so may enabled, there are two bits that enable interrupts cause erratic microcontroller behavior. globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) and GIEH bit (INTCON<7>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate Global Interrupt Enable bit are set, the interrupt will vector immediately to address, 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. DS30009960F-page 136  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 11-1: PIC18F87K22 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> TMR0IF Wake-up if in IPR1<7:0> TMR0IE Idle or Sleep modes TMR0IP RBIF PIR2<7,5:0> RBIE PIE2<7,5:0> RBIP IPR2<7,5:0> INT0IF INT0IE PIR3<7,5> INT1IF PIE3<7,5> INT1IE Interrupt to CPU IPR3<7,5> INT1IP Vector to Location INT2IF PIR4<7:0> INT2IE 0008h PIE4<7:0> INT2IP IPR4<7:0> INT3IF INT3IE INT3IP GIE/GIEH PIR5<7:0> PIE5<7:0> IPR5<7:0> IPEN PIR6<4, 2:0> IPEN PIE6<4, 2:0> PEIE/GIEL IPR6<4, 2:0> IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7, 5:0> PIE2<7, 5:0> IPR2<7, 5:0> Interrupt to CPU PIR3<7, 5:0> TTMMRR00IIEF IPEN V00e1c8tohr to Location PIE3<7, 5:0> TMR0IP IPR3<7, 5:0> RBIF PIR4<7:0> RBIE PIE4<7:0> RBIP GIE/GIEH IPR4<7:0> PEIE/GIEL INT1IF INT1IE PIR5<7:0> INT1IP PIE5<7:0> INT2IF IPR5<7:0> INT2IE INT2IP PIR6<4, 2:0> INT3IF PIE6<4, 2:0> INT3IE IPR6<4, 2:0> INT3IP  2009-2018 Microchip Technology Inc. DS30009960F-page 137

PIC18F87K22 FAMILY 11.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the Global registers that contain various enable, priority and flag Interrupt Enable bit. User software should bits. ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 11-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction cycle, will end the mismatch condition and allow the bit to be cleared. DS30009960F-page 138  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 11-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual TRIS register values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2009-2018 Microchip Technology Inc. DS30009960F-page 139

PIC18F87K22 FAMILY REGISTER 11-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS30009960F-page 140  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 11.2 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the Global peripheral interrupts. Due to the number of peripheral Interrupt Enable bit, GIE (INTCON<7>). interrupt sources, there are six Peripheral Interrupt Request (Flag) registers (PIR1 through PIR6). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 11-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or write operation has taken place (must be cleared in software) 0 = No read or write operation has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART receive buffer is empty bit 4 TX1IF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART transmit buffer is full bit 3 SSP1IF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (must be cleared in software) 0 = No timer gate interrupt occurred bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow  2009-2018 Microchip Technology Inc. DS30009960F-page 141

PIC18F87K22 FAMILY REGISTER 11-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF — SSP2IF BCL2IF BCL1IF HLVDIF TMR3IF TMR3GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock is operating bit 6 Unimplemented: Read as ‘0’ bit 5 SSP2IF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception has been completed (must be cleared in software) 0 = Waiting to transmit/receive bit 4 BCL2IF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 3 BCL1IF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the regulator’s low-voltage trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (must be cleared in software) 0 = No timer gate interrupt occurred DS30009960F-page 142  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 11-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR5GIF: Timer5 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (must be cleared in software) 0 = No timer gate interrupt occurred bit 6 Unimplemented: Read as ‘0’ bit 5 RC2IF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The EUSART receive buffer is empty bit 4 TX2IF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The EUSART transmit buffer is full bit 3 CTMUIF: CTMU Interrupt Flag bit 1 = CTMU interrupt occurred (must be cleared in software) 0 = No CTMU interrupt occurred bit 2 CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Unused in this mode. bit 1 CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Unused in this mode. bit 0 RTCCIF: RTCC Interrupt Flag bit 1 = RTCC interrupt occurred (must be cleared in software) 0 = No RTCC interrupt occurred  2009-2018 Microchip Technology Inc. DS30009960F-page 143

PIC18F87K22 FAMILY REGISTER 11-7: PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP10IF(1) CCP9IF(1) CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 CCP<10:4>IF: CCP<10:4> Interrupt Flag bits(1) Capture Mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare Mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode: Not used in PWM mode. bit 0 CCP3IF: ECCP3 Interrupt Flag bit Capture Mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare Mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode: Not used in PWM mode. Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). DS30009960F-page 144  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 11-8: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR7GIF(1) TMR12IF(1) TMR10IF(1) TMR8IF TMR7IF(1) TMR6IF TMR5IF TMR4IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR7GIF: TMR7 Gate Interrupt Flag bits(1) 1 = TMR gate interrupt occurred (bit must be cleared in software) 0 = No TMR gate interrupt occurred bit 6 TMR12IF: TMR12 to PR12 Match Interrupt Flag bit(1) 1 = TMR12 to PR12 match occurred (must be cleared in software) 0 = No TMR12 to PR12 match occurred bit 5 TMR10IF: TMR10 to PR10 Match Interrupt Flag bit(1) 1 = TMR10 to PR10 match occurred (must be cleared in software) 0 = No TMR10 to PR10 match occurred bit 4 TMR8IF: TMR8 to PR8 Match Interrupt Flag bit 1 = TMR8 to PR8 match occurred (must be cleared in software) 0 = No TMR8 to PR8 match occurred bit 3 TMR7IF: TMR7 Overflow Interrupt Flag bit(1) 1 = TMR7 register overflowed (must be cleared in software) 0 = TMR7 register did not overflow bit 2 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = TMR6 to PR6 match occurred (must be cleared in software) 0 = No TMR6 to PR6 match occurred bit 1 TMR5IF: TMR5 Overflow Interrupt Flag bit 1 = TMR5 register overflowed (must be cleared in software) 0 = TMR5 register did not overflow bit 0 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 145

PIC18F87K22 FAMILY REGISTER 11-9: PIR6: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 6 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — EEIF — CMP3IF CMP2IF CMP1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEDATA/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 Unimplemented: Read as ‘0’ bit 2 CMP3IF: CMP3 Interrupt Flag bit 1 = CMP3 interrupt occurred (must be cleared in software) 0 = No CMP3 interrupt occurred bit 1 CMP2IF: CMP2 Interrupt Flag bit 1 = CMP2 interrupt occurred (must be cleared in software) 0 = No CMP2 interrupt occurred bit 0 CMP1IF: CM1 Interrupt Flag bit 1 = CMP1 interrupt occurred (must be cleared in software) 0 = No CMP1 interrupt occurred DS30009960F-page 146  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 11.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Enable registers (PIE1 through PIE6). When IPEN (RCON<7>) = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 11-10: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TX1IE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSP1IE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 TMR1GIE: TMR1 Gate Interrupt Enable bit 1 = Enables the gate 0 = Disabled the gate bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt  2009-2018 Microchip Technology Inc. DS30009960F-page 147

PIC18F87K22 FAMILY REGISTER 11-11: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE — SSP2IE BCL2IE BCL1IE HLVDIE TMR3IE TMR3GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 Unimplemented: Read as ‘0’ bit 5 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 4 BCL2IE: Bus Collision Interrupt Enable bit 1 = Enables the bus collision interrupt 0 = Disables the bus collision interrupt bit 3 BCL1IE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled DS30009960F-page 148  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 11-12: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR5GIE: Timer5 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 Unimplemented: Read as ‘0’ bit 5 RC2IE: EUSART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 CTMUIE: CTMU Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled REGISTER 11-13: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP10IE(1) CCP9IE(1) CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CCP<10:3>IE: CCP<10:3> Interrupt Enable bits(1) 1 = Enabled 0 = Disabled Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 149

PIC18F87K22 FAMILY REGISTER 11-14: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR7GIE(1) TMR12IE(1) TMR10IE(1) TMR8IE TMR7IE(1) TMR6IE TMR5IE TMR4IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR7GIE: TMR7 Gate Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit 6 TMR12IE: TMR12 to PR12 Match Interrupt Enable bit(1) 1 = Enables the TMR12 to PR12 match interrupt 0 = Disables the TMR12 to PR12 match interrupt bit 5 TMR10IE: TMR10 to PR10 Match Interrupt Enable bit(1) 1 = Enables the TMR10 to PR10 match interrupt 0 = Disables the TMR10 to PR10 match interrupt bit 4 TMR8IE: TMR8 to PR8 Match Interrupt Enable bit 1 = Enables the TMR8 to PR8 match interrupt 0 = Disables the TMR8 to PR8 match interrupt bit 3 TMR7IE: TMR7 Overflow Interrupt Enable bit(1) 1 = Enables the TMR7 overflow interrupt 0 = Disables the TMR7 overflow interrupt bit 2 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the TMR6 to PR6 match interrupt 0 = Disables the TMR6 to PR6 match interrupt bit 1 TMR5IE: TMR5 Overflow Interrupt Enable bit 1 = Enables the TMR5 overflow interrupt 0 = Disables the TMR5 overflow interrupt bit 0 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 match interrupt 0 = Disables the TMR4 to PR4 match interrupt Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). DS30009960F-page 150  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 11-15: PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — EEIE — CMP3IE CMP2IE CMP1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEDATA/Flash Write Operation Enable bit 1 = Interrupt is enabled 0 = interrupt is disabled bit 3 Unimplemented: Read as ‘0’ bit 2 CMP3IE: CMP3 Enable bit 1 = Interrupt is enabled 0 = interrupt is disabled bit 1 CMP2E: CMP2 Enable bit 1 = Interrupt is enabled 0 = interrupt is disabled bit 0 CMP1IE: CMP1 Enable bit 1 = Interrupt is enabled 0 = interrupt is disabled  2009-2018 Microchip Technology Inc. DS30009960F-page 151

PIC18F87K22 FAMILY 11.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Priority registers (IPR1 through IPR6). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit (RCON<7>) be set. REGISTER 11-16: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSP1IP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 TMR1GIP: Timer1 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS30009960F-page 152  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 11-17: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP — SSP2IP BCL2IP BCL1IP HLVDIP TMR3IP TMR3GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 Unimplemented: Read as ‘0’ bit 5 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 BCL2IP: Bus Collision Interrupt priority bit (MSSP) 1 = High priority 0 = Low priority bit 3 BCL1IP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority  2009-2018 Microchip Technology Inc. DS30009960F-page 153

PIC18F87K22 FAMILY REGISTER 11-18: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 U-0 R-1 R-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR5GIP: Timer5 Gate interrupt Priority bit 1 = High priority 0 = Low priority bit 6 Unimplemented: Read as ‘0’ bit 5 RC2IP: EUSART Receive Priority Flag bit 1 = High priority 0 = Low priority bit 4 TX2IP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 CTMUIP: CTMU Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RTCCIP: RTCC Interrupt Priority bit 1 = High priority 0 = Low priority REGISTER 11-19: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CCP10IP(1) CCP9IP(1) CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CCP<10:3>IP: CCP<10:3> Interrupt Priority bits(1) 1 = High priority 0 = Low priority Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). DS30009960F-page 154  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 11-20: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR7GIP(1) TMR12IP(1) TMR10IP(1) TMR8IP TMR7IP(1) TMR6IP TMR5IP TMR4IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR7GIP: TMR7 Gate Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 TMR12IP: TMR12 to PR12 Match Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 5 TMR10IP: TMR10 to PR10 Match Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 4 TMR8IP: TMR8 to PR8 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR7IP: TMR7 Overflow Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 2 TMR6IP: TMR6 to PR6 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR5IP: TMR5 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 155

PIC18F87K22 FAMILY REGISTER 11-21: IPR6: PERIPHERAL INTERRUPT PRIORITY REGISTER 6 U-0 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — — EEIP — CMP3IP CMP2IP CMP1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 EEIP: EE Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 Unimplemented: Read as ‘0’ bit 2 CMP3IP: CMP3 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CMP2IP: CMP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CMP1IP: CMP1 Interrupt Priority bit 1 = High priority 0 = Low priority DS30009960F-page 156  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 11.5 RCON Register The RCON register contains the bits used to determine the cause of the last Reset, or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 11-22: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: Software BOR Enable bit For details of bit operation, see Register5-1. bit 5 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be subsequently set in software) bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register5-1. bit 3 TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register5-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register5-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register5-1.  2009-2018 Microchip Technology Inc. DS30009960F-page 157

PIC18F87K22 FAMILY 11.6 INTx Pin Interrupts 11.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, In 8-bit mode (the default), an overflow in the TMR0 RB2/INT2 and RB3/INT3 pins are edge-triggered. If the register (FFh00h) will set flag bit, TMR0IF. In 16-bit corresponding INTEDGx bit in the INTCON2 register is mode, an overflow in the TMR0H:TMR0L register pair set (= 1), the interrupt is triggered by a rising edge. If (FFFFh0000h) will set TMR0IF. that bit is clear, the trigger is on the falling edge. The interrupt can be enabled/disabled by setting/clearing When a valid edge appears on the RBx/INTx pin, the enable bit, TMR0IE (INTCON<5>). Interrupt priority for corresponding flag bit, INTxIF, is set. This interrupt can Timer0 is determined by the value contained in the inter- be disabled by clearing the corresponding enable bit, rupt priority bit, TMR0IP (INTCON2<2>). For further INTxIE. Before re-enabling the interrupt, the flag bit details on the Timer0 module, see Section13.0 “Timer0 (INTxIF) must be cleared in software in the Interrupt Module”. Service Routine. 11.8 PORTB Interrupt-on-Change All external interrupts (INT0, INT1, INT2 and INT3) can wake up the processor from the power-managed An input change on PORTB<7:4> sets flag bit, RBIF modes if bit, INTxIE, was set prior to going into the (INTCON<0>). The interrupt can be enabled/disabled power-managed modes. If the Global Interrupt Enable by setting/clearing enable bit, RBIE (INTCON<3>). bit (GIE) is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt The interrupt priority for INT1, INT2 and INT3 is priority bit, RBIP (INTCON2<0>). determined by the value contained in the Interrupt Priority bits, INT1IP (INTCON3<6>), INT2IP 11.9 Context Saving During Interrupts (INTCON3<7>) and INT3IP (INTCON2<1>). There is no priority bit associated with INT0. It is always During interrupts, the return PC address is saved on a high-priority interrupt source. the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack. If a fast return from interrupt is not used (see Section6.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR regis- ters on entry to the Interrupt Service Routine (ISR). Depending on the user’s application, other registers may also need to be saved. Example11-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 11-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS30009960F-page 158  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 11-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF PIR1 PSPIP ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIR2 OSCFIF — SSP2IF BCL2IF BCL1IF HLVDIF TMR3IF TMR3GIF PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIR4 CCP10IF(1) CCP9IF(1) CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF PIR5 TMR7GIF(1) TMR12IF(1) TMR10IF(1) TMR8IF TMR7IF(1) TMR6IF TMR5IF TMR4IF PIR6 — — — EEIF — CMP3IF CMP2IF CMP1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE PIE2 OSCFIE — SSP2IE BCL2IE BCL1IE HLVDIE TMR3IE TMR3GIE PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE PIE4 CCP10IE(1) CCP9IE(1) CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE PIE5 TMR7GIE(1) TMR12IE(1) TMR10IE(1) TMR8IE TMR7IE(1) TMR6IE TMR5IE TMR4IE PIE6 — — — EEIE — CMP3IE CMP2IE CMP1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP IPR2 OSCFIP — SSP2IP BCL2IP BCL1IP HLVDIP TMR3IP TMR3GIP IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP IPR4 CCP10IP(1) CCP9IP(1) CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP IPR5 TMR7GIP(1) TMR12IP(1) TMR10IP(1) TMR8IP TMR7IP(1) TMR6IP TMR5IP TMR4IP IPR6 — — — EEIP — CMP3IP CMP2IP CMP1IP RCON IPEN SBOREN CM RI TO PD POR BOR Legend: Shaded cells are not used by the interrupts. Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 159

PIC18F87K22 FAMILY 12.0 I/O PORTS 12.1 I/O Port Pin Capabilities Depending on the device selected and features When developing an application, the capabilities of the enabled, there are up to nine ports available. Some port pins must be considered. Outputs on some pins pins of the I/O ports are multiplexed with an alternate have higher output drive strength than others. Similarly, function from the peripheral features on the device. In some pins can tolerate higher than VDD input levels. general, when a peripheral is enabled, that pin may not All of the digital ports are 5.5V input tolerant. The ana- be used as a general purpose I/O pin. log ports have the same tolerance – having clamping Each port has three memory mapped registers for its diodes implemented internally. operation: 12.1.1 PIN OUTPUT DRIVE • TRIS register (Data Direction register) When used as digital I/O, the output pin drive strengths • PORT register (reads the levels on the pins of the vary, according to the pins’ grouping, to meet the needs device) for a variety of applications. In general, there are two • LAT register (Output Latch register) classes of output pins, in terms of drive capability: Reading the PORT register reads the current status of • Outputs designed to drive higher current loads, the pins, whereas writing to the PORT register writes to such as LEDs: the Output Latch (LAT) register. - PORTA - PORTB Setting a TRIS bit (= 1) makes the corresponding port - PORTC pin an input (putting the corresponding output driver in • Outputs with lower drive levels, but capable of a High-Impedance mode). Clearing a TRIS bit (= 0) driving normal digital circuit loads with a high input makes the corresponding port pin an output (i.e., puts the contents of the corresponding LAT bit on the impedance. Able to drive LEDs, but only those selected pin). with smaller current requirements: - PORTD - PORTE The Output Latch (LAT register) is useful for read-modify-write operations on the value that the I/O - PORTF - PORTG pins are driving. Read-modify-write operations on the - PORTH(†) - PORTJ(†) LAT register read and write the latched output value for † These ports are not available on 64-pin the PORT register. devices. A simplified model of a generic I/O port, without the 12.1.2 PULL-UP CONFIGURATION interfaces to other peripherals, is shown in Figure12-1. Four of the I/O ports (PORTB, PORTD, PORTE and FIGURE 12-1: GENERIC I/O PORT PORTJ) implement configurable weak pull-ups on all OPERATION pins. These are internal pull-ups that allow floating digital input signals to be pulled to a consistent level without the use of external resistors. RD LAT The pull-ups are enabled with a single bit for each of the Data ports: RBPU (INTCON2<7>) for PORTB, and RDPU, Bus D Q REPU and RJPU (PADCFG1<7:5>) for the other ports. WR LAT I/O Pin or PORT CKx Data Latch D Q WR TRIS CKx TRIS Latch Input Buffer RD TRIS Q D ENEN RD PORT DS30009960F-page 160  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 12-1: PADCFG1: PAD CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 RDPU REPU RJPU(2) — — RTSECSEL1(1) RTSECSEL0(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RDPU: PORTD Pull-up Enable bit 1 = PORTD pull-up resistors are enabled by individual port latch values 0 = All PORTD pull-up resistors are disabled bit 6 REPU: PORTE Pull-up Enable bit 1 = PORTE pull-up resistors are enabled by individual port latch values 0 = All PORTE pull-up resistors are disabled bit 5 RJPU: PORTJ Pull-up Enable bit(2) 1 = PORTJ pull-up resistors are enabled by individual port latch values 0 = All PORTJ pull-up resistors are disabled bit 4-3 Unimplemented: Read as ‘0’ bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1) 11 = Reserved; do not use 10 = RTCC source clock is selected for the RTCC pin (the pin can be LF-INTOSC or SOSC, depending on the RTCOSC (CONFIG3L<1>) bit setting) 01 = RTCC seconds clock is selected for the RTCC pin 00 = RTCC alarm pulse is selected for the RTCC pin bit 0 Unimplemented: Read as ‘0’ Note 1: To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set. 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.  2009-2018 Microchip Technology Inc. DS30009960F-page 161

PIC18F87K22 FAMILY 12.1.3 OPEN-DRAIN OUTPUTS FIGURE 12-2: USING THE OPEN-DRAIN OUTPUT (USART SHOWN The output pins for several peripherals are also AS EXAMPLE) equipped with a configurable, open-drain output option. This allows the peripherals to communicate with 3.3V +5V external digital logic, operating at a higher voltage level, without the use of level translators. PIC18F87K22 The open-drain option is implemented on port pins specifically associated with the data and clock outputs 3.3V of the USARTs, the MSSP module (in SPI mode) and VDD TXX 5V the CCP modules. This option is selectively enabled by (at logic ‘1’) setting the open-drain control bits in the registers, ODCON1, ODCON2 and ODCON3. When the open-drain option is required, the output pin must also be tied through an external pull-up resistor provided by the user to a higher voltage level, up to 5V (Figure12-2). When a digital logic high signal is output, it is pulled up to the higher voltage level. REGISTER 12-2: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 SSP1OD CCP2OD CCP1OD — — — — SSP2OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP1OD: MSSP1 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 6 CCP2OD: ECCP2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 5 CCP1OD: ECCP1 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 4-1 Unimplemented: Read as ‘0’ bit 0 SSP2OD: MSSP2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled DS30009960F-page 162  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 12-3: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP10OD(1) CCP9OD(1) CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CCP10OD: CCP10 Open-Drain Output Enable bit(1) 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 6 CCP9OD: CCP9 Open-Drain Output Enable bit(1) 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 5 CCP8OD: CCP8 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 4 CCP7OD: CCP7 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 3 CCP6OD: CCP6 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 2 CCP5OD: CCP5 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 1 CCP4OD: CCP4 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 0 CCP3OD: ECCP3 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled Note 1: Not implemented on devices with 32-byte program memory (PIC18FX5K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 163

PIC18F87K22 FAMILY REGISTER 12-4: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U2OD U1OD — — — — — CTMUDS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 U2OD: EUSART2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 6 U1OD: EUSART1 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 5-1 Unimplemented: Read as ‘0’ bit 0 CTMUDS: CTMU Pulse Delay Enable bit 1 = Pulse delay input for CTMU is enabled on pin, RF1 0 = Pulse delay input for CTMU is disabled on pin, RF1 12.1.4 ANALOG AND DIGITAL PORTS Setting these registers makes the corresponding pins analog and clearing the registers makes the ports digi- Many of the ports multiplex analog and digital function- tal. For details on these registers, see Section23.0 ality, providing a lot of flexibility for hardware designers. “12-Bit Analog-to-Digital Converter (A/D) Module”. PIC18F87K22 family devices can make any analog pin analog or digital, depending on an application’s needs. The ports’ analog/digital functionality is controlled by registers: ANCON0, ANCON1 and ANCON2. DS30009960F-page 164  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 12.2 PORTA, TRISA and OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally LATA Registers serve as the external circuit connections for the exter- nal (primary) oscillator circuit (HS Oscillator modes), or PORTA is an 8-bit wide, bidirectional port. The corre- the external clock input and output (EC Oscillator sponding Data Direction and Output Latch registers are modes). In these cases, RA6 and RA7 are not available TRISA and LATA. as digital I/O and their corresponding TRIS and LAT RA4/T0CKI is a Schmitt Trigger input. All other PORTA bits are read as ‘0’. When the device is configured to pins have TTL input levels and full CMOS output use HF-INTOSC, MF-INTOSC or LF-INTOSC as the drivers. default oscillator mode, RA6 and RA7 are automatically configured as digital I/O; the oscillator and clock RA5 and RA<3:0> are multiplexed with analog inputs in/clock out functions are disabled. for the A/D Converter. RA5 has additional functionality for Timer1 and Timer3. The operation of the analog inputs as A/D Converter It can be configured as the Timer1 clock input or the inputs is selected by clearing or setting the ANSEL Timer3 external clock gate input. control bits in the ANCON1 register. The corresponding TRISA bits control the direction of these pins, even EXAMPLE 12-1: INITIALIZING PORTA when they are being used as analog inputs. The user must ensure the bits in the TRISA register are CLRF PORTA ; Initialize PORTA by maintained set when using them as analog inputs. ; clearing output latches CLRF LATA ; Alternate method to Note: RA5 and RA<3:0> are configured as ; clear output data latches analog inputs on any Reset and are read BANKSEL ANCON1 ; Select bank with ANCON1 register MOVLW 00h ; Configure A/D as ‘0’. RA4 is configured as a digital input. MOVWF ANCON1 ; for digital inputs BANKSEL TRISA ; Select bank with TRISA register MOVLW 0BFh ; Value used to initialize ; data direction MOVWF TRISA ; Set RA<7, 5:0> as inputs, ; RA<6> as output  2009-2018 Microchip Technology Inc. DS30009960F-page 165

PIC18F87K22 FAMILY TABLE 12-1: PORTA FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RA0/AN0/ULPWU RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input is enabled. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. ULPWU 1 I ANA Ultra Low-Power Wake-up input. RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input is enabled. AN1 1 I ANA A/D Input Channel 1. Default input configuration on POR; does not affect digital output. RA2/AN2/VREF- RA2 0 O DIG LATA<2> data output; not affected by analog input. 1 I TTL PORTA<2> data input; disabled when analog functions are enabled. AN2 1 I ANA A/D Input Channel 2. Default input configuration on POR. VREF- 1 I ANA A/D and comparator low reference voltage input. RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input is enabled. AN3 1 I ANA A/D Input Channel 3. Default input configuration on POR. VREF+ 1 I ANA A/D and comparator high reference voltage input. RA4/T0CKI RA4 0 O DIG LATA<4> data output. 1 I ST PORTA<4> data input. Default configuration on POR. T0CKI x I ST Timer0 clock input. RA5/AN4/T1CKI/ RA5 0 O DIG LATA<5> data output; not affected by analog input. T3G/HLVDIN 1 I TTL PORTA<5> data input; disabled when analog input is enabled. AN4 1 I ANA A/D Input Channel 4. Default configuration on POR. T1CKI x I ST Timer1 clock input. T3G x I ST Timer3 external clock gate input. HLVDIN 1 I ANA High/Low-Voltage Detect (HLVD) external trip point input. OSC2/CLKO/RA6 OSC2 x O ANA Main oscillator feedback output connection (HS, XT and LP modes). CLKO x O DIG System cycle clock output (FOSC/4, EC and INTOSC modes). RA6 0 O DIG LATA<6> data output; disabled when FOSC2 Configuration bit is set. 1 I TTL PORTA<6> data input; disabled when FOSC2 Configuration bit is set. OSC1/CLKI/RA7 OSC1 x I ANA Main oscillator input connection (HS, XT and LP modes). CLKI x I ANA Main external clock source input (EC modes). RA7 0 O DIG LATA<7> data output; disabled when FOSC2 Configuration bit is set. 1 I TTL PORTA<7> data input; disabled when FOSC2 Configuration bit is set. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 LATA LATA7(1) LATA6(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘x’. DS30009960F-page 166  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 12.3 PORTB, TRISB and Four of the PORTB pins (RB<7:4>) have an LATB Registers interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur. Any RB<7:4> PORTB is an eight-bit wide, bidirectional port. The pin configured as an output will be excluded from the corresponding Data Direction and Output Latch registers interrupt-on-change comparison. are TRISB and LATB. All pins on PORTB are digital only. Comparisons with the input pins (of RB<7:4>) are made with the old value latched on the last read of EXAMPLE 12-2: INITIALIZING PORTB PORTB. The “mismatch” outputs of RB<7:4> are ORed CLRF PORTB ; Initialize PORTB by together to generate the RB Port Change Interrupt with ; clearing output Flag bit, RBIF (INTCON<0>). ; data latches This interrupt can wake the device from CLRF LATB ; Alternate method power-managed modes. To clear the interrupt in the ; to clear output Interrupt Service Routine: ; data latches MOVLW 0CFh ; Value used to a) Any read or write of PORTB (except with the ; initialize data MOVFF (ANY), PORTB instruction). This will ; direction end the mismatch condition. MOVWF TRISB ; Set RB<3:0> as inputs b) Wait one instruction cycle (such as executing a ; RB<5:4> as outputs ; RB<7:6> as inputs NOP instruction). c) Clear flag bit, RBIF. Each of the PORTB pins has a weak internal pull-up. A A mismatch condition will continue to set flag bit, RBIF. single control bit can turn on all the pull-ups. This is Reading PORTB will end the mismatch condition and performed by clearing bit, RBPU (INTCON2<7>). The allow flag bit, RBIF, to be cleared after one TCY delay. weak pull-up is automatically turned off when the port The interrupt-on-change feature is recommended for pin is configured as an output. The pull-ups are wake-up on key depression operation and operations disabled on a Power-on Reset. where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. The RB<3:2> pins are multiplexed as CTMU edge inputs. RB5 has an additional function for Timer3 and Timer1. It can be configured for Timer3 clock input or Timer1 external clock gate input. TABLE 12-3: PORTB FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RB0/INT0/FLT0 RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. INT0 1 I ST External Interrupt 0 input. FLT0 x I ST Enhanced PWM Fault input for ECCPx. RB1/INT1 RB1 0 O DIG LATB<1> data output. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. INT1 1 I ST External Interrupt 1 input. RB2/INT2/CTED1 RB2 0 O DIG LATB<2> data output. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. INT2 1 I ST External Interrupt 2 input. CTED1 x I ST CTMU Edge 1 input. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Extended Microcontroller mode.  2009-2018 Microchip Technology Inc. DS30009960F-page 167

PIC18F87K22 FAMILY TABLE 12-3: PORTB FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RB3/INT3/CTED2/ RB3 0 O DIG LATB<3> data output. ECCP2/P2A 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. INT3 1 I ST External Interrupt 3 input. CTED2 x I ST CTMU Edge 2 input. ECCP2(1) 0 O DIG ECCP2 compare output and ECCP2 PWM output. Takes priority over port data. 1 I ST ECCP2 capture input. P2A 0 O DIG ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RB4/KBI0 RB4 0 O DIG LATB<4> data output. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. KBI0 1 I TTL Interrupt-on-pin change. RB5/KBI1/T3CKI/ RB5 0 O DIG LATB<5> data output. T1G 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 I TTL Interrupt-on-pin change. T3CKI x I ST Timer3 clock input. T1G x I ST Timer1 external clock gate input. RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-pin change. PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operations. RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-pin change. PGD x O DIG Serial execution data output for ICSP and ICD operations. x I ST Serial execution data input for ICSP and ICD operations. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Extended Microcontroller mode. TABLE 12-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF ODCON1 SSP1OD CCP2OD CCP1OD — — — — SSP2OD Legend: Shaded cells are not used by PORTB. DS30009960F-page 168  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 12.4 PORTC, TRISC and When enabling peripheral functions, use care in defin- LATC Registers ing TRIS bits for each PORTC pin. Some peripherals can override the TRIS bit to make a pin an output or PORTC is an eight-bit wide, bidirectional port. The input. Consult the corresponding peripheral section for corresponding Data Direction and Output Latch registers the correct TRIS bit settings. are TRISC and LATC. Only PORTC pins, RC2 through Note: These pins are configured as digital inputs RC7, are digital only pins. on any device Reset. PORTC is multiplexed with ECCP, MSSP and EUSART peripheral functions (Table12-5). The pins have The contents of the TRISC register are affected by Schmitt Trigger input buffers. The pins for ECCP, SPI peripheral overrides. Reading TRISC always returns and EUSART are also configurable for open-drain out- the current contents, even though a peripheral device put whenever these functions are active. Open-drain may be overriding one or more of the pins. configuration is selected by setting the SPIOD, CCPxOD and U1OD control bits in the registers, EXAMPLE 12-3: INITIALIZING PORTC ODCON1 and ODCON3. CLRF PORTC ; Initialize PORTC by RC1 is normally configured as the default peripheral ; clearing output pin for the ECCP2 module. The assignment of ECCP2 ; data latches is controlled by Configuration bit, CCP2MX (default CLRF LATC ; Alternate method state, CCP2MX = 1). ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs TABLE 12-5: PORTC FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RC0/SOSCO/ RC0 0 O DIG LATC<0> data output. SCLKI/ 1 I ST PORTC<0> data input. SOSCO 1 I ST SOSC oscillator output. SCLKI 1 I ST Digital clock input; enabled when SOSC oscillator is disabled. RC1/SOSCI/ RC1 0 O DIG LATC<1> data output. ECCP2/P2A 1 I ST PORTC<1> data input. SOSCI x I ANA SOSC oscillator input. ECCP2(1) 0 O DIG ECCP2 compare output and ECCP2 PWM output; takes priority over port data. 1 I ST ECCP2 capture input. P2A 0 O DIG ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events; takes priority over port data. RC2/ECCP1/ RC2 0 O DIG LATC<2> data output. P1A 1 I ST PORTC<2> data input. ECCP1 0 O DIG ECCP1 compare output and ECCP1 PWM output; takes priority over port data. 1 I ST ECCP1 capture input. P1A 0 O DIG ECCP1 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events; takes priority over port data. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input, I2C = I2C/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.  2009-2018 Microchip Technology Inc. DS30009960F-page 169

PIC18F87K22 FAMILY TABLE 12-5: PORTC FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RC3/SCK1/ RC3 0 O DIG LATC<3> data output. SCL1 1 I ST PORTC<3> data input. SCK1 0 O DIG SPI clock output (MSSP module); takes priority over port data. 1 I ST SPI clock input (MSSP module). SCL1 0 O DIG I2C clock output (MSSP module); takes priority over port data. 1 I I2C I2C clock input (MSSP module); input type depends on module setting. RC4/SDI1/ RC4 0 O DIG LATC<4> data output. SDA1 1 I ST PORTC<4> data input. SDI1 I ST SPI data input (MSSP module). SDA1 1 O DIG I2C data output (MSSP module); takes priority over port data. 1 I I2C I2C data input (MSSP module); input type depends on module setting. RC5/SDO1 RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO1 0 O DIG SPI data output (MSSP module). RC6/TX1/CK1 RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX1 1 O DIG Synchronous serial data output (EUSART module); takes priority over port data. CK1 1 O DIG Synchronous serial data input (EUSART module); user must configure as an input. 1 I ST Synchronous serial clock input (EUSART module). RC7/RX1/DT1 RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX1 1 I ST Asynchronous serial receive data input (EUSART module). DT1 1 O DIG Synchronous serial data output (EUSART module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART module); user must configure as an input. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input, I2C = I2C/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 LATC LATC7 LATBC6 LATC5 LATCB4 LATC3 LATC2 LATC1 LATC0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 ODCON1 SSP1OD CCP2OD CCP1OD — — — — SSP2OD ODCON3 U2OD U1OD — — — — — CTMUDS Legend: Shaded cells are not used by PORTC. DS30009960F-page 170  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 12.5 PORTD, TRISD and PORTD can also be configured as an 8-bit wide micro- LATD Registers processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input PORTD is an 8-bit wide, bidirectional port. The buffers are TTL. For additional information, see corresponding Data Direction and Output Latch registers Section12.11 “Parallel Slave Port”. are TRISD and LATD. The PORTD also has the I2C and SPI functionality on All pins on PORTD are implemented with Schmitt RD4, RD5 and RD6. The pins for SPI are also Trigger input buffers. Each pin is individually configurable for open-drain output. Open-drain configurable as an input or output. configuration is selected by setting bit, SSP2OD (ODCON1<0>). Note: These pins are configured as digital inputs on any device Reset. RD0 has a CTMU functionality. RD1 has the functionality for the Timer5 clock input and Timer7 Each of the PORTD pins has a weak internal pull-up. A external clock gate input. single control bit can turn off all the pull-ups. This is performed by setting bit, RDPU (PADCFG1<7>). The EXAMPLE 12-4: INITIALIZING PORTD weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are CLRF PORTD ; Initialize PORTD by disabled on all device Resets. ; clearing output ; data latches On 80-pin devices, PORTD is multiplexed with the CLRF LATD ; Alternate method system bus as part of the external memory interface. ; to clear output The I/O port and other functions are only available ; data latches when the interface is disabled by setting the EBDIS bit MOVLW 0CFh ; Value used to (MEMCON<7>). When the interface is enabled, ; initialize data PORTD is the low-order byte of the multiplexed ; direction address/data bus (AD<7:0>). The TRISD bits are also MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs overridden. ; RD<7:6> as inputs TABLE 12-7: PORTD FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RD0/PSP0/ RD0 0 O DIG LATD<0> data output. AD0/CTPLS 1 I ST PORTD<0> data input. PSP0(1) x I/O TTL Parallel Slave Port data. AD0(2) x I/O TTL External Memory Address/Data 0. CTPLS x O DIG CTMU pulse generator output. RD1/PSP1/ RD1 0 O DIG LATD<1> data output. AD1/T5CKI/ 1 I ST PORTD<1> data input. T7G PSP1(1) x I/O TTL Parallel Slave Port data. AD1(2) x I/O TTL External Memory Address/Data 1. T5CKI x I ST Timer5 clock input. T7G x I ST Timer7 external clock gate input. RD2/PSP2/AD2 RD2 0 O DIG LATD<2> data output. 1 I ST PORTD<2> data input. PSP2(1) x I/O TTL Parallel Slave Port data. AD2(2) x I/O TTL External Memory Address/Data 2. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, I2C = I2C/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: The Parallel Slave Port (PSP) is available only in Microcontroller mode. 2: This feature is available only on PIC18F8XK22 devices.  2009-2018 Microchip Technology Inc. DS30009960F-page 171

PIC18F87K22 FAMILY TABLE 12-7: PORTD FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RD3/PSP3/AD3 RD3 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. PSP3(1) x I/O TTL Parallel Slave Port data. AD3(2) x I/O TTL External Memory Address/Data 3. RD4/PSP4/ RD4 0 O DIG LATD<4> data output. AD4/SDO2 1 I ST PORTD<4> data input. PSP4(1) x I/O TTL Parallel Slave Port data. AD4(2) x I/O TTL External Memory Address/Data 4. SDO2 0 P DOG SPI data output (MSSP module). RD5/PSP5/ RD5 0 O DIG LATD<5> data output. AD5/SDI2/ 1 I ST PORTD<5> data input. SDA2 PSP5(1) x I/O TTL Parallel Slave Port data. AD5(2) x I/O TTL External Memory Address/Data 5. SDI2 1 I ST SPI data input (MSSP module). SDA2 0 O I2C I2C data input (MSSP module). Input type depends on module setting. RD6/PSP6/ RD6 0 O DIG LATD<6> data output. AD6/SCK2/ 1 I ST PORTD<6> data input. SCL2 PSP6(1) x I/O TTL Parallel Slave Port data. AD6(2) x I/O TTL External Memory Address/Data 6. SCK2 0 O DIG SPI clock output (MSSP module); takes priority over port data. 1 I ST SPI clock input (MSSP module). SCL2 0 O DIG I2C clock output (MSSP module); takes priority over port data. 1 I I2C I2C clock input (MSSP module). Input type depends on module setting. RD7/PSP7/ RD7 0 O DIG LATD<7> data output. AD7/SS2 1 I ST PORTD<7> data input. PSP7(1) x I/O TTL Parallel Slave Port data. AD7(2) x I/O TTL External Memory Address/Data 7. SS2 1 I TTL Slave select input for MSSP module. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, I2C = I2C/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: The Parallel Slave Port (PSP) is available only in Microcontroller mode. 2: This feature is available only on PIC18F8XK22 devices. TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 PADCFG1 RDPU REPU RJPU(1) — — RTSECSEL1 RESECSEL0 — ODCON1 SSP1OD CCP2OD CCP1OD — — — — SSP2OD Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on PIC18F6XK22 devices, read as ‘0’. DS30009960F-page 172  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 12.6 PORTE, TRISE and On 80-pin devices, the multiplexing for the outputs of LATE Registers ECCP1 and ECCP3 is controlled by the ECCPMX Con- figuration bit. Clearing this bit re-assigns the P1B/P1C PORTE is an eight-bit wide, bidirectional port. The and P3B/P3C outputs to PORTH. corresponding Data Direction and Output Latch registers For devices operating in Microcontroller mode, the RE7 are TRISE and LATE. pin can be configured as the alternate peripheral pin for All pins on PORTE are implemented with Schmitt the ECCP2 module and Enhanced PWM Output 2A. Trigger input buffers. Each pin is individually This is done by clearing the CCP2MX Configuration bit. configurable as an input or output. The RE7 pin is also PORTE is also multiplexed with the Parallel Slave Port configurable for open-drain output when ECCP2 is address lines. RE1 and RE0 are multiplexed with the active on this pin. Open-drain configuration is selected control signals, WR and RD. by setting the CCP2OD control bit (ODCON1<6>) RE3 can also be configured as the Reference Clock Note: These pins are configured as digital inputs Output (REFO) from the system clock. For further on any device Reset. details, see Section3.7 “Reference Clock Output”. Each of the PORTE pins has a weak internal pull-up. A EXAMPLE 12-5: INITIALIZING PORTE single control bit can turn off all the pull-ups. This is performed by setting bit, REPU (PADCFG1<6>). The CLRF PORTE ; Initialize PORTE by ; clearing output weak pull-up is automatically turned off when the port ; data latches pin is configured as an output. The pull-ups are CLRF LATE ; Alternate method disabled on any device Reset. ; to clear output ; data latches PORTE is also multiplexed with Enhanced PWM MOVLW 03h ; Value used to Outputs, B and C for ECCP1 and ECCP3, for Outputs, ; initialize data B, C and D for ECCP2. For all devices, their default ; direction assignments are on PORTE<6:0>. MOVWF TRISE ; Set RE<1:0> as inputs ; RE<7:2> as outputs TABLE 12-9: PORTE FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RE0/RD/P2D RE0 0 O DIG LATE<0> data output. AD8 1 I ST PORTE<0> data input. RD x O DIG Parallel Slave Port read strobe pin. x I TTL Parallel Slave Port read pin. P2D 0 O — ECCP2 PWM Output D. May be configured for tri-state during Enhanced PWM shutdown events. AD8(2) x O DIG External memory interface, Data Bit 8 output. x I TTL External memory interface, Data Bit 8 input. RE1/P2C/WR/ RE1 0 O DIG LATE<1> data output. AD9 1 I ST PORTE<1> data input. P2C 0 O — ECCP2 PWM Output C. May be configured for tri-state during Enhanced PWM shutdown events. WR x O DIG Parallel Slave Port write strobe pin. x I TTL Parallel Slave Port write pin. AD9(2) x O DIG External memory interface, Data Bit 9 output. x I TTL External memory interface, Data Bit 9 input. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode. 2: This feature is only available on PIC18F8XKXX devices.  2009-2018 Microchip Technology Inc. DS30009960F-page 173

PIC18F87K22 FAMILY TABLE 12-9: PORTE FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RE2/CS/P2B/ RE2 0 O DIG LATE<2> data output. CCP10/AD10 1 I ST PORTE<2> data input. CS x I TTL Parallel Slave Port chip select. P2B 0 O — ECCP2 PWM Output B. May be configured for tri-state during Enhanced PWM shutdown events. CCP10 1 I/O ST Capture 10 input/Compare 10 output/PWM10 output. AD10(2) x O DIG External memory interface, Address/Data Bit 10 output. x I TTL External memory interface, Data Bit 10 input. RE3/P3C/ RE3 0 O DIG LATE<3> data output. CCP9/REFO/ 1 I ST PORTE<3> data input. AD11 P3C 0 O — ECCP3 PWM Output C. May be configured for tri-state during Enhanced PWM shutdown events. CCP9 0 O DIG CCP9 Compare/PWM output; takes priority over port data. 1 I ST CCP9 capture input. REFO x O DIG Reference output clock. AD11(2) x O DIG External memory interface, Address/Data Bit 11 output. x I TTL External memory interface, Data Bit 11 input. RE4/P3B/ RE4 0 O DIG LATE<4> data output. CCP8/AD12 1 I ST PORTE<4> data input. P3B 0 O — ECCP3 PWM Output B. May be configured for tri-state during Enhanced PWM shutdown events. CCP8 0 O DIG CCP8 compare/PWM output; takes priority over port data. 1 I ST CCP8 capture input. AD12(2) x O DIG External memory interface, Address/Data Bit 12 output. x I TTL External memory interface, Data Bit 12 input. RE5/P1C/ RE5 0 O DIG LATE<5> data output. CCP7/AD13 1 I ST PORTE<5> data input. P1C 0 O — ECCP1 PWM Output C. May be configured for tri-state during Enhanced PWM shutdown events. CCP7 0 O DIG CCP7 compare/PWM output; takes priority over port data. 1 I ST CCP7 capture input. AD13(2) x O DIG External memory interface, Address/Data Bit 13 output. x I TTL External memory interface, Data Bit 13 input. RE6/P1B/ RE6 0 O DIG LATE<6> data output. CCP6/AD14 1 I ST PORTE<6> data input. P1B 0 O — ECCP1 PWM Output B. May be configured for tri-state during Enhanced PWM shutdown events. CCP6 0 O DIG CCP6 compare/PWM output; takes priority over port data. 1 I ST CCP9 capture input. AD14(2) x O DIG External memory interface, Address/Data Bit 14 output. x I TTL External memory interface, Data Bit 14 input. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode. 2: This feature is only available on PIC18F8XKXX devices. DS30009960F-page 174  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 12-9: PORTE FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RE7/ECCP2/ RE7 0 O DIG LATE<7> data output. P2A/AD15 1 I ST PORTE<7> data input. ECCP2(1) 0 O DIG ECCP2 compare/PWM output; takes priority over port data. 1 I ST ECCP2 capture input. P2A 0 O — ECCP2 PWM Output A. May be configured for tri-state during Enhanced PWM shutdown event. AD15(2) x O DIG External memory interface, Address/Data Bit 15 output. x I TTL External memory interface, Data Bit 15 input. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode. 2: This feature is only available on PIC18F8XKXX devices. TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 PADCFG1 RDPU REPU RJPU(2) — — RTSECSEL1 RTSECSEL0 — ODCON1 SSP1OD CCP2OD CCP1OD — — — — SSP2OD ODCON2 CCP10OD(1) CCP9OD(1) CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on PIC18FX5K22 devices, read as ‘0’. 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.  2009-2018 Microchip Technology Inc. DS30009960F-page 175

PIC18F87K22 FAMILY 12.7 PORTF, LATF and TRISF Registers EXAMPLE 12-6: INITIALIZING PORTF CLRF PORTF ; Initialize PORTF by PORTF is a 7-bit wide, bidirectional port. The ; clearing output corresponding Data Direction and Output Latch registers ; data latches are TRISF and LATF. All pins on PORTF are CLRF LATF ; Alternate method implemented with Schmitt Trigger input buffers. Each pin ; to clear output is individually configurable as an input or output. ; data latches BANKSEL ANCON1 ; Select bank with ANCON1 register Pins, RF1 through RF6, may be used as comparator MOVLW 1Fh ; Make AN6, AN7 and AN5 digital inputs or outputs by setting the appropriate bits in the MOVWF ANCON1 ; CMCON register. To use RF<7:1> as digital inputs, it is MOVLW 0Fh ; Make AN8, AN9, AN10 and AN11 also necessary to turn off the comparators. digital MOVWF ANCON ; Set PORTF as digital I/O Note1: On device Resets, pins, RF<7:1>, are BANKSEL TRISF ; Select bank with TRISF register configured as analog inputs and are read MOVLW 0CEh ; Value used to as ‘0’. ; initialize data ; direction 2: To configure PORTF as a digital I/O, turn MOVWF TRISF ; Set RF3:RF1 as inputs off the comparators and clear ANCON1 ; RF5:RF4 as outputs and ANCON2 to digital. ; RF7:RF6 as inputs TABLE 12-11: PORTF FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RF1/AN6/C2OUT/ RF1 0 O DIG LATF<1> data output; not affected by analog input. CTDIN 1 I ST PORTF<1> data input; disabled when analog input is enabled. AN6 1 I ANA A/D Input Channel 6. Default configuration on POR. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. CTDIN 1 I ST CTMU pulse delay input. RF2/AN7/C1OUT RF2 0 O DIG LATF<2> data output; not affected by analog input. 1 I ST PORTF<2> data input; disabled when analog input is enabled. AN7 1 I ANA A/D Input Channel 7. Default configuration on POR. C1OUT 0 O DIG Comparator 1 output; takes priority over port data. RF3/AN8/C2INB/ RF3 0 O DIG LATF<3> data output; not affected by analog input. CTMUI 1 I ST PORTF<3> data input; disabled when analog input is enabled. AN8 1 I ANA A/D Input Channel 8 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. C2INB 1 I ANA Comparator 2 Input B. CTMUI x O — CTMU pulse generator charger for the C2INB comparator input. RF4/AN9/C2INA RF4 0 O DIG LATF<4> data output; not affected by analog input. 1 I ST PORTF<4> data input; disabled when analog input is enabled. AN9 1 I ANA A/D Input Channel 9 and Comparator C2- input. Default input configuration on POR; does not affect digital output. C2INA 1 I ANA Comparator 2 Input A. RF5/AN10/CVREF/ RF5 0 O DIG LATF<5> data output; not affected by analog input. Disabled when C1INB CVREF output is enabled. 1 I ST PORTF<5> data input; disabled when analog input is enabled. Disabled when CVREF output is enabled. AN10 1 I ANA A/D Input Channel 10 and Comparator C1+ input. Default input configuration on POR. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. C1INB 1 I ANA Comparator 1 Input B. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). DS30009960F-page 176  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 12-11: PORTF FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RF6/AN11/C1INA RF6 0 O DIG LATF<6> data output; not affected by analog input. 1 I ST PORTF<6> data input; disabled when analog input is enabled. AN11 1 I ANA A/D Input Channel 11 and Comparator C1- input. Default input configuration on POR; does not affect digital output. C1INA 1 I ANA Comparator 1 Input A. RF7/AN5/SS1 RF7 0 O DIG LATF<7> data output; not affected by analog input. 1 I ST PORTF<7> data input; disabled when analog input is enabled. AN5 1 I ANA A/D Input Channel 5. Default configuration on POR. SS1 1 I TTL Slave select input for MSSP module. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 12-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 — TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.  2009-2018 Microchip Technology Inc. DS30009960F-page 177

PIC18F87K22 FAMILY 12.8 PORTG, TRISG and When enabling peripheral functions, care should be LATG Registers taken in defining TRIS bits for each PORTG pin. Some peripherals override the TRIS bit to make a pin an PORTG is a 5-bit wide, bidirectional port. The output, while other peripherals override the TRIS bit to corresponding Data Direction and Output Latch registers make a pin an input. The user should refer to the are TRISG and LATG. corresponding peripheral section for the correct TRIS bit PORTG is multiplexed with the AUSART and CCP, settings. The pin override value is not loaded into the ECCP, Analog, Comparator, RTCC and Timer input TRIS register. This allows read-modify-write of the TRIS functions (Table12-13). When operating as I/O, all register without concern due to peripheral overrides. PORTG pins have Schmitt Trigger input buffers. The open-drain functionality for the CCPx and UART can be EXAMPLE 12-7: INITIALIZING PORTG configured using ODCONx. CLRF PORTG ; Initialize PORTG by ; clearing output ; data latches BCF CM1CON, CON ; disable ; comparator 1 CLRF LATG ; Alternate method ; to clear output ; data latches BANKSEL ANCON2 ; Select bank with ACON2 register MOVLW 0F0h ; make AN16 to AN19 ; digital MOVWF ANCON2 BANKSEL TRISG ; Select bank with TRISG register MOVLW 04h ; Value used to ; initialize data ; direction MOVWF TRISG ; Set RG1:RG0 as ; outputs ; RG2 as input ; RG4:RG3 as inputs TABLE 12-13: PORTG FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RG0/ECCP3/ RG0 0 O DIG LATG<0> data output. P3A 1 I ST PORTG<0> data input. ECCP3 0 O DIG ECCP3 compare output and ECCP3 PWM output; takes priority over port data. 1 I ST ECCP3 capture input. P3A 0 O — ECCP3 PWM Output A. May be configured for tri-state during Enhanced PWM shutdown events. RG1/TX2/CK2/ RG1 0 O DIG LATG<1> data output. AN19/C3OUT 1 I ST PORTG<1> data input. TX2 1 O DIG Synchronous serial data output (EUSART module); takes priority over port data. CK2 1 O DIG Synchronous serial data input (EUSART module); user must configure as an input. 1 I ST Synchronous serial clock input (EUSART module). AN19 1 I ANA A/D Input Channel 19. Default input configuration on POR. Does not affect digital output. C3OUT x O DIG Comparator 3 output. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). DS30009960F-page 178  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 12-13: PORTG FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RG2/RX2/DT2/ RG2 0 O DIG LATG<2> data output. AN18/C3INA 1 I ST PORTG<2> data input. RX2 1 I ST Asynchronous serial receive data input (EUSART module). DT2 1 O DIG Synchronous serial data output (EUSART module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART module); user must configure as an input. AN18 1 I ANA A/D Input Channel 18. Default input configuration on POR; does not affect digital output. C3INA x I ANA Comparator 3 Input A. RG3/CCP4/AN17/ RG3 0 O DIG LATG<3> data output. P3D/C3INB 1 I ST PORTG<3> data input. CCP4 0 O DIG CCP4 compare/PWM output; takes priority over port data. 1 I ST CCP4 capture input. AN17 1 I ANA A/D Input Channel 17. Default input configuration on POR; does not affect digital output. P3D 0 O — ECCP3 PWM Output D. May be configured for tri-state during Enhanced PWM. C3INB x I ANA Comparator 3 Input B. RG4/RTCC/ RG4 0 O DIG LATG<4> data output. T7CKI/T5G/ 1 I ST PORTG<4> data input. CCP5/AN16/ RTCC x O DIG RTCC output. P1D/C3INC T7CKI x I ST Timer7 clock input. T5G x I ST Timer5 external clock gate input. CCP5 0 O DIG CCP5 compare/PWM output; takes priority over port data. 1 I ST CCP5 capture input. AN16 1 I ANA A/D Input Channel 17. Default input configuration on POR; does not affect digital output. P1D 0 O — ECCP1 PWM Output D. May be configured for tri-state during Enhanced PWM. C3INC x I ANA Comparator 3 Input C. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 12-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTG — — RG5(2) RG4 RG3 RG2 RG1 RG0 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 ODCON1 SSP1OD CCP2OD CCP1OD — — — — SSP2OD ODCON2 CCP10OD(1) CCP9OD(1) CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD ODCON3 U2OD U1OD — — — — — CTMUDS Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: Unimplemented on PIC18FX5K22 devices, read as ‘0’. 2: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.  2009-2018 Microchip Technology Inc. DS30009960F-page 179

PIC18F87K22 FAMILY 12.9 PORTH, LATH and EXAMPLE 12-8: INITIALIZING PORTH TRISH Registers CLRF PORTH ; Initialize PORTH by ; clearing output Note: PORTH is available only on the 80-pin ; data latches devices. CLRF LATH ; Alternate method ; to clear output PORTH is an 8-bit wide, bidirectional I/O port. The ; data latches corresponding Data Direction and Output Latch registers BANKSEL ANCON2 ; Select bank with ANCON2 register MOVLW 0Fh ; Configure PORTH as are TRISH and LATH. MOVWF ANCON2 ; digital I/O All pins on PORTH are implemented with Schmitt MOVLW 0Fh ; Configure PORTH as Trigger input buffers. Each pin is individually MOVWF ANCON1 ; digital I/O configurable as an input or output. BANKSEL TRISH ; Select bank with TRISH register MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISH ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs ; RH7:RH6 as inputs TABLE 12-15: PORTH FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RH0/AN23/A16 RH0 0 O DIG LATH<0> data output. 1 I ST PORTH<0> data input. AN23 1 I ANA A/D Input Channel 23. Default input configuration on POR; does not affect digital input. A16 x O DIG External memory interface, Address Line 16; takes priority over port data. RH1/AN22/A17 RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. AN22 1 I ANA A/D Input Channel 22. Default input configuration on POR; does not affect digital input. A17 x O DIG External memory interface, Address Line 17; takes priority over port data. RH2/AN21/A18 RH2 0 O DIG LATH<2> data output. 1 I ST PORTH<2> data input. AN21 1 I ANA A/D Input Channel 21. Default input configuration on POR; does not affect digital input. A18 x O DIG External memory interface, Address Line 18; takes priority over port data. RH3/AN20/A19 RH3 0 O DIG LATH<3> data output. 1 I ST PORTH<3> data input. AN20 1 I ANA A/D Input Channel 20. Default input configuration on POR; does not affect digital input. A19 x O DIG External memory interface, Address Line 19; takes priority over port data. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). DS30009960F-page 180  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 12-15: PORTH FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RH4/CCP9/ RH4 0 O DIG LATH<4> data output. P3C/AN12/ 1 I ST PORTH<4> data input. C2INC CCP9 0 O DIG CCP9 compare/PWM output; takes priority over port data. 1 I ST CCP9 capture input. P3C 0 O — ECCP3 PWM Output C. May be configured for tri-state during Enhanced PWM. AN12 1 I ANA A/D Input Channel 12. Default input configuration on POR; does not affect digital input. C2INC x I ANA Comparator 2 Input C. RH5/CCP8/ RH5 0 O DIG LATH<5> data output. P3B/AN13/ 1 I ST PORTH<5> data input. C2IND CCP8 0 O DIG CCP8 compare/PWM output; takes priority over port data. 1 I ST CCP8 capture input. P3B 0 O — ECCP3 PWM Output B. May be configured for tri-state during Enhanced PWM. AN13 1 I ANA A/D Input Channel 13. Default input configuration on POR; does not affect digital input. C2IND x I ANA Comparator 2 Input D. RH6/CCP7/ RH6 0 O DIG LATH<6> data output. P1C/AN14/ 1 I ST PORTH<6> data input. C1INC CCP7 0 O DIG CCP7 compare/PWM output; takes priority over port data. 1 I ST CCP7 capture input. P1C 0 O — ECCP1 PWM Output C. May be configured for tri-state during Enhanced PWM. AN14 1 I ANA A/D Input Channel 14. Default input configuration on POR; does not affect digital input. C1INC x I ANA Comparator 1 Input C. RH7/CCP6/ RH7 0 O DIG LATH<7> data output. P1B/AN15 1 I ST PORTH<7> data input. CCP6 0 O DIG CCP6 compare/PWM output; takes priority over port data. 1 I ST CCP6 capture input. P1B 0 O — ECCP1 PWM Output B. May be configured for tri-state during Enhanced PWM. AN15 1 I ANA A/D Input Channel 15. Default input configuration on POR; does not affect digital input. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).  2009-2018 Microchip Technology Inc. DS30009960F-page 181

PIC18F87K22 FAMILY TABLE 12-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTH(1) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 LATH(1) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 TRISH(1) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 ODCON2 CCP10OD(2) CCP9OD(2) CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD Note 1: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. 2: Unimplemented on PIC18FX5K22 devices, read as ‘0’. 12.10 PORTJ, TRISJ and Each of the PORTJ pins has a weak internal pull-up. LATJ Registers The pull-ups are provided to keep the inputs at a known state for the external memory interface while powering Note: PORTJ is available only on 80-pin devices. up. A single control bit can turn off all the pull-ups. This is performed by clearing bit, RJPU (PADCFG1<5>). PORTJ is an 8-bit wide, bidirectional port. The The weak pull-up is automatically turned off when the corresponding Data Direction and Output Latch registers port pin is configured as an output. The pull-ups are are TRISJ and LATJ. disabled on any device Reset. All pins on PORTJ are implemented with Schmitt Trigger input buffers. Each pin is individually EXAMPLE 12-9: INITIALIZING PORTJ configurable as an input or output. CLRF PORTJ ; Initialize PORTJ by Note: These pins are configured as digital inputs ; clearing output latches CLRF LATJ ; Alternate method on any device Reset. ; to clear output latches When the external memory interface is enabled, all of MOVLW 0CFh ; Value used to the PORTJ pins function as control outputs for the inter- ; initialize data face. This occurs automatically when the interface is ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs enabled by clearing the EBDIS control bit ; RJ5:RJ4 as output (MEMCON<7>). The TRISJ bits are also overridden. ; RJ7:RJ6 as inputs DS30009960F-page 182  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 12-17: PORTJ FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RJ0/ALE RJ0 0 O DIG LATJ<0> data output. 1 I ST PORTJ<0> data input. ALE x O DIG External memory interface address latch enable control output; takes priority over digital I/O. RJ1/OE RJ1 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input. OE x O DIG External memory interface output enable control output; takes priority over digital I/O. RJ2/WRL RJ2 0 O DIG LATJ<2> data output. 1 I ST PORTJ<2> data input. WRL x O DIG External Memory Bus write low byte control; takes priority over digital I/O. RJ3/WRH RJ3 0 O DIG LATJ<3> data output. 1 I ST PORTJ<3> data input. WRH x O DIG External memory interface write high-byte control; takes priority over digital I/O. RJ4/BA0 RJ4 0 O DIG LATJ<4> data output. 1 I ST PORTJ<4> data input. BA0 x O DIG External Memory Interface Byte Address 0 control output; takes priority over digital I/O. RJ5/CE RJ5 0 O DIG LATJ<5> data output. 1 I ST PORTJ<5> data input. CE x O DIG External memory interface chip enable control output; takes priority over digital I/O. RJ6/LB RJ6 0 O DIG LATJ<6> data output. 1 I ST PORTJ<6> data input. LB x O DIG External memory interface lower byte enable control output; takes priority over digital I/O. RJ7/UB RJ7 0 O DIG LATJ<7> data output. 1 I ST PORTJ<7> data input. UB x O DIG External memory interface upper byte enable control output; takes priority over digital I/O. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 12-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTJ(1) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 LATJ(1) LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 TRISJ(1) TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 PADCFG1 RDPU REPU RJPU(1) — — RTSECSEL1 RTSECSEL0 — Legend: Shaded cells are not used by PORTJ. Note 1: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.  2009-2018 Microchip Technology Inc. DS30009960F-page 183

PIC18F87K22 FAMILY 12.11 Parallel Slave Port FIGURE 12-3: PORTD AND PORTE BLOCK DIAGRAM PORTD can function as an 8-bit-wide Parallel Slave (PARALLEL SLAVE PORT) Port (PSP), or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set. The port is asyn- chronously readable and writable by the external world Data Bus through the RD control input pin (RE0/P2D/RD/AD8) D Q and WR control input pin (RE1/P2C/WR/AD9). RDx WR LATD Pin(1) CK Note: The Parallel Slave Port is available only in or PORTD Microcontroller mode. Data Latch TTL The PSP can directly interface to an 8-bit micro- Q D processor data bus. The external microprocessor can read or write the PORTD latch as an eight-bit latch. RD PORTD ENEN TRIS Latch Setting bit, PSPMODE, enables port pin, RE0/P2D/RD/AD8, to be the RD input, RE1/P2C/WR/AD9 to be the WR input and RD LATD RE2/P2B/CCP10/CS/AD10 to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (= 111). One Bit of PORTD A write to the PSP occurs when both the CS and WR Set Interrupt Flag lines are first detected low and ends when either are PSPIF (PIR1<7>) detected high. The PSPIF and IBF flag bits (PIR1<7> and PSPCON<7>, respectively) are set when the write ends. A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit (PSPCON<6>) is set. If the user Read TTL RD writes new data to PORTD to set OBF, the data is immediately read out, but the OBF bit is not set. Chip Select TTL CS When either the CS or RD line is detected high, the PORTD pins return to the input state and the PSPIF bit Write is set. User applications should wait for PSPIF to be set TTL WR before servicing the PSP. When this happens, the IBF Note: The I/O pin has protection diodes to VDD and VSS. and OBF bits can be polled and the appropriate action taken. The timing for the control signals in Write and Read modes is shown in Figure12-4 and Figure12-5, respectively. DS30009960F-page 184  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 12-5: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word had not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ FIGURE 12-4: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF  2009-2018 Microchip Technology Inc. DS30009960F-page 185

PIC18F87K22 FAMILY FIGURE 12-5: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 12-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 PSPCON IBF OBF IBOV PSPMODE — — — — INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP PMD1 PSPMD CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD EMBDM Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. DS30009960F-page 186  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 13.0 TIMER0 MODULE The T0CON register (Register13-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software-selectable operation as a timer or Figure13-1 provides a simplified block diagram of the counter in both 8-bit or 16-bit modes Timer0 module in 8-bit mode. Figure13-2 provides a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 13-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin input edge 0 = Internal clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = Timer0 prescaler is not assigned; Timer0 clock input bypasses prescaler 0 = Timer0 prescaler is assigned; Timer0 clock input comes from prescaler output bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value  2009-2018 Microchip Technology Inc. DS30009960F-page 187

PIC18F87K22 FAMILY 13.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter. The timer/counter. mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on 13.2 Timer0 Reads and Writes in 16-Bit every clock by default unless a different prescaler value Mode is selected (see Section13.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited TMR0H is not the actual high byte of Timer0 in 16-bit for the following two instruction cycles. The user can mode. It is actually a buffered version of the real high work around this by writing an adjusted value to the byte of Timer0, which is not directly readable nor TMR0 register. writable (see Figure13-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of The Counter mode is selected by setting the T0CS bit TMR0L. This provides the ability to read all 16 bits of (= 1). In this mode, Timer0 increments either on every Timer0 without having to verify that the read of the high rising edge or falling edge of the T0CKI pin. The and low byte was valid, due to a rollover between incrementing edge is determined by the Timer0 Source successive reads of the high and low byte. Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external Similarly, a write to the high byte of Timer0 must also clock input are discussed below. take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a An external clock source can be used to drive Timer0; write occurs to TMR0L. This allows all 16 bits of Timer0 however, it must meet certain requirements to ensure to be updated at once. that the external clock can be synchronized with the FIGURE 13-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI Pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) T0CS 3 8 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 13-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with TMR0 Set 1 Internal TMR0L High Byte TMR0IF T0CKI Pin ProPgrreasmcamlearble 0 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS30009960F-page 188  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 13.3 Prescaler 13.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. The prescaler assignment is fully under software Its value is set by the PSA and T0PS<2:0> bits control and can be changed “on-the-fly” during program (T0CON<3:0>), which determine the prescaler execution. assignment and prescale ratio. 13.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Tim- er0 module. When it is assigned, prescale values from The TMR0 interrupt is generated when the TMR0 1:2 through 1:256, in power-of-two increments, are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (for example, CLRF TMR0, clearing the TMR0IE bit (INTCON<5>). Before re- MOVWF TMR0, BSF TMR0) clear the prescaler count. enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine (ISR). Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0L Timer0 Register Low Byte TMR0H Timer0 Register High Byte INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.  2009-2018 Microchip Technology Inc. DS30009960F-page 189

PIC18F87K22 FAMILY 14.0 TIMER1 MODULE Figure14-1 displays a simplified block diagram of the Timer1 module. The Timer1 timer/counter module incorporates these The Timer1 oscillator can also be used as a low-power features: clock source for the microcontroller in power-managed • Software-selectable operation as a 16-bit timer or operation. The Timer1 can also work on the SOSC counter oscillator. • Readable and writable eight-bit registers (TMR1H Timer1 is controlled through the T1CON Control and TMR1L) register (Register14-1). It also contains the Secondary • Selectable clock source (internal or external) with Oscillator Enable bit (SOSCEN). Timer1 can be device clock or SOSC oscillator internal options enabled or disabled by setting or clearing control bit, • Interrupt-on-overflow TMR1ON (T1CON<0>). • Reset on ECCP Special Event Trigger The FOSC clock source should not be used with the • Timer with gated control ECCP capture/compare features. If the timer will be used with the capture or compare features, always select one of the other timer clocking options. REGISTER 14-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 10 = Timer1 clock source is either from a pin or oscillator, depending on the SOSCEN bit: SOSCEN = 0: External clock from the T1CKI pin (on the rising edge). SOSCEN = 1: Depending on the SOSCSEL Configuration bit, the clock source is either a crystal oscillator on the SOSCI/SOSCO pins or an internal clock from the SCLKI pin. 01 = Timer1 clock source is the system clock (FOSC)(1) 00 = Timer1 clock source is the instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 SOSCEN: SOSC Oscillator Enable bit 1 = SOSC is enabled and available for Timer1 0 = SOSC is disabled for Timer1 The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit TMR1CS<1:0> = 10: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS<1:0> = 0x: This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1x. bit 1 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features. DS30009960F-page 190  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 14-1: T1CON: TIMER1 CONTROL REGISTER (CONTINUED) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features.  2009-2018 Microchip Technology Inc. DS30009960F-page 191

PIC18F87K22 FAMILY 14.1 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), displayed in Register14-2, is used to control the Tim- er1 gate. REGISTER 14-2: T1GCON: TIMER1 GATE CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0 TMR1GE T1GPOL T1GTM T1GSPM T1GGO/T1DONE T1GVAL T1GSS1 T1GSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored. If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single Pulse Mode bit 1 = Timer1 Gate Single Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single Pulse mode is disabled bit 3 T1GGO/T1DONE: Timer1 Gate Single Pulse Acquisition Status bit 1 = Timer1 gate single pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L; unaffected by Timer1 Gate Enable (TMR1GE) bit. bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 11 = Comparator 2 output 10 = Comparator 1 output 01 = TMR2 to match PR2 output 00 = Timer1 gate pin Note 1: Programming the T1GCON prior to T1CON is recommended. DS30009960F-page 192  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 14.2 Timer1 Operation 14.3.2 EXTERNAL CLOCK SOURCE The Timer1 module is an 8 or 16-bit incrementing When the external clock source is selected, the Timer1 counter that is accessed through the TMR1H:TMR1L module may work as a timer or a counter. register pair. When enabled to count, Timer1 is incremented on the When used with an internal clock source, the module is rising edge of the external clock input, T1CKI. Either of a timer and increments on every instruction cycle. these external clock sources can be synchronized to the When used with an external clock source, the module microcontroller system clock or they can run can be used as either a timer or counter. It increments asynchronously. on every selected edge of the external source. When used as a timer with a clock oscillator, an Timer1 is enabled by configuring the TMR1ON and external, 32.768 kHz crystal can be used in conjunction TMR1GE bits in the T1CON and T1GCON registers, with the dedicated internal oscillator circuit. respectively. Note: In Counter mode, a falling edge must be When SOSC is selected as Crystal mode (by registered by the counter prior to the first SOSCSEL), the RC1/SOSCI/ECCP2/P2A and RC0/ incrementing rising edge after any one or SOSCO/SCLKI pins become inputs. This means the more of the following conditions: values of TRISC<1:0> are ignored and the pins are • Timer1 enabled after POR Reset read as ‘0’. • Write to TMR1H or TMR1L • Timer1 is disabled 14.3 Clock Source Selection • Timer1 is disabled (TMR1ON = 0) When T1CKI is high, Timer1 is enabled The TMR1CS<1:0> and SOSCEN bits of the T1CON (TMR1ON = 1) when T1CKI is low. register are used to select the clock source for Timer1. Register14-1 displays the clock source selections. 14.3.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of FOSC, as determined by the Timer1 prescaler. TABLE 14-1: TIMER1 CLOCK SOURCE SELECTION TMR1CS1 TMR1CS0 SOSCEN Clock Source 0 1 x Clock Source (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 0 0 External Clock on T1CKI Pin 1 0 1 Oscillator Circuit on SOSCI/SOSCO Pins  2009-2018 Microchip Technology Inc. DS30009960F-page 193

PIC18F87K22 FAMILY FIGURE 14-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 T1GSPM From TMR2 01 T1G_IN 0 Data Bus Match PR2 0 T1GVAL D Q FOruotmpu Ctomparator 1 10 SAicnqg.l eC Ponutlrsoel 1 Q1 EN RT1DGCON D Q 1 From Comparator 2 Output 11 CK Q T1GGO/T1DONE Interrupt Set TMR1ON R det TMR1GIF T1GPOL T1GTM TMR1GE Set Flag bit, TMR1ON TMR1IF, on Overflow TMR1(2) EN Synchronized TMR1H TMR1L T1CLK 0 Clock Input Q D 1 TMR1CS<1:0> T1SYNC SOSCO/SCLKI OUT(4) SOSC 10 Prescaler Synchronize(3) 1 1, 2, 4, 8 det SOSCI EN FOSC 2 0 Internal 01 Clock T1CKPS<1:0> T1CON.SOSCEN T3CON.SSOOSSCCGEON IFnOteSrCn/a4l 00 IFnOteSrCn/a2l Sleep Input SCS<1:0> = 01 Clock Clock (1) T1CKI Note 1: ST Buffer is a high-speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronization does not operate while in Sleep. 4: The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits. DS30009960F-page 194  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 14.4 Timer1 16-Bit Read/Write Mode FIGURE 14-2: EXTERNAL COMPONENTS FOR THE SOSC Timer1 can be configured for 16-bit reads and writes. LOW-POWER OSCILLATOR When the RD16 control bit (T1CON<1>) is set, the address for TMR1H is mapped to a buffer register for C1 PIC18F87K22 the high byte of Timer1. A read from TMR1L loads the 12 pF contents of the high byte of Timer1 into the Timer1 High SOSCI Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without XTAL having to determine whether a read of the high byte, 32.768 kHz followed by a read of the low byte, has become invalid due to a rollover between reads. SOSCO C2 A write to the high byte of Timer1 must also take place 12 pF through the TMR1H Buffer register. The Timer1 high byte is updated with the contents of TMR1H when a Note: See the Notes with Table14-2 for additional information about capacitor selection. write occurs to TMR1L. This allows a user to write all 16 bits at once to both the high and low bytes of Timer1. TABLE 14-2: CAPACITOR SELECTION FOR The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take THE TIMER place through the Timer1 High Byte Buffer register. OSCILLATOR(2,3,4,5) Writes to TMR1H do not clear the Timer1 prescaler; the Oscillator prescaler is only cleared on writes to TMR1L. Freq. C1 C2 Type LP 32kHz 12pF(1) 12pF(1) 14.5 SOSC Oscillator An on-chip crystal oscillator circuit is incorporated Note1: Microchip suggests these values as a between pins, SOSCI (input) and SOSCO (amplifier starting point in validating the oscillator output). It is enabled by any peripheral that requests it. circuit. There are eight ways the SOSC can be enabled: if the 2: Higher capacitance increases the stabil- SOSC is selected as the source by any of the odd ity of the oscillator, but also increases the timers, which is done by each respective SOSCEN bit start-up time. (TxCON<3>), if the SOSC is selected as the RTCC 3: Since each resonator/crystal has its own source by the RTCOSC Configuration bit (CON- characteristics, the user should consult FIG3L<1>), if the SOSC is selected as the CPU clock the resonator/crystal manufacturer for source by the SCS bits (OSCCON<1:0>) or if the appropriate values of external SOSCGO bit is set (OSCCON2<3>). The SOSCGO bit components. is used to warm up the SOSC so that it is ready before any peripheral requests it. The oscillator is a low-power 4: Capacitor values are for design guid- circuit, rated for 32 kHz crystals. It will continue to run ance only. Values listed would be typical during all power-managed modes. The circuit for a typi- of a CL = 10 pF rated crystal when cal low-power oscillator is depicted in Figure14-2. SOSCSEL<1:0> = 11. Table14-2 provides the capacitor selection for the 5: Incorrect capacitance value may result in SOSC oscillator. a frequency not meeting the crystal The user must provide a software time delay to ensure manufacturer’s tolerance specification. proper start-up of the SOSC oscillator. The SOSC crystal oscillator drive level is determined based on the SOSCSEL<1:0> (CONFIG1L<4:3>) Con- figuration bits. The Higher Drive Level mode, SOSCSEL<1:0>= 11, is intended to drive a wide variety of 32.768 kHz crystals with a variety of Capacitance Load (CL) ratings.  2009-2018 Microchip Technology Inc. DS30009960F-page 195

PIC18F87K22 FAMILY The Lower Drive Level mode is highly optimized for If a high-speed circuit must be located near the extremely low-power consumption. It is not intended to oscillator, it may help to have a grounded guard ring drive all types of 32.768 kHz crystals. In the Low Drive around the oscillator circuit. The guard, as displayed in Level mode, the crystal oscillator circuit may not work Figure14-3, could be used on a single-sided PCB or in correctly if excessively large discrete capacitors are addition to a ground plane. (Examples of a high-speed placed on the SOSCO and SOSCI pins. This mode is circuit include the ECCP1 pin, in Output Compare or designed to work only with discrete capacitances of PWM mode, or the primary oscillator using the approximately 3pF-10pF on each pin. OSC2pin.) Crystal manufacturers usually specify a CL (Capaci- FIGURE 14-3: OSCILLATOR CIRCUIT tance Load) rating for their crystals. This value is related to, but not necessarily the same as, the values WITH GROUNDED that should be used for C1 and C2 in Figure14-2. GUARD RING For more details on selecting the optimum C1 and C2 VDD for a given crystal, see the crystal manufacturer’s appli- cations information. The optimum value depends, in VSS part, on the amount of parasitic capacitance in the circuit, which is often unknown. For that reason, it is OSC1 highly recommended that thorough testing and valida- OSC2 tion of the oscillator be performed after values have been selected. 14.5.1 USING SOSC AS A RC0 CLOCKSOURCE RC1 The SOSC oscillator is also available as a clock source in power-managed modes. By setting the System Clock Select bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, RC2 the device switches to SEC_RUN mode, and both the Note: Not drawn to scale. CPU and peripherals are clocked from the SOSC oscil- lator. If the IDLEN bit (OSCCON<7>) is cleared and a In the Low Drive Level mode, SOSCSEL<1:0> = 01, it is SLEEP instruction is executed, the device enters critical that RC2 I/O pin signals be kept away from the SEC_IDLE mode. Additional details are available in oscillator circuit. Configuring RC2 as a digital output, and Section4.0 “Power-Managed Modes”. toggling it, can potentially disturb the oscillator circuit, Whenever the SOSC oscillator is providing the clock even with a relatively good PCB layout. If possible, either source, the SOSC System Clock Status flag, leave RC2 unused or use it as an input pin with a slew SOSCRUN (OSCCON2<6>), is set. This can be used rate limited signal source. If RC2 must be used as a to determine the controller’s current clocking mode. It digital output, it may be necessary to use the Higher can also indicate the clock source currently being used Drive Level Oscillator mode (SOSCSEL<1:0> =11) with by the Fail-Safe Clock Monitor (FSCM). many PCB layouts. If the Clock Monitor is enabled and the SOSC oscillator Even in the Higher Drive Level mode, careful layout fails while providing the clock, polling the SOCSRUN procedures should still be followed when designing the bit will indicate whether the clock is being provided by oscillator circuit. the SOSC oscillator or another source. In addition to dV/dt induced noise considerations, it is important to ensure that the circuit board is clean. Even 14.5.2 SOSC OSCILLATOR LAYOUT a very small amount of conductive soldering flux CONSIDERATIONS residue can cause PCB leakage currents that can The SOSC oscillator circuit draws very little power overwhelm the oscillator circuit. during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing 14.6 Timer1 Interrupt signals in close proximity. This is especially true when the oscillator is configured for extremely Low-Power The TMR1 register pair (TMR1H:TMR1L) increments mode, SOSCSEL<1:0> (CONFIG1L<4:3>) = 01. from 0000h to FFFFh and rolls over to 0000h. The Tim- The oscillator circuit, displayed in Figure14-2, should er1 interrupt, if enabled, is generated on overflow which be located as close as possible to the microcontroller. is latched in interrupt flag bit, TMR1IF (PIR1<0>). This There should be no circuits passing within the oscillator interrupt can be enabled or disabled by setting or clear- circuit boundaries other than VSS or VDD. ing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). DS30009960F-page 196  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 14.7 Resetting Timer1 Using the ECCP 14.8.1 TIMER1 GATE COUNT ENABLE Special Event Trigger The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity If ECCP modules are configured to use Timer1 and to of the Timer1 Gate Enable mode is configured using generate a Special Event Trigger in Compare mode the T1GPOL bit (T1GCON<6>). (CCPxM<3:0>=1011), this signal will reset Timer1. The trigger from ECCP2 will also start an A/D conversion, if When Timer1 Gate Enable mode is enabled, Timer1 the A/D module is enabled. (For more information, see will increment on the rising edge of the Timer1 clock Section20.3.4 “Special Event Trigger”.) source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the To take advantage of this feature, the module must be current count. See Figure14-4 for timing details. configured as either a timer or a synchronous counter. When used this way, the CCPRxH:CCPRxL register TABLE 14-3: TIMER1 GATE ENABLE pair effectively becomes a period register for Timer1. SELECTIONS If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. T1CLK(†) T1GPOL T1G Pin Timer1 (T1GCON<6>) Operation In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take  0 0 Counts precedence.  0 1 Holds Count  1 0 Holds Count Note: The Special Event Trigger from the ECCPx module will only clear the TMR1  1 1 Counts register’s content, but not set the TMR1IF † The clock on which TMR1 is running. For more interrupt flag bit (PIR1<0>). information, see Figure14-1. 14.8 Timer1 Gate Note: The CCP and ECCP modules use Timers, 1 through 8, for some modes. The assign- Timer1 can be configured to count freely or the count can ment of a particular timer to a CCP/ECCP be enabled and disabled using the Timer1 gate circuitry. module is determined by the Timer to CCP This is also referred to as Timer1 gate count enable. enable bits in the CCPTMRSx registers. Timer1 gate can also be driven by multiple selectable For more details, see Register19-2, sources. Register19-3 and Register20-2.  2009-2018 Microchip Technology Inc. DS30009960F-page 197

PIC18F87K22 FAMILY FIGURE 14-4: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 14.8.2 TIMER1 GATE SOURCE occurs, a low-to-high pulse will automatically be gener- SELECTION ated and internally supplied to the Timer1 gate circuitry. The pulse will remain high for one instruction cycle and The Timer1 gate source can be selected from one of will return back to a low state until the next match. four sources. Source selection is controlled by the T1GSSx (T1GCON<1:0>) bits (see Table14-4). The T1GPOL bit determines when the Timer1 counter increments based on this pulse. When T1GPOL=1, TABLE 14-4: TIMER1 GATE SOURCES Timer1 increments for a single instruction cycle follow- ing a TMR2 match with PR2. When T1GPOL=0, Tim- T1GSS<1:0> Timer1 Gate Source er1 increments continuously, except for the cycle following the match, when the gate signal goes from 00 Timer1 Gate Pin low-to-high. 01 TMR2 to Match PR2 (TMR2 increments to match PR2) 14.8.2.3 Comparator 1 Output Gate 10 Comparator 1 Output Operation (comparator logic high output) The output of Comparator 1 can be internally supplied 11 Comparator 2 Output to the Timer1 gate circuitry. After setting up (comparator logic high output) Comparator1 with the CM1CON register, Timer1 will The polarity for each available source is also selectable, increment depending on the transitions of the controlled by the T1GPOL bit (T1GCON<6>). CMP1OUT (CMSTAT<5>) bit. 14.8.2.1 T1G Pin Gate Operation 14.8.2.4 Comparator 2 Output Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 The output of Comparator 2 can be internally supplied gate circuitry. to the Timer1 gate circuitry. After setting up Comparator2 with the CM2CON register, Timer1 will 14.8.2.2 Timer2 Match Gate Operation increment depending on the transitions of the CMP2OUT (CMSTAT<6>) bit. The TMR2 register will increment until it matches the value in the PR2 register. On the very next increment cycle, TMR2 will be reset to 00h. When this Reset DS30009960F-page 198  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 14.8.3 TIMER1 GATE TOGGLE MODE The T1GVAL bit (T1GCON<2>) indicates when the Toggled mode is active and the timer is counting. When Timer1 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer1 The Timer1 Gate Toggle mode is enabled by setting the gate signal, as opposed to the duration of a single level T1GTM bit (T1GCON<5>). When T1GTM is cleared, pulse. the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. (For timing details, see Figure14-5.) FIGURE 14-5: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8  2009-2018 Microchip Technology Inc. DS30009960F-page 199

PIC18F87K22 FAMILY 14.8.4 TIMER1 GATE SINGLE PULSE Clearing the T1GSPM bit of the T1GCON register will MODE also clear the T1GGO/T1DONE bit. (For timing details, see Figure14-6.) When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Simultaneously enabling the Toggle and Single Pulse Gate Single Pulse mode is enabled by setting the modes will permit both sections to work together. This T1GSPM bit (T1GCON<4>) and the T1GGO/T1DONE allows the cycle times on the Timer1 gate source to be bit (T1GCON<3>). The Timer1 will be fully enabled on measured. (For timing details, see Figure14-7.) the next incrementing edge. 14.8.5 TIMER1 GATE VALUE STATUS On the next trailing edge of the pulse, the T1GGO/ T1DONE bit will automatically be cleared. No other When the Timer1 gate value status is utilized, it is gate events will be allowed to increment Timer1 until possible to read the most current level of the gate the T1GGO/T1DONE bit is once again set in software. control value. The value is stored in the T1GVAL bit (T1GCON<2>). This bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). FIGURE 14-6: TIMER1 GATE SINGLE PULSE MODE TMR1GE T1GPOL T1GSPM Cleared by Hardware on T1GGO/ Set by Software Falling Edge of T1GVAL T1DONE Counting Enabled on Rising Edge of T1G T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 Cleared by RTCCIF Cleared by Software Set by Hardware on Software Falling Edge of T1GVAL DS30009960F-page 200  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 14-7: TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM Cleared by Hardware on T1GGO/ Set by Software Falling Edge of T1GVAL T1DONE Counting Enabled on Rising Edge of T1G T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 Set by Hardware on Cleared by RTCCIF Cleared by Software Falling Edge of T1GVAL Software TABLE 14-5: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP TMR1L Timer1 Register Low Byte TMR1H Timer1 Register High Byte T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 T1DONE OSCCON2 — SOSCRUN — — SOSCGO — MFIOFS MFIOSEL PMD1 PSPMD CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD EMBDM Legend: Shaded cells are not used by the Timer1 module. Note 1: Unimplemented on 32-Kbyte devices (PIC18FX5K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 201

PIC18F87K22 FAMILY 15.0 TIMER2 MODULE The value of TMR2 is compared to that of the Period reg- ister, PR2, on each clock cycle. When the two values The Timer2 module incorporates the following features: match, the comparator generates a match signal as the • Eight-bit Timer and Period registers (TMR2 and timer output. This signal also resets the value of TMR2 PR2, respectively) to 00h on the next cycle and drives the output counter/ postscaler. (See Section15.2 “Timer2 Interrupt”.) • Both registers are readable and writable • Software programmable prescaler The TMR2 and PR2 registers are both directly readable (1:1, 1:4 and 1:16) and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. • Software programmable postscaler Both the prescaler and postscaler counters are cleared (1:1 through 1:16) on the following events: • Interrupt on TMR2 to PR2 match • A write to the TMR2 register • Optional use as the shift clock for the MSSP modules • A write to the T2CON register • Any device Reset – Power-on Reset (POR), This module is controlled through the T2CON register MCLR Reset, Watchdog Timer Reset (WDTR) or (Register15-1) that enables or disables the timer, and Brown-out Reset (BOR) configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), TMR2 is not cleared when T2CON is written. to minimize power consumption. Note: The CCP and ECCP modules use Timers, A simplified block diagram of the module is shown in 1 through 8, for some modes. The assign- Figure15-1. ment of a particular timer to a CCP/ECCP module is determined by the Timer to CCP 15.1 Timer2 Operation enable bits in the CCPTMRSx registers. For more details, see Register20-2, In normal operation, TMR2 is incremented from 00h on Register19-2 and Register19-3. each clock (FOSC/4). A four-bit counter/prescaler on the clock input gives the prescale options of direct input, divide-by-4 or divide-by-16. These are selected by the prescaler control bits, T2CKPS<1:0> (T2CON<1:0>). REGISTER 15-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 DS30009960F-page 202  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 15.2 Timer2 Interrupt 15.3 Timer2 Output Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2 to PR2 match) provides the ECCP modules, where it is used as a time base for the input for the 4-bit output counter/postscaler. This operations in PWM mode. counter generates the TMR2 match interrupt flag, which Timer2 can optionally be used as the shift clock source is latched in TMR2IF (PIR1<1>). The interrupt is enabled for the MSSP modules operating in SPI mode. by setting the TMR2 Match Interrupt Enable bit, TMR2IE Additional information is provided in Section21.0 (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”. A range of 16 postscaler options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). FIGURE 15-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set TMR2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSPx) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP TMR2 Timer2 Register T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 PR2 Timer2 Period Register PMD1 PSPMD CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD EMBDM Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.  2009-2018 Microchip Technology Inc. DS30009960F-page 203

PIC18F87K22 FAMILY 16.0 TIMER3/5/7 MODULES A simplified block diagram of the Timer3/5/7 module is shown in Figure16-1. The Timer3/5/7 timer/counter modules incorporate The Timer3/5/7 module is controlled through the these features: TxCON register (Register16-1). It also selects the • Software-selectable operation as a 16-bit timer or clock source options for the ECCP modules. (For more counter information, see Section20.1.1 “ECCP Module and • Readable and writable eight-bit registers (TMRxH Timer Resources”.) and TMRxL) The FOSC clock source should not be used with the • Selectable clock source (internal or external) with ECCP capture/compare features. If the timer will be device clock or SOSC oscillator internal options used with the capture or compare features, always • Interrupt-on-overflow select one of the other timer clocking options. • Module Reset on ECCP Special Event Trigger Timer7 is unimplemented for devices with a program memory of 32 Kbytes (PIC18FX5K22). Note: Throughout this section, generic references are used for register and bit names that are the same – except for an ‘x’ variable that indicates the item’s association with the Timer3, Timer5 or Timer7 module. For example, the control register is named TxCON and refers to T3CON, T5CON and T7CON. DS30009960F-page 204  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 16-1: TxCON: TIMERx CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMRxCS1 TMRxCS0 TxCKPS1 TxCKPS0 SOSCEN TxSYNC RD16 TMRxON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TMRxCS<1:0>: Timerx Clock Source Select bits 10 = Timer1 clock source depends on the SOSCEN bit: SOSCEN = 0: External clock from the T1CKI pin (on the rising edge). SOSCEN = 1: Depending on the SOSCSEL fuses, either a crystal oscillator on the SOSCI/SOSCO pins or an external clock from the SCLKI pin. 01 = Timerx clock source is the system clock (FOSC)(1) 00 = Timerx clock source is the instruction clock (FOSC/4) bit 5-4 TxCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 SOSCEN: SOSC Oscillator Enable bit 1 = SOSC/SCLKI are enabled for Timerx (based on the SOSCSEL fuses) 0 = SOSC/SCLKI are disabled for Timerx and TxCKI is enabled bit 2 TxSYNC: Timerx External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMRxCS<1:0> = 10: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMRxCS<1:0> = 0x: This bit is ignored; Timer3 uses the internal clock. bit 1 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timerx in one 16-bit operation 0 = Enables register read/write of Timerx in two eight-bit operations bit 0 TMRxON: Timerx On bit 1 = Enables Timerx 0 = Stops Timerx Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features.  2009-2018 Microchip Technology Inc. DS30009960F-page 205

PIC18F87K22 FAMILY 16.1 Timer3/5/7 Gate Control Register The Timer3/5/7 Gate Control register (TxGCON), provided in Register 14-2, is used to control the Timerx gate. REGISTER 16-2: TxGCON: TIMERx GATE CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0 TMRxGE TxGPOL TxGTM TxGSPM TxGGO/TxDONE TxGVAL TxGSS1 TxGSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMRxGE: Timerx Gate Enable bit If TMRxON = 0: This bit is ignored. If TMRxON = 1: 1 = Timerx counting is controlled by the Timerx gate function 0 = Timerx counts regardless of Timerx gate function bit 6 TxGPOL: Timerx Gate Polarity bit 1 = Timerx gate is active-high (Timerx counts when gate is high) 0 = Timerx gate is active-low (Timerx counts when gate is low) bit 5 TxGTM: Timerx Gate Toggle Mode bit 1 = Timerx Gate Toggle mode is enabled. 0 = Timerx Gate Toggle mode is disabled and toggle flip-flop is cleared Timerx gate flip-flop toggles on every rising edge. bit 4 TxGSPM: Timerx Gate Single Pulse Mode bit 1 = Timerx Gate Single Pulse mode is enabled and is controlling Timerx gate 0 = Timerx Gate Single Pulse mode is disabled bit 3 TxGGO/TxDONE: Timerx Gate Single Pulse Acquisition Status bit 1 = Timerx gate single pulse acquisition is ready, waiting for an edge 0 = Timerx gate single pulse acquisition has completed or has not been started This bit is automatically cleared when TxGSPM is cleared. bit 2 TxGVAL: Timerx Gate Current State bit Indicates the current state of the Timerx gate that could be provided to TMRxH:TMRxL. Unaffected by the Timerx Gate Enable (TMRxGE) bit. bit 1-0 TxGSS<1:0>: Timerx Gate Source Select bits 11 = Comparator 2 output 10 = Comparator 1 output 01 = TMR(x+1) to match PR(x+1) output(2) 00 = Timer1 gate pin The Watchdog Timer oscillator is turned on if TMRxGE = 1, regardless of the state of TMRxON. Note 1: Programming the TxGCON prior to TxCON is recommended. 2: Timer(x+1) will be Timer4/6/8 for Timerx (Timer3/5/7), respectively. DS30009960F-page 206  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 16-3: OSCCON2: OSCILLATOR CONTROL REGISTER 2 U-0 R-0 U-0 U-0 R/W-0 U-0 R-x R/W-0 — SOSCRUN — — SOSCGO — MFIOFS MFIOSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from a secondary SOSC 0 = System clock comes from an oscillator other than SOSC bit 5-4 Unimplemented: Read as ‘0’ bit 3 SOSCGO: Oscillator Start Control bit 1 = Oscillator is running even if no other sources are requesting it 0 = Oscillator is shut off if no other sources are requesting it (When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect.) bit 2 Unimplemented: Read as ‘0’ bit 1 MFIOFS: MF-INTOSC Frequency Stable bit 1 = MF-INTOSC is stable 0 = MF-INTOSC is not stable bit 0 MFIOSEL: MF-INTOSC Select bit 1 = MF-INTOSC is used in place of HF-INTOSC frequencies of 500kHz, 250kHz and 31.25kHz 0 = MF-INTOSC is not used  2009-2018 Microchip Technology Inc. DS30009960F-page 207

PIC18F87K22 FAMILY 16.2 Timer3/5/7 Operation The operating mode is determined by the clock select bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits Timer3, Timer5 and Timer7 can operate in these are cleared (= 00), Timer3/5/7 increments on every inter- modes: nal instruction cycle (FOSC/4). When TMRxCSx = 01, the • Timer Timer3/5/7 clock source is the system clock (FOSC), and • Synchronous Counter when it is ‘10’, Timer3/5/7 works as a counter from the external clock from the TxCKI pin (on the rising edge after • Asynchronous Counter the first falling edge) or the SOSC oscillator. • Timer with Gated Control FIGURE 16-1: TIMER3/5/7 BLOCK DIAGRAM T3GSS<1:0> T3G 00 T3GSPM From TMR4 01 T3G_IN 0 Data Bus Match PR4 0 T3GVAL D Q FOruotmpu Ctomparator 1 10 SAicnqg.l eC Ponutlrsoel 1 Q1 EN RT3DGCON D Q 1 From Comparator 2 Output 11 CK Q T3GGO/T3DONE Interrupt Set TMR3ON R det TMR3GIF T3GPOL T3GTM TMR3GE Set Flag bit TMR3ON TMR3IF on Overflow TMR3(2) EN Synchronized TMR3H TMR3L T3CLK 0 Clock Input Q D 1 TMR3CS<1:0> T3SYNC SOSCO/SCLKI OUT(4) SOSC Prescaler Synchronize(3) 1 1, 2, 4, 8 det SOSCI EN 10 2 0 FOSC T3CKPS<1:0> T1CON.SOSCEN Internal 01 T3CON.SSOOSSCCGEON Clock IFnOteSrCn/a2l Sleep Input SCS<1:0> = 01 FOSC/4 Clock Internal 00 (1) Clock T3CKI Note 1: ST Buffer is high-speed type when using T3CKI. 2: Timer3 registers increment on rising edge. 3: Synchronization does not operate while in Sleep. 4: The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits. DS30009960F-page 208  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 16.3 Timer3/5/7 16-Bit Read/Write Mode 16.4 Using the SOSC Oscillator as the Timer3/5/7 Clock Source Timer3/5/7 can be configured for 16-bit reads and writes (see Figure16.3). When the RD16 control bit The SOSC internal oscillator may be used as the clock (TxCON<1>) is set, the address for TMRxH is mapped source for Timer3/5/7. The SOSC oscillator is enabled to a buffer register for the high byte of Timer3/5/7. A by any peripheral that requests it. There are eight ways read from TMRxL will load the contents of the high byte the SOSC can be enabled: if the SOSC is selected as of Timer3/5/7 into the Timerx High Byte Buffer register. the source by any of the odd timers, which is done by This provides users with the ability to accurately read each respective SOSCEN bit (TxCON<3>), if the all 16 bits of Timer3/5/7 without having to determine SOSC is selected as the RTCC source by the RTCOSC whether a read of the high byte, followed by a read of Configuration bit (CONFIG3L<1>), if the SOSC is the low byte, has become invalid due to a rollover selected as the CPU clock source by the SCS bits between reads. (OSCCON<1:0>) or if the SOSCGO bit is set (OSC- A write to the high byte of Timer3/5/7 must also take CON2<3>). The SOSCGO bit is used to warm up the place through the TMRxH Buffer register. The Timer3/ SOSC so that it is ready before any peripheral requests 5/7 high byte is updated with the contents of TMRxH it. To use it as the Timer3/5/7 clock source, the when a write occurs to TMRxL. This allows users to TMRxCS bit must also be set. As previously noted, this write all 16 bits to both the high and low bytes of Tim- also configures Timer3/5/7 to increment on every rising er3/5/7 at once. edge of the oscillator source. The high byte of Timer3/5/7 is not directly readable or The SOSC oscillator is described in Section14.5 writable in this mode. All reads and writes must take “SOSC Oscillator”. place through the Timerx High Byte Buffer register. Writes to TMRxH do not clear the Timer3/5/7 prescaler. The prescaler is only cleared on writes to TMRxL.  2009-2018 Microchip Technology Inc. DS30009960F-page 209

PIC18F87K22 FAMILY 16.5 Timer3/5/7 Gates When Timerx Gate Enable mode is enabled, Timer3/5/7 will increment on the rising edge of the Timer3/5/7 clock Timer3/5/7 can be configured to count freely or the count source. When Timerx Gate Enable mode is disabled, no can be enabled and disabled using the Timer3/5/7 gate incrementing will occur and Timer3/5/7 will hold the circuitry. This is also referred to as the Timer3/5/7 gate current count. See Figure16-2 for timing details. count enable. The Timer3/5/7 gate can also be driven by multiple TABLE 16-1: TIMER3/5/7 GATE ENABLE selectable sources. SELECTIONS 16.5.1 TIMER3/5/7 GATE COUNT ENABLE TxCLK(†) TxGPOL TxG Pin Timerx (TxGCON<6>) Operation The Timerx Gate Enable mode is enabled by setting the TMRxGE bit (TxGCON<7>). The polarity of the  0 0 Counts Timerx Gate Enable mode is configured using the  0 1 Holds Count TxGPOL bit (TxGCON<6>).  1 0 Holds Count  1 1 Counts † The clock on which TMR3/5/7 is running. For more information, see TxCLK in Figure16-1. FIGURE 16-2: TIMER3/5/7 GATE COUNT ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer3/5/7 N N + 1 N + 2 N + 3 N + 4 DS30009960F-page 210  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 16.5.2 TIMER3/5/7 GATE SOURCE cycle following a TMR(x+1) match with PR(x+1). When SELECTION TxGPOL = 0, Timerx increments continuously, except for the cycle following the match, when the gate signal The Timer3/5/7 gate source can be selected from one goes from low-to-high. of four different sources. Source selection is controlled by the TxGSS<1:0> bits (TxGCON<1:0>). The polarity 16.5.2.3 Comparator 1 Output Gate for each available source is also selectable and is Operation controlled by the TxGPOL bit (TxGCON <6>). The output of Comparator 1 can be internally supplied TABLE 16-2: TIMER3/5/7 GATE SOURCES to the Timerx gate circuitry. After setting up Comparator1 with the CM1CON register, Timerx will TxGSS<1:0> Timerx Gate Source increment depending on the transitions of the CMP1OUT (CMSTAT<5>) bit. 00 Timerx Gate Pin 01 TMR(x+1) to Match PR(x+1) 16.5.2.4 Comparator 2 Output Gate (TMR(x+1) increments to match Operation PR(x+1)) The output of Comparator 2 can be internally supplied 10 Comparator 1 Output to the Timerx gate circuitry. After setting up (comparator logic high output) Comparator2 with the CM2CON register, Timerx will 11 Comparator 2 Output increment depending on the transitions of the (comparator logic high output) CMP2OUT (CMSTAT<6>) bit. 16.5.2.1 TxG Pin Gate Operation 16.5.3 TIMER3/5/7 GATE TOGGLE MODE The TxG pin is one source for Timer3/5/7 gate control. It When Timer3/5/7 Gate Toggle mode is enabled, it is can be used to supply an external source to the Timerx possible to measure the full cycle length of a Timer3/5/7 gate circuitry. gate signal, as opposed to the duration of a single level pulse. 16.5.2.2 Timer4/6/8 Match Gate Operation The Timerx gate source is routed through a flip-flop that The TMR(x+1) register will increment until it matches the changes state on every incrementing edge of the value in the PR(x+1) register. On the very next increment signal. (For timing details, see Figure16-3.) cycle, TMR2 will be reset to 00h. When this Reset The TxGVAL bit will indicate when the Toggled mode is occurs, a low-to-high pulse will automatically be gener- active and the timer is counting. ated and internally supplied to the Timerx gate circuitry. The pulse will remain high for one instruction cycle and Timer3/5/7 Gate Toggle mode is enabled by setting the will return back to a low state until the next match. TxGTM bit (TxGCON<5>). When the TxGTM bit is cleared, the flip-flop is cleared and held clear. This is Depending on TxGPOL, Timerx increments differently necessary in order to control which edge is measured. when TMR(x+1) matches PR(x+1). When TxGPOL=1, Timerx increments for a single instruction FIGURE 16-3: TIMER3/5/7 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxG_IN TxCKI TxGVAL Timer3/5/7 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8  2009-2018 Microchip Technology Inc. DS30009960F-page 211

PIC18F87K22 FAMILY 16.5.4 TIMER3/5/7 GATE SINGLE PULSE No other gate events will be allowed to increment Tim- MODE er3/5/7 until the TxGGO/TxDONE bit is once again set in software. When Timer3/5/7 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Tim- Clearing the TxGSPM bit also will clear the TxGGO/ er3/5/7 Gate Single Pulse mode is first enabled by set- TxDONE bit. (For timing details, see Figure16-4.) ting the TxGSPM bit (TxGCON<4>). Next, the TxGGO/ Simultaneously enabling the Toggle mode and the TxDONE bit (TxGCON<3>) must be set. Single Pulse mode will permit both sections to work The Timer3/5/7 will be fully enabled on the next incre- together. This allows the cycle times on the Timer3/5/7 menting edge. On the next trailing edge of the pulse, gate source to be measured. (For timing details, see the TxGGO/TxDONE bit will automatically be cleared. Figure16-5.) FIGURE 16-4: TIMER3/5/7 GATE SINGLE PULSE MODE TMRxGE TxGPOL TxGSPM Cleared by Hardware on TxGGO/ Set by Software Falling Edge of TxGVAL TxDONE Counting Enabled on Rising Edge of TxG TxG_IN TxCKI TxGVAL Timer3/5/7 N N + 1 N + 2 Cleared by TMRxGIF Cleared by Software Set by Hardware on Software Falling Edge of TxGVAL DS30009960F-page 212  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 16-5: TIMER3/5/7 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM Cleared by Hardware on TxGGO/ Set by Software Falling Edge of TxGVAL TxDONE Counting Enabled on Rising Edge of TxG TxG_IN TxCKI TxGVAL Timer3/5/7 N N + 1 N + 2 N + 3 N + 4 Set by Hardware on Cleared by TMRxGIF Cleared by Software Falling Edge of TxGVAL Software 16.5.5 TIMER3/5/7 GATE VALUE STATUS 16.5.6 TIMER3/5/7 GATE EVENT INTERRUPT When Timer3/5/7 gate value status is utilized, it is possible to read the most current level of the gate con- When the Timer3/5/7 gate event interrupt is enabled, it trol value. The value is stored in the TxGVAL bit is possible to generate an interrupt upon the comple- (TxGCON<2>). The TxGVAL bit is valid even when the tion of a gate event. When the falling edge of TxGVAL Timer3/5/7 gate is not enabled (TMRxGE bit is occurs, the TMRxGIF flag bit in the PIRx register will be cleared). set. If the TMRxGIE bit in the PIEx register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Tim- er3/5/7 gate is not enabled (TMRxGE bit is cleared).  2009-2018 Microchip Technology Inc. DS30009960F-page 213

PIC18F87K22 FAMILY 16.6 Timer3/5/7 Interrupt 16.7 Resetting Timer3/5/7 Using the ECCP Special Event Trigger The TMRx register pair (TMRxH:TMRxL) increments from 0000h to FFFFh and overflows to 0000h. The If the ECCP modules are configured to use Timerx and Timerx interrupt, if enabled, is generated on overflow to generate a Special Event Trigger in Compare mode and is latched in the interrupt flag bit, TMRxIF. (CCPxM<3:0>=1011), this signal will reset Timerx. The Table16-3 gives each module’s flag bit. trigger from ECCP2 will also start an A/D conversion if TABLE 16-3: TIMER3/5/7 INTERRUPT the A/D module is enabled. (For more information, see FLAG BITS Section20.3.4 “Special Event Trigger”.) The module must be configured as either a timer or Timer Module Flag Bit synchronous counter to take advantage of this feature. 3 PIR2<1> When used this way, the CCPRxH:CCPRxL register 5 PIR5<1> pair effectively becomes a Period register for Timerx. 7 PIR5<3> If Timerx is running in Asynchronous Counter mode, the Reset operation may not work. This interrupt can be enabled or disabled by setting or In the event that a write to Timerx coincides with a clearing the TMRxIE bit, respectively. Table16-4 gives Special Event Trigger from an ECCP module, the write each module’s enable bit. will take precedence. TABLE 16-4: TIMER3/5/7 INTERRUPT Note: The Special Event Triggers from the ENABLE BITS ECCPx module will only clear the TMR3 register’s content, but not set the TMR3IF Timer Module Flag Bit interrupt flag bit (PIR1<0>). 3 PIE2<1> 5 PIE5<1> Note: The CCP and ECCP modules use Timers, 7 PIE5<3> 1 through 8, for some modes. The assign- ment of a particular timer to a CCP/ECCP module is determined by the Timer to CCP enable bits in the CCPTMRSx registers. For more details, see Register19-2, Register19-3 and Register20-2 DS30009960F-page 214  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 16-5: REGISTERS ASSOCIATED WITH TIMER3/5/7 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR5 TMR7GIF(1) TMR12IF(1) TMR10IF(1) TMR8IF TMR7IF(1) TMR6IF TMR5IF TMR4IF IPR5 TMR7GIP(1) TMR12IP(1) TMR10IP(1) TMR8IP TMR7IP(1) TMR6IP TMR5IP TMR4IP PIE5 TMR7GIE(1) TMR12IE(1) TMR10IE(1) TMR8IE TMR7IE(1) TMR6IE TMR5IE TMR4IE PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE2 OSCFIE — SSP2IE BCL2IE BCL1IE HLVDIE TMR3IE TMR3GIE PIR2 OSCFIF — SSP2IF BCL2IF BCL1IF HLVDIF TMR3IF TMR3GIF IPR2 OSCFIP — SSP2IP BCL2IP BCL1IP HLVDIP TMR3IP TMR3GIP TMR3H Timer3 Register High Byte TMR3L Timer3 Register Low Byte T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS1 T3GSS0 T3DONE T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16 TMR3ON TMR5H Timer5 Register High Byte TMR5L Timer5 Register Low Byte T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/ T5GVAL T5GSS1 T5GSS0 T5DONE T5CON TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 SOSCEN T5SYNC RD16 TMR5ON TMR7H(1) Timer7 Register High Byte TMR7L(1) Timer7 Register Low Byte T7GCON(1) TMR7GE T7GPOL T7GTM T7GSPM T7GGO/ T7GVAL T7GSS1 T7GSS0 T7DONE T7CON(1) TMR7CS1 TMR7CS0 T7CKPS1 T7CKPS0 SOSCEN T7SYNC RD16 TMR7ON OSCCON2 — SOSCRUN — — SOSCGO — MFIOFS MFIOSEL PMD1 PSPMD CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD EMBMD PMD2 TMR10MD(1) TMR8MD TMR7MD(1) TMR6MD TMR5MD CMP3MD CMP2MD CMP2MD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3/5/7 module. Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 215

PIC18F87K22 FAMILY 17.0 TIMER4/6/8/10/12 MODULES 17.1 Timer4/6/8/10/12 Operation The Timer4/6/8/10/12 timer modules have the following Timer4/6/8/10/12 can be used as the PWM time base features: for the PWM mode of the ECCP modules. The TMRx registers are readable and writable, and are cleared on • Eight-bit Timer register (TMRx) any device Reset. The input clock (FOSC/4) has a • Eight-bit Period register (PRx) prescale option of 1:1, 1:4 or 1:16, selected by control • Readable and writable (all registers) bits, TxCKPS<1:0> (TxCON<1:0>). The match output • Software programmable prescaler (1:1, 1:4, 1:16) of TMRx goes through a four-bit postscaler (that gives • Software programmable postscaler (1:1 to 1:16) a 1:1 to 1:16 inclusive scaling) to generate a TMRx interrupt, latched in the flag bit, TMRxIF. Table17-1 • Interrupt on TMRx match of PRx shows each module’s flag bit. Timer10 and Timer12 are unimplemented for devices with a program memory of 32 Kbytes (PIC18FX5K22). TABLE 17-1: TIMER4/6/8/10/12 FLAG BITS Note: Throughout this section, generic references Timer Flag Bit Timer Flag Bit are used for register and bit names that are the Module PIR5<x> Module PIR5<x> same, except for an ‘x’ variable that indicates 4 0 10 5 the item’s association with the Timer4, Timer6, 6 2 12 6 Timer8, Timer10 or Timer12 module. For example, the control register is named TxCON 8 4 and refers to T4CON, T6CON, T8CON, T10CON and T12CON. The interrupt can be enabled or disabled by setting or The Timer4/6/8/10/12 modules have a control register, clearing the Timerx Interrupt Enable bit (TMRxIE), which is shown in Register17-1. Timer4/6/8/10/12 can shown in Table17-2. be shut off by clearing control bit, TMRxON (TxCON<2>), TABLE 17-2: TIMER4/6/8/10/12 INTERRUPT to minimize power consumption. The prescaler and post- ENABLE BITS scaler selection of Timer4/6/8/10/12 are also controlled by this register. Figure17-1 is a simplified block diagram Timer Flag Bit Timer Flag Bit of the Timer4/6/8/10/12 modules. Module PIE5<x> Module PIE5<x> 4 0 10 5 6 2 12 6 8 4 The prescaler and postscaler counters are cleared when any of the following occurs: • A write to the TMRx register • A write to the TxCON register • Any device Reset – Power-on Reset (POR), MCLR Reset, Watchdog Timer Reset (WDTR) or Brown-out Reset (BOR) A TMRx is not cleared when a TxCON is written. Note: The CCP and ECCP modules use Timers, 1 through 8, for some modes. The assign- ment of a particular timer to a CCP/ECCP module is determined by the Timer to CCP enable bits in the CCPTMRSx registers. For more details, see Register19-2, Register19-3 and Register20-2. DS30009960F-page 216  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 17-1: TxCON: TIMERx CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 TMRxON TxCKPS1 TxCKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 TxOUTPS<3:0>: Timerx Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMRxON: Timerx On bit 1 = Timerx is on 0 = Timerx is off bit 1-0 TxCKPS<1:0>: Timerx Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 17.2 Timer4/6/8/10/12 Interrupt 17.3 Output of TMRx The Timer4/6/8/10/12 modules have eight-bit Period The outputs of TMRx (before the postscaler) are used registers, PRx, that are both readable and writable. only as a PWM time base for the ECCP modules. They Timer4/6/8/10/12 increment from 00h until they match are not used as baud rate clocks for the MSSP PR4/6/8/10/12 and then reset to 00h on the next modules as is the Timer2 output. increment cycle. The PRx registers are initialized to FFh upon Reset. FIGURE 17-1: TIMER4 BLOCK DIAGRAM 4 1:1 to 1:16 TxOUTPS<3:0> Set TMRxIF Postscaler 2 TxCKPS<1:0> TMRx Output (to PWM) TMRx/PRx Reset Match 1:1, 1:4, 1:16 FOSC/4 TMRx Comparator PRx Prescaler 8 8 8 Internal Data Bus  2009-2018 Microchip Technology Inc. DS30009960F-page 217

PIC18F87K22 FAMILY TABLE 17-3: REGISTERS ASSOCIATED WITH TIMER4/6/8/10/12 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPR5 TMR7GIP(1) TMR12IP(1) TMR10IP(1) TMR8IP TMR7IP(1) TMR6IP TMR5IP TMR4IP PIR5 TMR7GIF(1) TMR12IF(1) TMR10IF(1) TMR8IF TMR7IF(1) TMR6IF TMR5IF TMR4IF PIE5 TMR7GIE(1) TMR12IE(1) TMR10IE(1) TMR8IE TMR7IE(1) TMR6IE TMR5IE TMR4IE TMR4 Timer4 Register T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 PR4 Timer4 Period Register TMR6 Timer6 Register T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 PR6 Timer6 Period Register TMR8 Timer8 Register T8CON — T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 TMR8ON T8CKPS1 T8CKPS0 PR8 Timer8 Period Register TMR10(1) Timer10 Register T10CON(1) — T10OUTPS3 T10OUTPS2 T10OUTPS1 T10OUTPS0 TMR10ON T10CKPS1 T10CKPS0 PR10(1) Timer10 Period Register TMR12(1) Timer12 Register T12CON(1) — T12OUTPS3 T12OUTPS2 T12OUTPS1 T12OUTPS0 TMR12ON T12CKPS1 T12CKPS0 PR12(1) Timer12 Period Register PMD1 PSPMD CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD EMBMD PMD2 TMR10MD(1) TMR8MD TMR7MD(1) TMR6MD TMR5MD CMP3MD CMP2MD CMP2MD PMD3 CCP10MD(1) CCP9MD(1) CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD TMR12MD(1) Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4/6/8/10/12 module. Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). DS30009960F-page 218  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 18.0 REAL-TIME CLOCK AND The RTCC module is intended for applications where CALENDAR (RTCC) accurate time must be maintained for extended period with minimum to no intervention from the CPU. The The key features of the Real-Time Clock and Calendar module is optimized for low-power usage in order to (RTCC) module are: provide extended battery life while keeping track of time. • Time: hours, minutes and seconds The module is a 100-year clock and calendar with auto- • Twenty-four hour format (military time) matic leap year detection. The range of the clock is • Calendar: weekday, date, month and year from 00:00:00 (midnight) on January 1, 2000 to • Alarm configurable 23:59:59 on December 31, 2099. • Year range: 2000 to 2099 Hours are measured in 24-hour (military time) format. • Leap year correction The clock provides a granularity of one second with • BCD format for compact firmware half-second visibility to the user. • Optimized for low-power operation • User calibration with auto-adjust • Calibration range: 2.64 seconds error per month • Requirements: external 32.768 kHz clock crystal • Alarm pulse or seconds clock output on RTCC pin FIGURE 18-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain 32.768 kHz Input from SOSC Oscillator RTCCFG RTCC Prescalers Internal RC ALRMRPT YEAR (LF-INTOSC) 0.5s MTHDY RTCC Timer RTCVALx WKDYHR Alarm Event MINSEC Comparator ALMTHDY Compare Registers ALRMVALx ALWDHR with Masks ALMINSEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE  2009-2018 Microchip Technology Inc. DS30009960F-page 219

PIC18F87K22 FAMILY 18.1 RTCC MODULE REGISTERS Alarm Value Registers The RTCC module registers are divided into the • ALRMVALH following categories: • ALRMVALL Both registers access the following registers: RTCC Control Registers - ALRMMNTH • RTCCFG - ALRMDAY • RTCCAL - ALRMWD • PADCFG1 - ALRMHR • ALRMCFG - ALRMMIN • ALRMRPT - ALRMSEC Note: The RTCVALH and RTCVALL registers RTCC Value Registers can be accessed through RTCRPT<1:0> (RTCCFG<1:0>). ALRMVALH and • RTCVALH ALRMVALL can be accessed through • RTCVALL ALRMPTR<1:0> (ALRMCFG<1:0>). Both registers access the following registers: - YEAR - MONTH - DAY - WEEKDAY - HOUR - MINUTE - SECOND DS30009960F-page 220  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 18.1.1 RTCC CONTROL REGISTERS REGISTER 18-1: RTCCFG: RTCC CONFIGURATION REGISTER(1) R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 RTCEN(2) — RTCWREN(4) RTCSYNC HALFSEC(3) RTCOE RTCPTR1 RTCPTR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 RTCWREN: RTCC Value Registers Write Enable bit(4) 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 4 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALRMRPT registers can change while reading if a rollover ripple results in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL and ALCFGRPT registers can be read without concern over a rollover ripple bit 3 HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 2 RTCOE: RTCC Output Enable bit 1 = RTCC clock output is enabled 0 = RTCC clock output is disabled bit 1-0 RTCPTR<1:0>: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers. The RTCPTR<1:0> value decrements on every read or write of RTCVALH<15:8> until it reaches ‘00’. RTCVALH: 00 = Minutes 01 = Weekday 10 = Month 11 = Reserved RTCVALL: 00 = Seconds 01 = Hours 10 = Day 11 = Year Note 1: The RTCCFG register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register. 4: RTCWREN can only be written with the unlock sequence (see Example18-1).  2009-2018 Microchip Technology Inc. DS30009960F-page 221

PIC18F87K22 FAMILY REGISTER 18-2: RTCCAL: RTCC CALIBRATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 =Maximum positive adjustment. Adds 508 RTC clock pulses every minute. . . . 00000001 =Minimum positive adjustment. Adds four RTC clock pulses every minute. 00000000 =No adjustment 11111111 =Minimum negative adjustment. Subtracts four RTC clock pulses every minute. . . . 10000000 =Maximum negative adjustment. Subtracts 512 RTC clock pulses every minute. REGISTER 18-3: PADCFG1: PAD CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 RDPU REPU RJPU(2) — — RTSECSEL1(1) RTSECSEL0(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RDPU: PORTD Pull-up Enable bit 1 = PORTD pull-up resistors are enabled by individual port latch values 0 = All PORTD pull-up resistors are disabled bit 6 REPU: PORTE Pull-up Enable bit 1 = PORTE pull-up resistors are enabled by individual port latch values 0 = All PORTE pull-up resistors are disabled bit 5 RJPU: PORTJ Pull-up Enable bit(2) 1 = PORTJ pull-up resistors are enabled by individual port latch values 0 = All PORTJ pull-up resistors are disabled bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1) 11 = Reserved; do not use 10 = RTCC source clock is selected for the RTCC pin (pin can be LF-INTOSC or SOSC, depending on the RTCOSC (CONFIG3L<1>) bit setting) 01 = RTCC seconds clock is selected for the RTCC pin 00 = RTCC alarm pulse is selected for the RTCC pin bit 0 Unimplemented: Read as ‘0’ Note 1: To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set. 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. DS30009960F-page 222  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 18-4: ALRMCFG: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0>=00 and CHIME=0) 0 = Alarm is disabled bit 6 CHIME: Chime Enable bit 1 = Chime is enabled; ALRMPTR<1:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ALRMPTR<1:0> bits stop once they reach 00h bit 5-2 AMASK<3:0>: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every four years) 101x = Reserved – Do not use 11xx = Reserved – Do not use bit 1-0 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVALH: 00 =ALRMMIN 01 =ALRMWD 10 =ALRMMNTH 11 =Unimplemented ALRMVALL: 00 =ALRMSEC 01 =ALRMHR 10 =ALRMDAY 11 =Unimplemented  2009-2018 Microchip Technology Inc. DS30009960F-page 223

PIC18F87K22 FAMILY REGISTER 18-5: ALRMRPT: ALARM REPEAT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times . . . 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME=1. 18.1.2 RTCVALH AND RTCVALL REGISTER MAPPINGS REGISTER 18-6: RESERVED REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 Unimplemented: Read as ‘0’ REGISTER 18-7: YEAR: YEAR VALUE REGISTER(1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to the YEAR register is only allowed when RTCWREN=1. DS30009960F-page 224  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 18-8: MONTH: MONTH VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 3-0 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 18-9: DAY: DAY VALUE REGISTER(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 18-10: WEEKDAY: WEEKDAY VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. Note 1: A write to this register is only allowed when RTCWREN=1.  2009-2018 Microchip Technology Inc. DS30009960F-page 225

PIC18F87K22 FAMILY REGISTER 18-11: HOUR: HOUR VALUE REGISTER(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 18-12: MINUTE: MINUTE VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. REGISTER 18-13: SECOND: SECOND VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9. DS30009960F-page 226  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 18.1.3 ALRMVALH AND ALRMVALL REGISTER MAPPINGS REGISTER 18-14: ALRMMNTH: ALARM MONTH VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bits Contains a value of 0 or 1. bit 3-0 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 18-15: ALRMDAY: ALARM DAY VALUE REGISTER(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 18-16: ALRMWD: ALARM WEEKDAY VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. Note 1: A write to this register is only allowed when RTCWREN=1.  2009-2018 Microchip Technology Inc. DS30009960F-page 227

PIC18F87K22 FAMILY REGISTER 18-17: ALRMHR: ALARM HOURS VALUE REGISTER(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 18-18: ALRMMIN: ALARM MINUTES VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. REGISTER 18-19: ALRMSEC: ALARM SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9. DS30009960F-page 228  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 18.1.4 RTCEN BIT WRITE 18.2 Operation RTCWREN (RTCCFG<5>) must be set before a write 18.2.1 REGISTER INTERFACE to RTCEN can take place. Any write to the RTCEN bit, while RTCWREN=0, will be ignored. The register interface for the RTCC and alarm values is implemented using the Binary Coded Decimal (BCD) Like the RTCEN bit, the RTCVALH and RTCVALL format. This simplifies the firmware when using the registers can only be written to when RTCWREN=1. module, as each of the digits is contained within its own A write to these registers, while RTCWREN=0, will be 4-bit value (see Figure18-2 and Figure18-3). ignored. FIGURE 18-2: TIMER DIGIT FORMAT Year Month Day Day of Week 0-9 0-9 0-1 0-9 0-3 0-9 0-6 Hours 1/2 Second Bit (24-hour format) Minutes Seconds (binary format) 0-2 0-9 0-5 0-9 0-5 0-9 0/1 FIGURE 18-3: ALARM DIGIT FORMAT Month Day Day of Week 0-1 0-9 0-3 0-9 0-6 Hours (24-hour format) Minutes Seconds 0-2 0-9 0-5 0-9 0-5 0-9  2009-2018 Microchip Technology Inc. DS30009960F-page 229

PIC18F87K22 FAMILY 18.2.2 CLOCK SOURCE Calibration of the crystal can be done through this module to yield an error of 3seconds or less per month. As previously mentioned, the RTCC module is (For further details, see Section 18.2.9 “Calibration”.) intended to be clocked by an external Real-Time Clock (RTC) crystal, oscillating at 32.768kHz, but an internal oscillator can be used. The RTCC clock selection is decided by the RTCOSC bit (CONFIG3L<0>). FIGURE 18-4: CLOCK SOURCE MULTIPLEXING 32.768 kHz XTAL Half-Second from SOSC 1:16384 Clock One Second Clock Half Second(1) Clock Prescaler(1) Internal RC RTCCFG Day Second Hour:Minute Month Year Day of Week Note 1: Writing to the lower half of the MINSEC register resets all counters, allowing fraction of a second synchronization; clock prescaler is held in Reset when RTCEN =0. 18.2.2.1 Real-Time Clock Enable TABLE 18-1: DAY OF WEEK SCHEDULE The RTCC module can be clocked by an external, Day of Week 32.768 kHz crystal (SOSC oscillator) or the LF-INTOSC Sunday 0 oscillator, which can be selected in CONFIG3L<0>. Monday 1 If the external clock is used, the SOSC oscillator should be enabled. If LF-INTOSC is providing the clock, the Tuesday 2 INTOSC clock can be brought out to the RTCC pin by Wednesday 3 the RTSECSEL<1:0> bits (PADCFG<2:1>). Thursday 4 18.2.3 DIGIT CARRY RULES Friday 5 Saturday 6 This section explains which timer values are affected when there is a rollover: TABLE 18-2: DAY TO MONTH ROLLOVER • Time of Day: From 23:59:59 to 00:00:00 with a SCHEDULE carry to the Day field • Month: From 12/31 to 01/01 with a carry to the Month Maximum Day Field Year field 01 (January) 31 • Day of Week: From 6 to 0 with no carry (see 02 (February) 28 or 29(1) Table18-1) 03 (March) 31 • Year Carry: From 99 to 00; this also surpasses the use of the RTCC 04 (April) 30 For the day-to-month rollover schedule, see Table18-2. 05 (May) 31 06 (June) 30 Because the following values are in BCD format, the carry to the upper BCD digit occurs at the count of 10, 07 (July) 31 not 16 (SECONDS, MINUTES, HOURS, WEEKDAY, 08 (August) 31 DAYS and MONTHS). 09 (September) 30 10 (October) 31 11 (November) 30 12 (December) 31 Note 1: See Section 18.2.4 “Leap Year”. DS30009960F-page 230  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 18.2.4 LEAP YEAR 18.2.7 WRITE LOCK Since the year range on the RTCC module is 2000 to In order to perform a write to any of the RTCC Timer 2099, the leap year calculation is determined by any year registers, the RTCWREN bit (RTCCFG<5>) must be set. divisible by four in the above range. Only February is To avoid accidental writes to the RTCC Timer register, affected in a leap year. it is recommended that the RTCWREN bit February will have 29 days in a leap year and 28 days in (RTCCFG<5>) be kept clear when not writing to the any other year. register. For the RTCWREN bit to be set, there is only one instruction cycle time window allowed between the 18.2.5 GENERAL FUNCTIONALITY 55h/AA sequence and the setting of RTCWREN. For All Timer registers containing a time value of seconds or that reason, it is recommended that users follow the greater are writable. The user configures the time by code example in Example18-1. writing the required year, month, day, hour, minutes and seconds to the Timer registers, via register pointers. EXAMPLE 18-1: SETTING THE RTCWREN (See Section 18.2.8 “Register Mapping”.) BIT The timer uses the newly written values and proceeds movlw 0x55 with the count from the required starting point. movwf EECON2 movlw 0xAA The RTCC is enabled by setting the RTCEN bit movwf EECON2 (RTCCFG<7>). If enabled, while adjusting these bsf RTCCFG,RTCWREN registers, the timer still continues to increment. However, any time the MINSEC register is written to, both of the 18.2.8 REGISTER MAPPING timer prescalers are reset to ‘0’. This allows fraction of a second synchronization. To limit the register interface, the RTCC Timer and Alarm Timer registers are accessed through The Timer registers are updated in the same cycle as corresponding register pointers. The RTCC Value the write instruction’s execution by the CPU. The user register window (RTCVALH and RTCVALL) uses the must ensure that when RTCEN = 1, the updated RTCPTRx bits (RTCCFG<1:0>) to select the required registers will not be incremented at the same time. This Timer register pair. can be accomplished in several ways: By reading or writing to the RTCVALH register, the • By checking the RTCSYNC bit (RTCCFG<4>) RTCC Pointer value (RTCPTR<1:0>) decrements by ‘1’ • By checking the preceding digits from which a until it reaches ‘00’. When ‘00’ is reached, the carry can occur MINUTES and SECONDS value is accessible through • By updating the registers immediately following RTCVALH and RTCVALL until the pointer value is the seconds pulse (or an alarm interrupt) manually changed. The user has visibility to the half-second field of the counter. This value is read-only and can be reset only TABLE 18-3: RTCVALH AND RTCVALL by writing to the lower half of the SECONDS register. REGISTER MAPPING 18.2.6 SAFETY WINDOW FOR REGISTER RTCC Value Register Window RTCPTR<1:0> READS AND WRITES RTCVALH RTCVALL The RTCSYNC bit indicates a time window during 00 MINUTES SECONDS which the RTCC Clock Domain registers can be safely 01 WEEKDAY HOURS read and written without concern about a rollover. When RTCSYNC = 0, the registers can be safely 10 MONTH DAY accessed by the CPU. 11 — YEAR Whether RTCSYNC = 1 or 0, the user should employ a The Alarm Value register windows (ALRMVALH and firmware solution to ensure that the data read did not ALRMVALL) use the ALRMPTR bits (ALRMCFG<1:0>) fall on a rollover boundary, resulting in an invalid or to select the desired alarm register pair. partial read. This firmware solution would consist of reading each register twice and then comparing the two By reading or writing to the ALRMVALH register, the values. If the two values matched, then a rollover did Alarm Pointer value, ALRMPTR<1:0>, decrements by not occur. one until it reaches ‘00’. When it reaches ‘00’, the ALRMMIN and ALRMSEC values are accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed.  2009-2018 Microchip Technology Inc. DS30009960F-page 231

PIC18F87K22 FAMILY TABLE 18-4: ALRMVAL REGISTER Writes to the RTCCAL register should occur only when MAPPING the timer is turned off or immediately after the rising edge of the seconds pulse. Alarm Value Register Window ALRMPTR<1:0> Note: In determining the crystal’s error value, it ALRMVALH ALRMVALL is the user’s responsibility to include the crystal’s initial error from drift due to 00 ALRMMIN ALRMSEC temperature or crystal aging. 01 ALRMWD ALRMHR 10 ALRMMNTH ALRMDAY 18.3 Alarm 11 — — The Alarm features and characteristics are: 18.2.9 CALIBRATION • Configurable from half a second to one year The real-time crystal input can be calibrated using the • Enabled using the ALRMEN bit (ALRMCFG<7>, periodic auto-adjust feature. When properly calibrated, Register18-4) the RTCC can provide an error of less than three • Offers one-time and repeat alarm options seconds per month. To perform this calibration, find the number of error 18.3.1 CONFIGURING THE ALARM clock pulses and store the value into the lower half of The alarm feature is enabled using the ALRMEN bit. the RTCCAL register. The eight-bit, signed value, This bit is cleared when an alarm is issued. The bit will loaded into RTCCAL, is multiplied by four and will be not be cleared if the CHIME bit = 1 or if ALRMRPT  0. either added or subtracted from the RTCC timer, once every minute. The interval selection of the alarm is configured through the ALRMCFG bits (AMASK<3:0>); see To calibrate the RTCC module: Figure18-5. These bits determine which, and how 1. Use another timer resource on the device to find many, digits of the alarm must match the clock value for the error of the 32.768 kHz crystal. the alarm to occur. 2. Convert the number of error clock pulses per The alarm can also be configured to repeat based on a minute (see Equation18-1). preconfigured interval. The number of times this EQUATION 18-1: CONVERTING ERROR occurs, after the alarm is enabled, is stored in the CLOCK PULSES ALRMRPT register. (Ideal Frequency (32,758) – Measured Frequency) * 60 = Note: While the alarm is enabled (ALRMEN=1), Error Clocks per Minute changing any of the registers, other than the RTCCAL, ALRMCFG and ALRMRPT • If the oscillator is faster than ideal (negative registers and the CHIME bit, can result in a result from Step 2), the RCFGCALL register false alarm event leading to a false alarm value needs to be negative. This causes the interrupt. To avoid this, only change the specified number of clock pulses to be timer and alarm values while the alarm is subtracted from the timer counter, once every disabled (ALRMEN=0). It is recom- minute. mended that the ALRMCFG and • If the oscillator is slower than ideal (positive ALRMRPT registers and CHIME bit be result from Step 2), the RCFGCALL register changed when RTCSYNC = 0. value needs to be positive. This causes the specified number of clock pulses to be added to the timer counter, once every minute. 3. Load the RTCCAL register with the correct value. DS30009960F-page 232  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 18-5: ALARM MASK SETTINGS Alarm Mask Setting Day of the AMASK<3:0> Week Month Day Hours Minutes Seconds 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds s 0011 – Every minute s s 0100 – Every 10 minutes m s s 0101 – Every hour m m s s 0110 – Every day h h m m s s 0111 – Every week d h h m m s s 1000 – Every month d d h h m m s s 1001 – Every year(1) m m d d h h m m s s Note 1: Annually, except when configured for February 29. When ALRMCFG = 00 and the CHIME bit = 0 18.3.2 ALARM INTERRUPT (ALRMCFG<6>), the repeat function is disabled and At every alarm event, an interrupt is generated. Addi- only a single alarm will occur. The alarm can be tionally, an alarm pulse output is provided that operates repeated up to 255 times by loading the ALRMRPT at half the frequency of the alarm. register with FFh. The alarm pulse output is completely synchronous with After each alarm is issued, the ALRMRPT register is the RTCC clock and can be used as a trigger clock to decremented by one. Once the register has reached other peripherals. This output is available on the RTCC ‘00’, the alarm will be issued one last time. pin. The output pulse is a clock with a 50% duty cycle After the alarm is issued a last time, the ALRMEN bit is and a frequency half that of the alarm event (see cleared automatically and the alarm is turned off. Figure18-6). Indefinite repetition of the alarm can occur if the The RTCC pin also can output the seconds clock. The CHIMEbit = 1. user can select between the alarm pulse, generated by When CHIME = 1, the alarm is not disabled when the the RTCC module, or the seconds clock output. ALRMRPT register reaches ‘00’, but it rolls over to FF The RTSECSEL<1:0> bits (PADCFG1<2:1>) select and continues counting indefinitely. between these two outputs: • Alarm pulse – RTSECSEL<1:0> = 00 • Seconds clock – RTSECSEL<1:0> = 01  2009-2018 Microchip Technology Inc. DS30009960F-page 233

PIC18F87K22 FAMILY FIGURE 18-6: TIMER PULSE GENERATION RTCEN bit ALRMEN bit RTCC Alarm Event RTCC Pin 18.4 Sleep Mode 18.5.2 POWER-ON RESET (POR) The timer and alarm continue to operate while in Sleep The RTCCFG and ALRMRPT registers are reset only mode. The operation of the alarm is not affected by on a POR. Once the device exits the POR state, the Sleep, as an alarm event can always wake up the CPU. clock registers should be reloaded with the desired values. The Idle mode does not affect the operation of the timer or alarm. The timer prescaler values can be reset only by writing to the SECONDS register. No device Reset can affect the prescalers. 18.5 Reset 18.5.1 DEVICE RESET When a device Reset occurs, the ALRMRPT register is forced to its Reset state, causing the alarm to be disabled (if enabled prior to the Reset). If the RTCC was enabled, it will continue to operate when a basic device Reset occurs. DS30009960F-page 234  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 18.6 Register Maps Table18-5, Table18-6 and Table18-7 summarize the registers associated with the RTCC module. TABLE 18-5: RTCC CONTROL REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 PADCFG1 RDPU REPU RJPU(1) — — RTSECSEL1 RTSECSEL0 — ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 PMD1 PSPMD CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD EMBDM Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 80-pin devices. Note 1: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. TABLE 18-6: RTCC VALUE REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RTCVALH RTCC Value High Register Window Based on RTCPTR<1:0> RTCVALL RTCC Value Low Register Window Based on RTCPTR<1:0> TABLE 18-7: ALARM VALUE REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ALRMVALH Alarm Value High Register Window Based on ALRMPTR<1:0> ALRMVALL Alarm Value Low Register Window Based on ALRMPTR<1:0>  2009-2018 Microchip Technology Inc. DS30009960F-page 235

PIC18F87K22 FAMILY 19.0 CAPTURE/COMPARE/PWM Each CCP module contains a 16-bit register that can (CCP) MODULES operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. PIC18F87K22 family devices have seven CCP For the sake of clarity, all CCP module operation in the (Capture/Compare/PWM) modules, designated CCP4 following sections is described with respect to CCP4, through CCP10. All the modules implement standard but is equally applicable to CCP5 through CCP10. Capture, Compare and Pulse-Width Modulation (PWM) Note: The CCP9 and CCP10 modules are modes. disabled on the devices with 32 Kbytes of Note: Throughout this section, generic references program memory (PIC18FX5K22). are used for register and bit names that are the same, except for an ‘x’ variable that indicates the item’s association with the specific CCP module. For example, the control register is named CCPxCON and refers to CCP4CON through CCP10CON. REGISTER 19-1: CCPxCON: CCPx CONTROL REGISTER (CCP4-CCP10 MODULES)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3(2) CCPxM2(2) CCPxM1(2) CCPxM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PxM<1:0>: PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA is assigned as a capture/compare input/output; PxB, PxC and PxD are assigned as port pins If CCPxM<3:2> = 11: 00 = Single output: PxA, PxB, PxC and PxD are controlled by steering 01 = Full-bridge output forward: PxD is modulated; PxA is active; PxB, PxC are inactive 10 = Half-bridge output: PxA, PxB are modulated with dead-band control; PxC and PxD are assigned as port pins 11 = Full-bridge output reverse: PxB is modulated; PxC is active; PxA and PxD are inactive bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL. Note 1: The CCP9 and CCP10 modules are not available on devices with 32 Kbytes of program memory (PIC18FX5K22). 2: CCPxM<3:0> = 1011 will only reset the timer and not start AN A/D conversion on CCPx match. DS30009960F-page 236  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 19-1: CCPxCON: CCPx CONTROL REGISTER (CCP4-CCP10 MODULES)(1) bit 3-0 CCPxM<3:0>: CCPx Module Mode Select bits(2) 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Compare mode: Special Event Trigger; reset timer on CCPx match (CCPxIF bit is set) 11xx = PWM mode Note 1: The CCP9 and CCP10 modules are not available on devices with 32 Kbytes of program memory (PIC18FX5K22). 2: CCPxM<3:0> = 1011 will only reset the timer and not start AN A/D conversion on CCPx match. REGISTER 19-2: CCPTMRS1: CCP TIMER SELECT REGISTER 1 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 C7TSEL<1:0>: CCP7 Timer Selection bits 00 = CCP7 is based off of TMR1/TMR2 01 = CCP7 is based off of TMR5/TMR4 10 = CCP7 is based off of TMR5/TMR6 11 = CCP7 is based off of TMR5/TMR8 bit 5 Unimplemented: Read as ‘0’ bit 4 C6TSEL0: CCP6 Timer Selection bit 0 = CCP6 is based off of TMR1/TMR2 1 = CCP6 is based off of TMR5/TMR2 bit 3 Unimplemented: Read as ‘0’ bit 2 C5TSEL0: CCP5 Timer Selection bit 0 = CCP5 is based off of TMR1/TMR2 1 = CCP5 is based off of TMR5/TMR4 bit 1-0 C4TSEL<1:0>: CCP4 Timer Selection bits 00 = CCP4 is based off of TMR1/TMR2 01 = CCP4 is based off of TMR3/TMR4 10 = CCP4 is based off of TMR3/TMR6 11 = Reserved; do not use  2009-2018 Microchip Technology Inc. DS30009960F-page 237

PIC18F87K22 FAMILY REGISTER 19-3: CCPTMRS2: CCP TIMER SELECT REGISTER 2 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — C10TSEL0(1) — C9TSEL0(1) C8TSEL1 C8TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 C10TSEL0: CCP10 Timer Selection bit(1) 0 = CCP10 is based off of TMR1/TMR2 1 = CCP10 is based off of TMR7/TMR2 bit 3 Unimplemented: Read as ‘0’ bit 2 C9TSEL0: CCP9 Timer Selection bit(1) 0 = CCP9 is based off of TMR1/TMR2 1 = CCP9 is based off of TMR7/TMR4 bit 1-0 C8TSEL<1:0>: CCP8 Timer Selection bits On Non 32-Byte Device Variants: 00 = CCP8 is based off of TMR1/TMR2 01 = CCP8 is based off of TMR7/TMR4 10 = CCP8 is based off of TMR7/TMR6 11 = Reserved; do not use On 32-Byte Device Variants (PIC18F65K22 and PIC18F85K22): 00 = CCP8 is based off of TMR1/TMR2 01 = CCP8 is based off of TMR1/TMR4 10 = CCP8 is based off of TMR1/TMR6 11 = Reserved; do not use Note 1: This bit is unimplemented and reads as ‘0’ on devices with 32 Kbytes of program memory (PIC18FX- 5K22). DS30009960F-page 238  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 19-4: CCPRxL: CCPx PERIOD LOW BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CCPRxL7 CCPRxL6 CCPRxL5 CCPRxL4 CCPRxL3 CCPRxL2 CCPRxL1 CCPRxL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CCPRxL<7:0>: CCPx Period Register Low Byte bits Capture Mode: Capture Register Low Byte Compare Mode: Compare Register Low Byte PWM Mode: Duty Cycle Register REGISTER 19-5: CCPRxH: CCPx PERIOD HIGH BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CCPRxH7 CCPRxH6 CCPRxH5 CCPRxH4 CCPRxH3 CCPRxH2 CCPRxH1 CCPRxH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CCPRxH<7:0>: CCPx Period Register High Byte bits Capture Mode: Capture Register High Byte Compare Mode: Compare Register High Byte PWM Mode: Duty Cycle Buffer Register  2009-2018 Microchip Technology Inc. DS30009960F-page 239

PIC18F87K22 FAMILY 19.1 CCP Module Configuration TABLE 19-1: CCP MODE – TIMER RESOURCE Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a CCP Mode Timer Resource data register (CCPRx). The data register, in turn, is Capture comprised of two 8-bit registers: CCPRxL (low byte) Timer1, Timer3, Timer 5 or Timer7 and CCPRxH (high byte). All registers are both Compare readable and writable. PWM Timer2, Timer4, Timer 6 or Timer8 19.1.1 CCP MODULES AND TIMER The assignment of a particular timer to a module is RESOURCES determined by the timer to CCP enable bits in the CCPTMRSx registers (see Register19-2 and The CCP modules utilize Timers, 1 through 8, which Register19-3). All of the modules may be active at vary with the selected mode. Various timers are avail- once and may share the same timer resource if they able to the CCP modules in Capture, Compare or PWM are configured to operate in the same mode modes, as shown in Table19-1. (Capture/Compare or PWM) at the same time. The CCPTMRS1 register selects the timers for CCP modules, 7, 6, 5 and 4, and the CCPTMRS2 register selects the timers for CCP modules, 10, 9 and 8. The possible configurations are shown in Table19-2 and Table19-3. TABLE 19-2: TIMER ASSIGNMENTS FOR CCP MODULES 4, 5, 6 AND 7 CCPTMRS1 Register CCP4 CCP5 CCP6 CCP7 Capture/ Capture/ Capture/ Capture/ C4TSEL PWM PWM PWM C7TSEL PWM Compare C5TSEL0 Compare C6TSEL0 Compare Compare <1:0> Mode Mode Mode <1:0> Mode Mode Mode Mode Mode 0 0 TMR1 TMR2 0 TMR1 TMR2 0 TMR1 TMR2 0 0 TMR1 TMR2 0 1 TMR3 TMR4 1 TMR5 TMR4 1 TMR5 TMR2 0 1 TMR5 TMR4 1 0 TMR3 TMR6 1 0 TMR5 TMR6 1 1 Reserved(1) 1 1 TMR5 TMR8 Note 1: Do not use the reserved bits. TABLE 19-3: TIMER ASSIGNMENTS FOR CCP MODULES 8, 9 AND 10 CCPTMRS2 Register CCP8 CCP8 CCP9(1) CCP10(1) Devices with 32 Kbytes Capture/ Capture/ Capture/ Capture/ C8TSEL PWM C8TSEL PWM PWM PWM Compare Compare C9TSEL0 Compare C10TSEL0 Compare <1:0> Mode <1:0> Mode Mode Mode Mode Mode Mode Mode 0 0 TMR1 TMR2 0 0 TMR1 TMR2 0 TMR1 TMR2 0 TMR1 TMR2 0 1 TMR7 TMR4 0 1 TMR1 TMR4 1 TMR7 TMR4 1 TMR7 TMR2 1 0 TMR7 TMR6 1 0 TMR1 TMR6 1 1 Reserved(2) 1 1 Reserved(2) Note 1: The module is not available for devices with 32 Kbytes of program memory (PIC18F65K22 and PIC18F85K22). 2: Do not use the reserved setting. DS30009960F-page 240  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 19.1.2 OPEN-DRAIN OUTPUT OPTION 19.2 Capture Mode When operating in Output mode (the Compare or PWM In Capture mode, the CCPR4H:CCPR4L register pair modes), the drivers for the CCPx pins can be optionally captures the 16-bit value of the Timer register selected configured as open-drain outputs. This feature allows in the CCPTMRS1 when an event occurs on the CCP4 the voltage level on the pin to be pulled to a higher level pin. An event is defined as one of the following: through an external pull-up resistor and allows the • Every falling edge output to communicate with external circuits without the need for additional level shifters. • Every rising edge • Every 4th rising edge The open-drain output option is controlled by the CCPxOD bits (ODCON2<7:0>). Setting the appropri- • Every 16th rising edge ate bit configures the pin for the corresponding module The event is selected by the mode select bits, for open-drain operation. CCP4M<3:0> (CCP4CON<3:0>). When a capture is made, the interrupt request flag bit, CCP4IF (PIR4<1>), 19.1.3 PIN ASSIGNMENT FOR CCP6, is set. (It must be cleared in software.) If another CCP7, CCP8 AND CCP9 capture occurs before the value in CCPR4 is read, the The pin assignment for CCP6/7/8/9 (Capture input, old captured value is overwritten by the new captured Compare and PWM output) can change, based on the value. device configuration. Figure19-1 shows the Capture mode block diagram. The ECCPMX Configuration bit (CONFIG3H<1>) 19.2.1 CCP PIN CONFIGURATION determines the pin to which CCP6/7/8/9 is multiplexed. The pin assignments for these CCP modules are given In Capture mode, the appropriate CCPx pin should be in Table19-4. configured as an input by setting the corresponding TRIS direction bit. TABLE 19-4: CCP PIN ASSIGNMENT Note: If RC1 or RE7 is configured as a CCP4 Pin Mapped to output, a write to the port causes a ECCPMX capture condition. Value CCP6 CCP7 CCP8 CC9 1 19.2.2 TIMER1/3/5/7 MODE SELECTION RE6 RE5 RE4 RE3 (Default) For the available timers (1/3/5/7) to be used for the 0 RH7 RH6 RH5 RH4 capture feature, the used timers must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each CCP module is selected in the CCPTMRSx registers. (See Section19.1.1 “CCP Modules and Timer Resources”.) Details of the timer assignments for the CCP modules are given in Table19-2 and Table19-3.  2009-2018 Microchip Technology Inc. DS30009960F-page 241

PIC18F87K22 FAMILY FIGURE 19-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR5H TMR5L Set CCP5IF C5TSEL0 TMR5 Enable CCP5 Pin Prescaler and CCPR5H CCPR5L  1, 4, 16 Edge Detect TMR1 C5TSEL0 Enable 4 TMR1H TMR1L CCP5CON<3:0> Set CCP4IF 4 Q1:Q4 4 CCP4CON<3:0> C4TSEL1 TMR3H TMR3L C4TSEL0 TMR3 Enable CCP4 Pin Prescaler and CCPR4H CCPR4L  1, 4, 16 Edge Detect TMR1 Enable C4TSEL0 TMR1H TMR1L C4TSEL1 Note: This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of the CCP modules and their timer assignments, see Table19-2 and Table19-3. 19.2.3 SOFTWARE INTERRUPT Switching from one capture prescaler to another may generate an interrupt. Doing that will also not clear the When the Capture mode is changed, a false capture prescaler counter – meaning the first capture may be interrupt may be generated. The user should keep the from a non-zero prescaler. CCP4IE bit (PIE4<1>) clear to avoid false interrupts and should clear the flag bit, CCP4IF, following any Example19-1 shows the recommended method for such change in operating mode. switching between capture prescalers. This example also clears the prescaler counter and will not generate 19.2.4 CCP PRESCALER the “false” interrupt. There are four prescaler settings in Capture mode. EXAMPLE 19-1: CHANGING BETWEEN They are specified as part of the operating mode selected by the mode select bits (CCP4M<3:0>). CAPTURE PRESCALERS Whenever the CCP module is turned off, or the CCP CLRF CCP4CON ; Turn CCP module off module is not in Capture mode, the prescaler counter MOVLW NEW_CAPT_PS ; Load WREG with the is cleared. This means that any Reset will clear the ; new prescaler mode prescaler counter. ; value and CCP ON MOVWF CCP4CON ; Load CCP4CON with ; this value DS30009960F-page 242  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 19.3 Compare Mode 19.3.3 SOFTWARE INTERRUPT MODE In Compare mode, the 16-bit CCPR4 register value is When the Generate Software Interrupt mode is chosen constantly compared against the Timer register pair (CCP4M<3:0> = 1010), the CCP4 pin is not affected. value selected in the CCPTMR1 register. When a Only a CCP interrupt is generated, if enabled, and the match occurs, the CCP4 pin can be: CCP4IE bit is set. • Driven high 19.3.4 SPECIAL EVENT TRIGGER • Driven low Both CCP modules are equipped with a Special Event • Toggled (high-to-low or low-to-high) Trigger. This is an internal hardware signal generated • Unchanged (that is, reflecting the state of the I/O in Compare mode to trigger actions by other modules. latch) The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode The action on the pin is based on the value of the mode select bits (CCP4M<3:0>). At the same time, the (CCP4M<3:0> = 1011). interrupt flag bit, CCP4IF, is set. For either CCP module, the Special Event Trigger resets the Timer register pair for whichever timer resource is Figure19-2 gives the Compare mode block diagram currently assigned as the module’s time base. This 19.3.1 CCP PIN CONFIGURATION allows the CCPRx registers to serve as a programmable Period register for either timer. The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit. The Special Event Trigger for CCP4 cannot start an A/D conversion. Note: Clearing the CCP4CON register will force the RC1 or RE7 compare output latch Note: The Special Event Trigger of ECCP2 can start (depending on device configuration) to the an A/D conversion, but the A/D Converter default low level. This is not the PORTC or must be enabled. For more information, see PORTE I/O data latch. Section19.0 “Capture/Compare/PWM (CCP) Modules”. 19.3.2 TIMER1/3/5/7 MODE SELECTION If the CCP module is using the compare feature in conjunction with any of the Timer1/3/5/7 timers, the timers must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the compare operation may not work. Note: Details of the timer assignments for the CCP modules are given in Table19-2 and Table19-3.  2009-2018 Microchip Technology Inc. DS30009960F-page 243

PIC18F87K22 FAMILY FIGURE 19-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger Set CCP5IF (Timer1/5 Reset) CCPR5H CCPR5L CCP5 Pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCP5CON<3:0> TMR1H TMR1L 0 TMR5H TMR5L 1 C5TSEL0 TMR1H TMR1L 0 1 TMR5H TMR5L Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) C4TSEL1 C4TSEL0 Set CCP4IF CCP4 Pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCPR4H CCPR4L CCP4CON<3:0> Note: This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of the CCP modules and their timer assignments, see Table19-2 and Table19-3. TABLE 19-5: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF RCON IPEN SBOREN CM RI TO PD POR BOR PIR4 CCP10IF(1) CCP9IF(1) CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF PIE4 CCP10IE(1) CCP9IE(1) CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE IPR4 CCP10IP(1) CCP9IP(1) CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 TMR1L Timer1 Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1/3/5/7. Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22). 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. DS30009960F-page 244  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 19-5: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7 (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR1H Timer1 Register High Byte TMR3L Timer3 Register Low Byte TMR3H Timer3 Register High Byte TMR5L Timer5 Register Low Byte TMR5H Timer5 Register High Byte TMR7L(1) Timer7 Register Low Byte TMR7H(1) Timer7 Register High Byte T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16 TMR3ON T5CON TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 SOSCEN T5SYNC RD16 TMR5ON T7CON(1) TMR7CS1 TMR7CS0 T7CKPS1 T7CKPS0 SOSCEN T7SYNC RD16 TMR7ON CCPR4L Capture/Compare/PWM Register 4 Low Byte CCPR4H Capture/Compare/PWM Register 4 High Byte CCPR5L Capture/Compare/PWM Register 5 Low Byte CCPR5H Capture/Compare/PWM Register 5 High Byte CCPR6L Capture/Compare/PWM Register 6 Low Byte CCPR6H Capture/Compare/PWM Register 6 High Byte CCPR7L Capture/Compare/PWM Register 7 Low Byte CCPR7H Capture/Compare/PWM Register 7 High Byte CCPR8L Capture/Compare/PWM Register 8 Low Byte CCPR8H Capture/Compare/PWM Register 8 High Byte CCPR9L(1) Capture/Compare/PWM Register 9 Low Byte CCPR9H(1) Capture/Compare/PWM Register 9 High Byte CCPR10L(1) Capture/Compare/PWM Register 10 Low Byte CCPR10H(1) Capture/Compare/PWM Register 10 High Byte CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 CCP6CON — — DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0 CCP7CON — — DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0 CCP8CON — — DC8B1 DC8B0 CCP8M3 CCP8M2 CCP8M1 CCP8M0 CCP9CON(1) — — DC9B1 DC9B0 CCP9M3 CCP9M2 CCP9M1 CCP9M0 CCP10CON(1) — — DC10B1 DC10B0 CCP10M3 CCP10M2 CCP10M1 CCP10M0 CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0 CCPTMRS2 — — — C10TSEL0(1) — C9TSEL0(1) C8TSEL1 C8TSEL0 PMD3 CCP10MD(1) CCP9MD(1) CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD TMR12MD(1) Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1/3/5/7. Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22). 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.  2009-2018 Microchip Technology Inc. DS30009960F-page 245

PIC18F87K22 FAMILY 19.4 PWM Mode A PWM output (Figure19-4) has a time base (period) and a time that the output stays high (duty cycle). The In Pulse-Width Modulation (PWM) mode, the CCP4 pin frequency of the PWM is the inverse of the period produces up to a 10-bit resolution PWM output. Since (1/period). the CCP4 pin is multiplexed with a PORTC or PORTE data latch, the appropriate TRIS bit must be cleared to FIGURE 19-4: PWM OUTPUT make the CCP4 pin an output. Period Note: Clearing the CCP4CON register will force the RC1 or RE7 output latch (depending on device configuration) to the default low level. This is not the PORTC or PORTE Duty Cycle I/O data latch. TMR2 = PR2 Figure19-3 shows a simplified block diagram of the TMR2 = Duty Cycle ECCP1 module in PWM mode. For a step-by-step procedure on how to set up the CCP TMR2 = PR2 module for PWM operation, see Section19.4.3 “Setup for PWM Operation”. 19.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 FIGURE 19-3: SIMPLIFIED PWM BLOCK register. The PWM period can be calculated using the DIAGRAM following formula: CCP4CON<5:4> Duty Cycle Registers EQUATION 19-1: CCPR4L (Note 2) PWM Period = [(PR2) + 1] • 4 • TOSC • (TMR2 Prescale Value) CCPR4H (Slave) (Note 2) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events Comparator R Q occur on the next increment cycle: RC2/ECCP1 • TMR2 is cleared TMR2 (Note 1) • The CCP4 pin is set S (An exception: If PWM duty cycle=0%, the CCP4 pin will not be set) Comparator TRISC<2> Clear Timer, • The PWM duty cycle is latched from CCPR4L into ECCP1 Pin and CCPR4H Latch D.C. PR2 Note: The Timer2 postscalers (see Section15.0 “Timer2 Module”) are not Note1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create used in the determination of the PWM the 10-bit time base. frequency. The postscaler could be used 2: CCP4 and its appropriate timers are used as an to have a servo update rate at a different example. For details on all of the CCP modules and their timer assignments, see Table19-2 and frequency than the PWM output. Table19-3. DS30009960F-page 246  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 19.4.2 PWM DUTY CYCLE The CCPR4H register and a two-bit internal latch are used to double-buffer the PWM duty cycle. This The PWM duty cycle is specified to use CCP4, as an double-buffering is essential for glitchless PWM example, by writing to the CCPR4L register and to the operation. CCP4CON<5:4> bits. Up to 10-bit resolution is avail- able. The CCPR4L contains the eight MSbs and the When the CCPR4H and two-bit latch match TMR2, CCP4CON<5:4> bits contain the two LSbs. This 10-bit concatenated with an internal two-bit Q clock or two value is represented by CCPR4L:CCP4CON<5:4>. bits of the TMR2 prescaler, the CCP4 pin is cleared. The following equation is used to calculate the PWM The maximum PWM resolution (bits) for a given PWM duty cycle in time: frequency is shown in Equation19-3: EQUATION 19-2: EQUATION 19-3: PWM Duty Cycle = (CCPR4L:CCP4CON<5:4>) • TOSC • (TMR2 Prescale Value) logF--F--P-O--W--S---CM--- PWM Resolution (max) = -----------------------------bits log2 CCPR4L and CCP4CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR4H until after a match between PR2 and TMR2 Note: If the PWM duty cycle value is longer than occurs (that is, the period is complete). In PWM mode, the PWM period, the CCP4 pin will not be CCPR4H is a read-only register. cleared. TABLE 19-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 19.4.3 SETUP FOR PWM OPERATION 3. Make the CCP4 pin an output by clearing the appropriate TRIS bit. To configure the CCP module for PWM operation, using CCP4 as an example: 4. Set the TMR2 prescale value, then enable Tim- er2 by writing to T2CON. 1. Set the PWM period by writing to the PR2 5. Configure the CCP4 module for PWM operation. register. 2. Set the PWM duty cycle by writing to the CCPR4L register and CCP4CON<5:4> bits. TABLE 19-7: REGISTERS ASSOCIATED WITH PWM AND TIMERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF RCON IPEN SBOREN CM RI TO PD POR BOR PIR4 CCP10IF(1) CCP9IF(1) CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF PIE4 CCP10IE(1) CCP9IE(1) CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE IPR4 CCP10IP(1) CCP9IP(1) CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2/4/6/8. Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22). 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.  2009-2018 Microchip Technology Inc. DS30009960F-page 247

PIC18F87K22 FAMILY TABLE 19-7: REGISTERS ASSOCIATED WITH PWM AND TIMERS (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 TMR2 Timer2 Register TMR4 Timer4 Register TMR6 Timer6 Register TMR8 Timer8 Register PR2 Timer2 Period Register PR4 Timer4 Period Register PR6 Timer6 Period Register PR8 Timer8 Period Register T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 T8CON — T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 TMR8ON T8CKPS1 T8CKPS0 CCPR4L Capture/Compare/PWM Register 4 Low Byte CCPR4H Capture/Compare/PWM Register 4 High Byte CCPR5L Capture/Compare/PWM Register 5 Low Byte CCPR5H Capture/Compare/PWM Register 5 High Byte CCPR6L Capture/Compare/PWM Register 6 Low Byte CCPR6H Capture/Compare/PWM Register 6 High Byte CCPR7L Capture/Compare/PWM Register 7 Low Byte CCPR7H Capture/Compare/PWM Register 7 High Byte CCPR8L Capture/Compare/PWM Register 8 Low Byte CCPR8H Capture/Compare/PWM Register 8 High Byte CCPR9L(1) Capture/Compare/PWM Register 9 Low Byte CCPR9H(1) Capture/Compare/PWM Register 9 High Byte CCPR10L(1) Capture/Compare/PWM Register 10 Low Byte CCPR10H(1) Capture/Compare/PWM Register 10 High Byte CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 CCP6CON — — DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0 CCP7CON — — DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0 CCP8CON — — DC8B1 DC8B0 CCP8M3 CCP8M2 CCP8M1 CCP8M0 CCP9CON(1) — — DC9B1 DC9B0 CCP9M3 CCP9M2 CCP9M1 CCP9M0 CCP10CON(1) — — DC10B1 DC10B0 CCP10M3 CCP10M2 CCP10M1 CCP10M0 CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0 CCPTMRS2 — — — C10TSEL0(1) — C9TSEL0(1) C8TSEL1 C8TSEL0 PMD3 CCP10MD(1) CCP9MD(1) CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD TMR12MD(1) Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2/4/6/8. Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22). 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. DS30009960F-page 248  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 20.0 ENHANCED ECCP1, ECCP2 and ECCP3 are implemented as stan- CAPTURE/COMPARE/PWM dard CCP modules with Enhanced PWM capabilities. These include: (ECCP) MODULE • Provision for two or four output channels PIC18F87K22 family devices have three Enhanced • Output Steering modes Capture/Compare/PWM (ECCP) modules: ECCP1, • Programmable polarity ECCP2 and ECCP3. These modules contain a 16-bit register, which can operate as a 16-bit Capture register, • Programmable dead-band control a 16-bit Compare register or a PWM Master/Slave Duty • Automatic shutdown and restart Cycle register. These ECCP modules are upward The enhanced features are discussed in detail in compatible with CCP. Section20.4 “PWM (Enhanced Mode)”. Note: Throughout this section, generic references The ECCP1, ECCP2 and ECCP3 modules use the are used for register and bit names that are control registers: CCP1CON, CCP2CON and the same, except for an ‘x’ variable that indi- CCP3CON. The control registers, CCP4CON through cates the item’s association with the CCP10CON, are for the modules, CCP4 through ECCP1, ECCP2 or ECCP3 module. For CCP10. example, the control register is named CCPxCON and refers to CCP1CON, CCP2CON and CCP3CON.  2009-2018 Microchip Technology Inc. DS30009960F-page 249

PIC18F87K22 FAMILY REGISTER 20-1: CCPxCON: ENHANCED CAPTURE/COMPARE/PWMx CONTROL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA is assigned as capture/compare input/output; PxB, PxC and PxD are assigned as port pins If CCPxM<3:2> = 11: 00 = Single output: PxA, PxB, PxC and PxD are controlled by steering (see Section20.4.7 “Pulse Steering Mode”) 01 = Full-bridge output forward: PxD is modulated; PxA is active; PxB, PxC are inactive 10 = Half-bridge output: PxA, PxB are modulated with dead-band control; PxC and PxD are assigned as port pins 11 = Full-bridge output reverse: PxB is modulated; PxC is active; PxA and PxD are inactive bit 5-4 DCxB<1:0>: PWM Duty Cycle Bit 1 and Bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCPx module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Capture mode 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every fourth rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize ECCPx pin low, set output on compare match (set CCPxIF) 1001 = Compare mode: initialize ECCPx pin high, clear output on compare match (set CCPxIF) 1010 = Compare mode: generate software interrupt only, ECCPx pin reverts to I/O state 1011 = Compare mode: trigger special event (ECCPx resets TMR1 or TMR3, starts A/D conversion, sets CCPxIF bit) 1100 = PWM mode: PxA and PxC are active-high; PxB and PxD are active-high 1101 = PWM mode: PxA and PxC are active-high; PxB and PxD are active-low 1110 = PWM mode: PxA and PxC are active-low; PxB and PxD are active-high 1111 = PWM mode: PxA and PxC are active-low; PxB and PxD are active-low DS30009960F-page 250  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 20-2: CCPTMRS0: CCP TIMER SELECT 0 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 C3TSEL<1:0>: ECCP3 Timer Selection bits 00 = ECCP3 is based off of TMR1/TMR2 01 = ECCP3 is based off of TMR3/TMR4 10 = ECCP3 is based off of TMR3/TMR6 11 = ECCP3 is based off of TMR3/TMR8 bit 5-3 C2TSEL<2:0>: ECCP2 Timer Selection bits 000 = ECCP2 is based off of TMR1/TMR2 001 = ECCP2 is based off of TMR3/TMR4 010 = ECCP2 is based off of TMR3/TMR6 011 = ECCP2 is based off of TMR3/TMR8 100 = ECCP2 is based off of TMR3/TMR10: option reserved on the 32-Kbyte device variant; do not use 101 = Reserved; do not use 110 = Reserved; do not use 111 = Reserved; do not use bit 2-0 C1TSEL<2:0>: ECCP1 Timer Selection bits 000 = ECCP1 is based off of TMR1/TMR2 001 = ECCP1 is based off of TMR3/TMR4 010 = ECCP1 is based off of TMR3/TMR6 011 = ECCP1 is based off of TMR3/TMR8 100 = ECCP1 is based off of TMR3/TMR10: option reserved on the 32-Kbyte device variant; do not use 101 = ECCP1 is based off of TMR3/TMR12: option reserved on the 32-Kbyte device variant; do not use 110 = Reserved; do not use 111 = Reserved; do not use  2009-2018 Microchip Technology Inc. DS30009960F-page 251

PIC18F87K22 FAMILY In addition to the expanded range of modes available The assignment of a particular timer to a module is through the CCPxCON and ECCPxAS registers, the determined by the timer to ECCP enable bits in the ECCP modules have two additional registers associated CCPTMRSx register (Register20-2). The interactions with Enhanced PWM operation and auto-shutdown between the two modules are depicted in Figure20-1. features. They are: Capture operations are designed to be used when the timer is configured for Synchronous Counter mode. • ECCPxDEL – Enhanced PWM Control Capture operations may not work as expected if the • PSTRxCON – Pulse Steering Control associated timer is configured for Asynchronous Counter mode. 20.1 ECCP Outputs and Configuration 20.1.2 ECCP PIN ASSIGNMENT The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. The pin assignment for ECCPx (Capture input, The CCPxCON register is modified to allow control Compare and PWM output) can change, based on over four PWM outputs: ECCPx/PxA, PxB, PxC and device configuration. The ECCPMX (CONFIG3H<1>) PxD. Applications can use one, two or four of these Configuration bit determines which pins ECCP1 and outputs. ECCP3 are multiplexed to. The outputs that are active depend on the ECCP • Default/ECCPMX = 1: selected operating mode. The pin assignments are - ECCP1 (P1B/P1C) is multiplexed onto RE6 summarized in Table20-3. and RE5 To configure the I/O pins as PWM outputs, the proper - ECCP3 (P3B/P3C) is multiplexed onto RE4 PWM mode must be selected by setting the PxM<1:0> and RE3 and CCPxM<3:0> bits. The appropriate TRIS direction • ECCPMX = 0: bits for the port pins must also be set as outputs. - ECCP1 (P1B/P1C) is multiplexed onto RH7 and RH6 20.1.1 ECCP MODULE AND TIMER - ECCP3 (P3B/P3C) is multiplexed onto RH5 RESOURCES and RH4. The ECCP modules use Timers, 1, 2, 3, 4, 6, 8, 10 or 12, The pin assignment for ECCP2 (Capture input, depending on the mode selected. These timers are Compare and PWM output) can change, based on the available to CCP modules in Capture, Compare or PWM device configuration. modes, as shown in Table20-1. The CCP2MX Configuration bit (CONFIG3H<0>) TABLE 20-1: ECCP MODE – TIMER determines which pin ECCP2 is multiplexed to. RESOURCE • If CCP2MX = 1 (default) – ECCP2 is multiplexed to RC1 ECCP Mode Timer Resource • If CCP2MX = 0 – ECCP2 is multiplexed to RE7 Capture Timer1 or Timer3 Compare Timer1 or Timer3 PWM Timer2, Timer4, Timer6, Timer8, Tim- er10 or Timer12 DS30009960F-page 252  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 20.2 Capture Mode 20.2.2 TIMER1/2/3/4/6/8/10/12 MODE SELECTION In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 The timers that are to be used with the capture feature registers when an event occurs on the corresponding (Timer1 2, 3, 4, 6, 8, 10 or 12) must be running in Timer ECCPx pin. An event is defined as one of the following: mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation • Every falling edge may not work. The timer to be used with each ECCP • Every rising edge module is selected in the CCPTMRS0 register • Every fourth rising edge (Register20-2). • Every 16th rising edge 20.2.3 SOFTWARE INTERRUPT The event is selected by the mode select bits, CCPxM<3:0> (CCPxCON<3:0>). When a capture is When the Capture mode is changed, a false capture made, the interrupt request flag bit, CCPxIF, is set (see interrupt may be generated. The user should keep the Table20-2). The flag must be cleared by software. If CCPxIE interrupt enable bit clear to avoid false interrupts. another capture occurs before the value in the The interrupt flag bit, CCPxIF, should also be cleared CCPRxH/L register is read, the old captured value is following any such change in operating mode. overwritten by the new captured value. 20.2.4 ECCP PRESCALER TABLE 20-2: ECCP1/2/3 INTERRUPT FLAG There are four prescaler settings in Capture mode; they BITS are specified as part of the operating mode selected by ECCP Module Flag Bit the mode select bits (CCPxM<3:0>). Whenever the ECCP module is turned off, or Capture mode is dis- 1 PIR3<1> abled, the prescaler counter is cleared. This means 2 PIR3<2> that any Reset will clear the prescaler counter. 3 PIR4<0> Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will 20.2.1 ECCP PIN CONFIGURATION not be cleared; therefore, the first capture may be from In Capture mode, the appropriate ECCPx pin should be a non-zero prescaler. Example20-1 provides the configured as an input by setting the corresponding recommended method for switching between capture TRIS direction bit. prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. Note: If the ECCPx pin is configured as an out- put, a write to the port can cause a capture EXAMPLE 20-1: CHANGING BETWEEN condition. CAPTURE PRESCALERS CLRF CCP1CON ; Turn ECCP module off MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and ECCP ON MOVWF CCP1CON ; Load CCP1CON with ; this value  2009-2018 Microchip Technology Inc. DS30009960F-page 253

PIC18F87K22 FAMILY FIGURE 20-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP1IF C1TSEL0 C1TSEL1 TMR3 ECCP1 Pin C1TSEL2 Enable Prescaler and CCPR1H CCPR1L  1, 4, 16 Edge Detect C1TSEL0 TMR1 C1TSEL1 Enable C1TSEL2 4 TMR1H TMR1L CCP1CON<3:0> 4 Q1:Q4 DS30009960F-page 254  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 20.3 Compare Mode 20.3.2 TIMER1/2/3/4/6/8/10/12 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is constantly compared against the Timer register pair Timer1 2, 3, 4, 6, 8, 10 or 12 must be running in Timer value selected in the CCPTMR1 register. When a mode or Synchronized Counter mode if the ECCP match occurs, the ECCPx pin can be: module is using the compare feature. In Asynchronous Counter mode, the compare operation will not work • Driven high reliably. • Driven low • Toggled (high-to-low or low-to-high) 20.3.3 SOFTWARE INTERRUPT MODE • Unchanged (that is, reflecting the state of the I/O When the Generate Software Interrupt mode is chosen latch) (CCPxM<3:0> = 1010), the ECCPx pin is not affected; The action on the pin is based on the value of the mode only the CCPxIF interrupt flag is affected. select bits (CCPxM<3:0>). At the same time, the 20.3.4 SPECIAL EVENT TRIGGER interrupt flag bit, CCPxIF, is set. The ECCP module is equipped with a Special Event 20.3.1 ECCP PIN CONFIGURATION Trigger. This is an internal hardware signal generated Users must configure the ECCPx pin as an output by in Compare mode to trigger actions by other modules. clearing the appropriate TRIS bit. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode Note: Clearing the CCPxCON register will force (CCPxM<3:0> = 1011). the ECCPx compare output latch The Special Event Trigger resets the Timer register pair (depending on device configuration) to the for whichever timer resource is currently assigned as the default low level. This is not the PORTx module’s time base. This allows the CCPRx registers to I/O data latch. serve as a programmable Period register for either timer. The Special Event Trigger can also start an A/D conver- sion. In order to do this, the A/D Converter must already be enabled. FIGURE 20-2: COMPARE MODE OPERATION BLOCK DIAGRAM TMR1H TMR1L 0 1 TMR3H TMR3L Special Event Trigger C1TSEL0 (Timer1/Timer3 Reset, A/D Trigger) C1TSEL1 C1TSEL2 Set CCP1IF ECCP1 Pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCPR1H CCPR1L CCP1CON<3:0>  2009-2018 Microchip Technology Inc. DS30009960F-page 255

PIC18F87K22 FAMILY 20.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated: PxA, PxB, PxC and PxD. The polarity of the The Enhanced PWM mode can generate a PWM signal PWM pins is configurable and is selected by setting the on up to four different output pins with up to 10 bits of CCPxM bits in the CCPxCON register appropriately. resolution. It can do this through four different PWM Table20-1 provides the pin assignments for each Output modes: Enhanced PWM mode. • Single PWM Figure20-3 provides an example of a simplified block • Half-Bridge PWM diagram of the Enhanced PWM module. • Full-Bridge PWM, Forward mode Note: To prevent the generation of an • Full-Bridge PWM, Reverse mode incomplete waveform when the PWM is To select an Enhanced PWM mode, the PxM bits of the first enabled, the ECCP module waits until CCPxCON register must be set appropriately. the start of a new PWM period before generating a PWM signal. FIGURE 20-3: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DC1B<1:0> PxM<1:0> CCPxM<3:0> Duty Cycle Registers 2 4 CCPR1L ECCPx/PxA ECCP1/Output Pin TRIS CCPR1H (Slave) PxB Output Pin Output TRIS Comparator R Q Controller PxC Output Pin TMR2 (Note 1) S TRIS PxD Output Pin Comparator Clear Timer2, TRIS Toggle PWM Pin and Latch Duty Cycle PR2 ECCP1DEL Note 1: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. Note1: The TRIS register value for each PWM output must be configured appropriately. 2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions. DS30009960F-page 256  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 20-3: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Outputs are enabled by pulse steering in Single mode (see Register20-5). FIGURE 20-4: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse Width PR2 + 1 PxM<1:0> Signal 0 Period 00 (Single Output) PxA Modulated Delay(1) Delay(1) PxA Modulated 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCPxDEL<6:0>) Note 1: Dead-band delay is programmed using the ECCPxDEL register (see Section20.4.6 “Programmable Dead-Band Delay Mode”).  2009-2018 Microchip Technology Inc. DS30009960F-page 257

PIC18F87K22 FAMILY FIGURE 20-5: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal 0 Pulse PR2 + 1 Width Period 00 (Single Output) PxA Modulated PxA Modulated Delay(1) Delay(1) 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCPxDEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section20.4.6 “Programmable Dead-Band Delay Mode”). DS30009960F-page 258  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 20.4.1 HALF-BRIDGE MODE Since the PxA and PxB outputs are multiplexed with the port data latches, the associated TRIS bits must be In Half-Bridge mode, two pins are used as outputs to cleared to configure PxA and PxB as outputs. drive push-pull loads. The PWM output signal is output on the PxA pin, while the complementary PWM output FIGURE 20-6: EXAMPLE OF signal is output on the PxB pin (see Figure20-6). This HALF-BRIDGE PWM mode can be used for half-bridge applications, as shown in Figure20-7, or for full-bridge applications, OUTPUT where four power switches are being modulated with Period Period two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in PxA(2) half-bridge power devices. The value of the PxDC<6:0> td bits of the ECCPxDEL register sets the number of td instruction cycles before the output is driven active. If the PxB(2) value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. For more (1) (1) (1) details on the dead-band delay operations, see Section20.4.6 “Programmable Dead-Band Delay td = Dead-Band Delay Mode”. Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FIGURE 20-7: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA - Load FET Driver + PxB - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver PxA Load FET FET Driver Driver PxB  2009-2018 Microchip Technology Inc. DS30009960F-page 259

PIC18F87K22 FAMILY 20.4.2 FULL-BRIDGE MODE In the Reverse mode, the PxC pin is driven to its active state and the PxB pin is modulated, while the PxA and In Full-Bridge mode, all four pins are used as outputs. PxD pins are driven to their inactive state, as provided An example of a full-bridge application is provided in Figure20-9. Figure20-8. The PxA, PxB, PxC and PxD outputs are multiplexed In the Forward mode, the PxA pin is driven to its active with the port data latches. The associated TRIS bits state and the PxD pin is modulated, while the PxB and must be cleared to configure the PxA, PxB, PxC and PxC pins are driven to their inactive state, as provided in PxD pins as outputs. Figure20-9. FIGURE 20-8: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver PxA Load PxB FET FET Driver Driver PxC QB QD V- PxD DS30009960F-page 260  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 20-9: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA(2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: The output signal is shown as active-high.  2009-2018 Microchip Technology Inc. DS30009960F-page 261

PIC18F87K22 FAMILY 20.4.2.1 Direction Change in Full-Bridge • The direction of the PWM output changes when Mode the duty cycle of the output is at or near 100%. • The turn-off time of the power switch, including In Full-Bridge mode, the PxM1 bit in the CCPxCON the power device and driver circuit, is greater than register allows users to control the forward/reverse the turn-on time. direction. When the application firmware changes this direction control bit, the module will change to the new Figure20-11 shows an example of the PWM direction direction on the next PWM cycle. changing from forward to reverse, at a near 100% duty cycle. In this example, at time, t1, the PxA and PxD A direction change is initiated in software by changing outputs become inactive, while the PxC output the PxM1 bit of the CCPxCON register. The following becomes active. Since the turn-off time of the power sequence occurs prior to the end of the current PWM devices is longer than the turn-on time, a shoot-through period: current will flow through power devices, QC and QD • The modulated outputs (PxB and PxD) are placed (see Figure20-8), for the duration of ‘t’. The same in their inactive state. phenomenon will occur to power devices, QA and QB, • The associated unmodulated outputs (PxA and for PWM direction change from reverse to forward. PxC) are switched to drive in the opposite If changing PWM direction at high duty cycle is required direction. for an application, two possible solutions for eliminating • PWM modulation resumes at the beginning of the the shoot-through current are: next period. • Reduce PWM duty cycle for one PWM period For an illustration of this sequence, see Figure20-10. before changing directions. The Full-Bridge mode does not provide a dead-band • Use switch drivers that can drive the switches off delay. As one output is modulated at a time, a faster than they can drive them on. dead-band delay is generally not required. There is a Other options to prevent shoot-through current may situation where a dead-band delay is required. This exist. situation occurs when both of the following conditions are true: FIGURE 20-10: EXAMPLE OF PWM DIRECTION CHANGE Signal Period(1) Period PxA (Active-High) PxB (Active-High) Pulse Width PxC (Active-High) (2) PxD (Active-High) Pulse Width Note 1: The direction bit, PxM1 of the CCPxCON register, is written any time during the PWM cycle. 2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is: (1/FOSC) • TMR2 Prescale Value. DS30009960F-page 262  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 20-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE(1) Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON(2) External Switch C TOFF(3) External Switch D Potential T = TOFF – TON(2,3) Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn-on delay of power switch, QC, and its driver. 3: TOFF is the turn-off delay of power switch, QD, and its driver. 20.4.3 START-UP CONSIDERATIONS pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF or TMR4IF bit of the PIR1 When any PWM mode is used, the application or PIR5 register being set as the second PWM period hardware must use the proper external pull-up and/or begins. pull-down resistors on the PWM output pins. Note: When the microcontroller is released from 20.4.4 ENHANCED PWM Reset, all of the I/O pins are in the AUTO-SHUTDOWN MODE high-impedance state. The external The PWM mode supports an Auto-Shutdown mode that circuits must keep the power switch will disable the PWM outputs when an external devices in the OFF state until the micro- shutdown event occurs. Auto-Shutdown mode places controller drives the I/O pins with the the PWM output pins into a predetermined state. This proper signal levels or activates the PWM mode is used to help prevent the PWM from damaging output(s). the application. The CCPxM<1:0> bits of the CCPxCON register allow The auto-shutdown sources are selected using the the user to choose whether the PWM output signals are ECCPxAS<2:0> bits (ECCPxAS<6:4>). A shutdown active-high or active-low for each pair of PWM output event may be generated by: pins (PxA/PxC and PxB/PxD). The PWM output • A logic ‘0’ on the pin that is assigned the FLT0 polarities must be selected before the PWM pin output input function drivers are enabled. Changing the polarity configura- tion while the PWM pin output drivers are enabled is • C1 Comparator not recommended since it may result in damage to the • C2 Comparator application circuits. • Setting the ECCPxASE bit in firmware The PxA, PxB, PxC and PxD output latches may not be A shutdown condition is indicated by the ECCPxASE in the proper states when the PWM module is (Auto-Shutdown Event Status) bit (ECCPxAS<7>). If initialized. Enabling the PWM pin output drivers at the the bit is a ‘0’, the PWM pins are operating normally. If same time as the Enhanced PWM modes may cause the bit is a ‘1’, the PWM outputs are in the shutdown damage to the application circuit. The Enhanced PWM state. modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM  2009-2018 Microchip Technology Inc. DS30009960F-page 263

PIC18F87K22 FAMILY When a shutdown event occurs, two things happen: Each pin pair may be placed into one of three states: • The ECCPxASE bit is set to ‘1’. The ECCPxASE • Drive logic ‘1’ will remain set until cleared in firmware or an • Drive logic ‘0’ auto-restart occurs. (See Section20.4.5 • Tri-state (high-impedance) “Auto-Restart Mode”.) • The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs (PxA/PxC) and (PxB/PxD). The state of each pin pair is determined by the PSSxAC and PSSxBD bits (ECCPxAS<3:2> and <1:0>, respectively). REGISTER 20-3: ECCPxAS: ECCPx AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPxASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in a shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPxAS<2:0>: ECCP Auto-Shutdown Source Select bits 000 =Auto-shutdown is disabled 001 =Comparator C1OUT output is high 010 =Comparator C2OUT output is high 011 =Either Comparator C1OUT or C2OUT is high 100 =VIL on FLT0 pin 101 =VIL on FLT0 pin or Comparator C1OUT output is high 110 =VIL on FLT0 pin or Comparator C2OUT output is high 111 =VIL on FLT0 pin or Comparator C1OUT or Comparator C2OUT is high bit 3-2 PSSxAC<1:0>: PxA and PxC Pins Shutdown State Control bits 00 =Drive pins, PxA and PxC, to ‘0’ 01 =Drive pins, PxA and PxC, to ‘1’ 1x = PxA and PxC pins tri-state bit 1-0 PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits 00 = Drive pins, PxB and PxD, to ‘0’ 01 = Drive pins, PxB and PxD, to ‘1’ 1x = PxB and PxD pins tri-state Note1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCPxASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period. DS30009960F-page 264  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 20-12: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0) PWM Period Shutdown Event ECCPxASE bit PWM Activity Normal PWM ECCPxASE Start of Shutdown Shutdown Cleared by PWM PWM Period Event Occurs Event Clears Firmware Resumes 20.4.5 AUTO-RESTART MODE The module will wait until the next PWM period begins, however, before re-enabling the output pin. This behav- The Enhanced PWM can be configured to automatically ior allows the auto-shutdown with auto-restart features restart the PWM signal once the auto-shutdown condi- to be used in applications based on current mode of tion has been removed. Auto-restart is enabled by PWM control. setting the PxRSEN bit (ECCPxDEL<7>). If auto-restart is enabled, the ECCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPxASE bit will be cleared via hardware and normal operation will resume. FIGURE 20-13: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PxRSEN = 1) PWM Period Shutdown Event ECCPxASE bit PWM Activity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes  2009-2018 Microchip Technology Inc. DS30009960F-page 265

PIC18F87K22 FAMILY 20.4.6 PROGRAMMABLE DEAD-BAND FIGURE 20-14: EXAMPLE OF DELAY MODE HALF-BRIDGE PWM OUTPUT In half-bridge applications, where all power switches are modulated at the PWM frequency, the power switches Period Period normally require more time to turn off than to turn on. If Pulse Width both the upper and lower power switches are switched at the same time (one turned on and the other turned PxA(2) off), both switches may be on for a short period until one td switch completely turns off. During this brief interval, a td very high current (shoot-through current) will flow PxB(2) through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through (1) (1) (1) current from flowing during switching, turning on either of the power switches is normally delayed to allow the td = Dead-Band Delay other switch to completely turn off. In Half-Bridge mode, a digitally programmable Note 1: At this time, the TMR2 register is equal to the dead-band delay is available to avoid shoot-through PR2 register. current from destroying the bridge power switches. The 2: Output signals are shown as active-high. delay occurs at the signal transition from the non-active state to the active state. For an illustration, see Figure20-14. The lower seven bits of the associated ECCPxDEL register (Register20-4) set the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 20-15: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA V - Load FET Driver + PxB V - V- DS30009960F-page 266  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 20-4: ECCPxDEL: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPxASE must be cleared by software to restart the PWM bit 6-0 PxDC<6:0>: PWM Delay Count bits PxDCn = Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it does transition active. 20.4.7 PULSE STEERING MODE While the PWM Steering mode is active, the CCPxM<1:0> bits (CCPxCON<1:0>) select the PWM In Single Output mode, pulse steering allows any of the output polarity for the Px<D:A> pins. PWM pins to be the modulated signal. Additionally, the same PWM signal can simultaneously be available on The PWM auto-shutdown operation also applies to the multiple pins. PWM Steering mode, as described in Section20.4.4 “Enhanced PWM Auto-shutdown mode”. An Once the Single Output mode is selected auto-shutdown event will only affect pins that have (CCPxM<3:2> = 11 and PxM<1:0> = 00 of the PWM outputs enabled. CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR<D:A> bits (PSTRxCON<3:0>), as provided in Table20-3. Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin.  2009-2018 Microchip Technology Inc. DS30009960F-page 267

PIC18F87K22 FAMILY REGISTER 20-5: PSTRxCON: PULSE STEERING CONTROL(1) R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits 00 = See STR<D:A> 01 = PA and PB are selected as the complementary output pair 10 = PA and PC are selected as the complementary output pair 11 = PA and PD are selected as the complementary output pair bit 5 Unimplemented: Read as ‘0’ bit 4 STRSYNC: Steering Sync bit 1 = Output steering update occurs on the next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRD: Steering Enable bit D 1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxD pin is assigned to the port pin bit 2 STRC: Steering Enable bit C 1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxC pin is assigned to the port pin bit 1 STRB: Steering Enable bit B 1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxB pin is assigned to the port pin bit 0 STRA: Steering Enable bit A 1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxA pin is assigned to the port pin Note 1: The PWM Steering mode is available only when the CCPxCON register bits, CCPxM<3:2>=11 and PxM<1:0>=00. DS30009960F-page 268  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 20-16: SIMPLIFIED STEERING 20.4.7.1 Steering Synchronization BLOCK DIAGRAM The STRSYNC bit of the PSTRxCON register gives the STRA(2) user two choices for when the steering event will happen. When the STRSYNC bit is ‘0’, the steering PxA Signal Output Pin(1) event will happen at the end of the instruction that CCPxM1 1 writes to the PSTRxCON register. In this case, the out- PORT Data put signal at the Px<D:A> pins may be an incomplete 0 TRIS PWM waveform. This operation is useful when the user STRB(2) firmware needs to immediately remove a PWM signal from the pin. Output Pin(1) CCPxM0 1 When the STRSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM PORT Data 0 period. In this case, steering on/off the PWM output will TRIS STRC(2) always produce a complete PWM waveform. Figures 20-17 and20-18 illustrate the timing diagrams Output Pin(1) CCPxM1 1 of the PWM steering depending on the STRSYNC setting. PORT Data 0 TRIS STRD(2) Output Pin(1) CCPxM0 1 PORT Data 0 TRIS Note 1: Port outputs are configured as displayed when the CCPxCON register bits, PxM<1:0>=00 and CCP1M<3:2>=11. 2: Single PWM output requires setting at least one of the STRx bits. FIGURE 20-17: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0) PWM Period PWM STRn P1<D:A> PORT Data PORT Data P1n = PWM FIGURE 20-18: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) PWM STRn P1<D:A> PORT Data PORT Data P1n = PWM  2009-2018 Microchip Technology Inc. DS30009960F-page 269

PIC18F87K22 FAMILY 20.4.8 OPERATION IN POWER-MANAGED 20.4.8.1 Operation with Fail-Safe MODES ClockMonitor (FSCM) In Sleep mode, all clock sources are disabled. Tim- If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock er2/4/6/8 will not increment and the state of the module failure will force the device into the power-managed will not change. If the ECCPx pin is driving a value, it RC_RUN mode and the OSCFIF bit of the PIR2 register will continue to drive that value. When the device will be set. The ECCPx will then be clocked from the wakes up, it will continue from this state. If Two-Speed internal oscillator clock source, which may have a Start-ups are enabled, the initial start-up frequency different clock frequency than the primary clock. from HF-INTOSC and the postscaler may not be imme- diately stable. 20.4.9 EFFECTS OF A RESET In PRI_IDLE mode, the primary clock will continue to Both Power-on Reset and subsequent Resets will force clock the ECCPx module without change. all ports to Input mode and the ECCP registers to their Reset states. This forces the ECCP module to reset to a state compatible with previous, non-Enhanced CCP modules used on other PIC18 and PIC16 devices. TABLE 20-4: REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND TIMER1/2/3/4/6/8/10/12 File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF RCON IPEN SBOREN CM RI TO PD POR BOR PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIR4 CCP10IF(1) CCP9IF(1) CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE PIE4 CCP10IE(1) CCP9IE(1) CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP IPR4 CCP10IP(1) CCP9IP(1) CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 TMR1H Timer1 Register High Byte TMR1L Timer1 Register Low Byte TMR2 Timer2 Register TMR3H Timer3 Register High Byte TMR3L Timer3 Register Low Byte TMR4 Timer4 Register TMR6 Timer6 Register TMR8 Timer8 Register TMR10(1) TMR10 Register TMR12(1) TMR10 Register PR2 Timer2 Period Register PR4 Timer4 Period Register PR6 Timer6 Period Register PR8 Timer8 Period Register PR10(1) Timer10 Period Register PR12(1) Timer12 Period Register Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22). 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. DS30009960F-page 270  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 20-4: REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND TIMER1/2/3/4/6/8/10/12 (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16 TMR3ON T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 T8CON — T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 TMR8ON T8CKPS1 T8CKPS0 T10CON(1) — T10OUTPS3 T10OUTPS2 T10OUTPS1 T10OUTPS0 TMR10ON T10CKPS1 T10CKPS0 T12CON(1) — T12OUTPS3 T12OUTPS2 T12OUTPS1 T12OUTPS0 TMR12ON T12CKPS1 T12CKPS0 CCPR1H Capture/Compare/PWM Register 1 High Byte CCPR1L Capture/Compare/PWM Register 1 Low Byte CCPR2H Capture/Compare/PWM Register 2 High Byte CCPR2L Capture/Compare/PWM Register 2 Low Byte CCPR3H Capture/Compare/PWM Register 3 High Byte CCPR3L Capture/Compare/PWM Register 3 Low Byte CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 CCP3CON CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22). 2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.  2009-2018 Microchip Technology Inc. DS30009960F-page 271

PIC18F87K22 FAMILY 21.0 MASTER SYNCHRONOUS Note: The SSPxBUF register cannot be used with SERIAL PORT (MSSP) read-modify-write instructions, such as BCF, MODULE COMF, etc. To avoid lost data in Master mode, a read of the SSPxBUF must be performed to clear the 21.1 Master SSP (MSSP) Module Buffer Full (BF) detect bit (SSPSTAT<0>) Overview between each transmission. The Master Synchronous Serial Port (MSSP) module is 21.3 SPI Mode a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral The SPI mode allows eight bits of data to be devices may be serial EEPROMs, shift registers, synchronously transmitted and received display drivers, A/D Converters, etc. The MSSP simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are module can operate in one of two modes: used: • Serial Peripheral Interface (SPI) • Serial Data Out (SDOx) – RC5/SDO1 or • Inter-Integrated Circuit (I2C) RD4/PSP4/SDO2 - Full Master mode • Serial Data In (SDIx) – RC4/SDI1/SDA1 or RD5/PSP5/SDI2/SDA2 - Slave mode (with general address call) • Serial Clock (SCKx) – RC3/SCK1/SCL1 or The I2C interface supports the following modes in RD6/PSP6/SCK2/SCL2 hardware: Additionally, a fourth pin may be used when in a Slave • Master mode mode of operation: • Multi-Master mode • Slave Select (SSx) – RF7/AN5/SS1 or RD7/SS2 • Slave mode with 5-bit and 7-bit address masking Figure21-1 shows the block diagram of the MSSP (with address masking for both 10-bit and 7-bit module when operating in SPI mode. addressing) FIGURE 21-1: MSSP BLOCK DIAGRAM All members of the PIC18F87K22 family have two (SPIMODE) MSSP modules, designated as MSSP1 and MSSP2. Internal Each module operates independently of the other. Data Bus Note: Throughout this section, generic refer- Read Write ences to an MSSP module in any of its operating modes may be interpreted as SSPxBUF reg being equally applicable to MSSP1 or MSSP2. Register names and module I/O signals use the generic designator ‘x’ to SDIx indicate the use of a numeral to distinguish SSPxSR reg a particular module when required. Control SDOx bit 0 Shift bit names are not individuated. Clock 21.2 Control Registers Each MSSP module has three associated control regis- SSx SSxControl ters. These include a status register (SSPxSTAT) and Enable two control registers (SSPxCON1 and SSPxCON2). The Edge use of these registers and their individual configuration Select bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. 2 Clock Select Additional details are provided under the individual sections. SSPM<3:0> Note: In devices with more than one MSSP SCKx SMP:C2KE 4 ( T M R 2 2 O u t p u t ) module, it is very important to pay close Edge attention to SSPxCON register names. Select Prescaler TOSC SSP1CON1 and SSP1CON2 control 4, 16, 64 different operational aspects of the same Data to TXx/RXx in SSPxSR module, while SSP1CON1 and TRIS bit SSP2CON1 control the same features for Note: Only port I/O names are used in this diagram for the two different modules. sake of brevity. Refer to the text for a full list of multiplexed functions. DS30009960F-page 272  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data Each MSSP module has four registers for SPI mode bytes are written to or read from. operation. These are: In receive operations, SSPxSR and SSPxBUF • MSSPx Control Register 1 (SSPxCON1) together create a double-buffered receiver. When • MSSPx Status Register (SSPxSTAT) SSPxSR receives a complete byte, it is transferred to • Serial Receive/Transmit Buffer Register SSPxBUF and the SSPxIF interrupt is set. (SSPxBUF) During transmission, the SSPxBUF is not • MSSPx Shift Register (SSPxSR) – Not directly double-buffered. A write to SSPxBUF will write to both accessible SSPxBUF and SSPxSR. SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. REGISTER 21-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE(1) D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data is sampled at the end of data output time 0 = Input data is sampled at the middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Transmit occurs on the transition from active to Idle clock state 0 = Transmit occurs on the transition from Idle to active clock state bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSPx module is disabled; SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive is complete, SSPxBUF is full 0 = Receive is not complete, SSPxBUF is empty Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>).  2009-2018 Microchip Technology Inc. DS30009960F-page 273

PIC18F87K22 FAMILY REGISTER 21-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for the clock is a high level 0 = Idle state for the clock is a low level bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3) 1010 = SPI Master mode: clock = FOSC/8 0101 = SPI Slave mode: clock = SCKx pin; SSx pin control disabled; SSx can be used as I/O pin 0100 = SPI Slave mode: clock = SCKx pin; SSx pin control enabled 0011 = SPI Master mode: clock = TMR2 output/2 0010 = SPI Master mode: clock = FOSC/64 0001 = SPI Master mode: clock = FOSC/16 0000 = SPI Master mode: clock = FOSC/4 Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, these pins must be properly configured as inputs or outputs. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. DS30009960F-page 274  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.3.2 OPERATION When the application software is expecting to receive valid data, the SSPxBUF should be read before the next When initializing the SPI, several options need to be byte of data to transfer is written to the SSPxBUF. The specified. This is done by programming the appropriate Buffer Full bit, BF (SSPxSTAT<0>), indicates when control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). SSPxBUF has been loaded with the received data These control bits allow the following to be specified: (transmission is complete). When the SSPxBUF is read, • Master mode (SCKx is the clock output) the BF bit is cleared. This data may be irrelevant if the • Slave mode (SCKx is the clock input) SPI is only a transmitter. Generally, the MSSP interrupt • Clock Polarity (Idle state of SCKx) is used to determine when the transmission/reception has completed. If the interrupt method is not going to be • Data Input Sample Phase (middle or end of data used, then software polling can be done to ensure that a output time) write collision does not occur. Example21-1 shows the • Clock Edge (output data on rising/falling edge of loading of the SSPxBUF (SSPxSR) for data SCKx) transmission. • Clock Rate (Master mode only) The SSPxSR is not directly readable or writable and • Slave Select mode (Slave mode only) can only be accessed by addressing the SSPxBUF Each MSSP module consists of a Transmit/Receive register. Additionally, the SSPxSTAT register indicates Shift register (SSPxSR) and a Serial Input Buffer regis- the various status conditions. ter (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data 21.3.3 OPEN-DRAIN OUTPUT OPTION that was written to the SSPxSR until the received data The drivers for the SDOx output and SCKx clock pins is ready. Once the 8 bits of data have been received, can be optionally configured as open-drain outputs. that byte is moved to the SSPxBUF register. Then, the This feature allows the voltage level on the pin to be Buffer Full detect bit, BF (SSPxSTAT<0>), and the pulled to a higher level through an external pull-up interrupt flag bit, SSPxIF, are set. This double-buffering resistor, and allows the output to communicate with of the received data (SSPxBUF) allows the next byte to external circuits without the need for additional level start reception before reading the data that was just shifters. For more information, see Section12.1.3 received. Any write to the SSPxBUF register during “Open-Drain Outputs”. transmission/reception of data will be ignored and the The open-drain output option is controlled by the Write Collision Detect bit, WCOL (SSPxCON1<7>), will SSP2OD and SSP1OD bits (ODCON3<1:0>). Setting be set. User software must clear the WCOL bit so that an SSPxOD bit configures the SDOx and SCKx pins for it can be determined if the following write(s) to the the corresponding module for open-drain operation. SSPxBUF register completed successfully. Note: To avoid lost data in Master mode, a read of the SSPxBUF must be per- formed to clear the Buffer Full (BF) detect bit (SSPxSTAT<0>) between each transmission. EXAMPLE 21-1: LOADING THE SSP1BUF (SSP1SR) REGISTER LOOP BTFSS SSP1STAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSP1BUF, W ;WREG reg = contents of SSP1BUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSP1BUF ;New data to xmit  2009-2018 Microchip Technology Inc. DS30009960F-page 275

PIC18F87K22 FAMILY 21.3.4 ENABLING SPI I/O Any serial port function that is not desired may be overridden by programming the corresponding Data To enable the serial port, MSSP Enable bit, SSPEN Direction (TRIS) register to the opposite value. (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the 21.3.5 TYPICAL CONNECTION SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as Figure21-2 shows a typical connection between two serial port pins. For the pins to behave as the serial port microcontrollers. The master controller (Processor 1) function, some must have their data direction bits (in initiates the data transfer by sending the SCKx signal. the TRIS register) appropriately programmed as Data is shifted out of both shift registers on their pro- follows: grammed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to • SDIx must have the TRISC<4> or TRISD<5> bit set the same Clock Polarity (CKP), then both controllers • SDOx must have the TRISC<5> or TRISD<4> bit would send and receive data at the same time. cleared Whether the data is meaningful (or dummy data) • SCKx (Master mode) must have the TRISC<3> or depends on the application software. This leads to TRISD<6>bit cleared three scenarios for data transmission: • SCKx (Slave mode) must have the TRISC<3> or • Master sends data–Slave sends dummy data TRISD<6> bit set • Master sends data–Slave sends data • SSx must have the TRISF<7> or TRISD<7> bit set • Master sends dummy data–Slave sends data FIGURE 21-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDOx SDIx Serial Input Buffer Serial Input Buffer (SSPxBUF) (SSPxBUF) SDIx SDOx Shift Register Shift Register (SSPxSR) (SSPxSR) MSb LSb MSb LSb Serial Clock SCKx SCKx PROCESSOR 1 PROCESSOR 2 DS30009960F-page 276  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.3.6 MASTER MODE shown in Figure21-3, Figure21-5 and Figure21-6, where the MSB is transmitted first. In Master mode, the The master can initiate the data transfer at any time SPI clock rate (bit rate) is user-programmable to be one because it controls the SCKx. The master determines of the following: when the slave (Processor 1, Figure21-2) is to broadcast data by the software protocol. • FOSC/4 (or TCY) In Master mode, the data is transmitted/received as • FOSC/16 (or 4 • TCY) soon as the SSPxBUF register is written to. If the SPI • FOSC/64 (or 16 • TCY) is only going to receive, the SDOx output could be dis- • Timer2 output/2 abled (programmed as an input). The SSPxSR register This allows a maximum data rate (at 40MHz) of will continue to shift in the signal present on the SDIx 10.00Mbps. pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as Figure21-3 shows the waveforms for Master mode. if a normal received byte (interrupts and status bits When the CKE bit is set, the SDOx data is valid before appropriately set). This could be useful in receiver there is a clock edge on SCKx. The change of the input applications as a “Line Activity Monitor” mode. sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received The clock polarity is selected by appropriately data is shown. programming the CKP bit (SSPxCON1<4>). This, then, would give waveforms for SPI communication, as FIGURE 21-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDIx (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF Next Q4 Cycle SSPxSR to after Q2 SSPxBUF  2009-2018 Microchip Technology Inc. DS30009960F-page 277

PIC18F87K22 FAMILY 21.3.7 SLAVE MODE transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable In Slave mode, the data is transmitted and received as depending on the application. the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Note: When the SPI is in Slave mode with the SSx pin While in Slave mode, the external clock is supplied by control enabled (SSPxCON1<3:0>=0100), the external clock source on the SCKx pin. This the SPI module will reset if the SSx pin is set to external clock must meet the minimum high and low VDD. times as specified in the electrical specifications. If the SPI is used in Slave mode with CKE While in Sleep mode, the slave can transmit/receive set, then the SSx pin control must be data. When a byte is received, the device can be enabled. configured to wake up from Sleep. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SSx pin to 21.3.8 SLAVE SELECT a high level or clearing the SSPEN bit. SYNCHRONIZATION To emulate two-wire communication, the SDOx pin can The SSx pin allows a Synchronous Slave mode. The be connected to the SDIx pin. When the SPI needs to SPI must be in Slave mode with the SSx pin control operate as a receiver, the SDOx pin can be configured enabled (SSPxCON1<3:0> = 04h). When the SSx pin as an input. This disables transmissions from the is low, transmission and reception are enabled and the SDOx. The SDIx can always be left as an input (SDIx SDOx pin is driven. When the SSx pin goes high, the function) since it cannot create a bus conflict. SDOx pin is no longer driven, even if in the middle of a FIGURE 21-4: SLAVE SYNCHRONIZATION WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 7 bit 0 SDIx bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2 SSPxBUF DS30009960F-page 278  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 21-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2 SSPxBUF FIGURE 21-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2 SSPxSR to SSPxBUF  2009-2018 Microchip Technology Inc. DS30009960F-page 279

PIC18F87K22 FAMILY 21.3.9 OPERATION IN POWER-MANAGED 21.3.11 BUS MODE COMPATIBILITY MODES Table21-1 shows the compatibility between the In SPI Master mode, module clocks may be operating standard SPI modes and the states of the CKP and at a different speed than when in Full-Power mode. In CKE control bits. the case of Sleep mode, all clocks are halted. TABLE 21-1: SPI BUS MODES In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the Control Bits State Standard SPI Mode secondary clock (SOSC oscillator) or the INTOSC Terminology CKP CKE source. See Section3.3 “Clock Sources and Oscillator Switching” for additional information. 0, 0 0 1 In most cases, the speed that the master clocks SPI 0, 1 0 0 data is not important; however, this should be 1, 0 1 1 evaluated for each system. 1, 1 1 0 If MSSP interrupts are enabled, they can wake the con- There is also an SMP bit which controls when the data troller from Sleep mode, or one of the Idle modes, when is sampled. the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts 21.3.12 SPI CLOCK SPEED AND MODULE should be disabled. INTERACTIONS If the Sleep mode is selected, all module clocks are Because MSSP1 and MSSP2 are independent halted and the transmission/reception will remain in modules, they can operate simultaneously at different that state until the device wakes. After the device data rates. Setting the SSPM<3:0> bits of the SSPx- returns to Run mode, the module will resume CON1 register determines the rate for the transmitting and receiving data. corresponding module. In SPI Slave mode, the SPI Transmit/Receive Shift An exception is when both modules use Timer2 as a register operates asynchronously to the device. This time base in Master mode. In this instance, any allows the device to be placed in any power-managed changes to the Timer2 module’s operation will affect mode and data to be shifted into the SPI both MSSP modules equally. If different bit rates are Transmit/Receive Shift register. When all 8 bits have required for each module, the user should select one of been received, the MSSP interrupt flag bit will be set, the other three time base options for one of the and if enabled, will wake the device. modules. 21.3.10 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. DS30009960F-page 280  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 21-2: REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR2 OSCFIF — SSP2IF BCL2IF BCL1IF HLVDIF TMR3IF TMR3GIF PIE2 OSCFIE — SSP2IE BCL2IE BCL1IE HLVDIE TMR3IE TMR3GIE IPR2 OSCFIP — SSP2IP BCL2IP BCL1IP HLVDIP TMR3IP TMR3GIP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — SSP1BUF MSSP1 Receive Buffer/Transmit Register SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN SSP1STAT SMP CKE D/A P S R/W UA BF SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN SSP2STAT SMP CKE D/A P S R/W UA BF SSP2BUF MSSP2 Receive Buffer/Transmit Register ODCON1 SSP1OD CCP2OD CCP1OD — — — — SSP2OD PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Legend: Shaded cells are not used by the MSSP module in SPI mode.  2009-2018 Microchip Technology Inc. DS30009960F-page 281

PIC18F87K22 FAMILY 21.4 I2C Mode 21.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has seven registers for I2C master and slave functions (including general call operation. These are: support), and provides interrupts on Start and Stop bits • MSSPx Control Register 1 (SSPxCON1) in hardware to determine a free bus (multi-master • MSSPx Control Register 2 (SSPxCON2) function). The MSSP module implements the standard • MSSPx Status Register (SSPxSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPxBUF) Two pins are used for data transfer: • MSSPx Shift Register (SSPxSR) – Not directly • Serial Clock (SCLx) – RC3/SCK1/SCL1 or accessible RD6/SCK2/SCL2 • MSSPx Address Register (SSPxADD) • Serial Data (SDAx) – RC4/SDI1/SDA1 or • I2C Slave Address Mask Register (SSPxMSK) RD5/SDI2/SDA2 SSPxCON1, SSPxCON2 and SSPxSTAT are the The user must configure these pins as inputs by setting control and status registers in I2C mode operation. The the associated TRIS bits. SSPxCON1 and SSPxCON2 registers are readable and writable. The lower 6 bits of the SSPxSTAT are FIGURE 21-7: MSSP BLOCK DIAGRAM read-only. The upper two bits of the SSPxSTAT are (I2C MODE) read/write. SSPxSR is the shift register used for shifting data in or Internal out. SSPxBUF is the buffer register to which data Data Bus bytes are written to or read from. Read Write SSPxADD contains the slave device address when the MSSP is configured in I2C Slave mode. When the SSPxBUF reg SCLx MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator Shift reload value. Clock SSPxSR reg SSPxMSK holds the slave address mask value when SDAx MSb LSb the module is configured for 7-Bit Address Masking mode. While it is a separate register, it shares the same SFR address as SSPxADD; it is only accessible when Match Detect Addr Match the SSPM<3:0> bits are specifically set to permit Address Mask access. Additional details are provided in Section21.4.3.4 “7-Bit Address Masking Mode”. In receive operations, SSPxSR and SSPxBUF SSPxADD reg together, create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. Start and Set, Reset Stop bit Detect S, P bits During transmission, the SSPxBUF is not (SSPxSTAT reg) double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. DS30009960F-page 282  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 21-3: SSPxSTAT: MSSPx STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control is enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus-specific inputs 0 = Disable SMBus-specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode.  2009-2018 Microchip Technology Inc. DS30009960F-page 283

PIC18F87K22 FAMILY REGISTER 21-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: SCKx Release Control bit In Slave mode: 1 = Releases clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(2) 1111 = I2C Slave mode: 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode: 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1001 = Load SSPMSK register at SSPxADD SFR address(3,4) 1000 = I2C Master mode: clock = FOSC/(4 * (SSPxADD + 1)) 0111 = I2C Slave mode: 10-bit address 0110 = I2C Slave mode: 7-bit address Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs. 2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. 3: When SSPM<3:0> = 1001, any reads or writes to the SSPxADD SFR address actually accesses the SSPxMSK register. 4: This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit is ‘1’). DS30009960F-page 284  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 21-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit Unused in Master mode. bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence is Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive is Idle bit 2 PEN: Stop Condition Enable bit(2) 1 = Initiates Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition is Idle bit 1 RSEN: Repeated Start Condition Enable bit(2) 1 = Initiates Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition is Idle bit 0 SEN: Start Condition Enable bit(2) 1 = Initiates Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition is Idle Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).  2009-2018 Microchip Technology Inc. DS30009960F-page 285

PIC18F87K22 FAMILY REGISTER 21-6: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit 1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address is disabled bit 6 ACKSTAT: Acknowledge Status bit Unused in Slave mode. bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit(1) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence is Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(1) 1 = Enables Receive mode for I2C 0 = Receive is Idle bit 2 PEN: Stop Condition Enable bit(1) 1 = Initiates Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition is Idle bit 1 RSEN: Repeated Start Condition Enable bit(1) 1 = Initiates Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition is Idle bit 0 SEN: Stretch Enable bit(1) 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). REGISTER 21-7: SSPxMSK: I2C SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 MSK<7:0>: Slave Address Mask Select bit 1 = Masking of corresponding bit of SSPxADD is enabled 0 = Masking of corresponding bit of SSPxADD is disabled Note 1: This register shares the same SFR address as SSPxADD and is only addressable in select MSSPx operating modes. See Section21.4.3.4 “7-Bit Address Masking Mode” for more details. 2: MSK0 is not used as a mask bit in 7-bit addressing. DS30009960F-page 286  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.4.2 OPERATION 21.4.3.1 Addressing The MSSP module functions are enabled by setting the Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPxCON1<5>). a Start condition to occur. Following the Start condition, The SSPxCON1 register allows control of the I2C the 8 bits are shifted into the SSPxSR register. All incoming bits are sampled with the rising edge of the operation. Four mode selection bits (SSPxCON1<3:0>) allow one of the following I2C modes to be selected: clock (SCLx) line. The value of register, SSPxSR<7:1>, is compared to the value of the SSPxADD register. The • I2C Master mode, clock address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCLx) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) with Start and 1. The SSPxSR register value is loaded into the Stop bit interrupts enabled SSPxBUF register. • I2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is 4. The MSSP Interrupt Flag bit, SSPxIF, is set (and Idle an interrupt is generated, if enabled) on the Selection of any I2C mode with the SSPEN bit set falling edge of the ninth SCLx pulse. forces the SCLx and SDAx pins to be open-drain, In 10-Bit Addressing mode, two address bytes need to provided these pins are programmed as inputs by be received by the slave. The five Most Significant bits setting the appropriate TRISC or TRISD bits. To ensure (MSbs) of the first address byte specify if this is a 10-bit proper operation of the module, pull-up resistors must address. The R/W (SSPxSTAT<2>) bit must specify a be provided externally to the SCLx and SDAx pins. write so the slave device will receive the second address byte. For a 10-bit address, the first byte would 21.4.3 SLAVE MODE equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the In Slave mode, the SCLx and SDAx pins must be two MSbs of the address. The sequence of events for configured as inputs (TRISC<4:3> set). The MSSP 10-bit addressing is as follows, with Steps 7 through 9 module will override the input state with the output data for the slave-transmitter: when required (slave-transmitter). 1. Receive first (high) byte of address (bits, The I2C Slave mode hardware will always generate an SSPxIF, BF and UA, are set on address match). interrupt on an address match. Address masking will 2. Update the SSPxADD register with second (low) allow the hardware to generate an interrupt for more byte of address (clears bit, UA, and releases the than one address (up to 31 in 7-bit addressing and up SCLx line). to 63 in 10-bit addressing). Through the mode select 3. Read the SSPxBUF register (clears bit, BF) and bits, the user can also choose to interrupt on Start and clear flag bit, SSPxIF. Stop bits. 4. Receive second (low) byte of address (bits, When an address is matched, or the data transfer after SSPxIF, BF and UA, are set). an address match is received, the hardware auto- 5. Update the SSPxADD register with the first matically will generate the Acknowledge (ACK) pulse (high) byte of address. If match releases SCLx and load the SSPxBUF register with the received value line, this will clear bit, UA. currently in the SSPxSR register. 6. Read the SSPxBUF register (clears bit, BF) and Any combination of the following conditions will cause clear flag bit, SSPxIF. the MSSP module not to give this ACK pulse: 7. Receive Repeated Start condition. • The Buffer Full bit, BF (SSPxSTAT<0>), was set 8. Receive first (high) byte of address (bits, before the transfer was received. SSPxIF and BF, are set). • The overflow bit, SSPOV (SSPxCON1<6>), was 9. Read the SSPxBUF register (clears bit, BF) and set before the transfer was received. clear flag bit, SSPxIF. In this case, the SSPxSR register value is not loaded into the SSPxBUF, but bit, SSPxIF, is set. The BF bit is cleared by reading the SSPxBUF register, while bit, SSPOV, is cleared through software. The SCLx clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing Parameter 100 and Parameter 101.  2009-2018 Microchip Technology Inc. DS30009960F-page 287

PIC18F87K22 FAMILY 21.4.3.2 Address Masking Modes Acknowledge up to 31 addresses when using 7-bit addressing, or 63 addresses with 10-bit addressing Masking an address bit causes that bit to become a (see Example21-2). This Masking mode is selected “don’t care”. When one address bit is masked, two when the MSSPMSK Configuration bit is programmed addresses will be Acknowledged and cause an (‘0’). interrupt. It is possible to mask more than one address bit at a time, which greatly expands the number of The address mask in this mode is stored in the SSPx- addresses Acknowledged. CON2 register, which stops functioning as a control The I2C slave behaves the same way whether address register in I2C Slave mode (Register21-6). In 7-Bit Address Masking mode, address mask bits, masking is used or not. However, when address masking is used, the I2C slave can Acknowledge ADMSK<5:1> (SSPxCON2<5:1>), mask the corre- sponding address bits in the SSPxADD register. For multiple addresses and cause interrupts. When this any ADMSK bits that are set (ADMSK<n>=1), the cor- occurs, it is necessary to determine which address responding address bit is ignored (SSPxADD<n>=x). caused the interrupt by checking the SSPxBUF. For the module to issue an address Acknowledge, it is The PIC18F87K22 family of devices is capable of using sufficient to match only on addresses that do not have two different Address Masking modes in I2C slave an active address mask. operation: 5-Bit Address Masking and 7-Bit Address In 10-Bit Address Masking mode, bits, ADMSK<5:2>, Masking. The Masking mode is selected at device mask the corresponding address bits in the SSPxADD configuration using the MSSPMSK Configuration bit. register. In addition, ADMSK1 simultaneously masks The default device configuration is 7-Bit Address the two LSbs of the address (SSPxADD<1:0>). For any Masking. ADMSK bits that are active (ADMSK<n>=1), the cor- Both Masking modes, in turn, support address masking responding address bit is ignored (SPxADD<n>=x). of 7-bit and 10-bit addresses. The combination of Also note, that although in 10-Bit Address Masking Masking modes and addresses provides different mode, the upper address bits reuse part of the ranges of Acknowledgable addresses for each SSPxADD register bits. The address mask bits do not combination. interact with those bits; they only affect the lower While both Masking modes function in roughly the address bits. same manner, the way they use address masks are Note1: ADMSK1 masks the two Least Significant different. bits of the address. 21.4.3.3 5-Bit Address Masking Mode 2: The two Most Significant bits of the address are not affected by address As the name implies, 5-Bit Address Masking mode masking. uses an address mask of up to 5 bits to create a range of addresses to be Acknowledged, using bits, 5 through 1, of the incoming address. This allows the module to EXAMPLE 21-2: ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE 7-Bit Addressing: SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be ‘0’) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh 10-Bit Addressing: SSPxADD<7:0> = A0h (10100000) (The two MSb of the address are ignored in this example, since they are not affected by masking) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh DS30009960F-page 288  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.4.3.4 7-Bit Address Masking Mode Setting or clearing mask bits in SSPxMSK behaves in the opposite manner of the ADMSK bits in 5-Bit Unlike 5-bit masking, 7-Bit Address Masking mode Address Masking mode. That is, clearing a bit in uses a mask of up to 8 bits (in 10-bit addressing) to SSPxMSK causes the corresponding address bit to be define a range of addresses that can be Acknowl- masked; setting the bit requires a match in that edged, using the lowest bits of the incoming address. position. SSPxMSK resets to all ‘1’s upon any Reset This allows the module to Acknowledge up to condition and, therefore, has no effect on the standard 127different addresses with 7-bit addressing, or 255 MSSP operation until written with a mask value. with 10-bit addressing (see Example21-3). This mode is the default configuration of the module, which is With 7-bit addressing, SSPxMSK<7:1> bits mask the selected when MSSPMSK is unprogrammed (‘1’). corresponding address bits in the SSPxADD register. For any SSPxMSK bits that are active The address mask for 7-Bit Address Masking mode is (SSPxMSK<n>=0), the corresponding SSPxADD stored in the SSPxMSK register, instead of the SSPx- address bit is ignored (SSPxADD<n>=x). For the CON2 register. SSPxMSK is a separate hardware reg- module to issue an address Acknowledge, it is ister within the module, but it is not directly sufficient to match only on addresses that do not have addressable. Instead, it shares an address in the SFR an active address mask. space with the SSPxADD register. To access the SSPxMSK register, it is necessary to select MSSP With 10-bit addressing, SSPxMSK<7:0> bits mask the mode, ‘1001’ (SSPxCON1<3:0> = 1001) and then corresponding address bits in the SSPxADD register. read or write to the location of SSPxADD. For any SSPxMSK bits that are active (= 0), the corre- sponding SSPxADD address bit is ignored To use 7-Bit Address Masking mode, it is necessary to (SSPxADD<n>=x). initialize SSPxMSK with a value before selecting the I2C Slave Addressing mode. Thus, the required Note: The two Most Significant bits of the sequence of events is: address are not affected by address 1. Select SSPxMSK Access mode (SSPx- masking. CON2<3:0> = 1001). 2. Write the mask value to the appropriate SSPADD register address (FC8h for MSSP1, F6Eh for MSSP2). 3. Set the appropriate I2C Slave mode (SSPx- CON2<3:0> = 0111 for 10-bit addressing, ‘0110’ for 7-bit addressing). EXAMPLE 21-3: ADDRESS MASKING EXAMPLES IN 7-BIT MASKING MODE 7-Bit Addressing: SSPxADD<7:1> = 1010 000 SSPxMSK<7:1> = 1111 001 Addresses Acknowledged = ACh, A8h, A4h, A0h 10-Bit Addressing: SSPxADD<7:0> = 1010 0000 (The two MSb are ignored in this example since they are not affected) SSPxMSK<5:1> = 1111 0011 Addresses Acknowledged = ACh, A8h, A4h, A0h  2009-2018 Microchip Technology Inc. DS30009960F-page 289

PIC18F87K22 FAMILY 21.4.3.5 Reception 21.4.3.6 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPxSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPxSTAT register is set. The received address is the SSPxBUF register and the SDAx line is held low loaded into the SSPxBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin SCLx is held low regard- less of SEN (see Section21.4.4 “Clock Stretching” When the address byte overflow condition exists, then for more details). By stretching the clock, the master the no Acknowledge (ACK) pulse is given. An overflow will be unable to assert another clock pulse until the condition is defined as either bit, BF (SSPxSTAT<0>), slave is done preparing the transmit data. The transmit is set or bit, SSPOV (SSPxCON1<6>), is set. data must be loaded into the SSPxBUF register which An MSSP interrupt is generated for each data transfer also loads the SSPxSR register. Then, pin SCLx should byte. The interrupt flag bit, SSPxIF, must be cleared in be enabled by setting bit, CKP (SSPxCON1<4>). The software. The SSPxSTAT register is used to determine eight data bits are shifted out on the falling edge of the the status of the byte. SCLx input. This ensures that the SDAx signal is valid If SEN is enabled (SSPxCON2<0> = 1), SCLx will be during the SCLx high time (Figure21-10). held low (clock stretch) following each data transfer. The The ACK pulse from the master-receiver is latched on clock must be released by setting bit, CKP the rising edge of the ninth SCLx input pulse. If the (SSPxCON1<4>). See Section21.4.4 “Clock SDAx line is high (not ACK), then the data transfer is Stretching” for more details. complete. In this case, when the ACK is latched by the slave, the slave logic is reset and the slave monitors for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, pin SCLx must be enabled by setting bit, CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. DS30009960F-page 290  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 2 FIGURE 21-8: I C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 ec R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e Receiving D5D4 34 ared in softwarPxBUF is read D6 2 CleSS 7 D 1 K 9 = 0 AC W 8 R/ A1 7 2 )0 A 6 = ddress A3 5 n SEN A e Receiving A5A4 34 eset to ‘’ wh0 SDAxA7A6 SCLx12S SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP (SSPxCON<4>) (CKP does not r  2009-2018 Microchip Technology Inc. DS30009960F-page 291

PIC18F87K22 FAMILY 2 FIGURE 21-9: I C SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 pt. u D1 7 nterr n i D2 6 e a s u Data D3 5 e d ca eceiving D4 4 n softwarF is read dged an R D5 3 ared iPxBU owle D6 2 CleSS Ackn e D7 1 ’).0 X will b K 9 a ‘ X. R/W = 0 AC 8 a ‘’ or 1 5.X.A3. X 7 her be 7.A6.A Receiving Address SDAxA7A6A5XA3X SCLx123456S SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP (SSPxCON<4>) (CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can eitx 2:In this example, an address equal to A DS30009960F-page 292  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 2 FIGURE 21-10: I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S K F I AC 9 PxI S D0 8 m S o Data D1 7 Fr Transmitting D5D4D3D2 3456 eared in software UF is written in software et in software D6 2 Cl SSPxB KP is s C D7 1 R S ACK 9 PxIF I S S D0 8 m o Fr D1 7 Transmitting Data D6D7D5D4D3D2 234561 SCLx held lowwhile CPUresponds to SSPxIF Cleared in software SSPxBUF is written in software Clear by reading CKP is set in software K C A 9 1 = W 8 R/ 1 A 7 ess A2 6 Addr A3 5 g n eivi A4 4 ec R A5 3 >) 7 A6A7 12 Data in sampled > or PIR3< 0>) <4>) 3 < N DAx CLx S SPxIF (PIR1< F (SSPxSTAT KP (SSPxCO S S S B C  2009-2018 Microchip Technology Inc. DS30009960F-page 293

PIC18F87K22 FAMILY FIGURE 21-11: I2C SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n eceive Dat D5D4 34 Cleared i R D6 2 7 D 1 K AC 9 0 D 8 untilDD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPxADD is updated with highbyte of address nd cause an interrupt. Clock is held low Clock is held low untilupdate of SSPxAupdate of SSPxADD has taken placetaken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACKACKDAx11110A9A8A7A6A5XA3A2XXD7 CLx1234567891234567891S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPxADD needs to bewhen SSPxADD is updatedupdatedwith low byte of address UA is set indicating thatSSPxADD needs to beupdatedKP (SSPxCON<4>) (CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can either be a ‘’ or a ‘’).x10 2:In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged a 3:Note that the Most Significant bits of the address are not affected by the bit masking. S S S B S U C DS30009960F-page 294  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 21-12: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n eceive Dat D5D4 34 Cleared i R D6 2 7 D 1 K AC 9 0 D 8 untilDD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPxADD is updated with highbyte of address d low SPxA D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACKDAx11110A9A8A7A6A5A4A3A2A1 CLx1234567891234567S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPxADD needs to bewhen SSPxADD is updatedupdatedwith low byte of address UA is set indicating thatSSPxADD needs to beupdatedKP (SSPxCON<4>) (CKP does not reset to ‘’ when SEN = )00 S S S B S U C  2009-2018 Microchip Technology Inc. DS30009960F-page 295

PIC18F87K22 FAMILY 2 FIGURE 21-13: I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCLx low w Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressTransmitting Data ByteR/W = 1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPxBUFWrite of SSPxBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPxADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPxADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with lowbyte of address UA is set indicating thatSSPxADD needs to beupdated R/ 8 h be Receive First Byte of Address DAx11110A9A8 CLx1234567S SPxIF (PIR1<3> or PIR3<7>) F (SSPxSTAT<0>) SSPxBUF is written witcontents of SSPxSR A (SSPxSTAT<1>) UA is set indicating thatthe SSPxADD needs to updated KP (SSPxCON1<4>) S S S B U C DS30009960F-page 296  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.4.4 CLOCK STRETCHING Note: If the user polls the UA bit and clears it by Both 7-Bit and 10-Bit Slave modes implement updating the SSPxADD register before the automatic clock stretching during a transmit sequence. falling edge of the ninth clock occurs, and if the user hasn’t cleared the BF bit by The SEN bit (SSPxCON2<0>) allows clock stretching reading the SSPxBUF register before that to be enabled during receives. Setting SEN will cause time, then the CKP bit will still NOT be the SCLx pin to be held low at the end of each data asserted low. Clock stretching, on the receive sequence. basis of the state of the BF bit, only occurs 21.4.4.1 Clock Stretching for 7-Bit Slave during a data sequence, not an address sequence. Receive Mode (SEN = 1) In 7-Bit Slave Receive mode, on the falling edge of the 21.4.4.3 Clock Stretching for 7-Bit Slave ninth clock at the end of the ACK sequence, if the BF Transmit Mode bit is set, the CKP bit in the SSPxCON1 register is The 7-Bit Slave Transmit mode implements clock automatically cleared, forcing the SCLx output to be stretching by clearing the CKP bit after the falling edge held low. The CKP bit being cleared to ‘0’ will assert of the ninth clock if the BF bit is clear. This occurs the SCLx line low. The CKP bit must be set in the regardless of the state of the SEN bit. user’s ISR before reception is allowed to continue. By holding the SCLx line low, the user has time to service The user’s ISR must set the CKP bit before transmis- the ISR and read the contents of the SSPxBUF before sion is allowed to continue. By holding the SCLx line the master device can initiate another receive low, the user has time to service the ISR and load the sequence. This will prevent buffer overruns from contents of the SSPxBUF before the master device occurring (see Figure21-15). can initiate another transmit sequence (see Figure21-10). Note1: If the user reads the contents of the SSPxBUF before the falling edge of the Note1: If the user loads the contents of ninth clock, thus clearing the BF bit, the SSPxBUF, setting the BF bit before the CKP bit will not be cleared and clock falling edge of the ninth clock, the CKP bit stretching will not occur. will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. The 2: The CKP bit can be set in software user should be careful to clear the BF bit regardless of the state of the BF bit. in the ISR before the next receive sequence in order to prevent an overflow 21.4.4.4 Clock Stretching for 10-Bit Slave condition. Transmit Mode In 10-Bit Slave Transmit mode, clock stretching is 21.4.4.2 Clock Stretching for 10-Bit Slave controlled during the first two address sequences by Receive Mode (SEN = 1) the state of the UA bit, just as it is in 10-Bit Slave In 10-Bit Slave Receive mode, during the address Receive mode. The first two addresses are followed sequence, clock stretching automatically takes place by a third address sequence, which contains the but CKP is not cleared. During this time, if the UA bit is high-order bits of the 10-bit address and the R/W bit set after the ninth clock, clock stretching is initiated. set to ‘1’. After the third address sequence is The UA bit is set after receiving the upper byte of the performed, the UA bit is not set, the module is now 10-bit address and following the receive of the second configured in Transmit mode and clock stretching is byte of the 10-bit address with the R/W bit cleared to controlled by the BF flag as in 7-Bit Slave Transmit ‘0’. The release of the clock line occurs upon updating mode (see Figure21-13). SSPxADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode.  2009-2018 Microchip Technology Inc. DS30009960F-page 297

PIC18F87K22 FAMILY 21.4.4.5 Clock Synchronization and already asserted the SCLx line. The SCLx output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx. This When the CKP bit is cleared, the SCLx output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, clearing the CKP bit will not assert the minimum high time requirement for SCLx (see SCLx output low until the SCLx output is already Figure21-14). sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 21-14: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX DX – 1 SCLx Master Device CKP Asserts Clock Master Device Deasserts Clock WR SSPxCON1 DS30009960F-page 298  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 2 FIGURE 21-15: I C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R D5 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPxBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 ss e ddr A3 5 A g eivin A4 4 c e R A5 3 >) A6 2 R3<7 >) A7 1 > or PI 0>) ON1<6 <4>) DAx CLxS SPxIF (PIR1<3 F (SSPxSTAT< SPOV (SSPxC KP (SSPxCON S S S B S C  2009-2018 Microchip Technology Inc. DS30009960F-page 299

PIC18F87K22 FAMILY FIGURE 21-16: I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) Clock is not held lowbecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D 8 1 D 7 e yte D2 6 war Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data B ACKD7D6D5D4D3D1D0D2D7D6D5D4D3 12345789612345 Cleared in softwareCleared in soft Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPxADD register beforethe falling edge of the ninth clock will have noeffect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 DAx11110A9A8A7A6A5A4A3A2A1A0ACK CLx12345678912345678S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardware whenthe SSPxADD needs to beSSPxADD is updated with lowupdatedbyte of address after falling edgeof ninth clock UA is set indicating thatSSPxADD needs to beupdated KP (SSPxCON<4>)Note:An update of the SSPxADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. S S S B S U C DS30009960F-page 300  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPxSR is SUPPORT transferred to the SSPxBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK The addressing procedure for the I2C bus is such that bit), the SSPxIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the the master. The exception is the general call address interrupt can be checked by reading the contents of the which can address all devices. When this address is SSPxBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device-specific or a general call address. Acknowledge. In 10-Bit Addressing mode, the SSPxADD is required The general call address is one of eight addresses to be updated for the second half of the address to reserved for specific purposes by the I2C protocol. It match and the UA bit is set (SSPxSTAT<1>). If the gen- consists of all ‘0’s with R/W = 0. eral call address is sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing The general call address is recognized when the mode, then the second half of the address is not General Call Enable bit, GCEN, is enabled (SSPx- necessary, the UA bit will not be set and the slave will CON2<7> set). Following a Start bit detect, eight bits begin receiving data after the Acknowledge are shifted into the SSPxSR and the address is (Figure21-17). compared against the SSPxADD. It is also compared to the general call address and fixed in hardware. FIGURE 21-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is Compared to General Call Address After ACK, Set Interrupt R/W = 0 Receiving Data ACK General Call Address SDAx ACK D7 D6 D5 D4 D3 D2 D1 D0 SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPxIF BF (SSPxSTAT<0>) Cleared in Software SSPxBUF is Read SSPOV (SSPxCON1<6>) ‘0’ GCEN (SSPxCON2<7>) ‘1’  2009-2018 Microchip Technology Inc. DS30009960F-page 301

PIC18F87K22 FAMILY 21.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPxCON1, and by setting of events. For instance, the user is not the SSPEN bit. In Master mode, the SCLx and SDAx allowed to initiate a Start condition and lines are manipulated by the MSSP hardware if the immediately write the SSPxBUF register TRIS bits are set. to initiate transmission before the Start condition is complete. In this case, the The Master mode of operation is supported by interrupt SSPxBUF will not be written to and the generation on the detection of the Start and Stop WCOL bit will be set, indicating that a write conditions. The Stop (P) and Start (S) bits are cleared to the SSPxBUF did not occur. from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is The following events will cause the MSSP Interrupt set, or the bus is Idle, with both the S and P bits clear. Flag bit, SSPxIF, to be set (and MSSP interrupt, if In Firmware Controlled Master mode, user code enabled): conducts all I2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options. • Acknowledge transmitted 1. Assert a Start condition on SDAx and SCLx. • Repeated Start 2. Assert a Repeated Start condition on SDAx and SCLx. 3. Write to the SSPxBUF register, initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDAx and SCLx. 2 FIGURE 21-18: MSSP BLOCK DIAGRAM (I C MASTER MODE) Internal SSPM<3:0> Data Bus SSPxADD<6:0> Read Write SSPxBUF Baud Rate Generator SDAx Shift SDAx In Clock ct e SSPxSR Detce) MSb LSb L ur e Oo abl WCk s SCLx Receive En StAarcGtk beninot,ew Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCLx In Write Collision Detect Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1); Clock Arbitration Set SSPxIF, BCLxIF; Bus Collision State Counter for Reset ACKSTAT, PEN (SSPxCON2) End of XMIT/RCV DS30009960F-page 302  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPxCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPxIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPxBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDAx while SCLx outputs the serial clock. The 4. Address is shifted out the SDAx pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the SSPx- transmitted, 8 bits at a time. After each byte is transmit- CON2 register (SSPxCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the end of a serial transfer. SSPxIF bit. In Master Receive mode, the first byte transmitted 7. The user loads the SSPxBUF with eight bits of contains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDAx pin until all 8 bits logic ‘1’. Thus, the first byte transmitted is a 7-bit slave are transmitted. address, followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDAx, while SCLx outputs slave device and writes its value into the SSPx- the serial clock. Serial data is received, 8 bits at a time. CON2 register (SSPxCON2<6>). After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the 10. The MSSP module generates an interrupt at the beginning and end of transmission. end of the ninth clock cycle by setting the SSPxIF bit. The Baud Rate Generator, used for the SPI mode 11. The user generates a Stop condition by setting operation, is used to set the SCLx clock frequency for either 100kHz, 400kHz or 1MHz I2C operation. See the Stop Enable bit, PEN (SSPxCON2<2>). Section21.4.7 “Baud Rate” for more details. 12. Interrupt is generated once the Stop condition is complete.  2009-2018 Microchip Technology Inc. DS30009960F-page 303

PIC18F87K22 FAMILY 21.4.7 BAUD RATE 21.4.7.1 Baud Rate and Module In I2C Master mode, the Baud Rate Generator (BRG) Interdependence reload value is placed in the lower 7 bits of the Because MSSP1 and MSSP2 are independent, they SSPxADD register (Figure21-19). When a write can operate simultaneously in I2C Master mode at occurs to SSPxBUF, the Baud Rate Generator will different baud rates. This is done by using different automatically begin counting. The BRG counts down to BRG reload values for each module. 0 and stops until another reload has taken place. The Because this mode derives its basic clock source from BRG count is decremented twice per instruction cycle the system clock, any changes to the clock will affect (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the both modules in the same proportion. It may be BRG is reloaded automatically. possible to change one or both baud rates back to a Once the given operation is complete (i.e., transmis- previous value by changing the BRG reload value. sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCLx pin will remain in its last state. Table21-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. The SSPxADD BRG value of 0x00 is not supported. FIGURE 21-19: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPxADD<6:0> SSPM<3:0> Reload Reload SCLx Control CLKO BRG Down Counter FOSC/4 TABLE 21-3: I2C CLOCK RATE w/BRG FSCL FOSC FCY FCY * 2 BRG Value (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 18h 400 kHz 40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 20 MHz 63h 100 kHz 16 MHz 4 MHz 8 MHz 09h 400 kHz 16 MHz 4 MHz 8 MHz 0Ch 308 kHz 16 MHz 4 MHz 8 MHz 27h 100 kHz 4 MHz 1 MHz 2 MHz 02h 333 kHz 4 MHz 1 MHz 2 MHz 09h 100 kHz 16 MHz 4 MHz 8 MHz 03h 1 MHz(1) Note 1: A minimum of 16 MHz FOSC is required to get 1 MHz I2C. DS30009960F-page 304  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.4.7.2 Clock Arbitration SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCLx high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCLx pin (SCLx allowed to float high). event that the clock is held low by an external device When the SCLx pin is allowed to float high, the Baud (Figure21-20). Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 21-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX DX – 1 SCLx Deasserted but Slave Holds SCLx Allowed to Transition High SCLx Low (clock arbitration) SCLx BRG Decrements on Q2 and Q4 Cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCLx is Sampled High, Reload takes Place and BRG Starts its Count BRG Reload  2009-2018 Microchip Technology Inc. DS30009960F-page 305

PIC18F87K22 FAMILY 21.4.8 I2C MASTER MODE START Note: If, at the beginning of the Start condition, CONDITION TIMING the SDAx and SCLx pins are already To initiate a Start condition, the user sets the Start sampled low, or if during the Start condi- Enable bit, SEN (SSPxCON2<0>). If the SDAx and tion, the SCLx line is sampled low before SCLx pins are sampled high, the Baud Rate Generator the SDAx line is driven low, a bus collision is reloaded with the contents of SSPxADD<6:0> and occurs, the Bus Collision Interrupt Flag, starts its count. If SCLx and SDAx are both sampled BCLxIF, is set, the Start condition is high when the Baud Rate Generator times out (TBRG), aborted and the I2C module is reset into its the SDAx pin is driven low. The action of the SDAx Idle state. being driven low while SCLx is high is the Start condi- 21.4.8.1 WCOL Status Flag tion and causes the S bit (SSPxSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded If the user writes the SSPxBUF when a Start sequence with the contents of SSPxADD<6:0> and resumes its is in progress, the WCOL bit is set and the contents of count. When the Baud Rate Generator times out the buffer are unchanged (the write doesn’t occur). (TBRG), the SEN bit (SSPxCON2<0>) will be Note: Because queueing of events is not automatically cleared by hardware. The Baud Rate allowed, writing to the lower 5 bits of Generator is suspended, leaving the SDAx line held low SSPxCON2 is disabled until the Start and the Start condition is complete. condition is complete. FIGURE 21-21: FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit Occurs Here SDAx = 1, At Completion of Start bit, SCLx = 1 Hardware Clears SEN bit and Sets SSPxIF bit TBRG TBRG Write to SSPxBUF Occurs Here 1st bit 2nd bit SDAx TBRG SCLx TBRG S DS30009960F-page 306  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPxCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDAx is sampled low when SCLx the SCLx pin is asserted low. When the SCLx pin is goes from low-to-high. sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<5:0> and begins counting. • SCLx goes low before SDAx is The SDAx pin is released (brought high) for one Baud asserted low. This may indicate that Rate Generator count (TBRG). When the Baud Rate another master is attempting to Generator times out, and if SDAx is sampled high, the transmit a data ‘1’. SCLx pin will be deasserted (brought high). When Immediately following the SSPxIF bit getting set, the SCLx is sampled high, the Baud Rate Generator is user may write the SSPxBUF with the 7-bit address in reloaded with the contents of SSPxADD<6:0> and 7-bit mode or the default first address in 10-bit mode. begins counting. SDAx and SCLx must be sampled After the first eight bits are transmitted and an ACK is high for one TBRG. This action is then followed by received, the user may then transmit an additional eight assertion of the SDAx pin (SDAx = 0) for one TBRG bits of address (10-bit mode) or eight bits of data (7-bit while SCLx is high. Following this, the RSEN bit mode). (SSPxCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the 21.4.9.1 WCOL Status Flag SDAx pin held low. As soon as a Start condition is If the user writes the SSPxBUF when a Repeated Start detected on the SDAx and SCLx pins, the S bit sequence is in progress, the WCOL is set and the (SSPxSTAT<3>) will be set. The SSPxIF bit will not be contents of the buffer are unchanged (the write doesn’t set until the Baud Rate Generator has timed out. occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPxCON2 is disabled until the Repeated Start condition is complete. FIGURE 21-22: REPEATED START CONDITION WAVEFORM S bit Set by Hardware SDAx = 1, At Completion of Start bit, Write to SSPxCON2 Occurs Here: SDAx = 1, SCLx = 1 Hardware Clears RSEN bit SCLx (no change). and Sets SSPxIF TBRG TBRG TBRG SDAx 1st bit RSEN bit Set by Hardware on Falling Edge of Ninth Clock, Write to SSPxBUF Occurs Here End of XMIT TBRG SCLx TBRG Sr = Repeated Start  2009-2018 Microchip Technology Inc. DS30009960F-page 307

PIC18F87K22 FAMILY 21.4.10 I2C MASTER MODE TRANSMISSION The user should verify that the WCOL bit is clear after each write to SSPxBUF to ensure the transfer is correct. Transmission of a data byte, a 7-bit address or the In all cases, WCOL must be cleared in software. other half of a 10-bit address, is accomplished by simply writing a value to the SSPxBUF register. This 21.4.10.3 ACKSTAT Status Flag action will set the Buffer Full flag bit, BF, and allow the In Transmit mode, the ACKSTAT bit (SSPxCON2<6>) Baud Rate Generator to begin counting and start the is cleared when the slave has sent an Acknowledge next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of (ACK=0) and is set when the slave does not Acknowl- SCLx is asserted (see data hold time specification edge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), Parameter106). SCLx is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid or when the slave has properly received its data. before SCLx is released high (see data setup time 21.4.11 I2C MASTER MODE RECEPTION specification Parameter 107). When the SCLx pin is released high, it is held that way for TBRG. The data on Master mode reception is enabled by programming the the SDAx pin must remain stable for that duration and Receive Enable bit, RCEN (SSPxCON2<3>). some hold time after the next falling edge of SCLx. Note: The MSSP module must be in an inactive After the eighth bit is shifted out (the falling edge of the state before the RCEN bit is set or the eighth clock), the BF flag is cleared and the master RCEN bit will be disregarded. releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth The Baud Rate Generator begins counting, and on bit time if an address match occurred, or if data was each rollover, the state of the SCLx pin changes received properly. The status of ACK is written into the (high-to-low/low-to-high) and data is shifted into the ACKDT bit on the falling edge of the ninth clock. If the SSPxSR. After the falling edge of the eighth clock, the master receives an Acknowledge, the Acknowledge receive enable flag is automatically cleared, the con- Status bit, ACKSTAT, is cleared; if not, the bit is set. tents of the SSPxSR are loaded into the SSPxBUF, the After the ninth clock, the SSPxIF bit is set and the BF flag bit is set, the SSPxIF flag bit is set and the Baud master clock (Baud Rate Generator) is suspended until Rate Generator is suspended from counting, holding the next data byte is loaded into the SSPxBUF, leaving SCLx low. The MSSP is now in Idle state awaiting the SCLx low and SDAx unchanged (Figure21-23). next command. When the buffer is read by the CPU, After the write to the SSPxBUF, each bit of the address the BF flag bit is automatically cleared. The user can will be shifted out on the falling edge of SCLx until all then send an Acknowledge bit at the end of reception seven address bits and the R/W bit are completed. On by setting the Acknowledge Sequence Enable bit, the falling edge of the eighth clock, the master will ACKEN (SSPxCON2<4>). deassert the SDAx pin, allowing the slave to respond 21.4.11.1 BF Status Flag with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the In receive operation, the BF bit is set when an address address was recognized by a slave. The status of the or data byte is loaded into SSPxBUF from SSPxSR. It ACK bit is loaded into the ACKSTAT status bit (SSPx- is cleared when the SSPxBUF register is read. CON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPxIF flag is set, the 21.4.11.2 SSPOV Status Flag BF flag is cleared and the Baud Rate Generator is In receive operation, the SSPOV bit is set when 8 bits turned off until another write to the SSPxBUF takes are received into the SSPxSR and the BF flag bit is place, holding SCLx low and allowing SDAx to float. already set from a previous reception. 21.4.10.1 BF Status Flag 21.4.11.3 WCOL Status Flag In Transmit mode, the BF bit (SSPxSTAT<0>) is set If the user writes the SSPxBUF when a receive is when the CPU writes to SSPxBUF and is cleared when already in progress (i.e., SSPxSR is still shifting in a all 8 bits are shifted out. data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). 21.4.10.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur) after 2TCY after the SSPxBUF write. If SSPxBUF is rewritten within 2 TCY, the WCOL bit is set and SSPxBUF is updated. This may result in a corrupted transfer. DS30009960F-page 308  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 21-23: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 AT in ON2 = oftware STxC P n s ACKSSP ared i K e >) AC 9 Cl 6 N2< D0 8 e slave, clear ACKSTAT bit (SSPxCO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared in software service routinfrom MSSP interrupt SSPxBUF is written in software om D7 1 xIF Fr ow SP = 0 SCLx held lwhile CPUsponds to S CK re = 0 A W, 9 are R/W A1 ess and R/ 78 d by hardw ave A2 addr 6 eare PxCON2<0> (SEN = ),1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPxBUF written with 7-bit start transmit 12345 Cleared in software SSPxBUF written After Start condition, SEN cl Sn So Write Start c S T<0>) A T S x F SP SDAx SCLx SSPxI BF (S SEN PEN R/W  2009-2018 Microchip Technology Inc. DS30009960F-page 309

PIC18F87K22 FAMILY FIGURE 21-24: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) et ACKEN, start Acknowledge sequence,DAx = ACKDT = 1 PEN bit = 1N clearedwritten herematically D0ACK Bus masterACK is not sentterminatestransfer98PSet SSPxIF at endof receiveSet SSPxIF interruptat end of Acknowledgesequence Set P bit (SSPxSTAT<4>)Cleared insoftwareand SSPxIF SSPOV is set becauseSSPxBUF is still full SS RCEauto D1 7 CLK Write to SSPxCON2<4>to start Acknowledge sequence,SDAx = ACKDT (SSPxCON2<5>) = 0 ACK from master,er configured as a receiverSDAx = ACKDT = 0ogramming SSPxCON2<3> (RCEN = )1 RCEN = , start1RCEN clearednext receiveautomatically Receiving Data from SlaveReceiving Data from SlaveACKD2D5D2D5D3D4D6D7D3D4D6D7D1D0 678956512343124 Data shifted in on falling edge of Set SSPxIF interruptSet SSPxIF interruptat end of receiveat end of Acknowledgesequence Cleared in softwareCleared in softwareCleared in software Last bit is shifted into SSPxSR andcontents are unloaded into SSPxBUF stpr Maby ACK from Slave R/W = 1A1ACK 798 e, Write to SSPxCON2<0> (SEN = ),1begin Start condition SEN = 0Write to SSPxBUF occurs herstart XMIT Transmit Address to Slave A7A6A5A4A3A2SDAx 361245SCLxS SSPxIF Cleared in softwareSDAx = , SCLx = ,01while CPU responds to SSPxIF BF (SSPxSTAT<0>) SSPOV ACKEN DS30009960F-page 310  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.4.12 ACKNOWLEDGE SEQUENCE 21.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDAx pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN (SSPx- bit, PEN (SSPxCON2<2>). At the end of a CON2<4>). When this bit is set, the SCLx pin is pulled low receive/transmit, the SCLx line is held low after the and the contents of the Acknowledge data bit are pre- falling edge of the ninth clock. When the PEN bit is set, sented on the SDAx pin. If the user wishes to generate an the master will assert the SDAx line low. When the Acknowledge, then the ACKDT bit should be cleared. If SDAx line is sampled low, the Baud Rate Generator is not, the user should set the ACKDT bit before starting an reloaded and counts down to 0. When the Baud Rate Acknowledge sequence. The Baud Rate Generator then Generator times out, the SCLx pin will be brought high counts for one rollover period (TBRG) and the SCLx pin is and one TBRG (Baud Rate Generator rollover count) deasserted (pulled high). When the SCLx pin is sampled later, the SDAx pin will be deasserted. When the SDAx high (clock arbitration), the Baud Rate Generator counts pin is sampled high while SCLx is high, the P bit for TBRG; the SCLx pin is then pulled low. Following this, (SSPxSTAT<4>) is set. A TBRG later, the PEN bit is the ACKEN bit is automatically cleared, the Baud Rate cleared and the SSPxIF bit is set (see Figure21-26). Generator is turned off and the MSSP module then goes 21.4.13.1 WCOL Status Flag into an inactive state (Figure21-25). If the user writes the SSPxBUF when a Stop sequence 21.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the If the user writes the SSPxBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the occur). contents of the buffer are unchanged (the write doesn’t occur). FIGURE 21-25: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge Sequence Starts Here, ACKEN Automatically Cleared Write to SSPxCON2, ACKEN = 1, ACKDT = 0 TBRG TBRG SDAx D0 ACK SCLx 8 9 SSPxIF Cleared in SSPxIF Set at Cleared in Software the End of Receive Software SSPxIF Set at the End of Acknowledge Sequence Note: TBRG = one Baud Rate Generator period. FIGURE 21-26: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPxCON2, SCLx = 1 for TBRG, Followed by SDAx = 1 for TBRG Set PEN after SDAx Sampled High. P bit (SSPxSTAT<4>) is Set Falling Edge of PEN bit (SSPxCON2<2>) is Cleared by 9th Clock Hardware and the SSPxIF bit is Set TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx Brought High After TBRG SDAx Asserted Low Before Rising Edge of Clock to Set up Stop Condition Note: TBRG = one Baud Rate Generator period.  2009-2018 Microchip Technology Inc. DS30009960F-page 311

PIC18F87K22 FAMILY 21.4.14 SLEEP OPERATION 21.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data, and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master 21.4.15 EFFECTS OF A RESET outputs a ‘1’ on SDAx, by letting SDAx float high, and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCLx pin floats current transfer. high, data should be stable. If the expected data on SDAx is a ‘1’ and the data sampled on the SDAx 21.4.16 MULTI-MASTER MODE pin=0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF, In Multi-Master mode, the interrupt generation on the and reset the I2C port to its Idle state (Figure21-27). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDAx and SCLx lines are deasserted and be taken when the P bit (SSPxSTAT<4>) is set, or the the SSPxBUF can be written to. When the user services bus is Idle, with both the S and P bits clear. When the the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the MSSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDAx line must be If a Start, Repeated Start, Stop or Acknowledge condition monitored for arbitration to see if the signal level is the was in progress when the bus collision occurred, the con- expected output level. This check is performed in dition is aborted, the SDAx and SCLx lines are hardware with the result placed in the BCLxIF bit. deasserted and the respective control bits in the SSPx- CON2 register are cleared. When the user services the The states where arbitration can be lost are: bus collision Interrupt Service Routine (ISR), and if the • Address Transfer I2C bus is free, the user can resume communication by • Data Transfer asserting a Start condition. • A Start Condition The master will continue to monitor the SDAx and SCLx • A Repeated Start Condition pins. If a Stop condition occurs, the SSPxIF bit will be set. • An Acknowledge Condition A write to the SSPxBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determi- nation of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 21-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDAx. While SCLx is High, Data Changes SDAx Line Pulled Low Data Doesn’t Match what is Driven while SCLx = 0 by Another Source by the Master; Bus Collision has Occurred SDAx Released by Master SDAx SCLx Set Bus Collision Interrupt (BCLxIF) BCLxIF DS30009960F-page 312  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.4.17.1 Bus Collision During a Start If the SDAx pin is sampled low during this count, the Condition BRG is reset and the SDAx line is asserted early (Figure21-30). If, however, a ‘1’ is sampled on the During a Start condition, a bus collision occurs if: SDAx pin, the SDAx pin is asserted low at the end of a) SDAx or SCLx is sampled low at the beginning the BRG count. The Baud Rate Generator is then of the Start condition (Figure21-28). reloaded and counts down to 0. If the SCLx pin is b) SCLx is sampled low before SDAx is asserted sampled as ‘0’ during this time, a bus collision does not low (Figure21-29). occur. At the end of the BRG count, the SCLx pin is asserted low. During a Start condition, both the SDAx and the SCLx pins are monitored. Note: The reason that a bus collision is not a factor during a Start condition is that no two If the SDAx pin is already low, or the SCLx pin is bus masters can assert a Start condition at already low, then all of the following occur: the exact same time. Therefore, one • The Start condition is aborted master will always assert SDAx before the • The BCLxIF flag is set other. This condition does not cause a bus • The MSSP module is reset to its inactive state collision because the two masters must be (Figure21-28) allowed to arbitrate the first address The Start condition begins with the SDAx and SCLx following the Start condition. If the address pins deasserted. When the SDAx pin is sampled high, is the same, arbitration must be allowed to the Baud Rate Generator is loaded from continue into the data portion, Repeated SSPxADD<6:0> and counts down to 0. If the SCLx pin Start or Stop conditions. is sampled low while SDAx is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 21-28: BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx Goes Low Before the SEN bit is Set. Set BCLxIF, S bit and SSPxIF Set Because SDAx = 0, SCLx = 1 SDAx SCLx Set SEN, Enable Start SEN Cleared Automatically Because of Bus Collision, Condition if SDAx = 1, SCLx = 1 MSSP module Reset into Idle State SEN SDAx Sampled Low Before Start Condition, Set BCLxIF, S bit and SSPxIF Set Because BCLxIF SDAx = 0, SCLx = 1 SSPxIF and BCLxIF are Cleared in Software S SSPxIF SSPxIF and BCLxIF are Cleared in Software  2009-2018 Microchip Technology Inc. DS30009960F-page 313

PIC18F87K22 FAMILY FIGURE 21-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, Enable Start SCLx Sequence if SDAx = 1, SCLx = 1 SCLx = 0 Before SDAx = 0, Bus Collision Occurs, Set BCLxIF SEN SCLx = 0 Before BRG Time-out, Bus Collision Occurs, Set BCLxIF BCLxIF Interrupt Cleared in Software S ‘0’ ‘0’ SSPxIF ‘0’ ‘0’ FIGURE 21-30: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Set SSPxIF Less than TBRG TBRG SDAx SDAx Pulled Low by Other Master, Reset BRG and Assert SDAx SCLx S SCLx Pulled Low After BRG Time-out SEN Set SEN, Enable Start Sequence if SDAx = 1, SCLx = 1 BCLxIF ‘0’ S SSPxIF SDAx = 0, SCLx = 1, Interrupts Cleared Set SSPxIF in Software DS30009960F-page 314  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 21.4.17.2 Bus Collision During a Repeated If SDAx is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure21-31). If SDAx is sampled high, the BRG is During a Repeated Start condition, a bus collision reloaded and begins counting. If SDAx goes from occurs if: high-to-low before the BRG times out, no bus collision a) A low level is sampled on SDAx when SCLx occurs because no two masters can assert SDAx at goes from a low level to a high level. exactly the same time. b) SCLx goes low before SDAx is asserted low, If SCLx goes from high-to-low before the BRG times indicating that another master is attempting to out and SDAx has not already been asserted, a bus transmit a data ‘1’. collision occurs. In this case, another master is When the user deasserts SDAx and the pin is allowed attempting to transmit a data ‘1’ during the Repeated to float high, the BRG is loaded with SSPxADD<6:0> Start condition (see Figure21-32). and counts down to 0. The SCLx pin is then deasserted If, at the end of the BRG time-out, both SCLx and SDAx and when sampled high, the SDAx pin is sampled. are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. FIGURE 21-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes High, If SDAx = 0, Set BCLxIF and Release SDAx and SCLx RSEN BCLxIF Cleared in Software S ‘0’ SSPxIF ‘0’ FIGURE 21-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx SCLx goes Low Before SDAx, BCLxIF Set BCLxIF, Release SDAx and SCLx Interrupt Cleared in Software RSEN S ‘0’ SSPxIF  2009-2018 Microchip Technology Inc. DS30009960F-page 315

PIC18F87K22 FAMILY 21.4.17.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low. Condition When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with a) After the SDAx pin has been deasserted and SSPxADD<6:0> and counts down to 0. After the BRG allowed to float high, SDAx is sampled low after times out, SDAx is sampled. If SDAx is sampled low, a the BRG has timed out. bus collision has occurred. This is due to another b) After the SCLx pin is deasserted, SCLx is master attempting to drive a data ‘0’ (Figure21-33). If sampled low before SDAx goes high. the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure21-34). FIGURE 21-33: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDAx Sampled Low After TBRG, Set BCLxIF SDAx SDAx Asserted Low SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ FIGURE 21-34: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes Low Before SDAx goes High, Assert SDAx Set BCLxIF SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ DS30009960F-page 316  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 21-4: REGISTERS ASSOCIATED WITH I2C OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP PIR2 OSCFIF — SSP2IF BLC2IF BCL1IF HLVDIF TMR3IF TMR3GIF PIE2 OSCFIE — SSP2IE BLC2IE BCL1IE HLVDIE TMR3IE TMR3GIE IPR2 OSCFIP — SSP2IP BLC2IP BCL1IP HLVDIP TMR3IP TMR3GIP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 SSP1BUF MSSP1 Receive Buffer/Transmit Register SSP1ADD MSSP1 Address Register (I2C Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) SSP1MSK(1) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN SSP1STAT SMP CKE D/A P S R/W UA BF SSP2BUF MSSP2 Receive Buffer/Transmit Register SSP2ADD MSSP2 Address Register (I2C Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) SSP2MSK(1) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN SSP2STAT SMP CKE D/A P S R/W UA BF PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode. Note 1: SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I2C Slave operating modes in 7-Bit Masking mode. See Section21.4.3.4 “7-Bit Address Masking Mode” for more details. 2: Alternate bit definitions for use in I2C Slave mode operations only.  2009-2018 Microchip Technology Inc. DS30009960F-page 317

PIC18F87K22 FAMILY 22.0 ENHANCED UNIVERSAL The pins of EUSART1 and EUSART2 are multiplexed SYNCHRONOUS with the functions of PORTC (RC6/TX1/CK1 and RC7/RX1/DT1) and PORTG (RG1/TX2/CK2/AN19/C3OUT ASYNCHRONOUS RECEIVER and RG2/RX2/DT2/AN18/C3INA), respectively. In TRANSMITTER (EUSART) order to configure these pins as an EUSART: The Enhanced Universal Synchronous Asynchronous • For EUSART1: Receiver Transmitter (EUSART) module is one of two - Bit, SPEN (RCSTA1<7>), must be set (= 1) serial I/O modules. (Generically, the EUSART is also - Bit, TRISC<7>, must be set (= 1) known as a Serial Communications Interface or SCI.) - Bit, TRISC<6>, must be cleared (= 0) for The EUSART can be configured as a full-duplex, Asynchronous and Synchronous Master asynchronous system that can communicate with modes peripheral devices, such as CRT terminals and - Bit, TRISC<6>, must be set (= 1) for personal computers. It can also be configured as a Synchronous Slave mode half-duplex synchronous system that can communicate • For EUSART2: with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. - Bit, SPEN (RCSTA2<7>), must be set (= 1) - Bit, TRISG<2>, must be set (= 1) The Enhanced USART module implements additional features, including automatic baud rate detection and - Bit TRISG<1> must be cleared (= 0) for calibration, automatic wake-up on Sync Break recep- Asynchronous and Synchronous Master tion and 12-bit Break character transmit. These make it modes ideally suited for use in Local Interconnect Network bus - Bit, TRISC<6>, must be set (= 1) for (LIN/J2602 bus) systems. Synchronous Slave mode All members of the PIC18F87K22 family are equipped Note: The EUSART control will automatically with two independent EUSART modules, referred to as reconfigure the pin from input to output as EUSART1 and EUSART2. They can be configured in needed. the following modes: The operation of each Enhanced USART module is • Asynchronous (full duplex) with: controlled through three registers: - Auto-wake-up on character reception • Transmit Status and Control (TXSTAx) - Auto-baud calibration • Receive Status and Control (RCSTAx) - 12-bit Break character transmission • Baud Rate Control (BAUDCONx) • Synchronous – Master (half duplex) with These are detailed on the following pages in selectable clock polarity Register22-1, Register22-2 and Register22-3, • Synchronous – Slave (half duplex) with selectable respectively. clock polarity Note: Throughout this section, references to register and bit names that may be asso- ciated with a specific EUSART module are referred to generically by the use of ‘x’ in place of the specific module number. Thus, “RCSTAx” might refer to the Receive Status register for either EUSART1 or EUSART2. DS30009960F-page 318  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 22-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit is enabled 0 = Transmit is disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission has completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR is empty 0 = TSR is full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2009-2018 Microchip Technology Inc. DS30009960F-page 319

PIC18F87K22 FAMILY REGISTER 22-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled 0 = Serial port is disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-Bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and the ninth bit can be used as a parity bit Asynchronous mode 8-Bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be cleared by reading the RCREGx register and receiving the next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be an address/data bit or a parity bit and must be calculated by user firmware. DS30009960F-page 320  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 22-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 RXDTP: Data/Receive Polarity Select bit Asynchronous mode: 1 = Receive data (RXx) is inverted (active-low) 0 = Receive data (RXx) is not inverted (active-high) Synchronous mode: 1 = Data (DTx) is inverted (active-low) 0 = Data (DTx) is not inverted (active-high) bit 4 TXCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TXx) is a low level 0 = Idle state for transmit (TXx) is a high level Synchronous mode: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator – SPBRGx only (Compatible mode), SPBRGHx value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RXx pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement is disabled or has completed Synchronous mode: Unused in this mode.  2009-2018 Microchip Technology Inc. DS30009960F-page 321

PIC18F87K22 FAMILY 22.1 Baud Rate Generator (BRG) Writing a new value to the SPBRGHx:SPBRGx registers causes the BRG timer to be reset (or cleared). The BRG is a dedicated, 8-bit or 16-bit generator that This ensures the BRG does not wait for a timer over- supports both the Asynchronous and Synchronous flow before outputting the new baud rate. When modes of the EUSART. By default, the BRG operates operated in the Synchronous mode, SPBRGH:SPBRG in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) values of 0000h and 0001h are not supported. In the selects 16-bit mode. Asynchronous mode, all BRG values may be used. The SPBRGHx:SPBRGx register pair controls the period 22.1.1 OPERATION IN POWER-MANAGED of a free-running timer. In Asynchronous mode, bits, BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>), MODES also control the baud rate. In Synchronous mode, BRGH The device clock is used to generate the desired baud is ignored. Table22-1 shows the formula for computation rate. When one of the power-managed modes is of the baud rate for different EUSART modes which only entered, the new clock source may be operating at a apply in Master mode (internally generated clock). different frequency. This may require an adjustment to Given the desired baud rate and FOSC, the nearest the value in the SPBRGx register pair. integer value for the SPBRGHx:SPBRGx registers can 22.1.2 SAMPLING be calculated using the formulas in Table22-1. From this, the error in baud rate can be determined. An example The data on the RXx pin (either RC7/RX1/DT1 or calculation is shown in Example22-1. Typical baud rates RG2/RX2/DT2/AN18/C3INA) is sampled three times and error values for the various Asynchronous modes by a majority detect circuit to determine if a high or a are shown in Table22-2. It may be advantageous to use low level is present at the RXx pin. the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. TABLE 22-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair DS30009960F-page 322  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY EXAMPLE 22-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 22-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.  2009-2018 Microchip Technology Inc. DS30009960F-page 323

PIC18F87K22 FAMILY TABLE 22-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — DS30009960F-page 324  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 22-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — —  2009-2018 Microchip Technology Inc. DS30009960F-page 325

PIC18F87K22 FAMILY 22.1.3 AUTO-BAUD RATE DETECT Note1: If the WUE bit is set with the ABDEN bit, The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on detection and calibration of baud rate. This feature is the byte following the Break character. active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the bit is clear. incoming character baud rate is within the The automatic baud rate measurement sequence range of the selected BRG clock source. (Figure22-1) begins whenever a Start bit is received Some combinations of oscillator fre- and the ABDEN bit is set. The calculation is quency and EUSART baud rates are not self-averaging. possible due to bit error rates. Overall system timing and communication baud In the Auto-Baud Rate Detect (ABD) mode, the clock to rates must be taken into consideration the BRG is reversed. Rather than the BRG clocking the when using the Auto-Baud Rate Detection incoming RXx signal, the RXx signal is timing the BRG. feature. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming 3: To maximize baud rate range, if that serial byte stream. feature is used, it is recommended that the BRG16 bit (BAUDCONx<3>) be set. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value, 55h (ASCII TABLE 22-4: BRG COUNTER “U”, which is also the LIN/J2602 bus Sync character), in CLOCK RATES order to calculate the proper bit rate. The measurement BRG16 BRGH BRG Counter Clock is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incom- 0 0 FOSC/512 ing signal. After a Start bit, the SPBRGx begins counting 0 1 FOSC/128 up, using the preselected clock source on the first rising edge of RXx. After eight bits on the RXx pin or the fifth 1 0 FOSC/128 rising edge, an accumulated value totalling the proper 1 1 FOSC/32 BRG period is left in the SPBRGHx:SPBRGx register pair. Once the 5th edge is seen (this should correspond 22.1.3.1 ABD and EUSART Transmission to the Stop bit), the ABDEN bit is automatically cleared. Since the BRG clock is reversed during ABD acquisi- If a rollover of the BRG occurs (an overflow from FFFFh tion, the EUSART transmitter cannot be used during to 0000h), the event is trapped by the ABDOVF status ABD. This means that whenever the ABDEN bit is set, bit (BAUDCONx<7>). It is set in hardware by BRG roll- TXREGx cannot be written to. Users should also overs and can be set or cleared by the user in software. ensure that ABDEN does not become set during a ABD mode remains active after rollover events and the transmit sequence. Failing to do this may result in ABDEN bit remains set (Figure22-2). unpredictable EUSART operation. While calibrating the baud rate period, the BRG regis- ters are clocked at 1/8th the preconfigured clock rate. The BRG clock will be configured by the BRG16 and BRGH bits. The BRG16 bit must be set to use both SPBRG1 and SPBRGH1 as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table22-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCxIF interrupt is set once the fifth rising edge on RXx is detected. The value in the RCREGx needs to be read to clear the RCxIF interrupt. The contents of RCREGx should be discarded. DS30009960F-page 326  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 22-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RXx Pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE=0. FIGURE 22-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RXx Pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h  2009-2018 Microchip Technology Inc. DS30009960F-page 327

PIC18F87K22 FAMILY 22.2 EUSART Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register The Asynchronous mode of operation is selected by is empty and the TXxIF flag bit is set. This interrupt can clearing the SYNC bit (TXSTAx<4>). In this mode, the be enabled or disabled by setting or clearing the inter- EUSART uses standard Non-Return-to-Zero (NRZ) rupt enable bit, TXxIE. TXxIF will be set regardless of format (one Start bit, eight or nine data bits and one Stop the state of TXxIE; it cannot be cleared in software. bit). The most common data format is 8 bits. An on-chip, TXxIF is also not cleared immediately upon loading dedicated 8-bit/16-bit Baud Rate Generator can be used TXREGx, but becomes valid in the second instruction to derive standard baud rate frequencies from the cycle following the load instruction. Polling TXxIF oscillator. immediately following a load of TXREGx will return The EUSART transmits and receives the LSb first. The invalid results. EUSART’s transmitter and receiver are functionally While TXxIF indicates the status of the TXREGx regis- independent but use the same data format and baud ter; another bit, TRMT (TXSTAx<1>), shows the status rate. The Baud Rate Generator produces a clock, either of the TSR register. TRMT is a read-only bit which is set x16 or x64 of the bit shift rate, depending on the BRGH when the TSR register is empty. No interrupt logic is and BRG16 bits (TXSTAx<2> and BAUDCONx<3>). tied to this bit so the user has to poll this bit in order to Parity is not supported by the hardware but can be determine if the TSR register is empty. implemented in software and stored as the 9th data bit. Note1: The TSR register is not mapped in data When operating in Asynchronous mode, the EUSART memory, so it is not available to the user. module consists of the following important elements: 2: Flag bit, TXxIF, is set when enable bit, • Baud Rate Generator TXEN, is set. • Sampling Circuit To set up an Asynchronous Transmission: • Asynchronous Transmitter • Asynchronous Receiver 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the • Auto-Wake-up on Sync Break Character BRGH and BRG16 bits, as required, to achieve • 12-Bit Break Character Transmit the desired baud rate. • Auto-Baud Rate Detection 2. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. 22.2.1 EUSART ASYNCHRONOUS TRANSMITTER 3. If interrupts are desired, set enable bit, TXxIE. 4. If 9-bit transmission is desired, set transmit bit, The EUSART transmitter block diagram is shown in TX9; can be used as an address/data bit. Figure22-3. The heart of the transmitter is the Transmit 5. Enable the transmission by setting bit, TXEN, (Serial) Shift Register (TSR). The Shift register obtains which will also set bit, TXxIF. its data from the Read/Write Transmit Buffer register, TXREGx. The TXREGx register is loaded with data in 6. If 9-bit transmission is selected, the ninth bit software. The TSR register is not loaded until the Stop should be loaded in bit, TX9D. bit has been transmitted from the previous load. As 7. Load data to the TXREGx register (starts soon as the Stop bit is transmitted, the TSR is loaded transmission). with new data from the TXREGx register (if available). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. DS30009960F-page 328  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 22-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb LSb (8)  0 Pin Buffer and Control TSR Register TXx Pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGHx SPBRGx TX9 Baud Rate Generator TX9D FIGURE 22-4: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 22-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXxIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions.  2009-2018 Microchip Technology Inc. DS30009960F-page 329

PIC18F87K22 FAMILY TABLE 22-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG2 EUSART2 Transmit Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register ODCON3 U2OD U1OD — — — — — CTMUDS PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. DS30009960F-page 330  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 22.2.2 EUSART ASYNCHRONOUS 22.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure22-6. This mode would typically be used in RS-485 systems. The data is received on the RXx pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGHx:SPBRGx registers for whereas the main receive serial shifter operates at the the appropriate baud rate. Set or clear the bit rate or at FOSC. This mode would typically be used BRGH and BRG16 bits, as required, to achieve in RS-232 systems. the desired baud rate. To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing 1. Initialize the SPBRGHx:SPBRGx registers for the SYNC bit and setting the SPEN bit. the appropriate baud rate. Set or clear the 3. If interrupts are required, set the RCEN bit and BRGH and BRG16 bits, as required, to achieve select the desired priority level with the RCxIP bit. the desired baud rate. 4. Set the RX9 bit to enable 9-bit reception. 2. Enable the asynchronous serial port by clearing 5. Set the ADDEN bit to enable address detect. bit, SYNC, and setting bit, SPEN. 6. Enable reception by setting the CREN bit. 3. If interrupts are desired, set enable bit, RCxIE. 7. The RCxIF bit will be set when reception is 4. If 9-bit reception is desired, set bit, RX9. complete. The interrupt will be Acknowledged if 5. Enable the reception by setting bit, CREN. the RCxIE and GIE bits are set. 6. Flag bit, RCxIF, will be set when reception is 8. Read the RCSTAx register to determine if any complete and an interrupt will be generated if error occurred during reception, as well as read enable bit, RCxIE, was set. bit 9 of data (if applicable). 7. Read the RCSTAx register to get the 9th bit (if 9. Read RCREGx to determine if the device is enabled) and determine if any error occurred being addressed. during reception. 10. If any error occurred, clear the CREN bit. 8. Read the 8-bit received data by reading the 11. If the device has been addressed, clear the RCREGx register. ADDEN bit to allow all received data into the 9. If any error occurred, clear the error by clearing receive buffer and interrupt the CPU. enable bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 22-6: EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGHx SPBRGx  o6r4 MSb RSR Register LSb  16 or Stop (8) 7  1 0 Start Baud Rate Generator  4 RX9 Pin Buffer Data and Control Recovery RXx RX9D RCREGx Register FIFO SPEN 8 Interrupt RCxIF Data Bus RCxIE  2009-2018 Microchip Technology Inc. DS30009960F-page 331

PIC18F87K22 FAMILY FIGURE 22-7: ASYNCHRONOUS RECEPTION RXx (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREGx RCREGx Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word, causing the OERR (Overrun) bit to be set. TABLE 22-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG1 EUSART1 Receive Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG2 EUSART2 Receive Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register ODCON3 U2OD U1OD — — — — — CTMUDS PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. DS30009960F-page 332  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 22.2.4 AUTO-WAKE-UP ON SYNC BREAK 22.2.4.1 Special Considerations Using CHARACTER Auto-Wake-up During Sleep mode, all clocks to the EUSART are Since auto-wake-up functions by sensing rising edge suspended. Because of this, the Baud Rate Generator transitions on RXx/DTx, information with any state is inactive and a proper byte reception cannot be per- changes before the Stop bit may signal a false formed. The auto-wake-up feature allows the controller End-of-Character (EOC) and cause data or framing to wake up due to activity on the RXx/DTx line while the errors. To work properly, therefore, the initial character EUSART is operating in Asynchronous mode. in the transmission must be all ‘0’s. This can be 00h (8bits) for standard RS-232 devices or 000h (12 bits) The auto-wake-up feature is enabled by setting the for the LIN/J2602 bus. WUE bit (BAUDCONx<1>). Once set, the typical receive sequence on RXx/DTx is disabled and the Oscillator start-up time must also be considered, EUSART remains in an Idle state, monitoring for a especially in applications using oscillators with longer wake-up event independent of the CPU mode. A start-up intervals (i.e., HS or HSPLL mode). The Sync wake-up event consists of a high-to-low transition on Break (or Wake-up Signal) character must be of the RXx/DTx line. (This coincides with the start of a sufficient length and be followed by a sufficient interval Sync Break or a Wake-up Signal character for the to allow enough time for the selected oscillator to start LIN/J2602 protocol.) and provide proper initialization of the EUSART. Following a wake-up event, the module generates an RCxIF interrupt. The interrupt is generated synchro- nously to the Q clocks in normal operating modes (Figure22-8) and asynchronously if the device is in Sleep mode (Figure22-9). The interrupt condition is cleared by reading the RCREGx register. The WUE bit is automatically cleared once a low-to-high transition is observed on the RXx line following the wake-up event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over.  2009-2018 Microchip Technology Inc. DS30009960F-page 333

PIC18F87K22 FAMILY 22.2.4.2 Special Considerations Using The fact that the WUE bit has been cleared (or is still the WUE Bit set), and the RCxIF flag is set, should not be used as an indicator of the integrity of the data in RCREGx. The timing of WUE and RCxIF events may cause some Users should consider implementing a parallel method confusion when it comes to determining the validity of in firmware to verify received data integrity. received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a To assure that no actual data is lost, check the RCIDL receive interrupt by setting the RCxIF bit. The WUE bit bit to verify that a receive operation is not in process. If is cleared after this when a rising edge is seen on a receive operation is not occurring, the WUE bit may RXx/DTx. The interrupt condition is then cleared by then be set just prior to entering Sleep mode. reading the RCREGx register. Ordinarily, the data in RCREGx will be dummy data and should be discarded. FIGURE 22-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto-Cleared WUE bit(1) RXx/DTx Line RCxIF Cleared due to User Read of RCREGx Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 22-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto-Cleared WUE bit(2) RXx/DTx Line Note 1 RCxIF Cleared due to User Read of RCREGx SLEEP Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. DS30009960F-page 334  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 22.2.5 BREAK CHARACTER SEQUENCE 1. Configure the EUSART for the desired mode. The EUSART module has the capability of sending the 2. Set the TXEN and SENDB bits to set up the special Break character sequences that are required by Break character. the LIN/J2602 bus standard. The Break character 3. Load the TXREGx with a dummy character to transmit consists of a Start bit, followed by twelve ‘0’ initiate transmission (the value is ignored). bits and a Stop bit. The Frame Break character is sent 4. Write ‘55h’ to TXREGx to load the Sync whenever the SENDB and TXEN bits (TXSTAx<3> and character into the transmit FIFO buffer. TXSTAx<5>, respectively) are set while the Transmit 5. After the Break has been sent, the SENDB bit is Shift Register is loaded with data. Note that the value reset by hardware. The Sync character now of data written to TXREGx will be ignored and all ‘0’s transmits in the preconfigured mode. will be transmitted. When the TXREGx becomes empty, as indicated by The SENDB bit is automatically reset by hardware after the TXxIF, the next data byte can be written to the corresponding Stop bit is sent. This allows the user TXREGx. to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync 22.2.6 RECEIVING A BREAK CHARACTER character in the LIN/J2602 specification). The Enhanced USART module can receive a Break Note that the data value written to the TXREGx for the character in two ways. Break character is ignored. The write simply serves the The first method forces configuration of the baud rate purpose of initiating the proper sequence. at a frequency of 9/13 the typical speed. This allows for The TRMT bit indicates when the transmit operation is the Stop bit transition to be at the correct sampling active or Idle, just as it does during normal transmis- location (13 bits for Break versus Start bit and 8 data sion. See Figure22-10 for the timing of the Break bits for typical data). character sequence. The second method uses the auto-wake-up feature 22.2.5.1 Break and Sync Transmit Sequence described in Section22.2.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the The following sequence will send a message frame EUSART will sample the next two transitions on header made up of a Break, followed by an Auto-Baud RXx/DTx, cause an RCxIF interrupt and receive the Sync byte. This sequence is typical of a LIN/J2602 bus next data byte followed by another interrupt. master. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABDEN bit once the TXxIF interrupt is observed. FIGURE 22-10: SEND BREAK CHARACTER SEQUENCE Write to TXREGx Dummy Write BRG Output (Shift Clock) TXx (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here Auto-Cleared SENDB bit (Transmit Shift Reg. Empty Flag)  2009-2018 Microchip Technology Inc. DS30009960F-page 335

PIC18F87K22 FAMILY 22.3 EUSART Synchronous Once the TXREGx register transfers the data to the Master Mode TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be The Synchronous Master mode is entered by setting enabled or disabled by setting or clearing the interrupt the CSRC bit (TXSTAx<7>). In this mode, the data is enable bit, TXxIE. TXxIF is set regardless of the state transmitted in a half-duplex manner (i.e., transmission of enable bit, TXxIE; it cannot be cleared in software. It and reception do not occur at the same time). When will reset only when new data is loaded into the transmitting data, the reception is inhibited and vice TXREGx register. versa. Synchronous mode is entered by setting bit, While flag bit, TXxIF, indicates the status of the TXREGx SYNC (TXSTAx<4>). In addition, enable bit, SPEN register, another bit, TRMT (TXSTAx<1>), shows the (RCSTAx<7>), is set in order to configure the TXx and status of the TSR register. TRMT is a read-only bit which RXx pins to CKx (clock) and DTx (data) lines, is set when the TSR is empty. No interrupt logic is tied to respectively. this bit, so the user must poll this bit in order to determine The Master mode indicates that the processor trans- if the TSR register is empty. The TSR is not mapped in mits the master clock on the CKx line. Clock polarity is data memory so it is not available to the user. selected with the TXCKP bit (BAUDCONx<4>). Setting To set up a Synchronous Master Transmission: TXCKP sets the Idle state on CKx as high, while clear- ing the bit sets the Idle state as low. This option is 1. Initialize the SPBRGHx:SPBRGx registers for the provided to support Microwire devices with this module. appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. 22.3.1 EUSART SYNCHRONOUS MASTER 2. Enable the synchronous master serial port by TRANSMISSION setting bits, SYNC, SPEN and CSRC. The EUSART transmitter block diagram is shown in 3. If interrupts are desired, set enable bit, TXxIE. Figure22-3. The heart of the transmitter is the Transmit 4. If 9-bit transmission is desired, set bit, TX9. (Serial) Shift Register (TSR). The Shift register obtains 5. Enable the transmission by setting bit, TXEN. its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit TXREGx. The TXREGx register is loaded with data in should be loaded in bit, TX9D. software. The TSR register is not loaded until the last 7. Start transmission by loading data to the bit has been transmitted from the previous load. As TXREGx register. soon as the last bit is transmitted, the TSR is loaded with new data from the TXREGx (if available). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 22-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1/ Pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX1/CK1/ Pin (TXCKP = 0) RC6/TX1/CK1/ Pin (TXCKP = 1) Write to TxREG1 Reg Write Word 1 Write Word 2 Tx1IF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. This example is equally applicable to EUSART2 (RG1/TX2/CK2/AN19/C3OUT and RG2/RX2/DT2/AN18/C3INA). DS30009960F-page 336  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 22-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 Pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 Pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2/AN19/C3OUT and RG2/RX2/DT2/AN18/C3INA). TABLE 22-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG2 EUSART2 Transmit Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register ODCON3 U2OD U1OD — — — — — CTMUDS PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.  2009-2018 Microchip Technology Inc. DS30009960F-page 337

PIC18F87K22 FAMILY 22.3.2 EUSART SYNCHRONOUS 3. Ensure bits, CREN and SREN, are clear. MASTER RECEPTION 4. If interrupts are desired, set enable bit, RCxIE. 5. If 9-bit reception is desired, set bit, RX9. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, 6. If a single reception is required, set bit, SREN. SREN (RCSTAx<5>), or the Continuous Receive For continuous reception, set bit, CREN. Enable bit, CREN (RCSTAx<4>). Data is sampled on 7. Interrupt flag bit, RCxIF, will be set when recep- the RXx pin on the falling edge of the clock. tion is complete and an interrupt will be generated if the enable bit, RCxIE, was set. If enable bit, SREN, is set, only a single word is 8. Read the RCSTAx register to get the 9th bit (if received. If enable bit, CREN, is set, the reception is enabled) and determine if any error occurred continuous until CREN is cleared. If both bits are set, during reception. then CREN takes precedence. 9. Read the 8-bit received data by reading the To set up a Synchronous Master Reception: RCREGx register. 1. Initialize the SPBRGHx:SPBRGx registers for the 10. If any error occurred, clear the error by clearing appropriate baud rate. Set or clear the BRG16 bit CREN. bit, as required, to achieve the desired baud rate. 11. If using interrupts, ensure that the GIE and PEIE bits 2. Enable the synchronous master serial port by in the INTCON register (INTCON<7:6>) are set. setting bits, SYNC, SPEN and CSRC. FIGURE 22-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 Pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX1/CK1 Pin (TXCKP = 0) RC6/TX1/CK1 Pin (TXCKP = 1) Write to bit, SREN SREN bit CREN b‘0it’ ‘0’ RC1IF bit (Interrupt) Read RCREG1 Note: Timing diagram demonstrates Sync Master mode with bit, SREN = 1, and bit, BRGH = 0. This example is equally applicable to EUSART2 (RG1/TX2/CK2/AN19/C3OUT and RG2/RX2/DT2/AN18/C3INA). DS30009960F-page 338  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 22-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG1 EUSART1 Receive Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG2 EUSART2 Receive Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register ODCON3 U2OD U1OD — — — — — CTMUDS PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.  2009-2018 Microchip Technology Inc. DS30009960F-page 339

PIC18F87K22 FAMILY 22.4 EUSART Synchronous e) If enable bit, TXxIE, is set, the interrupt will wake Slave Mode the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt Synchronous Slave mode is entered by clearing bit, vector. CSRC (TXSTAx<7>). This mode differs from the To set up a Synchronous Slave Transmission: Synchronous Master mode in that the shift clock is sup- plied externally at the CKx pin (instead of being supplied 1. Enable the synchronous slave serial port by internally in Master mode). This allows the device to setting bits, SYNC and SPEN, and clearing bit, transfer or receive data while in any low-power mode. CSRC. 2. Clear bits, CREN and SREN. 22.4.1 EUSART SYNCHRONOUS 3. If interrupts are desired, set enable bit, TXxIE. SLAVE TRANSMISSION 4. If 9-bit transmission is desired, set bit, TX9. The operation of the Synchronous Master and Slave 5. Enable the transmission by setting enable bit, modes is identical, except in the case of Sleep mode. TXEN. If two words are written to the TXREGx and then the 6. If 9-bit transmission is selected, the ninth bit SLEEP instruction is executed, the following will occur: should be loaded in bit, TX9D. a) The first word will immediately transfer to the 7. Start transmission by loading data to the TSR register and transmit. TXREGx register. b) The second word will remain in the TXREGx 8. If using interrupts, ensure that the GIE and PEIE register. bits in the INTCON register (INTCON<7:6>) are set. c) Flag bit, TXxIF, will not be set. d) When the first word has been shifted out of TSR, the TXREGx register will transfer the second word to the TSR and flag bit, TXxIF, will now be set. TABLE 22-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG2 EUSART2 Transmit Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register ODCON3 U2OD U1OD — — — — — CTMUDS PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. DS30009960F-page 340  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 22.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical except in the case of Sleep, or any CSRC. Idle mode, and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCxIE. Slave mode. 3. If 9-bit reception is desired, set bit, RX9. If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN. entering Sleep or any Idle mode, then a word may be 5. Flag bit, RCxIF, will be set when reception is received while in this low-power mode. Once the word complete. An interrupt will be generated if is received, the RSR register will transfer the data to the enable bit, RCxIE, was set. RCREGx register. If the RCxIE enable bit is set, the 6. Read the RCSTAx register to get the 9th bit (if interrupt generated will wake the chip from the enabled) and determine if any error occurred low-power mode. If the global interrupt is enabled, the during reception. program will branch to the interrupt vector. 7. Read the 8-bit received data by reading the RCREGx register. 8. If any error occurred, clear the error by clearing bit, CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 22-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG1 EUSART1 Receive Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG2 EUSART2 Receive Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register ODCON3 U2OD U1OD — — — — — CTMUDS PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.  2009-2018 Microchip Technology Inc. DS30009960F-page 341

PIC18F87K22 FAMILY 23.0 12-BIT ANALOG-TO-DIGITAL 23.1 Differential A/D Converter CONVERTER (A/D) MODULE The converter in PIC18F87K22 family devices is implemented as a differential A/D where the differential The Analog-to-Digital (A/D) Converter module in the voltage between two channels is measured and PIC18F87K22 family of devices has 16inputs for the converted to digital values (see Figure23-1). 64-pin devices and 24inputs for the 80-pin devices. This module allows conversion of an analog input The converter can also be configured to measure a signal to a corresponding 12-bit digital number. voltage from a single input by clearing the CHSN bits (ADCON1<2:0>). With this configuration, the negative The module has these registers: channel input is connected internally to AVSS (see • A/D Control Register 0 (ADCON0) Figure23-2). • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) FIGURE 23-1: DIFFERENTIAL CHANNEL • A/D Port Configuration Register 0 (ANCON0) MEASUREMENT • A/D Port Configuration Register 1 (ANCON1) Positive Input • A/D Port Configuration Register 2 (ANCON2) CHS<4:0> • ADRESH (the upper, A/D Results register) Negative Input ADC • ADRESL (the lower, A/D Results register) CHSN<2:0> The ADCON0 register, shown in Register23-1, con- trols the operation of the A/D module. The ADCON1 Differential conversion feeds the two input channels to register, shown in Register23-2, configures the voltage a unity gain differential amplifier. The positive channel reference and special trigger selection. The ADCON2 input is selected using the CHS bits (ADCON0<6:2>) register, shown in Register23-3, configures the A/D and the negative channel input is selected using the clock source and programmed acquisition time and CHSN bits (ADCON1<2:0>). justification. The output from the amplifier is fed to the A/D Con- verter, as shown in Figure23-1. The 12-bit result is available on the ADRESH and ADRESL registers. An additional bit indicates if the 12-bit result is a positive or negative value. FIGURE 23-2: SINGLE CHANNEL MEASUREMENT Positive Input CHS<4:0> CHSN<2:0> = 000 ADC In the Single Channel Measurement mode, the nega- tive input is connected to AVSS by clearing the CHSN bits (ADCON1<2:0>). DS30009960F-page 342  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 23.2 A/D Registers 23.2.1 A/D CONTROL REGISTERS REGISTER 23-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 = Channel 00 (AN0) 10000= Channel 16 (AN16) 00001 = Channel 01 (AN1) 10001= Channel 17 (AN17) 00010 = Channel 02 (AN2) 10010= Channel 18 (AN18) 00011 = Channel 03 (AN3) 10011= Channel 19 (AN19) 00100 = Channel 04 (AN4) 10100= Channel 20 (AN20)(1,2) 00101 = Channel 05 (AN5) 10101= Channel 21 (AN21)(1,2) 00110 = Channel 06 (AN6) 10110= Channel 22 (AN22)(1,2) 00111 = Channel 07 (AN7) 10111= Channel 23 (AN23)(1,2) 01000 = Channel 08 (AN8) 11000= (Reserved)(2) 01001 = Channel 09 (AN9) 11001= (Reserved)(2) 01010 = Channel 10 (AN10 11010= (Reserved)(2) 01011 = Channel 11 (AN11) 11011= (Reserved)(2) 01100 = Channel 12 (AN12)(1,2) 11100= Channel 28 (Reserved CTMU) 01101 = Channel 13 (AN13)(1,2) 11101= Channel 29 (Internal temperature diode) 01110 = Channel 14 (AN14)(1,2) 11110= Channel 30 (VDDCORE) 01111 = Channel 15 (AN15)(1,2) 11111= Channel 31 (v1.024V band gap) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D (or calibration) cycle in progress. Setting this bit starts an A/D conversion cycle. The bit is cleared automatically by hardware when the A/D conversion is completed. 0 = A/D conversion has completed or is not in progress bit 0 ADON: A/D On bit 1 = A/D Converter is operating 0 = A/D conversion module is shut off and consuming no operating current Note 1: These channels are not implemented on 64-pin devices. 2: Performing a conversion on unimplemented channels will return random values.  2009-2018 Microchip Technology Inc. DS30009960F-page 343

PIC18F87K22 FAMILY REGISTER 23-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TRIGSEL<1:0>: Special Trigger Select bits 11 = Selects the special trigger from the RTCC 10 = Selects the special trigger from the Timer1 01 = Selects the special trigger from the CTMU 00 = Selects the special trigger from the ECCP2 bit 5-4 VCFG<1:0>: A/D VREF+ Configuration bits 11 = Internal VREF+ (4.096V) 10 = Internal VREF+ (2.048V) 01 = External VREF+ 00 = AVDD bit 3 VNCFG: A/D VREF- Configuration bit 1 = External VREF 0 = AVSS bit 2-0 CHSN<2:0>: Analog Negative Channel Select bits 111 = Channel 07 (AN6) 110 = Channel 06 (AN5) 101 = Channel 05 (AN4) 100 = Channel 04 (AN3) 011 = Channel 03 (AN2) 010 = Channel 02 (AN1) 001 = Channel 01 (AN0) 000 = Channel 00 (AVSS) DS30009960F-page 344  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 23-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion.  2009-2018 Microchip Technology Inc. DS30009960F-page 345

PIC18F87K22 FAMILY 23.2.2 A/D RESULT REGISTERS Figure23-3 shows the operation of the A/D result justi- fication and location of the extended sign bits The ADRESH:ADRESL register pair is where the 12-bit (ADSGN). The extended sign bits allow for easier A/D result and extended sign bits (ADSGN) are loaded 16-bit math to be performed on the result. The results at the completion of a conversion. This register pair is are represented as a two's compliment binary value. 16 bits wide. The A/D module gives the flexibility of left This means that when sign bits and magnitude bits are or right justifying the 12-bit result in the 16-Bit Result considered together in right justification, the ADRESH register. The A/D Format Select bit (ADFM) controls and ADRESL registers can be read as a single signed this justification. integer value. When the A/D Converter is disabled, these 8-bit registers can be used as two general purpose registers. FIGURE 23-3: A/D RESULT JUSTIFICATION 12-Bit Result Left Justified Right Justified ADFM = 0 ADFM = 1 ADRESH ADRESL ADRESH ADRESL Result bits ADSGN bit Two’s Complement Example Results Number Line Left Justified Right Justified Hex Decimal Hex Decimal 0xFFF0 4095 0x0FFF 4095 0xFFE0 4094 0x0FFE 4094 … … … … 0x0020 2 0x0002 2 0x0010 1 0x0001 1 0x0000 0 0x0000 0 0xFFFF -1 0xFFFF -1 0xFFEF -2 0xFFFE -2 … … … … 0x001F -4095 0xF001 -4095 0x000F -4096 0xF000 -4096 DS30009960F-page 346  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 23-4: ADRESH: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES11 ADRES10 ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<11:4>: A/D Result High Byte bits REGISTER 23-5: ADRESL: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES3 ADRES2 ADRES1 ADRES0 ADSGN ADSGN ADSGN ADSGN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 ADRES<3:0>: A/D Result Low Byte bits bit 3-0 ADSGN: A/D Result Sign bit 1 = A/D result is negative 0 = A/D result is positive  2009-2018 Microchip Technology Inc. DS30009960F-page 347

PIC18F87K22 FAMILY REGISTER 23-6: ADRESH: A/D RESULT HIGH BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADSGN ADSGN ADSGN ADSGN ADRES11 ADRES10 ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 ADSGN: A/D Result Sign bit 1 = A/D result is negative 0 = A/D result is positive bit 3-0 ADRESH<11:8>: A/D Result High Byte bits REGISTER 23-7: ADRESL: A/D RESULT LOW BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: A/D Result Low Byte bits DS30009960F-page 348  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY The ANCONx registers are used to configure the As a rule, I/O pins that are multiplexed with analog operation of the I/O pin associated with each analog inputs default to analog operation on any device Reset. channel. Clearing an ANSELx bit configures the corresponding pin (ANx) to operate as a digital only I/O. Setting a bit configures the pin to operate as an analog input for either the A/D Converter or the comparator module, with all digital peripherals disabled and digital inputs read as ‘0’. REGISTER 23-8: ANCON0: A/D PORT CONFIGURATION REGISTER 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ANSEL<7:0>: Analog Port Configuration bits (AN7 and AN0) 1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’ 0 = Pin is configured as a digital port REGISTER 23-9: ANCON1: A/D PORT CONFIGURATION REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSEL15(1) ANSEL14(1) ANSEL13(1) ANSEL12(1) ANSEL11 ANSEL10 ANSEL9 ANSEL8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ANSEL<15:8>: Analog Port Configuration bits (AN15 through AN8)(1) 1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’ 0 = Pin is configured as a digital port Note 1: AN15 through AN12 and AN23 to AN20 are implemented only on 80-pin devices. For 64-pin devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect.  2009-2018 Microchip Technology Inc. DS30009960F-page 349

PIC18F87K22 FAMILY REGISTER 23-10: ANCON2: A/D PORT CONFIGURATION REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSEL23(1) ANSEL22(1) ANSEL21(1) ANSEL20(1) ANSEL19 ANSEL18 ANSEL17 ANSEL16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ANSEL<23:16>: Analog Port Configuration bits (AN23 through AN16)(1) 1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’ 0 = Pin is configured as a digital port Note 1: AN15 through AN12 and AN23 through AN20 are implemented only on 80-pin devices. For 64-pin devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect. The analog reference voltage is software-selectable to Each port pin associated with the A/D Converter can be either the device’s positive and negative supply voltage configured as an analog input or a digital I/O. The (AVDD and AVSS) or the voltage level on the ADRESH and ADRESL registers contain the result of RA3/AN3/VREF+ and RA2/AN2/VREF- pins. VREF+ has the A/D conversion. When the A/D conversion is com- two additional Internal Reference Voltage selections: plete, the result is loaded into the ADRESH:ADRESL 2.048V and 4.096V. register pair, the GO/DONE bit (ADCON0<1>) is cleared and the A/D Interrupt Flag bit, ADIF (PIR1<6>), The A/D Converter can uniquely operate while the is set. device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D A device Reset forces all registers to their Reset state. Converter’s internal RC oscillator. This forces the A/D module to be turned off and any conversion in progress is aborted. The value in the The output of the Sample-and-Hold (S/H) is the input ADRESH:ADRESL register pair is not modified for a into the converter, which generates the result via Power-on Reset. These registers will contain unknown successive approximation. data after a Power-on Reset. The block diagram of the A/D module is shown in Figure23-4. DS30009960F-page 350  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 23-4: A/D BLOCK DIAGRAM CHS<4:0> 11111 1.024V Band Gap 11110 VDDCORE 11101 Reserved Temperature Diode 11100 Reserved CTMU 11011 (Unimplemented) 11010 (Unimplemented) 11001 (Unimplemented) 11000 (Unimplemented) 10111 AN23(1) 12-Bit A/D 10110 Converter AN22(1) 00100 AN4 00011 AN3 00010 AN2 00001 AN1 00000 AN0 Positive Input Voltage CHSN<2:0> 111 Negative Input Voltage AN6 110 AN5 Reference Voltage VCFG<1:0> 11 Internal VREF+ 001 (4.096V) AN0 VREF+ 10 Internal VREF+ 000 AVSS (2.048V) 01 AN3 VREF- VDD 00 VNCFG AN2 VSS(2) Note 1: Channels, AN15 through AN12, and AN20 through AN23, are not available on 64-pin devices. 2: I/O pins have diode protection to VDD and VSS.  2009-2018 Microchip Technology Inc. DS30009960F-page 351

PIC18F87K22 FAMILY After the A/D module has been configured as desired, 2. Configure the A/D interrupt (if desired): the selected channel must be acquired before the • Clear the ADIF bit (PIR1<6>) conversion can start. The analog input channels must • Set the ADIE bit (PIE1<6>) have their corresponding TRIS bits selected as inputs. • Set the GIE bit (INTCON<7>) To determine acquisition time, see Section23.3 “A/D 3. Wait the required acquisition time (if required). Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be started. 4. Start the conversion: An acquisition time can be programmed to occur • Set the GO/DONE bit (ADCON0<1>) between setting the GO/DONE bit and the actual start 5. Wait for A/D conversion to complete, by either: of the conversion. • Polling for the GO/DONE bit to be cleared To do an A/D conversion, follow these steps: OR 1. Configure the A/D module: • Waiting for the A/D interrupt • Configure the required ADC pins as analog 6. Read A/D Result registers (ADRESH:ADRESL) pins (ANCON0, ANCON1 and ANCON2) and, if required, clear bit, ADIF. • Set the voltage reference (ADCON1) 7. For the next conversion, begin with Step 1 or 2, • Select the A/D positive and negative input as required. channels (ADCON0 and ADCON1) The A/D conversion time per bit is defined as TAD. • Select the A/D acquisition time (ADCON2) Before the next acquisition starts, a minimum Wait • Select the A/D conversion clock (ADCON2) of 2 TAD is required. • Turn on the A/D module (ADCON0) FIGURE 23-5: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to VDD various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) RSS = Sampling Switch Resistance 1 2 3 4 Sampling Switch (k) DS30009960F-page 352  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 23.3 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation23-1 can be used. This equation assumes For the A/D Converter to meet its specified accuracy, that 1/2 LSb error is used (1,024 steps for the A/D). The the Charge Holding (CHOLD) capacitor must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is shown in Figure23-5. The Equation23-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time, TACQ. This calculation is based on the following application system required to charge the capacitor CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). • CHOLD = 25 pF The source impedance affects the offset voltage at the • Rs = 2.5 k analog input (due to pin leakage current). The maxi- • Conversion Error  1/2 LSb mum recommended impedance for analog sources • VDD = 3VRss = 2 k is 2.5k. After the analog input channel is selected or • Temperature = 85C changed, the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 23-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 23-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 23-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 s TCOFF = (Temp – 25C)(0.02 s/C) (85C – 25C)(0.02 s/C) 1.2 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) s -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s 1.05 s TACQ = 0.2 s + 1.05 s + 1.2 s 2.45 s  2009-2018 Microchip Technology Inc. DS30009960F-page 353

PIC18F87K22 FAMILY 23.4 Selecting and Configuring TABLE 23-1: TAD vs. DEVICE OPERATING Automatic Acquisition Time FREQUENCIES The ADCON2 register allows the user to select an AD Clock Source (TAD) Maximum acquisition time that occurs each time the GO/DONE Device bit is set. Operation ADCS<2:0> Frequency When the GO/DONE bit is set, sampling is stopped and 2 TOSC 000 2.50 MHz a conversion begins. The user is responsible for ensur- 4 TOSC 100 5.00 MHz ing the required acquisition time has passed between 8 TOSC 001 10.00 MHz selecting the desired input channel and setting the GO/DONE bit. 16 TOSC 101 20.00 MHz This occurs when the ACQT<2:0> bits 32 TOSC 010 40.00 MHz (ADCON2<5:3>) remain in their Reset state (‘000’), 64 TOSC 110 64.00 MHz which is compatible with devices that do not offer RC(2) x11 1.00 MHz(1) programmable acquisition times. Note 1: The RC source has a typical TAD time of If desired, the ACQTx bits can be set to select a pro- 4s. grammable acquisition time for the A/D module. When 2: For device frequencies above 1MHz, the the GO/DONE bit is set, the A/D module continues to device must be in Sleep mode for the sample the input for the selected acquisition time, then entire conversion or the A/D accuracy may automatically begins a conversion. Since the acquisi- be out of specification. tion time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. 23.6 Configuring Analog Port Pins In either case, when the conversion is completed, the The ANCON0, ANCON1, ANCON2, TRISA, TRISF, GO/DONE bit is cleared, the ADIF flag is set and the TRISG and TRISH registers control the operation of the A/D begins sampling the currently selected channel A/D port pins. The port pins needed as analog inputs again. If an acquisition time is programmed, there is must have their corresponding TRISx bits set (input). If nothing to indicate if the acquisition time has ended or the TRISx bit is cleared (output), the digital output level if the conversion has begun. (VOH or VOL) will be converted. 23.5 Selecting the A/D Conversion The A/D operation is independent of the state of the CHS<3:0> bits and the TRISx bits. Clock Note1: When reading the PORT register, all pins The A/D conversion time per bit is defined as TAD. The configured as analog input channels will A/D conversion requires 14 TAD per 12-bit conversion. read as cleared (a low level). Pins config- The source of the A/D conversion clock is ured as digital inputs will convert an software-selectable. analog input. Analog levels on a digitally The possible options for TAD are: configured input will be accurately converted. • 2 TOSC • 4 TOSC 2: Analog levels on any pin defined as a digital input may cause the digital input • 8 TOSC buffer to consume current out of the • 16 TOSC device’s specification limits. • 32 TOSC • 64 TOSC • Using the internal RC Oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD. (For more information, see Parameter130 in Table31-29.) Table23-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. DS30009960F-page 354  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 23.7 A/D Conversions ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last Figure23-6 shows the operation of the A/D Converter value written to the ADRESH:ADRESL registers). after the GO/DONE bit has been set and the After the A/D conversion is completed or aborted, a ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep 2TAD Wait is required before the next acquisition can be started. After this Wait, acquisition on the selected mode before the conversion begins. channel is automatically started. Figure23-7 shows the operation of the A/D Converter after the GO/DONE bit has been set, the ACQT<2:0> Note: The GO/DONE bit should NOT be set in bits set to ‘010’ and a 4TAD acquisition time selected. the same instruction that turns on the A/D. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the FIGURE 23-6: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11TAD12TAD13 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 23-7: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input.  2009-2018 Microchip Technology Inc. DS30009960F-page 355

PIC18F87K22 FAMILY 23.8 Use of the Special Event Triggers 23.9 Operation in Power-Managed Modes A/D conversion can be started by the Special Event Trigger of any of these modules: The selection of the automatic acquisition time and A/D • ECCP2 – Requires CCP2M<3:0> bits conversion clock is determined, in part, by the clock (CCP2CON<3:0>) set at ‘1011’ source and frequency while in a power-managed mode. • CTMU – Requires the setting of the CTTRIG bit (CTMUCONH<0>) If the A/D is expected to operate while the device is in • Timer1 a power-managed mode, the ACQT<2:0> and ADCS<2:0> bits in ADCON2 should be updated in • RTCC accordance with the power-managed mode clock that To start an A/D conversion: will be used. • The A/D module must be enabled (ADON = 1) After the power-managed mode is entered (either of the • The appropriate analog input channel is selected power-managed Run modes), an A/D acquisition or • The minimum acquisition period is set one of conversion may be started. Once an acquisition or con- these ways: version is started, the device should continue to be - Timing provided by the user clocked by the same power-managed mode clock source until the conversion has been completed. If desired, the - Selection made of an appropriate TACQ time device may be placed into the corresponding With these conditions met, the trigger sets the power-managed Idle mode during the conversion. GO/DONE bit and the A/D acquisition starts. If the power-managed mode clock frequency is less If the A/D module is not enabled (ADON = 0), the than 1MHz, the A/D RC clock source should be module ignores the Special Event Trigger. selected. Note: With an ECCP2 trigger, Timer1 or Timer 3 Operation in Sleep mode requires that the A/D RC is cleared. The timers reset to automati- clock be selected. If bits, ACQT<2:0>, are set to ‘000’ cally repeat the A/D acquisition period and a conversion is started, the conversion will be with minimal software overhead (moving delayed one instruction cycle to allow execution of the ADRESH:ADRESL to the desired loca- SLEEP instruction and entry into Sleep mode. The tion). If the A/D module is not enabled, the IDLEN and SCS<1:0> bits in the OSCCON register Special Event Trigger is ignored by the must have already been cleared prior to starting the module, but the timer’s counter resets. conversion. DS30009960F-page 356  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 23-2: REGISTERS ASSOCIATED WITH A/D MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON ADCON1 TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 PORTA RA7(2) RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 TRISA TRISA7(2) TRISA6(2) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — PORTG — — RG5(3) RG4 RG3 RG2 RG1 RG0 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 PORTH(1) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 TRISH(1) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: This register is not implemented on 64-pin devices. 2: These bits are available only in certain oscillator modes, when the FOSC2 Configuration bit = 0. If that Configuration bit is cleared, this signal is not implemented. 3: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.  2009-2018 Microchip Technology Inc. DS30009960F-page 357

PIC18F87K22 FAMILY 24.0 COMPARATOR MODULE 24.1 Registers The analog comparator module contains three The CMxCON registers (CM1CON, CM2CON and comparators that can be independently configured in a CM3CON) select the input and output configuration for variety of ways. The inputs can be selected from the each comparator, as well as the settings for interrupt analog inputs and two Internal Reference Voltages. The generation (see Register24-1). digital outputs are available at the pin level and can The CMSTAT register (Register24-2) provides the out- also be read through the control register. Multiple put results of the comparators. The bits in this register output and interrupt event generation are also are read-only. available. A generic single comparator from the module is shown in Figure24-1. Key features of the module includes: • Independent comparator control • Programmable input configuration • Output to both pin and register levels • Programmable output polarity • Independent interrupt generation for each comparator with configurable interrupt-on-change FIGURE 24-1: COMPARATOR SIMPLIFIED BLOCK DIAGRAM CCH<1:0> CMPxOUT (CMSTAT<7:5>) CxINB 0 CxINC(2) 1 Interrupt C2INB/C2IND(1,2) 2 Logic CMPxIF VBG 3 EVPOL<1:0> CREF COE VIN- CxOUT Polarity CxINA 0 VIN+ Cx Logic CVREF 1 CON CPOL Note 1: Comparators, 1 and 3, use C2INB as an input to the inverting terminal. Comparator 2 uses C2IND as an input to the inverted terminal. 2: C1INC, C2INC and C2IND are all unavailable for 64-pin devices (PIC18F6XK22). DS30009960F-page 358  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 24-1: CMxCON: COMPARATOR CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 5 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 4-3 EVPOL<1:0>: Interrupt Polarity Select bits 11 = Interrupt generation on any change of the output(1) 10 = Interrupt generation only on high-to-low transition of the output 01 = Interrupt generation only on low-to-high transition of the output 00 = Interrupt generation is disabled bit 2 CREF: Comparator Reference Select bit (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CxINA pin bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG 10 = Inverting input of comparator connects to C2INB or C2IND pin(2,3) 01 = Inverting input of comparator connects to CxINC pin 00 = Inverting input of comparator connects to CxINB pin Note 1: The CMPxIF bit is automatically set any time this mode is selected and must be cleared by the application after the initial configuration. 2: Comparators, 1 and 3, use C2INB as an input to the inverting terminal. Comparator 2 uses C2IND. 3: C1INC, C2INC and C2IND are all unavailable for 64-pin devices (PIC18F6XK22).  2009-2018 Microchip Technology Inc. DS30009960F-page 359

PIC18F87K22 FAMILY REGISTER 24-2: CMSTAT: COMPARATOR STATUS REGISTER R-x R-x R-x U-0 U-0 U-0 U-0 U-0 CMP3OUT CMP2OUT CMP1OUT — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 CMP<3:1>OUT: Comparator x Status bits If CPOL (CMxCON<5>)= 0 (noninverted polarity): 1 = Comparator x’s VIN+ > VIN- 0 = Comparator x’s VIN+ < VIN- If CPOL = 1 (inverted polarity): 1 = Comparator x’s VIN+ < VIN- 0 = Comparator x’s VIN+ > VIN- bit 4-0 Unimplemented: Read as ‘0’ DS30009960F-page 360  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 24.2 Comparator Operation 24.3 Comparator Response Time A single comparator is shown in Figure24-2, along with Response time is the minimum time, after selecting a the relationship between the analog input levels and new reference voltage or input source, before the com- the digital output. When the analog input at VIN+ is less parator output has a valid level. The response time of than the analog input, VIN-, the output of the compara- the comparator differs from the settling time of the volt- tor is a digital low level. When the analog input at VIN+ age reference. Therefore, both of these times must be is greater than the analog input, VIN-, the output of the considered when determining the total response to a comparator is a digital high level. The shaded areas of comparator input change; otherwise, the maximum the output of the comparator, in Figure24-2, represent delay of the comparators should be used (see the uncertainty due to input offsets and response time. Section31.0 “Electrical Characteristics”). 24.4 Analog Input Connection FIGURE 24-2: SINGLE COMPARATOR Considerations VIN- – A simplified circuit for an analog input is shown in Output Figure24-3. Since the analog pins are connected to a VIN+ + digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may VIN- occur. VIN+ A maximum source impedance of 10k is recommended for the analog sources. Any external component connected to an analog input pin, such as Output a capacitor or a Zener diode, should have very little leakage current. FIGURE 24-3: COMPARATOR ANALOG INPUT MODEL VDD RS VT = 0.6V RIC Comparator <10k AIN Input VA C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage  2009-2018 Microchip Technology Inc. DS30009960F-page 361

PIC18F87K22 FAMILY 24.5 Comparator Control and operating mode, either an external or Internal Configuration Reference Voltage may be used. For external analog pins that are unavailable in 64-pin devices (C1INC, Each comparator has up to eight possible combina- C2INC and C2IND), the corresponding configurations tions of inputs: up to four external analog inputs and that use them as inputs are unavailable. one of two Internal Reference Voltages. The analog signal present at VIN- is compared to the All of the comparators allow a selection of the signal signal at VIN+ and the digital output of the comparator from pin, CxINA, or the voltage from the comparator is adjusted accordingly. reference (CVREF) on the non-inverting channel. This is The external reference is used when CREF=0 compared to either CxINB, CxINC, C2INB/C2IND or (CMxCON<2>) and VIN+ is connected to the CxINA the microcontroller’s fixed Internal Reference Voltage pin. When external reference voltages are used, the (VBG, 1.024V nominal) on the inverting channel. The comparator module can be configured to have the comparator inputs and outputs are tied to fixed I/O pins, reference sources externally. The reference signal defined in Table24-1. The available comparator config- must be between VSS and VDD, and can be applied to urations and their corresponding bit settings are shown either pin of the comparator. in Figure24-4. The comparator module also allows the selection of an TABLE 24-1: COMPARATOR INPUTS AND internally generated reference voltage from the Com- OUTPUTS parator Voltage Reference (CVREF) module. This module is described in more detail in Section25.0 Comparator Input or Output I/O Pin “Comparator Voltage Reference Module”. The reference from the comparator reference voltage C1INA (VIN+) RF6 module is only available when CREF=1. In this mode, C1INB (VIN-) RF5 the Internal Reference Voltage is applied to the 1 C1INC(1) (VIN-) RH6 comparator’s VIN+ pin. C2INB (VIN-) RF3 Note: The comparator input pin, selected by C1OUT RF2 CCH<1:0>, must be configured as an input C2INA (VIN+) RF4 by setting both the corresponding TRISF, TRISG or TRISH bit and the corresponding C2INB (VIN-) RF3 ANSELx bit in the ANCONx register. 2 C2INC(1) (VIN-) RH4 C2IND(1) (VIN-) RH5 24.5.2 COMPARATOR ENABLE AND OUTPUT SELECTION C2OUT RF1 C3INA (VIN+) RG2 The comparator outputs are read through the CMSTAT register. The CMSTAT<5> bit reads the Comparator1 C3INB (VIN-) RG3 output, CMSTAT<6> reads Comparator2 output and 3 C3INC (VIN-) RG4 CMSTAT<7> reads Comparator3 output. These bits C2INB (VIN-) RF3 are read-only. C3OUT RG1 The comparator outputs may also be directly output to Note 1: C1INC, C2INC and C2IND are all the RF2, RF1 and RG1 I/O pins by setting the COE bit unavailable for 64-pin devices (CMxCON<6>). When enabled, multiplexers in the (PIC18F6XK22). output path of the pins switch to the output of the com- parator. While in this mode, the TRISF<2:1> and TRISG<1> bits still function as the digital output enable 24.5.1 COMPARATOR ENABLE AND bits for the RF2, RF1 and RG1 pins. INPUT SELECTION By default, the comparator’s output is at logic high Setting the CON bit of the CMxCON register whenever the voltage on VIN+ is greater than on VIN-. (CMxCON<7>) enables the comparator for operation. The polarity of the comparator outputs can be inverted Clearing the CON bit disables the comparator, resulting using the CPOL bit (CMxCON<5>). in minimum current consumption. The uncertainty of each of the comparators is related to The CCH<1:0> bits in the CMxCON register the input offset voltage and the response time given in (CMxCON<1:0>) direct either one of three analog input the specifications, as discussed in Section24.2 pins, or the Internal Reference Voltage (VBG), to the “Comparator Operation”. comparator, VIN-. Depending on the Comparator DS30009960F-page 362  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 24-4: COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx COE VIN- VIN+ Cx Off (Read as ‘0’) CxOUT Pin Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare(2,3) CON = 1, CREF = 0, CCH<1:0> = 00 CON = 1, CREF = 0, CCH<1:0> = 01 COE COE CxINB VIN- CxINC VIN- CxINA VIN+ Cx CxOUT CxINA VIN+ Cx CxOUT Pin Pin Comparator CxIND > CxINA Compare(3) Comparator VIRV > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 10 CON = 1, CREF = 0, CCH<1:0> = 11 COE COE CC22IINNDB/ VIN- VBG(1) VIN- VIN+ Cx VIN+ Cx CxINA CxOUT CxINA CxOUT Pin Pin Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare(2,3) CON = 1, CREF = 1, CCH<1:0> = 00 CON = 1, CREF = 1, CCH<1:0> = 01 COE COE CxINB VIN- CxINC VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT Pin Pin Comparator CxIND > CVREF Compare(3) Comparator VIRV > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 10 CON = 1, CREF = 1, CCH<1:0> = 11 COE COE CC22IINNBD/ VIN- VBG(1) VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT Pin Pin Note 1: VBG is the Internal Reference Voltage (1.024V nominal). 2: Configuration is unavailable for CM1CON on 64-pin devices (PIC18F6XK22). 3: Configuration is unavailable for CM2CON on 64-pin devices (PIC18F6XK22).  2009-2018 Microchip Technology Inc. DS30009960F-page 363

PIC18F87K22 FAMILY 24.6 Comparator Interrupts When EVPOL<1:0> = 11, the comparator interrupt flag is set whenever there is a change in the output value of The comparator interrupt flag is set whenever any of either comparator. Software will need to maintain the following occurs: information about the status of the output bits, as read • Low-to-high transition of the comparator output from CMSTAT<7:5>, to determine the actual change • High-to-low transition of the comparator output that occurred. • Any change in the comparator output The CMPxIF bits (PIR6<2:0>) are the Comparator Interrupt Flags. The CMPxIF bits must be reset by The comparator interrupt selection is done by the clearing them. Since it is also possible to write a ‘1’ to EVPOL<1:0> bits in the CMxCON register this register, a simulated interrupt may be initiated. (CMxCON<4:3>). Table24-2 shows the interrupt generation with respect In order to provide maximum flexibility, the output of the to comparator input voltages and EVPOL bit settings. comparator may be inverted using the CPOL bit in the Both the CMPxIE bits (PIE6<2:0>) and the PEIE bit CMxCON register (CMxCON<5>). This is functionally (INTCON<6>) must be set to enable the interrupt. In identical to reversing the inverting and non-inverting addition, the GIE bit (INTCON<7>) must also be set. If inputs of the comparator for a particular mode. any of these bits are clear, the interrupt is not enabled, An interrupt is generated on the low-to-high or high-to- though the CMPxIF bits will still be set if an interrupt low transition of the comparator output. This mode of condition occurs. interrupt generation is dependent on EVPOL<1:0> in A simplified diagram of the interrupt section is shown in the CMxCON register. When EVPOL<1:0> = 01 or 10, Figure24-3. the interrupt is generated on a low-to-high or high-to- low transition of the comparator output. Once the Note: The CMPxIF bits will not be set when interrupt is generated, it is required to clear the interrupt EVPOL<1:0> = 00. flag by software. TABLE 24-2: COMPARATOR INTERRUPT GENERATION Comparator Interrupt CPOL EVPOL<1:0> CxOUT Transition Input Change Generated VIN+ > VIN- Low-to-High No 00 VIN+ < VIN- High-to-Low No VIN+ > VIN- Low-to-High Yes 01 VIN+ < VIN- High-to-Low No 0 VIN+ > VIN- Low-to-High No 10 VIN+ < VIN- High-to-Low Yes VIN+ > VIN- Low-to-High Yes 11 VIN+ < VIN- High-to-Low Yes VIN+ > VIN- High-to-Low No 00 VIN+ < VIN- Low-to-High No VIN+ > VIN- High-to-Low No 01 VIN+ < VIN- Low-to-High Yes 1 VIN+ > VIN- High-to-Low Yes 10 VIN+ < VIN- Low-to-High No VIN+ > VIN- High-to-Low Yes 11 VIN+ < VIN- Low-to-High Yes DS30009960F-page 364  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 24.7 Comparator Operation To minimize power consumption while in Sleep mode, During Sleep turn off the comparators (CON=0) before entering Sleep. If the device wakes up from Sleep, the contents When a comparator is active and the device is placed of the CMxCON register are not affected. in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will 24.8 Effects of a Reset wake up the device from Sleep mode, when enabled. Each operational comparator will consume additional A device Reset forces the CMxCON registers to their current. Reset state. This forces both comparators and the voltage reference to the OFF state. TABLE 24-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR6 — — — EEIF — CMP3IF CMP2IF CMP1IF PIE6 — — — EEIE — CMP3IE CMP2IE CMP1IE IPR6 — — — EEIP — CMP3IP CMP2IP CMP1IP CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 CM3CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 CVRCON CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 CMSTAT CMP3OUT CMP2OUT CMP1OUT — — — — — PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 — TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — PORTG — — RG5(1) RG4 RG3 RG2 RG1 RG0 LATG — — — LATG4 LATG3 LATG2 LATG1 LATG0 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 PORTH RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 LATH LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD Legend: — = unimplemented, read as ‘0’. Note 1: Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.  2009-2018 Microchip Technology Inc. DS30009960F-page 365

PIC18F87K22 FAMILY 25.0 COMPARATOR VOLTAGE EQUATION 25-1: REFERENCE MODULE If CVRSS = 1: The comparator voltage reference is a 32-tap resistor CVREF = (VREF-) + (CVR<4:0>/32) • (VREF+ – VREF-) ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a If CVRSS = 0: reference for the analog comparators, it may also be used independently of them. CVREF = (AVSS) + (CVR<4:0>/32) • (AVDD – AVSS) A block diagram of the module is shown in Figure25-1. The resistor ladder is segmented to provide a range of The comparator reference supply voltage can come CVREF values and has a power-down function to from either VDD and VSS, or the external VREF+ and conserve power when the reference is not being used. VREF- that are multiplexed with RA3 and RA2. The The module’s supply reference can be provided from voltage source is selected by the CVRSS bit either device VDD/VSS or an external voltage reference. (CVRCON<5>). The settling time of the comparator voltage reference 25.1 Configuring the Comparator must be considered when changing the CVREF Voltage Reference output (see Table31-2 in Section31.0 “Electrical The comparator voltage reference module is controlled Characteristics”). through the CVRCON register (Register25-1). The comparator voltage reference provides a range of output voltage with 32 levels. The CVR<4:0> selection bits (CVRCON<4:0>) offer a range of output voltages. Equation25-1 shows the how the comparator voltage reference is computed. REGISTER 25-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin bit 5 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+–VREF- 0 = Comparator reference source, CVRSRC = AVDD–AVSS bit 4-0 CVR<4:0>: Comparator VREF Value Selection 0  CVR<4:0>  31 bits When CVRSS = 1: CVREF = (VREF-) + (CVR<4:0>/32)  (VREF+ – VREF-) When CVRSS = 0: CVREF = (AVSS) + (CVR<4:0>/32)  (AVDD – AVSS) DS30009960F-page 366  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 25-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ AVDD CVRSS = 0 CVR<4:0> R CVREN R R R X U M 32 Steps 1 CVREF o- 2-t 3 R R R CVRSS = 1 VREF- CVRSS = 0 25.2 Voltage Reference Accuracy/Error 25.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit, CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RF5 pin by clearing (Figure25-1) keep CVREF from approaching the refer- bit, CVROE (CVRCON<6>). ence source rails. The voltage reference is derived from the reference source; therefore, the CVREF output 25.5 Connection Considerations changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be The voltage reference module operates independently found in Section31.0 “Electrical Characteristics”. of the comparator module. The output of the reference generator may be connected to the RF5 pin if the 25.3 Operation During Sleep CVROE bit is set. Enabling the voltage reference out- put onto RF5 when it is configured as a digital input will When the device wakes up from Sleep through an increase current consumption. Connecting RF5 as a interrupt or a Watchdog Timer time-out, the contents of digital output, with CVRSS enabled, will also increase the CVRCON register are not affected. To minimize current consumption. current consumption in Sleep mode, the voltage The RF5 pin can be used as a simple D/A output with reference should be disabled. limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure25-2 shows an example buffering technique.  2009-2018 Microchip Technology Inc. DS30009960F-page 367

PIC18F87K22 FAMILY FIGURE 25-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F87K22 CVREF R(1) Module + Voltage RF5 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the Voltage Reference Configuration bits, CVRCON<3:0> and CVRCON<5>. TABLE 25-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CVRCON CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 CM3CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference. DS30009960F-page 368  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 26.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect Control register (HLVD) (Register26-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned The PIC18F87K22 family of devices has a High/Low- off” by the user under software control, which Voltage Detect module (HLVD). This is a programmable minimizes the current consumption for the device. circuit that sets both a device voltage trip point and the The module’s block diagram is shown in Figure26-1. direction of change from that point. If the device experi- ences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the pro- gram execution branches to the interrupt vector address and the software responds to the interrupt. REGISTER 26-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 VDIRMAG BGVST IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 BGVST: Band Gap Reference Voltages Stable Status Flag bit 1 = Internal band gap voltage references are stable 0 = Internal band gap voltage references are not stable bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD is enabled 0 = HLVD is disabled bit 3-0 HLVDL<3:0>: Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting Note 1: For the electrical specifications, see Parameter D420.  2009-2018 Microchip Technology Inc. DS30009960F-page 369

PIC18F87K22 FAMILY The module is enabled by setting the HLVDEN bit trip point voltage. The “trip point” voltage is the voltage (HLVDCON<4>). Each time the HLVD module is level at which the device detects a high or low-voltage enabled, the circuitry requires some time to stabilize. event, depending on the configuration of the module. The IRVST bit (HLVDCON<5>) is a read-only bit used When the supply voltage is equal to the trip point, the to indicate when the circuit is stable. The module can voltage tapped off of the resistor array is equal to the only generate an interrupt after the circuit is stable and internal reference voltage generated by the voltage IRVST is set. reference module. The comparator then generates an The VDIRMAG bit (HLVDCON<7>) determines the interrupt signal by setting the HLVDIF bit. overall operation of the module. When VDIRMAG is The trip point voltage is software programmable to any of cleared, the module monitors for drops in VDD below a 16 values. The trip point is selected by programming the predetermined set point. When the bit is set, the HLVDL<3:0> bits (HLVDCON<3:0>). module monitors for rises in VDD above the set point. The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an 26.1 Operation external source. This mode is enabled when bits, When the HLVD module is enabled, a comparator uses HLVDL<3:0>, are set to ‘1111’. In this state, the an internally generated voltage reference as the set comparator input is multiplexed from the external input point. The set point is compared with the trip point, pin, HLVDIN. This gives users the flexibility of configur- where each node in the resistor divider represents a ing the High/Low-Voltage Detect interrupt to occur at any voltage in the valid operating range. FIGURE 26-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL<3:0> HLVDCON Register HLVDEN VDIRMAG HLVDIN X Set U M HLVDIF 1 o- 6-t 1 HLVDEN Internal Voltage BOREN Reference 1.024V Typical DS30009960F-page 370  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 26.2 HLVD Setup 26.3 Current Consumption To set up the HLVD module: When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static 1. Select the desired HLVD trip point by writing the current. The total current consumption, when enabled, value to the HLVDL<3:0> bits. is specified in electrical specification Parameter D022B 2. Set the VDIRMAG bit to detect high voltage (Table31-14). (VDIRMAG = 1) or low voltage (VDIRMAG = 0). Depending on the application, the HLVD module does 3. Enable the HLVD module by setting the not need to operate constantly. To reduce current HLVDEN bit. requirements, the HLVD circuitry may only need to be 4. Clear the HLVD interrupt flag (PIR2<2>), which enabled for short periods where the voltage is checked. may have been set from a previous interrupt. After such a check, the module could be disabled. 5. If interrupts are desired, enable the HLVD inter- rupt by setting the HLVDIE and GIE bits 26.4 HLVD Start-up Time (PIE2<2> and INTCON<7>, respectively). An interrupt will not be generated until the The internal reference voltage of the HLVD module, IRVST bit is set. specified in electrical specification Parameter 37 (Section31.0 “Electrical Characteristics”), may be Note: Before changing any module settings used by other internal circuitry, such as the (VDIRMAG, LVDL<3:0>), first disable the programmable Brown-out Reset. If the HLVD or other module (LVDEN = 0), make the changes circuits using the voltage reference are disabled to and re-enable the module. This prevents lower the device’s current consumption, the reference the generation of false HLVD events. voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. This start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical specification Parameter 37 (Table31-14). The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval (see Figure26-2 or Figure26-3).  2009-2018 Microchip Technology Inc. DS30009960F-page 371

PIC18F87K22 FAMILY FIGURE 26-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be Set VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST HLVDIF Cleared in Software Internal Reference is Stable CASE 2: VDD VHLVD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is Stable HLVDIF Cleared in Software HLVDIF Cleared in Software, HLVDIF Remains Set since HLVD Condition still Exists DS30009960F-page 372  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 26-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be Set VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST HLVDIF Cleared in Software Internal Reference is Stable CASE 2: VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is Stable HLVDIF Cleared in Software HLVDIF Cleared in Software, HLVDIF Remains Set since HLVD Condition still Exists 26.5 Applications FIGURE 26-4: TYPICAL LOW-VOLTAGE DETECT APPLICATION In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach VA would indicate a High-Voltage Detect from, for example, VB 3.3V to 5V (the voltage on USB) and vice versa for a e g detach. This feature could save a design a few extra a components and an attach signal (input pin). olt V For general battery applications, Figure26-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an Interrupt Time TA TB Service Routine (ISR), which would allow the applica- tion to perform “housekeeping tasks” and a controlled Legend: VA = HLVD trip point shutdown before the device voltage exits the valid VB = Minimum valid device operating range at TB. This would give the application operating voltage a time window, represented by the difference between TA and TB, to safely exit.  2009-2018 Microchip Technology Inc. DS30009960F-page 373

PIC18F87K22 FAMILY 26.6 Operation During Sleep 26.7 Effects of a Reset When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state. during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off. point, the HLVDIF bit will be set and the device will wake up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 26-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR2 OSCFIF — SSP2IF BLC2IF BCL1IF HLVDIF TMR3IF TMR3GIF PIE2 OSCFIE — SSP2IE BLC2IE BCL1IE HLVDIE TMR3IE TMR3GIE IPR2 OSCFIP — SSP2IP BLC2IP BCL1IP HLVDIP TMR3IP TMR3GIP TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. DS30009960F-page 374  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 27.0 CHARGE TIME • Control of response to edges MEASUREMENT UNIT (CTMU) • Time measurement resolution of one nanosecond • High-precision time measurement The Charge Time Measurement Unit (CTMU) is a • Time delay of external or internal signal flexible analog module that provides accurate differen- asynchronous to system clock tial time measurement between pulse sources, as well • Accurate current source suitable for capacitive as asynchronous pulse generation. By working with measurement other on-chip analog modules, the CTMU can precisely measure time, capacitance and relative changes in The CTMU works in conjunction with the A/D Converter capacitance or generate output pulses with a specific to provide up to 24 channels for time or charge time delay. The CTMU is ideal for interfacing with measurement, depending on the specific device and capacitive-based sensors. the number of A/D channels available. When config- ured for time delay, the CTMU is connected to one of The module includes these key features: the analog comparators. The level-sensitive input edge • Up to 24 channels available for capacitive or time sources can be selected from four sources: two measurement input external inputs or the ECCP1/ECCP2 Special Event • On-chip precision current source Triggers. • Four-edge input trigger sources The CTMU special event can trigger the Analog-to-Digital • Polarity control for each edge source Converter module. • Control of edge sequence Figure27-1 provides a block diagram of the CTMU. FIGURE 27-1: CTMU BLOCK DIAGRAM CTMUCON CTMUICON EDGEN EDGSEQEN EDG1SELx ITRIM<5:0> TGEN EDG1POL IRNG<1:0> IDISSEN EDG2SELx EDG1STAT CTTRIG Current Source EDG2POL EDG2STAT CTED1 Edge CTMU Control Control A/D Trigger CTED2 Logic Current Logic Control ECCP2 Pulse CTPLS ECCP1 Generator A/D Converter Comparator 2 Input Comparator 2 Output  2009-2018 Microchip Technology Inc. DS30009960F-page 375

PIC18F87K22 FAMILY 27.1 CTMU Registers The CTMUCONH and CTMUCONL registers (Register27-1 and Register27-2) contain control bits The control registers for the CTMU are: for configuring the CTMU module edge source selec- • CTMUCONH tion, edge source polarity selection, edge sequencing, • CTMUCONL A/D trigger, analog circuit capacitor discharge and enables. The CTMUICON register (Register27-3) has • CTMUICON bits for selecting the current source range and current source trim. REGISTER 27-1: CTMUCONH: CTMU CONTROL HIGH REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 4 TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation bit 3 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 2 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 1 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 0 CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled DS30009960F-page 376  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 27-2: CTMUCONL: CTMU CONTROL LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = ECCP2 Special Event Trigger bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = ECCP2 Special Event Trigger bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred  2009-2018 Microchip Technology Inc. DS30009960F-page 377

PIC18F87K22 FAMILY REGISTER 27-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current bit 1-0 IRNG<1:0>: Current Source Range Select bits 11 = 100 x Base Current 10 = 10 x Base Current 01 = Base Current Level (0.55A nominal) 00 = Current Source Disabled DS30009960F-page 378  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 27.2 CTMU Operation Current trim is provided by the ITRIM<5:0> bits (CTMUICON<7:2>). These six bits allow trimming of The CTMU works by using a fixed current source to the current source in steps of approximately 2% per charge a circuit. The type of circuit depends on the type step. Half of the range adjusts the current source posi- of measurement being made. tively and the other half reduces the current source. A In the case of charge measurement, the current is fixed value of ‘000000’ is the neutral position (no change). A and the amount of time the current is applied to the cir- value of ‘100000’ is the maximum negative adjustment cuit is fixed. The amount of voltage read by the A/D (approximately -62%) and ‘011111’ is the maximum becomes a measurement of the circuit’s capacitance. positive adjustment (approximately +62%). In the case of time measurement, the current, as well 27.2.3 EDGE SELECTION AND CONTROL as the capacitance of the circuit, is fixed. In this case, the voltage read by the A/D is representative of the CTMU measurements are controlled by edge events amount of time elapsed from the time the current occurring on the module’s two input channels. Each source starts and stops charging the circuit. channel, referred to as Edge 1 and Edge 2, can be con- If the CTMU is being used as a time delay, both capaci- figured to receive input pulses from one of the edge tance and current source are fixed, as well as the voltage input pins (CTED1 and CTED2) or CCPx Special Event supplied to the comparator circuit. The delay of a signal Triggers. The input channels are level-sensitive, is determined by the amount of time it takes the voltage responding to the instantaneous level on the channel to charge to the comparator threshold voltage. rather than a transition between levels. The inputs are selected using the EDG1SEL and EDG2SEL bit pairs 27.2.1 THEORY OF OPERATION (CTMUCONL<3:2, 6:5>). The operation of the CTMU is based on the equation In addition to source, each channel can be configured for for charge: event polarity using the EDGE2POL and EDGE1POL dV bits (CTMUCONL<7,4>). The input channels can also C = I • dT be filtered for an edge event sequence (Edge 1 occur- ring before Edge 2) by setting the EDGSEQEN bit More simply, the amount of charge measured in (CTMUCONH<2>). coulombs in a circuit is defined as current in amperes 27.2.4 EDGE STATUS (I) multiplied by the amount of time in seconds that the current flows (t). Charge is also defined as the capaci- The CTMUCON register also contains two status bits: tance in farads (C) multiplied by the voltage of the EDG2STAT and EDG1STAT (CTMUCONL<1:0>). circuit (V). It follows that: Their primary function is to show if an edge response has occurred on the corresponding channel. The I • t = C • V CTMU automatically sets a particular bit when an edge response is detected on its channel. The level-sensitive The CTMU module provides a constant, known current nature of the input channels also means that the status source. The A/D Converter is used to measure (V) in bits become set immediately if the channel’s configura- the equation, leaving two unknowns: capacitance (C) tion is changed and matches the channel’s current and time (t). The above equation can be used to calcu- state. late capacitance or time, by either the relationship using the known fixed capacitance of the circuit: The module uses the edge status bits to control the cur- rent source output to external analog modules (such as t = (C • V)/I the A/D Converter). Current is only supplied to external modules when only one (not both) of the status bits is or by: set. Current is shut off when both bits are either set or C = (I • t)/V cleared. This allows the CTMU to measure current only during the interval between edges. After both status using a fixed time that the current source is applied to bits are set, it is necessary to clear them before another the circuit. measurement is taken. Both bits should be cleared simultaneously, if possible, to avoid re-enabling the 27.2.2 CURRENT SOURCE CTMU current source. At the heart of the CTMU is a precision current source, In addition to being set by the CTMU hardware, the designed to provide a constant reference for measure- edge status bits can also be set by software. This per- ments. The level of current is user-selectable across mits a user application to manually enable or disable three ranges or a total of two orders of magnitude, with the current source. Setting either (but not both) of the the ability to trim the output in ±2% increments bits enables the current source. Setting or clearing both (nominal). The current range is selected by the bits at once disables the source. IRNG<1:0> bits (CTMUICON<1:0>), with a value of ‘00’ representing the lowest range.  2009-2018 Microchip Technology Inc. DS30009960F-page 379

PIC18F87K22 FAMILY 27.2.5 INTERRUPTS Depending on the type of measurement or pulse generation being performed, one or more additional The CTMU sets its interrupt flag (PIR3<3>) whenever modules may also need to be initialized and configured the current source is enabled, then disabled. An inter- with the CTMU module: rupt is generated only if the corresponding interrupt enable bit (PIE3<3>) is also set. If edge sequencing is • Edge Source Generation: In addition to the not enabled (i.e., Edge 1 must occur before Edge 2), it external edge input pins, CCPx Special Event is necessary to monitor the edge status bits and Triggers can be used as edge sources for the determine which edge occurred last and caused the CTMU. interrupt. • Capacitance or Time Measurement: The CTMU module uses the A/D Converter to measure the 27.3 CTMU Module Initialization voltage across a capacitor that is connected to one of the analog input channels. The following sequence is a general guideline used to • Pulse Generation: When generating system clock initialize the CTMU module: independent, output pulses, the CTMU module 1. Select the current source range using the uses Comparator 2 and the associated IRNGx bits (CTMUICON<1:0>). comparator voltage reference. 2. Adjust the current source trim using the ITRIMx bits (CTMUICON<7:2>). 27.4 Calibrating the CTMU Module 3. Configure the edge input sources for Edge 1 and The CTMU requires calibration for precise measure- Edge 2 by setting the EDG1SEL and EDG2SEL ments of capacitance and time, as well as for accurate bits (CTMUCONL<3:2> and <6:5>, respectively). time delay. If the application only requires measurement 4. Configure the input polarities for the edge inputs of a relative change in capacitance or time, calibration is using the EDG2POL and EDG1POL bits usually not necessary. An example of a less precise (CTMUCONL<7,4>). application is a capacitive touch switch, in which the The default configuration is for negative edge touch circuit has a baseline capacitance and the added polarity (high-to-low transitions). capacitance of the human body changes the overall capacitance of a circuit. 5. Enable edge sequencing using the EDGSEQEN bit (CTMUCONH<2>). If actual capacitance or time measurement is required, two hardware calibrations must take place: By default, edge sequencing is disabled. • The current source needs calibration to set it to a 6. Select the operating mode (Measurement or precise current. Time Delay) with the TGEN bit. • The circuit being measured needs calibration to The default mode is Time/Capacitance measure or nullify any capacitance other than that Measurement. to be measured. 7. Configure the module to automatically trigger an A/D conversion when the second edge 27.4.1 CURRENT SOURCE CALIBRATION event has occurred, using the CTTRIG bit The current source on board the CTMU module has a (CTMUCONH<0>). range of ±60% nominal for each of three current The conversion trigger is disabled by default. ranges. For precise measurements, it is possible to measure and adjust this current source by placing a 8. Discharge the connected circuit by setting the IDISSEN bit (CTMUCONH<1>). high-precision resistor, RCAL, onto an unused analog channel. An example circuit is shown in Figure27-2. 9. After waiting a sufficient time for the circuit to discharge, clear IDISSEN. To measure the current source: 10. Disable the module by clearing the CTMUEN bit 1. Initialize the A/D Converter. (CTMUCONH<7>). 2. Initialize the CTMU. 11. Clear the Edge Status bits, EDG2STAT and 3. Enable the current source by setting EDG1STAT EDG1STAT (CTMUCONL<1:0>). (CTMUCONL<0>). 12. Enable both edge inputs by setting the EDGEN 4. Issue the settling time delay. bit (CTMUCONH<3>). 5. Perform the A/D conversion. 13. Enable the module by setting the CTMUEN bit. 6. Calculate the current source current using I=V/RCAL, where RCAL is a high-precision resistance and V is measured by performing an A/D conversion. DS30009960F-page 380  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY The CTMU current source may be trimmed with the A value of 70% of full-scale voltage is chosen to make trim bits in CTMUICON using an iterative process to get sure that the A/D Converter was in a range that is well the exact current desired. Alternatively, the nominal above the noise floor. If an exact current is chosen to value without adjustment may be used. That value may incorporate the trimming bits from CTMUICON, the be stored by software for use in all subsequent resistor value of RCAL may need to be adjusted accord- capacitive or time measurements. ingly. RCAL may also be adjusted to allow for available To calculate the value for RCAL, the nominal current resistor values. RCAL should be of the highest precision available, in light of the precision needed for the circuit must be chosen. Then, the resistance can be that the CTMU will be measuring. A recommended calculated. minimum would be 0.1% tolerance. For example, if the A/D Converter reference voltage is The following examples show a typical method for 3.3V, use 70% of full scale (or 2.31V) as the desired performing a CTMU current calibration. approximate voltage to be read by the A/D Converter. If the range of the CTMU current source is selected to be • Example27-1 demonstrates how to initialize the 0.55 A, the resistor value needed is calculated as A/D Converter and the CTMU. RCAL=2.31V/0.55A, for a value of 4.2MΩ. Similarly, This routine is typical for applications using both if the current source is chosen to be 5.5A, RCAL would modules. be 420,000Ω, and 42,000Ω if the current source is set to 55A. • Example27-2 demonstrates one method for the actual calibration routine. FIGURE 27-2: CTMU CURRENT SOURCE This method manually triggers the A/D Converter to CALIBRATION CIRCUIT demonstrate the entire step-wise process. It is also possible to automatically trigger the conversion by PIC18F87K22 setting the CTMU’s CTTRIG bit (CTMUCONH<0>). CTMU Current Source A/D Trigger A/D Converter ANx A/D RCAL MUX  2009-2018 Microchip Technology Inc. DS30009960F-page 381

PIC18F87K22 FAMILY EXAMPLE 27-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.h" /**************************************************************************/ /*Setup CTMU *****************************************************************/ /**************************************************************************/ void setup(void) { //CTMUCON - CTMU Control register CTMUCONH = 0x00; //make sure CTMU is disabled CTMUCONL = 0X90; //CTMU continues to run when emulator is stopped,CTMU continues //to run in idle mode,Time Generation mode disabled, Edges are blocked //No edge sequence order, Analog current source not grounded, trigger //output disabled, Edge2 polarity = positive level, Edge2 source = //source 0, Edge1 polarity = positive level, Edge1 source = source 0, // Set Edge status bits to zero //CTMUICON - CTMU Current Control Register CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment /**************************************************************************/ //Setup AD converter; /**************************************************************************/ TRISA=0x04; //set channel 2 as an input // Configured AN2 as an analog channel // ANCON0 ANCON0 = 0X04; // ANCON1 ANCON1 = 0XE0; // ADCON2 ADCON2bits.ADFM=1; // Resulst format 1= Right justified ADCON2bits.ACQT=1; // Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD ADCON2bits.ADCS=2; // Clock conversion bits 6= FOSC/64 2=FOSC/32 // ADCON0 ADCON1bits.VCFG0 =0; // Vref+ = AVdd ADCON0bits.VCFG1 =0; // Vref+ = AVdd ADCON0bits.VCFG = 0; // Vref- = AVss ADCON0bits.CHS=2; // Select ADC channel ADCON0bits.ADON=1; // Turn on ADC } DS30009960F-page 382  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY EXAMPLE 27-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 //@ 8MHz = 125uS. #define DELAY for(i=0;i<COUNT;i++) #define RCAL .027 //R value is 4200000 (4.2M) //scaled so that result is in //1/100th of uA #define ADSCALE 1023 //for unsigned conversion 10 sig bits #define ADREF 3.3 //Vdd connected to A/D Vr+ int main(void) { int i; int j = 0; //index for loop unsigned int Vread = 0; double VTot = 0; float Vavg=0, Vcal=0, CTMUISrc = 0; //float values stored for calcs //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag VTot += Vread; //Add the reading to the total } Vavg = (float)(VTot/10.000); //Average of 10 readings Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA }  2009-2018 Microchip Technology Inc. DS30009960F-page 383

PIC18F87K22 FAMILY 27.4.2 CAPACITANCE CALIBRATION This measured value is then stored and used for calculations of time measurement or subtracted for There is a small amount of capacitance from the inter- capacitance measurement. For calibration, it is nal A/D Converter sample capacitor, as well as stray expected that the capacitance of CSTRAY+CAD is capacitance from the circuit board traces and pads that approximately known; CAD is approximately 4pF. affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by An iterative process may be required to adjust the time, making sure the desired capacitance to be measured t, that the circuit is charged to obtain a reasonable volt- has been removed. age reading from the A/D Converter. The value of t may be determined by setting COFFSET to a theoretical value After removing the capacitance to be measured: and solving for t. For example, if CSTRAY is theoretically 1. Initialize the A/D Converter and the CTMU. calculated to be 11pF, and V is expected to be 70% of 2. Set EDG1STAT (=1). VDD or 2.31V, t would be: 3. Wait for a fixed delay of time, t. (4 pF + 11 pF) • 2.31V/0.55 A 4. Clear EDG1STAT. 5. Perform an A/D conversion. or 63s. 6. Calculate the stray and A/D sample capacitances: See Example27-3 for a typical routine for CTMU COFFSET = CSTRAY + CAD = (I • t)/V capacitance calibration. Where: • I is known from the current source measurement step • t is a fixed delay • V is measured by performing an A/D conversion DS30009960F-page 384  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY EXAMPLE 27-3: CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 25 //@ 8MHz INTFRC = 62.5 us. #define ETIME COUNT*2.5 //time in uS #define DELAY for(i=0;i<COUNT;i++) #define ADSCALE 1023 //for unsigned conversion 10 sig bits #define ADREF 3.3 //Vdd connected to A/D Vr+ #define RCAL .027 //R value is 4200000 (4.2M) //scaled so that result is in //1/100th of uA int main(void) { int i; int j = 0; //index for loop unsigned int Vread = 0; float CTMUISrc, CTMUCap, Vavg, VTot, Vcal; //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag VTot += Vread; //Add the reading to the total } Vavg = (float)(VTot/10.000); //Average of 10 readings Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA CTMUCap = (CTMUISrc*ETIME/Vcal)/100; }  2009-2018 Microchip Technology Inc. DS30009960F-page 385

PIC18F87K22 FAMILY 27.5 Measuring Capacitance with the 27.5.2 RELATIVE CHARGE CTMU MEASUREMENT Not all applications require precise capacitance There are two ways to measure capacitance with the measurements. When detecting a valid press of a CTMU. The absolute method measures the actual capacitance-based switch, only a relative change of capacitance value. The relative method only measures capacitance needs to be detected. for any change in the capacitance. In such an application, when the switch is open (or not 27.5.1 ABSOLUTE CAPACITANCE touched), the total capacitance is the capacitance of the MEASUREMENT combination of the board traces, the A/D Converter and other elements. A larger voltage will be measured by the For absolute capacitance measurements, both the A/D Converter. When the switch is closed (or touched), current and capacitance calibration steps found in the total capacitance is larger due to the addition of the Section 27.4 “Calibrating the CTMU Module” should capacitance of the human body to the above listed be followed. capacitances and a smaller voltage will be measured by To perform these measurements: the A/D Converter. 1. Initialize the A/D Converter. To detect capacitance changes simply: 2. Initialize the CTMU. 1. Initialize the A/D Converter and the CTMU. 3. Set EDG1STAT. 2. Set EDG1STAT. 4. Wait for a fixed delay, T. 3. Wait for a fixed delay. 5. Clear EDG1STAT. 4. Clear EDG1STAT. 6. Perform an A/D conversion. 5. Perform an A/D conversion. 7. Calculate the total capacitance, CTOTAL = (I * T)/V, The voltage measured by performing the A/D conver- where: sion is an indication of the relative capacitance. In this • I is known from the current source case, no calibration of the current source or circuit measurement step (Section 27.4.1 “Current capacitance measurement is needed. (For a sample Source Calibration”) software routine for a capacitive touch switch, see • T is a fixed delay Example27-4.) • V is measured by performing an A/D conversion 8. Subtract the stray and A/D capacitance (COFFSET from Section 27.4.2 “Capacitance Calibration”) from CTOTAL to determine the measured capacitance. DS30009960F-page 386  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY EXAMPLE 27-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define COUNT 500 //@ 8MHz = 125uS. #define DELAY for(i=0;i<COUNT;i++) #define OPENSW 1000 //Un-pressed switch value #define TRIP 300 //Difference between pressed //and un-pressed switch #define HYST 65 //amount to change //from pressed to un-pressed #define PRESSED 1 #define UNPRESSED 0 int main(void) { unsigned int Vread; //storage for reading unsigned int switchState; int i; //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D if(Vread < OPENSW - TRIP) { switchState = PRESSED; } else if(Vread > OPENSW - TRIP + HYST) { switchState = UNPRESSED; } }  2009-2018 Microchip Technology Inc. DS30009960F-page 387

PIC18F87K22 FAMILY 27.6 Measuring Time with the CTMU It is assumed that the time measured is small enough Module that the capacitance, COFFSET, provides a valid voltage to the A/D Converter. For the smallest time measure- Time can be precisely measured after the ratio (C/I) is ment, always set the A/D Channel Select register measured from the current and capacitance calibration (AD1CHS) to an unused A/D channel, the correspond- step. To do that: ing pin for which is not connected to any circuit board 1. Initialize the A/D Converter and the CTMU. trace. This minimizes added stray capacitance, keep- ing the total circuit capacitance close to that of the A/D 2. Set EDG1STAT. Converter itself (25pF). 3. Set EDG2STAT. To measure longer time intervals, an external capacitor 4. Perform an A/D conversion. may be connected to an A/D channel and that channel 5. Calculate the time between edges as T = (C/I) * V, selected whenever making a time measurement. where: • I is calculated in the current calibration step (Section 27.4.1 “Current Source Calibration”) • C is calculated in the capacitance calibra- tion step (Section 27.4.2 “Capacitance Calibration”) • V is measured by performing the A/D conversion FIGURE 27-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC18F87K22 CTMU CTED1 EDG1 Current Source CTED2 EDG2 Output Pulse A/D Converter ANX CAD RPR DS30009960F-page 388  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 27.7 Creating a Delay with the CTMU An example use of the external capacitor feature is Module interfacing with variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the A unique feature on board the CTMU module is its ability pulse-width output on CTPLS will vary. An example use to generate system clock independent output pulses, of the CTDIN feature is interfacing with a digital sensor. based on either an external voltage or an external The CTPLS output pin can be connected to an input capacitor value. When using an external voltage, this is capture pin and the varying pulse width measured to accomplished using the CTDIN input pin as a trigger for determine the sensor’s output in the application. the pulse delay. When using an external capacitor To use this feature: value, this is accomplished using the internal compara- tor voltage reference module and Comparator 2 input 1. If CTMUDS is cleared, initialize Comparator 2. pin.The pulse is output onto the CTPLS pin. To enable 2. If CTMUDS is cleared, initialize the comparator this mode, set the TGEN bit. voltage reference. See Figure27-4 for an example circuit. When 3. Initialize the CTMU and enable time delay CTMUDS (ODCON3<0>) is cleared, the pulse delay is generation by setting the TGEN bit. determined by the output of Comparator 2, and when it 4. Set EDG1STAT. is set, the pulse delay is determined by the input of When CTMUDS is cleared, as soon as CDELAY charges CTDIN. CDELAY is chosen by the user to determine the to the value of the voltage reference trip point, an out- output pulse width on CTPLS. The pulse width is calcu- put pulse is generated on CTPLS. When CTMUDS is lated by T = (CDELAY/I)*V, where I is known from the set, as soon as CTDIN is set, an output pulse is current source measurement step (Section27.4.1 generated on CTPLS. “Current Source Calibration”) and V is the Internal Reference Voltage (CVREF). FIGURE 27-4: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC18F87K22 CTMU CTED1 EDG1 CTPLS Current Source Comparator CTMUDS CTMUI CTDIN C2 CDELAY CVREF C1 External Reference External Comparator  2009-2018 Microchip Technology Inc. DS30009960F-page 389

PIC18F87K22 FAMILY 27.8 Measuring Temperature with the source the current to the diode. The ADC reading will CTMU Module reflect the temperature. With the increase, the ADC readings will go low. This can be used for low-cost The CTMU, along with an internal diode, can be used temperature measurement applications. to measure the temperature. The ADC can be con- nected to the internal diode and the CTMU module can EXAMPLE 27-5: ROUTINE FOR TEMPERATURE MEASUREMENT USING INTERNAL DIODE // Initialize CTMU CTMUICON = 0x03; CTMUCONHbits.CTMUEN = 1; CTMUCONLbits.EDG1STAT = 1; // Initialize ADC ADCON0 = 0xE5; // Enable ADC and connect to Internal diode ADCON1 = 0x00; ADCON2 = 0xBE; // Right Justified ADCON0bits.GO = 1; // Start conversion while(ADCON0bits.G0); Temp = ADRES; // Read ADC results (inversely proportional to temperature) Note: The temperature diode is not calibrated or standardized; the user must calibrate the diode to their application. DS30009960F-page 390  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 27.9 Operation During Sleep/Idle Modes 27.10 Effects of a Reset on CTMU 27.9.1 SLEEP MODE Upon Reset, all registers of the CTMU are cleared. This disables the CTMU module, turns off its current source When the device enters any Sleep mode, the CTMU and returns all configuration options to their default set- module current source is always disabled. If the CTMU tings. The module needs to be re-initialized following is performing an operation that depends on the current any Reset. source when Sleep mode is invoked, the operation may If the CTMU is in the process of taking a measurement not terminate correctly. Capacitance and time at the time of Reset, the measurement will be lost. A measurements may return erroneous values. partial charge may exist on the circuit that was being 27.9.2 IDLE MODE measured, which should be properly discharged before the CTMU makes subsequent attempts to make a The behavior of the CTMU in Idle mode is determined measurement. The circuit is discharged by setting and by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL clearing the IDISSEN bit (CTMUCONH<1>) while the is cleared, the module will continue to operate in Idle A/D Converter is connected to the appropriate channel. mode. If CTMUSIDL is set, the module’s current source is disabled when the device enters Idle mode. In this case, if the module is performing an operation when Idle mode is invoked, the results will be similar to those with Sleep mode. TABLE 27-1: REGISTERS ASSOCIATED WITH CTMU MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.  2009-2018 Microchip Technology Inc. DS30009960F-page 391

PIC18F87K22 FAMILY 28.0 SPECIAL FEATURES OF THE 28.1 Configuration Bits CPU The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various The PIC18F87K22 family of devices includes several device configurations. These bits are mapped starting features intended to maximize reliability and minimize at program memory location, 300000h. cost through elimination of external components. These include: The user will note that address, 300000h, is beyond the user program memory space. In fact, it belongs to the • Oscillator Selection configuration memory space (300000h-3FFFFFh), • Resets: which can only be accessed using table reads and - Power-on Reset (POR) table writes. - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) Software programming of the Configuration registers is - Brown-out Reset (BOR) done in a manner similar to programming the Flash memory. The WR bit in the EECON1 register starts a • Interrupts self-timed write to the Configuration register. In normal • Watchdog Timer (WDT) and On-chip Regulator Operation mode, a TBLWT instruction, with the TBLPTR • Fail-Safe Clock Monitor pointing to the Configuration register, sets up the • Two-Speed Start-up address and the data for the Configuration register write. • Code Protection Setting the WR bit starts a long write to the Configuration • ID Locations register. The Configuration registers are written a byte at • In-Circuit Serial Programming™ (ICSP™) a time. To write or erase a configuration cell, a TBLWT The oscillator can be configured for the application instruction can write a ‘1’ or a ‘0’ into the cell. For depending on frequency, power, accuracy and cost. All additional details on Flash programming, refer to of the options are discussed in detail in Section3.0 Section7.5 “Writing to Flash Program Memory”. “Oscillator Configurations”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, the PIC18F87K22 family of devices has a Watchdog Timer, which is either perma- nently enabled via the Configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator (LF-INTOSC) also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its fail- ure. Two-Speed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits. DS30009960F-page 392  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 28-1: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300000h CONFIG1L — XINST — SOSCSEL1 SOSCSEL0 INTOSCSEL — RETEN -1-1 1--1 300001h CONFIG1H IESO FCMEN — PLLCFG FOSC3 FOSC2 FOSC1 FOSC0 00-0 1000 300002h CONFIG2L — BORPWR1 BORWPR0 BORV1 BORV0 BOREN1 BOREN0 PWRTEN -111 1111 300003h CONFIG2H — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 -111 1111 300004h CONFIG3L WAIT(2) BW(2) ABW1(2) ABW0(2) EASHFT(2) — — RTCOSC ---- ---1 300005h CONFIG3H MCLRE — — — MSSPMSK — ECCPMX(2) CCP2MX 1--- 1-11 300006h CONFIG4L DEBUG — — BBSIZ0 — — — STVREN 1--1 ---1 300008h CONFIG5L CP7(1) CP6(1) CP5(1) CP4(1) CP3 CP2 CP1 CP0 1111 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L WRT7(1) WRT6(1) WRT5(1) WRT4(1) WRT3 WRT2 WRT1 WRT0 1111 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L EBTR7(1) EBTR6(1) EBTR5(1) EBTR4(1) EBTR3 EBTR2 EBTR1 EBTR0 1111 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1(3) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx 3FFFFFh DEVID2(3) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Implemented only on the PIC18F67K22 and PIC18F87K22 devices. 2: Implemented only on the 80-pin devices (PIC18F8XK22). 3: See Register28-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.  2009-2018 Microchip Technology Inc. DS30009960F-page 393

PIC18F87K22 FAMILY REGISTER 28-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) U-0 R/P-1 U-0 R/P-1 R/P-1 R/P-1 U-0 R/P-1 — XINST — SOSCSEL1 SOSCSEL0 INTOSCSEL — RETEN bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode are enabled 0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode) bit 5 Unimplemented: Read as ‘0’ bit 4-3 SOSCSEL<1:0>: SOSC Power Selection and Mode Configuration bits 11 = High-power SOSC circuit is selected 10 = Digital (SCLKI) mode; I/O port functionality of RC0 and RC1 is enabled 01 = Low-power SOSC circuit is selected 00 = Reserved bit 2 INTOSCSEL: LF-INTOSC Low-power Enable bit 1 = LF-INTOSC is in High-Power mode during Sleep 0 = LF-INTOSC is in Low-Power mode during Sleep bit 1 Unimplemented: Read as ‘0’ bit 0 RETEN: VREG Sleep Enable bit 1 = Regulator power while in Sleep mode is controlled by VREGSLP (WDTCON<7>) 0 = Regulator power while in Sleep mode is controlled by SRETEN (WDTCON<4>). Ultra low-power regulator is enabled. DS30009960F-page 394  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 28-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-1 R/P-0 R/P-0 R/P-0 IESO FCMEN — PLLCFG(1) FOSC3(2) FOSC2(2) FOSC1(2) FOSC0(2) bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Two-Speed Start-up is enabled 0 = Two-Speed Start-up is disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 5 Unimplemented: Read as ‘0’ bit 4 PLLCFG: 4x PLL Enable bit(1) 1 = Oscillator is multiplied by 4 0 = Oscillator is used directly bit 3-0 FOSC<3:0>: Oscillator Selection bits(2) 1101 = EC1, EC oscillator (low power, DC-160 kHz) 1100 = EC1IO, EC oscillator with CLKOUT function on RA6 (low power, DC-160 kHz) 1011 = EC2, EC oscillator (medium power, 160 kHz-16 MHz) 1010 = EC2IO, EC oscillator with CLKOUT function on RA6 (medium power, DC-160 kHz-16 MHz) 1001 = INTIO1, internal RC oscillator with CLKOUT function on RA6 1000 = INTIO2, internal RC oscillator 0111 = RC, external RC oscillator 0110 = RCIO, external RC oscillator with CKLOUT function on RA6 0101 = EC3, EC oscillator (high power, 4 MHz-64 MHz) 0100 = EC3IO, EC oscillator with CLKOUT function on RA6 (high power, 4 MHz-64 MHz) 0011 = HS1, HS oscillator (medium power, 4 MHz-16 MHz) 0010 = HS2, HS oscillator (high power, 16 MHz-25 MHz) 0001 = XT oscillator 0000 = LP oscillator Note 1: Not valid for the INTIOx PLL mode. 2: INTIO + PLL can be enabled only by the PLLEN bit (OSCTUNE<6>). Other PLL modes can be enabled by either the PLLEN bit or the PLLCFG (CONFIG1H<4>) bit.  2009-2018 Microchip Technology Inc. DS30009960F-page 395

PIC18F87K22 FAMILY REGISTER 28-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — BORPWR1(1) BORPWR0(1) BORV1(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2) bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-5 BORPWR<1:0>: BORMV Power-Level bits(1) 11 = ZPBORVMV instead of BORMV is selected 10 = BORMV is set to a high-power level 01 = BORMV is set to a medium power level 00 = BORMV is set to a low-power level bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1) 11 = VBORMV is set to 1.8V 10 = VBORMV is set to 2.0V 01 = VBORMV is set to 2.7V 00 = VBORMV is set to 3.0V bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits(2) 11 = Brown-out Reset is enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset is enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset is enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset is disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT is disabled 0 = PWRT is enabled Note 1: For the specifications, see Section31.1 “DC Characteristics: Supply Voltage PIC18F87K22 Family (Industrial/Extended)”. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. DS30009960F-page 396  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 28-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-2 WDTPS<4:0>: Watchdog Timer Postscale Select bits 10101-11111 = Reserved 10100 = 1:1,048,576 (4,194.304s) 10011 = 1:524,288 (2,097.152s) 10010 = 1:262,144 (1,048.576s) 10001 = 1:131,072 (524.288s) 10000 = 1:65,536 (262.144s) 01111 = 1:32,768 (131.072s) 01110 = 1:16,384 (65.536s) 01101 = 1:8,192 (32.768s) 01100 = 1:4,096 (16.384s) 01011 = 1:2,048 (8.192s) 01010 = 1:1,024 (4.096s) 01001 = 1:512 (2.048s) 01000 = 1:256 (1.024s) 00111 = 1:128 (512 ms) 00110 = 1:64 (256 ms) 00101 = 1:32 (128 ms) 00100 = 1:16 (64 ms) 00011 = 1:8 (32 ms) 00010 = 1:4 (16 ms) 00001 = 1:2 (8 ms) 00000 = 1:1 (4 ms) bit 1-0 WDTEN<1:0>: Watchdog Timer Enable bits 11 = WDT is enabled in hardware; SWDTEN bit is disabled 10 = WDT is controlled by the SWDTEN bit setting 01 = WDT is enabled only while the device is active and disabled in Sleep mode; SWDTEN bit is disabled 00 = WDT is disabled in hardware; SWDTEN bit is disabled  2009-2018 Microchip Technology Inc. DS30009960F-page 397

PIC18F87K22 FAMILY REGISTER 28-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) U-1 U-1 U-1 U-1 U-1 U-0 U-0 R/P-1 WAIT(1) BW(1) ABW1(1) ABW0(1) EASHFT(1) — — RTCOSC bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states on the external bus are disabled 0 = Wait states on the external bus are enabled and selected by MEMCON <5:4> bit 6 BW: Data Bus Width Select bit(1) 1 = 16-Bit Data Width modes 0 = 8-Bit Data Width modes bit 5-4 ABW<1:0>: External Memory Bus Configuration bits(1) 11 = 8-Bit Address mode (Microcontroller mode) 10 = 12-Bit Address mode 01 = 16-Bit Address mode 00 = 20-Bit Address mode bit 3 EASHFT: External Address Bus Shift Enable bit(1) 1 = Address shifting is enabled; external address is shifted to start at 000000h 0 = Address shifting is disabled; external address bus reflects the PC value bit 2-1 Unimplemented: Read as ‘0’ bit 0 RTCOSC: RTCC Reference Clock Select bit 1 = RTCC uses SOSC as the reference clock 0 = RTCC uses LF-INTOSC as the reference clock Note 1: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. DS30009960F-page 398  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 28-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 R/P-1 U-0 R/P-1 R/P-1 MCLRE — — — MSSPMSK — ECCPMX(1) CCP2MX bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin is enabled; RG5 input pin is disabled 0 = RG5 input pin is enabled; MCLR is disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 MSSPMSK: MSSP V3 7-Bit Address Masking Mode Enable bit 1 = 7-Bit Address Masking mode is enabled 0 = 5-Bit Address Masking mode is enabled bit 2 Unimplemented: Read as ‘0’ bit 1 ECCPMX: ECCP MUX bit(1) 1 = - ECCP1 (P1B/P1C) is multiplexed onto RE6 and RE5, CCP6 onto RE6, and CCP7 onto RE5 - ECCP3 (P3B/P3C) is multiplexed onto RE4 and RE3, CCP8 onto RE4, and CCP9 onto RE3 0 = - ECCP1 (P1B/P1C) is multiplexed onto RH7 and RH6, CCP6 onto RH7, and CCP7(2) onto RH6 - ECCP3 (P3B/P3C) is multiplexed onto RH5 and RH4, CCP8 onto RH5, and CCP9(2) onto RH4 bit 0 CCP2MX: ECCP2 MUX bit 1 = ECCP2 is multiplexed with RC1 0 = ECCP2 is multiplexed with RB3 in Extended Microcontroller mode; ECCP2 is multiplexed with RE7 in Microcontroller mode Note 1: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’. 2: Not implemented on 32K devices (PIC18F65K22 and PIC18F85K22).  2009-2018 Microchip Technology Inc. DS30009960F-page 399

PIC18F87K22 FAMILY REGISTER 28-7: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 R/P-0 U-0 U-0 U-0 R/P-1 DEBUG — — BBSIZ0 — — — STVREN bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled, RB6 and RB7 are configured as general purpose I/O pins 0 = Background debugger is enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6-5 Unimplemented: Read as ‘0’ bit 4 BBSIZ0: Boot Block Size Select bit 1 = 2 kW boot block size 0 = 1 kW boot block size bit 3-1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset DS30009960F-page 400  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 28-8: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 CP7(1) CP6(1) CP5(1) CP4(1) CP3 CP2 CP1 CP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CP7: Code Protection bit(1) 1 = Block 7 is not code-protected(2) 0 = Block 7 is code-protected(2) bit 6 CP6: Code Protection bit(1) 1 = Block 6 is not code-protected(2) 0 = Block 6 is code-protected(2) bit 5 CP5: Code Protection bit(1) 1 = Block 5 is not code-protected(2) 0 = Block 5 is code-protected(2) bit 4 CP4: Code Protection bit(1) 1 = Block 4 is not code-protected(2) 0 = Block 4 is code-protected(2) bit 3 CP3: Code Protection bit 1 = Block 3 is not code-protected(2) 0 = Block 3 is code-protected(2) bit 2 CP2: Code Protection bit 1 = Block 2 is not code-protected(2) 0 = Block 2 is code-protected(2) bit 1 CP1: Code Protection bit 1 = Block 1 is not code-protected(2) 0 = Block 1 is code-protected(2) bit 0 CP0: Code Protection bit 1 = Block 0 is not code-protected(2) 0 = Block 0 is code-protected(2) Note 1: This bit is available only on PIC18F67K22 and PIC18F87K22 devices. 2: For the memory size of the blocks, see Figure28-6.  2009-2018 Microchip Technology Inc. DS30009960F-page 401

PIC18F87K22 FAMILY REGISTER 28-9: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot block is not code-protected(1) 0 = Boot block is code-protected(1) bit 5-0 Unimplemented: Read as ‘0’ Note 1: For the memory size of the blocks, see Figure28-6. The boot block size changes with BBSIZ0. DS30009960F-page 402  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 28-10: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 WRT7(1) WRT6(1) WRT5(1) WRT4(1) WRT3 WRT2 WRT1 WRT0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WRT7: Write Protection bit(1) 1 = Block 7 is not write-protected(2) 0 = Block 7 is write-protected(2) bit 6 WRT6: Write Protection bit(1) 1 = Block 6 is not write-protected(2) 0 = Block 6 is write-protected(2) bit 5 WRT5: Write Protection bit(1) 1 = Block 5 is not write-protected(2) 0 = Block 5 is write-protected(2) bit 4 WRT4: Write Protection bit(1) 1 = Block 4 is not write-protected(2) 0 = Block 4 is write-protected(2) bit 3 WRT3: Write Protection bit 1 = Block 3 is not write-protected(2) 0 = Block 3 is write-protected(2) bit 2 WRT2: Write Protection bit 1 = Block 2 is not write-protected(2) 0 = Block 2 is write-protected(2) bit 1 WRT1: Write Protection bit 1 = Block 1 is not write-protected(2) 0 = Block 1 is write-protected(2) bit 0 WRT0: Write Protection bit 1 = Block 0 is not write-protected(2) 0 = Block 0 is write-protected(2) Note 1: This bit is available only on PIC18F67K22 and PIC18F87K22 devices. 2: For the memory size of the blocks, see Figure28-6.  2009-2018 Microchip Technology Inc. DS30009960F-page 403

PIC18F87K22 FAMILY REGISTER 28-11: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot block is not write-protected(2) 0 = Boot block is write-protected(2) bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers are not write-protected(2) 0 = Configuration registers are write-protected(2) bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is read-only in normal Execution mode; it can be written only in Program mode. 2: For the memory size of the blocks, see Figure28-6. DS30009960F-page 404  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 28-12: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 EBTR7(1,3) EBTR6(1,3) EBTR5(1,3) EBTR4(1,3) EBTR3(3) EBTR2(3) EBTR1(3) EBTR0(3) bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EBTR7: Table Read Protection bit(1,3) 1 = Block 7 is not protected from table reads executed in other blocks(2) 0 = Block 7 is protected from table reads executed in other blocks(2) bit 6 EBTR6: Table Read Protection bit(1,3) 1 = Block 6 is not protected from table reads executed in other blocks(2) 0 = Block 6 is protected from table reads executed in other blocks(2) bit 5 EBTR5: Table Read Protection bit(1,3) 1 = Block 5 is not protected from table reads executed in other blocks(2) 0 = Block 5 is protected from table reads executed in other blocks(2) bit 4 EBTR4: Table Read Protection bit(1,3) 1 = Block 4 is not protected from table reads executed in other blocks(2) 0 = Block 4 is protected from table reads executed in other blocks(2) bit 3 EBTR3: Table Read Protection bit(3) 1 = Block 3 is not protected from table reads executed in other blocks(2) 0 = Block 3 is protected from table reads executed in other blocks(2) bit 2 EBTR2: Table Read Protection bit(3) 1 = Block 2 is not protected from table reads executed in other blocks(2) 0 = Block 2 is protected from table reads executed in other blocks(2) bit 1 EBTR1: Table Read Protection bit(3) 1 = Block 1 is not protected from table reads executed in other blocks(2) 0 = Block 1 is protected from table reads executed in other blocks(2) bit 0 EBTR0: Table Read Protection bit(3) 1 = Block 0 is not protected from table reads executed in other blocks(2) 0 = Block 0 is protected from table reads executed in other blocks(2) Note 1: This bit is available only on PIC18F67K22 and PIC18F87K22 devices. 2: For the memory size of the blocks, see Figure28-6 3: Enable the corresponding CPx bit to protect the block from external read operations.  2009-2018 Microchip Technology Inc. DS30009960F-page 405

PIC18F87K22 FAMILY REGISTER 28-13: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB(2) — — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit(2) 1 = Boot block is not protected from table reads executed in other blocks(1) 0 = Boot block is protected from table reads executed in other blocks(1) bit 5-0 Unimplemented: Read as ‘0’ Note 1: For the memory size of the blocks, see Figure28-6. 2: Enable the corresponding CPx bit to protect the block from external read operations. DS30009960F-page 406  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY REGISTER 28-14: DEVID1: DEVICE ID REGISTER 1 FOR THE PIC18F87K22 FAMILY R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 DEV<2:0>: Device ID bits Devices with DEV<10:3> of ‘0101 0010’ (see DEVID2): 010 = PIC18F65K22 000 = PIC18F66K22 101 = PIC18F85K22 011 = PIC18F86K22 Devices with DEV<10:3> of ‘0101 0001’: 000 = PIC18F67K22 010 = PIC18F87K22 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. REGISTER 28-15: DEVID2: DEVICE ID REGISTER 2 FOR THE PIC18F87K22 FAMILY R R R R R R R R DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 DEV<10:3>: Device ID bits(1) These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. 0101 0010 = PIC18F65K22, PIC18F66K22, PIC18F85K22 and PIC18F86K22 0101 0001 = PIC18F67K22 and PIC18F87K22 Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified by using the entire DEV<10:0> bit sequence.  2009-2018 Microchip Technology Inc. DS30009960F-page 407

PIC18F87K22 FAMILY 28.2 Watchdog Timer (WDT) The WDT can be operated in one of four modes as determined by the WDTEN<1:0> (CONFIG2H<1:0> For the PIC18F87K22 family of devices, the WDT is bits. The four modes are: driven by the LF-INTOSC source. When the WDT is • WDT Enabled enabled, the clock source is also enabled. The nominal WDT period is 4ms and has the same stability as the • WDT Disabled LF-INTOSC oscillator. • WDT under Software Control, SWDTEN (WDTCON<0>) The 4ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is • WDT selected by a multiplexer, controlled by bits in - Enabled during normal operation Configuration Register 2H. Available periods range - Disabled during Sleep from 4ms to 4,194seconds (about one hour). The Note1: The CLRWDT and SLEEP instructions WDT and postscaler are cleared when any of the clear the WDT and postscaler counts following events occur: a SLEEP or CLRWDT instruction when executed. is executed, the IRCF bits (OSCCON<6:4>) are changed or a clock failure has occurred. 2: Changing the setting of the IRCF bits (OSCCON<6:4>) clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared. FIGURE 28-1: WDT BLOCK DIAGRAM WDT Enabled, SWDTEN Disabled WDT Controlled with SWDTEN bit Setting WDT Enabled only while Device is Active, Disabled WDT Disabled in Hardware, SWDTEN Disabled WDTEN1 Enable WDT Wake-up from WDTEN0 WDT Counter Power-Managed Modes INTRC Source 128 Change on IRCF bits Programmable Postscaler Reset WDT CLRWDT Reset 1:1 to 1:1,048,576 All Device Resets 4 WDTPS<3:0> Sleep SWDTEN Enable WDT WDTEN<1:0> INTRC Source DS30009960F-page 408  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 28.2.1 CONTROL REGISTER Register28-16 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT Enable Configuration bit, but only if the Configuration bit has disabled the WDT. REGISTER 28-16: WDTCON: WATCHDOG TIMER CONTROL REGISTER R/W-0 U-0 R-x R/W-0 U-0 R/W-0 R/W-0 R/W-0 REGSLP — ULPLVL SRETEN(2) — ULPEN ULPSINK SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 REGSLP: Regulator Voltage Sleep Enable bit 1 = Regulator goes into Low-Power mode when device’s Sleep mode is enabled 0 = Regulator stays in normal Operation mode when device’s Sleep mode is activated bit 6 Unimplemented: Read as ‘0’ bit 5 ULPLVL: Ultra Low-Power Wake-up Output bit Not valid unless ULPEN = 1. 1 = Voltage on RA0 pin > ~ 0.5V 0 = Voltage on RA0 pin < ~ 0.5V. bit 4 SRETEN: Regulator Voltage Sleep Disable bit(2) 1 = If RETEN (CONFIG1L<0>) = 0 and the regulator is enabled, the device goes into Ultra Low-Power mode in Sleep 0 = The regulator is on when the device’s Sleep mode is enabled and the Low-Power mode is controlled by REGSLP bit 3 Unimplemented: Read as ‘0’ bit 2 ULPEN: Ultra Low-Power Wake-up Module Enable bit 1 = Ultra Low-Power Wake-up module is enabled; ULPLVL bit indicates the comparator output 0 = Ultra Low-Power Wake-up module is disabled bit 1 ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit Not valid unless ULPEN = 1. 1 = Ultra Low-Power Wake-up current sink is enabled 0 = Ultra Low-Power Wake-up current sink is disabled bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bits, WDTEN<1:0>, are enabled. 2: This bit is available only when ENVREG = 1 and RETEN = 0. TABLE 28-2: SUMMARY OF WATCHDOG TIMER REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCON IPEN SBOREN CM RI TO PD POR BOR WDTCON REGSLP — ULPLVL SRETEN — ULPEN ULPSINK SWDTEN Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.  2009-2018 Microchip Technology Inc. DS30009960F-page 409

PIC18F87K22 FAMILY 28.3 On-Chip Voltage Regulator FIGURE 28-2: CONNECTIONS FOR THE ON-CHIP REGULATOR All of the PIC18F87K22 family devices power their core digital logic at a nominal 3.3V. For designs that are Regulator Enabled (ENVREG tied to VDD): required to operate at a higher typical voltage, such as 5V 5V, all family devices incorporate two on-chip regula- PIC18F87K22 tors that allow the device to run its core logic from VDD. Those regulators are: VDD ENVREG • Normal On-Chip Regulator • Ultra Low-Power On-Chip Regulator VDDCORE/VCAP The hardware configuration of these regulators is the CF VSS same and is explained in Section28.3.1 “Regulator Enable/Disable By Hardware”. The regulators’ only differences relate to when the device enters Sleep, as explained in Section28.3.2 “Operation of Regulator in Sleep”. Regulator Disabled (ENVREG tied to VSS): 28.3.1 REGULATOR ENABLE/DISABLE BY 3.3V(1) HARDWARE PIC18F87K22 The regulator can be enabled or disabled only by hard- VDD ware. The regulator is controlled by the ENVREG pin ENVREG and the VDDCORE/VCAP pin. 0.1µF VDDCORE/VCAP 28.3.1.1 Regulator Enable Mode Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. VSS When the regulator is enabled, a low-ESR filter capac- itor must be connected to the VDDCORE/VCAP pin (see Figure28-2). This helps maintain the regulator’s Note 1: These are typical operating voltages. For the stability. The recommended value for the filter capacitor full operating ranges of VDD and VDDCORE, see Section31.2 “DC Characteristics: is given in Section31.2 “DC Characteristics: Power- Power-Down and Supply Current Down and Supply Current PIC18F87K22 Family PIC18F87K22 Family (Industrial/ (Industrial/Extended)”. Extended)”. 28.3.1.2 Regulator Disable Mode If the regulator is disabled by connecting VSS to the ENVREG pin, the power to the core is supplied directly by VDD. The voltage levels for VDD must not exceed the specified VDDCORE levels. In Regulator Disabled mode, a 0.1 µF capacitor should be connected to the VDDCORE/VCAP pin (see Figure28-2). When the regulator is being used, the overall voltage budget is very tight. The regulator should operate the device down to 1.8V. When VDD drops below 3.3V, the regulator no longer regulates, but the output voltage follows the input until VDD reaches 1.8V. Below this voltage, the output of the regulator output may drop to 0V. DS30009960F-page 410  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 28.3.2 OPERATION OF REGULATOR IN The various modes of regulator operation are shown in SLEEP Table28-3. The difference in the two regulators’ operation arises When the ultra low-power regulator is in Sleep mode, with Sleep mode. The ultra low-power regulator gives the internal reference voltages in the chip will be shut the device the lowest current in the Regulator Enabled off and any interrupts referring to the internal reference mode. will not wake up the device. If the BOR or LVD is enabled, the regulator will keep the internal references The on-chip regulator can go into a lower power mode, on and the lowest possible current will not be achieved. when the device goes to Sleep, by setting the REGSLP bit (WDTCON<7>). This puts the regulator in a Standby When using the ultra low-power regulator in Sleep mode so that the device consumes much less current. mode, the device will take about 250s, typical, to start executing the code after it wakes up. The on-chip regulator can also go into the Ultra Low- Power mode, which consumes the lowest current possible with the regulator enabled. This mode is controlled by the RETEN bit (CONFIG1L<0>) and SRETEN bit (WDTCON<4>). TABLE 28-3: SLEEP MODE REGULATOR SETTINGS(1) VREGSLP SRETEN RETEN Regulator Power Mode WDTCON<7> WDTCON<4> CONFIG1L<0> Enabled Normal Operation (Sleep) 0 x 1 Enabled Low-Power mode (Sleep) 1 x 1 Enabled Normal Operation (Sleep) 0 0 x Enabled Low-Power mode (Sleep) 1 0 x Enabled Ultra Low-Power mode (Sleep) x 1 0 Note 1: x = Indicates that VIT status is invalid.  2009-2018 Microchip Technology Inc. DS30009960F-page 411

PIC18F87K22 FAMILY 28.4 Two-Speed Start-up In all other power-managed modes, Two-Speed Start- up is not used. The device will be clocked by the The Two-Speed Start-up feature helps to minimize the currently selected clock source until the primary clock latency period, from oscillator start-up to code execution, source becomes available. The setting of the IESO bit by allowing the microcontroller to use the INTOSC is ignored. (LF-INTOSC, MF-INTOSC, HF-INTOSC) oscillator as a clock source until the primary clock source is available; 28.4.1 SPECIAL CONSIDERATIONS FOR it is enabled by setting the IESO Configuration bit. USING TWO-SPEED START-UP Two-Speed Start-up should be enabled only if the While using the INTOSC oscillator in Two-Speed Start- primary oscillator mode is LP, XT or HS (Crystal-Based up, the device still obeys the normal command modes). Other sources do not require an OST start-up sequences for entering power-managed modes, delay; for these, Two-Speed Start-up should be including multiple SLEEP instructions (refer to disabled. Section4.1.4 “Multiple Sleep Commands”). In When enabled, Resets and wake-ups from Sleep mode practice, this means that user code can change the cause the device to configure itself to run from the SCS<1:0> bit settings or issue SLEEP instructions internal oscillator block as the clock source, following before the OST times out. This would allow an the time-out of the Power-up Timer after a Power-on application to briefly wake up, perform routine Reset is enabled. This allows almost immediate code “housekeeping” tasks and return to Sleep before the execution while the primary oscillator starts and the device starts to operate from the primary oscillator. OST is running. Once the OST times out, the device User code can also check if the primary clock source is automatically switches to PRI_RUN mode. currently providing the device clocking by checking the To use a higher clock speed on wake-up, the INTOSC status of the OSTS bit (OSCCON<3>). If the bit is set, or postscaler clock sources can be selected to provide the primary oscillator is providing the clock. Otherwise, a higher clock speed by setting bits, IRCF<2:0>, the internal oscillator block is providing the clock during immediately after Reset. For wake-ups from Sleep, the wake-up from Reset or Sleep mode. INTOSC or postscaler clock sources can be selected by setting the IRCF<2:0> bits prior to entering Sleep mode. FIGURE 28-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 PC + 6 Wake from Interrupt Event OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS30009960F-page 412  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 28.5 Fail-Safe Clock Monitor To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide The Fail-Safe Clock Monitor (FSCM) allows the a higher clock speed by setting bits, IRCF<2:0>, microcontroller to continue operation in the event of an immediately after Reset. For wake-ups from Sleep, the external oscillator failure by automatically switching the INTOSC or postscaler clock sources can be selected device clock to the internal oscillator block. The FSCM by setting the IRCF<2:0> bits prior to entering Sleep function is enabled by setting the FCMEN mode. Configuration bit. The FSCM will detect only failures of the primary or When FSCM is enabled, the LF-INTOSC oscillator runs secondary clock sources. If the internal oscillator block at all times to monitor clocks to peripherals and provide fails, no failure would be detected nor would any action a backup clock in the event of a clock failure. Clock be possible. monitoring (shown in Figure28-4) is accomplished by creating a sample clock signal, which is the output from 28.5.1 FSCM AND THE WATCHDOG TIMER the LF-INTOSC, divided by 64. This allows ample time Both the FSCM and the WDT are clocked by the between FSCM sample clocks for a peripheral clock INTOSC oscillator. Since the WDT operates with a edge to occur. The peripheral device clock and the separate divider and counter, disabling the WDT has sample clock are presented as inputs to the Clock no effect on the operation of the INTOSC oscillator Monitor (CM) latch. The CM is set on the falling edge of when the FSCM is enabled. the device clock source, but cleared on the rising edge of the sample clock. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. FIGURE 28-4: FSCM BLOCK DIAGRAM Depending on the frequency selected by the IRCF<2:0> bits, this may mean a substantial change in Clock Monitor the speed of code execution. If the WDT is enabled Latch (CM) (edge-triggered) with a small prescale value, a decrease in clock speed Peripheral allows a WDT time-out to occur and a subsequent S Q Clock device Reset. For this reason, Fail-Safe Clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed, and INTRC decreasing the likelihood of an erroneous time-out. ÷ 64 C Q Source 28.5.2 EXITING FAIL-SAFE OPERATION (32 s) 488 Hz (2.048 ms) The Fail-Safe condition is terminated by either a device Reset or by entering a power-managed mode. On Clock Reset, the controller starts the primary clock source Failure specified in Configuration Register 1H (with any Detected required start-up delays that are required for the Oscillator mode, such as the OST or PLL timer). The Clock failure is tested for on the falling edge of the INTOSC multiplexer provides the device clock until the sample clock. If a sample clock falling edge occurs primary clock source becomes ready (similar to a Two- while CM is still set, a clock failure has been detected Speed Start-up). The clock source is then switched to (Figure28-5). This causes the following: the primary clock (indicated by the OSTS bit in the • The FSCM generates an oscillator fail interrupt by OSCCON register becoming set). The Fail-Safe Clock setting bit, OSCFIF (PIR2<7>) Monitor then resumes monitoring the peripheral clock. • The device clock source switches to the internal The primary clock source may never become ready oscillator block (OSCCON is not updated to show during start-up. In this case, operation is clocked by the the current clock source – this is the Fail-Safe INTOSC multiplexer. The OSCCON register will remain condition) in its Reset state until a power-managed mode is • The WDT is reset entered. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing-sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shut- down. See Section4.1.4 “Multiple Sleep Commands” and Section28.4.1 “Special Considerations for Using Two-Speed Start-up” for more details.  2009-2018 Microchip Technology Inc. DS30009960F-page 413

PIC18F87K22 FAMILY FIGURE 28-5: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 28.5.3 FSCM INTERRUPTS IN For Oscillator modes involving a crystal or resonator POWER-MANAGED MODES (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up By entering a power-managed mode, the clock time considerably longer than the FCSM sample clock multiplexer selects the clock source selected by the time, a false clock failure may be detected. To prevent OSCCON register. Fail-Safe Clock Monitoring of this, the internal oscillator block is automatically config- the power-managed clock source resumes in the ured as the device clock and functions until the primary power-managed mode. clock is stable (when the OST and PLL timers have If an oscillator failure occurs during power-managed timed out). operation, the subsequent events depend on whether This is identical to Two-Speed Start-up mode. Once the or not the Oscillator Failure Interrupt Flag bit is enabled primary clock is stable, the INTOSC returns to its role (OSCFIF=1). If enabled, code execution will be as the FSCM source. clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. Note: The same logic that prevents false oscilla- tor failure interrupts on POR, or wake from If the interrupt is disabled, subsequent interrupts while Sleep, also prevents the detection of the in Idle mode will cause the CPU to begin executing oscillator’s failure to start at all following instructions while being clocked by the INTOSC these events. This can be avoided by source. monitoring the OSTS bit and using a 28.5.4 POR OR WAKE FROM SLEEP timing routine to determine if the oscillator is taking too long to start. Even so, no The FSCM is designed to detect oscillator failure at any oscillator failure interrupt will be flagged. point after the device has exited Power-on Reset (POR) or low-power Sleep mode. When the primary As noted in Section28.4.1 “Special Considerations device clock is EC, RC or INTRC modes, monitoring for Using Two-Speed Start-up”, it is also possible to can begin immediately following these events. select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power- managed mode is selected, the primary clock is disabled. DS30009960F-page 414  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 28.6 Program Verification and Each of the blocks has three code protection bits Code Protection associated with them. They are: • Code-Protect bit (CPx) The user program memory is divided into four blocks • Write-Protect bit (WRTx) for the PIC18FX5K22 and PIC18FX6K22 devices, and • External Block Table Read bit (EBTRx) eight blocks for PIC18FX7K22 devices. One of these is a boot block of 1 or 2Kbytes. The remainder of the Figure28-6 shows the program memory organization for memory is divided into blocks on binary boundaries. 48, 64, 96 and 128 Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table28-4. FIGURE 28-6: CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F87K22 FAMILY(1) 000000h Code Memory 01FFFFh Device/Memory Size(2) PIC18FX7K22 PIC18FX6K22 PIC18FX5K22 BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 Address Boot Boot Boot Boot Boot Boot 0000h Unimplemented Block Block Block Block Block Block Read as ‘0’ 2kW 2kW Block 0 2kW Block 0 0800h 7kW 3kW Block 0 Block 0 1000h Block 0 Block 0 7kW 6kW 2kW 17FFh 6kW Block 1 Block 1 1800 4kW 4kW 3FFF Block 1 Block 1 Block 2 Block 2 4000h Block 1 Block 1 8kW 8kW 4kW 4kW 5FFFh 8kW 8kW Block 3 Block 3 6000h 200000h 4kW 4kW 7FFF Block 2 Block 2 Block 2 Block 2 8000h 8kW 8kW 8kW 8kW BFFFh Block 3 Block 3 Block 3 Block 3 C000h 8kW 8kW 8kW 8kW FFFFh Configuration Block 4 Block 4 10000h and ID 8kW 8kW 13FFFh Space Block 5 Block 5 14000h 8kW 8kW 17FFFh Block 6 Block 6 18000h 8kW 8kW 1BFFFh Block 7 Block 7 1C000h 8kW 8kW 1FFFFh 3FFFFFh Note 1: Sizes of memory areas are not to scale. 2: Boot block size is determined by the BBSIZ0 bit (CONFIG4L<4>).  2009-2018 Microchip Technology Inc. DS30009960F-page 415

PIC18F87K22 FAMILY TABLE 28-4: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L CP7(1) CP6(1) CP5(1) CP4(1) CP3 CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L WRT7(1) WRT6(1) WRT5(1) WRT4(1) WRT3 WRT2 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L EBTR7(1) EBTR6(1) EBTR5(1) EBTR4(1) EBTR3 EBTR2 EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. Note 1: This bit is available only on the PIC18F67K22 and PIC18F87K22 devices. 28.6.1 PROGRAM MEMORY to read. A table read instruction that executes from a CODE PROTECTION location outside of that block is not allowed to read and will result in reading ‘0’s. Figures28-7 through28-9 The program memory may be read to, or written from, illustrate table write and table read protection. any location using the table read and table write instructions. The Device ID may be read with table Note: Code protection bits may only be written reads. The Configuration registers may be read and to a ‘0’ from a ‘1’ state. It is not possible to written with the table read and table write instructions. write a ‘1’ to a bit in the ‘0’ state. Code protection bits are only set to ‘1’ by a full In normal Execution mode, the CPx bits have no direct chip erase or block erase function. The full effect. CPx bits inhibit external reads and writes. A block chip erase and block erase functions can of user memory may be protected from table writes if the only be initiated via ICSP or an external WRTx Configuration bit is ‘0’. programmer. Refer to the device The EBTRx bits control table reads. For a block of user programming specification for more memory, with the EBTRx bit set to ‘0’, a table read information. instruction that executes from within that block is allowed FIGURE 28-7: TABLE WRITE (WRTx) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 01 PC = 003FFEh TBLWT* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h PC = 00BFFEh TBLWT* WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table writes are disabled to Blockn whenever WRTx = 0. DS30009960F-page 416  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 28-8: EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 003FFFh 004000h PC = 007FFEh TBLRD* WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0. The TABLAT register returns a value of ‘0’. FIGURE 28-9: EXTERNAL BLOCK TABLE READ (EBTRx) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 PC = 003FFEh TBLRD* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: Table reads are permitted within Blockn, even when EBTRBx = 0. The TABLAT register returns the value of the data at the location, TBLPTR.  2009-2018 Microchip Technology Inc. DS30009960F-page 417

PIC18F87K22 FAMILY 28.6.2 DATA EEPROM 28.8 In-Circuit Serial Programming CODE PROTECTION The PIC18F87K22 family of devices can be serially The entire data EEPROM is protected from external programmed while in the end application circuit. This is reads and writes by two bits: CPD and WRTD. CPD simply done with two lines for clock and data, and three inhibits external reads and writes of data EEPROM. other lines for power, ground and the programming WRTD inhibits internal and external writes to data voltage. This allows customers to manufacture boards EEPROM. The CPU can always read data EEPROM with unprogrammed devices and then program the under normal operation, regardless of the protection bit microcontroller just before shipping the product. This settings. also allows the most recent firmware or a custom firmware to be programmed. 28.6.3 CONFIGURATION REGISTER For the various Programming modes, see the device PROTECTION programming specification. The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration 28.9 In-Circuit Debugger registers. In normal Execution mode, the WRTC bit is When the DEBUG Configuration bit is programmed to readable only. WRTC can only be written via ICSP or a ‘0’, the In-Circuit Debugger (ICD) functionality is an external programmer. enabled. This function allows simple debugging 28.7 ID Locations functions when used with MPLAB® IDE. When the microcontroller has this feature enabled, some Eight memory locations (200000h-200007h) are resources are not available for general use. Table28-5 designated as ID locations, where the user can store shows which resources are required by the background checksum or other code identification numbers. These debugger. locations are both readable and writable, during normal execution, through the TBLRD and TBLWT instructions TABLE 28-5: DEBUGGER RESOURCES or during program/verify. The ID locations can be read I/O Pins: RB6, RB7 when the device is code-protected. Stack: Two levels Program Memory: 512 bytes Data Memory: 10 bytes To use the In-Circuit Debugger function of the micro- controller, the design must implement In-Circuit Serial Programming connections to MCLR/RG5/VPP, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module, available from Microchip or one of the third-party development tool companies. DS30009960F-page 418  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 29.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: The PIC18F87K22 family of devices incorporates the • A literal value to be loaded into a file register standard set of 75 PIC18 core instructions, as well as (specified by ‘k’) an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software • The desired FSR register to load the literal value stack. The extended set is discussed later in this into (specified by ‘f’) section. • No operand required (specified by ‘—’) 29.1 Standard Instruction Set The control instructions may use some of the following operands: The standard PIC18 MCU instruction set adds many enhancements to the previous PIC® MCU instruction • A program memory address (specified by ‘n’) sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions PIC MCU instruction sets. Most instructions are a (specified by ‘s’) single program memory word (16 bits), but there are • The mode of the table read and table write four instructions that require two program memory instructions (specified by ‘m’) locations. • No operand required Each single-word instruction is a 16-bit word divided (specified by ‘—’) into an opcode, which specifies the instruction type and All instructions are a single word, except for four one or more operands, which further specify the double-word instructions. These instructions were operation of the instruction. made double-word to contain the required information The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If into four basic categories: this second word is executed as an instruction (by itself), it will execute as a NOP. • Byte-oriented operations • Bit-oriented operations All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the • Literal operations Program Counter is changed as a result of the instruc- • Control operations tion. In these cases, the execution takes two instruction The PIC18 instruction set summary in Table29-2 lists cycles with the additional instruction cycle(s) executed byte-oriented, bit-oriented, literal and control as a NOP. operations. Table29-1 shows the opcode field The double-word instructions execute in two instruction descriptions. cycles. Most byte-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. 1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4MHz, the normal 2. The destination of the result (specified by ‘d’) instruction execution time is 1s. If a conditional test is 3. The accessed memory (specified by ‘a’) true, or the Program Counter is changed as a result of an instruction, the instruction execution time is 2 s. The file register designator, ‘f’, specifies which file reg- Two-word branch instructions (if true) would take 3 s. ister is to be used by the instruction. The destination designator, ‘d’, specifies where the result of the Figure29-1 shows the general formats that the instruc- operation is to be placed. If ‘d’ is zero, the result is tions can have. All examples use the convention ‘nnh’ placed in the WREG register. If ‘d’ is one, the result is to represent a hexadecimal number. placed in the file register specified in the instruction. The Instruction Set Summary, shown in Table29-2, All bit-oriented instructions have three operands: lists the standard instructions recognized by the Microchip MPASMTM Assembler. 1. The file register (specified by ‘f’) Section29.1.1 “Standard Instruction Set” provides 2. The bit in the file register (specified by ‘b’) a description of each instruction. 3. The accessed memory (specified by ‘a’) The bit field designator, ‘b’, selects the number of the bit affected by the operation, while the file register desig- nator, ‘f’, represents the number of the file in which the bit is located.  2009-2018 Microchip Technology Inc. DS30009960F-page 419

PIC18F87K22 FAMILY TABLE 29-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h). f 12-bit register file address (000h to FFFh). This is the source address. s f 12-bit register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No Change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-Down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or Unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for Indirect Addressing of register files (source). s z 7-bit offset value for Indirect Addressing of register files (destination). d { } Optional argument. [text] Indicates an Indexed Address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr.  Assigned to. < > Register bit field.  In the set of. italics User-defined term (font is Courier New). DS30009960F-page 420  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC  2009-2018 Microchip Technology Inc. DS30009960F-page 421

PIC18F87K22 FAMILY TABLE 29-2: PIC18F87K22 FAMILY INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1, 2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS30009960F-page 422  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 29-2: PIC18F87K22 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.  2009-2018 Microchip Technology Inc. DS30009960F-page 423

PIC18F87K22 FAMILY TABLE 29-2: PIC18F87K22 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY  PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS30009960F-page 424  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 29.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) + k  W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f)  dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. Q Cycle Activity: If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data W set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: ADDLW 15h Section29.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = 10h Literal Offset Mode” for details. After Instruction Words: 1 W = 25h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).  2009-2018 Microchip Technology Inc. DS30009960F-page 425

PIC18F87K22 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0  f  255 Operands: 0  k  255 d [0,1] Operation: (W) .AND. k  W a [0,1] Status Affected: N, Z Operation: (W) + (f) + (C)  dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read literal Process Write to GPR bank. ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: ANDLW 05Fh in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Before Instruction W = A3h Section29.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. W = 03h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS30009960F-page 426  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0  f  255 Operands: -128  n  127 d [0,1] Operation: if Carry bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: (W) .AND. (f)  dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ’1’, then the program Description: The contents of W are ANDed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’. incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a GPR bank. two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates Cycles: 1(2) in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Q Cycle Activity: Section29.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to Words: 1 ‘n’ Data PC No No No No Cycles: 1 operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If Carry = 1; W = 02h PC = address (HERE + 12) REG = C2h If Carry = 0; PC = address (HERE + 2)  2009-2018 Microchip Technology Inc. DS30009960F-page 427

PIC18F87K22 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0  f  255 Operands: -128  n  127 0  b  7 Operation: if Negative bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: 0  f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank. incremented to fetch the next instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Words: 1 Section29.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to Q Cycle Activity: ‘n’ Data PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No ‘n’ Data operation Before Instruction FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS30009960F-page 428  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128  n  127 Operands: -128  n  127 Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’, (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2)  2009-2018 Microchip Technology Inc. DS30009960F-page 429

PIC18F87K22 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128  n  127 Operands: -128  n  127 Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’, (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS30009960F-page 430  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024  n  1023 Operands: 0  f  255 0  b  7 Operation: (PC) + 2 + 2n  PC a [0,1] Status Affected: None Operation: 1  f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected. PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the two-cycle instruction. GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section29.2.3 “Byte-Oriented and Decode Read literal Process Write to Bit-Oriented Instructions in Indexed ‘n’ Data PC Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah  2009-2018 Microchip Technology Inc. DS30009960F-page 431

PIC18F87K22 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0  f  255 Operands: 0  f  255 0  b  7 0  b < 7 a [0,1] a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction set If ‘a’ is ‘0’ and the extended instruction is enabled, this instruction operates in set is enabled, this instruction operates in Indexed Literal Offset Addressing mode Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS30009960F-page 432  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0  f  255 Operands: -128  n  127 0  b < 7 Operation: if Overflow bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: (f<b>)  f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location, ‘f’, is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank. instruction, the new address will be PC + 2 + 2n. This instruction is then a If ‘a’ is ‘0’ and the extended instruction two-cycle instruction. set is enabled, this instruction operates in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Cycles: 1(2) Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Q1 Q2 Q3 Q4 Words: 1 Decode Read literal Process Write to PC Cycles: 1 ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: Before Instruction PORTC = 0110 0101 [65h] PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2)  2009-2018 Microchip Technology Inc. DS30009960F-page 433

PIC18F87K22 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128  n  127 Operands: 0  k  1048575 s [0,1] Operation: if Zero bit is ‘1’, (PC) + 2 + 2n  PC Operation: (PC) + 4  TOS, k  PC<20:1>; Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (W)  WS, Description: If the Zero bit is ‘1’, then the program (STATUS)  STATUSS, will branch. (BSR)  BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will have Encoding: incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk 7 0 instruction, the new address will be 2nd word(k<19:8>) 1111 k kkk kkkk kkkk 19 8 PC + 2 + 2n. This instruction is then a Description: Subroutine call of entire 2-Mbyte two-cycle instruction. memory range. First, return address Words: 1 (PC+ 4) is pushed onto the return stack. Cycles: 1(2) If ‘s’ = 1, the W, STATUS and BSR registers are also pushed into their Q Cycle Activity: respective shadow registers, WS, If Jump: STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs. Then, the 20-bit value ‘k’ Decode Read literal Process Write to is loaded into PC<20:1>. CALL is a ‘n’ Data PC two-cycle instruction. No No No No Words: 2 operation operation operation operation Cycles: 2 If No Jump: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No ‘n’ Data operation Decode Read literal Push PC to Read literal ‘k’<7:0>, stack ’k’<19:8>, Write to PC Example: HERE BZ Jump No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction Example: HERE CALL THERE,1 If Zero = 1; PC = address (Jump) Before Instruction If Zero = 0; PC = address (HERE) PC = address (HERE + 2) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS30009960F-page 434  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0  f  255 Operands: None a [0,1] Operation: 000h  WDT, Operation: 000h  f, 000h  WDT postscaler, 1  Z 1  TO, 1  PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the Watchdog Timer. It also resets the post- If ‘a’ is ‘0’, the Access Bank is selected. scaler of the WDT. Status bits, TO and If ‘a’ is ‘1’, the BSR is used to select the PD, are set. GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Cycles: 1 in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Decode No Process No Literal Offset Mode” for details. operation Data operation Words: 1 Example: CLRWDT Cycles: 1 Before Instruction Q Cycle Activity: WDT Counter = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write WDT Counter = 00h register ‘f’ Data register ‘f’ WDT Postscaler = 0 TO = 1 PD = 1 Example: CLRF FLAG_REG,1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h  2009-2018 Microchip Technology Inc. DS30009960F-page 435

PIC18F87K22 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: f  dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’. If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank. instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank. mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Words: 1 Section29.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Cycles: 1(2) register ‘f’ Data destination Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h W = ECh Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG  W; PC = Address (NEQUAL) DS30009960F-page 436  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0  f  255 Operands: 0  f  255 a  [0,1] a  [0,1] Operation: (f) –W), Operation: (f) –W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of the W by Description: Compares the contents of data memory performing an unsigned subtraction. location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are greater than the contents of WREG, then the fetched If the contents of ‘f’ are less than the instruction is discarded and a NOP is contents of W, then the fetched executed instead, making this a instruction is discarded and a NOP is two-cycle instruction. executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Note: 3 cycles if skip and followed Section29.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 Words: 1 Decode Read Process No Cycles: 1(2) register ‘f’ Data operation Note: 3 cycles if skip and followed If skip: by a 2-word instruction. Q1 Q2 Q3 Q4 Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process No If skip and followed by 2-word instruction: register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; PC = Address (LESS) Before Instruction If REG  W; PC = Address (HERE) PC = Address (NLESS) W = ? After Instruction If REG  W; PC = Address (GREATER) If REG  W; PC = Address (NGREATER)  2009-2018 Microchip Technology Inc. DS30009960F-page 437

PIC18F87K22 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0  f  255 d  [0,1] Operation: If [W<3:0> > 9] or [DC = 1], then a  [0,1] (W<3:0>) + 6  W<3:0>; else Operation: (f) – 1  dest (W<3:0>)  W<3:0> Status Affected: C, DC, N, OV, Z If [W<7:4> > 9] or [C = 1], then Encoding: 0000 01da ffff ffff (W<7:4>) + 6  W<7:4>; Description: Decrement register, ‘f’. If ‘d’ is ‘0’, the C =1; result is stored in W. If ‘d’ is ‘1’, the else result is stored back in register ‘f’. (W<7:4>)  W<7:4> If ‘a’ is ‘0’, the Access Bank is selected. Status Affected: C If ‘a’ is ‘1’, the BSR is used to select the Encoding: 0000 0000 0000 0111 GPR bank. Description: DAW adjusts the 8-bit value in W, If ‘a’ is ‘0’ and the extended instruction resulting from the earlier addition of two set is enabled, this instruction operates variables (each in packed BCD format) in Indexed Literal Offset Addressing and produces a correct packed BCD mode whenever f 95 (5Fh). See result. Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Words: 1 Literal Offset Mode” for details. Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write Q1 Q2 Q3 Q4 register W Data W Decode Read Process Write to register ‘f’ Data destination Example 1: DAW Before Instruction W = A5h Example: DECF CNT, 1, 0 C = 0 Before Instruction DC = 0 CNT = 01h After Instruction Z = 0 W = 05h After Instruction C = 1 DC = 0 CNT = 00h Z = 1 Example 2: Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS30009960F-page 438  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – 1  dest, Operation: (f) – 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’. placed back in register ‘f’. If the result is ‘0’, the next instruction If the result is not ‘0’, the next which is already fetched is discarded instruction which is already fetched is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing Section29.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See Bit-Oriented Instructions in Indexed Section29.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT  0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP  0; PC = Address (NZERO)  2009-2018 Microchip Technology Inc. DS30009960F-page 439

PIC18F87K22 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0  k  1048575 Operands: 0  f  255 d  [0,1] Operation: k  PC<20:1> a  [0,1] Status Affected: None Operation: (f) + 1  dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire 2-Mbyte memory incremented. If ‘d’ is ‘0’, the result is range. The 20-bit value ‘k’ is loaded into placed in W. If ‘d’ is ‘1’, the result is PC<20:1>. GOTO is always a two-cycle placed back in register ‘f’. instruction. If ‘a’ is ‘0’, the Access Bank is selected. Words: 2 If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Cycles: 2 If ‘a’ is ‘0’ and the extended instruction Q Cycle Activity: set is enabled, this instruction operates Q1 Q2 Q3 Q4 in Indexed Literal Offset Addressing Decode Read literal No Read literal mode whenever f 95 (5Fh). See ‘k’<7:0>, operation ‘k’<19:8>, Section29.2.3 “Byte-Oriented and Write to PC Bit-Oriented Instructions in Indexed No No No No Literal Offset Mode” for details. operation operation operation operation Words: 1 Cycles: 1 Example: GOTO THERE Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 PC = Address (THERE) Decode Read Process Write to register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS30009960F-page 440  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) + 1  dest, Operation: (f) + 1  dest, skip if result  0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’. placed back in register ‘f’. If the result is not ‘0’, the next If the result is ‘0’, the next instruction instruction which is already fetched is which is already fetched is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG  0; PC = Address (ZERO) PC = Address (NZERO) If CNT  0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO)  2009-2018 Microchip Technology Inc. DS30009960F-page 441

PIC18F87K22 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) .OR. k  W a  [0,1] Status Affected: N, Z Operation: (W) .OR. (f)  dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. Q Cycle Activity: If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data W set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: IORLW 35h mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = 9Ah Literal Offset Mode” for details. After Instruction W = BFh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS30009960F-page 442  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0  f  2 Operands: 0  f  255 0  k  4095 d  [0,1] a  [0,1] Operation: k  FSRf Operation: f  dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to file select register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’. Location ‘f’ Q Cycle Activity: can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 Decode Read literal Process Write If ‘a’ is ‘0’, the Access Bank is selected. ‘k’ MSB Data literal ‘k’ If ‘a’ is ‘1’, the BSR is used to select the MSB to GPR bank. FSRfH If ‘a’ is ‘0’ and the extended instruction Decode Read literal Process Write literal set is enabled, this instruction operates ‘k’ LSB Data ‘k’ to FSRfL in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Example: LFSR 2, 3ABh Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. FSR2H = 03h FSR2L = ABh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data W Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h  2009-2018 Microchip Technology Inc. DS30009960F-page 443

PIC18F87K22 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLB k s d Operands: 0  f  4095 Operands: 0  k  255 s 0  f  4095 d Operation: k  BSR Operation: (f )  f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffff s Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffff d of BSR<7:4> always remains ‘0’ Description: The contents of source register, ‘f ’, are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Decode Read Process Write literal Either source or destination can be W literal ‘k’ Data ‘k’ to BSR (a useful special situation). MOVFF is particularly useful for Example: MOVLB 5 transferring a data memory location to a peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h After Instruction The MOVFF instruction cannot use the BSR Register = 05h PCL, TOSU, TOSH or TOSL as the destination register Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS30009960F-page 444  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: k  W Operation: (W)  f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank. literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: MOVLW 5Ah in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See After Instruction Section29.2.3 “Byte-Oriented and W = 5Ah Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh  2009-2018 Microchip Technology Inc. DS30009960F-page 445

PIC18F87K22 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: (W) x k  PRODH:PRODL Operation: (W) x (f)  PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried out 8-bit literal ‘k’. The 16-bit result is between the contents of W and the placed in the PRODH:PRODL register register file location ‘f’. The 16-bit result is pair. PRODH contains the high byte. stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W is unchanged. W and ‘f’ are unchanged. None of the Status flags are affected. None of the Status flags are affected. Note that neither Overflow nor Carry is Note that neither Overflow nor Carry is possible in this operation. A Zero result possible in this operation. A Zero result is is possible but not detected. possible but not detected. Words: 1 If ‘a’ is ‘0’, the Access Bank is selected. If Cycles: 1 ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set Decode Read Process Write is enabled, this instruction operates in literal ‘k’ Data registers Indexed Literal Offset Addressing mode PRODH: whenever f 95 (5Fh). See PRODL Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: MULLW 0C4h Words: 1 Before Instruction W = E2h Cycles: 1 PRODH = ? Q Cycle Activity: PRODL = ? After Instruction Q1 Q2 Q3 Q4 W = E2h Decode Read Process Write PRODH = ADh register ‘f’ Data registers PRODL = 08h PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS30009960F-page 446  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0  f  255 Operands: None a  [0,1] Operation: No operation Operation: (f) + 1  f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: Section29.2.3 “Byte-Oriented and None. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h]  2009-2018 Microchip Technology Inc. DS30009960F-page 447

PIC18F87K22 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC + 2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS30009960F-page 448  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n  PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC + 2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC + 2 + 2n. This instruction is a Decode Start No No two-cycle instruction. reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to PC Flags* = Reset Value ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2)  2009-2018 Microchip Technology Inc. DS30009960F-page 449

PIC18F87K22 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, Operation: k  W, 1  GIE/GIEH or PEIE/GIEL; (TOS)  PC, if s = 1, PCLATU, PCLATH are unchanged (WS)  W, Status Affected: None (STATUSS)  STATUS, (BSRS)  BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the 8-bit literal ‘k’. The Status Affected: GIE/GIEH, PEIE/GIEL. Program Counter is loaded from the top of the stack (the return address). The Encoding: 0000 0000 0001 000s high address latch (PCLATH) remains Description: Return from interrupt. Stack is popped unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 Global Interrupt Enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers WS, Q1 Q2 Q3 Q4 STATUSS and BSRS are loaded into Decode Read Process POP PC their corresponding registers W, literal ‘k’ Data from stack, STATUS and BSR. If ‘s’ = 0, no update write to W of these registers occurs. No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS RETLW kn ; End of table W = WS BSR = BSRS STATUS = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn DS30009960F-page 450  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s  [0,1] Operands: 0  f  255 d  [0,1] Operation: (TOS)  PC; a  [0,1] if s = 1, (WS)  W, Operation: (f<n>)  dest<n + 1>, (STATUSS)  STATUS, (f<7>)  C, (BSRS)  BSR, (C)  dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry flag. popped and the top of the stack (TOS) If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is loaded into the Program Counter. If is ‘1’, the result is stored back in register ‘s’= 1, the contents of the shadow ‘f’. registers WS, STATUSS and BSRS are If ‘a’ is ‘0’, the Access Bank is selected. loaded into their corresponding If ‘a’ is ‘1’, the BSR is used to select the registers W, STATUS and BSR. If GPR bank. ‘s’ = 0, no update of these registers occurs. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 2 mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Q Cycle Activity: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1  2009-2018 Microchip Technology Inc. DS30009960F-page 451

PIC18F87K22 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f<n>)  dest<n + 1>, Operation: (f<n>)  dest<n – 1>, (f<7>)  dest<0> (f<0>)  C, (C)  dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’. flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘0’, the Access Bank is selected. register ‘f’. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank. set is enabled, this instruction operates in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f 95 (5Fh). See set is enabled, this instruction operates Section29.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f 95 (5Fh). See Literal Offset Mode” for details. Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS30009960F-page 452  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a [0,1] a  [0,1] Operation: FFh  f Operation: (f<n>)  dest<n – 1>, Status Affected: None (f<0>)  dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank. placed back in register ‘f’. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f 95 (5Fh). See per the BSR value. Section29.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111  2009-2018 Microchip Technology Inc. DS30009960F-page 453

PIC18F87K22 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 f 255 d  [0,1] Operation: 00h  WDT, a  [0,1] 0  WDT postscaler, 1  TO, Operation: (W) – (f) – (C) dest 0  PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored in is set. The Watchdog Timer and its W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’. The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is selected. If with the oscillator stopped. ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction operates in Q Cycle Activity: Indexed Literal Offset Addressing mode Q1 Q2 Q3 Q4 whenever f 95 (5Fh). See Decode No Process Go to Section29.2.3 “Byte-Oriented and operation Data Sleep Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to TO = 1 † register ‘f’ Data destination PD = 0 Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS30009960F-page 454  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 k 255 Operands: 0 f 255 d  [0,1] Operation: k – (W) W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the result Q Cycle Activity: is stored back in register ‘f’. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read Process Write to If ‘a’ is ‘1’, the BSR is used to select the literal ‘k’ Data W GPR bank. If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction operates Before Instruction in Indexed Literal Offset Addressing W = 01h mode whenever f 95 (5Fh). See C = ? Section29.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 01h Literal Offset Mode” for details. C = 1 ; result is positive Z = 0 Words: 1 N = 0 Cycles: 1 Example 2: SUBLW 02h Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 W = 02h C = ? Decode Read Process Write to After Instruction register ‘f’ Data destination W = 00h C = 1 ; result is zero Example 1: SUBWF REG, 1, 0 Z = 1 Before Instruction N = 0 REG = 3 Example 3: SUBLW 02h W = 2 C = ? Before Instruction After Instruction W = 03h REG = 1 C = ? W = 2 After Instruction C = 1 ; result is positive W = FFh ; (2’s complement) Z = 0 C = 0 ; result is negative N = 0 Z = 0 Example 2: SUBWF REG, 0, 0 N = 1 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1  2009-2018 Microchip Technology Inc. DS30009960F-page 455

PIC18F87K22 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: (f<3:0>)  dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>)  dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored Description: The upper and lower nibbles of register in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’. is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing Section29.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See Bit-Oriented Instructions in Indexed Section29.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) REG = 35h C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS30009960F-page 456  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR))  TABLAT; MEMORY(00A356h) = 34h TBLPTR – No Change After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR))  TABLAT; TBLPTR = 00A357h (TBLPTR) + 1  TBLPTR Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR))  TABLAT; Before Instruction (TBLPTR) – 1  TBLPTR TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY(01A357h) = 12h (TBLPTR) + 1  TBLPTR; MEMORY(01A358h) = 34h (Prog Mem (TBLPTR))  TABLAT After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR<0> = 0:Least Significant Byte of Program Memory Word TBLPTR<0> = 1:Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write Memory) TABLAT)  2009-2018 Microchip Technology Inc. DS30009960F-page 457

PIC18F87K22 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT)  Holding Register; TBLPTR = 00A356h HOLDING REGISTER TBLPTR – No Change (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT)  Holding Register; TABLAT = 55h (TBLPTR) + 1  TBLPTR TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT)  Holding Register; (00A356h) = 55h (TBLPTR) – 1  TBLPTR Example 2: TBLWT +*; if TBLWT+*, Before Instruction (TBLPTR) + 1  TBLPTR; TABLAT = 34h (TABLAT)  Holding Register TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER (01389Bh) = 34h 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section6.0 “Memory Organization” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0:Least Significant Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register) DS30009960F-page 458  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0  f  255 Operands: 0 k 255 a  [0,1] Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to set is enabled, this instruction operates literal ‘k’ Data W in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: XORLW 0AFh Section29.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. W = B5h After Instruction Words: 1 W = 1Ah Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT  00h, PC = Address (NZERO)  2009-2018 Microchip Technology Inc. DS30009960F-page 459

PIC18F87K22 FAMILY XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS30009960F-page 460  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 29.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table29-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section29.2.2 “Extended Instruction instruction set, the PIC18F87K22 family of devices also Set”. The opcode field descriptions in Table29-1 provides an optional extension to the core CPU func- (page420) apply to both the standard and extended tionality. The added features include eight additional PIC18 instruction sets. instructions that augment Indirect and Indexed Addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction set these instructions directly in assembler. are enabled by default on unprogrammed devices. The syntax for these commands is Users must properly set or clear the XINST Configura- provided as a reference for users who tion bit during programming to enable or disable these may be reviewing code that has been features. generated by a compiler. The instructions in the extended set can all be classified as literal operations, which either manipulate 29.2.1 EXTENDED INSTRUCTION SYNTAX the File Select Registers, or use them for Indexed Most of the extended instructions use indexed argu- Addressing. Two of the instructions, ADDFSR and ments, using one of the File Select Registers and some SUBFSR, each have an additional special instantiation offset to specify a source or destination register. When for using FSR2. These versions (ADDULNK and an argument for an instruction serves as part of SUBULNK) allow for automatic return after execution. Indexed Addressing, it is enclosed in square brackets The extended instructions are specifically implemented (“[ ]”). This is done to indicate that the argument is used to optimize re-entrant program code (that is, code that as an index or offset. The MPASM™ Assembler will is recursive or that uses a software stack) written in flag an error if it determines that an index or offset value high-level languages, particularly C. Among other is not bracketed. things, they allow users working in high-level When the extended instruction set is enabled, brackets languages to perform certain operations on data are also used to indicate index arguments in structures more efficiently. These include: byte-oriented and bit-oriented instructions. This is in • Dynamic allocation and deallocation of software addition to other changes in their syntax. For more stack space when entering and leaving details, see Section29.2.3.1 “Extended Instruction subroutines Syntax with Standard PIC18 Commands”. • Function Pointer invocation Note: In the past, square brackets have been • Software Stack Pointer manipulation used to denote optional arguments in the • Manipulation of variables located in a software PIC18 and earlier instruction sets. In this stack text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 29-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None Decrement FSR2 SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None return  2009-2018 Microchip Technology Inc. DS30009960F-page 461

PIC18F87K22 FAMILY 29.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 + k  FSR2, Operation: FSR(f) + k  FSR(f) (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the TOS. Cycles: 1 Q Cycle Activity: The instruction takes two cycles to execute; a NOP is performed during Q1 Q2 Q3 Q4 the second cycle. Decode Read Process Write to literal ‘k’ Data FSR This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates Example: ADDFSR 2, 23h only on FSR2. Words: 1 Before Instruction FSR2 = 03FFh Cycles: 2 After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS30009960F-page 462  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0  z  127 s 0  f  4095 Operation: (PC + 2)  TOS, d (W)  PCL, Operation: ((FSR2) + z )  f s d (PCLATH)  PCH, Status Affected: None (PCLATU)  PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffff d Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’, in the first word, to the value s latched into PCH and PCU, of FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘fd’ in the second word. Both addresses new next instruction is fetched. can be anywhere in the 4096-byte data space (000h to FFFh). Unlike CALL, there is no option to update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an Indirect Addressing register, the Q1 Q2 Q3 Q4 value returned will be 00h. Decode Read Push PC to No Words: 2 WREG stack operation Cycles: 2 No No No No operation operation operation operation Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Before Instruction Decode No No Write PC = address (HERE) operation operation register ‘f’ PCLATH = 10h No dummy (dest) PCLATU = 00h W = 06h read After Instruction PC = 001006h TOS = address (HERE + 2) Example: MOVSF [05h], REG2 PCLATH = 10h PCLATU = 00h Before Instruction W = 06h FSR2 = 80h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h  2009-2018 Microchip Technology Inc. DS30009960F-page 463

PIC18F87K22 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0  zs  127 Operands: 0k  255 0  z  127 d Operation: k  (FSR2), Operation: ((FSR2) + zs)  ((FSR2) + zd) FSR2 – 1  FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1110 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. Description The contents of the source register are FSR2 is decremented by 1 after the moved to the destination register. The operation. addresses of the source and destination registers are determined by adding the This instruction allows users to push 7-bit literal offsets, ‘z ’ or ‘z ’, values onto a software stack. s d respectively, to the value of FSR2. Both Words: 1 registers can be located anywhere in the 4096-byte data memory space Cycles: 1 (000h to FFFh). Q Cycle Activity: The MOVSS instruction cannot use the Q1 Q2 Q3 Q4 PCL, TOSU, TOSH or TOSL as the Decode Read ‘k’ Process Write to destination register. data destination If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. If the Example: PUSHL 08h resultant destination address points to Before Instruction an Indirect Addressing register, the FSR2H:FSR2L = 01ECh instruction will execute as a NOP. Memory (01ECh) = 00h Words: 2 After Instruction Cycles: 2 FSR2H:FSR2L = 01EBh Q Cycle Activity: Memory (01ECh) = 08h Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS30009960F-page 464  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 – k  FSR2, Operation: FSRf – k  FSRf (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified contents of the FSR2. A RETURN is then by ‘f’. executed by loading the PC with the TOS. Words: 1 Cycles: 1 The instruction takes two cycles to execute; a NOP is performed during the Q Cycle Activity: second cycle. Q1 Q2 Q3 Q4 This may be thought of as a special case Decode Read Process Write to of the SUBFSR instruction, where f = 3 register ‘f’ Data destination (binary ‘11’); it operates only on FSR2. Words: 1 Example: SUBFSR 2, 23h Cycles: 2 Before Instruction Q Cycle Activity: FSR2 = 03FFh Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to FSR2 = 03DCh register ‘f’ Data destination No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS)  2009-2018 Microchip Technology Inc. DS30009960F-page 465

PIC18F87K22 FAMILY 29.2.3 BYTE-ORIENTED AND 29.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file Note: Enabling the PIC18 instruction set exten- register argument ‘f’ in the standard byte-oriented and sion may cause legacy applications to bit-oriented commands is replaced with the literal offset value ‘k’. As already noted, this occurs only when ‘f’ is behave erratically or fail entirely. less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing (Section6.6.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within the brackets, will the standard PIC18 instruction set are interpreted. generate an error in the MPASM™ Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is either as a location in the Access Bank (a = 0) or in a never specified; it will automatically be assumed to be GPR bank designated by the BSR (a = 1). When the ‘0’. This is in contrast to standard operation (extended extended instruction set is enabled and a = 0, however, instruction set disabled), when ‘a’ is set on the basis of a file register argument of 5Fh or less is interpreted as the target address. Declaring the Access RAM bit in an offset from the pointer value in FSR2 and not as a this mode will also generate an error in the MPASM literal address. For practical purposes, this means that Assembler. all instructions that use the Access RAM bit as an The destination argument, ‘d’, functions as before. argument – that is, all byte-oriented and bit-oriented instructions, or almost half of the core PIC18 instruc- In the latest versions of the MPASM Assembler, tions – may behave differently when the extended language support for the extended instruction set must instruction set is enabled. be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the When the content of FSR2 is 00h, the boundaries of the source listing. Access RAM are essentially remapped to their original values. This may be useful in creating backward 29.2.4 CONSIDERATIONS WHEN compatible code. If this technique is used, it may be ENABLING THE EXTENDED necessary to save the value of FSR2 and restore it INSTRUCTION SET when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users It is important to note that the extensions to the instruc- must also keep in mind the syntax requirements of the tion set may not be beneficial to all users. In particular, extended instruction set (see Section29.2.3.1 users who are not writing code that uses a software “Extended Instruction Syntax with Standard PIC18 stack may not benefit from using the extensions to the Commands”). instruction set. Although the Indexed Literal Offset mode can be very Additionally, the Indexed Literal Offset Addressing useful for dynamic stack and pointer manipulation, it mode may create issues with legacy applications can also be very annoying if a simple arithmetic opera- written to the PIC18 assembler. This is because tion is carried out on the wrong register. Users who are instructions in the legacy code may attempt to address accustomed to the PIC18 programming must keep in registers in the Access Bank below 5Fh. Since these mind, that when the extended instruction set is addresses are interpreted as literal offsets to FSR2 enabled, register addresses of 5Fh or less are used for when the instruction set extension is enabled, the Indexed Literal Offset Addressing. application may read or write to the wrong data addresses. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset When porting an application to the PIC18F87K22 family, mode are provided on the following page to show how it is very important to consider the type of code. A large, execution is affected. The operand conditions shown in re-entrant application that is written in C and would the examples are applicable to all instructions of these benefit from efficient compilation will do well when using types. the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS30009960F-page 466  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0  k  95 Operands: 0  f  95 d  [0,1] 0  b  7 Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ Cycles: 1 is ‘1’, the result is stored back in register ‘f’. Q Cycle Activity: Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1 register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Contents Example: ADDWF [OFST],0 of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction Set Indexed SETF W = 37h (Indexed Literal Offset mode) Contents of 0A2Ch = 20h Syntax: SETF [k] Operands: 0  k  95 Operation: FFh  ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh  2009-2018 Microchip Technology Inc. DS30009960F-page 467

PIC18F87K22 FAMILY 29.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set for the PIC18F87K22 family. This includes the • A menu option or dialog box within the MPLAB C18 C Compiler, MPASM assembly language environment that allows the user to configure the and MPLAB Integrated Development Environment language tool and its settings for the project (IDE). • A command line option When selecting a target device for software • A directive in the source code development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for These options vary between different compilers, the XINST Configuration bit is ‘0’, disabling the assemblers and development environments. Users are extended instruction set and Indexed Literal Offset encouraged to review the documentation accompany- Addressing. For proper execution of applications ing their development systems for the appropriate developed to take advantage of the extended information. instruction set, XINST must be set during programming. DS30009960F-page 468  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 30.0 DEVELOPMENT SUPPORT 30.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker Preliminary  2009-2018 Microchip Technology Inc. DS30009960F-page 469

PIC18F87K22 FAMILY 30.2 MPLAB XC Compilers 30.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 30.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 30.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process Preliminary DS30009960F-page 470  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 30.6 MPLAB X SIM Software Simulator 30.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 30.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 30.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 30.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. Preliminary  2009-2018 Microchip Technology Inc. DS30009960F-page 471

PIC18F87K22 FAMILY 30.11 Demonstration/Development 30.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary DS30009960F-page 472  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 31.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any digital only I/O pin with respect to VSS (except VDD)...........................................................-0.3V to 7.5V Voltage on MCLR with respect to VSS...........................................................................................................0.3V to 9.0V Voltage on any combined digital and analog pin with respect to VSS (except VDD and MCLR)......-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS (with regulator enabled)..................................................................... -0.3V to 5.5V Voltage on VDD with respect to VSS (with regulator disabled)..................................................................... -0.3V to 3.6V Total power dissipation (Note 1)..................................................................................................................................1W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20mA Maximum output current sunk by PORTA<7:6> and any PORTB and PORTC I/O pins.........................................25mA Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins..........................................................8mA Maximum output current sunk by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins............................2mA Maximum output current sourced by PORTA<7:6> and any PORTB and PORTC I/O pins...................................25mA Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins.....................................................8mA Maximum output current sourced by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins.......................2mA Maximum current sunk byall ports combined.......................................................................................................200mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2009-2018 Microchip Technology Inc. DS30009960F-page 473

PIC18F87K22 FAMILY FIGURE 31-1: VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (INDUSTRIAL/EXTENDED)(1) 6V 5.5V 5V 4V PIC18F87K22 Family PIC18F87K22 Family ) (Extended) (Industrial Only) D D V 3V ( e 3V g a olt 1.8V V 0 4 MHz 48 MHz 64 MHz(1) Frequency Note 1: FMAX = 25 MHz in 8-Bit External Memory mode. For VDD values, 1.8V to 3V, FMAX = (VDD – 1.72)/0.02 MHz. 2: FMAX = 64 MHz in all other modes. For VDD values, 1.8V to 3V, FMAX = (VDD – 1.72)/0.02 MHz. FIGURE 31-2: VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (INDUSTRIAL/EXTENDED)(1,2) 4V 3.75V 3.6V PIC18F87K22 Family 3.25V PIC18F87K22 Family (Industrial Only) (Extended) 3V )D 2.5V D V ( e 1.8V g a olt V 4 MHz 48 MHz 64 MHz Frequency Note 1: When the on-chip voltage regulator is disabled, VDD must be maintained so that VDD 3.6V. 2: For VDD values, 1.8V to 3V, FMAX = (VDD – 1.72)/0.02 MHz. DS30009960F-page 474  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 31.1 DC Characteristics: Supply Voltage PIC18F87K22 Family (Industrial/Extended) Standard Operating Conditions (unless otherwise stated) PIC18F87K22 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage 1.8 — 3.6 V ENVREG tied to VSS 1.8 — 5.5 V ENVREG tied to VDD D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V D001D AVSS Analog Ground Potential VSS – 0.3 — VSS + 0.3 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See Section5.3 “Power-on to Ensure Internal Reset (POR)” for details Power-on Reset Signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section5.3 “Power-on to Ensure Internal Reset (POR)” for details Power-on Reset Signal D005 BVDD Brown-out Reset Voltage (High/Medium/ Low-Power mode)(2) BORV<1:0> = 11(3) 1.69 1.8 1.91 BORV<1:0> = 10 1.88 2.0 2.12 BORV<1:0> = 01 2.53 2.7 2.86 BORV<1:0> = 00 2.82 3.0 3.18 Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: The following values are taken in HP-BOR mode. 3: The device will operate normally until Brown-out Reset occurs, even though VDD may be below VDDMIN.  2009-2018 Microchip Technology Inc. DS30009960F-page 475

PIC18F87K22 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) Standard Operating Conditions (unless otherwise stated) PIC18F87K22 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) All devices 10 500 nA -40°C 20 500 nA +25°C VDD = 1.8V(4) 120 600 nA +60°C (Sleep mode) 630 1800 nA +85°C Regulator Disabled 4 9 µA +125ºC All devices 50 700 nA -40°C 60 700 nA +25°C VDD = 3.3V(4) 170 800 nA +60°C (Sleep mode) 700 2700 nA +85°C Regulator Disabled 5 11 µA +125ºC All devices 350 1300 nA -40°C 400 1400 nA +25°C VDD = 5V(5) 550 1500 nA +60°C (Sleep mode) 1350 4000 nA +85°C Regulator Enabled 6 12 µA +125ºC Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = External square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CONFIG1L<0>) = 1). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0). 6: 48 MHz, maximum frequency at +125ºC. DS30009960F-page 476  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F87K22 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) All devices 5.3 10 µA -40°C 5.5 10 µA +25°C VDD = 1.8V(4) 5.5 10 µA +85°C Regulator Disabled 12 24 µA +125ºC All devices 10 15 µA -40°C 10 16 µA +25°C VDD = 3.3V(4) FOSC = 31kHz (RC_RUN mode, 11 17 µA +85°C Regulator Disabled LF-INTOSC) 15 35 µA +125ºC All devices 70 180 µA -40°C 80 185 µA +25°C VDD = 5V(5) 90 190 µA +85°C Regulator Enabled 200 500 µA +125ºC All devices 410 850 µA -40°C 410 800 µA +25°C VDD = 1.8V(4) 410 830 µA +85°C Regulator Disabled 700 1500 µA +125ºC All devices 680 990 µA -40°C 680 960 µA +25°C VDD = 3.3V(4) FOSC = 1MHz (RC_RUN mode, 670 950 µA +85°C Regulator Disabled HF-INTOSC) 800 1700 µA +125ºC All devices 760 1400 µA -40°C 780 1400 µA +25°C VDD = 5V(5) 800 1500 µA +85°C Regulator Enabled 1200 2400 µA +125ºC All devices 760 1300 µA -40°C 760 1400 µA +25°C VDD = 1.8V(4) 770 1500 µA +85°C Regulator Disabled 800 1700 µA +125ºC All devices 1.4 2.5 mA -40°C 1.4 2.5 mA +25°C VDD = 3.3V(4) FOSC = 4MHz (RC_RUN mode, 1.4 2.5 mA +85°C Regulator Disabled HF-INTOSC) 1.5 3.0 mA +125ºC All devices 1.5 2.7 mA -40°C 1.5 2.7 mA +25°C VDD = 5V(5) 1.5 2.7 mA +85°C Regulator Enabled 1.6 3.3 mA +125ºC Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = External square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CONFIG1L<0>) = 1). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0). 6: 48 MHz, maximum frequency at +125ºC.  2009-2018 Microchip Technology Inc. DS30009960F-page 477

PIC18F87K22 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F87K22 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) All devices 2.1 5.5 µA -40°C 2.1 5.7 µA +25°C VDD = 1.8V(4) 2.2 6.0 µA +85°C Regulator Disabled 10 20 µA +125ºC All devices 3.7 7.5 µA -40°C 3.9 7.8 µA +25°C VDD = 3.3V(4) FOSC = 31kHz (RC_IDLE mode, 3.9 8.5 µA +85°C Regulator Disabled LF-INTOSC) 12 24 µA +125ºC All devices 70 180 µA -40°C 80 190 µA +25°C VDD = 5V(5) 80 200 µA +85°C Regulator Enabled 200 420 µA +125ºC All devices 330 650 µA -40°C 330 640 µA +25°C VDD = 1.8V(4) 330 630 µA +85°C Regulator Disabled 500 850 µA +125ºC All devices 520 850 µA -40°C 520 900 µA +25°C VDD = 3.3V(4) FOSC = 1MHz (RC_IDLE mode, 520 850 µA +85°C Regulator Disabled HF-INTOSC) 800 1200 µA +125ºC All devices 590 940 µA -40°C 600 960 µA +25°C VDD = 5V(5) 620 990 µA +85°C Regulator Enabled 1000 1400 µA +125ºC All devices 470 770 µA -40°C 470 770 µA +25°C VDD = 1.8V(4) 460 760 µA +85°C Regulator Disabled 700 1000 µA +125ºC All devices 800 1400 µA -40°C 800 1350 µA +25°C VDD = 3.3V(4) FOSC = 4MHz (RC_IDLE mode, 790 1300 µA +85°C Regulator Disabled internal HF-INTOSC) 1100 1400 µA +125ºC All devices 880 1600 µA -40°C 890 1700 µA +25°C VDD = 5V(5) 910 1800 µA +85°C Regulator Enabled 1200 2200 µA +125ºC Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = External square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CONFIG1L<0>) = 1). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0). 6: 48 MHz, maximum frequency at +125ºC. DS30009960F-page 478  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F87K22 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) All devices 130 390 µA -40°C 130 390 µA +25°C VDD = 1.8V(4) 130 390 µA +85°C Regulator Disabled 250 500 µA +125ºC All devices 270 790 µA -40°C 270 790 µA +25°C VDD = 3.3V(4) FOSC = 1MHZ (PRI_RUN mode, 270 790 µA +85°C Regulator Disabled EC oscillator) 400 900 µA +125ºC All devices 430 990 µA -40°C 450 980 µA +25°C VDD = 5V(5) 460 980 µA +85°C Regulator Enabled 600 1300 µA +125ºC All devices 430 860 µA -40°C 530 900 µA +25°C VDD = 1.8V(4) 490 880 µA +85°C Regulator Disabled 750 1600 µA +125ºC All devices 850 1750 µA -40°C 850 1700 µA +25°C VDD = 3.3V(4) FOSC = 4MHz (PRI_RUN mode, 850 1800 µA +85°C Regulator Disabled EC oscillator) 1150 2400 µA +125ºC All devices 1.1 2.7 mA -40°C 1.1 2.6 mA +25°C VDD = 5V(5) 1.1 2.6 mA +85°C Regulator Enabled 2.0 4.0 mA +125ºC All devices 12 19 mA -40°C 12 19 mA +25°C VDD = 3.3V(4) 12 19 mA +85°C Regulator Disabled 13 22 mA +125ºC(6) FOSC = 64MHZ (PRI_RUN mode, All devices 13 20 mA -40°C EC oscillator) 13 20 mA +25°C VDD = 5V(4) 13 20 mA +85°C Regulator Enabled 14 23 mA +125ºC(6) Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = External square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CONFIG1L<0>) = 1). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0). 6: 48 MHz, maximum frequency at +125ºC.  2009-2018 Microchip Technology Inc. DS30009960F-page 479

PIC18F87K22 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F87K22 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) All devices 3.3 5.6 mA -40°C 3.3 5.5 mA +25°C VDD = 3.3V(4) 3.3 5.5 mA +85°C Regulator Disabled 3.6 6.0 mA +125ºC FOSC = 16MHZ, (PRI_RUN mode, 4 MHz All devices 3.5 5.9 mA -40°C EC oscillator with PLL) 3.5 5.8 mA +25°C VDD = 5V(5) 3.5 5.8 mA +85°C Regulator Enabled 3.8 7.0 mA +125ºC All devices 12 18 mA -40°C 12 18 mA +25°C VDD = 3.3V(4) 12 18 mA +85°C Regulator Disabled 13 22 mA +125ºC(6) FOSC = 64MHZ, (PRI_RUN mode, 16 MHz All devices 13 20 mA -40°C EC oscillator with PLL) 13 20 mA +25°C VDD = 5V(5) 13 20 mA +85°C Regulator Enabled 14 24 mA +125ºC(6) Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = External square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CONFIG1L<0>) = 1). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0). 6: 48 MHz, maximum frequency at +125ºC. DS30009960F-page 480  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F87K22 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) All devices 42 73 µA -40°C 42 73 µA +25°C VDD = 1.8V(4) 43 74 µA +85°C Regulator Disabled 53 100 µA +125ºC All devices 110 190 µA -40°C 110 195 µA +25°C VDD = 3.3V(4) FOSC = 1MHz (PRI_IDLE mode, 110 195 µA +85°C Regulator Disabled EC oscillator) 130 250 µA +125ºC All devices 280 450 µA -40°C 290 440 µA +25°C VDD = 5V(5) 300 460 µA +85°C Regulator Enabled 330 500 µA +125ºC All devices 160 360 µA -40°C 160 360 µA +25°C VDD = 1.8V(4) 170 370 µA +85°C Regulator Disabled 200 400 µA +125ºC All devices 330 650 µA -40°C 340 660 µA +25°C VDD = 3.3V(4) FOSC = 4MHz (PRI_IDLE mode, 340 660 µA +85°C Regulator Disabled EC oscillator) 370 700 µA +125ºC All devices 510 900 µA -40°C 520 950 µA +25°C VDD = 5V(5) 540 990 µA +85°C Regulator Enabled 600 1200 µA +125ºC All devices 4.7 9 mA -40°C 4.8 9 mA +25°C VDD = 3.3V(4) 4.8 10 mA +85°C Regulator Disabled 5.2 12 mA +125ºC(6) FOSC = 64MHz (PRI_IDLE mode, All devices 5.1 11 mA -40°C EC oscillator) 5.1 11 mA +25°C VDD = 5V(5) 5.2 12 mA +85°C Regulator Enabled 5.7 14 mA +125ºC(6) Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = External square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CONFIG1L<0>) = 1). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0). 6: 48 MHz, maximum frequency at +125ºC.  2009-2018 Microchip Technology Inc. DS30009960F-page 481

PIC18F87K22 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F87K22 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) All devices 3.7 8.5 µA -40°C 5.4 10 µA +25°C VDD = 1.8V(4) 6.6 13 µA +85°C Regulator Disabled 13 30 µA +125ºC All devices 8.7 18 µA -40°C 10 20 µA +25°C VDD = 3.3V(4) FOSC = 32kHz(3) (SEC_RUN mode, 12 23 µA +85°C Regulator Disabled SOSCSEL = 01) 25 60 µA +125ºC All devices 60 160 µA -40°C 90 190 µA +25°C VDD = 5V(4) 100 240 µA +85°C Regulator Enabled 200 450 µA +125ºC All devices 1.2 4 µA -40°C 1.7 5 µA +25°C VDD = 1.8V(4) 2.6 6 µA +85°C Regulator Disabled 9 20 µA +125ºC All devices 1.6 7 µA -40°C 2.8 9 µA +25°C VDD = 3.3V(4) FOSC = 32kHz(3) (SEC_IDLE mode, 4.1 10 µA +85°C Regulator Disabled SOSCSEL = 01) 17 40 µA +125ºC All devices 60 150 µA -40°C 80 180 µA +25°C VDD = 5V(5) 100 240 µA +85°C Regulator Enabled 180 440 µA +125ºC Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = External square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CONFIG1L<0>) = 1). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0). 6: 48 MHz, maximum frequency at +125ºC. DS30009960F-page 482  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F87K22 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Module Differential Currents (IWDT, IBOR, IHLVD, IOSCB, IAD) Watchdog Timer D022 All devices 0.3 1 µA -40°C (IWDT) 0.3 1 µA +25°C VDD = 1.8V(4) D022 0.3 1 µA +85°C Regulator Disabled (IWDT) 0.5 2 µA +125ºC All devices 0.6 2 µA -40°C 0.6 2 µA +25°C VDD = 3.3V(4) 0.7 2 µA +85°C Regulator Disabled 1 3 µA +125ºC All Devices 0.6 2 µA -40°C 0.6 2 µA +25°C VDD = 5V(5) 0.7 2 µA +85°C Regulator Enabled 1.5 4 µA +125ºC D022A Brown-out Reset (IBOR) All devices 4.6 19 µA -40°C (IBOR) 4.5 20 µA +25°C VDD = 3.3V(4) High-Power BOR 4.7 20 µA +85°C Regulator Disabled 18 40 µA +125ºC All devices 4.2 20 µA -40°C 4.3 20 µA +25°C VDD = 5V(5) High-Power BOR 4.4 20 µA +85°C Regulator Enabled 20 40 µA +125ºC D022B High/Low-Voltage Detect (IHLVD) All devices 3.8 9 µA -40°C 4.2 9 µA +25°C VDD = 1.8V(4) 4.3 10 µA +85°C Regulator Disabled 4.5 12 µA +125ºC All devices 4.5 11 µA -40°C 4.8 12 µA +25°C VDD = 3.3V(4) 4.8 12 µA +85°C Regulator Disabled 5.0 14 µA +125ºC All devices 4.9 13 µA -40°C 4.9 13 µA +25°C VDD = 5V(5) 4.9 13 µA +85°C Regulator Enabled 5.3 15 µA +125ºC Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = External square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CONFIG1L<0>) = 1). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0). 6: 48 MHz, maximum frequency at +125ºC.  2009-2018 Microchip Technology Inc. DS30009960F-page 483

PIC18F87K22 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F87K22 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. D025 Real-Time Clock/Calendar with SOSC Oscillator (IRTCC) All devices 0.7 2.7 µA -40°C 0.7 2.8 µA +25°C VDD = 1.8V(4) 1.1 2.8 µA +60°C Regulator Disabled 1.1 2.9 µA +85°C 2.2 4.4 µA +125ºC All devices 1.2 2.9 µA -40°C 1.1 2.8 µA +25°C VDD = 3.3V(4) 32.768 kHz, 2 4.6 µA +60°C Regulator Disabled SOSCRUN = 1 2 4.8 µA +85°C 4 6.5 µA +125ºC All devices 1.5 4.4 µA -40°C 1.5 4.4 µA +25°C VDD = 5V(5) 1.7 4.7 µA +60°C Regulator Enabled 1.7 4.7 µA +85°C 3.5 6.9 µA +125ºC Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = External square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CONFIG1L<0>) = 1). 5: Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0). 6: 48 MHz, maximum frequency at +125ºC. DS30009960F-page 484  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 31.3 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage I/O Ports: D030 with TTL Buffer VSS 0.8 V 4.5V < VDD < 5.5V D030A VSS 0.15 VDD V VDD  4.5V D031 with Schmitt Trigger Levels — 0.2 VDD V with I2C Levels VSS 0.3 VDD V with SMBus Levels VSS 0.8 V 2.7V  VDD 5.5V D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.2 VDD V D034 SOSCI VSS 0.3 VDD V VIH Input High Voltage I/O Ports: D040 with TTL Buffer 2.0 — V 4.5V < VDD 5.5V 0.25 VDD V 1.8V  VDD 4.5V D041 with Schmitt Trigger Buffer 0.8 VDD — V 2.0V  VDD 5.5V with I2C Levels 0.7 VDD — V V with SMBus Levels 2.1 — 2.7V  VDD 5.5V D042 MCLR 0.8 VDD — V D043 OSC1 (HS mode) 0.7 VDD — V D043A OSC1 (EC/ECPLL mode) 0.8 VDD — V D044 SOSCI 0.7 VDD V IIL Input Leakage Current(1) D060 I/O Ports ±50 ±200 nA VSS VPIN VDD, Pin at high-impedance D061 MCLR — ±5 A Vss VPIN VDD, +85°C D063 OSC1 — ±5 A Vss VPIN VDD IPU Weak Pull-up Current D070 IPURB PORTB Weak Pull-up Current 50 400 A VDD = 3.3V, VPIN = VSS Note 1: Negative current is defined as current sourced by the pin.  2009-2018 Microchip Technology Inc. DS30009960F-page 485

PIC18F87K22 FAMILY 31.3 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O Ports: PORTA, PORTB, PORTC — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +125C PORTD, PORTE, PORTF, PORTG, — 0.6 V IOL = 3.5 mA, VDD = 4.5V, PORTH, PORTJ -40C to +125C D083 OSC2/CLKO (EC modes) — 0.6 V IOL = 1.6 mA. VDD = 5.5V, -40C to +125C VOH Output High Voltage(1) D090 I/O Ports: V PORTA, PORTB, PORTC VDD – 0.7 — V IOH = -3 mA, VDD = 4.5V, -40C to +125C PORTD, PORTE, PORTF, PORTG, VDD – 0.7 — V IOH = -2 mA, VDD = 4.5V, PORTH, PORTJ -40C to +125C D092 OSC2/CLKO (INTOSC, EC modes) VDD – 0.7 — V IOH = -1 mA, VDD = 5.5V, -40C to +125C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 Pin — 20 pF In HS mode when external clock is used to drive OSC1 D101 CIO All I/O Pins and OSC2 — 50 pF To meet the AC Timing Specifications D102 CB SCLx, SDAx — 400 pF I2C Specification Note 1: Negative current is defined as current sourced by the pin. 31.4 DC Characteristics: CTMU Current Source Specifications Standard Operating Conditions: 1.8V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. IOUT1 CTMU Current Source, — 550 — nA CTMUICON<1:0> = 01 Base Range IOUT2 CTMU Current Source, — 5.5 — A CTMUICON<1:0> = 10 10x Range IOUT3 CTMU Current Source, — 55 — A CTMUICON<1:0> = 11 100x Range Note 1: Nominal value at center point of current trim range (CTMUICON<7:2> = 000000). DS30009960F-page 486  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 31-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP/RE5 VDD + 1.5 — 10 V (Note 3, Note 4) pin D113 IDDP Supply Current during — — 10 mA Programming Data EEPROM Memory (Note 2) D120 ED Byte Endurance 100K — — E/W -40C to +125C D121 VDRW VDD for Read/Write 1.8 — 5.5 V Using EECON to read/ write, ENVREG tied to VDD 1.8 — 3.6 V Using EECON to read/ write, ENVREG tied to VSS D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +125°C Cycles before Refresh(2) Program Flash Memory D130 EP Cell Endurance 10K — — E/W -40C to +125C D131 VPR VDD for Read 1.8 — 5.5 V ENVREG tied to VDD 1.8 — 3.6 V ENVREG tied to VSS D132B VPEW Voltage for Self-Timed Erase or Write Operations VDD 1.8 — 5.5 V ENVREG tied to VDD D133A TIW Self-Timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D135 IDDP Supply Current during — — 10 mA Programming D140 TWE Writes per Erase Cycle — — 1 For each physical address † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guid- ance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section9.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if Single-Supply Programming is disabled. 4: The MPLAB® ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP volt- age must be placed between the MPLAB ICD 2 and the target system when programming or debugging with the MPLAB ICD 2.  2009-2018 Microchip Technology Inc. DS30009960F-page 487

PIC18F87K22 FAMILY 31.5 DC Characteristics: Injection Current (Industrial Only) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial Param Sym Characteristic Min Typ† Max Units Conditions No. 160A IICL Input Low Injection Current 0 — -5(1) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO 160B IICH Input High Injection Current 0 — +5(1) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO 160C IICT Total Input Injection Current -20(1,2) — +20(1,2) mA Absolute instantaneous (sum of all I/O and control sum of all input injection pins) currents from all I/O pins (IICL + IICH) IICT † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Injection currents > | 0 | can affect the A/D results. 2: Any number and/or combination of I/O pins not excluded under |ICL or |ICH conditions are permitted. DS30009960F-page 488  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 31-2: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V  VDD  5V, -40°C  TA  +125°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ±5.0 40 mV D301 VICM Input Common Mode Voltage — — AVDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB D303 TRESP Response Time(1) — 675 1200 ns D304 TMC2OV Comparator Mode Change to — — 10 s Output Valid* Note 1: Response time measured with one comparator input at (AVDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 31-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 1.8V  VDD  5V, -40°C  TA  +125°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution — VDD/32 — LSb D311 VRAA Absolute Accuracy — — 1/2 LSb D312 VRUR Unit Resistor Value (R) — 2k —  D313 TSET Settling Time(1) — — 10 s Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. TABLE 31-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C  TA  +125°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. VRGOUT Regulator Output Voltage — 3.3 — V CEFC External Filter Capacitor Value 4.7 10 — F Capacitor must be low-ESR, a low series resistance (< 5) TABLE 31-5: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance Junction to Ambient 47.6 °C/W 64-pin TQFP package 27.7 °C/W 64-pin QFN package 51.1 °C/W 80-pin TQFP package TH02 JC Thermal Resistance Junction to Case 14.4 °C/W 64-pin TQFP package 13.6 °C/W 64-pin QFN package 18.6 °C/W 80-pin TQFP package  2009-2018 Microchip Technology Inc. DS30009960F-page 489

PIC18F87K22 FAMILY 31.6 AC (Timing) Characteristics 31.6.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS30009960F-page 490  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 31.6.2 TIMING CONDITIONS The temperature and voltages specified in Table31-6 apply to all timing specifications unless otherwise noted. Figure31-3 specifies the load conditions for the timing specifications. TABLE 31-6: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA +85°C for industrial AC CHARACTERISTICS -40°C  TA +125°C for extended Operating voltage VDD range as described in Section31.1 and Section31.3. FIGURE 31-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464 CL = 50 pF for all pins except OSC2/CLKO/RA6 and including D and E outputs as ports CL = 15 pF for OSC2/CLKO/RA6  2009-2018 Microchip Technology Inc. DS30009960F-page 491

PIC18F87K22 FAMILY 31.6.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 31-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 31-7: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKIN DC 64 MHz EC, ECIO Oscillator mode Frequency(1) -40°C ≤ TA ≤ +85°C DC 48 MHz -40°C ≤ TA ≤ +125°C Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 16 MHz HS Oscillator mode 4 16 MHz HS + PLL Oscillator mode 5 33 kHz LP Oscillator mode 1 TOSC External CLKIN Period(1) 15.6 — ns EC, ECIO Oscillator mode Oscillator Period(1) 250 — ns RC Oscillator mode 250 10,000 ns XT Oscillator mode 40 250 ns HS Oscillator mode 62.5 250 ns HS + PLL Oscillator mode 5 200 s LP Oscillator mode 2 TCY Instruction Cycle Time(1) 62.5 — ns TCY = 4/FOSC 3 TOSL, External Clock in (OSC1) 30 — ns XT Oscillator mode TOSH High or Low Time 2.5 — s LP Oscillator mode 10 — ns HS Oscillator mode 4 TOSR, External Clock in (OSC1) — 20 ns XT Oscillator mode TOSF Rise or Fall Time — 50 ns LP Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS30009960F-page 492  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 31-8: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 5.5V) Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 5 MHz VDD = 1.8-5.5V 4 — 16 MHz VDD = 3.0-5.5V, -40°C to +85°C 4 — 12 MHz VDD = 3.0-5.5V, -40°C to +125°C F11 FSYS On-Chip VCO System Frequency 16 — 20 MHz VDD = 1.8-5.5V 16 — 64 MHz VDD = 3.0-5.5V, -40°C to +85°C 16 — 48 MHz VDD = 3.0-5.5V, -40°C to +125°C F12 t PLL Start-up Time (Lock Time) — — 2 ms rc F13 CLK CLKOUT Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 31-9: INTERNAL RC ACCURACY (INTOSC) Standard Operating Conditions (unless otherwise stated) PIC18F87K22 Family Operating temperature -40°C  TA  +125°C Param Min Typ Max Units Conditions No. OA1 HFINTOSC/MFINTOSC Accuracy @ Freq = 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz(1) -2 — 2 % +25°C VDD = 3.0-5.5V -5 — 5 % -5 — 5 % -40°C to +85°C VDD = 1.8-5.5V -10 — 10 % -40°C to +125°C VDD = 1.8-5.5V OA2 LFINTOSC Accuracy @ Freq = 31 kHz -15 — 15 % -40°C to +125°C VDD = 1.8-5.5V Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.  2009-2018 Microchip Technology Inc. DS30009960F-page 493

PIC18F87K22 FAMILY FIGURE 31-5: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure31-3 for load conditions. TABLE 31-10: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1  to CLKO  — 75 200 ns (Note 1) 11 TOSH2CKH OSC1  to CLKO  — 75 200 ns (Note 1) 12 TCKR CLKO Rise Time — 15 30 ns (Note 1) 13 TCKF CLKO Fall Time — 15 30 ns (Note 1) 14 TCKL2IOV CLKO  to Port Out Valid — — 0.5 TCY + 20 ns 15 TIOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns 16 TCKH2IOI Port In Hold after CLKO  0 — — ns 17 TOSH2IOV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1  (Q2 cycle) to Port Input Invalid 100 — — ns (I/O in hold time) 19 TIOV2OSH Port Input Valid to OSC1  0 — — ns (I/O in setup time) 20 TIOR Port Output Rise Time — 10 25 ns 21 TIOF Port Output Fall Time — 10 25 ns 22† TINP INTx pin High or Low Time 20 — — ns 23† TRBP RB<7:4> Change INTx High or Low TCY — — ns Time † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC. DS30009960F-page 494  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 31-6: PROGRAM MEMORY FETCH TIMING DIAGRAM (8-BIT) Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:8> Address Address 167 166 150 161 151 AD<7:0> Address Data Data Address 162 153 162A 155 154 163 BA0 170 ALE 170A 168 CE OE Note: Fmax = 25 MHz in 8-Bit External Memory mode. TABLE 31-11: PROGRAM MEMORY FETCH TIMING REQUIREMENTS (8-BIT) Param Symbol Characteristics Min Typ Max Units No 150 TadV2aIL Address Out Valid to ALE  (address setup time) 0.25 TCY – 10 — — ns 151 TaIL2adl ALE  to Address Out Invalid (address hold time) 5 — — ns 153 BA01 BA0  to Most Significant Data Valid 0.125 TCY — — ns 154 BA02 BA0  to Least Significant Data Valid 0.125 TCY — — ns 155 TaIL2oeL ALE  to OE  0.125 TCY — — ns 161 ToeH2adD OE  to A/D Driven 0.125 TCY – 5 — — ns 162 TadV2oeH Least Significant Data Valid Before OE  20 — — ns (data setup time) 162A TadV2oeH Most Significant Data Valid Before OE  0.25 TCY + 20 — — ns (data setup time) 163 ToeH2adI OE  to Data in Invalid (data hold time) 0 — — ns 166 TaIH2aIH ALE  to ALE  (cycle time) — TCY — ns 167 TACC Address Valid to Data Valid 0.5 TCY – 10 — — ns 168 Toe OE  to Data Valid — — 0.125 TCY + 5 ns 170 TubH2oeH BA0 = 0 Valid Before OE  0.25 TCY — — ns 170A TubL2oeH BA0 = 1 Valid Before OE  0.5 TCY — — ns  2009-2018 Microchip Technology Inc. DS30009960F-page 495

PIC18F87K22 FAMILY FIGURE 31-7: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 AD<15:0> Address Data from External Address 150 160 163 151 162 161 155 166 167 168 ALE 164 169 171 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated. TABLE 31-12: CLKO AND I/O TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE  0.25 TCY – 10 — — ns (address setup time) 151 TalL2adl ALE  to Address Out Invalid 5 — — ns (address hold time) 155 TalL2oeL ALE to OE  10 0.125 TCY — ns 160 TadZ2oeL AD High-Z to OE (bus release to OE) 0 — — ns 161 ToeH2adD OE  to AD Driven 0.125 TCY – 5 — — ns 162 TadV2oeH LS Data Valid before OE (data setup time) 20 — — ns 163 ToeH2adl OE  to Data In Invalid (data hold time) 0 — — ns 164 TalH2alL ALE Pulse Width — 0.25 TCY — ns 165 ToeL2oeH OE Pulse Width 0.5 TCY – 5 0.5 TCY — ns 166 TalH2alH ALE  to ALE  (cycle time) — TCY — ns 167 Tacc Address Valid to Data Valid 0.75 TCY – 25 — — ns 168 Toe OE  to Data Valid — 0.5 TCY – 25 ns 169 TalL2oeH ALE to OE  0.625 TCY – 10 — 0.625 TCY + 10 ns 171 TalH2csL Chip Enable Active to ALE  0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns DS30009960F-page 496  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 31-8: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 166 AD<15:0> Address Data Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157 157A UB or LB Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated. TABLE 31-13: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE (address setup time) 0.25 TCY – 10 — — ns 151 TalL2adl ALE  to Address Out Invalid (address hold time) 5 — — ns 153 TwrH2adl WRn  to Data Out Invalid (data hold time) 5 — — ns 154 TwrL WRn Pulse Width 0.5 TCY – 5 0.5 TCY — ns 156 TadV2wrH Data Valid before WRn (data setup time) 0.5 TCY – 10 — — ns 157 TbsV2wrL Byte Select Valid before WRn  0.25 TCY — — ns (byte select setup time) 157A TwrH2bsI WRn  to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 — — ns 166 TalH2alH ALE  to ALE  (cycle time) — TCY — ns 171 TalH2csL Chip Enable Active to ALE  0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns  2009-2018 Microchip Technology Inc. DS30009960F-page 497

PIC18F87K22 FAMILY FIGURE 31-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure31-3 for load conditions. FIGURE 31-10: BROWN-OUT RESET TIMING VDD BVDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 DS30009960F-page 498  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY TABLE 31-14: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — s 31 TWDT Watchdog Timer Time-out Period — 4.00 — ms (no postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period — 1 — ms 34 TIOZ I/O High-Impedance from MCLR — 2 — s Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — s VDD  BVDD (see D005) 36 TIRVST Time for Internal Reference — 25 — s Voltage to become Stable 37 THLVD High/Low-Voltage Detect Pulse Width 200 — — s VDD  VHLVD 38 TCSD CPU Start-up Time 5 — 10 s 39 TIOBST Time for INTOSC to Stabilize — 1 — s  2009-2018 Microchip Technology Inc. DS30009960F-page 499

PIC18F87K22 FAMILY FIGURE 31-11: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 31-15: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ Max Units Conditions No. D420 HLVD Voltage on VDD HLVDL<3:0> = 0000 1.69 1.84 1.99 V Transition High-to-Low HLVDL<3:0> = 0001 1.92 2.07 2.22 V HLVDL<3:0> = 0010 2.08 2.28 2.48 V HLVDL<3:0> = 0011 2.24 2.44 2.64 V HLVDL<3:0> = 0100 2.34 2.54 2.74 V HLVDL<3:0> = 0101 2.54 2.74 2.94 V HLVDL<3:0> = 0110 2.62 2.87 3.12 V HLVDL<3:0> = 0111 2.76 3.01 3.26 V HLVDL<3:0> = 1000 3.00 3.30 3.60 V HLVDL<3:0> = 1001 3.18 3.48 3.78 V HLVDL<3:0> = 1010 3.44 3.69 3.94 V HLVDL<3:0> = 1011 3.66 3.91 4.16 V HLVDL<3:0> = 1100 3.90 4.15 4.40 V HLVDL<3:0> = 1101 4.11 4.41 4.71 V HLVDL<3:0> = 1110 4.39 4.74 5.09 V HLVDL<3:0> = 1111 HLVDIN pin input V DS30009960F-page 500  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 31-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure31-3 for load conditions. TABLE 31-16: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 TT1H T1CKI High Synchronous, no prescaler 0.5 TCY + 20 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 46 TT1L T1CKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 47 TT1P T1CKI Input Synchronous Greater of: — ns N = prescale Period 20ns or value (TCY + 40)/N (1, 2, 4, 8) Asynchronous 60 — ns FT1 T1CKI Oscillator Input Frequency Range DC 50 kHz 48 TCKE2TMRI Delay from External T1CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment  2009-2018 Microchip Technology Inc. DS30009960F-page 501

PIC18F87K22 FAMILY FIGURE 31-13: CAPTURE/COMPARE/PWM TIMINGS (ECCP1, ECCP2 MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure31-3 for load conditions. TABLE 31-17: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP1, ECCP2 MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With prescaler 10 — ns 51 TCCH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With prescaler 10 — ns 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TCCR CCPx Output Fall Time — 25 ns 54 TCCF CCPx Output Fall Time — 25 ns DS30009960F-page 502  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 31-14: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SCKx (CKPx = 0) 78 79 SCKx (CKPx = 1) 79 78 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure31-3 for load conditions. TABLE 31-18: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns of Byte 2 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV  2009-2018 Microchip Technology Inc. DS30009960F-page 503

PIC18F87K22 FAMILY FIGURE 31-15: EXAMPLE SPI MASTER MODE TIMING (CKE=1) 81 SCKx (CKPx = 0) 79 73 SCKx (CKPx = 1) 80 78 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure31-3 for load conditions. TABLE 31-19: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns of Byte 2 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TCY — ns TDOV2SCL DS30009960F-page 504  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 31-16: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SSx 70 SCKx (CKPx = 0) 83 71 72 78 79 SCKx (CKP = 1) 79 78 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure31-3 for load conditions. TABLE 31-20: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx  to SCKx  or SCKx  Input 3 TCY — ns TSSL2SCL 70A TSSL2WB SSx to Write to SSPBUF 3 TCY — ns 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx  to SDOx Output High-Impedance 10 50 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 83 TSCH2SSH, SSx  after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used.  2009-2018 Microchip Technology Inc. DS30009960F-page 505

PIC18F87K22 FAMILY FIGURE 31-17: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SSx 70 SCKx 83 (CKPx = 0) 71 72 SCKx (CKPx = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure31-3 for load conditions. TABLE 31-21: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx  to SCKx  or SCKx  Input 3 TCY — ns TSSL2SCL 70A TSSL2WB SSx to Write to SSPBUF 3 TCY — ns 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx  to SDOx Output High-Impedance 10 50 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 82 TSSL2DOV SDOx Data Output Valid after SSx  Edge — 50 ns 83 TSCH2SSH, SSx  after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS30009960F-page 506  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 31-18: I2C BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure31-3 for load conditions. TABLE 31-22: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 —  2009-2018 Microchip Technology Inc. DS30009960F-page 507

PIC18F87K22 FAMILY FIGURE 31-19: I2C BUS DATA TIMING 103 100 102 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure31-3 for load conditions. TABLE 31-23: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s MSSP module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s MSSP module 1.5 TCY — 102 TR SDAx and SCLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDAx and SCLx Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — s Only relevant for Repeated 400 kHz mode 0.6 — s Start condition 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — s After this period, the first clock 400 kHz mode 0.6 — s pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before 400 kHz mode 1.3 — s a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS30009960F-page 508  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 31-20: MSSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure31-3 for load conditions. TABLE 31-24: MSSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins. FIGURE 31-21: MSSP I2C BUS DATA TIMING 103 100 102 101 SCLx 90 106 91 107 92 SDAx In 109 109 110 SDAx Out Note: Refer to Figure31-3 for load conditions.  2009-2018 Microchip Technology Inc. DS30009960F-page 509

PIC18F87K22 FAMILY TABLE 31-25: MSSP I2C BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High 100 kHz mode 2(TOSC)(BRG + 1) — — Time 400 kHz mode 2(TOSC)(BRG + 1) — — 1 MHz mode(1) 2(TOSC)(BRG + 1) — — 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — — 400 kHz mode 2(TOSC)(BRG + 1) — — 1 MHz mode(1) 2(TOSC)(BRG + 1) — — 102 TR SDAx and 100 kHz mode — 1000 ns CB is specified to be from SCLx Rise 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF Time 1 MHz mode(1) — 300 ns 103 TF SDAx and 100 kHz mode — 300 ns CB is specified to be from SCLx Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — — Only relevant for Repeated Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — — Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — — After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — — clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — — 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(1) — — ns 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) — — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — — Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — — 1 MHz mode(1) 2(TOSC)(BRG + 1) — — 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start 1 MHz mode(1) — — s D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but Parameter #107250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, Parameter #102 + Parameter #107=1000+250=1250ns (for 100 kHz mode), before the SCLx line is released. DS30009960F-page 510  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 31-22: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx Pin 121 121 RXx/DTx Pin 120 122 Note: Refer to Figure31-3 for load conditions. TABLE 31-26: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid — 40 ns 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns 122 TDTRF Data Out Rise Time and Fall Time — 20 ns FIGURE 31-23: EUSART/AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TXx/CKx Pin 125 RXx/DTx Pin 126 Note: Refer to Figure31-3 for load conditions. TABLE 31-27: EUSART/AUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CKx  (DTx hold time) 10 — ns 126 TCKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns  2009-2018 Microchip Technology Inc. DS30009960F-page 511

PIC18F87K22 FAMILY TABLE 31-28: A/D CONVERTER CHARACTERISTICS: PIC18F87K22 FAMILY (INDUSTRIAL) Param Sym Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 12 bit VREF  5.0V A03 EIL Integral Linearity Error — ±1 ±6.0 LSB VREF = 5.0V A04 EDL Differential Linearity Error — ±1 +3.0/-1.0 LSB VREF = 5.0V A06 EOFF Offset Error — ±1 ±18.0 LSB VREF = 5.0V A07 EGN Gain Error — ±1 ±8.0 LSB VREF = 5.0V A10 — Monotonicity(1) — — — — VSS  VAIN  VREF A20 VREF Reference Voltage Range 3 — VDD – VSS V (VREFH – VREFL) A21 VREFH Reference Voltage High VSS + 3.0V — VDD + 0.3V V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended — — 2.5 k Impedance of Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 A During VAIN acquisition — — 150 A During A/D conversion cycle Note 1: The A/D conversion result doesn’t decrease with an increase in the input voltage. 2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from the RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source. DS30009960F-page 512  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY FIGURE 31-24: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 A/D DATA 11 10 9 . . . . . . 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY (Note 1) GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 31-29: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period 0.8 12.5(1) µs TOSC-based, VREF  3.0V 1.4 25(1) µs VDD = 3.0V; TOSC-based, VREF full range — 1 µs A/D RC mode — 3 µs VDD = 3.0V; A/D RC mode 131 TCNV Conversion Time 14 15 TAD (not including acquisition time)(2) 132 TACQ Acquisition Time(3) 1.4 — µs -40°C to +125°C 135 TSWC Switching Time from Convert  Sample — (Note 4) 137 TDIS Discharge Time 0.2 — µs -40°C to +125°C Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. 4: On the following cycle of the device clock.  2009-2018 Microchip Technology Inc. DS30009960F-page 513

PIC18F87K22 FAMILY DS30009960F-page 514  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX 18F67K22 XXXXXXXXXX PTe3 XXXXXXXXXX 1110017 YYWWNNN 64-Lead QFN Example XXXXXXXXXX 18F67K22 XXXXXXXXXX MR e3 XXXXXXXXXX 1110017 YYWWNNN 80-Lead TQFP Example XXXXXXXXXXXX PIC18F87K22 XXXXXXXXXXXX PT e3 YYWWNNN 1110017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free.The Pb-free JEDEC® designator (e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2009-2018 Microchip Technology Inc. DS30009960F-page 515

PIC18F87K22 FAMILY 32.2 Package Details The following sections give the technical details of the packages. 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(cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)@/1 DS30009960F-page 516  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2018 Microchip Technology Inc. DS30009960F-page 517

PIC18F87K22 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009960F-page 518  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2018 Microchip Technology Inc. DS30009960F-page 519

PIC18F87K22 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009960F-page 520  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY )(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 E e E1 b N NOTE1 123 NOTE2 α A c φ β A1 A2 L L1 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 @(cid:4) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)/(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)(cid:6)(cid:17)1  2009-2018 Microchip Technology Inc. DS30009960F-page 521

PIC18F87K22 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009960F-page 522  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY APPENDIX A: REVISION HISTORY Revision F (December 2018) Updated Sections 2.4 and 31.3. Updated Tables 31-27 and 32-2. Updated the Product Identification System section. Added Section 3.6.5: LFINTOSC Operation in Sleep. Added Section 31.5: DC Characteristics: Injection Current (Industrial Only). Revision E (April 2018) Updated Section3.9 “Power-up Delays”, Section5.0 “Reset”, and Section5.6 “Power-up Timer (PWRT)”. Updated Power-up Timer Period (TPWRT) from Table31-14. Other minor corrections. Revision D (June 2011) Updated Section31.2 “DC Characteristics: Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended)” and Table31-9 with new electrical specification information. The extended temperature information has been included in this revision. Revision C (March 2011) Section2.4 “Voltage Regulator Pins (ENVREG and VCAP/VDDCORE)” has been replaced with a new and more detailed description and the 80-pin TQFP diagrams have been updated. Minor text edits throughout document. Revision B (May 2010) Minor edits to text throughout document. Replaced all TBDs with the correct value. Revision A (November 2009) Original data sheet for PIC18F87K22 family devices.  2009-2018 Microchip Technology Inc. DS30009960F-page 523

PIC18F87K22 FAMILY APPENDIX B: MIGRATION FROM PIC18F87J11 AND PIC18F8722 TO PIC18F87K22 Devices in the PIC18F87K22, PIC18F87J11 and PIC18F8722 families are similar in their functions and features. Code can be migrated from the other families to the PIC18F87K22 without many changes. The differ- ences between the device families are listed in TableB-1. TABLE B-1: NOTABLE DIFFERENCES BETWEEN PIC18F87K22, PIC18F87J11 AND PIC18F8722 FAMILIES Characteristic PIC18F87K22 Family 18F87J11 Family PIC18F8722 Family Max Operating Frequency 64MHz 48 MHz 40 MHz Max Program Memory 128 Kbytes 128 Kbytes 128 Kbytes Data Memory 3,862 bytes 3,930 bytes 3,930 bytes Program Memory 10,000 Write/Erase (minimum) 10,000 Write/Erase (minimum) 10,000 Write/Erase (minimum) Endurance Single Word Write for Flash No Yes No Oscillator Options PLL can be used with INTOSC PLL can be used with INTOSC PLL can be used with INTOSC CTMU Yes No No RTCC Yes No No SOSC Oscillator Options Low-Power Oscillator Option for No No SOSC TICKI Clock T1CKI can be used as a Clock without Enabling the SOSC Oscillator INTOSC Up to 16 MHz Up to 8 MHz Up to 8 MHz SPI/I2C 2 2 2 Timers 11 5 5 ECCP 3 3 CCP 7 2 2 Data EEPROM Yes No Yes Programmable BOR Multiple Level BOR One Level BOR Multiple Level BOR WDT Prescale Options 22 16 16 5V Operation Yes No (3.3V) Yes XLP Yes No No Regulator Yes Yes No Low-Power BOR Yes No No A/D Converter 12-Bit Resolution, 24 Input 10-Bit Resolution, 15 Input 10-Bit Resolution, 16 Input Channels, Differential Channels, Non-Differential Channels, Non-Differential Internal Temperature Sensor Yes No No Programmable HLVD Yes No Yes EUSART 2 EUSARTs 2 EUSARTs 2 EUSARTs Comparators 3 2 2 Oscillator options 14 Options by FOSC<3:0> 8 Options by FOSC<3:0> 12 Options by FOSC<3:0> Ultra-Low-Power Wake-up Yes No No (ULPW) Power-up Timer Yes Yes Yes MCLR Pin as Input Port Yes No Yes DS30009960F-page 524  2009-2018 Microchip Technology Inc.

DEVICE FAMILY THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Product Support – Data sheets and errata, • Technical Support application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or Field Application Engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the website program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2009-2018 Microchip Technology Inc. DS30009960F-page 525

DEVICE FAMILY NOTES: DS30009960F-page 526  2009-2018 Microchip Technology Inc.

PIC18F87K22 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC18F87K22-I/PT 301 = Industrial temperature, Option Range TQFP package, QTP pattern #301. b) PIC18F87K22T-I/PT = Tape and reel, Industrial temperature, TQFP package c) PIC18F87K22T-E/PT = Tape and reel, Device: PIC18F65K22, PIC18F65K22T Extended temperature, TQFP package PIC18F66K22, PIC18F66K22T PIC18F67K22, PIC18F67K22T PIC18F85K22, PIC18F85K22T PIC18F86K22, PIC18F86K22T PIC18F87K22, PIC18F87K22T Tape and Reel Blank = Standard packaging (tube or tray) Option: T = Tape and Reel(1) Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Note1: Tape and Reel identifier only appears in the catalog part number description. This identi- fier is used for ordering purposes and is nto Package: PT = TQFP (Thin Quad Flatpack) printed on the device package. Check with MR = QFN (Plastic Quad Flat) your Microchip Sales Office for package availability with the Tape and Reel option. 2: F = Standard Voltage Range Pattern: QTP, SQTP, Code or Special Requirements 3: T = In tape and reel PLCC and TQFP (blank otherwise) packages only 4: RSL = Silicon Revision A3.  2009-2018 Microchip Technology Inc. DS30009960F-page 527

PIC18F87K22 FAMILY DS30009960F-page 528  2009-2018 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR, and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, ensure that your application meets with your specifications. CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, MICROCHIP MAKES NO REPRESENTATIONS OR JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries. arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company, devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A. suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Microchip received ISO/TS-16949:2009 certification for its worldwide SQTP is a service mark of Microchip Technology Incorporated in headquarters, design and wafer fabrication facilities in Chandler and the U.S.A. Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures Silicon Storage Technology is a registered trademark of Microchip are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping Technology Inc. in other countries. devices, Serial EEPROMs, microperipherals, nonvolatile memory and GestIC is a registered trademark of Microchip Technology analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their QUALITY MANAGEMENT SYSTEM respective companies. © 2018, Microchip Technology Incorporated, All Rights Reserved. CERTIFIED BY DNV ISBN: 978-1-5224-3984-4 == ISO/TS 16949 ==  2009-2018 Microchip Technology Inc. DS30009960F-page 529

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