PIC18F2XK20/4XK20 28/40/44-Pin Flash Microcontrollers with XLP Technology High-Performance RISC CPU Extreme Low-Power Management with XLP • C Compiler Optimized Architecture: - Optional extended instruction set designed to • Sleep Mode: < 100 nA @ 1.8V optimize re-entrant code • Watchdog Timer: < 800 nA @ 1.8V • Up to 1024 bytes Data EEPROM • Timer1 Oscillator: < 800 nA @ 32 kHz and 1.8V • Up to 64Kbytes Linear Program Memory Addressing Analog Features • Up to 3936 bytes Linear Data Memory Addressing • Analog-to-Digital Converter (ADC) Module: • Up to 16 MIPS Operation • 16-bit Wide Instructions, 8-bit Wide Data Path - 10-bit resolution, 13 External Channels • Priority Levels for Interrupts - Auto-acquisition capability • 31-Level, Software Accessible Hardware Stack - Conversion available during Sleep • 8 x 8 Single-Cycle Hardware Multiplier - 1.2V Fixed Voltage Reference (FVR) channel Flexible Oscillator Structure - Independent input multiplexing • Analog Comparator Module: • Precision 16MHz Internal Oscillator Block: - Two rail-to-rail analog comparators - Factory calibrated to ± 1% - Independent input multiplexing - Software selectable frequencies range of 31kHz to 16MHz • Voltage Reference (CVREF) Module - 64MHz performance available using PLL – - Programmable (% VDD), 16 steps no external components required - Two 16-level voltage ranges using VREF pins • Four Crystal Modes up to 64MHz Peripheral Highlights • Two External Clock Modes up to 64MHz • 4X Phase Lock Loop (PLL) • Up to 35 I/O Pins plus 1 Input-only Pin: • Secondary Oscillator using Timer1 @ 32kHz - High-Current Sink/Source 25mA/25mA • Fail-Safe Clock Monitor: - Three programmable external interrupts - Allows for safe shutdown, if peripheral clock - Four programmable interrupt-on-change stops - Eight programmable weak pull-ups - Two-Speed Oscillator Start-up - Programmable slew rate • Capture/Compare/PWM (CCP) Module Special Microcontroller Features • Enhanced CCP (ECCP) module: • Operating Voltage Range: 1.8V to 3.6V - One, two or four PWM outputs • Self-Programmable under Software Control - Selectable polarity • Programmable 16-Level High/Low-Voltage - Programmable dead time Detection (HLVD) module: - Auto-shutdown and auto-restart - Interrupt on High/Low-Voltage Detection • Master Synchronous Serial Port (MSSP) Module • Programmable Brown-out Reset (BOR): - 3-wire SPI (supports all four modes) - With software enable option - I2C™ Master and Slave modes with address • Extended Watchdog Timer (WDT): mask - Programmable period from 4ms to 131s • Enhanced Universal Synchronous Asynchronous • Single-Supply 3V In-Circuit Serial Receiver Transmitter (EUSART) Module: Programming™ (ICSP™) via Two Pins - Supports RS-485, RS-232 and LIN • In-Circuit Debug (ICD) via Two Pins - RS-232 operation using internal oscillator - Auto-Wake-up on Break - Auto-Baud Detect  2010-2015 Microchip Technology Inc. DS40001303H-page 1

PIC18F2XK20/4XK20 -PIC18F2XK20/4XK20 Family Types Device (FblyaPtserohsg)ra#mI nS sMintergumlceo-tiWroynosrd ( SbyRDtAaetsMa) MEe(EmbPyoRtreyOs)M I/O(1) (1cA0h-/)bD(2i t) (EPCCWCCPMP/) SPIMSSMIP2aCs™ter EUSART Comp. 8T/i1m6e-brsit PIC18F23K20 8K 4096 512 256 25 11 1/1 Y Y 1 2 1/3 PIC18F24K20 16K 8192 768 256 25 11 1/1 Y Y 1 2 1/3 PIC18F25K20 32K 16384 1536 256 25 11 1/1 Y Y 1 2 1/3 PIC18F26K20 64k 32768 3936 1024 25 11 1/1 Y Y 1 2 1/3 PIC18F43K20 8K 4096 512 256 36 14 1/1 Y Y 1 2 1/3 PIC18F44K20 16K 8192 768 256 36 14 1/1 Y Y 1 2 1/3 PIC18F45K20 32K 16384 1536 256 36 14 1/1 Y Y 1 2 1/3 PIC18F46K20 64k 32768 3936 1024 36 14 1/1 Y Y 1 2 1/3 Note 1: One pin is input-only. 2: Channel count includes internal Fixed Voltage Reference channel. Note: For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. DS40001303H-page 2  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 Pin Diagrams FIGURE 1: 28-PIN SPDIP, SOIC, SSOP MCLR/VPP/RE3 1 28 RB7/KBI3/PGD AN0/C12IN0-/RA0 2 27 RB6//KBI2/PGC AN1/C12IN1-/RA1 3 26 RB5/KBI1/PGM AN2/VREF-/CVREF/C2IN+/RA2 4 25 RB4/KBI0/AN11/P1D AN3/VREF+/C1IN+/RA3 5 24 RB3/AN9/C12IN2-/CCP2(1) 0000 T0CKI/C1OUT/RA4 6 K2K2K2K2 23 RB2/INT2/AN8/P1B AN4/SS/HLVDIN/C2OUT/RA5 7 23242526 22 RB1/INT1/AN10/C12IN3-/P1C VSS 8 8F8F8F8F 21 RB0/INT0/FLT0/AN12 OSC1/CLKIN/RA7 9 C1C1C1C1 20 VDD OSC2/CLKOUT/RA6 10 PIPIPIPI 19 VSS T1OSO/T13CKI/RC0 11 18 RC7/RX/DT T1OSI/CCP2(1)/RC1 12 17 RC6/TX/CK CCP1/P1A/RC2 13 16 RC5/SDO SCK/SCL/RC3 14 15 RC4/SDI/SDA Note: See Table1 for pin allocation table. FIGURE 2: 28-PIN QFN/UQFN D 1 N1/C12IN1-N0/C12IN0- CLR/VPPBI3/PGDBI2/PGCBI1/PGMBI0/AN11/P AA MKKKK 1/0/ 3/7/6/5/4/ AA EBBBB RR RRRRR 28272625242322 AN2/VREF-/CVREF/C2IN+/RA2 1 21 RB3/AN9/C12IN2-/CCP2(1) AN3/VREF+/C1IN+/RA3 2 PIC18F23K20 20 RB2/INT2/AN8/P1B T0CKI/C1OUT/RA4 3 PIC18F24K20 19 RB1/INT1/AN10/C12IN3-/P1C AN4/SS/HLVDIN/C2OUT/RA5 4 PIC18F25K20 18 RB0/INT0/FLT0/AN12 VSS 5 PIC18F26K20 17 VDD OSC1/CLKIN/RA7 6 16 VSS OSC2/CLKOUT/RA6 7 15 RC7/RX/DT 8 91011121314 0123456 CCCCCCC RRRRRRR SO/T13CKI/(1)SI/CCP2/CCP1/P1A/SCK/SCL/SDI/SDA/SDO/TX/CK/ OO T1T1 Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: UQFN package availability applies only to PIC18F23K20. 3: See Table1 for pin allocation table. 4: The exposed pad should be connected to VSS.  2010-2015 Microchip Technology Inc. DS40001303H-page 3

PIC18F2XK20/4XK20 FIGURE 3: 40-PIN PDIP MCLR/VPP/RE3 1 40 RB7/KBI3/PGD AN0/C12IN0-/RA0 2 39 RB6/KBI2/PGC AN1/C12IN1-/RA1 3 38 RB5/KBI1/PGM AN2/VREF-/CVREF/C2IN+/RA2 4 37 RB4/KBI0/AN11 AN3/VREF+/C1IN+/RA3 5 36 RB3/AN9/C12IN2-/CCP2(1) T0CKI/C1OUT/RA4 6 35 RB2/INT2/AN8 AN4/SS/HLVDIN/C2OUT/RA5 7 34 RB1/INT1/AN10/C12IN3- RD/AN5/RE0 8 0000 33 RB0/INT0/FLT0/AN12 WR/AN6/RE1 9 K2K2K2K2 32 VDD CS/AN7/RE2 10 43444546 31 VSS FFFF VDD 11 8888 30 RD7/PSP7/P1D 1111 VSS 12 CCCC 29 RD6/PSP6/P1C OSC1/CLKIN/RA7 13 PIPIPIPI 28 RD5/PSP5/P1B OSC2/CLKOUT/RA6 14 27 RD4/PSP4 T1OSO/T13CKI/RC0 15 26 RC7/RX/DT T1OSI/CCP2(1)/RC1 16 25 RC6/TX/CK CCP1/P1A/RC2 17 24 RC5/SDO SCK/SCL/RC3 18 23 RC4/SDI/SDA PSP0/RD0 19 22 RD3/PSP3 PSP1/RD1 20 21 RD2/PSP2 Note: See Table2 for pin allocation table. FIGURE 4: 40-PIN UQFN 2 P X/Ck DO DI/SDA SP3 SP2 SP1 SP0 CK/SCL CP1/P1A 1OSI/CC T S S P P P P S C T 6/ 5/ 4/ 3/ 2/ 1/ 0/ 3/ 2/ 1/ C C C D D D D C C C R R R R R R R R R R 40 39 38 37 36 35 34 33 32 31 RX/DT/RC7 1 RD4/PSP4/RD4 2 30 RC0/T1OSO/T13CKI PSP5/P1B/RD5 3 29 RA6/OSC2/CLKOUT RD6/PSP6/P1C/RD6 4 28 RA7/OSC1/CLKIN PSP7/P1D/RD7 5 27 VSS VSS 6 PIC18F4XK20 26 VDD VDD 7 25 RE2/CS/AN7 INT0/FLT0/AN12/RB0 8 24 RE1/WR/AN6 INT1/AN10/C12IN3-/RB1 9 23 RE0/RD/AN5 INT2/AN8/RB2 10 22 RA5/AN4/SS/HLVDIN/C2OUT 21 RA4/T0CKI/C1OUT 11 12 13 14 15 16 1718 1920 B3 B4 B5 B6 B7 E3 A0 A1 A2 A3 R R R R R R R R R R AN9/C12IN2-/CCP/ KBI0/AN11/ KBI1/PGM/ KBI2/PGC/ KBI3/PGD/ MCLR/V/PP AN0/C12IN0-/ AN1/C12/IN1-/ -/CV/C2IN+/REFREF AN3/V+/C1IN+/REF V 2/ N A Note 1: See Table2 for location of all peripheral functions. 2: It is recommended that the exposed bottom pad be connected to VSS. DS40001303H-page 4  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 5: 44-PIN QFN (1)2CKI TX/CKSDOSDI/SDAPSP3PSP2PSP1PSP0SCK/SCLCCP1/P1AT1OSI/CCPT1OSO/T13 6/5/4/3/2/1/0/3/2/1/0/ CCCDDDDCCCC RRRRRRRRRRR 43210987654 44444333333 RX/DT/RC7 1 33 RA6/OSC2/CLKOUT RD4/PSP4/RD4 2 32 RA7/OSC1/CLKIN PSP5/P1B/RD5 3 31 VSS PSP6/P1C/RD6 4 PIC18F43K20 30 VSS PSP7/P1D/RD7 5 PIC18F44K20 29 VDD VSS 6 PIC18F45K20 28 VDD VDD 7 PIC18F46K20 27 RE2/CS/AN7 VDD 8 26 RE1/WR/AN6 INT0/FLT0/AN12/RB0 9 25 RE0/RD/AN5 INT1/AN10/C12IN3-/RB1 10 24 RA5/AN4/SS/HLVDIN/C2OUT INT2/AN8/RB2 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 3C456730123 BNBBBBEAAAA R RRRRRRRRR (1)12IN2-/CCP2/ KBI0/AN11/KBI1/PGM/KBI2/PGC/KBI3/PGD/MCLR/V/PPAN0/C12IN0-/AN1/C12IN1-/-/CV/C2IN+/FREF3/V+/C1IN+/REF 9/C VREAN N 2/ A N A Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: The exposed pad should be connected to VSS. 3: See Table2 for pin allocation table. FIGURE 6: 44-PIN TQFP 1) (2 TX/CKSDOSDI/SDAPSP3PSP2PSP1PSP0SCK/SCLCCP1/P1AT1OSI/CCP 6/5/4/3/2/1/0/3/2/1/ CCCDDDDCCCC RRRRRRRRRRN 43210987654 44444333333 RX/DT/RC7 1 33 NC PSP4/RD4 2 32 RC0/T1OSO/T13CKI PSP5/P1B/RD5 3 31 RA6/OSC2/CLKOUT PSP6/P1C/RD6 4 PIC18F43K20 30 RA7/OSC1/CLKIN PSP7/P1D/RD7 5 PIC18F44K20 29 VSS VSS 6 PIC18F45K20 28 VDD VDD 7 PIC18F46K20 27 RE2/CS/AN7 INT0/FLT0/AN12/RB0 8 26 RE1/WR/AN6 INT1/AN10/C12IN3-/RB1 9 25 RE0/RD/AN5 INT2/AN8/RB2 10 24 RA5/AN4/SS/HLVDIN/C2OUT AN9/C12IN2-/CCP2(1)/RB3 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 CC456730123 NNBBBBEAAAA RRRRRRRRR KBI0/AN11/KBI1/PGM/KBI2/PGC/KBI3/PGD/MCLR/V/PPAN0/C12IN0-/AN1/C12IN1-/CV/C2IN+/REFV+/C1IN+/REF -/EFN3/ RA V 2/ N A Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: See Table2 for pin allocation table.  2010-2015 Microchip Technology Inc. DS40001303H-page 5

PIC18F2XK20/4XK20 Pin Allocation Tables TABLE 1: 28-PIN ALLOCATION TABLE (PIC18F2XK20) P O S S N C, QF r I/O SPDIP, SOI Pin QFN/U Analog Comparato Reference ECCP EUSART MSSP Timers Slave Interrupts Pull-up Basic n 8- Pi 2 8- 2 RA0 2 27 AN0 C12IN0- — — — — — — — — — RA1 3 28 AN1 C12IN1- — — — — — — — — — RA2 4 1 AN2 C2IN+ VREF-/ — — — — — — — — CVREF RA3 5 2 AN3 C1IN+ VREF+ — — — — — — — — RA4 6 3 — C1OUT — — — — T0CKI — — — — RA5 7 4 AN4 C2OUT HLVDIN — — SS — — — — — RA6 10 7 — — — — — — — — — — OSC2/ CLKOUT RA7 9 6 — — — — — — — — — — OSC1/ CLKIN RB0 21 18 AN12 — — FLT0 — — — — INT0 Yes — RB1 22 19 AN10 C12IN3- — P1C — — — — INT1 Yes — RB2 23 20 AN8 — — P1B — — — — INT2 Yes — RB3 24 21 AN9 C12IN2- CCP2(1) — — — — — Yes — RB4 25 22 AN11 — — P1D — — — — KBI0 Yes — RB5 26 23 — — — — — — — — KBI1 Yes PGM RB6 27 24 — — — — — — — — KBI2 Yes PGC RB7 28 25 — — — — — — — — KBI3 Yes PGD RC0 11 8 — — — — — — T1OSO/ — — — — T13CKI RC1 12 9 — — — CCP2(2) — — T1OSI — — — — RC2 13 10 — — — CCP1/ — — — — — — — P1A RC3 14 11 — — — — — SCK/ — — — — — SCL RC4 15 12 — — — — — SDI/ — — — — — SDA RC5 16 13 — — — — — SDO — — — — — RC6 17 14 — — — — TX/CK — — — — — — RC7 18 15 — — — — RX/DT — — — — — — RE3(3) 1 26 — — — — — — — — — — MCLR/ VPP 8 5 — — — — — — — — — — VSS 19 16 — — — — — — — — — — VSS 20 17 — — — — — — — — — — VDD Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0 2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1 3: Input-only DS40001303H-page 6  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC18F4XK20) I/O 40-Pin PDIP 40-Pin UQFN 44-Pin TQFP 44-Pin QFN Analog Comp. Reference ECCP EUSART MSSP Timers Slave Interrupts Pull-up Basic RA0 2 17 19 19 AN0 C12IN0 — — — — — — — — — - RA1 3 18 20 20 AN1 C12IN1 — — — — — — — — — - RA2 4 19 21 21 AN2 C2IN+ VREF-/ — — — — — — — — CVREF RA3 5 20 22 22 AN3 C1IN+ VREF+ — — — — — — — — RA4 6 21 23 23 — C1OUT — — — — T0CKI — — — — RA5 7 22 24 24 AN4 C2OUT HLVDIN — — SS — — — — — RA6 14 29 31 33 — — — — — — — — — — OSC2/ CLKOUT RA7 13 28 30 32 — — — — — — — — — — OSC1/ CLKIN RB0 33 8 8 9 AN12 — — FLT0 — — — — INT0 Yes — RB1 34 9 9 10 AN10 C12IN3 — — — — — — INT1 Yes — - RB2 35 10 10 11 AN8 — — — — — — — INT2 Yes — RB3 36 11 11 12 AN9 C12IN2 — CCP2(1) — — — — — Yes — - RB4 37 12 14 14 AN11 — — — — — — — KBI0 Yes — RB5 38 13 15 15 — — — — — — — — KBI1 Yes PGM RB6 39 14 16 16 — — — — — — — — KBI2 Yes PGC RB7 40 15 17 17 — — — — — — — — KBI3 Yes PGD RC0 15 30 32 34 — — — — — — T1OSO/ — — — — T13CKI RC1 16 31 35 35 — — — CCP2(2) — — T1OSI — — — — RC2 17 32 36 36 — — — CCP1/ — — — — — — — P1A RC3 18 33 37 37 — — — — — SCK/ — — — — — SCL RC4 23 38 42 42 — — — — — SDI/ — — — — — SDA RC5 24 39 43 43 — — — — — SDO — — — — — RC6 25 40 44 44 — — — — TX/ — — — — — — CK RC7 26 1 1 1 — — — — RX/ — — — — — — DT RD0 19 34 38 38 — — — — — — — PSP0 — — — RD1 20 35 39 39 — — — — — — — PSP1 — — — RD2 21 36 40 40 — — — — — — — PSP2 — — — RD3 22 37 41 41 — — — — — — — PSP3 — — — RD4 27 2 2 2 — — — — — — — PSP4 — — — RD5 28 3 3 3 — — — P1B — — — PSP5 — — — RD6 29 4 4 4 — — — P1C — — — PSP6 — — — Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0 2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1 3: Input-only.  2010-2015 Microchip Technology Inc. DS40001303H-page 7

PIC18F2XK20/4XK20 TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC18F4XK20) (CONTINUED) I/O 40-Pin PDIP 40-Pin UQFN 44-Pin TQFP 44-Pin QFN Analog Comp. Reference ECCP EUSART MSSP Timers Slave Interrupts Pull-up Basic RD7 30 5 5 5 — — — P1D — — — PSP7 — — — RE0 8 23 25 25 AN5 — — — — — — RD — — — RE1 9 24 26 26 AN6 — — — — — — WR — — — RE2 10 25 27 27 AN7 — — — — — — CS — — — RE3(3) 1 16 18 18 — — — — — — — — — — MCLR/VPP — 11 7 7 7 — — — — — — — — — — VDD — 32 26 28 28 — — — — — — — — — — VDD — 12 6 6 6 — — — — — — — — — — VSS — 31 27 29 30 — — — — — — — — — — VSS — – — NC 8 — — — — — — — — — — VDD — – — NC 29 — — — — — — — — — — VDD — –- — NC 31 — — — — — — — — — — VSS Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0 2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1 3: Input-only. DS40001303H-page 8  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 Table of Contents 1.0 Device Overview....................................................................................................................................................................... 11 2.0 Oscillator Module (With Fail-Safe Clock Monitor)...................................................................................................................... 26 3.0 Power-Managed Modes............................................................................................................................................................ 41 4.0 Reset......................................................................................................................................................................................... 48 5.0 Memory Organization................................................................................................................................................................ 61 6.0 Flash Program Memory............................................................................................................................................................. 84 7.0 Data EEPROM Memory............................................................................................................................................................ 93 8.0 8 x 8 Hardware Multiplier........................................................................................................................................................... 98 9.0 Interrupts................................................................................................................................................................................. 100 10.0 I/O Ports.................................................................................................................................................................................. 113 11.0 Capture/Compare/PWM (CCP) Modules................................................................................................................................ 134 12.0 Timer0 Module........................................................................................................................................................................ 145 13.0 Timer1 Module........................................................................................................................................................................ 148 14.0 Timer2 Module........................................................................................................................................................................ 155 15.0 Timer3 Module........................................................................................................................................................................ 157 16.0 Enhanced Capture/Compare/PWM (ECCP) Module............................................................................................................... 161 17.0 Master Synchronous Serial Port (MSSP) Module................................................................................................................... 179 18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART).............................................................. 222 19.0 Analog-to-Digital Converter (ADC) Module............................................................................................................................. 249 20.0 Comparator Module................................................................................................................................................................. 262 21.0 Voltage References................................................................................................................................................................. 272 22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................ 276 23.0 Special Features of the CPU................................................................................................................................................... 281 24.0 Instruction Set Summary......................................................................................................................................................... 296 25.0 Development Support.............................................................................................................................................................. 346 26.0 Electrical Characteristics......................................................................................................................................................... 350 27.0 DC and AC Characteristics Graphs and Tables...................................................................................................................... 387 28.0 Packaging Information............................................................................................................................................................. 410 Appendix A: Revision History............................................................................................................................................................ 435 Appendix B: Device Differences....................................................................................................................................................... 436 The Microchip Web Site.................................................................................................................................................................... 437 Customer Change Notification Service............................................................................................................................................. 437 Customer Support............................................................................................................................................................................. 437 Product Identification System........................................................................................................................................................... 438  2010-2015 Microchip Technology Inc. DS40001303H-page 9

PIC18F2XK20/4XK20 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS40001303H-page 10  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 1.0 DEVICE OVERVIEW 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES This document contains device specific information for the following devices: All of the devices in the PIC18F2XK20/4XK20 family offer ten different oscillator options, allowing users a • PIC18F23K20 • PIC18F43K20 wide range of choices in developing application • PIC18F24K20 • PIC18F44K20 hardware. These include: • PIC18F25K20 • PIC18F45K20 • Four Crystal modes, using crystals or ceramic resonators • PIC18F26K20 • PIC18F46K20 • Two External Clock modes, offering the option of This family offers the advantages of all PIC18 using two pins (oscillator input and a divide-by-4 microcontrollers – namely, high computational clock output) or one pin (oscillator input, with the performance at an economical price – with the addition second pin reassigned as general I/O) of high-endurance, Flash program memory. On top of • Two External RC Oscillator modes with the same these features, the PIC18F2XK20/4XK20 family pin options as the External Clock modes introduces design enhancements that make these microcontrollers a logical choice for many • An internal oscillator block which contains a high-performance, power sensitive applications. 16MHz HFINTOSC oscillator and a 31kHz LFINTOSC oscillator which together provide 8 1.1 New Core Features user selectable clock frequencies, from 31kHz to 16MHz. This option frees the two oscillator pins 1.1.1 XLP TECHNOLOGY for use as additional general purpose I/O. All of the devices in the PIC18F2XK20/4XK20 family • A Phase Lock Loop (PLL) frequency multiplier, incorporate a range of features that can significantly available to both the high-speed crystal and inter- reduce power consumption during operation. Key nal oscillator modes, which allows clock speeds of items include: up to 64MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock • Alternate Run Modes: By clocking the controller speeds, from 31kHz to 64MHz – all without using from the Timer1 source or the internal oscillator an external crystal or clock circuit. block, power consumption during code execution can be reduced by as much as 90%. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that • Multiple Idle Modes: The controller can also run gives the family additional features for robust with its CPU core disabled but the peripherals still operation: active. In these states, power consumption can be reduced even further, to as little as 4% of normal • Fail-Safe Clock Monitor: This option constantly operation requirements. monitors the main clock source against a • On-the-fly Mode Switching: The power- reference signal provided by the LFINTOSC. If a managed modes are invoked by user code during clock failure occurs, the controller is switched to operation, allowing the user to incorporate the internal oscillator block, allowing for continued power-saving ideas into their application’s operation or a safe application shutdown. software design. • Two-Speed Start-up: This option allows the • Low Consumption in Key Modules: The internal oscillator to serve as the clock source power requirements for both Timer1 and the from Power-on Reset, or wake-up from Sleep Watchdog Timer are minimized. See mode, until the primary clock source is available. Section26.0 “Electrical Specifications” for values.  2010-2015 Microchip Technology Inc. DS40001303H-page 11

PIC18F2XK20/4XK20 1.2 Other Special Features 1.3 Details on Individual Family Members • Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to Devices in the PIC18F2XK20/4XK20 family are last for many thousands of erase/write cycles – up to available in 28-pin and 40/44-pin packages. Block 10K for program memory and 100K for EEPROM. diagrams for the two groups are shown in Figure1-1 Data retention without refresh is conservatively and Figure1-2. estimated to be greater than 40 years. The devices are differentiated from each other in five • Self-programmability: These devices can write ways: to their own program memory spaces under 1. Flash program memory (8Kbytes for internal software control. By using a bootloader routine located in the protected Boot Block at the PIC18F23K20/43K20 devices, 16Kbytes for top of program memory, it becomes possible to PIC18F24K20/44K20 devices, 32Kbytes for create an application that can update itself in the PIC18F25K20/45K20 AND 64Kbytes for field. PIC18F26K20/46K20). • Extended Instruction Set: The PIC18F2XK20/ 2. A/D channels (11 for 28-pin devices, 14 for 40/44-pin devices). 4XK20 family introduces an optional extension to the PIC18 instruction set, which adds eight new 3. I/O ports (three bidirectional ports on 28-pin instructions and an Indexed Addressing mode. devices, five bidirectional ports on 40/44-pin This extension, enabled as a device configuration devices). option, has been specifically designed to optimize 4. Parallel Slave Port (present only on 40/44-pin re-entrant application code originally developed in devices). high-level languages, such as C. All other features for devices in this family are identical. • Enhanced CCP module: In PWM mode, this These are summarized in Table1-1. module provides 1, 2 or 4 modulated outputs for The pinouts for all devices are listed in the pin summary controlling half-bridge and full-bridge drivers. tables: Table and Table, and I/O description tables: Other features include: Table1-2 and Table1-3. - Auto-Shutdown, for disabling PWM outputs on interrupt or other select conditions - Auto-Restart, to reactivate outputs once the condition has cleared - Output steering to selectively enable one or more of four outputs to provide the PWM signal. • Enhanced Addressable EUSART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit postscaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section26.0 “Electrical Specifications” for time-out periods. DS40001303H-page 12  2010-2015 Microchip Technology Inc.

 TABLE 1-1: DEVICE FEATURES 2 0 1 Features PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K20 0 -2 0 Operating Frequency(2) DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz DC – 64 MHz 1 5 M Program Memory (Bytes) 8192 16384 32768 65536 8192 16384 32768 65536 ic Program Memory 4096 8192 16384 32768 4096 8192 16384 32768 roc (Instructions) h ip Data Memory (Bytes) 512 768 1536 3936 512 768 1536 3936 T e Data EEPROM Memory 256 256 256 1024 256 256 256 1024 c h (Bytes) n olo Interrupt Sources 19 19 19 19 20 20 20 20 gy I/O Ports A, B, C, (E)(1) A, B, C, (E)(1) A, B, C, (E)(1) A, B, C, (E)(1) A, B, C, D, E A, B, C, D, E A, B, C, D, E A, B, C, D, E Inc Timers 4 4 44 44 44 . Capture/Compare/PWM 1 1 1 1 1 1 1 1 Modules Enhanced Capture/ 1 1 11 11 11 Compare/PWM Modules Serial Communications MSSP, Enhanced MSSP, Enhanced MSSP, Enhanced MSSP, Enhanced MSSP, Enhanced MSSP, Enhanced MSSP, Enhanced MSSP, Enhanced EUSART EUSART EUSART EUSART EUSART EUSART EUSART EUSART Parallel Communica- No No No No Yes Yes Yes Yes tions (PSP) 10-bit Analog-to-Digital 1 internal plus 10 1 internal plus 10 1 internal plus 10 1 internal plus 10 1 internal plus 13 1 internal plus 13 1 internal plus 13 1 internal plus 13 Module Input Channels Input Channels Input Channels Input Channels Input Channels Input Channels Input Channels Input Channels Resets (and Delays) POR, BOR, RESET POR, BOR, RESET POR, BOR, RESET POR, BOR, RESET POR, BOR, RESET POR, BOR, RESET POR, BOR, RESET POR, BOR, RESET Instruction, Stack Instruction, Stack Instruction, Stack Instruction, Stack Instruction, Stack Instruction, Stack Instruction, Stack Instruction, Stack P Full, Stack Underflow Full, Stack Underflow Full, Stack Underflow Full, Stack Underflow Full, Stack Underflow Full, Stack Underflow Full, Stack Underflow Full, Stack (PWRT, OST), (PWRT, OST), MCLR (PWRT, OST), (PWRT, OST), MCLR (PWRT, OST), (PWRT, OST), (PWRT, OST), Underflow (PWRT, I C MCLR (optional), (optional), WDT MCLR (optional), (optional), WDT MCLR (optional), MCLR (optional), MCLR (optional), OST), MCLR WDT WDT WDT WDT WDT (optional), WDT 1 Programmable High/ Yes Yes Yes Yes Yes Yes Yes Yes 8 Low-Voltage Detect F Programmable Brown- Yes Yes Yes Yes Yes Yes Yes Yes out Reset 2 Instruction Set 75 Instructions; 83 75 Instructions; 83 75 Instructions; 83 75 Instructions; 83 75 Instructions; 83 75 Instructions; 83 75 Instructions; 83 75 Instructions; 83 X with Extended with Extended with Extended with Extended with Extended with Extended with Extended with Extended Instruction Set Instruction Set Instruction Set Instruction Set Instruction Set Instruction Set Instruction Set Instruction Set K enabled enabled enabled enabled enabled enabled enabled enabled 2 Packages 28-pin PDIP 28-pin PDIP 28-pin PDIP 28-pin PDIP 40-pin PDIP 40-pin PDIP 40-pin PDIP 40-pin PDIP D 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin SOIC 44-pin QFN 44-pin QFN 44-pin QFN 44-pin QFN 0 S 28-pin QFN 28-pin QFN 28-pin QFN 28-pin QFN 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP 4 / 000 2288--ppiinn USSQOFNP 28-pin SSOP 28-pin SSOP 28-pin SSOP 40-pin UQFN 40-pin UQFN 40-pin UQFN 40-pin UQFN 4 1 X 30 Note 1: PORTE contains the single RE3 read-only bit. The LATE and TRISE registers are not implemented. 3H 2: Frequency range shown applies to industrial range devices only. Maximum frequency for extended range devices is 48 MHz. K -p a 2 g e 1 0 3

PIC18F2XK20/4XK20 FIGURE 1-1: PIC18F2XK20 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 8 Data Latch PORTA inc/dec logic RA0/AN0 Data Memory RA1/AN1 21 PCLAT U PCLATH RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ 20 Address Latch RA4/T0CKI/C1OUT PCU PCH PCL RA5/AN4/SS/HLVDIN/C2OUT Program Counter 12 OSC2/CLKOUT(3)/RA6 Data Address<12> OSC1/CLKIN(3)/RA7 31-Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (8/16/32/64Kbytes) FSR1 Data Latch FSR2 12 PORTB RB0/INT0/FLT0/AN12 inc/dec 8 logic RB1/INT1/AN10/C12IN3- Table Latch RB2/INT2/AN8 RB3/AN9/CCP2(1)/C12IN2- RB4/KBI0/AN11 Address ROM Latch RB5/KBI1/PGM Instruction Bus <16> Decode RB6/KBI2/PGC RB7/KBI3/PGD IR 8 Instruction State machine Decode and control signals Control PRODH PRODL PORTC 8 x 8 Multiply RC0/T1OSO/T13CKI 3 8 RC1/T1OSI/CCP2(1) RC2/CCP1 BITOP W RC3/SCK/SCL 8 8 8 RC4/SDI/SDA OSC1(3) OInsBtceloilrlcnakatolr PoTwimere-rup 8 8 RRRCCC657///TSRXDX/O/CDKT OSC2(3) Oscillator ALU<8> LFINTOSC Start-up Timer T1OSI Oscillator Power-on 8 Reset 16 MHz T1OSO Oscillator Watchdog Timer MCLR(2) SPirnogglrea-mSumpipnlgy BrRowesne-otut RBPearefnecdri esGnioacnpe FVR PORTE In-Circuit Fail-Safe VDD,VSS Debugger Clock Monitor MCLR/VPP/RE3(2) BOR Data HLVD EEPROM Timer0 Timer1 Timer2 Timer3 FVR ADC FVR CVREF Comparator ECCP1 CCP2 MSSP EUSART 10-bit Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information. DS40001303H-page 14  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 1-2: PIC18F4XK20 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA RA0/AN0 8 8 Data Latch RA1/AN1 inc/dec logic RA2/AN2/VREF-/CVREF Data Memory RA3/AN3/VREF+ 21 PCLAT U PCLATH RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT 20 Address Latch OSC2/CLKOUT(3)/RA6 PCU PCH PCL OSC1/CLKIN(3)/RA7 Program Counter 12 Data Address<12> PORTB 31-Level Stack RB0/INT0/FLT0/AN12 Address Latch 4 12 4 RB1/INT1/AN10/C12IN3- BSR Access Program Memory STKPTR FSR0 Bank RB2/INT2/AN8 (8/16/32/64Kbytes) FSR1 RB3/AN9/CCP2(1)/C12IN2- Data Latch FSR2 12 RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC inc/dec 8 logic RB7/KBI3/PGD Table Latch Address PORTC ROM Latch Instruction Bus <16> Decode RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A IR RC3/SCK/SCL RC4/SDI/SDA 8 RC5/SDO Instruction State machine RC6/TX/CK Decode and control signals RC7/RX/DT Control PRODH PRODL PORTD 3 8 x 8 Multiply 8 RD0/PSP0 RD1/PSP1 RD2/PSP2 BITOP W 8 8 8 RD3/PSP3 RD4/PSP4 OSC1(3) Internal Power-up RD5/PSP5/P1B Oscillator Timer 8 8 RD6/PSP6/P1C Block RD7/PSP7/P1D OSC2(3) Oscillator ALU<8> LFINTOSC Start-up Timer T1OSI Oscillator Power-on 8 Reset 16 MHz T1OSO Oscillator Watchdog PORTE Timer MCLR(2) Single-Supply Brown-out BParencdi sGioanp FVR RREE01//RWDR//AANN56 Programming Reset Reference RE2/CS/AN7 In-Circuit Fail-Safe MCLR/VPP/RE3(2) VDD,VSS Debugger Clock Monitor BOR Data HLVD EEPROM Timer0 Timer1 Timer2 Timer3 FVR ADC FVR CVREF Comparator ECCP1 CCP2 MSSP EUSART 10-bit PSP Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information.  2010-2015 Microchip Technology Inc. DS40001303H-page 15

PIC18F2XK20/4XK20 TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name PDIP, Description QFN Type Type SOIC MCLR/VPP/RE3 1 26 Master Clear (input) or programming voltage (input) MCLR I ST Active-low Master Clear (device Reset) input VPP P Programming voltage input RE3 I ST Digital input OSC1/CLKIN/RA7 9 6 Oscillator crystal or external clock input OSC1 I ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise CLKIN I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKIN, OSC2/CLKOUT pins) RA7 I/O TTL General purpose I/O pin OSC2/CLKOUT/RA6 10 7 Oscillator crystal or clock output OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode CLKOUT O — In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate RA6 I/O TTL General purpose I/O pin Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS40001303H-page 16  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PDIP, Description QFN Type Type SOIC PORTA is a bidirectional I/O port. RA0/AN0/C12IN0- 2 27 RA0 I/O TTL Digital I/O AN0 I Analog Analog input 0, ADC channel 0 C12IN0- I Analog Comparators C1 and C2 inverting input RA1/AN1/C12IN1- 3 28 RA1 I/O TTL Digital I/O AN1 I Analog ADC input 1, ADC channel 1 C12IN1- I Analog Comparators C1 and C2 inverting input RA2/AN2/VREF-/CVREF/ 4 1 C2IN+ RA2 I/O TTL Digital I/O AN2 I Analog Analog input 2, ADC channel 2 VREF- I Analog A/D reference voltage (low) input CVREF O Analog Comparator reference voltage output C2IN+ I Analog Comparator C2 non-inverting input RA3/AN3/VREF+/C1IN+ 5 2 RA3 I/O TTL Digital I/O AN3 I Analog Analog input 3, ADC channel 3 VREF+ I Analog A/D reference voltage (high) input C1IN+ I Analog Comparator C1 non-inverting input RA4/T0CKI/C1OUT 6 3 RA4 I/O ST Digital I/O T0CKI I ST Timer0 external clock input C1OUT O CMOS Comparator C1 output RA5/AN4/SS/HLVDIN/ 7 4 C2OUT RA5 I/O TTL Digital I/O AN4 I Analog Analog input 4, ADC channel 4 SS I TTL SPI slave select input HLVDIN I Analog High/Low-Voltage Detect input C2OUT O CMOS Comparator C2 output RA6 See the OSC2/CLKOUT/RA6 pin RA7 See the OSC1/CLKIN/RA7 pin Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.  2010-2015 Microchip Technology Inc. DS40001303H-page 17

PIC18F2XK20/4XK20 TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PDIP, Description QFN Type Type SOIC PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on each input. RB0/INT0/FLT0/AN12 21 18 RB0 I/O TTL Digital I/O INT0 I ST External interrupt 0 FLT0 I ST PWM Fault input for CCP1 AN12 I Analog Analog input 12, ADC channel 12 RB1/INT1/AN10/C12IN3- 22 19 /P1C RB1 I/O TTL Digital I/O INT1 I ST External interrupt 1 AN10 I Analog Analog input 10, ADC channel 10 C12IN3- I Analog Comparators C1 and C2 inverting input P1C O CMOS Enhanced CCP1 PWM output RB2/INT2/AN8/P1B 23 20 RB2 I/O TTL Digital I/O INT2 I ST External interrupt 2 AN8 I Analog Analog input 8, ADC channel 8 P1B O CMOS Enhanced CCP1 PWM output RB3/AN9/C12IN2-/CCP2 24 21 RB3 I/O TTL Digital I/O AN9 I Analog Analog input 9, ADC channel 9 C12IN2- I Analog Comparators C1 and C2 inverting input CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM 2 output RB4/KBI0/AN11/P1D 25 22 RB4 I/O TTL Digital I/O KBI0 I TTL Interrupt-on-change pin AN11 I Analog Analog input 11, ADC channel 11 P1D O CMOS Enhanced CCP1 PWM output RB5/KBI1/PGM 26 23 RB5 I/O TTL Digital I/O KBI1 I TTL Interrupt-on-change pin PGM I/O ST Low-Voltage ICSP™ Programming enable pin RB6/KBI2/PGC 27 24 RB6 I/O TTL Digital I/O KBI2 I TTL Interrupt-on-change pin PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin RB7/KBI3/PGD 28 25 RB7 I/O TTL Digital I/O KBI3 I TTL Interrupt-on-change pin PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS40001303H-page 18  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 1-2: PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PDIP, Description QFN Type Type SOIC PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 11 8 RC0 I/O ST Digital I/O T1OSO O — Timer1 oscillator output T13CKI I ST Timer1/Timer3 external clock input RC1/T1OSI/CCP2 12 9 RC1 I/O ST Digital I/O T1OSI I Analog Timer1 oscillator input CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output RC2/CCP1/P1A 13 10 RC2 I/O ST Digital I/O CCP1 I/O ST Capture 1 input/Compare 1 output P1A O CMOS Enhanced CCP1 PWM output RC3/SCK/SCL 14 11 RC3 I/O ST Digital I/O SCK I/O ST Synchronous serial clock input/output for SPI mode SCL I/O ST Synchronous serial clock input/output for I2C™ mode RC4/SDI/SDA 15 12 RC4 I/O ST Digital I/O SDI I ST SPI data in SDA I/O ST I2C™ data I/O RC5/SDO 16 13 RC5 I/O ST Digital I/O SDO O — SPI data out RC6/TX/CK 17 14 RC6 I/O ST Digital I/O TX O — EUSART asynchronous transmit CK I/O ST EUSART synchronous clock (see related RX/DT) RC7/RX/DT 18 15 RC7 I/O ST Digital I/O RX I ST EUSART asynchronous receive DT I/O ST EUSART synchronous data (see related TX/CK) RE3 — — — — See MCLR/VPP/RE3 pin VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins VDD 20 17 P — Positive supply for logic and I/O pins Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.  2010-2015 Microchip Technology Inc. DS40001303H-page 19

PIC18F2XK20/4XK20 TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP UQFN Type Type MCLR/VPP/RE3 1 18 18 16 Master Clear (input) or programming voltage MCLR I ST (input) VPP P Active-low Master Clear (device Reset) input RE3 I ST Programming voltage input Digital input OSC1/CLKIN/RA7 13 32 30 28 Oscillator crystal or external clock input OSC1 I ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CLKIN I CMOS analog otherwise External clock source input. Always associated with RA7 I/O TTL pin function OSC1 (See related OSC1/CLKIN, OSC2/CLKOUT pins) General purpose I/O pin OSC2/CLKOUT/ 14 33 31 29 Oscillator crystal or clock output RA6 O — Oscillator crystal output. Connects to crystal OSC2 or resonator in Crystal Oscillator mode O — In RC mode, OSC2 pin outputs CLKOUT which CLKOUT has 1/4 the frequency of OSC1 and denotes the instruction cycle rate I/O TTL General purpose I/O pin RA6 Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS40001303H-page 20  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP UQFN Type Type PORTA is a bidirectional I/O port. RA0/AN0/C12IN0- 2 19 19 RA0 I/O TTL Digital I/O AN0 I Analog Analog input 0, ADC channel 0 C12IN0- I Analog Comparator C1 and C2 inverting input RA1/AN1/C12IN0- 3 20 20 RA1 I/O TTL Digital I/O AN1 I Analog Analog input 1, ADC channel 1 C12IN0- I Analog Comparator C1 and C2 inverting input RA2/AN2/VREF-/ 4 21 21 CVREF/C2IN+ RA2 I/O TTL Digital I/O AN2 I Analog Analog input 2, ADC channel 2 VREF- I Analog A/D reference voltage (low) input CVREF O Analog Comparator reference voltage output C2IN+ I Analog Comparator C2 non-inverting input RA3/AN3/VREF+/ 5 22 22 C1IN+ RA3 I/O TTL Digital I/O AN3 I Analog Analog input 3, ADC channel 3 VREF+ I Analog A/D reference voltage (high) input C1IN+ I Analog Comparator C1 non-inverting input RA4/T0CKI/C1OUT 6 23 23 RA4 I/O ST Digital I/O T0CKI I ST Timer0 external clock input C1OUT O CMOS Comparator C1 output RA5/AN4/SS/HLV- 7 24 24 DIN/C2OUT RA5 I/O TTL Digital I/O AN4 I Analog Analog input 4, ADC channel 4 SS I TTL SPI slave select input HLVDIN I Analog High/Low-Voltage Detect input C2OUT O CMOS Comparator C2 output RA6 See the OSC2/CLKOUT/RA6 pin RA7 See the OSC1/CLKIN/RA7 pin Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.  2010-2015 Microchip Technology Inc. DS40001303H-page 21

PIC18F2XK20/4XK20 TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP UQFN Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on each input. RB0/INT0/FLT0/ 33 9 8 AN12 I/O TTL Digital I/O RB0 I ST External interrupt 0 INT0 I ST PWM Fault input for Enhanced CCP1 FLT0 I Analog Analog input 12, ADC channel 12 AN12 RB1/INT1/AN10/ 34 10 9 C12IN3- RB1 I/O TTL Digital I/O INT1 I ST External interrupt 1 AN10 I Analog Analog input 10, ADC channel 10 C12IN3- I Analog Comparator C1 and C2 inverting input RB2/INT2/AN8 35 11 10 RB2 I/O TTL Digital I/O INT2 I ST External interrupt 2 AN8 I Analog Analog input 8, ADC channel 8 RB3/AN9/C12IN2-/ 36 12 11 CCP2 RB3 I/O TTL Digital I/O AN9 I Analog Analog input 9, ADC channel 9 C12IN23- I Analog Comparator C1 and C2 inverting input CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM 2 output RB4/KBI0/AN11 37 14 14 RB4 I/O TTL Digital I/O KBI0 I TTL Interrupt-on-change pin AN11 I Analog Analog input 11, ADC channel 11 RB5/KBI1/PGM 38 15 15 RB5 I/O TTL Digital I/O KBI1 I TTL Interrupt-on-change pin PGM I/O ST Low-Voltage ICSP™ Programming enable pin RB6/KBI2/PGC 39 16 16 RB6 I/O TTL Digital I/O KBI2 I TTL Interrupt-on-change pin PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin RB7/KBI3/PGD 40 17 17 RB7 I/O TTL Digital I/O KBI3 I TTL Interrupt-on-change pin PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS40001303H-page 22  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP UQFN Type Type PORTC is a bidirectional I/O port. RC0/T1OSO/ 15 34 32 T13CKI I/O ST Digital I/O RC0 O — Timer1 oscillator output T1OSO I ST Timer1/Timer3 external clock input T13CKI RC1/T1OSI/CCP2 16 35 35 RC1 I/O ST Digital I/O T1OSI I CMOS Timer1 oscillator input CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output RC2/CCP1/P1A 17 36 36 RC2 I/O ST Digital I/O CCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 P1A O — output Enhanced CCP1 output RC3/SCK/SCL 18 37 37 RC3 I/O ST Digital I/O SCK I/O ST Synchronous serial clock input/output for SPI mode SCL I/O ST Synchronous serial clock input/output for I2C™ mode RC4/SDI/SDA 23 42 42 RC4 I/O ST Digital I/O SDI I ST SPI data in SDA I/O ST I2C™ data I/O RC5/SDO 24 43 43 RC5 I/O ST Digital I/O SDO O — SPI data out RC6/TX/CK 25 44 44 RC6 I/O ST Digital I/O TX O — EUSART asynchronous transmit CK I/O ST EUSART synchronous clock (see related RX/ DT) RC7/RX/DT 26 1 1 RC7 I/O ST Digital I/O RX I ST EUSART asynchronous receive DT I/O ST EUSART synchronous data (see related TX/ CK) Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.  2010-2015 Microchip Technology Inc. DS40001303H-page 23

PIC18F2XK20/4XK20 TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP UQFN Type Type PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. RD0/PSP0 19 38 38 RD0 I/O ST Digital I/O PSP0 I/O TTL Parallel Slave Port data RD1/PSP1 20 39 39 RD1 I/O ST Digital I/O PSP1 I/O TTL Parallel Slave Port data RD2/PSP2 21 40 40 RD2 I/O ST Digital I/O PSP2 I/O TTL Parallel Slave Port data RD3/PSP3 22 41 41 RD3 I/O ST Digital I/O PSP3 I/O TTL Parallel Slave Port data RD4/PSP4 27 2 2 RD4 I/O ST Digital I/O PSP4 I/O TTL Parallel Slave Port data RD5/PSP5/P1B 28 3 3 RD5 I/O ST Digital I/O PSP5 I/O TTL Parallel Slave Port data P1B O — Enhanced CCP1 output RD6/PSP6/P1C 29 4 4 RD6 I/O ST Digital I/O PSP6 I/O TTL Parallel Slave Port data P1C O — Enhanced CCP1 output RD7/PSP7/P1D 30 5 5 RD7 I/O ST Digital I/O PSP7 I/O TTL Parallel Slave Port data P1D O — Enhanced CCP1 output Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS40001303H-page 24  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 1-3: PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP UQFN Type Type PORTE is a bidirectional I/O port RE0/RD/AN5 8 25 25 RE0 I/O ST Digital I/O RD I TTL Read control for Parallel Slave Port (see related WR and CS pins) AN5 I Analog Analog input 5, ADC channel 5 RE1/WR/AN6 9 26 26 RE1 I/O ST Digital I/O WR I TTL Write control for Parallel Slave Port (see related CS and RD pins) AN6 I Analog Analog input 6, ADC channel 6 RE2/CS/AN7 10 27 27 RE2 I/O ST Digital I/O CS I TTL Chip Select control for Parallel Slave Port (see related RD and WR) AN7 I Analog Analog input 7, ADC channel 7 RE3 — — — — — See MCLR/VPP/RE3 pin VSS 12, 31 6, 30, 6, 29 P — Ground reference for logic and I/O pins 31 VDD 11, 32 7, 8, 7, 28 P — Positive supply for logic and I/O pins 28, 29 NC — 13 12, 13, — — No connect 33, 34 Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.  2010-2015 Microchip Technology Inc. DS40001303H-page 25

PIC18F2XK20/4XK20 2.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of ten FAIL-SAFE CLOCK MONITOR) primary clock modes. 1. LP Low-Power Crystal 2.1 Overview 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator The oscillator module has a wide variety of clock 4. HSPLL High-Speed Crystal/Resonator sources and selection features that allow it to be used with PLL enabled in a wide range of applications while maximizing performance and minimizing power consumption. 5. RC External Resistor/Capacitor with Figure2-1 illustrates a block diagram of the oscillator FOSC/4 output on RA6 module. 6. RCIO External Resistor/Capacitor with I/O on RA6 Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators 7. INTOSC Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two 8. INTOSCIO Internal Oscillator with I/O on RA6 internal oscillators, with a choice of speeds selectable via and RA7 software. Additional clock features include: 9. EC External Clock with FOSC/4 output • Selectable system clock source between external 10. ECIO External Clock with I/O on RA6 or internal via software. Primary Clock modes are selected by the FOSC<3:0> • Two-Speed Start-up mode, which minimizes bits of the CONFIG1H Configuration Register. The latency between external oscillator start-up and HFINTOSC and LFINTOSC are factory calibrated code execution. high-frequency and low-frequency oscillators, • Fail-Safe Clock Monitor (FSCM) designed to respectively, which are used as the internal clock detect a failure of the external clock source (LP, sources. XT, HS, EC or RC modes) and switch automatically to the internal oscillator. FIGURE 2-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM PIC18F2XK20/4XK20 Primary Oscillator LP, XT, HS, RC, EC OSC2 IDLEN Sleep HSPLL, HFINTOSC/PLL 4 x PLL Sleep OSC1 OSCTUNE<6>(1) Secondary Oscillator T1OSC X Main Peripherals T1OSO U M T1OSCEN Enable T1OSI Oscillator OSCCON<6:4> Internal Oscillator FOSC<3:0> OSCCON< 1:0> 16 MHz 111 CPU 8 MHz Internal 110 Sleep Oscillator 4 MHz Block er 2 MHz 101 Clock 1S6o uMrHcez 16 MHz stscal 1 MHz 100101MUX Control 31 kHz (HFINTOSC) Po 500 kHz 010 FOSC<3:0> OSCCON< 1:0> Source 250 kHz 001 Clock Source Option 1 31 kHz 31 kHz (LFINTOSC) 000 for other Modules 0 OSCTUNE<7> WDT, PWRT, FSCM and Two-Speed Start-up Note 1: Operates only when HFINTOSC is the primary oscillator. DS40001303H-page 26  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 2.2 Oscillator Control 2.2.4 CLOCK STATUS The OSCCON register (Register2-1) controls several The OSTS and IOFS bits of the OSCCON register, and aspects of the device clock’s operation, both in full the T1RUN bit of the T1CON register, indicate which power operation and in power-managed modes. clock source is currently providing the main clock. The OSTS bit indicates that the Oscillator Start-up Timer • Main System Clock Selection (SCS) has timed out and the primary clock is providing the • Internal Frequency selection bits (IRCF) device clock. The IOFS bit indicates when the internal • Clock Status bits (OSTS, IOFS) oscillator block has stabilized and is providing the • Power management selection (IDLEN) device clock in HFINTOSC Clock modes. The IOFS and OSTS Status bits will both be set when 2.2.1 MAIN SYSTEM CLOCK SELECTION SCS<1:0>=00 and HFINTOSC is the primary clock. The T1RUN bit indicates when the Timer1 oscillator is The System Clock Select bits, SCS<1:0>, select the providing the device clock in secondary clock modes. main clock source. The available clock sources are When SCS<1:0>00, only one of these three bits will • Primary clock defined by the FOSC<3:0> bits of be set at any time. If none of these bits are set, the CONFIG1H. The primary clock can be the primary LFINTOSC is providing the clock or the HFINTOSC has oscillator, an external clock, or the internal just started and is not yet stable. oscillator block. • Secondary clock (Timer1 oscillator) 2.2.5 POWER MANAGEMENT • Internal oscillator block (HFINTOSC and The IDLEN bit of the OSCCON register determines if LFINTOSC). the device goes into Sleep mode or one of the Idle The clock source changes immediately after one or modes when the SLEEP instruction is executed. more of the bits is written to, following a brief clock The use of the flag and control bits in the OSCCON transition interval. The SCS bits are cleared to select register is discussed in more detail in Section3.0 the primary clock on all forms of Reset. “Power-Managed Modes”. 2.2.2 INTERNAL FREQUENCY Note1: The Timer1 oscillator must be enabled to SELECTION select the secondary clock source. The Timer1 oscillator is enabled by setting the The Internal Oscillator Frequency Select bits T1OSCEN bit of the T1CON register. If (IRCF<2:0>) select the frequency output of the internal the Timer1 oscillator is not enabled, then oscillator block. The choices are the LFINTOSC source the main oscillator will continue to run (31kHz), the HFINTOSC source (16MHz) or one of from the previously selected source. The the frequencies derived from the HFINTOSC source will then switch to the secondary postscaler (31.25kHz to 8MHz). If the internal oscillator after the T1OSCEN bit is set. oscillator block is supplying the main clock, changing the states of these bits will have an immediate change 2: It is recommended that the Timer1 on the internal oscillator’s output. On device Resets, oscillator be operating and stable before the output frequency of the internal oscillator is set to selecting the secondary clock source or a the default frequency of 1MHz. very long delay may occur while the Timer1 oscillator starts. 2.2.3 LOW FREQUENCY SELECTION When a nominal output frequency of 31kHz is selected (IRCF<2:0> = 000), users may choose which internal oscillator acts as the source. This is done with the INTSRC bit of the OSCTUNE register. Setting this bit selects the HFINTOSC as a 31.25kHz clock source by enabling the divide-by-512 output of the HFINTOSC postscaler. Clearing INTSRC selects LFINTOSC (nominally 31kHz) as the clock source. This option allows users to select the tunable and more precise HFINTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, LFINTOSC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor.  2010-2015 Microchip Technology Inc. DS40001303H-page 27

PIC18F2XK20/4XK20 REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R-q R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS(1) IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 16MHz (HFINTOSC drives clock directly) 110 = 8MHz 101 = 4MHz 100 = 2MHz 011 = 1MHz(3) 010 = 500kHz 001 = 250kHz 000 = 31kHz (from either HFINTOSC/512 or LFINTOSC directly)(2) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC) bit 2 IOFS: HFINTOSC Frequency Stable bit 1 = HFINTOSC frequency is stable 0 = HFINTOSC frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary clock (determined by CONFIG1H[FOSC<3:0>]). Note 1: Reset state depends on state of the IESO Configuration bit. 2: Source selected by the INTSRC bit of the OSCTUNE register, see text. 3: Default output frequency of HFINTOSC on Reset. DS40001303H-page 28  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 2.3 Clock Source Modes 2.4 External Clock Modes Clock Source modes can be classified as external or 2.4.1 OSCILLATOR START-UP TIMER (OST) internal. When the oscillator module is configured for LP, XT or • External Clock modes rely on external circuitry for HS modes, the Oscillator Start-up Timer (OST) counts the clock source. Examples are: Clock modules 1024 oscillations from OSC1. This occurs following a (EC mode), quartz crystal resonators or ceramic Power-on Reset (POR) and when the Power-up Timer resonators (LP, XT and HS modes) and Resistor- (PWRT) has expired (if configured), or a wake-up from Capacitor (RC mode) circuits. Sleep. During this time, the program counter does not • Internal clock sources are contained internally increment and program execution is suspended. The within the Oscillator block. The Oscillator block OST ensures that the oscillator circuit, using a quartz has two internal oscillators: the 16MHz crystal resonator or ceramic resonator, has started and High-Frequency Internal Oscillator (HFINTOSC) is providing a stable system clock to the oscillator and the 31kHz Low-Frequency Internal Oscillator module. When switching between clock sources, a (LFINTOSC). delay is required to allow the new clock to stabilize. The system clock can be selected between external or These oscillator delays are shown in Table2-1. internal clock sources via the System Clock Select In order to minimize latency between external oscillator (SCS<1:0>) bits of the OSCCON register. See start-up and code execution, the Two-Speed Clock Section2.9 “Clock Switching” for additional Start-up mode can be selected (see Section2.10 information. “Two-Speed Clock Start-up Mode”). TABLE 2-1: OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Oscillator Delay LFINTOSC 31kHz Sleep/POR Oscillator Warm-Up Delay (TWARM) HFINTOSC 250kHz to 16MHz Sleep/POR EC, RC DC – 64MHz 2 instruction cycles LFINTOSC (31kHz) EC, RC DC – 64MHz 1 cycle of each Sleep/POR LP, XT, HS 32kHz to 40MHz 1024 Clock Cycles (OST) Sleep/POR HSPLL 32MHz to 64MHz 1024 Clock Cycles (OST) + 2 ms LFINTOSC (31kHz) HFINTOSC 250kHz to 16MHz 1s (approx.) 2.4.2 EC MODE FIGURE 2-2: EXTERNAL CLOCK (EC) MODE OPERATION The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is Clock from OSC1/CLKIN connected to the OSC1 input and the OSC2 is available Ext. System for general purpose I/O. Figure2-2 shows the pin PIC® MCU connections for EC mode. I/O OSC2/CLKOUT(1) The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up Note 1: Alternate pin functions are listed in from Sleep. Because the PIC® MCU design is fully Section1.0 “Device Overview”. static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.  2010-2015 Microchip Technology Inc. DS40001303H-page 29

PIC18F2XK20/4XK20 2.4.3 LP, XT, HS MODES Note 1: Quartz crystal characteristics vary The LP, XT and HS modes support the use of quartz according to type, package and crystal resonators or ceramic resonators connected to manufacturer. The user should consult the OSC1 and OSC2 (Figure2-3). The mode selects a low, manufacturer data sheets for specifications medium or high gain setting of the internal inverter- and recommended application. amplifier to support various resonator types and speed. 2: Always verify oscillator performance over LP Oscillator mode selects the lowest gain setting of the the VDD and temperature range that is internal inverter-amplifier. LP mode current consumption expected for the application. is the least of the three modes. This mode is best suited 3: For oscillator design assistance, reference to drive resonators with a low drive level specification, for the following Microchip Applications Notes: example, tuning fork type crystals. • AN826, “Crystal Oscillator Basics and XT Oscillator mode selects the intermediate gain Crystal Selection for rfPIC® and PIC® setting of the internal inverter-amplifier. XT mode Devices” (DS00826) current consumption is the medium of the three modes. • AN849, “Basic PIC® Oscillator Design” This mode is best suited to drive resonators with a (DS00849) medium drive level specification. • AN943, “Practical PIC® Oscillator HS Oscillator mode selects the highest gain setting of the Analysis and Design” (DS00943) internal inverter-amplifier. HS mode current consumption • AN949, “Making Your Oscillator Work” is the highest of the three modes. This mode is best (DS00949) suited for resonators that require a high drive setting. Figure2-3 and Figure2-4 show typical circuits for FIGURE 2-4: CERAMIC RESONATOR quartz crystal and ceramic resonators, respectively. OPERATION (XT OR HS MODE) FIGURE 2-3: QUARTZ CRYSTAL OPERATION (LP, XT OR PIC® MCU HS MODE) OSC1/CLKIN PIC® MCU C1 To Internal Logic OSC1/CLKIN C1 To Internal RP(3) RF(2) Sleep Logic Quartz RF(2) Sleep Crystal C2 Ceramic RS(1) OSC2/CLKOUT Resonator C2 RS(1) OSC2/CLKOUT Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. Note 1: A series resistor (RS) may be required for 2: The value of RF varies with the Oscillator mode quartz crystals with low drive level. selected (typically between 2M to 10M. 2: The value of RF varies with the Oscillator mode 3: An additional parallel feedback resistor (RP) selected (typically between 2M to 10M. may be required for proper ceramic resonator operation. DS40001303H-page 30  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 2.4.4 EXTERNAL RC MODES 2.5 Internal Clock Modes The external Resistor-Capacitor (RC) modes support The oscillator module has two independent, internal the use of an external RC circuit. This allows the oscillators that can be configured or selected as the designer maximum flexibility in frequency choice while system clock source. keeping costs to a minimum when clock accuracy is not 1. The HFINTOSC (High-Frequency Internal required. There are two modes: RC and RCIO. Oscillator) is factory calibrated and operates at 2.4.4.1 RC Mode 16MHz. The frequency of the HFINTOSC can be user-adjusted via software using the In RC mode, the RC circuit connects to OSC1. OSC2/ OSCTUNE register (Register2-2). CLKOUT outputs the RC oscillator frequency divided 2. The LFINTOSC (Low-Frequency Internal by 4. This signal may be used to provide a clock for Oscillator) operates at 31kHz. external circuitry, synchronization, calibration, test or other application requirements. Figure2-5 shows the The system clock speed can be selected via software external RC mode connections. using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register. FIGURE 2-5: EXTERNAL RC MODES The system clock can be selected between external or internal clock sources via the System Clock Selection VDD PIC® MCU (SCS<1:0>) bits of the OSCCON register. See Section2.9 “Clock Switching” for more information. REXT 2.5.1 INTOSC AND INTOSCIO MODES OSC1/CLKIN Internal Clock The INTOSC and INTOSCIO modes configure the CEXT internal oscillators as the primary clock source. The FOSC<3:0> bits in the CONFIG1H Configuration VSS register determine which mode is selected. See FOSC/4 or OSC2/CLKOUT(1) Section23.0 “Special Features of the CPU” for more I/O(2) information. In INTOSC mode, OSC1/CLKIN is available for general Recommended values: 10 k  REXT  100 k purpose I/O. OSC2/CLKOUT outputs the selected CEXT > 20 pF internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other Note 1: Alternate pin functions are listed in application requirements. Section1.0 “Device Overview”. 2: Output depends upon RC or RCIO clock mode. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O. 2.4.4.2 RCIO Mode 2.5.2 HFINTOSC In RCIO mode, the RC circuit is connected to OSC1. The output of the HFINTOSC connects to a postscaler OSC2 becomes an additional general purpose I/O pin. and multiplexer (see Figure2-1). One of eight The RC oscillator frequency is a function of the supply frequencies can be selected via software using the voltage, the resistor (REXT) and capacitor (CEXT) values IRCF<2:0> bits of the OSCCON register. See and the operating temperature. Other factors affecting Section2.5.4 “Frequency Select Bits (IRCF)” for the oscillator frequency are: more information. • input threshold voltage variation The HFINTOSC is enabled when: • component tolerances • packaging variations in capacitance • SCS1 = 1 and IRCF<2:0> 000 • SCS1 = 1 and IRCF<2:0>=000 and INTSRC=1 The user also needs to take into account variation due to tolerance of external RC components used. • IESO bit of CONFIG1H=1 enabling Two-Speed Start-up. • FCMEM bit of CONFIG1H=1 enabling Two-Speed Start-up and Fail-Safe mode. • FOSC<3:0> of CONFIG1H selects the internal oscillator as the primary clock The HF Internal Oscillator (IOFS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not.  2010-2015 Microchip Technology Inc. DS40001303H-page 31

PIC18F2XK20/4XK20 2.5.2.1 OSCTUNE Register (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the The HFINTOSC is factory calibrated but can be change in frequency. adjusted in software by writing to the TUN<5:0> bits of the OSCTUNE register (Register2-2). The OSCTUNE register also implements the INTSRC and PLLEN bits, which control certain features of the The default value of the TUN<5:0> is ‘000000’. The internal oscillator block. value is a 6-bit two’s complement number. The INTSRC bit allows users to select which internal When the OSCTUNE register is modified, the oscillator provides the clock source when the 31kHz HFINTOSC frequency will begin shifting to the new frequency option is selected. This is covered in greater frequency. Code execution continues during this shift. detail in Section2.2.3 “Low Frequency Selection”. There is no indication that the shift has occurred. The PLLEN bit controls the operation of the frequency OSCTUNE does not affect the LFINTOSC frequency. multiplier, PLL, in internal oscillator modes. For more Operation of features that depend on the LFINTOSC details about the function of the PLLEN bit see clock source frequency, such as the Power-up Timer Section2.6.2 “PLL in HFINTOSC Modes” REGISTER 2-2: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock derived from 16MHz HFINTOSC source (divide-by-512 enabled) 0 = 31kHz device clock derived directly from LFINTOSC internal oscillator bit 6 PLLEN: Frequency Multiplier PLL for HFINTOSC Enable bit(1) 1 = PLL enabled for HFINTOSC (8MHz and 16MHz only) 0 = PLL disabled bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = • • • 000001 = 000000 = Oscillator module is running at the factory calibrated frequency. 111111 = • • • 100000 = Minimum frequency Note 1: The PLLEN bit is active only when the HFINTOSC is the primary clock source (FOSC<2:0>=100X) and the selected frequency is 8 MHz or 16 MHz. Otherwise, the PLLEN bit is unavailable and always reads ‘0’. DS40001303H-page 32  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 2.5.3 LFINTOSC 2.5.5 HFINTOSC FREQUENCY DRIFT The Low-Frequency Internal Oscillator (LFINTOSC) is The factory calibrates the internal oscillator block output a 31kHz internal clock source. (HFINTOSC) for 16MHz. However, this frequency may The output of the LFINTOSC connects to internal drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. It is possible to oscillator block frequency selection multiplexer (see adjust the HFINTOSC frequency by modifying the value Figure2-1). Select 31kHz, via software, using the of the TUN<5:0> bits in the OSCTUNE register. This has IRCF<2:0> bits of the OSCCON register and the no effect on the LFINTOSC clock source frequency. INTSRC bit of the OSCTUNE register. See Section2.5.4 “Frequency Select Bits (IRCF)” for Tuning the HFINTOSC source requires knowing when to more information. The LFINTOSC is also the frequency make the adjustment, in which direction it should be for the Power-up Timer (PWRT), Watchdog Timer made and in some cases, how large a change is (WDT) and Fail-Safe Clock Monitor (FSCM). needed. Three possible compensation techniques are discussed in the following sections, however other The LFINTOSC is enabled when any of the following techniques may be used. are enabled: • IRCF<2:0> bits of the OSCCON register = 000 and 2.5.5.1 Compensating with the EUSART INTSRC bit of the OSCTUNE register = 0 An adjustment may be required when the EUSART • Power-up Timer (PWRT) begins to generate framing errors or receives data with • Watchdog Timer (WDT) errors while in Asynchronous mode. Framing errors • Fail-Safe Clock Monitor (FSCM) indicate that the device clock frequency is too high; to adjust for this, decrement the value in OSCTUNE to 2.5.4 FREQUENCY SELECT BITS (IRCF) reduce the clock frequency. On the other hand, errors The output of the 16MHz HFINTOSC and 31kHz in data may suggest that the clock speed is too low; to LFINTOSC connects to a postscaler and multiplexer compensate, increment OSCTUNE to increase the (see Figure2-1). The Internal Oscillator Frequency clock frequency. Select bits IRCF<2:0> of the OSCCON register select 2.5.5.2 Compensating with the Timers the output frequency of the internal oscillators. One of eight frequencies can be selected via software: This technique compares device clock speed to some reference clock. Two timers may be used; one timer is • 16 MHz clocked by the peripheral clock, while the other is • 8 MHz clocked by a fixed reference source, such as the • 4 MHz Timer1 oscillator. • 2 MHz Both timers are cleared, but the timer clocked by the • 1 MHz (Default after Reset) reference generates interrupts. When an interrupt • 500 kHz occurs, the internally clocked timer is read and both • 250 kHz timers are cleared. If the internally clocked timer value • 31 kHz (LFINTOSC or HFINTOSC/512) is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. Note: Following any Reset, the IRCF<2:0> bits 2.5.5.3 Compensating with the CCP Module of the OSCCON register are set to ‘011’ in Capture Mode and the frequency selection is set to 1MHz. The user can modify the IRCF bits A CCP module can use free running Timer1 (or Timer3), to select a different frequency. clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calcu- lated time, the internal oscillator block is running too fast; to compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the OSCTUNE register.  2010-2015 Microchip Technology Inc. DS40001303H-page 33

PIC18F2XK20/4XK20 2.6 PLL Frequency Multiplier 2.6.2 PLL IN HFINTOSC MODES A Phase-Locked Loop (PLL) circuit is provided as an The 4x frequency multiplier can be used with the option for users who wish to use a lower frequency internal oscillator block to produce faster device clock oscillator circuit or to clock the device up to its highest speeds than are normally possible with an internal rated frequency from the crystal oscillator. This may be oscillator. When enabled, the PLL produces a clock useful for customers who are concerned with EMI due speed of up to 64MHz. to high-frequency crystals or users who require higher Unlike HSPLL mode, the PLL is controlled through clock speeds from an internal oscillator. There are software. The PLLEN control bit of the OSCTUNE three conditions when the PLL can be used: register is used to enable or disable the PLL operation • When the primary clock is HSPLL when the HFINTOSC is used. • When the primary clock is HFINTOSC and the The PLL is available when the device is configured to selected frequency is 16 MHz use the internal oscillator block as its primary clock • When the primary clock is HFINTOSC and the source (FOSC<3:0> = 1001 or 1000). Additionally, the selected frequency is 8 MHz PLL will only function when the selected output fre- quency is either 8MHz or 16MHz (OSCCON<6:4> = 2.6.1 HSPLL OSCILLATOR MODE 111 or 110). If both of these conditions are not met, the PLL is disabled. The HSPLL mode makes use of the HS mode oscillator for frequencies up to 16 MHz. A PLL then multiplies the The PLLEN control bit is only functional in those oscillator output frequency by 4 to produce an internal internal oscillator modes where the PLL is available. In clock frequency up to 64 MHz. The PLLEN bit of the all other modes, it is forced to ‘0’ and is effectively OSCTUNE register is active only when the HFINTOSC unavailable. is the primary clock and is not available in HSPLL oscillator mode. The PLL is only available to the primary oscillator when the FOSC<3:0> Configuration bits are programmed for HSPLL mode (= 0110). FIGURE 2-6: PLL BLOCK DIAGRAM (HS MODE) HS Oscillator Enable PLL Enable (from Configuration Register 1H) OSC2 Phase HS Mode FIN Comparator OSC1 Crystal FOUT Osc Loop Filter 4 VCO SYSCLK X U M DS40001303H-page 34  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 2.7 Effects of Power-Managed Modes significant current consumption are listed in on the Various Clock Sources SectionTABLE 26-8: “Peripheral Supply Current, PIC18F2XK20/4XK20”. For more information about the modes discussed in this section see Section3.0 “Power-Managed Modes”. A 2.8 Power-up Delays quick reference list is also available in Table3-1. Power-up delays are controlled by two timers, so that When PRI_IDLE mode is selected, the designated no external Reset circuitry is required for most applica- primary oscillator continues to run without interruption. tions. The delays ensure that the device is kept in For all other power-managed modes, the oscillator Reset until the device power supply is stable under nor- using the OSC1 pin is disabled. The OSC1 pin (and mal circumstances and the primary clock is operating OSC2 pin, if used by the oscillator) will stop oscillating. and stable. For additional information on power-up In secondary clock modes (SEC_RUN and delays, see Section4.5 “Device Reset Timers”. SEC_IDLE), the Timer1 oscillator is operating and The first timer is the Power-up Timer (PWRT), which providing the device clock. The Timer1 oscillator may provides a fixed delay on power-up (parameter 33, also run in all power-managed modes if required to Table). It is enabled by clearing (= 0) the PWRTEN clock Timer1 or Timer3. Configuration bit. In internal oscillator modes (INTOSC_RUN and The second timer is the Oscillator Start-up Timer INTOSC_IDLE), the internal oscillator block provides (OST), intended to keep the chip in Reset until the the device clock source. The 31kHz LFINTOSC output crystal oscillator is stable (LP, XT and HS modes). The can be used directly to provide the clock and may be OST does this by counting 1024 oscillator cycles enabled to support various special features, regardless before allowing the oscillator to clock the device. of the power-managed mode (see Section23.2 “Watchdog Timer (WDT)”, Section2.10 “Two- When the HSPLL Oscillator mode is selected, the Speed Clock Start-up Mode” and Section2.11 “Fail- device is kept in Reset for an additional 2ms, following Safe Clock Monitor” for more information on WDT, the HS mode OST delay, so the PLL can lock to the Fail-Safe Clock Monitor and Two-Speed Start-up). The incoming clock frequency. HFINTOSC output at 16MHz may be used directly to There is a delay of interval TCSD (parameter 38, Table), clock the device or may be divided down by the following POR, while the controller becomes ready to postscaler. The HFINTOSC output is disabled if the execute instructions. This delay runs concurrently with clock is provided directly from the LFINTOSC output. any other delays. This may be the only delay that If the Sleep mode is selected, all clock sources are occurs when any of the EC, RC or INTIO modes are stopped. Since all the transistor switching currents used as the primary clock source. have been stopped, Sleep mode achieves the lowest When the HFINTOSC is selected as the primary clock, current consumption of the device (only leakage the main system clock can be delayed until the currents). HFINTOSC is stable. This is user selectable by the Enabling any on-chip feature that will operate during HFOFST bit of the CONFIG3H Configuration register. Sleep will increase the current consumed during Sleep. When the HFOFST bit is cleared the main system clock The LFINTOSC is required to support WDT operation. is delayed until the HFINTOSC is stable. When the The Timer1 oscillator may be operating to support a HFOFST bit is set the main system clock starts real-time clock. Other features may be operating that immediately. In either case the IOFS bit of the do not require a device clock source (i.e., SSP slave, OSCCON register can be read to determine whether PSP, INTn pins and others). Peripherals that may add the HFINTOSC is operating and stable. TABLE 2-2: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTOSC Floating, external resistor should pull high At logic low (clock/4 output) RCIO Floating, external resistor should pull high Configured as PORTA, bit 6 INTOSCIO Configured as PORTA, bit 7 Configured as PORTA, bit 6 ECIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) LP, XT, HS and HSPLL Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table4-2 in Section4.0 “Reset” for time-outs due to Sleep and MCLR Reset.  2010-2015 Microchip Technology Inc. DS40001303H-page 35

PIC18F2XK20/4XK20 2.9 Clock Switching 2.9.3 CLOCK SWITCH TIMING The system clock source can be switched between When switching between one oscillator and another, external and internal clock sources via software using the new oscillator may not be operating which saves the System Clock Select (SCS<1:0>) bits of the power (see Figure2-7). If this is the case, there is a OSCCON register. delay after the SCS<1:0> bits of the OSCCON register are modified before the frequency change takes place. PIC18F2XK20/4XK20 devices contain circuitry to The OSTS and IOFS bits of the OSCCON register will prevent clock “glitches” when switching between clock reflect the current active status of the external and sources. A short pause in the device clock occurs HFINTOSC oscillators. The timing of a frequency during the clock switch. The length of this pause is the selection is as follows: sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula 1. SCS<1:0> bits of the OSCCON register are mod- assumes that the new clock source is stable. ified. 2. The old clock continues to operate until the new Clock transitions are discussed in greater detail in clock is ready. Section3.1.2 “Entering Power-Managed Modes”. 3. Clock switch circuitry waits for two consecutive 2.9.1 SYSTEM CLOCK SELECT rising edges of the old clock after the new clock (SCS<1:0>) BITS ready signal goes true. 4. The system clock is held low starting at the next The System Clock Select (SCS<1:0>) bits of the falling edge of the old clock. OSCCON register select the system clock source that is used for the CPU and peripherals. 5. Clock switch circuitry waits for an additional two rising edges of the new clock. • When SCS<1:0> = 00, the system clock source is 6. On the next falling edge of the new clock the low determined by configuration of the FOSC<2:0> hold on the system clock is released and new bits in the CONFIG1H Configuration register. clock is switched in as the system clock. • When SCS<1:0> = 10, the system clock source is 7. Clock switch is complete. chosen by the internal oscillator frequency selected by the INTSRC bit of the OSCTUNE See Figure2-1 for more details. register and the IRCF<2:0> bits of the OSCCON If the HFINTOSC is the source of both the old and new register. frequency, there is no start-up delay before the new • When SCS<1:0> = 01, the system clock source is frequency is active. This is because the old and new the 32.768 kHz secondary oscillator shared with frequencies are derived from the HFINTOSC via the Timer1. postscaler and multiplexer. After a Reset, the SCS<1:0> bits of the OSCCON Start-up delay specifications are located in register are always cleared. Section26.0 “Electrical Specifications”, under AC Specifications (Oscillator Module). Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail- Safe Clock Monitor, does not update the SCS<1:0> bits of the OSCCON register. The user can monitor the T1RUN bit of the T1CON register and the IOFS and OSTS bits of the OSCCON register to determine the current system clock source. 2.9.2 OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCCON register indicates whether the system clock is running from the external clock source, as defined by the FOSC<3:0> bits in the CONFIG1H Configuration register, or from the internal clock source. In particular, when the primary oscillator is the source of the primary clock, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. DS40001303H-page 36  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 2.10 Two-Speed Clock Start-up Mode 2.10.2 TWO-SPEED START-UP SEQUENCE Two-Speed Start-up mode provides additional power savings by minimizing the latency between external 1. Wake-up from Power-on Reset or Sleep. oscillator start-up and code execution. In applications 2. Instructions begin executing by the internal that make heavy use of the Sleep mode, Two-Speed oscillator at the frequency set in the IRCF<2:0> Start-up will remove the external oscillator start-up bits of the OSCCON register. time from the time spent awake and can reduce the 3. OST enabled to count 1024 external clock overall power consumption of the device. cycles. This mode allows the application to wake-up from 4. OST timed out. External clock is ready. Sleep, perform a few instructions using the HFINTOSC 5. OSTS is set. as the clock source and go back to Sleep without 6. Clock switch finishes according to FIGURE 2-7: waiting for the primary oscillator to become stable. “Clock Switch Timing” Note: Executing a SLEEP instruction will abort 2.10.3 CHECKING TWO-SPEED CLOCK the oscillator start-up time and will cause STATUS the OSTS bit of the OSCCON register to remain clear. Checking the state of the OSTS bit of the OSCCON When the oscillator module is configured for LP, XT or register will confirm if the microcontroller is running HS modes, the Oscillator Start-up Timer (OST) is from the external clock source, as defined by the enabled (see Section2.4.1 “Oscillator Start-up Timer FOSC<2:0> bits in CONFIG1H Configuration register, (OST)”). The OST will suspend program execution until or the internal oscillator. OSTS = 0 when the external 1024 oscillations are counted. Two-Speed Start-up oscillator is not ready, which indicates that the system mode minimizes the delay in code execution by is running from the internal oscillator. operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit of the OSCCON register is set, program execution switches to the external oscillator. 2.10.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is enabled when all of the following settings are configured as noted: • Two-Speed Start-up mode is enabled by setting the IESO of the CONFIG1H Configuration register is set. Fail-Safe mode (FCMEM = 1) also enables two-speed by default. • SCS<1:0> (of the OSCCON register) = 00. • FOSC<2:0> bits of the CONFIG1H Configuration register are configured for LP, XT or HS mode. Two-Speed Start-up mode becomes active after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.  2010-2015 Microchip Technology Inc. DS40001303H-page 37

PIC18F2XK20/4XK20 FIGURE 2-7: CLOCK SWITCH TIMING High Speed Low Speed Old Clock Start-up Time(1) Clock Sync Running New Clock New Clk Ready IRCF <2:0> Select Old Select New System Clock Low Speed High Speed Old Clock Start-up Time(1) Clock Sync Running New Clock New Clk Ready IRCF <2:0>Select Old Select New System Clock Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode. DS40001303H-page 38  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 2.11 Fail-Safe Clock Monitor 2.11.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared by either one of the to continue operating should the external oscillator fail. following: The FSCM can detect oscillator failure any time after • Any Reset the Oscillator Start-up Timer (OST) has expired. The • By toggling the SCS1 bit of the OSCCON register FSCM is enabled by setting the FCMEN bit in the Both of these conditions restart the OST. While the CONFIG1H Configuration register. The FSCM is OST is running, the device continues to operate from applicable to all external oscillator modes (LP, XT, HS, the INTOSC selected in OSCCON. When the OST EC, RC and RCIO). times out, the Fail-Safe condition is cleared and the device automatically switches over to the external clock FIGURE 2-8: FSCM BLOCK DIAGRAM source. The Fail-Safe condition need not be cleared before the OSCFIF flag is cleared. Clock Monitor Latch External 2.11.4 RESET OR WAKE-UP FROM SLEEP S Q Clock The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after LFINTOSC Oscillator ÷ 64 R Q any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as 31 kHz 488 Hz soon as the Reset or wake-up has completed. When (~32 s) (~2 ms) the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing Sample Clock Clock code while the OST is operating. Failure Detected Note: Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting 2.11.1 FAIL-SAFE DETECTION Reset or Sleep). After an appropriate The FSCM module detects a failed oscillator by amount of time, the user should check the comparing the external oscillator to the FSCM sample OSTS bit of the OSCCON register to verify clock. The sample clock is generated by dividing the the oscillator start-up and that the system LFINTOSC by 64. See Figure2-8. Inside the fail clock switchover has successfully detector block is a latch. The external clock sets the completed. latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half- cycle of the sample clock elapses before the primary clock goes low. 2.11.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSCFIF of the PIR2 register. The OSCFIF flag will generate an interrupt if the OSCFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. An automatic transition back to the failed clock source will not occur. The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2010-2015 Microchip Technology Inc. DS40001303H-page 39

PIC18F2XK20/4XK20 FIGURE 2-9: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 2-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets(1) CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 — — INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000x OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0011 q000 0011 q000 OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 000u uuuu PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 0000 0000 0000 0000 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 0000 0000 0000 0000 IPR2 OSCFIP — — — — — — — 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS40001303H-page 40  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 3.0 POWER-MANAGED MODES 3.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three PIC18F2XK20/4XK20 devices offer a total of seven clock sources for power-managed modes. They are: operating modes for more efficient power management. These modes provide a variety of • the primary clock, as defined by the FOSC<3:0> options for selective power conservation in applications Configuration bits where resources may be limited (i.e., battery-powered • the secondary clock (the Timer1 oscillator) devices). • the internal oscillator block There are three categories of power-managed modes: 3.1.2 ENTERING POWER-MANAGED • Run modes MODES • Idle modes Switching from one power-managed mode to another • Sleep mode begins by loading the OSCCON register. The These categories define which portions of the device SCS<1:0> bits select the clock source and determine are clocked and sometimes, what speed. The Run and which Run or Idle mode is to be used. Changing these Idle modes may use any of the three available clock bits causes an immediate switch to the new clock sources (primary, secondary or internal oscillator source, assuming that it is running. The switch may block); the Sleep mode does not use a clock source. also be subject to clock transition delays. These are The power-managed modes include several discussed in Section3.1.3 “Clock Transitions and power-saving features offered on previous PIC® Status Indicators” and subsequent sections. microcontroller devices. One is the clock switching Entry to the power-managed Idle or Sleep modes is feature which allows the controller to use the Timer1 triggered by the execution of a SLEEP instruction. The oscillator in place of the primary oscillator. Also included actual mode that results depends on the status of the is the Sleep mode, offered by all PIC® microcontroller IDLEN bit of the OSCCON register. devices, where all device clocks are stopped. Depending on the current mode and the mode being switched to, a change to a power-managed mode does 3.1 Selecting Power-Managed Modes not always require setting all of these bits. Many Selecting a power-managed mode requires two transitions may be done by changing the oscillator select decisions: bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured • Whether or not the CPU is to be clocked correctly, it may only be necessary to perform a SLEEP • The selection of a clock source instruction to switch to the desired mode. The IDLEN bit of the OSCCON register controls CPU clocking, while the SCS<1:0> bits of the OSCCON register select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table3-1. TABLE 3-1: POWER-MANAGED MODES OSCCON Bits Module Clocking Mode Available Clock and Oscillator Source IDLEN(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC and Internal Oscillator Block(2). This is the normal full power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.  2010-2015 Microchip Technology Inc. DS40001303H-page 41

PIC18F2XK20/4XK20 3.1.3 CLOCK TRANSITIONS AND STATUS 3.2 Run Modes INDICATORS In the Run modes, clocks to both the core and The length of the transition between clock sources is peripherals are active. The difference between these the sum of: modes is the clock source. • Start-up time of the new clock 3.2.1 PRI_RUN MODE • Two and one half cycles of the old clock source • Two and one half cycles of the new clock The PRI_RUN mode is the normal, full power execution mode of the microcontroller. This is also the default Three flag bits indicate the current clock source and its mode upon a device Reset, unless Two-Speed Start-up status. They are: is enabled (see Section2.10 “Two-Speed Clock • OSTS (of the OSCCON register) Start-up Mode” for details). In this mode, the OSTS bit • IOFS (of the OSCCON register) is set. The IOFS bit will be set if the HFINTOSC is the primary clock source and the oscillator is stable (see • T1RUN (of the T1CON register) Section2.2 “Oscillator Control”). In general, only one of these bits will be set while in a given power-managed mode. Table3-2 shows the 3.2.2 SEC_RUN MODE relationship of the flags to the active main system clock The SEC_RUN mode is the mode compatible to the source. “clock switching” feature offered in other PIC18 devices. In this mode, the CPU and peripherals are TABLE 3-2: SYSTEM CLOCK INDICATORS clocked from the Timer1 oscillator. This gives users the OSTSIOFS T1RUN Main System Clock Source option of lower power consumption while still using a high accuracy clock source. 1 0 0 Primary Oscillator SEC_RUN mode is entered by setting the SCS<1:0> 0 1 0 HFINTOSC bits to ‘01’. When SEC_RUN mode is active all of the 0 0 1 Secondary Oscillator following are true: 1 1 0 HFINTOSC as primary clock • The main clock source is switched to the Timer1 LFINTOSC or oscillator 0 0 0 HFINTOSC is not yet stable • Primary oscillator is shut down . • T1RUN bit of the T1CON register is set • OSTS bit is cleared. Note1: Executing a SLEEP instruction does not necessarily place the device into Sleep Note: The Timer1 oscillator should already be mode. It acts as the trigger to place the running prior to entering SEC_RUN controller into either the Sleep mode or mode. If the T1OSCEN bit is not set when one of the Idle modes, depending on the the SCS<1:0> bits are set to ‘01’, entry to setting of the IDLEN bit. SEC_RUN mode will not occur until T1OSCEN bit is set and Timer1 oscillator 3.1.4 MULTIPLE FUNCTIONS OF THE is ready. SLEEP COMMAND On transitions from SEC_RUN mode to PRI_RUN, the The power-managed mode that is invoked with the peripherals and CPU continue to be clocked from the SLEEP instruction is determined by the setting of the Timer1 oscillator while the primary clock is started. IDLEN bit of the OSCCON register at the time the When the primary clock becomes ready, a clock switch instruction is executed. All clocks stop and minimum back to the primary clock occurs (see Figure2-7). power is consumed when SLEEP is executed with the When the clock switch is complete, the T1RUN bit is IDLEN bit cleared. The system clock continues to cleared, the OSTS bit is set and the primary clock is supply a clock to the peripherals but is disconnected providing the main system clock. The Timer1 oscillator from the CPU when SLEEP is executed with the IDLEN continues to run as long as the T1OSCEN bit is set. bit set. DS40001303H-page 42  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 3.2.3 RC_RUN MODE 3.3 Sleep Mode In RC_RUN mode, the CPU and peripherals are The Power-Managed Sleep mode in the PIC18F2XK20/ clocked from the internal oscillator block using one of 4XK20 devices is identical to the legacy Sleep mode the selections from the HFINTOSC multiplexer. In this offered in all other PIC® microcontroller devices. It is mode, the primary oscillator is shut down. RC_RUN entered by clearing the IDLEN bit (the default state on mode provides the best power conservation of all the device Reset) and executing the SLEEP instruction. Run modes when the LFINTOSC is the main clock This shuts down the selected oscillator (Figure3-1). All source. It works well for user applications which are not clock source Status bits are cleared. highly timing sensitive or do not require high-speed Entering the Sleep mode from any other mode does not clocks at all times. require a clock switch. This is because no clocks are If the primary clock source is the internal oscillator needed once the controller has entered Sleep. If the block (either LFINTOSC or HFINTOSC), there are no WDT is selected, the LFINTOSC source will continue to distinguishable differences between PRI_RUN and operate. If the Timer1 oscillator is enabled, it will also RC_RUN modes during execution. However, a clock continue to run. switch delay will occur during entry to and exit from When a wake event occurs in Sleep mode (by interrupt, RC_RUN mode. Therefore, if the primary clock source Reset or WDT time-out), the device will not be clocked is the internal oscillator block, the use of RC_RUN until the clock source selected by the SCS<1:0> bits mode is not recommended. See 2.9.3 “Clock Switch becomes ready (see Figure3-2), or it will be clocked Timing” for details about clock switching. from the internal oscillator block if either the Two-Speed RC_RUN mode is entered by setting the SCS1 bit to Start-up or the Fail-Safe Clock Monitor are enabled ‘1’. The SCS0 bit can be either ‘0’ or ‘1’ but should be (see Section23.0 “Special Features of the CPU”). In ‘0’ to maintain software compatibility with future either case, the OSTS bit is set when the primary clock devices. When the clock source is switched from the is providing the device clocks. The IDLEN and SCS bits primary oscillator to the HFINTOSC multiplexer, the are not affected by the wake-up. primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to 3.4 Idle Modes immediately change the clock speed. The Idle modes allow the controller’s CPU to be On transitions from RC_RUN mode to PRI_RUN mode, selectively shut down while the peripherals continue to the device continues to be clocked from the internal operate. Selecting a particular Idle mode allows users oscillator block while the primary oscillator is started. to further manage power consumption. When the primary oscillator becomes ready, a clock switch to the primary clock occurs. When the clock If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is switch is complete, the IOFS bit is cleared, the OSTS executed, the peripherals will be clocked from the clock bit is set and the primary oscillator is providing the main source selected by the SCS<1:0> bits; however, the CPU system clock. The HFINTOSC will continue to run if any will not be clocked. The clock source Status bits are not of the conditions noted in Section2.5.2 “HFINTOSC” affected. Setting IDLEN and executing a SLEEP instruc- are met. The LFINTOSC source will continue to run if tion provides a quick method of switching from a given any of the conditions noted in Section2.5.3 “LFIN- Run mode to its corresponding Idle mode. TOSC” are met. If the WDT is selected, the LFINTOSC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out, or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (parameter38, Table) while it becomes ready to exe- cute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits.  2010-2015 Microchip Technology Inc. DS40001303H-page 43

PIC18F2XK20/4XK20 FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS bit set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS40001303H-page 44  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 3.4.1 PRI_IDLE MODE 3.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes, in that it does not disable the primary device peripherals continue to be clocked from the Timer1 clock. For timing sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by the fastest resumption of device operation with its more setting the IDLEN bit and executing a SLEEP accurate primary clock source, since the clock source instruction. If the device is in another Run mode, set the does not have to “warm-up” or transition from another IDLEN bit first, then set the SCS<1:0> bits to ‘01’ and oscillator. execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut PRI_IDLE mode is entered from PRI_RUN mode by down, the OSTS bit is cleared and the T1RUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then clear the SCS bits and execute SLEEP. be clocked from the Timer1 oscillator. After an interval Although the CPU is disabled, the peripherals continue of TCSD following the wake event, the CPU begins exe- to be clocked from the primary clock source specified cuting code being clocked by the Timer1 oscillator. The by the FOSC<3:0> Configuration bits. The OSTS bit IDLEN and SCS bits are not affected by the wake-up; remains set (see Figure3.3). the Timer1 oscillator continues to run (see Figure3-4). When a wake event occurs, the CPU is clocked from the Note: The Timer1 oscillator should already be primary clock source. A delay of interval TCSD is running prior to entering SEC_IDLE required between the wake event and when code mode. If the T1OSCEN bit is not set when execution starts. This is required to allow the CPU to the SLEEP instruction is executed, the become ready to execute instructions. After the wake- main system clock will continue to operate up, the OSTS bit remains set. The IDLEN and SCS bits in the previously selected mode and the are not affected by the wake-up (see Figure3-4). corresponding IDLE mode will be entered (i.e., PRI_IDLE or RC_IDLE). FIGURE 3-3: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 3-4: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event  2010-2015 Microchip Technology Inc. DS40001303H-page 45

PIC18F2XK20/4XK20 3.4.3 RC_IDLE MODE 3.5.1 EXIT BY INTERRUPT In RC_IDLE mode, the CPU is disabled but the Any of the available interrupt sources can cause the peripherals continue to be clocked from the internal device to exit from an Idle mode or the Sleep mode to oscillator block from the HFINTOSC multiplexer output. a Run mode. To enable this functionality, an interrupt This mode allows for controllable power conservation source must be enabled by setting its enable bit in one during Idle periods. of the INTCON or PIE registers. The PEIE bit must also be set If the desired interrupt enable bit is in a PIE From RC_RUN, this mode is entered by setting the register. The exit sequence is initiated when the IDLEN bit and executing a SLEEP instruction. If the corresponding interrupt flag bit is set. device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. It is recommended The instruction immediately following the SLEEP that SCS0 also be cleared, although its value is instruction is executed on all exits by interrupt from Idle ignored, to maintain software compatibility with future or Sleep modes. Code execution then branches to the devices. The HFINTOSC multiplexer may be used to interrupt vector if the GIE/GIEH bit of the INTCON select a higher clock frequency by modifying the IRCF register is set, otherwise code execution continues bits before executing the SLEEP instruction. When the without branching (see Section9.0 “Interrupts”). clock source is switched to the HFINTOSC multiplexer, A fixed delay of interval TCSD following the wake event the primary oscillator is shut down and the OSTS bit is is required when leaving Sleep and Idle modes. This cleared. delay is required for the CPU to prepare for execution. If the IRCF bits are set to any non-zero value, or the Instruction execution resumes on the first clock cycle INTSRC bit is set, the HFINTOSC output is enabled. following this delay. The IOFS bit becomes set, after the HFINTOSC output becomes stable, after an interval of TIOBST 3.5.2 EXIT BY WDT TIME-OUT (parameter39, Table). Clocks to the peripherals con- A WDT time-out will cause different actions depending tinue while the HFINTOSC source stabilizes. If the on which power-managed mode the device is in when IRCF bits were previously at a non-zero value, or the time-out occurs. INTSRC was set before the SLEEP instruction was exe- If the device is not executing code (all Idle modes and cuted and the HFINTOSC source was already stable, Sleep mode), the time-out will result in an exit from the the IOFS bit will remain set. If the IRCF bits and power-managed mode (see Section3.2 “Run INTSRC are all clear, the HFINTOSC output will not be Modes” and Section3.3 “Sleep Mode”). If the device enabled, the IOFS bit will remain clear and there will be is executing code (all Run modes), the time-out will no indication of the current clock source. result in a WDT Reset (see Section23.2 “Watchdog When a wake event occurs, the peripherals continue to Timer (WDT)”). be clocked from the HFINTOSC multiplexer output. The WDT timer and postscaler are cleared by any one After a delay of TCSD following the wake event, the CPU of the following: begins executing code being clocked by the HFINTOSC multiplexer. The IDLEN and SCS bits are • executing a SLEEP instruction not affected by the wake-up. The LFINTOSC source • executing a CLRWDT instruction will continue to run if either the WDT or the Fail-Safe • the loss of the currently selected clock source Clock Monitor is enabled. when the Fail-Safe Clock Monitor is enabled • modifying the IRCF bits in the OSCCON register 3.5 Exiting Idle and Sleep Modes when the internal oscillator block is the device An exit from Sleep mode or any of the Idle modes is clock source triggered by any one of the following: 3.5.3 EXIT BY RESET • an interrupt Exiting Sleep and Idle modes by Reset causes code • a Reset execution to restart at address 0. See Section4.0 • a watchdog time-out “Reset” for more details. This section discusses the triggers that cause exits The exit delay time from Reset to the start of code from power-managed modes. The clocking subsystem execution depends on both the clock sources before actions are discussed in each of the power-managed and after the wake-up and the type of oscillator. Exit modes (see Section3.2 “Run Modes”, Section3.3 delays are summarized in Table3-3. “Sleep Mode” and Section3.4 “Idle Modes”). DS40001303H-page 46  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 3.5.4 EXIT WITHOUT AN OSCILLATOR In these instances, the primary clock source either START-UP DELAY does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not Certain exits from power-managed modes do not require an oscillator start-up delay (RC, EC, INTOSC, invoke the OST at all. There are two cases: and INTOSCIO modes). However, a fixed delay of • PRI_IDLE mode, where the primary clock source interval TCSD following the wake event is still required is not stopped and when leaving Sleep and Idle modes to allow the CPU • the primary clock source is not any of the LP, XT, to prepare for execution. Instruction execution resumes HS or HSPLL modes. on the first clock cycle following this delay. TABLE 3-3: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Clock Source Clock Ready Status Exit Delay before Wake-up after Wake-up Bit (OSCCON) LP, XT, HS Primary Device Clock HSPLL OSTS TCSD(1) (PRI_IDLE mode) EC, RC HFINTOSC(2) IOFS LP, XT, HS TOST(3) T1OSC or LFINTOSC(1) HSPLL TOST + tPLL(3) OSTS EC, RC TCSD(1) HFINTOSC(1) TIOBST(4) IOFS LP, XT, HS TOST(4) HFINTOSC(2) HSPLL TOST + tPLL(3) OSTS EC, RC TCSD(1) HFINTOSC(1) None IOFS LP, XT, HS TOST(3) None HSPLL TOST + tPLL(3) OSTS (Sleep mode) EC, RC TCSD(1) HFINTOSC(1) TIOBST(4) IOFS Note 1: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section3.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz. 2: Includes both the HFINTOSC 16MHz source and postscaler derived frequencies. 3: TOST is the Oscillator Start-up Timer (parameter 32). tPLL is the PLL Lock-out Timer (parameter F12). 4: Execution continues during the HFINTOSC stabilization period, TIOBST (parameter 39).  2010-2015 Microchip Technology Inc. DS40001303H-page 47

PIC18F2XK20/4XK20 4.0 RESET A simplified block diagram of the On-Chip Reset Circuit is shown in Figure4-1. The PIC18F2XK20/4XK20 devices differentiate between various kinds of Reset: 4.1 RCON Register a) Power-on Reset (POR) Device Reset events are tracked through the RCON b) MCLR Reset during normal operation register (Register4-1). The lower five bits of the regis- c) MCLR Reset during power-managed modes ter indicate that a specific Reset event has occurred. In d) Watchdog Timer (WDT) Reset (during most cases, these bits can only be cleared by the event execution) and must be set by the application after the event. The e) Programmable Brown-out Reset (BOR) state of these flag bits, taken together, can be read to f) RESET Instruction indicate the type of Reset that just occurred. This is described in more detail in Section4.6 “Reset State g) Stack Full Reset of Registers”. h) Stack Underflow Reset The RCON register also has control bits for setting This section discusses Resets generated by MCLR, interrupt priority (IPEN) and software control of the POR and BOR and covers the operation of the various BOR (SBOREN). Interrupt priority is discussed in start-up timers. Stack Reset events are covered in Section9.0 “Interrupts”. BOR is covered in Section5.1.2.4 “Stack Full and Underflow Resets”. Section4.4 “Brown-out Reset (BOR)”. WDT Resets are covered in Section23.2 “Watchdog Timer (WDT)”. FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD POR Detect VDD Brown-out Reset BOREN S OST/PWRT OST(2) 1024 Cycles Chip_Reset 10-bit Ripple Counter R Q OSC1 32 s PWRT(2) 65.5 ms LFINTOSC 11-bit Ripple Counter Enable PWRT Enable OST(1) Note 1: See Table4-2 for time-out situations. 2: PWRT and OST counters are reset by POR and BOR. See Sections 4.3 and 4.4. DS40001303H-page 48  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN(1) — RI TO PD POR(2) BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN<1:0> = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN<1:0> = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware or Power-on Reset) 0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a code-executed Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit(3) 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs) Note 1: When CONFIG2L[2:1] = 01, then the SBOREN Reset state is ‘1’; otherwise, it is ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section4.6 “Reset State of Registers” for additional information. 3: See Table4-3. Note1: Brown-out Reset is indicated when BOR is ‘0’ and POR is ‘1’ (assuming that both POR and BOR were set to ‘1’ by firmware immediately after POR). 2: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected.  2010-2015 Microchip Technology Inc. DS40001303H-page 49

PIC18F2XK20/4XK20 4.2 Master Clear (MCLR) FIGURE 4-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering an SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small VDD VDD pulses. PIC® MCU The MCLR pin is not driven low by any internal Resets, D R including the WDT. R1 MCLR In PIC18F2XK20/4XK20 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When C MCLR is disabled, the pin becomes a digital input. See Section10.6 “PORTE, TRISE and LATE Registers” for more information. Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. 4.3 Power-on Reset (POR) The diode D helps discharge the capacitor A Power-on Reset pulse is generated on-chip quickly when VDD powers down. whenever VDD rises above a certain threshold. This 2: 15 k < R < 40k is recommended to make sure that the voltage drop across R does not allows the device to start in the initialized state when violate the device’s electrical specification. VDD is adequate for operation. 3: R1  1 k will limit any current flowing into To take advantage of the POR circuitry, tie the MCLR MCLR from external capacitor C, in the event pin through a resistor to VDD. This will eliminate exter- of MCLR/VPP pin breakdown, due to nal RC components usually needed to create a Electrostatic Discharge (ESD) or Electrical Power-on Reset delay. A minimum rise rate for VDD is Overstress (EOS). specified (parameter D004). For a slow rise time, see Figure4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure proper operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit of the RCON register. The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user must manually set the bit to ‘1’ by software following any POR. DS40001303H-page 50  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 4.4 Brown-out Reset (BOR) 4.4.2 SOFTWARE ENABLED BOR PIC18F2XK20/4XK20 devices implement a BOR circuit When BOREN<1:0> = 01, the BOR can be enabled or that provides the user with a number of configuration and disabled by the user in software. This is done with the power-saving options. The BOR is controlled by the SBOREN control bit of the RCON register. Setting BORV<1:0> and BOREN<1:0> bits of the CONFIG2L SBOREN enables the BOR to function as previously Configuration register. There are a total of four BOR described. Clearing SBOREN disables the BOR configurations which are summarized in Table4-1. entirely. The SBOREN bit operates only in this mode; otherwise it is read as ‘0’. The BOR threshold is set by the BORV<1:0> bits. If BOR is enabled (any values of BOREN<1:0>, except Placing the BOR under software control gives the user ‘00’), any drop of VDD below VBOR (parameterD005) the additional flexibility of tailoring the application to its for greater than TBOR (parameter35) will reset the environment without having to reprogram the device to device. A Reset may or may not occur if VDD falls below change BOR configuration. It also allows the user to VBOR for less than TBOR. The chip will remain in tailor device power consumption in software by Brown-out Reset until VDD rises above VBOR. eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, If the Power-up Timer is enabled, it will be invoked after it may have some impact in low-power applications. VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT Note: Even when BOR is under software (parameter33). If VDD drops below VBOR while the control, the BOR Reset voltage level is still Power-up Timer is running, the chip will go back into a set by the BORV<1:0> Configuration bits. Brown-out Reset and the Power-up Timer will be It cannot be changed by software. initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. 4.4.3 DISABLING BOR IN SLEEP MODE BOR and the Power-on Timer (PWRT) are When BOREN<1:0> = 10, the BOR remains under independently configured. Enabling BOR Reset does hardware control and operates as previously not automatically enable the PWRT. described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the The BOR circuit has an output that feeds into the POR device returns to any other operating mode, BOR is circuit and rearms the POR within the operating range automatically re-enabled. of the BOR. This early rearming of the POR ensures that the device will remain in Reset in the event that VDD This mode allows for applications to recover from falls below the operating range of the BOR circuitry. brown-out situations, while actively executing code, when the device requires BOR protection the most. At 4.4.1 DETECTING BOR the same time, it saves additional power in Sleep mode When BOR is enabled, the BOR bit always resets to ‘0’ by eliminating the small incremental BOR current. on any BOR or POR event. This makes it difficult to 4.4.4 MINIMUM BOR ENABLE TIME determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to Enabling the BOR also enables the Fixed Voltage simultaneously check the state of both POR and BOR. Reference (FVR) when no other peripheral requiring the This assumes that the POR and BOR bits are reset to FVR is active. The BOR becomes active only after the ‘1’ by software immediately after any POR event. If FVR stabilizes. Therefore, to ensure BOR protection, BOR is ‘0’ while POR is ‘1’, it can be reliably assumed the FVR settling time must be considered when that a BOR event has occurred. enabling the BOR in software or when the BOR is automatically enabled after waking from Sleep. If the BOR is disabled, in software or by reentering Sleep before the FVR stabilizes, the BOR circuit will not sense a BOR condition. The FVRST bit of the CVRCON2 register can be used to determine FVR stability. TABLE 4-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN BOR Operation BOREN1 BOREN0 (RCON<6>) 0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR enabled by software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled by hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled by hardware; must be disabled by reprogramming the Configuration bits.  2010-2015 Microchip Technology Inc. DS40001303H-page 51

PIC18F2XK20/4XK20 4.5 Device Reset Timers The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit PIC18F2XK20/4XK20 devices incorporate three from all power-managed modes that stop the external separate on-chip timers that help regulate the oscillator. Power-on Reset process. Their main function is to ensure that the device clock is stable before code is 4.5.3 PLL LOCK TIME-OUT executed. These timers are: With the PLL enabled in its PLL mode, the time-out • Power-up Timer (PWRT) sequence following a Power-on Reset is slightly • Oscillator Start-up Timer (OST) different from other oscillator modes. A separate timer • PLL Lock Time-out is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This 4.5.1 POWER-UP TIMER (PWRT) PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. The Power-up Timer (PWRT) of PIC18F2XK20/4XK20 devices is an 11-bit counter 4.5.4 TIME-OUT SEQUENCE which uses the LFINTOSC source as the clock input. This yields an approximate time interval of On power-up, the time-out sequence is as follows: 2048x32s=65.6ms. While the PWRT is counting, 1. After the POR pulse has cleared, PWRT time-out the device is held in Reset. is invoked (if enabled). The power-up time delay depends on the LFINTOSC 2. Then, the OST is activated. clock and will vary from chip-to-chip due to temperature The total time-out will vary based on oscillator and process variation. See DC parameter 33 for configuration and the status of the PWRT. Figure4-3, details. Figure4-4, Figure4-5, Figure4-6 and Figure4-7 all The PWRT is enabled by clearing the PWRTEN depict time-out sequences on power-up, with the Configuration bit. Power-up Timer enabled and the device operating in HS Oscillator mode. Figures 4-3 through 4-6 also 4.5.2 OSCILLATOR START-UP TIMER apply to devices operating in XT or LP modes. For (OST) devices in RC mode and with the PWRT disabled, on the other hand, there will be no time-out at all. The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the Since the time-outs occur from the POR pulse, if MCLR PWRT delay is over (parameter 33). This ensures that is kept low long enough, all time-outs will expire, after the crystal oscillator or resonator has started and which, bringing MCLR high will allow program stabilized. execution to begin immediately (Figure4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXK20 device operating in parallel. TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Exit from Configuration Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) — — RC, RCIO 66 ms(1) — — INTIO1, INTIO2 66 ms(1) — — Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. DS40001303H-page 52  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  2010-2015 Microchip Technology Inc. DS40001303H-page 53

PIC18F2XK20/4XK20 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL  2 ms max. First three stages of the PWRT timer. DS40001303H-page 54  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 4.6 Reset State of Registers Table4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Some registers are unaffected by a Reset. Their status Power-on and Brown-out Resets, Master Clear and is unknown on POR and unchanged by all other WDT Resets and WDT wake-ups. Resets. All other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table4-3. These bits are used by software to determine the nature of the Reset. TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter SBOREN RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u(2) 0 u u u u u u Brown-out Reset 0000h u(2) 1 1 1 u 0 u u MCLR during Power-Managed 0000h u(2) u 1 u u u u u Run Modes MCLR during Power-Managed 0000h u(2) u 1 0 u u u u Idle Modes and Sleep Mode WDT Time-out during Full Power 0000h u(2) u 0 u u u u u or Power-Managed Run Mode MCLR during Full Power 0000h u(2) u u u u u u u Execution Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset 0000h u(2) u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u(2) u u u u u u 1 actual Reset, STVREN = 0) WDT Time-out during PC + 2 u(2) u 0 0 u u u u Power-Managed Idle or Sleep Modes Interrupt Exit from PC + 2(1) u(2) u u 0 u u u u Power-Managed Modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled (BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’.  2010-2015 Microchip Technology Inc. DS40001303H-page 55

PIC18F2XK20/4XK20 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets TOSU PIC18F2XK20 PIC18F4XK20 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu(3) TOSL PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu(3) STKPTR PIC18F2XK20 PIC18F4XK20 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU PIC18F2XK20 PIC18F4XK20 ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu PCL PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F2XK20 PIC18F4XK20 --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F2XK20 PIC18F4XK20 0000 000x 0000 000u uuuu uuuu(1) INTCON2 PIC18F2XK20 PIC18F4XK20 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 PIC18F2XK20 PIC18F4XK20 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A POSTINC0 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A POSTDEC0 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A PREINC0 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A PLUSW0 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A FSR0H PIC18F2XK20 PIC18F4XK20 ---- 0000 ---- 0000 ---- uuuu FSR0L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A POSTINC1 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A POSTDEC1 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A PREINC1 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A PLUSW1 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’. DS40001303H-page 56  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets FSR1H PIC18F2XK20 PIC18F4XK20 ---- 0000 ---- 0000 ---- uuuu FSR1L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F2XK20 PIC18F4XK20 ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A POSTINC2 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A POSTDEC2 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A PREINC2 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A PLUSW2 PIC18F2XK20 PIC18F4XK20 N/A N/A N/A FSR2H PIC18F2XK20 PIC18F4XK20 ---- 0000 ---- 0000 ---- uuuu FSR2L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F2XK20 PIC18F4XK20 ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu TMR0L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F2XK20 PIC18F4XK20 0011 qq00 0011 qq00 uuuu uuuu HLVDCON PIC18F2XK20 PIC18F4XK20 0-00 0101 0-00 0101 u-uu uuuu WDTCON PIC18F2XK20 PIC18F4XK20 ---- ---0 ---- ---0 ---- ---u RCON(4) PIC18F2XK20 PIC18F4XK20 0q-1 11q0 0u-q qquu uu-u qquu TMR1H PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F2XK20 PIC18F4XK20 0000 0000 u0uu uuuu uuuu uuuu TMR2 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 1111 1111 T2CON PIC18F2XK20 PIC18F4XK20 -000 0000 -000 0000 -uuu uuuu SSPBUF PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu SSPSTAT PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu SSPCON1 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu SSPCON2 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.  2010-2015 Microchip Technology Inc. DS40001303H-page 57

PIC18F2XK20/4XK20 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets ADRESH PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F2XK20 PIC18F4XK20 --00 0000 --00 0000 --uu uuuu ADCON1 PIC18F2XK20 PIC18F4XK20 --00 0qqq --00 0qqq --uu uuuu ADCON2 PIC18F2XK20 PIC18F4XK20 0-00 0000 0-00 0000 u-uu uuuu CCPR1H PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F2XK20 PIC18F4XK20 --00 0000 --00 0000 --uu uuuu PSTRCON PIC18F2XK20 PIC18F4XK20 ---0 0001 ---0 0001 ---u uuuu BAUDCON PIC18F2XK20 PIC18F4XK20 0100 0-00 0100 0-00 uuuu u-uu PWM1CON PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu ECCP1AS PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu CVRCON PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu CVRCON2 PIC18F2XK20 PIC18F4XK20 00-- ---- 00-- ---- uu-- ---- TMR3H PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F2XK20 PIC18F4XK20 0000 0000 uuuu uuuu uuuu uuuu SPBRGH PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu SPBRG PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu RCREG PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu TXREG PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu TXSTA PIC18F2XK20 PIC18F4XK20 0000 0010 0000 0010 uuuu uuuu RCSTA PIC18F2XK20 PIC18F4XK20 0000 000x 0000 000x uuuu uuuu EEADR PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu EEADRH PIC18F26K20 PIC18F46K20 ---- --00 ---- --00 ---- --uu EEDATA PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu EECON2 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 0000 0000 EECON1 PIC18F2XK20 PIC18F4XK20 xx-0 x000 uu-0 u000 uu-0 u000 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’. DS40001303H-page 58  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets IPR2 PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu PIR2 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu(1) PIE2 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu IPR1 PIC18F2XK20 PIC18F4XK20 -111 1111 -111 1111 -uuu uuuu PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu(1) PIR1 PIC18F2XK20 PIC18F4XK20 -000 0000 -000 0000 -uuu uuuu(1) PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu PIE1 PIC18F2XK20 PIC18F4XK20 -000 0000 -000 0000 -uuu uuuu OSCTUNE PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu TRISE PIC18F2XK20 PIC18F4XK20 ---- -111 ---- -111 ---- -uuu TRISD PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu TRISA(5) PIC18F2XK20 PIC18F4XK20 1111 1111(5) 1111 1111(5) uuuu uuuu(5) LATE PIC18F2XK20 PIC18F4XK20 ---- -xxx ---- -uuu ---- -uuu LATD PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu LATC PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) PIC18F2XK20 PIC18F4XK20 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) PIC18F2XK20 PIC18F4XK20 ---- x000 ---- u000 ---- uuuu PORTE PIC18F2XK20 PIC18F4XK20 ---- x--- ---- u--- ---- u--- PORTD PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC18F2XK20 PIC18F4XK20 xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F2XK20 PIC18F4XK20 xxx0 0000 uuu0 0000 uuuu uuuu PORTA(5) PIC18F2XK20 PIC18F4XK20 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) ANSELH(6) PIC18F2XK20 PIC18F4XK20 ---1 1111 ---1 1111 ---u uuuu ANSEL PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu IOCB PIC18F2XK20 PIC18F4XK20 0000 ---- 0000 ---- uuuu ---- WPUB PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu CM1CON0 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu CM2CON0 PIC18F2XK20 PIC18F4XK20 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.  2010-2015 Microchip Technology Inc. DS40001303H-page 59

PIC18F2XK20/4XK20 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets CM2CON1 PIC18F2XK20 PIC18F4XK20 0000 ---- 0000 ---- uuuu ---- SLRCON PIC18F2XK20 PIC18F4XK20 ---1 1111 ---1 1111 ---u uuuu SSPMSK PIC18F2XK20 PIC18F4XK20 1111 1111 1111 1111 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’. DS40001303H-page 60  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 5.0 MEMORY ORGANIZATION 5.1 Program Memory Organization There are three types of memory in PIC18 Enhanced PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address will return all ‘0’s (a • Data EEPROM NOP instruction). As Harvard architecture devices, the data and program This family of devices contain the following: memories use separate busses; this allows for • PIC18F23K20, PIC18F43K20: 8Kbytes of Flash concurrent access of the two memory spaces. The data Memory, up to 4,096 single-word instructions EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed • PIC18F24K20, PIC18F44K20: 16Kbytes of Flash through a set of control registers. Memory, up to 8,192 single-word instructions • PIC18F25K20, PIC18F45K20: 32Kbytes of Flash Additional detailed information on the operation of the Memory, up to 16,384 single-word instructions Flash program memory is provided in Section6.0 • PIC18F26K20, PIC18F46K20: 64Kbytes of Flash “Flash Program Memory”. Data EEPROM is Memory, up to 37,768 single-word instructions discussed separately in Section7.0 “Data EEPROM Memory”. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory map for PIC18F2XK20/4XK20 devices is shown in Figure5-1. Memory block details are shown in Figure23-2. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2XK20/4XK20 DEVICES PC<20:0> CALL,RCALL,RETURN 21 RETFIE,RETLW Stack Level 1    Stack Level 31 Reset Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory 1FFFh On-Chip Program Memory 2000h 3FFFh On-Chip PIC18F23K20/ Program Memory 4000h 43K20 e On-Chip c PIC18F24K20/ a Program Memory p 44K20 S y 7FFFh or 8000h m e M PIC18F25K20/ er s 45K20 U FFFFh 10000h Read ‘0’ Read ‘0’ Read ‘0’ PIC18F26K20/ 46K20 Read ‘0’ 1FFFFFh 200000h  2010-2015 Microchip Technology Inc. DS40001303H-page 61

PIC18F2XK20/4XK20 5.1.1 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and is contained in three separate 8-bit registers. The the stack is readable and writable through the Top-of- low byte, known as the PCL register, is both readable Stack (TOS) Special File Registers. Data can also be and writable. The high byte, or PCH register, contains pushed to, or popped from the stack, using these the PC<15:8> bits; it is not directly readable or writable. registers. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack; register contains the PC<20:16> bits; it is also not the Stack Pointer is first incremented and the location directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the register are performed through the PCLATU register. contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred a pop from the stack; the contents of the location to the program counter by any operation that writes pointed to by the STKPTR are transferred to the PC PCL. Similarly, the upper two bytes of the program and then the Stack Pointer is decremented. counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all offsets to the PC (see Section5.1.4.1 “Computed Resets. There is no RAM associated with the location GOTO”). corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is The PC addresses bytes in the program memory. To full or has overflowed or has underflowed. prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to 5.1.2.1 Top-of-Stack Access a value of ‘0’. The PC increments by two to address sequential instructions in the program memory. Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, The CALL, RCALL, GOTO and program branch hold the contents of the stack location pointed to by the instructions write to the program counter directly. For STKPTR register (Figure5-2). This allows users to these instructions, the contents of PCLATH and implement a software stack if necessary. After a CALL, PCLATU are not transferred to the program counter. RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These 5.1.2 RETURN ADDRESS STACK values can be placed on a user defined software stack. At The return address stack allows any combination of up return time, the software can return these values to to 31 program calls and interrupts to occur. The PC is TOSU:TOSH:TOSL and do a return. pushed onto the stack when a CALL or RCALL The user must disable the global interrupt enable bits instruction is executed or an interrupt is Acknowledged. while accessing the stack to prevent inadvertent stack The PC value is pulled off the stack on a RETURN, corruption. RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> 11111 11110 Top-of-Stack Registers Stack Pointer 11101 TOSU TOSH TOSL STKPTR<4:0> 00h 1Ah 34h 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 DS40001303H-page 62  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 5.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The STKPTR register (Register5-1) contains the Stack to the PC and sets the STKUNF bit, while the Stack Pointer value, the STKFUL (stack full) Status bit and Pointer remains at zero. The STKUNF bit will remain the STKUNF (stack underflow) Status bits. The value of set until cleared by software or until a POR occurs. the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System (RTOS) for return stack maintenance. not the same as a Reset, as the contents After the PC is pushed onto the stack 31 times (without of the SFRs are not affected. popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a 5.1.2.3 PUSH and POP Instructions POR. Since the Top-of-Stack is readable and writable, the The action that takes place when the stack becomes ability to push values onto the stack and pull values off full depends on the state of the STVREN (Stack Over- the stack without disturbing normal program execution flow Reset Enable) Configuration bit. (Refer to is a desirable feature. The PIC18 instruction set Section23.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control. (default), the 31st push will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data onto the stack, set the STKFUL bit and reset the or a return address on the stack. device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto Pointer will be set to zero. the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st push and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by Any additional pushes will not overwrite the 31st push decrementing the Stack Pointer. The previous value and STKPTR will remain at 31. pushed onto the stack then becomes the TOS value. REGISTER 5-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.  2010-2015 Microchip Technology Inc. DS40001303H-page 63

PIC18F2XK20/4XK20 5.1.2.4 Stack Full and Underflow Resets 5.1.4 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in There may be programming situations that require the Configuration Register 4L. When STVREN is set, a full creation of data structures, or look-up tables, in or underflow will set the appropriate STKFUL or program memory. For PIC18 devices, look-up tables STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit but not cause • Table Reads a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 5.1.4.1 Computed GOTO 5.1.3 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in A fast register stack is provided for the Status, WREG Example5-2. and BSR registers, to provide a “fast return” option for interrupts. The stack for each register is only one level A look-up table can be formed with an ADDWF PCL deep and is neither readable nor writable. It is loaded instruction and a group of RETLW nn instructions. The with the current value of the corresponding register W register is loaded with an offset into the table before when the processor vectors for an interrupt. All inter- executing a call to that table. The first instruction of the rupt sources will push values into the stack registers. called routine is the ADDWF PCL instruction. The next The values in the registers are then loaded back into instruction executed will be one of the RETLW nn their associated registers if the RETFIE, FAST instructions that returns the value ‘nn’ to the calling instruction is used to return from the interrupt. function. If both low and high priority interrupts are enabled, the The offset value (in WREG) specifies the number of stack registers cannot be used reliably to return from bytes that the program counter should advance and low priority interrupts. If a high priority interrupt occurs should be multiples of 2 (LSb = 0). while servicing a low priority interrupt, the stack register In this method, only one data byte may be stored in values stored by the low priority interrupt will be each instruction location and room on the return overwritten. In these cases, users must save the key address stack is required. registers by software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 5-2: COMPUTED GOTO USING fast register stack for returns from interrupt. If no AN OFFSET VALUE interrupts are used, the fast register stack can be used MOVF OFFSET, W to restore the Status, WREG and BSR registers at the CALL TABLE end of a subroutine call. To use the fast register stack ORG nn00h for a subroutine call, a CALL label, FAST instruction TABLE ADDWF PCL must be executed to save the Status, WREG and BSR RETLW nnh registers to the fast register stack. A RETURN, FAST RETLW nnh instruction is then executed to restore these registers RETLW nnh from the fast register stack. . . Example5-1 shows a source code example that uses . the fast register stack during a subroutine call and return. 5.1.4.2 Table Reads and Table Writes EXAMPLE 5-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per ;STACK program word by using table reads and writes. The  Table Pointer (TBLPTR) register specifies the byte  address and the Table Latch (TABLAT) register contains the data that is read from or written to program SUB1  memory. Data is transferred to or from program  memory one byte at a time. RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK Table read and table write operations are discussed further in Section6.1 “Table Reads and Table Writes”. DS40001303H-page 64  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 5.2 PIC18 Instruction Cycle 5.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 5.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are The microcontroller clock input, whether from an pipelined in such a manner that a fetch takes one internal or external source, is internally divided by four instruction cycle, while the decode and execute take to generate four non-overlapping quadrature clocks another instruction cycle. However, due to the (Q1, Q2, Q3 and Q4). Internally, the program counter is pipelining, each instruction effectively executes in one incremented on every Q1; the instruction is fetched cycle. If an instruction causes the program counter to from the program memory and latched into the change (e.g., GOTO), then two cycles are required to instruction register during Q4. The instruction is complete the instruction (Example5-3). decoded and executed during the following Q1 through A fetch cycle begins with the Program Counter (PC) Q4. The clocks and instruction execution flow are incrementing in Q1. shown in Figure5-3. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 5-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKOUT (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.  2010-2015 Microchip Technology Inc. DS40001303H-page 65

PIC18F2XK20/4XK20 5.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruction. Since instructions are always stored on word The program memory is addressed in bytes. boundaries, the data contained in the instruction is a Instructions are stored as either two bytes or four bytes word address. The word address is written to PC<20:1>, in program memory. The Least Significant Byte of an which accesses the desired byte address in program instruction word is always stored in a program memory memory. Instruction #2 in Figure5-4 shows how the location with an even address (LSb = 0). To maintain instruction GOTO 0006h is encoded in the program alignment with instruction boundaries, the PC memory. Program branch instructions, which encode a increments in steps of 2 and the LSb will always read relative address offset, operate in the same manner. The ‘0’ (see Section5.1.1 “Program Counter”). offset value stored in a branch instruction represents the Figure5-4 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section24.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0  Program Memory 000000h Byte Locations  000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 5.2.4 TWO-WORD INSTRUCTIONS and used by the instruction sequence. If the first word is skipped for some reason and the second word is The standard PIC18 instruction set has four two-word executed by itself, a NOP is executed instead. This is instructions: CALL, MOVFF, GOTO and LSFR. In all necessary for cases when the two-word instruction is cases, the second word of the instruction always has preceded by a conditional instruction that changes the ‘1111’ as its four Most Significant bits; the other 12 bits PC. Example5-4 shows how this works. are literal data, usually a data memory address. Note: See Section5.6 “PIC18 Instruction The use of ‘1111’ in the 4 MSbs of an instruction Execution and the Extended Instruc- specifies a special form of NOP. If the instruction is tion Set” for information on two-word executed in proper sequence – immediately after the instructions in the extended instruction set. first word – the data in the second word is accessed EXAMPLE 5-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code DS40001303H-page 66  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 5.3 Data Memory Organization 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section5.5 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit 12-bit address, allowing up to 4096 bytes of data low-order address and a 4-bit Bank Pointer. memory. The memory space is divided into as many as Most instructions in the PIC18 instruction set make use 16banks that contain 256 bytes each. Figures 5-5 of the Bank Pointer, known as the Bank Select Register through 5-7 show the data memory organization for the (BSR). This SFR holds the four Most Significant bits of PIC18F2XK20/4XK20 devices. a location’s address; the instruction itself includes the The data memory contains Special Function Registers eight Least Significant bits. Only the four lower bits of (SFRs) and General Purpose Registers (GPRs). The the BSR are implemented (BSR<3:0>). The upper four SFRs are used for control and status of the controller bits are unused; they will always read ‘0’ and cannot be and peripheral functions, while GPRs are used for data written to. The BSR can be loaded directly by using the storage and scratchpad operations in the user’s MOVLB instruction. application. Any read of an unimplemented location will The value of the BSR indicates the bank in data read as ‘0’s. memory; the eight bits in the instruction show the The instruction set and architecture allow operations location in the bank and can be thought of as an offset across all banks. The entire data memory may be from the bank’s lower boundary. The relationship accessed by Direct, Indirect or Indexed Addressing between the BSR’s value and the bank division in data modes. Addressing modes are discussed later in this memory is shown in Figures 5-5 through 5-7. subsection. Since up to 16 registers may share the same low-order To ensure that commonly used registers (SFRs and address, the user must always be careful to ensure that select GPRs) can be accessed in a single cycle, PIC18 the proper bank is selected before performing a data devices implement an Access Bank. This is a 256-byte read or write. For example, writing what should be memory space that provides fast access to SFRs and program data to an 8-bit address of F9h while the BSR the lower portion of GPR Bank 0 without using the Bank is 0Fh will end up resetting the program counter. Select Register (BSR). Section5.3.2 “Access Bank” While any bank can be selected, only those banks that provides a detailed description of the Access RAM. are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory maps in Figures 5-5 through 5-7 indicate which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers.  2010-2015 Microchip Technology Inc. DS40001303H-page 67

PIC18F2XK20/4XK20 FIGURE 5-5: DATA MEMORY MAP FOR PIC18F23K20/43K20 DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 96 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 160 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 FFh 4FFh = 0101 00h 500h Bank 5 FFh 5FFh = 0110 00h 600h Bank 6 Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low 5Fh FFh 7FFh Access RAM High 60h = 1000 00h 800h (SFRs) FFh Bank 8 FFh 8FFh = 1001 00h Unused 900h Bank 9 Read 00h FFh 9FFh = 1010 00h A00h Bank 10 FFh AFFh = 1011 00h B00h Bank 11 FFh BFFh C00h = 1100 00h Bank 12 CFFh FFh D00h = 1101 00h Bank 13 DFFh FFh 00h E00h = 1110 Bank 14 FFh EFFh = 1111 00h Unused FF50F0hh Bank 15 F60h FFh SFR FFFh DS40001303H-page 68  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F24K20/44K20 DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 96 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 160 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 FFh 4FFh = 0101 00h 500h Bank 5 FFh 5FFh = 0110 00h 600h Bank 6 Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low 5Fh FFh 7FFh Access RAM High 60h = 1000 00h 800h (SFRs) FFh Bank 8 FFh 8FFh = 1001 00h Unused 900h Bank 9 Read 00h FFh 9FFh = 1010 00h A00h Bank 10 FFh AFFh = 1011 00h B00h Bank 11 FFh BFFh C00h = 1100 00h Bank 12 CFFh FFh D00h = 1101 00h Bank 13 DFFh FFh 00h E00h = 1110 Bank 14 FFh EFFh = 1111 00h Unused FF50F0hh Bank 15 F60h FFh SFR FFFh  2010-2015 Microchip Technology Inc. DS40001303H-page 69

PIC18F2XK20/4XK20 FIGURE 5-7: DATA MEMORY MAP FOR PIC18F25K20/45K20 DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 96 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 160 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank GPR used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 GPR FFh 4FFh = 0101 00h 500h Bank 5 GPR FFh 5FFh = 0110 00h 600h Bank 6 Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low 5Fh FFh 7FFh Access RAM High 60h = 1000 00h 800h (SFRs) FFh Bank 8 FFh 8FFh = 1001 00h 900h Bank 9 FFh 9FFh = 1010 00h Unused A00h Bank 10 Read 00h FFh AFFh = 1011 00h B00h Bank 11 FFh BFFh C00h = 1100 00h Bank 12 CFFh FFh D00h = 1101 00h Bank 13 DFFh FFh 00h E00h = 1110 Bank 14 FFh EFFh = 1111 00h Unused FF50F0hh Bank 15 F60h FFh SFR FFFh DS40001303H-page 70  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 5-8: DATA MEMORY MAP FOR PIC18F26K20/46K20 DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 96 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 160 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank GPR used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 GPR FFh 4FFh = 0101 00h 500h Bank 5 GPR FFh 5FFh = 0110 00h 600h Bank 6 GPR Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 GPR Access RAM Low 5Fh FFh 7FFh Access RAM High 60h = 1000 00h 800h (SFRs) FFh Bank 8 GPR FFh 8FFh = 1001 00h 900h Bank 9 GPR FFh 9FFh = 1010 00h A00h Bank 10 GPR FFh AFFh = 1011 00h B00h Bank 11 GPR FFh BFFh C00h = 1100 00h Bank 12 GPR CFFh FFh D00h = 1101 00h Bank 13 GPR DFFh FFh 00h E00h = 1110 Bank 14 GPR FFh EFFh = 1111 00h GPR FF50F0hh Bank 15 F60h FFh SFR FFFh  2010-2015 Microchip Technology Inc. DS40001303H-page 71

PIC18F2XK20/4XK20 FIGURE 5-9: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) Data Memory From Opcode(2) 7 0 000h 00h 7 0 0 0 0 0 0 0 1 1 Bank 0 FFh 1 1 1 1 1 1 1 1 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS40001303H-page 72  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 5.3.2 ACCESS BANK 5.3.3 GENERAL PURPOSE REGISTER FILE While the use of the BSR with an embedded 8-bit address allows users to address the entire range of PIC18 devices may have banked memory in the GPR data memory, it also means that the user must always area. This is data RAM, which is available for use by all ensure that the correct bank is selected. Otherwise, instructions. GPRs start at the bottom of Bank 0 data may be read from or written to the wrong location. (address 000h) and grow upwards towards the bottom of This can be disastrous if a GPR is the intended target the SFR area. GPRs are not initialized by a Power-on of an operation, but an SFR is written to instead. Reset and are unchanged on all other Resets. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. 5.3.4 SPECIAL FUNCTION REGISTERS To streamline access for the most commonly used data The Special Function Registers (SFRs) are registers memory locations, the data memory is configured with used by the CPU and peripheral modules for controlling an Access Bank, which allows users to access a the desired operation of the device. These registers are mapped block of memory without specifying a BSR. implemented as static RAM. SFRs start at the top of The Access Bank consists of the first 96 bytes of mem- data memory (FFFh) and extend downward to occupy ory (00h-5Fh) in Bank 0 and the last 160 bytes of mem- the top portion of Bank 15 (F60h to FFFh). A list of ory (60h-FFh) in Block 15. The lower half is known as these registers is given in Table5-1 and Table5-2. the “Access RAM” and is composed of GPRs. This The SFRs can be classified into two sets: those upper half is also where the device’s SFRs are associated with the “core” device functionality (ALU, mapped. These two areas are mapped contiguously in Resets and interrupts) and those related to the the Access Bank and can be addressed in a linear peripheral functions. The Reset and interrupt registers fashion by an 8-bit address (Figures 5-5 through 5-7). are described in their respective chapters, while the The Access Bank is used by core PIC18 instructions ALU’s STATUS register is described later in this that include the Access RAM bit (the ‘a’ parameter in section. Registers related to the operation of a the instruction). When ‘a’ is equal to ‘1’, the instruction peripheral feature are described in the chapter for that uses the BSR and the 8-bit address included in the peripheral. opcode for the data memory address. When ‘a’ is ‘0’, The SFRs are typically distributed among the however, the instruction is forced to use the Access peripherals whose functions they control. Unused SFR Bank address map; the current value of the BSR is locations are unimplemented and read as ‘0’s. ignored entirely. Using this “forced” addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section5.5.3 “Mapping the Access Bank in Indexed Literal Offset Mode”.  2010-2015 Microchip Technology Inc. DS40001303H-page 73

PIC18F2XK20/4XK20 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2XK20/4XK20 DEVICES Address Name Address Name Address Name Address Name FFFh TOSU FD7h TMR0H FAFh SPBRG F87h —(2) FFEh TOSH FD6h TMR0L FAEh RCREG F86h —(2) FFDh TOSL FD5h T0CON FADh TXREG F85h —(2) FFCh STKPTR FD4h —(2) FACh TXSTA F84h PORTE FFBh PCLATU FD3h OSCCON FABh RCSTA F83h PORTD(3) FFAh PCLATH FD2h HLVDCON FAAh EEADRH(4) F82h PORTC FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA FF7h TBLPTRH FCFh TMR1H FA7h EECON2(1) F7Fh ANSELH FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh ANSEL FF5h TABLAT FCDh T1CON FA5h —(2) F7Dh IOCB FF4h PRODH FCCh TMR2 FA4h —(2) F7Ch WPUB FF3h PRODL FCBh PR2 FA3h —(2) F7Bh CM1CON0 FF2h INTCON FCAh T2CON FA2h IPR2 F7Ah CM2CON0 FF1h INTCON2 FC9h SSPBUF FA1h PIR2 F79h CM2CON1 FF0h INTCON3 FC8h SSPADD FA0h PIE2 F78h SLRCON FEFh INDF0(1) FC7h SSPSTAT F9Fh IPR1 F77h SSPMSK FEEh POSTINC0(1) FC6h SSPCON1 F9Eh PIR1 F76h —(2) FEDh POSTDEC0(1) FC5h SSPCON2 F9Dh PIE1 F75h —(2) FECh PREINC0(1) FC4h ADRESH F9Ch —(2) F74h —(2) FEBh PLUSW0(1) FC3h ADRESL F9Bh OSCTUNE F73h —(2) FEAh FSR0H FC2h ADCON0 F9Ah —(2) F72h —(2) FE9h FSR0L FC1h ADCON1 F99h —(2) F71h —(2) FE8h WREG FC0h ADCON2 F98h —(2) F70h —(2) FE7h INDF1(1) FBFh CCPR1H F97h —(2) F6Fh —(2) FE6h POSTINC1(1) FBEh CCPR1L F96h TRISE(3) F6Eh —(2) FE5h POSTDEC1(1) FBDh CCP1CON F95h TRISD(3) F6Dh —(2) FE4h PREINC1(1) FBCh CCPR2H F94h TRISC F6Ch —(2) FE3h PLUSW1(1) FBBh CCPR2L F93h TRISB F6Bh —(2) FE2h FSR1H FBAh CCP2CON F92h TRISA F6Ah —(2) FE1h FSR1L FB9h PSTRCON F91h —(2) F69h —(2) FE0h BSR FB8h BAUDCON F90h —(2) F68h —(2) FDFh INDF2(1) FB7h PWM1CON F8Fh —(2) F67h —(2) FDEh POSTINC2(1) FB6h ECCP1AS F8Eh —(2) F66h —(2) FDDh POSTDEC2(1) FB5h CVRCON F8Dh LATE(3) F65h —(2) FDCh PREINC2(1) FB4h CVRCON2 F8Ch LATD(3) F64h —(2) FDBh PLUSW2(1) FB3h TMR3H F8Bh LATC F63h —(2) FDAh FSR2H FB2h TMR3L F8Ah LATB F62h —(2) FD9h FSR2L FB1h T3CON F89h LATA F61h —(2) FD8h STATUS FB0h SPBRGH F88h —(2) F60h —(2) Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available on PIC18F2XK20 devices. 4: This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices. DS40001303H-page 74  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 56, 62 TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 56, 62 TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 56, 62 STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 56, 63 PCLATU — — — Holding Register for PC<20:16> ---0 0000 56, 62 PCLATH Holding Register for PC<15:8> 0000 0000 56, 62 PCL PC, Low Byte (PC<7:0>) 0000 0000 56, 62 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 56, 87 TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>) 0000 0000 56, 87 TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR<7:0>) 0000 0000 56, 87 TABLAT Program Memory Table Latch 0000 0000 56, 87 PRODH Product Register, High Byte xxxx xxxx 56, 98 PRODL Product Register, Low Byte xxxx xxxx 56, 98 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 56, 102 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 56, 103 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 56, 104 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 56, 80 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 56, 80 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 56, 80 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 56, 80 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register) – N/A 56, 80 FSR0H — — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000 56, 80 FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx 56, 80 WREG Working Register xxxx xxxx 56 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 56, 80 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 56, 80 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 56, 80 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 56, 80 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register) – value of N/A 56, 80 FSR1H — — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000 57, 80 FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx 57, 80 BSR — — — — Bank Select Register ---- 0000 57, 67 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 57, 80 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 57, 80 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 57, 80 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 57, 80 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register) – value of N/A 57, 80 FSR2H — — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000 57, 80 FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx 57, 80 STATUS — — — N OV Z DC C ---x xxxx 57, 78 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise it is disabled and reads as ‘0’. See Section4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section2.6.2 “PLL in HFINTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit=0). Otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’. 7: This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices.  2010-2015 Microchip Technology Inc. DS40001303H-page 75

PIC18F2XK20/4XK20 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TMR0H Timer0 Register, High Byte 0000 0000 57, 147 TMR0L Timer0 Register, Low Byte xxxx xxxx 57, 147 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 57, 145 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0011 qq00 28, 57 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 57, 276 WDTCON — — — — — — — SWDTEN --- ---0 57, 291 RCON IPEN SBOREN(1) — RI TO PD POR BOR 0q-1 11q0 48, 55, 111 TMR1H Timer1 Register, High Byte xxxx xxxx 57, 154 TMR1L Timer1 Register, Low Bytes xxxx xxxx 57, 154 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 57, 148 TMR2 Timer2 Register 0000 0000 57, 156 PR2 Timer2 Period Register 1111 1111 57, 156 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 57, 155 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 57, 188, 189 SSPADD SSP Address Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 57, 189 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 57, 181, 191 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 57, 182, 192 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 57, 193 ADRESH A/D Result Register, High Byte xxxx xxxx 58, 261 ADRESL A/D Result Register, Low Byte xxxx xxxx 58, 261 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 58, 255 ADCON1 — — VCFG1 VCFG0 — — — — --00 ---- 59, 256 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 58, 257 CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxx 58, 135 CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx 58, 135 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 58, 161 CCPR2H Capture/Compare/PWM Register 2, High Byte xxxx xxxx 58, 135 CCPR2L Capture/Compare/PWM Register 2, Low Byte xxxx xxxx 58, 135 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 58, 134 PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 58, 175 BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 0100 0-00 58, 233 PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 58, 174 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 58, 171 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 58, 274 CVRCON2 FVREN FVRST — — — — — — 00-- ---- 58, 275 TMR3H Timer3 Register, High Byte xxxx xxxx 58, 160 TMR3L Timer3 Register, Low Byte xxxx xxxx 58, 160 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 58, 157 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise it is disabled and reads as ‘0’. See Section4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section2.6.2 “PLL in HFINTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit=0). Otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’. 7: This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices. DS40001303H-page 76  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: SPBRGH EUSART Baud Rate Generator Register, High Byte 0000 0000 58, 226 SPBRG EUSART Baud Rate Generator Register, Low Byte 0000 0000 58, 226 RCREG EUSART Receive Register 0000 0000 58, 223 TXREG EUSART Transmit Register 0000 0000 58, 222 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 58, 231 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 58, 232 EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 58, 85, 93 EEADRH(7) — — — — — — EEADR9 EEADR8 ---- --00 58, 85, 93 EEDATA EEPROM Data Register 0000 0000 58, 85, 93 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 58, 85, 93 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 58, 86, 93 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 1111 1111 59, 110 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 0000 0000 59, 106 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 0000 0000 59, 108 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 59, 109 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 59, 105 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 59, 107 OSCTUNE INTSRC PLLEN(3) TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0q00 0000 32, 59 TRISE(2) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 59, 126 TRISD(2) PORTD Data Direction Control Register 1111 1111 59, 122 TRISC PORTC Data Direction Control Register 1111 1111 59, 119 TRISB PORTB Data Direction Control Register 1111 1111 59, 116 TRISA TRISA7(5) TRISA6(5) Data Direction Control Register for PORTA 1111 1111 59, 113 LATE(2) — — — — — PORTE Data Latch Register ---- -xxx 59, 125 (Read and Write to Data Latch) LATD(2) PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 59, 122 LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 59, 119 LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 59, 116 LATA LATA7(5) LATA6(5) PORTA Data Latch Register (Read and Write to Data Latch) xxxx xxxx 59, 113 PORTE — — — — RE3(4) RE2(2) RE1(2) RE0(2) ---- x000 59, 125 PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 59, 122 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 59, 119 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxx0 0000 59, 116 PORTA RA7(5) RA6(5) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 59, 113 ANSELH(6) — — — ANS12 ANS11 ANS10 ANS9 ANS8 ---1 1111 59, 129 ANSEL ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 59, 128 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 59, 116 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 59, 116 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 59, 267 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 59, 268 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — — — 0000 ---- 60, 270 SLRCON — — — SLRE(2) SLRD(2) SLRC SLRB SLRA ---1 1111 60, 130 SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 60, 200 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise it is disabled and reads as ‘0’. See Section4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section2.6.2 “PLL in HFINTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit=0). Otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’. 7: This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices.  2010-2015 Microchip Technology Inc. DS40001303H-page 77

PIC18F2XK20/4XK20 5.3.5 STATUS REGISTER It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS The STATUS register, shown in Register5-2, contains register, because these instructions do not affect the Z, the arithmetic status of the ALU. As with any other SFR, C, DC, OV or N bits in the STATUS register. it can be the operand for any instruction. For other instructions that do not affect Status bits, see If the STATUS register is the destination for an the instruction set summaries in Table24-2 and instruction that affects the Z, DC, C, OV or N bits, the Table24-3. results of the instruction are not written; instead, the STATUS register is updated according to the Note: The C and DC bits operate as the borrow instruction performed. Therefore, the result of an and digit borrow bits, respectively, in instruction with the STATUS register as its destination subtraction. may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). REGISTER 5-2: STATUS: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (two’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit magni- tude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS40001303H-page 78  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 5.4 Data Addressing Modes The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR Note: The execution of some instructions in the (Section5.3.1 “Bank Select Register (BSR)”) are core PIC18 instruction set are changed used with the address to determine the complete 12-bit when the PIC18 extended instruction set is address of the register. When ‘a’ is ‘0’, the address is enabled. See Section5.5 “Data Memory interpreted as being a register in the Access Bank. and the Extended Instruction Set” for Addressing that uses the Access RAM is sometimes more information. also known as Direct Forced Addressing mode. While the program memory can be addressed in only A few instructions, such as MOVFF, include the entire one way – through the program counter – information 12-bit address (either source or destination) in their in the data memory space can be addressed in several opcodes. In these cases, the BSR is ignored entirely. ways. For most instructions, the addressing mode is The destination of the operation’s results is determined fixed. Other instructions may use up to three modes, by the destination bit ‘d’. When ‘d’ is ‘1’, the results are depending on which operands are used and whether or stored back in the source register, overwriting its origi- not the extended instruction set is enabled. nal contents. When ‘d’ is ‘0’, the results are stored in The addressing modes are: the W register. Instructions without the ‘d’ argument have a destination that is implicit in the instruction; their • Inherent destination is either the target register being operated • Literal on or the W register. • Direct 5.4.3 INDIRECT ADDRESSING • Indirect Indirect addressing allows the user to access a location An additional addressing mode, Indexed Literal Offset, in data memory without giving a fixed address in the is available when the extended instruction set is instruction. This is done by using File Select Registers enabled (XINST Configuration bit = 1). Its operation is (FSRs) as pointers to the locations which are to be read discussed in greater detail in Section5.5.1 “Indexed or written. Since the FSRs are themselves located in Addressing with Literal Offset”. RAM as Special File Registers, they can also be 5.4.1 INHERENT AND LITERAL directly manipulated under program control. This ADDRESSING makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. Many PIC18 control instructions do not need any argu- ment at all; they either perform an operation that glob- The registers for indirect addressing are also ally affects the device or they operate implicitly on one implemented with Indirect File Operands (INDFs) that register. This addressing mode is known as Inherent permit automatic manipulation of the pointer value with Addressing. Examples include SLEEP, RESET and DAW. auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using Other instructions work in a similar way but require an loops, such as the example of clearing an entire RAM additional explicit argument in the opcode. This is bank in Example5-5. known as Literal Addressing mode because they require some literal value as an argument. Examples EXAMPLE 5-5: HOW TO CLEAR RAM include ADDLW and MOVLW, which respectively, add or (BANK 1) USING move a literal value to the W register. Other examples INDIRECT ADDRESSING include CALL and GOTO, which include a 20-bit program memory address. LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF 5.4.2 DIRECT ADDRESSING ; register then ; inc pointer Direct addressing specifies all or part of the source BTFSS FSR0H,1 ; All done with and/or destination address of the operation within the ; Bank1? opcode itself. The options are specified by the BRA NEXT ; NO, clear next arguments accompanying the instruction. CONTINUE ; YES, continue In the core PIC18 instruction set, bit-oriented and byte- oriented instructions use some version of direct addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section5.3.3 “General Purpose Register File”) or a location in the Access Bank (Section5.3.2 “Access Bank”) as the data source for the instruction.  2010-2015 Microchip Technology Inc. DS40001303H-page 79

PIC18F2XK20/4XK20 5.4.3.1 FSR Registers and the INDF 5.4.3.2 FSR Registers and POSTINC, Operand POSTDEC, PREINC and PLUSW At the core of indirect addressing are three sets of In addition to the INDF operand, each FSR register pair registers: FSR0, FSR1 and FSR2. Each represents a also has four additional indirect operands. Like INDF, pair of 8-bit registers, FSRnH and FSRnL. Each FSR these are “virtual” registers which cannot be directly pair holds a 12-bit value, therefore the four upper bits read or written. Accessing these registers actually of the FSRnH register are not used. The 12-bit FSR accesses the location to which the associated FSR value can address the entire range of the data memory register pair points, and also performs a specific action in a linear fashion. The FSR register pairs, then, serve on the FSR value. They are: as pointers to data memory locations. • POSTDEC: accesses the location to which the Indirect addressing is accomplished with a set of FSR points, then automatically decrements the Indirect File Operands, INDF0 through INDF2. These FSR by 1 afterwards can be thought of as “virtual” registers: they are • POSTINC: accesses the location to which the mapped in the SFR space but are not physically FSR points, then automatically increments the implemented. Reading or writing to a particular INDF FSR by 1 afterwards register actually accesses its corresponding FSR • PREINC: automatically increments the FSR by 1, register pair. A read from INDF1, for example, reads then uses the location to which the FSR points in the data at the address indicated by FSR1H:FSR1L. the operation Instructions that use the INDF registers as operands • PLUSW: adds the signed value of the W register actually use the contents of their corresponding FSR as (range of -127 to 128) to that of the FSR and uses a pointer to the instruction’s target. The INDF operand the location to which the result points in the is just a convenient way of using the pointer. operation. Because indirect addressing uses a full 12-bit address, In this context, accessing an INDF register uses the data RAM banking is not necessary. Thus, the current value in the associated FSR register without changing contents of the BSR and the Access RAM bit have no it. Similarly, accessing a PLUSW register gives the effect on determining the target address. FSR value an offset by that in the W register; however, neither W nor the FSR is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR register. FIGURE 5-10: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 indirect addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 0 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains E00h ECCh. This means the contents of Bank 14 location ECCh will be added to that F00h of the W register and stored back in Bank 15 ECCh. FFFh Data Memory DS40001303H-page 80  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 Operations on the FSRs with POSTDEC, POSTINC 5.5.1 INDEXED ADDRESSING WITH and PREINC affect the entire register pair; that is, roll- LITERAL OFFSET overs of the FSRnL register from FFh to 00h carry over Enabling the PIC18 extended instruction set changes to the FSRnH register. On the other hand, results of the behavior of indirect addressing using the FSR2 these operations do not change the value of any flags register pair within Access RAM. Under the proper in the STATUS register (e.g., Z, N, OV, etc.). conditions, instructions that use the Access Bank – that The PLUSW register can be used to implement a form is, most bit-oriented and byte-oriented instructions – of indexed addressing in the data memory space. By can invoke a form of indexed addressing using an manipulating the value in the W register, users can offset specified in the instruction. This special reach addresses that are fixed offsets from pointer addressing mode is known as Indexed Addressing with addresses. In some applications, this can be used to Literal Offset, or Indexed Literal Offset mode. implement some powerful program control structure, When using the extended instruction set, this such as software stacks, inside of data memory. addressing mode requires the following: 5.4.3.3 Operations by FSRs on FSRs • The use of the Access Bank is forced (‘a’ = 0) and Indirect addressing operations that target other FSRs • The file address argument is less than or equal to or virtual registers represent special cases. For 5Fh. example, using an FSR to point to one of the virtual Under these conditions, the file address of the registers will not result in successful operations. As a instruction is not interpreted as the lower byte of an specific case, assume that FSR0H:FSR0L contains address (used with the BSR in direct addressing), or as FE7h, the address of INDF1. Attempts to read the an 8-bit address in the Access Bank. Instead, the value value of the INDF1 using INDF0 as an operand will is interpreted as an offset value to an Address Pointer, return 00h. Attempts to write to INDF1 using INDF0 as specified by FSR2. The offset and the contents of the operand will result in a NOP. FSR2 are added to obtain the target address of the On the other hand, using the virtual registers to write to operation. an FSR pair may not occur as planned. In these cases, 5.5.2 INSTRUCTIONS AFFECTED BY the value will be written to the FSR pair but without any INDEXED LITERAL OFFSET MODE incrementing or decrementing. Thus, writing to either the INDF2 or POSTDEC2 register will write the same Any of the core PIC18 instructions that can use direct value to the FSR2H:FSR2L. addressing are potentially affected by the Indexed Since the FSRs are physical registers mapped in the Literal Offset Addressing mode. This includes all SFR space, they can be manipulated through all direct byte-oriented and bit-oriented instructions, or almost operations. Users should proceed cautiously when one-half of the standard PIC18 instruction set. working on these registers, particularly if their code Instructions that only use Inherent or Literal Addressing uses indirect addressing. modes are unaffected. Similarly, operations by indirect addressing are generally Additionally, byte-oriented and bit-oriented instructions permitted on all other SFRs. Users should exercise the are not affected if they do not use the Access Bank appropriate caution that they do not inadvertently change (Access RAM bit is ‘1’), or include a file address of 60h settings that might affect the operation of the device. or above. Instructions meeting these criteria will continue to execute as before. A comparison of the 5.5 Data Memory and the Extended different possible addressing modes when the extended instruction set is enabled is shown in Instruction Set Figure5-11. Enabling the PIC18 extended instruction set (XINST Those who desire to use byte-oriented or bit-oriented Configuration bit = 1) significantly changes certain instructions in the Indexed Literal Offset mode should aspects of data memory and its addressing. Specifi- note the changes to assembler syntax for this mode. cally, the use of the Access Bank for many of the core This is described in more detail in Section24.2.1 PIC18 instructions is different; this is due to the intro- “Extended Instruction Syntax”. duction of a new addressing mode for the data memory space. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged.  2010-2015 Microchip Technology Inc. DS40001303H-page 81

PIC18F2XK20/4XK20 FIGURE 5-11: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When ‘a’ = 0 and f  60h: The instruction executes in 060h Direct Forced mode. ‘f’ is inter- Bank 0 preted as a location in the 100h Access RAM between 060h 00h and 0FFh. This is the same as Bank 1 through 60h locations F60h to FFFh Bank 14 (Bank15) of data memory. Valid range for ‘f’ Locations below 60h are not FFh available in this addressing F00h Access RAM mode. Bank 15 F60h SFRs FFFh Data Memory When ‘a’ = 0 and f5Fh: 000h The instruction executes in Indexed Literal Offset mode. ‘f’ 060h Bank 0 is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F60h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When ‘a’ = 1 (all values of f): 000h 00000000 The instruction executes in 060h Direct mode (also known as Bank 0 Direct Long mode). ‘f’ is inter- 100h preted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F60h SFRs FFFh Data Memory DS40001303H-page 82  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 5.5.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to INDEXED LITERAL OFFSET MODE operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will The use of Indexed Literal Offset Addressing mode continue to use direct addressing as before. effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing 5.6 PIC18 Instruction Execution and just the contents of the bottom section of Bank 0, this the Extended Instruction Set mode maps the contents from a user defined “window” that can be located anywhere in the data memory Enabling the extended instruction set adds eight space. The value of FSR2 establishes the lower bound- additional commands to the existing PIC18 instruction ary of the addresses mapped into the window, while the set. These instructions are executed as described in upper boundary is defined by FSR2 plus 95 (5Fh). Section24.2 “Extended Instruction Set”. Addresses in the Access RAM above 5Fh are mapped as previously described (see Section5.3.2 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure5-12. FIGURE 5-12: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a FSR2H:FSR2L = 120h Bank 0 Locations in the region from the FSR2 pointer 100h (120h) to the pointer plus Bank 1 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Access RAM (000h-05Fh). 200h Bank 1 “Window” 5Fh Special File Registers at 60h F60h through FFFh are mapped to 60h through Bank 2 FFh, as usual. through SFRs Bank 0 addresses below Bank 14 5Fh can still be addressed FFh by using the BSR. Access Bank F00h Bank 15 F60h SFRs FFFh Data Memory  2010-2015 Microchip Technology Inc. DS40001303H-page 83

PIC18F2XK20/4XK20 6.0 FLASH PROGRAM MEMORY A value written to program memory does not need to be a valid instruction. Executing a program memory The Flash program memory is readable, writable and location that forms an invalid instruction results in a erasable during normal operation over the entire VDD NOP. range. A read from program memory is executed one byte at 6.1 Table Reads and Table Writes a time. A write to program memory is executed on In order to read and write program memory, there are blocks of 64, 32 or 16 bytes at a time, depending on the two operations that allow the processor to move bytes specific device (See Table6-1). Program memory is between the program memory space and the data RAM: erased in blocks of 64 bytes at a time. The difference between the write and erase block sizes requires from • Table Read (TBLRD) 1 to 4 block writes to restore the contents of a single • Table Write (TBLWT) block erase. A bulk erase operation cannot be issued The program memory space is 16 bits wide, while the from user code. data RAM space is eight bits wide. Table reads and table writes move data between these two memory TABLE 6-1: WRITE/ERASE BLOCK SIZES spaces through an 8-bit register (TABLAT). Write Block Erase Block Device The table read operation retrieves one byte of data Size (bytes) Size (bytes) directly from program memory and places it into the PIC18F43K20, 16 64 TABLAT register. Figure6-1 shows the operation of a PIC18F23K20 table read. PIC18F24K20, 32 64 The table write operation stores one byte of data from the PIC18F25K20, TABLAT register into a write block holding register. The PIC18F44K20, procedure to write the contents of the holding registers PIC18F45K20 into program memory is detailed in Section6.5 “Writing to Flash Program Memory”. Figure6-2 shows the PIC18F26K20, 64 64 operation of a table write with program memory and data PIC18F46K20 RAM. Writing or erasing program memory will cease Table operations work with byte entities. Tables instruction fetches until the operation is complete. The containing data, rather than program instructions, are program memory cannot be accessed during the write not required to be word aligned. Therefore, a table can or erase, therefore, code cannot execute. An internal start and end at any byte address. If a table write is being programming timer terminates program memory writes used to write executable code into program memory, and erases. program instructions will need to be word aligned. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. DS40001303H-page 84  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR<MSBs>) Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL actually point to an address within the write block holding registers. The MSBs of the Table Pointer deter- mine where the write block will eventually be written. The process for writing the holding registers to the program memory array is discussed in Section6.5 “Writing to Flash Program Memory”. 6.2 Control Registers The FREE bit allows the program memory erase operation. When FREE is set, an erase operation is Several control registers are used in conjunction with initiated on the next WR command. When FREE is the TBLRD and TBLWT instructions. These include the: clear, only writes are enabled. • EECON1 register The WREN bit, when set, will allow a write operation. • EECON2 register The WREN bit is clear on power-up. • TABLAT register The WRERR bit is set by hardware when the WR bit is • TBLPTR registers set and cleared when the internal programming timer expires and the write operation is complete. 6.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is The EECON1 register (Register6-1) is the control read as ‘1’. This can indicate that a write register for memory accesses. The EECON2 register is operation was prematurely terminated by not a physical register; it is used exclusively in the a Reset, or a write operation was memory write and erase sequences. Reading attempted improperly. EECON2 will read all ‘0’s. The EEPGD control bit determines if the access will be The WR control bit initiates write operations. The WR a program or data EEPROM memory access. When bit cannot be cleared, only set, by firmware. Then WR EEPGD is clear, any subsequent operations will bit is cleared by hardware at the completion of the write operate on the data EEPROM memory. When EEPGD operation. is set, any subsequent operations will operate on the Note: The EEIF interrupt flag bit of the PIR2 program memory. register is set when the write is complete. The CFGS control bit determines if the access will be The EEIF flag stays set until cleared by to the Configuration/Calibration registers or to program firmware. memory/data EEPROM memory. When CFGS is set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section23.0 “Special Features of the CPU”). When CFGS is clear, memory selection access is determined by EEPGD.  2010-2015 Microchip Technology Inc. DS40001303H-page 85

PIC18F2XK20/4XK20 REGISTER 6-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row (Block) Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) by software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS40001303H-page 86  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 6.2.2 TABLAT – TABLE LATCH REGISTER When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory The Table Latch (TABLAT) is an 8-bit register mapped directly into the TABLAT register. into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program When a TBLWT is executed the byte in the TABLAT memory and data RAM. register is written, not to Flash memory but, to a holding register in preparation for a program memory write. The 6.2.3 TBLPTR – TABLE POINTER holding registers constitute a write block which varies REGISTER depending on the device (See Table6-1).The 3, 4, or 5 LSbs of the TBLPTRL register determine which specific The Table Pointer (TBLPTR) register addresses a byte address within the holding register block is written to. within the program memory. The TBLPTR is comprised The MSBs of the Table Pointer have no effect during of three SFR registers: Table Pointer Upper Byte, Table TBLWT operations. Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- When a program memory write is executed the entire ters join to form a 22-bit wide pointer. The low-order holding register block is written to the Flash memory at 21bits allow the device to address up to 2 Mbytes of the address determined by the MSbs of the TBLPTR. program memory space. The 22nd bit allows access to The 3, 4, or 5 LSBs are ignored during Flash memory the device ID, the user ID and the Configuration bits. writes. For more detail, see Section6.5 “Writing to Flash Program Memory”. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can When an erase of program memory is executed, the update the TBLPTR in one of four ways based on the 16MSbs of the Table Pointer register (TBLPTR<21:6>) table operation. These operations are shown in point to the 64-byte block that will be erased. The Least Table6-2. These operations on the TBLPTR affect only Significant bits (TBLPTR<5:0>) are ignored. the low-order 21bits. Figure6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. 6.2.4 TABLE POINTER BOUNDARIES TBLPTR is used in reads, writes and erases of the Flash program memory. TABLE 6-2: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 TABLE ERASE/WRITE TABLE WRITE TBLPTR<21:n+1>(1) TBLPTR<n:0>(1) TABLE READ – TBLPTR<21:0> Note1: n = 3, 4, 5, or 6 for block sizes of 8, 16, 32 or 64 bytes, respectively.  2010-2015 Microchip Technology Inc. DS40001303H-page 87

PIC18F2XK20/4XK20 6.3 Reading the Flash Program The internal program memory is typically organized by Memory words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure6-4 The TBLRD instruction retrieves data from program shows the interface between the internal program memory and places it into data RAM. Table reads from memory and the TABLAT. program memory are performed one byte at a time. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT (IR) FETCH TBLRD Read Register EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVFW TABLAT, W ; get data MOVF WORD_ODD DS40001303H-page 88  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 6.4 Erasing Flash Program Memory 6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through The sequence of events for erasing a block of internal ICSP™ control, can larger blocks of program memory program memory is: be bulk erased. Word erase in the Flash array is not 1. Load Table Pointer register with address of supported. block being erased. When initiating an erase sequence from the 2. Set the EECON1 register for the erase operation: Microcontroller itself, a block of 64 bytes of program • set EEPGD bit to point to program memory; memory is erased. The Most Significant 16 bits of the • clear the CFGS bit to access program memory; TBLPTR<21:6> point to the block being erased. The • set WREN bit to enable writes; TBLPTR<5:0> bits are ignored. • set FREE bit to enable the erase. The EECON1 register commands the erase operation. 3. Disable interrupts. The EEPGD bit must be set to point to the Flash pro- 4. Write 55h to EECON2. gram memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase 5. Write 0AAh to EECON2. operation. 6. Set the WR bit. This will begin the block erase cycle. The write initiate sequence for EECON2, shown as steps 4 through 6 in Section6.4.1 “Flash Program 7. The CPU will stall for duration of the erase Memory Erase Sequence”, is used to guard against (about 2ms using internal timer). accidental writes. This is sometimes referred to as a 8. Re-enable interrupts. long write. A long write is necessary for erasing the internal Flash. Instruction execution is halted during the long write cycle. The long write is terminated by the internal programming timer. EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable block Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts  2010-2015 Microchip Technology Inc. DS40001303H-page 89

PIC18F2XK20/4XK20 6.5 Writing to Flash Program Memory The long write is necessary for programming the internal Flash. Instruction execution is halted during a The programming block size is 16, 32 or 64 bytes, long write cycle. The long write will be terminated by depending on the device (See Table6-1). Word or byte the internal programming timer. programming is not supported. The EEPROM on-chip timer controls the write time. Table writes are used internally to load the holding The write/erase voltages are generated by an on-chip registers needed to program the Flash memory. There charge pump, rated to operate over the voltage range are only as many holding registers as there are bytes of the device. in a write block (See Table6-1). Note: The default value of the holding registers on Since the Table Latch (TABLAT) is only a single byte, device Resets and after write operations is the TBLWT instruction may need to be executed 16, 32 FFh. A write of FFh to a holding register or 64 times, depending on the device, for each pro- does not modify that byte. This means that gramming operation. All of the table write operations individual bytes of program memory may will essentially be short writes because only the holding be modified, provided that the change does registers are written. After all the holding registers have not attempt to change any bit from a ‘0’ to a been written, the programming operation of that block ‘1’. When modifying individual bytes, it is of memory is started by configuring the EECON1 regis- not necessary to load all holding registers ter for a program memory write and performing the long before executing a long write operation. write sequence. FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxx00 TBLPTR = xxxx01 TBLPTR = xxxx02 TBLPTR = xxxxYY(1) Holding Register Holding Register Holding Register Holding Register Program Memory Note1: YY = x7, xF, or 1F for 8, 16 or 32 byte write blocks, respectively. 6.5.1 FLASH PROGRAM MEMORY WRITE 8. Disable interrupts. SEQUENCE 9. Write 55h to EECON2. The sequence of events for programming an internal 10. Write 0AAh to EECON2. program memory location should be: 11. Set the WR bit. This will begin the write cycle. 1. Read 64 bytes into RAM. 12. The CPU will stall for duration of the write (about 2ms using internal timer). 2. Update data values in RAM as necessary. 13. Re-enable interrupts. 3. Load Table Pointer register with address being erased. 14. Repeat steps 6 to 13 for each block until all 64 bytes are written. 4. Execute the block erase procedure. 15. Verify the memory (table read). 5. Load Table Pointer register with address of first byte being written. This procedure will require about 6ms to update each 6. Write the 16, 32 or 64 byte block into the holding write block of memory. An example of the required code registers with auto-increment. is given in Example6-3. 7. Set the EECON1 register for the write operation: Note: Before setting the WR bit, the Table • set EEPGD bit to point to program memory; Pointer address needs to be within the • clear the CFGS bit to access program memory; intended address range of the bytes in the • set WREN to enable byte writes. holding registers. DS40001303H-page 90  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64’ ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L WRITE_BUFFER_BACK MOVLW BlockSize ; number of bytes in holding register MOVWF COUNTER MOVLW D’64’/BlockSize ; number of write blocks in 64 bytes MOVWF COUNTER2 WRITE_BYTE_TO_HREGS MOVF POSTINC0, W ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register.  2010-2015 Microchip Technology Inc. DS40001303H-page 91

PIC18F2XK20/4XK20 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) DECFSZ COUNTER ; loop until holding registers are full BRA WRITE_WORD_TO_HREGS PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) DCFSZ COUNTER2 ; repeat for remaining write blocks BRA WRITE_BYTE_TO_HREGS ; BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory 6.5.2 WRITE VERIFY 6.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the To protect against spurious writes to Flash program memory should be verified against the original value. memory, the write initiate sequence must also be This should be used in applications where excessive followed. See Section23.0 “Special Features of the writes can stress bits near the specification limit. CPU” for more detail. 6.5.3 UNEXPECTED TERMINATION OF 6.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section23.3 “Program Verification and Code location just programmed should be verified and Protection” for details on code protection of Flash reprogrammed if needed. If the write operation is program memory. interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the WRERR bit will be set which the user can check to decide whether a rewrite of the location(s) is needed. TABLE 6-3: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 56 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 56 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 56 TABLAT Program Memory Table Latch 56 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 EECON2 EEPROM Control Register 2 (not a physical register) 58 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 58 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. DS40001303H-page 92  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 7.0 DATA EEPROM MEMORY The EECON1 register (Register7-1) is the control reg- ister for data and program memory access. Control bit The data EEPROM is a nonvolatile memory array, sep- EEPGD determines if the access will be to program or arate from the data RAM and program memory, which data EEPROM memory. When the EEPGD bit is clear, is used for long-term storage of program data. It is not operations will access the data EEPROM memory. directly mapped in either the register file or program When the EEPGD bit is set, program memory is memory space but is indirectly addressed through the accessed. Special Function Registers (SFRs). The EEPROM is Control bit, CFGS, determines if the access will be to readable and writable during normal operation over the the Configuration registers or to program memory/data entire VDD range. EEPROM memory. When the CFGS bit is set, Four SFRs are used to read and write to the data subsequent operations access Configuration registers. EEPROM as well as the program memory. They are: When the CFGS bit is clear, the EEPGD bit selects • EECON1 either program Flash or data EEPROM memory. • EECON2 The WREN bit, when set, will allow a write operation. • EEDATA On power-up, the WREN bit is clear. • EEADR The WRERR bit is set by hardware when the WR bit is • EEADRH set and cleared when the internal programming timer expires and the write operation is complete. The data EEPROM allows byte read and write. When interfacing to the data memory block, EEDATA holds Note: During normal operation, the WRERR the 8-bit data for read/write and the EEADR:EEADRH may read as ‘1’. This can indicate that a register pair hold the address of the EEPROM location write operation was prematurely termi- being accessed. nated by a Reset, or a write operation was attempted improperly. The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the The WR control bit initiates write operations. The bit location and writes the new data (erase-before-write). can be set but not cleared by software. It is cleared only The write time is controlled by an on-chip timer; it will by hardware at the completion of the write operation. vary with voltage and temperature as well as from chip- to-chip. Please refer to parameter D122 (Table26-10 in Note: The EEIF interrupt flag bit of the PIR2 Section26.0 “Electrical Specifications”) for exact register is set when the write is complete. limits. It must be cleared by software. 7.1 EEADR and EEADRH Registers Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware The EEADR register is used to address the data and cleared by hardware at the completion of the EEPROM for read and write operations. The 8-bit operation. range of the register can address a memory range of The RD bit cannot be set when accessing program 256 bytes (00h to FFh). The EEADRH register expands memory (EEPGD = 1). Program memory is read using the range to 1024 bytes by adding an additional two table read instructions. See Section6.1 “Table Reads address bits. and Table Writes” regarding table reads. 7.2 EECON1 and EECON2 Registers The EECON2 register is not a physical register. It is used exclusively in the memory write and erase Access to the data EEPROM is controlled by two sequences. Reading EECON2 will read all ‘0’s. registers: EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM.  2010-2015 Microchip Technology Inc. DS40001303H-page 93

PIC18F2XK20/4XK20 REGISTER 7-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row (Block) Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) by software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS40001303H-page 94  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 7.3 Reading the Data EEPROM Additionally, the WREN bit in EECON1 must be set to Memory enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code To read a data memory location, the user must write the execution (i.e., runaway programs). The WREN bit address to the EEADR register, clear the EEPGD con- should be kept clear at all times, except when updating trol bit of the EECON1 register and then set control bit, the EEPROM. The WREN bit is not cleared by RD. The data is available on the very next instruction hardware. cycle; therefore, the EEDATA register can be read by After a write sequence has been initiated, EECON1, the next instruction. EEDATA will hold this value until EEADR and EEDATA cannot be modified. The WR bit another read operation, or until it is written to by the will be inhibited from being set unless the WREN bit is user (during a write operation). set. Both WR and WREN cannot be set with the same The basic process is shown in Example7-1. instruction. At the completion of the write cycle, the WR bit is 7.4 Writing to the Data EEPROM cleared by hardware and the EEPROM Interrupt Flag Memory bit, EEIF, is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by To write an EEPROM data location, the address must software. first be written to the EEADR register and the data writ- ten to the EEDATA register. The sequence in 7.5 Write Verify Example7-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly Depending on the application, good programming followed (write 55h to EECON2, write 0AAh to practice may dictate that the value written to the EECON2, then set WR bit) for each byte. It is strongly memory should be verified against the original value. recommended that interrupts be disabled during this This should be used in applications where excessive codesegment. writes can stress bits near the specification limit. EXAMPLE 7-1: DATA EEPROM READ MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA EXAMPLE 7-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDR_LOW ; MOVWF EEADR ; Data Memory Address to write MOVLW DATA_EE_ADDR_HI ; MOVWF EEADRH ; MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable Interrupts ; User code execution BCF EECON1, WREN ; Disable writes on write complete (EEIF set)  2010-2015 Microchip Technology Inc. DS40001303H-page 95

PIC18F2XK20/4XK20 7.6 Operation During Code-Protect The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, Data EEPROM memory has its own code-protect bits in power glitch or software malfunction. Configuration Words. External read and write operations are disabled if code protection is enabled. 7.8 Using the Data EEPROM The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the The data EEPROM is a high-endurance, byte addressable array that has been optimized for the code-protect Configuration bit. Refer to Section23.0 storage of frequently changing information (e.g., “Special Features of the CPU” for additional program variables or other data that are updated often). information. When variables in one section change frequently, while variables in another section do not change, it is possible 7.7 Protection Against Spurious Write to exceed the total number of write cycles to the There are conditions when the user may not want to EEPROM (specification D124) without exceeding the write to the data EEPROM memory. To protect against total number of write cycles to a single byte (specification spurious EEPROM writes, various mechanisms have D120). If this is the case, then an array refresh must be been implemented. On power-up, the WREN bit is performed. For this reason, variables that change cleared. In addition, writes to the EEPROM are blocked infrequently (such as constants, IDs, calibration, etc.) during the Power-up Timer period (TPWRT, should be stored in Flash program memory. parameter33). A simple data EEPROM refresh routine is shown in Example7-3. Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification. EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE CLRF EEADR ; Start at address 0 BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes Loop ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA LOOP ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts DS40001303H-page 96  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 58 EEADRH(1) — — — — — — EEADR9 EEADR8 58 EEDATA EEPROM Data Register 58 EECON2 EEPROM Control Register 2 (not a physical register) 58 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 58 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: PIC18F26K20/PIC18F46K20 only.  2010-2015 Microchip Technology Inc. DS40001303H-page 97

PIC18F2XK20/4XK20 8.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 8-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 8.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY operation does not affect any flags in the STATUS ROUTINE register. MOVF ARG1, W Making multiplication a hardware operation allows it to MULWF ARG2 ; ARG1 * ARG2 -> be completed in a single instruction cycle. This has the ; PRODH:PRODL advantages of higher computational throughput and BTFSC ARG2, SB ; Test Sign Bit reduced code size for multiplication algorithms and SUBWF PRODH, F ; PRODH = PRODH allows the PIC18 devices to be used in many applica- ; - ARG1 tions previously reserved for digital signal processors. MOVF ARG2, W BTFSC ARG1, SB ; Test Sign Bit A comparison of various hardware and software SUBWF PRODH, F ; PRODH = PRODH multiply operations, along with the savings in memory ; - ARG2 and execution time, is shown in Table8-1. 8.2 Operation Example8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example8-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the argu- ments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 s 27.6 s 69 s 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 s Without hardware multiply 33 91 9.1 s 36.4 s 91 s 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 s 6 s Without hardware multiply 21 242 24.2 s 96.8 s 242 s 16 x 16 unsigned Hardware multiply 28 28 2.8 s 11.2 s 28 s Without hardware multiply 52 254 25.4 s 102.6 s 254 s 16 x 16 signed Hardware multiply 35 40 4.0 s 16.0 s 40 s DS40001303H-page 98  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 Example8-3 shows the sequence to do a 16 x 16 EQUATION 8-2: 16 x 16 SIGNED unsigned multiplication. Equation8-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES<3:0>). RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L = (ARG1H  ARG2H  216) + EQUATION 8-1: 16 x 16 UNSIGNED (ARG1H  ARG2L  28) + MULTIPLICATION (ARG1L  ARG2H  28) + ALGORITHM (ARG1L  ARG2L) + (-1  ARG2H<7>  ARG1H:ARG1L  216) + RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L (-1  ARG1H<7>  ARG2H:ARG2L  216) = (ARG1H  ARG2H  216) + (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + EXAMPLE 8-4: 16 x 16 SIGNED (ARG1L  ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 8-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example8-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation8-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers ; (RES<3:0>). To account for the sign bits of the argu- SIGN_ARG1 ments, the MSb for each argument pair is tested and BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? the appropriate subtractions are done. BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE :  2010-2015 Microchip Technology Inc. DS40001303H-page 99

PIC18F2XK20/4XK20 9.0 INTERRUPTS 9.2 Interrupt Priority The PIC18F2XK20/4XK20 devices have multiple The interrupt priority feature is enabled by setting the interrupt sources and an interrupt priority feature that IPEN bit of the RCON register. When interrupt priority allows most interrupt sources to be assigned a high is enabled the GIE and PEIE global interrupt enable priority level or a low priority level. The high priority bits of Compatibility mode are replaced by the GIEH interrupt vector is at 0008h and the low priority interrupt high priority, and GIEL low priority, global interrupt vector is at 0018h. A high priority interrupt event will enables. When set, the GIEH bit of the INTCON regis- interrupt a low priority interrupt that may be in progress. ter enables all interrupts that have their associated IPRx register or INTCONx register priority bit set (high There are ten registers which are used to control priority). When clear, the GIEH bit disables all interrupt interrupt operation. These registers are: sources including those selected as low priority. When • RCON clear, the GIEL bit of the INTCON register disables only • INTCON the interrupts that have their associated priority bit • INTCON2 cleared (low priority). When set, the GIEL bit enables the low priority sources when the GIEH bit is also set. • INTCON3 • PIR1, PIR2 When the interrupt flag, enable bit and appropriate global interrupt enable bit are all set, the interrupt will • PIE1, PIE2 vector immediately to address 0008h for high priority, • IPR1, IPR2 or 0018h for low priority, depending on level of the It is recommended that the Microchip header files sup- interrupting source’s priority bit. Individual interrupts plied with MPLAB® IDE be used for the symbolic bit can be disabled through their corresponding interrupt names in these registers. This allows the assembler/ enable bits. compiler to automatically take care of the placement of these bits within the specified register. 9.3 Interrupt Response In general, interrupt sources have three bits to control When an interrupt is responded to, the global interrupt their operation. They are: enable bit is cleared to disable further interrupts. The • Flag bit to indicate that an interrupt event GIE bit is the global interrupt enable when the IPEN bit occurred is cleared. When the IPEN bit is set, enabling interrupt • Enable bit that allows program execution to priority levels, the GIEH bit is the high priority global branch to the interrupt vector address when the interrupt enable and the GIEL bit is the low priority flag bit is set global interrupt enable. High priority interrupt sources • Priority bit to select high priority or low priority can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority 9.1 Mid-Range Compatibility interrupts are in progress. The return address is pushed onto the stack and the When the IPEN bit is cleared (default state), the interrupt PC is loaded with the interrupt vector address (0008h priority feature is disabled and interrupts are compatible or 0018h). Once in the Interrupt Service Routine, the with PIC® microcontroller mid-range devices. In source(s) of the interrupt can be determined by polling Compatibility mode, the interrupt priority bits of the IPRx the interrupt flag bits in the INTCONx and PIRx registers have no effect. The PEIE bit of the INTCON registers. The interrupt flag bits must be cleared by register is the global interrupt enable for the peripherals. software before re-enabling interrupts to avoid The PEIE bit disables only the peripheral interrupt repeating the same interrupt. sources and enables the peripheral interrupt sources when the GIE bit is also set. The GIE bit of the INTCON The “return from interrupt” instruction, RETFIE, exits register is the global interrupt enable which enables all the interrupt routine and sets the GIE bit (GIEH or GIEL non-peripheral interrupt sources and disables all if priority levels are used), which re-enables interrupts. interrupt sources, including the peripherals. All interrupts For external interrupt events, such as the INT pins or branch to address 0008h in Compatibility mode. the PORTB interrupt-on-change, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one-cycle or two-cycle instruc- tions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bits or the global interrupt enable bit. DS40001303H-page 100  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. FIGURE 9-1: PIC18 INTERRUPT LOGIC Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF (1) RBIE RBIP INT0IF INT0IE Interrupt to CPU INT1IF Vector to Location INT1IE SSPIF INT1IP 0008h SSPIE INT2IF SSPIP INT2IE INT2IP GIEH/GIE ADIF ADIE ADIP IPEN RCIF IPEN RCIE RCIP GIEL/PEIE IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation SSPIF SSPIE SSPIP Interrupt to CPU TMR0IF Vector to Location TMR0IE 0018h ADIF TMR0IP ADIE ADIP RBIF (1) RBIE RCIF RBIP GIEH/GIE RCIE GIEL/PEIE RCIP INT1IF INT1IE INT1IP Additional Peripheral Interrupts INT2IF INT2IE INT2IP Note 1: The RBIF interrupt also requires the individual pin IOCB enables.  2010-2015 Microchip Technology Inc. DS40001303H-page 101

PIC18F2XK20/4XK20 9.4 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers, which contain various enable, priority and enable bit. User software should ensure flag bits. the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts including peripherals When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts including low priority. bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority interrupts 0 = Disables all low priority interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit(2) 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared by software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared by software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared by software) 0 = None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. 2: RB port change interrupts also require the individual pin IOCB enables. DS40001303H-page 102  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 9-2: INTCON2: INTERRUPT CONTROL 2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled provided that the pin is an input and the corresponding WPUB bit is set. bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2010-2015 Microchip Technology Inc. DS40001303H-page 103

PIC18F2XK20/4XK20 REGISTER 9-3: INTCON3: INTERRUPT CONTROL 3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared by software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared by software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS40001303H-page 104  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 9.5 PIR Registers Note1: Interrupt flag bits are set when an inter- rupt condition occurs, regardless of the The PIR registers contain the individual flag bits for the state of its corresponding enable bit or the peripheral interrupts. Due to the number of peripheral Global Interrupt Enable bit, GIE of the interrupt sources, there are two Peripheral Interrupt INTCON register. Request Flag registers (PIR1 and PIR2). 2: User software should ensure the appro- priate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared by software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared by software) 0 = The A/D conversion is not complete or has not been started bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared by software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared by software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared by software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared by software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared by software) 0 = TMR1 register did not overflow Note1: The PSPIF bit is unimplemented on 28-pin devices and will read as ‘0’.  2010-2015 Microchip Technology Inc. DS40001303H-page 105

PIC18F2XK20/4XK20 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software) 0 = Device clock operating bit 6 C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator C1 output has changed (must be cleared by software) 0 = Comparator C1 output has not changed bit 5 C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator C2 output has changed (must be cleared by software) 0 = Comparator C2 output has not changed bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared by software) 0 = The write operation is not complete or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared by software) 0 = No bus collision occurred bit 2 HLVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (direction determined by the VDIRMAG bit of the HLVDCON register) 0 = A low-voltage condition has not occurred bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared by software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared by software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared by software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. DS40001303H-page 106  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 9.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-6: PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: The PSPIE bit is unimplemented on 28-pin devices and will read as ‘0’.  2010-2015 Microchip Technology Inc. DS40001303H-page 107

PIC18F2XK20/4XK20 REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 C1IE: Comparator C1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 C2IE: Comparator C2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS40001303H-page 108  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 9.7 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note1: The PSPIF bit is unimplemented on 28-pin devices and will read as ‘0’.  2010-2015 Microchip Technology Inc. DS40001303H-page 109

PIC18F2XK20/4XK20 REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 C1IP: Comparator C1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 C2IP: Comparator C2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority DS40001303H-page 110  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 9.8 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section4.1 “RCON Register”. REGISTER 9-10: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN(1) — RI TO PD POR(1) BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (Mid-Range Compatibility mode) bit 6 SBOREN: Software BOR Enable bit(1) For details of bit operation, see Register4-1. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register4-1. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register4-1. bit 2 PD: Power-down Detection Flag bit For details of bit operation, see Register4-1 bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register4-1. Note1: Actual Reset values are determined by device configuration and the nature of the device Reset. See Register4-1 for additional information.  2010-2015 Microchip Technology Inc. DS40001303H-page 111

PIC18F2XK20/4XK20 9.9 INTn Pin Interrupts 9.10 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1 and In 8-bit mode (which is the default), an overflow in the RB2/INT2 pins are edge-triggered. If the corresponding TMR0 register (FFh00h) will set flag bit, TMR0IF. In INTEDGx bit in the INTCON2 register is set (= 1), the 16-bit mode, an overflow in the TMR0H:TMR0L regis- interrupt is triggered by a rising edge; if the bit is clear, ter pair (FFFFh 0000h) will set TMR0IF. The interrupt the trigger is on the falling edge. When a valid edge can be enabled/disabled by setting/clearing enable bit, appears on the RBx/INTx pin, the corresponding flag TMR0IE of the INTCON register. Interrupt priority for bit, INTxF, is set. This interrupt can be disabled by Timer0 is determined by the value contained in the clearing the corresponding enable bit, INTxE. Flag bit, interrupt priority bit, TMR0IP of the INTCON2 register. INTxF, must be cleared by software in the Interrupt See Section12.0 “Timer0 Module” for further details Service Routine before re-enabling the interrupt. on the Timer0 module. All external interrupts (INT0, INT1 and INT2) can wake- 9.11 PORTB Interrupt-on-Change up the processor from Idle or Sleep modes if bit INTxE was set prior to going into those modes. If the Global An input change on PORTB<7:4> sets flag bit, RBIF of Interrupt Enable bit, GIE, is set, the processor will the INTCON register. The interrupt can be enabled/ branch to the interrupt vector following wake-up. disabled by setting/clearing enable bit, RBIE of the Interrupt priority for INT1 and INT2 is determined by the INTCON register. Pins must also be individually value contained in the interrupt priority bits, INT1IP and enabled with the IOCB register. Interrupt priority for INT2IP of the INTCON3 register. There is no priority bit PORTB interrupt-on-change is determined by the value associated with INT0. It is always a high priority inter- contained in the interrupt priority bit, RBIP of the rupt source. INTCON2 register. 9.12 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section5.1.3 “Fast Register Stack”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS40001303H-page 112  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 10.0 I/O PORTS Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the PORT latch. Depending on the device selected and features The Data Latch (LATA) register is also memory mapped. enabled, there are up to five ports available. Some pins Read-modify-write operations on the LATA register read of the I/O ports are multiplexed with an alternate and write the latched output value for PORTA. function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not The RA4 pin is multiplexed with the Timer0 module be used as a general purpose I/O pin. clock input and one of the comparator outputs to become the RA4/T0CKI/C1OUT pin. Pins RA6 and Each port has three registers for its operation. These RA7 are multiplexed with the main oscillator pins; they registers are: are enabled as oscillator or I/O pins by the selection of • TRIS register (data direction register) the main oscillator in the Configuration register (see • PORT register (reads the levels on the pins of the Section23.1 “Configuration Bits” for details). When device) they are not used as port pins, RA6 and RA7 and their • LAT register (output latch) associated TRIS and LAT bits are read as ‘0’. The Data Latch (LAT register) is useful for read-modify- The other PORTA pins are multiplexed with analog write operations on the value that the I/O pins are inputs, the analog VREF+ and VREF- inputs, and the driving. comparator voltage reference output. The operation of pins RA<3:0> and RA5 as analog is selected by setting A simplified model of a generic I/O port, without the the ANS<4:0> bits in the ANSEL register which is the interfaces to other peripherals, is shown in Figure10-1. default setting after a Power-on Reset. FIGURE 10-1: GENERIC I/O PORT Pins RA0 through RA5 may also be used as comparator inputs or outputs by setting the appropriate bits in the OPERATION CM1CON0 and CM2CON0 registers. Note: On a Power-on Reset, RA5 and RA<3:0> RD LAT are configured as analog inputs and read Data as ‘0’. RA4 is configured as a digital input. Bus D Q The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input. WR LAT I/O pin(1) orPort All other PORTA pins have TTL input levels and full CK CMOS output drivers. Data Latch The TRISA register controls the drivers of the PORTA D Q pins, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register WR TRIS CK are maintained set when using them as analog inputs. TRIS Latch Input Buffer EXAMPLE 10-1: INITIALIZING PORTA RD TRIS CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches Q D CLRF LATA ; Alternate method ; to clear output ENEN ; data latches MOVLW E0h ; Configure I/O RD Port MOVWF ANSEL ; for digital inputs MOVLW 0CFh ; Value used to Note1: I/O pins have diode protection to VDD and VSS. ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs 10.1 PORTA, TRISA and LATA Registers ; RA<5:4> as outputs PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).  2010-2015 Microchip Technology Inc. DS40001303H-page 113

PIC18F2XK20/4XK20 TABLE 10-1: PORTA I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RA0/AN0/C12IN0- RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA ADC input channel 0. Default input configuration on POR; does not affect digital output. C12IN0- 1 I ANA Comparators C1 and C2 inverting input, channel 0. Analog select is shared with ADC. RA1/AN1/C12IN1- RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA ADC input channel 1. Default input configuration on POR; does not affect digital output. C12IN1- 1 I ANA Comparators C1 and C2 inverting input, channel 1. Analog select is shared with ADC. RA2/AN2/C2IN+ RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when VREF-/CVREF CVREF output enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. AN2 1 I ANA ADC input channel 2. Default input configuration on POR; not affected by analog output. C2IN+ 1 I ANA Comparator C2 non-inverting input. Analog selection is shared with ADC. VREF- 1 I ANA ADC and comparator voltage reference low input. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RA3/AN3/C1IN+/ RA3 0 O DIG LATA<3> data output; not affected by analog input. VREF+ 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D input channel 3. Default input configuration on POR. C1IN+ 1 I ANA Comparator C1 non-inverting input. Analog selection is shared with ADC. VREF+ 1 I ANA ADC and comparator voltage reference high input. RA4/T0CKI/C1OUT RA4 0 O DIG LATA<4> data output. 1 I ST PORTA<4> data input; default configuration on POR. T0CKI 1 I ST Timer0 clock input. C1OUT 0 O DIG Comparator 1 output; takes priority over port data. RA5/AN4/SS/ RA5 0 O DIG LATA<5> data output; not affected by analog input. HLVDIN/C2OUT 1 I TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 I ANA A/D input channel 4. Default configuration on POR. SS 1 I TTL Slave select input for SSP (MSSP module). HLVDIN 1 I ANA Low-Voltage Detect external trip point input. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. OSC2/CLKOUT/ RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. RA6 1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes). CLKOUT x O DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator modes. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). DS40001303H-page 114  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 10-1: PORTA I/O SUMMARY (CONTINUED) TRIS I/O Pin Function I/O Description Setting Type OSC1/CLKIN/RA7 RA7 0 O DIG LATA<7> data output. Disabled in external oscillator modes. 1 I TTL PORTA<7> data input. Disabled in external oscillator modes. OSC1 x I ANA Main oscillator input connection. CLKIN x I ANA Main clock input connection. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 59 LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 59 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 59 ANSEL ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 59 SLRCON — — — SLRE(2) SLRD(2) SLRC SLRB SLRA 60 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 59 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 59 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: Not implemented on PIC18F2XK20 devices.  2010-2015 Microchip Technology Inc. DS40001303H-page 115

PIC18F2XK20/4XK20 10.2 PORTB, TRISB and LATB 10.3.2 INTERRUPT-ON-CHANGE Registers Four of the PORTB pins (RB<7:4>) are individually configurable as interrupt-on-change pins. Control bits PORTB is an 8-bit wide, bidirectional port. The corre- in the IOCB register enable (when set) or disable (when sponding data direction register is TRISB. Setting a clear) the interrupt function for each pin. TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a When set, the RBIE bit of the INTCON register enables TRISB bit (= 0) will make the corresponding PORTB interrupts on all pins which also have their correspond- pin an output (i.e., enable the output driver and put the ing IOCB bit set. When clear, the RBIE bit disables all contents of the output latch on the selected pin). interrupt-on-changes. The Data Latch register (LATB) is also memory Only pins configured as inputs can cause this interrupt mapped. Read-modify-write operations on the LATB to occur (i.e., any RB<7:4> pin configured as an output register read and write the latched output value for is excluded from the interrupt-on-change comparison). PORTB. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of EXAMPLE 10-2: INITIALIZING PORTB PORTB. The ‘mismatch’ outputs of the last read are CLRF PORTB ; Initialize PORTB by OR’d together to set the PORTB Change Interrupt flag ; clearing output bit (RBIF) in the INTCON register. ; data latches This interrupt can wake the device from the Sleep CLRF LATB ; Alternate method mode, or any of the Idle modes. The user, in the ; to clear output Interrupt Service Routine, can clear the interrupt in the ; data latches following manner: CLRF ANSELH ; Set RB<4:0> as ; digital I/O pins a) Any read or write of PORTB to clear the mis- ;(required if config bit match condition (except when PORTB is the ; PBADEN is set) source or destination of a MOVFF instruction). MOVLW 0CFh ; Value used to b) Clear the flag bit, RBIF. ; initialize data ; direction A mismatch condition will continue to set the RBIF flag bit. MOVWF TRISB ; Set RB<3:0> as inputs Reading or writing PORTB will end the mismatch ; RB<5:4> as outputs condition and allow the RBIF bit to be cleared. The latch ; RB<7:6> as inputs holding the last read value is not affected by a MCLR nor Brown-out Reset. After either one of these Resets, the 10.3 Additional PORTB Pin Functions RBIF flag will continue to be set if a mismatch is present. PORTB pins RB<7:4> have an interrupt-on-change Note: If a change on the I/O pin should occur option. All PORTB pins have a weak pull-up option. An when the read operation is being executed alternate CCP2 peripheral option is available on RB3. (start of the Q2 cycle), then the RBIF interrupt flag may not getset. Furthermore, 10.3.1 WEAK PULL-UPS since a read or write on a port affects all bits of that port, care must be taken when Each of the PORTB pins has an individually controlled using multiple pins in Interrupt-on-change weak internal pull-up. When set, each bit of the WPUB mode. Changes on one pin may not be register enables the corresponding pin pull-up. When seen while servicing changes on another cleared, the RBPU bit of the INTCON2 register enables pin. pull-ups on all pins which also have their corresponding WPUB bit set. When set, the RBPU bit disables all The interrupt-on-change feature is recommended for weak pull-ups. The weak pull-up is automatically turned wake-up on key depression operation and operations off when the port pin is configured as an output. The where PORTB is only used for the interrupt-on-change pull-ups are disabled on a Power-on Reset. feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. Note: On a Power-on Reset, RB<4:0> are configured as analog inputs by default and 10.3.3 ALTERNATE CCP2 OPTION read as ‘0’; RB<7:5> are configured as digital inputs. RB3 can be configured as the alternate peripheral pin for the CCP2 module by clearing the CCP2MX Config- When the PBADEN Configuration bit is uration bit of CONFIG3H. The default state of the set to ‘1’, RB<4:0> will alternatively be CCP2MX Configuration bit is ‘1’ which selects RC1 as configured as digital inputs on POR. the CCP2 peripheral pin. DS40001303H-page 116  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 10-3: PORTB I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RB0/INT0/FLT0/ RB0 0 O DIG LATB<0> data output; not affected by analog input. AN12 1 I TTL PORTB<0> data input; Programmable weak pull-up. Disabled when analog input enabled.(1) INT0 1 I ST External interrupt 0 input. FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled by software. AN12 1 I ANA A/D input channel 12.(1) RB1/INT1/AN10/ RB1 0 O DIG LATB<1> data output; not affected by analog input. C12IN3-/P1C 1 I TTL PORTB<1> data input; Programmable weak pull-up. Disabled when analog input enabled.(1) INT1 1 I ST External Interrupt 1 input. AN10 1 I ANA ADC input channel 10.(1) C12IN3- 1 I ANA Comparators C1 and C2 inverting input, channel 3. Analog select is shared with ADC. P1C 0 O DIG ECCP PWM output (28-pin devices only). RB2/INT2/AN8/ RB2 0 O DIG LATB<2> data output; not affected by analog input. P1B 1 I TTL PORTB<2> data input; Programmable weak pull-up. Disabled when analog input enabled.(1) INT2 1 I ST External interrupt 2 input. AN8 1 I ANA ADC input channel 8.(1) P1B 0 O DIG ECCP PWM output (28-pin devices only). RB3/AN9/C12IN2-/ RB3 0 O DIG LATB<3> data output; not affected by analog input. CCP2 1 I TTL PORTB<3> data input; Programmable weak pull-up. Disabled when analog input enabled.(1) AN9 1 I ANA ADC input channel 9.(1) C12IN2- 1 I ANA Comparators C1 and C2 inverting input, channel 2. Analog select is shared with ADC. CCP2(2) 0 O DIG CCP2 compare and PWM output. 1 I ST CCP2 capture input RB4/KBI0/AN11/ RB4 0 O DIG LATB<4> data output; not affected by analog input. P1D 1 I TTL PORTB<4> data input; Programmable weak pull-up. Disabled when analog input enabled.(1) KBI0 1 I TTL Interrupt-on-pin change. AN11 1 I ANA ADC input channel 11.(1) P1D 0 O DIG ECCP PWM output (28-pin devices only). RB5/KBI1/PGM RB5 0 O DIG LATB<5> data output. 1 I TTL PORTB<5> data input; Programmable weak pull-up. KBI1 1 I TTL Interrupt-on-pin change. PGM x I ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP Configuration bit; all other pin functions disabled. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled.  2010-2015 Microchip Technology Inc. DS40001303H-page 117

PIC18F2XK20/4XK20 TABLE 10-3: PORTB I/O SUMMARY (CONTINUED) TRIS I/O Pin Function I/O Description Setting Type RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; Programmable weak pull-up. KBI2 1 I TTL Interrupt-on-pin change. PGC x I ST Serial execution (ICSP) clock input for ICSP and ICD operation.(3) RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; Programmable weak pull-up. KBI3 1 I TTL Interrupt-on-pin change. PGD x O DIG Serial execution data output for ICSP and ICD operation.(3) x I ST Serial execution data input for ICSP and ICD operation.(3) Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled. TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 59 LATB PORTB Data Latch Register (Read and Write to Data Latch) 59 TRISB PORTB Data Direction Control Register 59 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 59 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 59 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 60 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 56 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 56 ANSELH — — — ANS12 ANS11 ANS10 ANS9 ANS8 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. Note 1: Not implemented on PIC18F2XK20 devices. DS40001303H-page 118  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 10.4 PORTC, TRISC and LATC EXAMPLE 10-3: INITIALIZING PORTC Registers CLRF PORTC ; Initialize PORTC by ; clearing output PORTC is an 8-bit wide, bidirectional port. The corre- ; data latches sponding data direction register is TRISC. Setting a CLRF LATC ; Alternate method TRISC bit (= 1) will make the corresponding PORTC ; to clear output pin an input (i.e., disable the output driver). Clearing a ; data latches TRISC bit (= 0) will make the corresponding PORTC MOVLW 0CFh ; Value used to pin an output (i.e., enable the output driver and put the ; initialize data ; direction contents of the output latch on the selected pin). MOVWF TRISC ; Set RC<3:0> as inputs The Data Latch register (LATC) is also memory ; RC<5:4> as outputs mapped. Read-modify-write operations on the LATC ; RC<7:6> as inputs register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table10-5). The pins have Schmitt Trigger input buf- fers. RC1 is the default configuration for the CCP2 peripheral pin. The CCP2 function can be relocated to the RB3 pin by clearing the CCP2MX bit of Configura- tion Word CONFIG3H. The default state of the CCP2MX Configuration bit is ‘1’. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. The EUSART and MSSP peripherals override the TRIS bit to make a pin an output or an input, depending on the peripheral configuration. Refer to the corresponding peripheral section for additional information. Note: On a Power-on Reset, these pins are con- figured as digital inputs. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins.  2010-2015 Microchip Technology Inc. DS40001303H-page 119

PIC18F2XK20/4XK20 TABLE 10-5: PORTC I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RC0/T1OSO/ RC0 0 O DIG LATC<0> data output. T13CKI 1 I ST PORTC<0> data input. T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T13CKI 1 I ST Timer1/Timer3 counter input. RC1/T1OSI/CCP2 RC1 0 O DIG LATC<1> data output. 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. CCP2(1) 0 O DIG CCP2 compare and PWM output; takes priority over port data. 1 I ST CCP2 capture input. RC2/CCP1/P1A RC2 0 O DIG LATC<2> data output. 1 I ST PORTC<2> data input. CCP1 0 O DIG ECCP1 compare or PWM output; takes priority over port data. 1 I ST ECCP1 capture input. P1A 0 O DIG ECCP1 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC3/SCK/SCL RC3 0 O DIG LATC<3> data output. 1 I ST PORTC<3> data input. SCK 0 O DIG SPI clock output (MSSP module); takes priority over port data. 1 I ST SPI clock input (MSSP module). SCL 0 O DIG I2C™ clock output (MSSP module); takes priority over port data. 1 I I2C/SMB I2C clock input (MSSP module); input type depends on module setting. RC4/SDI/SDA RC4 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input. SDI 1 I ST SPI data input (MSSP module). SDA 1 O DIG I2C data output (MSSP module); takes priority over port data. 1 I I2C/SMB I2C data input (MSSP module); input type depends on module setting. RC5/SDO RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO 0 O DIG SPI data output (MSSP module); takes priority over port data. RC6/TX/CK RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX 1 O DIG Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as output. CK 1 O DIG Synchronous serial clock output (EUSART module); takes priority over port data. 1 I ST Synchronous serial clock input (EUSART module). RC7/RX/DT RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX 1 I ST Asynchronous serial receive data input (EUSART module). DT 1 O DIG Synchronous serial data output (EUSART module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART module). User must configure as an input. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3. DS40001303H-page 120  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 59 LATC PORTC Data Latch Register (Read and Write to Data Latch) 59 TRISC PORTC Data Direction Control Register 59 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 57 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 58 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 57 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 58 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 58 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 58 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 60 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC. Note 1: Not implemented on PIC18F2XK20 devices.  2010-2015 Microchip Technology Inc. DS40001303H-page 121

PIC18F2XK20/4XK20 10.5 PORTD, TRISD and LATD PORTD can also be configured as an 8-bit wide micro- Registers processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input Note: PORTD is only available on 40/44-pin buffers are TTL. See Section10.9 “Parallel Slave devices. Port” for additional information on the Parallel Slave Port (PSP). PORTD is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISD. Setting a Note: When the enhanced PWM mode is used TRISD bit (= 1) will make the corresponding PORTD with either dual or quad outputs, the PSP pin an input (i.e., disable the output driver). Clearing a functions of PORTD are automatically TRISD bit (= 0) will make the corresponding PORTD disabled. pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). EXAMPLE 10-4: INITIALIZING PORTD The Data Latch register (LATD) is also memory CLRF PORTD ; Initialize PORTD by mapped. Read-modify-write operations on the LATD ; clearing output register read and write the latched output value for ; data latches PORTD. CLRF LATD ; Alternate method ; to clear output All pins on PORTD are implemented with Schmitt Trig- ; data latches ger input buffers. Each pin is individually configurable MOVLW 0CFh ; Value used to as an input or output. ; initialize data ; direction Three of the PORTD pins are multiplexed with outputs MOVWF TRISD ; Set RD<3:0> as inputs P1B, P1C and P1D of the enhanced CCP module. The ; RD<5:4> as outputs operation of these additional PWM output pins is ; RD<7:6> as inputs covered in greater detail in Section16.0 “Enhanced Capture/Compare/PWM (ECCP) Module”. Note: On a Power-on Reset, these pins are configured as digital inputs. DS40001303H-page 122  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 10-7: PORTD I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RD0/PSP0 RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. PSP0 x O DIG PSP read data output (LATD<0>); takes priority over port data. x I TTL PSP write data input. RD1/PSP1 RD1 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. PSP1 x O DIG PSP read data output (LATD<1>); takes priority over port data. x I TTL PSP write data input. RD2/PSP2 RD2 0 O DIG LATD<2> data output. 1 I ST PORTD<2> data input. PSP2 x O DIG PSP read data output (LATD<2>); takes priority over port data. x I TTL PSP write data input. RD3/PSP3 RD3 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. PSP3 x O DIG PSP read data output (LATD<3>); takes priority over port data. x I TTL PSP write data input. RD4/PSP4 RD4 0 O DIG LATD<4> data output. 1 I ST PORTD<4> data input. PSP4 x O DIG PSP read data output (LATD<4>); takes priority over port data. x I TTL PSP write data input. RD5/PSP5/P1B RD5 0 O DIG LATD<5> data output. 1 I ST PORTD<5> data input. PSP5 x O DIG PSP read data output (LATD<5>); takes priority over port data. x I TTL PSP write data input. P1B 0 O DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD6/PSP6/P1C RD6 0 O DIG LATD<6> data output. 1 I ST PORTD<6> data input. PSP6 x O DIG PSP read data output (LATD<6>); takes priority over port data. x I TTL PSP write data input. P1C 0 O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD7/PSP7/P1D RD7 0 O DIG LATD<7> data output. 1 I ST PORTD<7> data input. PSP7 x O DIG PSP read data output (LATD<7>); takes priority over port data. x I TTL PSP write data input. P1D 0 O DIG ECCP1 Enhanced PWM output, channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).  2010-2015 Microchip Technology Inc. DS40001303H-page 123

PIC18F2XK20/4XK20 TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 59 LATD(1) PORTD Data Latch Register (Read and Write to Data Latch) 59 TRISD(1) PORTD Data Direction Control Register 59 TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 59 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 58 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 60 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: Not implemented on PIC18F2XK20 devices. DS40001303H-page 124  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 10.6 PORTE, TRISE and LATE The fourth pin of PORTE (MCLR/VPP/RE3) is an input Registers only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin Depending on the particular PIC18F2XK20/4XK20 (MCLRE=0), it functions as a digital input only pin; as device selected, PORTE is implemented in two such, it does not have TRIS or LAT bits associated with its different ways. operation. Otherwise, it functions as the device’s Master Clear input. In either configuration, RE3 also functions as 10.6.1 PORTE IN PIC18F4XK20 DEVICES the programming voltage input during programming. For PIC18F4XK20 devices, PORTE is a 4-bit wide port. Note: On a Power-on Reset, RE3 is enabled as Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/ a digital input only if Master Clear AN7) are individually configurable as inputs or outputs. functionality is disabled. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s. EXAMPLE 10-5: INITIALIZING PORTE The corresponding data direction register is TRISE. CLRF PORTE ; Initialize PORTE by Setting a TRISE bit (= 1) will make the corresponding ; clearing output PORTE pin an input (i.e., disable the output driver). ; data latches Clearing a TRISE bit (= 0) will make the corresponding CLRF LATE ; Alternate method PORTE pin an output (i.e., enable the output driver and ; to clear output put the contents of the output latch on the selected pin). ; data latches MOVLW 1Fh ; Configure analog pins TRISE controls the direction of the RE pins, even when ANDWF ANSEL,w; for digital only they are being used as analog inputs. The user must MOVLW 05h ; Value used to make sure to keep the pins configured as inputs when ; initialize data using them as analog inputs. ; direction MOVWF TRISE ; Set RE<0> as input Note: On a Power-on Reset, RE<2:0> are ; RE<1> as output configured as analog inputs. ; RE<2> as input The upper four bits of the TRISE register also control the operation of the Parallel Slave Port. Their operation 10.6.2 PORTE IN PIC18F2XK20 DEVICES is explained in Register10-1. For PIC18F2XK20 devices, PORTE is only available The Data Latch register (LATE) is also memory when Master Clear functionality is disabled mapped. Read-modify-write operations on the LATE (MCLR=0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates register, read and write the latched output value for as previously described. PORTE.  2010-2015 Microchip Technology Inc. DS40001303H-page 125

PIC18F2XK20/4XK20 REGISTER 10-1: TRISE: PORTE/PSP CONTROL REGISTER (PIC18F4XK20 DEVICES ONLY) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared by software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General purpose I/O mode bit 3 Unimplemented: Read as ‘0’ bit 2 TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output DS40001303H-page 126  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 10-9: PORTE I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RE0/RD/AN5 RE0 0 O DIG LATE<0> data output; not affected by analog input. 1 I ST PORTE<0> data input; disabled when analog input enabled. RD 1 I TTL PSP read enable input (PSP enabled). AN5 1 I ANA A/D input channel 5; default input configuration on POR. RE1/WR/AN6 RE1 0 O DIG LATE<1> data output; not affected by analog input. 1 I ST PORTE<1> data input; disabled when analog input enabled. WR 1 I TTL PSP write enable input (PSP enabled). AN6 1 I ANA A/D input channel 6; default input configuration on POR. RE2/CS/AN7 RE2 0 O DIG LATE<2> data output; not affected by analog input. 1 I ST PORTE<2> data input; disabled when analog input enabled. CS 1 I TTL PSP write enable input (PSP enabled). AN7 1 I ANA A/D input channel 7; default input configuration on POR. MCLR/VPP/ MCLR — I ST External Master Clear input; enabled when MCLRE Configuration bit is RE3(1,2) set. VPP — I ANA High-voltage detection; used for ICSP™ mode entry detection. Always available, regardless of pin mode. RE3 —(2) I ST PORTE<3> data input; enabled when MCLRE Configuration bit is clear. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: RE3 is available on both PIC18F2XK20 and PIC18F4XK20 devices. All other PORTE pins are only implemented on PIC18F4XK20 devices. 2: RE3 does not have a corresponding TRIS bit to control data direction. TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTE — — — — RE3(1,2) RE2 RE1 RE0 59 LATE(2) — — — — — LATE Data Output Register 59 TRISE(3) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 59 SLRCON — — — SLRE(3) SLRD(3) SLRC SLRB SLRA 60 ANSEL ANS7(3) ANS6(3) ANS5(3) ANS4 ANS3 ANS2 ANS1 ANS0 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both PIC18F2XK20 and PIC18F4XK20 devices. All other bits are implemented only when PORTE is implemented (i.e., PIC18F4XK20 devices). 3: Unimplemented on PIC18F2XK20 devices.  2010-2015 Microchip Technology Inc. DS40001303H-page 127

PIC18F2XK20/4XK20 10.7 Port Analog Control buffer and cause all reads of that pin to return ‘0’ while allowing analog functions of that pin to operate Some port pins are multiplexed with analog functions correctly. such as the Analog-to-Digital Converter and compara- The state of the ANSx bits has no affect on digital tors. When these I/O pins are to be used as analog output functions. A pin with the associated TRISx bit inputs it is necessary to disable the digital input buffer clear and ANSx bit set will still operate as a digital to avoid excessive current caused by improper biasing output but the input mode will be analog. This can of the digital input. Individual control of the digital input cause unexpected behavior when performing read- buffers on pins which share analog functions is pro- modify-write operations on the affected port. vided by the ANSEL and ANSELH registers. Setting an ANSx bit high will disable the associated digital input REGISTER 10-2: ANSEL: ANALOG SELECT REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANS7(1) ANS6(1) ANS5(1) ANS4 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ANS7: RE2 Analog Select Control bit(1) 1 = Digital input buffer of RE2 is disabled 0 = Digital input buffer of RE2 is enabled bit 6 ANS6: RE1 Analog Select Control bit(1) 1 = Digital input buffer of RE1 is disabled 0 = Digital input buffer of RE1 is enabled bit 5 ANS5: RE0 Analog Select Control bit(1) 1 = Digital input buffer of RE0 is disabled 0 = Digital input buffer of RE0 is enabled bit 4 ANS4: RA5 Analog Select Control bit 1 = Digital input buffer of RA5 is disabled 0 = Digital input buffer of RA5 is enabled bit 3 ANS3: RA3 Analog Select Control bit 1 = Digital input buffer of RA3 is disabled 0 = Digital input buffer of RA3 is enabled bit 2 ANS2: RA2 Analog Select Control bit 1 = Digital input buffer of RA2 is disabled 0 = Digital input buffer of RA2 is enabled bit 1 ANS1: RA1 Analog Select Control bit 1 = Digital input buffer of RA1 is disabled 0 = Digital input buffer of RA1 is enabled bit 0 ANS0: RA0 Analog Select Control bit 1 = Digital input buffer of RA0 is disabled 0 = Digital input buffer of RA0 is enabled Note 1: These bits are not implemented on PIC18F2XK20 devices. DS40001303H-page 128  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 10-3: ANSELH: ANALOG SELECT REGISTER 2 U-0 U-0 U-0 R/W-1(1) R/W-1(1) R/W-1(1) R/W-1(1) R/W-1(1) — — — ANS12 ANS11 ANS10 ANS9 ANS8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 ANS12: RB0 Analog Select Control bit 1 = Digital input buffer of RB0 is disabled 0 = Digital input buffer of RB0 is enabled bit 3 ANS11: RB4 Analog Select Control bit 1 = Digital input buffer of RB4 is disabled 0 = Digital input buffer of RB4 is enabled bit 2 ANS10: RB1 Analog Select Control bit 1 = Digital input buffer of RB1 is disabled 0 = Digital input buffer of RB1 is enabled bit 1 ANS9: RB3 Analog Select Control bit 1 = Digital input buffer of RB3 is disabled 0 = Digital input buffer of RB3 is enabled bit 0 ANS8: RB2 Analog Select Control bit 1 = Digital input buffer of RB2 is disabled 0 = Digital input buffer of RB2 is enabled Note 1: Default state is determined by the PBADEN bit of CONFIG3H. The default state is ‘0’ When PBADEN=‘0’.  2010-2015 Microchip Technology Inc. DS40001303H-page 129

PIC18F2XK20/4XK20 10.8 Port Slew Rate Control The output slew rate of each port is programmable to select either the standard transition rate or a reduced transition rate of 0.1 times the standard to minimize EMI. The reduced transition time is the default slew rate for all ports. REGISTER 10-4: SLRCON: SLEW RATE CONTROL REGISTER U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SLRE(1) SLRD(1) SLRC SLRB SLRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 SLRE: PORTE Slew Rate Control bit(1) 1 = All outputs on PORTE slew at a limited rate 0 = All outputs on PORTE slew at the standard rate bit 3 SLRD: PORTD Slew Rate Control bit(1) 1 = All outputs on PORTD slew at a limited rate 0 = All outputs on PORTD slew at the standard rate bit 2 SLRC: PORTC Slew Rate Control bit 1 = All outputs on PORTC slew at a limited rate 0 = All outputs on PORTC slew at the standard rate bit 1 SLRB: PORTB Slew Rate Control bit 1 = All outputs on PORTB slew at a limited rate 0 = All outputs on PORTB slew at the standard rate bit 0 SLRA: PORTA Slew Rate Control bit 1 = All outputs on PORTA slew at a limited rate(2) 0 = All outputs on PORTA slew at the standard rate Note 1: These bits are not implemented on PIC18F2XK20 devices. 2: The slew rate of RA6 defaults to standard rate when the pin is used as CLKOUT. DS40001303H-page 130  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 10.9 Parallel Slave Port The timing for the control signals in Write and Read modes is shown in Figure10-3 and Figure10-4, Note: The Parallel Slave Port is only available respectively. on PIC18F4XK20 devices. FIGURE 10-2: PORTD AND PORTE In addition to its function as a general I/O port, PORTD BLOCK DIAGRAM can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is (PARALLEL SLAVE PORT) controlled by the four upper bits of the TRISE register (Register10-1). Setting control bit, PSPMODE One bit of PORTD (TRISE<4>), enables PSP operation as long as the Data Bus enhanced CCP module is not operating in dual output D Q or quad output PWM mode. In Slave mode, the port is RDx pin asynchronously readable and writable by the external WR LATD CK or world. WR PORTD Data Latch TTL The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor Q D can read or write the PORTD latch as an 8-bit latch. Setting the control bit, PSPMODE, enables the PORTE RD PORTD ENEN I/O pins to become control inputs for the microprocessor port. When set, port pin RE0 is the RD input, RE1 is the WR input and RE2 is the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the RD LATD TRISE register (TRISE<2:0>) must be configured as inputs (set) and the ANSEL<7:5> bits must be cleared. Set Interrupt Flag PSPIF (PIR1<7>) A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set PORTE Pins when the write ends. Read A read from the PSP occurs when both the CS and RD TTL RD lines are first detected low. The data in PORTD is read Chip Select out and the OBF bit is clear. If the user writes new data TTL CS to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. Write TTL WR When either the CS or RD lines are detected high, the PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set Note: I/O pins have diode protection to VDD and VSS. before servicing the PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken.  2010-2015 Microchip Technology Inc. DS40001303H-page 131

PIC18F2XK20/4XK20 FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF DS40001303H-page 132  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 59 LATD(1) PORTD Data Latch Register (Read and Write to Data Latch) 59 TRISD(1) PORTD Data Direction Control Register 59 PORTE — — — — RE3 RE2(1) RE1(1) RE0(1) 59 LATE(1) — — — — — LATE Data Output bits 59 TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 59 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 60 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 ANSEL ANS7(1) ANS6(1) ANS5(1) ANS4 ANS3 ANS2 ANS1 ANS0 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: Unimplemented on PIC18F2XK20 devices.  2010-2015 Microchip Technology Inc. DS40001303H-page 133

PIC18F2XK20/4XK20 11.0 CAPTURE/COMPARE/PWM The Capture and Compare operations described in this (CCP) MODULES chapter apply to both standard and enhanced CCP modules. PIC18F2XK20/4XK20 devices have two CCP Note: Throughout this section and Section16.0 Capture/Compare/PWM) modules. Each module “Enhanced Capture/Compare/PWM contains a 16-bit register which can operate as a 16-bit (ECCP) Module”, references to the register Capture register, a 16-bit Compare register or a PWM and bit names for CCP modules are referred Master/Slave Duty Cycle register. to generically by the use of ‘x’ or ‘y’ in place of CCP1 is implemented as an enhanced CCP module with the specific module number. Thus, standard Capture and Compare modes and enhanced “CCPxCON” might refer to the control register PWM modes. The ECCP implementation is discussed in for CCP1, CCP2 or ECCP1. “CCPxCON” is Section16.0 “Enhanced Capture/Compare/PWM used throughout these sections to refer to the (ECCP) Module”. CCP2 is implemented as a standard module control register, regardless of whether CCP module without the enhanced features. the CCP module is a standard or enhanced implementation. REGISTER 11-1: CCP2CON: STANDARD CAPTURE/COMPARE/PWM CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DC2B<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP2 Module Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DC2B<9:2>) of the duty cycle are found in CCPR2L. bit 3-0 CCP2M<3:0>: CCP2 Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCP2 module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCP2IF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode: initialize CCP2 pin low; on compare match, force CCP2 pin high (CCP2IF bit is set) 1001 = Compare mode: initialize CCP2 pin high; on compare match, force CCP2 pin low (CCP2IF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCP2IF bit is set, CCP2 pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCP2 match (CCP2IF bit is set) 11xx = PWM mode DS40001303H-page 134  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 11.1 CCP Module Configuration The assignment of a particular timer to a module is determined by the Timer-to-CCP enable bits in the Each Capture/Compare/PWM module is associated T3CON register (Register15-1). Both modules can be with a control register (generically, CCPxCON) and a active at the same time and can share the same timer data register (CCPRx). The data register, in turn, is resource if they are configured to operate in the same comprised of two 8-bit registers: CCPRxL (low byte) mode (Capture/Compare or PWM). The interactions and CCPRxH (high byte). All registers are both between the two modules are summarized in Figure11-1 readable and writable. and Figure11-2. In Asynchronous Counter mode, the capture operation will not work reliably. 11.1.1 CCP MODULES AND TIMER RESOURCES 11.1.2 CCP2 PIN ASSIGNMENT The CCP modules utilize Timers 1, 2 or 3, depending The pin assignment for CCP2 (Capture input, Compare on the mode selected. Timer1 and Timer3 are available and PWM output) can change, based on device config- to modules in Capture or Compare modes, while uration. The CCP2MX Configuration bit determines the Timer2 is available for modules in PWM mode. pin with which CCP2 is multiplexed. By default, it is assigned to RC1 (CCP2MX = 1). If the Configuration bit TABLE 11-1: CCP MODE – TIMER is cleared, CCP2 is multiplexed with RB3. RESOURCE Changing the pin assignment of CCP2 does not CCP/ECCP Mode Timer Resource automatically change any requirements for configuring the port pin. Users must always verify that the Capture Timer1 or Timer3 appropriate TRIS register is configured correctly for Compare Timer1 or Timer3 CCP2 operation, regardless of where it is located. PWM Timer2 TABLE 11-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES CCP1 Mode CCP2 Mode Interaction Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different for each CCP. Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Automatic A/D conversions on trigger event can also be done. Operation of CCP1 could be affected if it is using the same timer as a time base. Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Operation of CCP2 could be affected if it is using the same timer as a time base. Compare Compare Either module can be configured for the Special Event Trigger to reset the time base. Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if both modules are using the same time base. Capture PWM None Compare PWM None PWM(1) Capture None PWM(1) Compare None PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). Note 1: Includes standard and enhanced PWM operation.  2010-2015 Microchip Technology Inc. DS40001303H-page 135

PIC18F2XK20/4XK20 11.2 Capture Mode EXAMPLE 11-1: CHANGING BETWEEN CAPTURE PRESCALERS In Capture mode, the CCPRxH:CCPRxL register pair (CCP2 SHOWN) captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CLRF CCP2CON ; Turn CCP module off CCPx pin. An event is defined as one of the following: MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode • every falling edge ; value and CCP ON • every rising edge MOVWF CCP2CON ; Load CCP2CON with • every 4th rising edge ; this value • every 16th rising edge The event is selected by the mode select bits, CCPxM<3:0> of the CCPxCON register. When a cap- ture is made, the interrupt request flag bit, CCPxIF, is set; it must be cleared by software. If another capture occurs before the value in register CCPRx is read, the old captured value is overwritten by the new captured value. 11.2.1 CCP PIN CONFIGURATION In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. 11.2.2 TIMER1/TIMER3 MODE SELECTION The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each CCP module is selected in the T3CON register (see Section11.1.1 “CCP Modules and Timer Resources”). 11.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false inter- rupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. 11.2.4 CCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCPxM<3:0>). Whenever the CCP module is turned off or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example11-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. DS40001303H-page 136  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 11-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP1IF T3CCP2 TMR3 Enable CCP1 pin Prescaler and CCPR1H CCPR1L  1, 4, 16 Edge Detect TMR1 T3CCP2 Enable 4 TMR1H TMR1L CCP1CON<3:0> Set CCP2IF 4 Q1:Q4 4 CCP2CON<3:0> T3CCP1 TMR3H TMR3L T3CCP2 TMR3 Enable CCP2 pin Prescaler and CCPR2H CCPR2L  1, 4, 16 Edge Detect TMR1 Enable T3CCP2 TMR1H TMR1L T3CCP1  2010-2015 Microchip Technology Inc. DS40001303H-page 137

PIC18F2XK20/4XK20 11.3 Compare Mode 11.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is Timer1 and/or Timer3 must be running in Timer mode constantly compared against either the TMR1 or TMR3 or Synchronized Counter mode if the CCP module is register pair value. When a match occurs, the CCPx pin using the compare feature. In Asynchronous Counter can be: mode, the compare operation will not work reliably. • driven high 11.3.3 SOFTWARE INTERRUPT MODE • driven low When the Generate Software Interrupt mode is chosen • toggled (high-to-low or low-to-high) (CCPxM<3:0> = 1010), the corresponding CCPx pin is • remain unchanged (that is, reflects the state of the not affected. Only the CCPxIF interrupt flag is affected. I/O latch) 11.3.4 SPECIAL EVENT TRIGGER The action on the pin is based on the value of the mode select bits (CCPxM<3:0>). At the same time, the inter- Both CCP modules are equipped with a Special Event rupt flag bit, CCPxIF, is set. Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. 11.3.1 CCP PIN CONFIGURATION The Special Event Trigger is enabled by selecting The user must configure the CCPx pin as an output by the Compare Special Event Trigger mode clearing the appropriate TRIS bit. (CCPxM<3:0> = 1011). For either CCP module, the Special Event Trigger resets Note: Clearing the CCPxCON register will force the timer register pair for whichever timer resource is the CCPx compare output latch (depend- currently assigned as the module’s time base. This ing on device configuration) to the default allows the CCPRx registers to serve as a programmable low level. This is not the PORTB or period register for either timer. PORTC I/O data latch. The Special Event Trigger for CCP2 can also start an A/D conversion. In order to do this, the A/D converter must already be enabled. FIGURE 11-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger Set CCP1IF (Timer1/Timer3 Reset) CCPR1H CCPR1L CCP1 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCP1CON<3:0> TMR1H TMR1L 0 0 1 TMR3H TMR3L 1 Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) T3CCP1 T3CCP2 Set CCP2IF CCP2 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCPR2H CCPR2L CCP2CON<3:0> DS40001303H-page 138  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 11-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 RCON IPEN SBOREN — RI TO PD POR BOR 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59 TRISB PORTB Data Direction Control Register 59 TRISC PORTC Data Direction Control Register 59 TMR1L Timer1 Register, Low Byte 57 TMR1H Timer1 Register, High Byte 57 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 57 TMR3H Timer3 Register, High Byte 58 TMR3L Timer3 Register, Low Byte 58 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 58 CCPR1L Capture/Compare/PWM Register 1, Low Byte 58 CCPR1H Capture/Compare/PWM Register 1, High Byte 58 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 58 CCPR2L Capture/Compare/PWM Register 2, Low Byte 58 CCPR2H Capture/Compare/PWM Register 2, High Byte 58 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: Not implemented on PIC18F2XK20 devices.  2010-2015 Microchip Technology Inc. DS40001303H-page 139

PIC18F2XK20/4XK20 11.4 PWM Mode The PWM output (Figure11-4) has a time base (period) and a time that the output stays high (duty The PWM mode generates a Pulse-Width Modulated cycle). signal on the CCP2 pin for the CCP module and the P1A through P1D pins for the ECCP module. Hereafter FIGURE 11-4: CCP PWM OUTPUT the modulated output pin will be referred to as the CCPx pin. The duty cycle, period and resolution are Period determined by the following registers: • PR2 Pulse Width TMR2 = PR2 • T2CON TMR2 = CCPRxL:DCxB<1:0> • CCPRxL • CCPxCON TMR2 = 0 In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCPx pin. Since the CCPx pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCPx pin output driver. Note: Clearing the CCPxCON register will relinquish CCPx control of the CCPx pin. Figure11.1.1 shows a simplified block diagram of PWM operation. Figure11-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section11.4.7 “Setup for PWM Operation”. FIGURE 11-3: SIMPLIFIED PWM BLOCK DIAGRAM DCxB<1:0> Duty Cycle Registers CCPRxL CCPRxH(2) (Slave) CCPx Comparator R Q S TMR2 (1) TRIS Comparator Clear Timer2, toggle CCPx pin and latch duty cycle PR2 Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. 2: In PWM mode, CCPRxH is a read-only register. DS40001303H-page 140  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 11.4.1 PWM PERIOD 11.4.2 PWM DUTY CYCLE The PWM period is specified by the PR2 register of The PWM duty cycle is specified by writing a 10-bit Timer2. The PWM period can be calculated using the value to multiple registers: CCPRxL register and formula of Equation11-1. DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB<1:0> EQUATION 11-1: PWM PERIOD bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB<1:0> bits of the CCPxCON PWM Period = PR2+14TOSC register can be written to at any time. The duty cycle (TMR2 Prescale Value) value is not latched into CCPRxH until after the period completes (i.e., a match between PR2 and TMR2 Note: TOSC = 1/FOSC. registers occurs). While using the PWM, the CCPRxH register is read-only. When TMR2 is equal to PR2, the following three events Equation11-2 is used to calculate the PWM pulse occur on the next increment cycle: width. • TMR2 is cleared Equation11-3 is used to calculate the PWM duty cycle • The CCPx pin is set. (Exception: If the PWM duty ratio. cycle=0%, the pin will not be set.) • The PWM duty cycle is latched from CCPRxL into EQUATION 11-2: PULSE WIDTH CCPRxH. Pulse Width = CCPRxL:DCxB<1:0>  Note: The Timer2 postscaler (see Section14.1 TOSC  (TMR2 Prescale Value) “Timer2 Operation”) is not used in the determination of the PWM frequency. EQUATION 11-3: DUTY CYCLE RATIO CCPRxL:DCxB<1:0> Duty Cycle Ratio = ----------------------------------------------------------- 4PR2+1 The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure11-3).  2010-2015 Microchip Technology Inc. DS40001303H-page 141

PIC18F2XK20/4XK20 11.4.3 PWM RESOLUTION EQUATION 11-4: PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution log4PR2+1 Resolution = ------------------------------------------ bits will result in 1024 discrete duty cycles, whereas an 8-bit log2 resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is Note: If the pulse width value is greater than the 255. The resolution is a function of the PR2 register period the assigned PWM pin(s) will value as shown by Equation11-4. remain unchanged. TABLE 11-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 TABLE 11-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 11-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 DS40001303H-page 142  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 11.4.4 OPERATION IN POWER-MANAGED 11.4.7 SETUP FOR PWM OPERATION MODES The following steps should be taken when configuring In Sleep mode, the TMR2register will not increment the CCP module for PWM operation: and the state of the module will not change. If the CCPx 1. Disable the PWM pin (CCPx) output drivers by pin is driving a value, it will continue to drive that value. setting the associated TRIS bit. When the device wakes up, TMR2 will continue from its 2. For the ECCP module only: Select the desired previous state. PWM outputs (P1A through P1D) by setting the In PRI_IDLE mode, the primary clock will continue to appropriate steering bits of the PSTRCON clock the CCP module without change. In all other register. power-managed modes, the selected power-managed 3. Set the PWM period by loading the PR2 register. mode clock will clock Timer2. Other power-managed 4. Configure the CCP module for the PWM mode mode clocks will most likely be different than the by loading the CCPxCON register with the primary clock frequency. appropriate values. 11.4.5 CHANGES IN SYSTEM CLOCK 5. Set the PWM duty cycle by loading the CCPRxL FREQUENCY register and CCPx bits of the CCPxCON register. 6. Configure and start Timer2: The PWM frequency is derived from the system clock • Clear the TMR2IF interrupt flag bit of the frequency. Any changes in the system clock frequency PIR1 register. will result in changes to the PWM frequency. See Section2.0 “Oscillator Module (With Fail-Safe • Set the Timer2 prescale value by loading the Clock Monitor)” for additional details. T2CKPS bits of the T2CON register. • Enable Timer2 by setting the TMR2ON bit of 11.4.6 EFFECTS OF RESET the T2CON register. Any Reset will force all ports to Input mode and the 7. Enable PWM output after a new PWM cycle has CCP registers to their Reset states. started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCPx pin output driver by clearing the associated TRIS bit.  2010-2015 Microchip Technology Inc. DS40001303H-page 143

PIC18F2XK20/4XK20 TABLE 11-7: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 RCON IPEN SBOREN — RI TO PD POR BOR 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 TRISB PORTB Data Direction Control Register 59 TRISC PORTC Data Direction Control Register 59 TMR2 Timer2 Register 57 PR2 Timer2 Period Register 57 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 57 CCPR1L Capture/Compare/PWM Register 1, Low Byte 58 CCPR1H Capture/Compare/PWM Register 1, High Byte 58 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 58 CCPR2L Capture/Compare/PWM Register 2, Low Byte 58 CCPR2H Capture/Compare/PWM Register 2, High Byte 58 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 58 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 58 PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC PDC0 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: Not implemented on PIC18F2XK20 devices. DS40001303H-page 144  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 12.0 TIMER0 MODULE The T0CON register (Register12-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or A simplified block diagram of the Timer0 module in 8-bit counter in both 8-bit or 16-bit modes mode is shown in Figure12-1. Figure12-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value  2010-2015 Microchip Technology Inc. DS40001303H-page 145

PIC18F2XK20/4XK20 12.1 Timer0 Operation 12.2 Timer0 Reads and Writes in 16-Bit Mode Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit of the T0CON TMR0H is not the actual high byte of Timer0 in 16-bit register. In Timer mode (T0CS = 0), the module mode; it is actually a buffered version of the real high increments on every clock by default unless a different byte of Timer0 which is neither directly readable nor prescaler value is selected (see Section12.3 writable (refer to Figure12-2). TMR0H is updated with “Prescaler”). Timer0 incrementing is inhibited for two the contents of the high byte of Timer0 during a read of instruction cycles following a TMR0 register write. The TMR0L. This provides the ability to read all 16 bits of user can work around this by adjusting the value written Timer0 without the need to verify that the read of the to the TMR0 register to compensate for the anticipated high and low byte were valid. Invalid reads could missing increments. otherwise occur due to a rollover between successive The Counter mode is selected by setting the T0CS bit reads of the high and low byte. (= 1). In this mode, Timer0 increments either on every Similarly, a write to the high byte of Timer0 must also rising or falling edge of pin RA4/T0CKI. The increment- take place through the TMR0H Buffer register. Writing ing edge is determined by the Timer0 Source Edge to TMR0H does not directly affect Timer0. Instead, the Select bit, T0SE of the T0CON register; clearing this bit high byte of Timer0 is updated with the contents of selects the rising edge. Restrictions on the external TMR0H when a write occurs to TMR0L. This allows all clock input are discussed below. 16 bits of Timer0 to be updated at once. An external clock source can be used to drive Timer0; however, it must meet certain requirements (see Table) to ensure that the external clock can be syn- chronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 0 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 1 Clocks on Overflow Prescaler T0SE (2 TCY Delay) 8 T0CS 3 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS40001303H-page 146  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 0 1 SIynntecr nwaitlh TMR0L HTigMh RB0yte STMetR 0IF T0CKI pin ProPgrreasmcamlearble 1 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 12.3 Prescaler 12.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software its value is set by the PSA and T0PS<2:0> bits of the control and can be changed “on-the-fly” during program T0CON register which determine the prescaler execution. assignment and prescale ratio. 12.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When the prescaler is assigned, The TMR0 interrupt is generated when the TMR0 reg- prescale values from 1:2 through 1:256 in integer ister overflows from FFh to 00h in 8-bit mode, or from power-of-2 increments are selectable. FFFFh to 0000h in 16-bit mode. This overflow sets the When assigned to the Timer0 module, all instructions TMR0IF flag bit. The interrupt can be masked by clear- writing to the TMR0 register (e.g., CLRF TMR0, MOVWF ing the TMR0IE bit of the INTCON register. Before TMR0, BSF TMR0, etc.) clear the prescaler count. re-enabling the interrupt, the TMR0IF bit must be cleared by software in the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TMR0L Timer0 Register, Low Byte 57 TMR0H Timer0 Register, High Byte 57 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 57 TRISA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 59 Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’.  2010-2015 Microchip Technology Inc. DS40001303H-page 147

PIC18F2XK20/4XK20 13.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is shown in Figure13-1. A block diagram of the module’s The Timer1 timer/counter module incorporates the operation in Read/Write mode is shown in Figure13-2. following features: The module incorporates its own low-power oscillator • Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1 counter oscillator can also be used as a low-power clock source • Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation. and TMR1L) Timer1 can also be used to provide Real-Time Clock • Selectable internal or external clock source and (RTC) functionality to applications with only a minimal Timer1 oscillator options addition of external components and code overhead. • Interrupt-on-overflow Timer1 is controlled through the T1CON Control • Reset on CCP Special Event Trigger register (Register13-1). It also contains the Timer1 • Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON of the T1CON register. REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Main system clock is derived from Timer1 oscillator 0 = Main system clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 =Timer1 oscillator is enabled 0 =Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 DS40001303H-page 148  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 13.1 Timer1 Operation instruction cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of either the Timer1 Timer1 can operate in one of the following modes: external clock input or the Timer1 oscillator, if enabled. • Timer When the Timer1 oscillator is enabled, the digital • Synchronous Counter circuitry associated with the RC1/T1OSI and • Asynchronous Counter RC0/T1OSO/T13CKI pins is disabled. This means the values of TRISC<1:0> are ignored and the pins are The operating mode is determined by the clock select read as ‘0’. bit, TMR1CS of the T1CON register. When TMR1CS is cleared (= 0), Timer1 increments on every internal FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input On/Off 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Clear TMR1 TMR1L HTigMh RB1yte TMSRet1 IF (CCP Special Event Trigger) on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 T1CKPS<1:0> On/Off T1SYNC TMR1ON Clear TMR1 TMR1L HTigMh RB1yte TMSRet1 IF (CCP Special Event Trigger) on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.  2010-2015 Microchip Technology Inc. DS40001303H-page 149

PIC18F2XK20/4XK20 13.2 Clock Source Selection 13.2.3 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER The TMR1CS bit of the T1CON register is used to MODE select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source Reading TMR1H or TMR1L while the timer is running is supplied externally. from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user 13.2.1 INTERNAL CLOCK SOURCE should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the When the internal clock source is selected, the timer may overflow between the reads. TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler. For writes, it is recommended that the user simply stop the timer and write the desired values. A write 13.2.2 EXTERNAL CLOCK SOURCE contention may occur by writing to the timer registers, When the external clock source is selected, the Timer1 while the register is incrementing. This may produce an module may work as a timer or a counter. unpredictable value in the TMR1H:TTMR1L register pair. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the 13.3 Timer1 Prescaler Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. Timer1 has four prescaler options allowing 1, 2, 4 or 8 If an external clock oscillator is needed (and the divisions of the clock input. The T1CKPS bits of the microcontroller is using the INTOSC without CLKOUT), T1CON register control the prescale counter. The Timer1 can use the LP oscillator as a clock source. prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to Note: In Counter mode, a falling edge must be TMR1H or TMR1L. registered by the counter prior to the first incrementing rising edge after one or more 13.4 Timer1 Operation in of the following conditions (see Asynchronous Counter Mode Figure13-3): • Timer1 is enabled after POR or BOR If control bit T1SYNC of the T1CON register is set, the Reset external clock input is not synchronized. The timer continues to increment asynchronous to the internal • A write to TMR1H or TMR1L phase clocks. The timer will continue to run during • Timer1 is disabled (TMR1ON = 0) Sleep and can generate an interrupt on overflow, when T1CKI is high then Timer1 is which will wake-up the processor. However, special enabled (TMR1ON = 1) when T1CKI precautions in software are needed to read/write the is low. timer (see Section13.2.3 “Reading and Writing Timer1 in Asynchronous Counter Mode”). Note1: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. FIGURE 13-3: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. DS40001303H-page 150  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 13.5 Timer1 16-Bit Read/Write Mode TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Timer1 can be configured for 16-bit reads and writes (see Figure13-2). When the RD16 control bit of the Osc Type Freq C1 C2 T1CON register is set, the address for TMR1H is LP 32kHz 27pF(1) 27pF(1) mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high Note1: Microchip suggests these values only as byte of Timer1 into the Timer1 high byte buffer. This a starting point in validating the oscillator provides the user with the ability to accurately read all circuit. 16 bits of Timer1 without the need to determine 2: Higher capacitance increases the stabil- whether a read of the high byte, followed by a read of ity of the oscillator but also increases the the low byte, has become invalid due to a rollover or start-up time. carry between reads. 3: Since each resonator/crystal has its own Writing to TMR1H does not directly affect Timer1. characteristics, the user should consult Instead, the high byte of Timer1 is updated with the the resonator/crystal manufacturer for contents of TMR1H when a write occurs to TMR1L. appropriate values of external This allows all 16 bits of Timer1 to be updated at once. components. The high byte of Timer1 is not directly readable or 4: Capacitor values are for design guidance writable in this mode. All reads and writes must take only. place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. 13.6.1 USING TIMER1 AS A The prescaler is only cleared on writes to TMR1L. CLOCK SOURCE The Timer1 oscillator is also available as a clock source 13.6 Timer1 Oscillator in power-managed modes. By setting the clock select An on-chip crystal oscillator circuit is incorporated bits, SCS<1:0> of the OSCCON register, to ‘01’, the between pins T1OSI (input) and T1OSO (amplifier device switches to SEC_RUN mode; both the CPU and output). It is enabled by setting the Timer1 Oscillator peripherals are clocked from the Timer1 oscillator. If the Enable bit, T1OSCEN of the T1CON register. The IDLEN bit of the OSCCON register is cleared and a oscillator is a low-power circuit rated for 32kHz crystals. SLEEP instruction is executed, the device enters It will continue to run during all power-managed modes. SEC_IDLE mode. Additional details are available in The circuit for a typical LP oscillator is shown in Section3.0 “Power-Managed Modes”. Figure13-4. Table13-1 shows the capacitor selection Whenever the Timer1 oscillator is providing the clock for the Timer1 oscillator. source, the Timer1 system clock status flag, T1RUN of The user must provide a software time delay to ensure the T1CON register, is set. This can be used to deter- proper start-up of the Timer1 oscillator. mine the controller’s current clocking mode. It can also indicate which clock source is currently being used by FIGURE 13-4: EXTERNAL the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing COMPONENTS FOR THE the clock, polling the T1RUN bit will indicate whether TIMER1 LP OSCILLATOR the clock is being provided by the Timer1 oscillator or C1 another source. PIC® MCU 27 pF T1OSI XTAL 32.768 kHz T1OSO C2 27 pF Note: See the Notes with Table13-1 for additional information about capacitor selection.  2010-2015 Microchip Technology Inc. DS40001303H-page 151

PIC18F2XK20/4XK20 13.6.2 LOW-POWER TIMER1 OPTION 13.7 Timer1 Interrupt The Timer1 oscillator can operate at two distinct levels The TMR1 register pair (TMR1H:TMR1L) increments of power consumption based on device configuration. from 0000h to FFFFh and rolls over to 0000h. The When the LPT1OSC Configuration bit of the Timer1 interrupt, if enabled, is generated on overflow, CONFIG3H register is set, the Timer1 oscillator which is latched in the TMR1IF interrupt flag bit of the operates in a low-power mode. When LPT1OSC is not PIR1 register. This interrupt can be enabled or disabled set, Timer1 operates at a higher power level. Power by setting or clearing the TMR1IE Interrupt Enable bit consumption for a particular mode is relatively of the PIE1 register. constant, regardless of the device’s operating mode. The default Timer1 configuration is the higher power 13.8 Resetting Timer1 Using the CCP mode. Special Event Trigger As the low-power Timer1 mode tends to be more sensitive to interference, high noise environments may If either of the CCP modules is configured to use Timer1 cause some oscillator instability. The low-power option is, and generate a Special Event Trigger in Compare mode therefore, best suited for low noise applications where (CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will power conservation is an important design consideration. reset Timer1. The trigger from CCP2 will also start an A/D conversion if the A/D module is enabled (see 13.6.3 TIMER1 OSCILLATOR LAYOUT Section11.3.4 “Special Event Trigger” for more CONSIDERATIONS information). The Timer1 oscillator circuit draws very little power The module must be configured as either a timer or a during operation. Due to the low-power nature of the synchronous counter to take advantage of this feature. oscillator, it may also be sensitive to rapidly changing When used this way, the CCPRH:CCPRL register pair signals in close proximity. effectively becomes a period register for Timer1. The oscillator circuit, shown in Figure13-4, should be If Timer1 is running in Asynchronous Counter mode, located as close as possible to the microcontroller. this Reset operation may not work. There should be no circuits passing within the oscillator In the event that a write to Timer1 coincides with a circuit boundaries other than VSS or VDD. special Event Trigger, the write operation will take If a high-speed circuit must be located near the oscilla- precedence. tor (such as the CCP1 pin in Output Compare or PWM Note: The Special Event Triggers from the mode, or the primary oscillator using the OSC2 pin), a CCP2 module will not set the TMR1IF grounded guard ring around the oscillator circuit, as interrupt flag bit of the PIR1 register. shown in Figure13-5, may be helpful when used on a single-sided PCB or in addition to a ground plane. FIGURE 13-5: OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING VDD VSS OSC1 OSC2 RC0 RC1 RC2 Note: Not drawn to scale. DS40001303H-page 152  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 13.9 Using Timer1 as a Real-Time Clock Since the register pair is 16 bits wide, a 32.768kHz clock source will take two seconds to count up to over- Adding an external LP oscillator to Timer1 (such as the flow. To force the overflow at the required one-second one described in Section13.6 “Timer1 Oscillator” intervals, it is necessary to preload it; the simplest above) gives users the option to include RTC function- method is to set the MSb of TMR1H with a BSF instruc- ality to their applications. This is accomplished with an tion. Note that the TMR1L register is never preloaded inexpensive watch crystal to provide an accurate time or altered; doing so may introduce cumulative error base and several lines of application code to calculate over many cycles. the time. When operating in Sleep mode and using a For this method to be accurate, Timer1 must operate in battery or supercapacitor as a power source, it can Asynchronous mode and the Timer1 overflow interrupt completely eliminate the need for a separate RTC must be enabled (PIE1<0> = 1), as shown in the device and battery backup. routine, RTCinit. The Timer1 oscillator must also be The application code routine, RTCisr, shown in enabled and running at all times. Example13-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented on overflows of the less significant counters. EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done CLRF hours ; Reset hours RETURN ; Done  2010-2015 Microchip Technology Inc. DS40001303H-page 153

PIC18F2XK20/4XK20 TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 TMR1L Timer1 Register, Low Byte 57 TMR1H Timer1 Register, High Byte 57 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 57 Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. DS40001303H-page 154  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 14.0 TIMER2 MODULE 14.1 Timer2 Operation The Timer2 module timer incorporates the following In normal operation, TMR2 is incremented from 00h on features: each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and • 8-bit timer and period registers (TMR2 and PR2, divide-by-16 prescale options; these are selected by respectively) the prescaler control bits, T2CKPS<1:0> of the T2CON • Readable and writable (both registers) register. The value of TMR2 is compared to that of the • Software programmable prescaler (1:1, 1:4 and period register, PR2, on each clock cycle. When the 1:16) two values match, the comparator generates a match • Software programmable postscaler (1:1 through signal as the timer output. This signal also resets the 1:16) value of TMR2 to 00h on the next cycle and drives the • Interrupt on TMR2-to-PR2 match output counter/postscaler (see Section14.2 “Timer2 Interrupt”). • Optional use as the shift clock for the MSSP module The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any The module is controlled through the T2CON register device Reset, whereas the PR2 register initializes to (Register14-1), which enables or disables the timer FFh. Both the prescaler and postscaler counters are and configures the prescaler and postscaler. Timer2 cleared on the following events: can be shut off by clearing control bit, TMR2ON of the T2CON register, to minimize power consumption. • a write to the TMR2 register A simplified block diagram of the module is shown in • a write to the T2CON register Figure14-1. • any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16  2010-2015 Microchip Technology Inc. DS40001303H-page 155

PIC18F2XK20/4XK20 14.2 Timer2 Interrupt 14.3 Timer2 Output Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2-to-PR2 match) pro- the CCP modules, where it is used as a time base for vides the input for the 4-bit output counter/postscaler. operations in PWM mode. This counter generates the TMR2 match interrupt flag Timer2 can be optionally used as the shift clock source which is latched in TMR2IF of the PIR1 register. The for the MSSP module operating in SPI mode. Addi- interrupt is enabled by setting the TMR2 Match Inter- tional information is provided in Section17.0 “Master rupt Enable bit, TMR2IE of the PIE1 register. Synchronous Serial Port (MSSP) Module”. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> of the T2CON register. FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set TMR2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSP) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 TMR2 Timer2 Register 57 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 57 PR2 Timer2 Period Register 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. DS40001303H-page 156  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 15.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure15-1. A block diagram of the module’s The Timer3 module timer/counter incorporates these operation in Read/Write mode is shown in Figure15-2. features: The Timer3 module is controlled through the T3CON • Software selectable operation as a 16-bit timer or register (Register15-1). It also selects the clock source counter options for the CCP modules (see Section11.1.1 • Readable and writable 8-bit registers (TMR3H “CCP Modules and Timer Resources” for more and TMR3L) information). • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 15-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits 1x =Timer3 is the capture/compare clock source for CCP1 and CP2 01 =Timer3 is the capture/compare clock source for CCP2 and Timer1 is the capture/compare clock source for CCP1 00 =Timer1 is the capture/compare clock source for CCP1 and CP2 bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3  2010-2015 Microchip Technology Inc. DS40001303H-page 157

PIC18F2XK20/4XK20 15.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS of the T3CON register. When TMR3CS is Timer3 can operate in one of three modes: cleared (= 0), Timer3 increments on every internal • Timer instruction cycle (FOSC/4). When the bit is set, Timer3 • Synchronous Counter increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. • Asynchronous Counter As with Timer1, the digital circuitry associated with the RC1/T1OSI and RC0/T1OSO/T13CKI pins is disabled when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. FIGURE 15-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 On/Off T3CKPS<1:0> T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set CCP1/CCP2 Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS40001303H-page 158  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 15-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T13CKI/T1OSO 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 T3CKPS<1:0> On/Off T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set CCP1/CCP2 Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. 15.2 Timer3 16-Bit Read/Write Mode 15.3 Using the Timer1 Oscillator as the Timer3 Clock Source Timer3 can be configured for 16-bit reads and writes (see Figure15-2). When the RD16 control bit of the The Timer1 internal oscillator may be used as the clock T3CON register is set, the address for TMR3H is source for Timer3. The Timer1 oscillator is enabled by mapped to a buffer register for the high byte of Timer3. setting the T1OSCEN bit of the T1CON register. To use A read from TMR3L will load the contents of the high it as the Timer3 clock source, the TMR3CS bit must byte of Timer3 into the Timer3 High Byte Buffer register. also be set. As previously noted, this also configures This provides the user with the ability to accurately read Timer3 to increment on every rising edge of the all 16 bits of Timer1 without having to determine oscillator source. whether a read of the high byte, followed by a read of The Timer1 oscillator is described in Section13.0 the low byte, has become invalid due to a rollover “Timer1 Module”. between reads. A write to the high byte of Timer3 must also take place 15.4 Timer3 Interrupt through the TMR3H Buffer register. The Timer3 high byte is updated with the contents of TMR3H when a The TMR3 register pair (TMR3H:TMR3L) increments write occurs to TMR3L. This allows a user to write all from 0000h to FFFFh and overflows to 0000h. The 16 bits to both the high and low bytes of Timer3 at once. Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF of the PIR2 The high byte of Timer3 is not directly readable or register. This interrupt can be enabled or disabled by writable in this mode. All reads and writes must take setting or clearing the Timer3 Interrupt Enable bit, place through the Timer3 High Byte Buffer register. TMR3IE of the PIE2 register. Writes to TMR3H do not clear the Timer3 prescaler. The prescaler is only cleared on writes to TMR3L.  2010-2015 Microchip Technology Inc. DS40001303H-page 159

PIC18F2XK20/4XK20 15.5 Resetting Timer3 Using the CCP Special Event Trigger If either of the CCP modules is configured to use Timer3 and to generate a Special Event Trigger in Compare mode (CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will reset Timer3. It will also start an A/D conversion if the A/D module is enabled (see Section11.3.4 “Special Event Trigger” for more information). The module must be configured as either a timer or synchronous counter to take advantage of this feature. When used this way, the CCPR2H:CCPR2L register pair effectively becomes a period register for Timer3. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. In the event that a write to Timer3 coincides with a Special Event Trigger from a CCP module, the write will take precedence. Note: The Special Event Triggers from the CCP2 module will not set the TMR3IF interrupt flag bit of the PIR2 register. TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59 TMR3L Timer3 Register, Low Byte 58 TMR3H Timer3 Register, High Byte 58 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 57 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. DS40001303H-page 160  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 16.0 ENHANCED The enhanced features are discussed in detail in CAPTURE/COMPARE/PWM Section16.4 “PWM (Enhanced Mode)”. Capture, Compare and single-output PWM functions of the (ECCP) MODULE ECCP module are the same as described for the CCP1 is implemented as a standard CCP module with standard CCP module. enhanced PWM capabilities. These include: The control register for the enhanced CCP module is • Provision for two or four output channels shown in Register16-1. It differs from the CCP2CON register in that the two Most Significant bits are • Output steering implemented to control PWM functionality. • Programmable polarity • Programmable dead-band control • Automatic shutdown and restart. REGISTER 16-1: CCP1CON: ENHANCED CAPTURE/COMPARE/PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 P1M<1:0>: Enhanced PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output: P1A, P1B, P1C and P1D controlled by steering (See Section16.4.7 “Pulse Steering Mode”). 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. bit 3-0 CCP1M<3:0>: Enhanced CCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Reserved 0010 = Compare mode, toggle output on match 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF) 1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF) 1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state 1011 = Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CC1IF bit) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low  2010-2015 Microchip Technology Inc. DS40001303H-page 161

PIC18F2XK20/4XK20 In addition to the expanded range of modes available 16.3 Standard PWM Mode through the CCP1CON register and ECCP1AS register, the ECCP module has two additional registers When configured in Single Output mode, the ECCP associated with Enhanced PWM operation and module functions identically to the standard CCP auto-shutdown features. They are: module in PWM mode, as described in Section11.4 “PWM Mode”. This is also sometimes referred to as • PWM1CON (Dead-band delay) “Single CCP” mode, as in Table16-1. • PSTRCON (output steering) 16.1 ECCP Outputs and Configuration The enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTC and PORTD (for PIC18F4XK20 devices) or PORTB (for PIC18F2XK20 devices). The outputs that are active depend on the CCP operating mode selected. The pin assignments are summarized in Table16-1. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1M<1:0> and CCP1M<3:0> bits. The appropriate TRISC and TRISD direction bits for the port pins must also be set as outputs. 16.1.1 ECCP MODULES AND TIMER RESOURCES Like the standard CCP modules, the ECCP module can utilize Timers 1, 2 or 3, depending on the mode selected. Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 is available for modules in PWM mode. Interactions between the standard and enhanced CCP modules are identical to those described for standard CCP modules. Additional details on timer resources are provided in Section11.1.1 “CCP Modules and Timer Resources”. 16.2 Capture and Compare Modes Except for the operation of the Special Event Trigger discussed below, the Capture and Compare modes of the ECCP module are identical in operation to that of CCP2. These are discussed in detail in Section11.2 “Capture Mode” and Section11.3 “Compare Mode”. No changes are required when moving between 28-pin and 40/44-pin devices. 16.2.1 SPECIAL EVENT TRIGGER The Special Event Trigger output of ECCP1 resets the TMR1 or TMR3 register pair, depending on which timer resource is currently selected. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1 or Timer3. DS40001303H-page 162  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 16.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the The Enhanced PWM Mode can generate a PWM signal PWM pins is configurable and is selected by setting the on up to four different output pins with up to ten bits of CCP1M bits in the CCP1CON register appropriately. resolution. It can do this through four different PWM Table16-1 shows the pin assignments for each output modes: Enhanced PWM mode. • Single PWM Figure16-1 shows an example of a simplified block • Half-Bridge PWM diagram of the Enhanced PWM module. • Full-Bridge PWM, Forward mode Note: To prevent the generation of an • Full-Bridge PWM, Reverse mode incomplete waveform when the PWM is To select an Enhanced PWM mode, the P1M bits of the first enabled, the ECCP module waits until CCP1CON register must be set appropriately. the start of a new PWM period before Note: The PWM Enhanced mode is available on generating a PWM signal. the Enhanced Capture/Compare/PWM module (CCP1) only. FIGURE 16-1: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DC1B<1:0> P1M<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L CCP1/P1A CCP1/P1A TRIS CCPR1H (Slave) P1B P1B Output TRIS Comparator R Q Controller P1C P1C TMR2 (1) S TRIS P1D P1D Comparator Clear Timer2, TRIS toggle PWM pin and latch duty cycle PR2 PWM1CON Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. Note1: The TRIS register value for each PWM output must be configured appropriately. 2: Clearing the CCPxCON register will relinquish ECCP control of all PWM output pins. 3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions. TABLE 16-1: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode P1M<1:0> CCP1/P1A P1B P1C P1D Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Outputs are enabled by pulse steering in Single mode. See Register16-4.  2010-2015 Microchip Technology Inc. DS40001303H-page 163

PIC18F2XK20/4XK20 FIGURE 16-2: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse PR2+1 P1M<1:0> Signal 0 Width Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section16.4.6 “Programmable Dead-Band Delay mode”). DS40001303H-page 164  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 16-3: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) P1M<1:0> Signal 0 Pulse PR2+1 Width Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section16.4.6 “Programmable Dead-Band Delay mode”).  2010-2015 Microchip Technology Inc. DS40001303H-page 165

PIC18F2XK20/4XK20 16.4.1 HALF-BRIDGE MODE Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must In Half-Bridge mode, two pins are used as outputs to be cleared to configure P1A and P1B as outputs. drive push-pull loads. The PWM output signal is output on the CCPx/P1A pin, while the complementary PWM FIGURE 16-4: EXAMPLE OF output signal is output on the P1B pin (see HALF-BRIDGE PWM Figure16-5). This mode can be used for Half-Bridge applications, as shown in Figure16-5, or for Full-Bridge OUTPUT applications, where four power switches are being Period Period modulated with two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in P1A(2) Half-Bridge power devices. The value of the PDC<6:0> td bits of the PWM1CON register sets the number of td instruction cycles before the output is driven active. If the P1B(2) value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See (1) (1) (1) Section16.4.6 “Programmable Dead-Band Delay mode” for more details of the dead-band delay td = Dead-Band Delay operations. Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FIGURE 16-5: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A - Load FET Driver + P1B - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver P1A Load FET FET Driver Driver P1B DS40001303H-page 166  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 16.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure16-6. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure16-7. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure16-7. P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 16-6: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D  2010-2015 Microchip Technology Inc. DS40001303H-page 167

PIC18F2XK20/4XK20 FIGURE 16-7: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS40001303H-page 168  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 16.4.2.1 Direction Change in Full-Bridge The Full-Bridge mode does not provide dead-band Mode delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation In the Full-Bridge mode, the P1M1 bit in the CCP1CON where dead-band delay is required. This situation register allows users to control the forward/reverse occurs when both of the following conditions are true: direction. When the application firmware changes this direction control bit, the module will change to the new 1. The direction of the PWM output changes when direction on the next PWM cycle. the duty cycle of the output is at or near 100%. 2. The turn off time of the power switch, including A direction change is initiated in software by changing the power device and driver circuit, is greater the P1M1 bit of the CCP1CON register. The following than the turn on time. sequence occurs prior to the end of the current PWM period: Figure16-9 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty • The modulated outputs (P1B and P1D) are placed cycle. In this example, at time t1, the output P1A and in their inactive state. P1D become inactive, while output P1C becomes • The associated unmodulated outputs (P1A and active. Since the turn off time of the power devices is P1C) are switched to drive in the opposite longer than the turn on time, a shoot-through current direction. will flow through power devices QC and QD (see • PWM modulation resumes at the beginning of the Figure16-6) for the duration of ‘t’. The same next period. phenomenon will occur to power devices QA and QB See Figure16-8 for an illustration of this sequence. for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 16-8: EXAMPLE OF PWM DIRECTION CHANGE Period(1) Period Signal P1A (Active-High) P1B (Active-High) Pulse Width P1C (Active-High) (2) P1D (Active-High) Pulse Width Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is (1/FOSC)  TMR2 prescale value.  2010-2015 Microchip Technology Inc. DS40001303H-page 169

PIC18F2XK20/4XK20 FIGURE 16-9: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential T = TOFF – TON Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver. 16.4.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external cir- cuits must keep the power switch devices in the Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). The CCP1M<1:0> bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. DS40001303H-page 170  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 16.4.4 ENHANCED PWM A shutdown condition is indicated by the ECCPASE AUTO-SHUTDOWN MODE (Auto-Shutdown Event Status) bit of the ECCP1AS register. If the bit is a ‘0’, the PWM pins are operating The PWM mode supports an Auto-Shutdown mode that normally. If the bit is a ‘1’, the PWM outputs are in the will disable the PWM outputs when an external shutdown state. shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This When a shutdown event occurs, two things happen: mode is used to help prevent the PWM from damaging The ECCPASE bit is set to ‘1’. The ECCPASE will the application. remain set until cleared in firmware or an auto-restart The auto-shutdown sources are selected using the occurs (see Section16.4.5 “Auto-Restart Mode”). ECCPAS<2:0> bits of the ECCP1AS register. A The enabled PWM pins are asynchronously placed in shutdown event may be generated by: their shutdown states. The PWM output pins are • A logic ‘0’ on the FLT0 pin grouped into pairs [P1A/P1C] and [P1B/P1D]. The state of each pin pair is determined by the PSSAC and • Comparator C1 PSSBD bits of the ECCP1AS register. Each pin pair may • Comparator C2 be placed into one of three states: • Setting the ECCPASE bit in firmware • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) REGISTER 16-2: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits 000 =Auto-Shutdown is disabled 001 =Comparator C1OUT output is high 010 =Comparator C2OUT output is high 011 =Either Comparator C1OUT or C2OUT is high 100 =VIL on FLT0 pin 101 =VIL on FLT0 pin or Comparator C1OUT output is high 110 =VIL on FLT0 pin or Comparator C2OUT output is high 111 =VIL on FLT0 pin or Comparator C1OUT or Comparator C2OUT is high bit 3-2 PSSACn: Pins P1A and P1C Shutdown State Control bits 00 = Drive pins P1A and P1C to ‘0’ 01 = Drive pins P1A and P1C to ‘1’ 1x = Pins P1A and P1C tri-state bit 1-0 PSSBDn: Pins P1B and P1D Shutdown State Control bits 00 = Drive pins P1B and P1D to ‘0’ 01 = Drive pins P1B and P1D to ‘1’ 1x = Pins P1B and P1D tri-state  2010-2015 Microchip Technology Inc. DS40001303H-page 171

PIC18F2XK20/4XK20 Note1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period. FIGURE 16-10: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0) PWM Period ShutdownEvent ECCPASE bit PWM Activity Normal PWM ECCPASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes 16.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automati- cally restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register. If auto-restart is enabled, the ECCPASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPASE bit will be cleared via hardware and normal operation will resume. FIGURE 16-11: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) PWM Period ShutdownEvent ECCPASE bit PWM Activity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes DS40001303H-page 172  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 16.4.6 PROGRAMMABLE DEAD-BAND FIGURE 16-12: EXAMPLE OF DELAY MODE HALF-BRIDGE PWM OUTPUT In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power Period Period switches normally require more time to turn off than to turn on. If both the upper and lower power switches are Pulse Width switched at the same time (one turned on, and the P1A(2) other turned off), both switches may be on for a short td period of time until one switch completely turns off. td During this brief interval, a very high current P1B(2) (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this (1) (1) (1) potentially destructive shoot-through current from flowing during switching, turning on either of the power td = Dead-Band Delay switches is normally delayed to allow the other switch to completely turn off. Note 1: At this time, the TMR2 register is equal to the In Half-Bridge mode, a digitally programmable PR2 register. dead-band delay is available to avoid shoot-through 2: Output signals are shown as active-high. current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure16-12 for illustration. The lower seven bits of the associated PWM1CON register (Register16-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 16-13: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A V - Load FET Driver + P1B V - V-  2010-2015 Microchip Technology Inc. DS40001303H-page 173

PIC18F2XK20/4XK20 REGISTER 16-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared by software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits PDCn = Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active DS40001303H-page 174  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 16.4.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the Note: The associated TRIS bits must be set to PWM pins to be the modulated signal. Additionally, the output (‘0’) to enable the pin output driver same PWM signal can be simultaneously available on in order to see the PWM signal on the pin. multiple pins. While the PWM Steering mode is active, CCP1M<1:0> Once the Single Output mode is selected bits of the CCP1CON register select the PWM output (CCP1M<3:2>=11 and P1M<1:0>=00 of the polarity for the P1<D:A> pins. CCP1CON register), the user firmware can bring out The PWM auto-shutdown operation also applies to the same PWM signal to one, two, three or four output PWM Steering mode as described in Section16.4.4 pins by setting the appropriate STR<D:A> bits of the “Enhanced PWM Auto-shutdown mode”. An PSTRCON register, as shown in Table16-1. auto-shutdown event will only affect pins that have PWM outputs enabled. REGISTER 16-4: PSTRCON: PULSE STEERING CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRD: Steering Enable bit D 1 = P1D pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1D pin is assigned to port pin bit 2 STRC: Steering Enable bit C 1 = P1C pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1C pin is assigned to port pin bit 1 STRB: Steering Enable bit B 1 = P1B pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1B pin is assigned to port pin bit 0 STRA: Steering Enable bit A 1 = P1A pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2>=11 and P1M<1:0>=00.  2010-2015 Microchip Technology Inc. DS40001303H-page 175

PIC18F2XK20/4XK20 FIGURE 16-14: SIMPLIFIED STEERING BLOCK DIAGRAM STRA P1A Signal P1A pin CCP1M1 1 PORT Data 0 TRIS STRB P1B pin CCP1M0 1 PORT Data 0 TRIS STRC P1C pin CCP1M1 1 PORT Data 0 TRIS STRD P1D pin CCP1M0 1 PORT Data 0 TRIS Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0>=00 and CCP1M<3:2>=11. 2: Single PWM output requires setting at least one of the STRx bits. DS40001303H-page 176  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 16.4.7.1 Steering Synchronization The STRSYNC bit of the PSTRCON register gives the user two selections of when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRCON register. In this case, the output signal at the P1<D:A> pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. When the STRSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. Figures 16-15 and 16-16 illustrate the timing diagrams of the PWM steering depending on the STRSYNC setting. FIGURE 16-15: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0) PWM Period PWM STRn P1<D:A> PORT Data PORT Data P1n = PWM FIGURE 16-16: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) PWM STRn P1<D:A> PORT Data PORT Data P1n = PWM  2010-2015 Microchip Technology Inc. DS40001303H-page 177

PIC18F2XK20/4XK20 16.4.8 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the ECCP pin is driving a value, it will con- tinue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from HFINTOSC and the postscaler may not be stable immediately. In PRI_IDLE mode, the primary clock will continue to clock the ECCP module without change. In all other power-managed modes, the selected power-managed mode clock will clock Timer2. Other power-managed mode clocks will most likely be different than the primary clock frequency. 16.4.8.1 Operation with Fail-Safe Clock Monitor If the Fail-Safe Clock Monitor is enabled, a clock failure will force the device into the RC_RUN Power-Managed mode and the OSCFIF bit of the PIR2 register will be set. The ECCP will then be clocked from the internal oscillator clock source, which may have a different clock frequency than the primary clock. See the previous section for additional details. 16.4.9 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states. This forces the enhanced CCP module to reset to a state compatible with the standard CCP module. DS40001303H-page 178  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 16-2: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 RCON IPEN SBOREN — RI TO PD POR BOR 55 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59 TRISB PORTB Data Direction Control Register 59 TRISC PORTC Data Direction Control Register 59 TRISD PORTD Data Direction Control Register 59 TMR1L Timer1 Register, Low Byte 57 TMR1H Timer1 Register, High Byte 57 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 57 TMR2 Timer2 Register 57 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 57 PR2 Timer2 Period Register 57 TMR3L Timer3 Register, Low Byte 58 TMR3H Timer3 Register, High Byte 58 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 58 CCPR1L Capture/Compare/PWM Register 1, Low Byte 58 CCPR1H Capture/Compare/PWM Register 1, High Byte 58 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 58 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 58 PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.  2010-2015 Microchip Technology Inc. DS40001303H-page 179

PIC18F2XK20/4XK20 17.0 MASTER SYNCHRONOUS 17.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows eight bits of data to be MODULE synchronously transmitted and received simultaneously. All four modes of SPI are supported. To 17.1 Master SSP (MSSP) Module accomplish communication, typically three pins are used: Overview • Serial Data Out – SDO The Master Synchronous Serial Port (MSSP) module is • Serial Data In – SDI/SDA a serial interface, useful for communicating with other • Serial Clock – SCK/SCL peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, Additionally, a fourth pin may be used when in a Slave display drivers, A/D converters, etc. The MSSP module mode of operation: can operate in one of two modes: • Slave Select – SS • Serial Peripheral Interface (SPI) Figure17-1 shows the block diagram of the MSSP • Inter-Integrated Circuit (I2C) module when operating in SPI mode. - Full Master mode - Slave mode (with general address call) FIGURE 17-1: MSSP BLOCK DIAGRAM The I2C interface supports the following modes in (SPIMODE) hardware: Internal Data Bus • Master mode Read Write • Multi-Master mode • Slave mode SSPBUF Reg 17.2 Control Registers SDI/SDA The MSSP module has seven associated registers. These include: SSPSR Reg • SSPSTA – STATUS register SDO bit 0 Shift Clock • SSPCON1 – First Control register • SSPCON2 – Second Control register • SSPBUF – Transmit/Receive buffer • SSPSR – Shift register (not directly accessible) SS SS Control • SSPADD – Address register Enable • SSPMSK – Address Mask register Edge Select The use of these registers and their individual Configu- ration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. 2 Clock Select Additional details are provided under the individual sections. SSPM<3:0> SMP:CKE ( ) 4 TMR2 Output SCK/SCL 2 2 Edge Select Prescaler TOSC 4, 16, 64 Data to TX/RX in SSPSR TRIS bit DS40001303H-page 180  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.3.1 REGISTERS SSPSR is the shift register used for shifting data in and out. SSPBUF provides indirect access to the SSPSR The MSSP module has four registers for SPI mode register. SSPBUF is the buffer register to which data operation. These are: bytes are written, and from which data bytes are read. • SSPCON1 – Control Register In receive operations, SSPSR and SSPBUF together • SSPSTAT – STATUS register create a double-buffered receiver. When SSPSR • SSPBUF – Serial Receive/Transmit Buffer receives a complete byte, it is transferred to SSPBUF • SSPSR – Shift Register (Not directly accessible) and the SSPIF interrupt is set. SSPCON1 and SSPSTAT are the control and STATUS During transmission, the SSPBUF is not registers in SPI mode operation. The SSPCON1 regis- double-buffered. A write to SSPBUF will write to both ter is readable and writable. The lower six bits of the SSPBUF and SSPSR. SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Output data changes on clock transition from active to idle 0 = Output data changes on clock transition from idle to active bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Note 1: Polarity of clock state is set by the CKP bit of the SSPCON1 register.  2010-2015 Microchip Technology Inc. DS40001303H-page 181

PIC18F2XK20/4XK20 REGISTER 17-2: SSPCON1: MSSP CONTROL 1 REGISTER (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared by software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over- flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared by software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins. When enabled, the SDA and SCL pins must be configured as inputs. 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. DS40001303H-page 182  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.3.2 OPERATION When the application software is expecting to receive valid data, the SSPBUF should be read before the next When initializing the SPI, several options need to be byte of data to transfer is written to the SSPBUF. The specified. This is done by programming the appropriate Buffer Full bit, BF of the SSPSTAT register, indicates control bits (SSPCON1<5:0> and SSPSTAT<7:6>). when SSPBUF has been loaded with the received data These control bits allow the following to be specified: (transmission is complete). When the SSPBUF is read, • Master mode (SCK is the clock output) the BF bit is cleared. This data may be irrelevant if the • Slave mode (SCK is the clock input) SPI is only a transmitter. Generally, the MSSP interrupt • Clock Polarity (Idle state of SCK) is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or • Data Input Sample Phase (middle or end of data written. If the interrupt method is not going to be used, output time) then software polling can be done to ensure that a write • Clock Edge (output data on rising/falling edge of collision does not occur. Example17-1 shows the SCK) loading of the SSPBUF (SSPSR) for data transmission. • Clock Rate (Master mode only) The SSPSR is not directly readable or writable and can • Slave Select mode (Slave mode only) only be accessed by addressing the SSPBUF register. The MSSP consists of a transmit/receive shift register Additionally, the MSSP STATUS register (SSPSTAT) (SSPSR) and a buffer register (SSPBUF). The SSPSR indicates the various status conditions. shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full detect bit, BF of the SSPSTAT register, and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSPCON1 register, will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit  2010-2015 Microchip Technology Inc. DS40001303H-page 183

PIC18F2XK20/4XK20 17.3.3 ENABLING SPI I/O 17.3.4 TYPICAL CONNECTION To enable the serial port, SSP Enable bit, SSPEN of the Figure17-2 shows a typical connection between two SSPCON1 register, must be set. To reset or reconfig- microcontrollers. The master controller (Processor 1) ure SPI mode, clear the SSPEN bit, reinitialize the initiates the data transfer by sending the SCK signal. SSPCON registers and then set the SSPEN bit. This Data is shifted out of both shift registers on their pro- configures the SDI, SDO, SCK and SS pins as serial grammed clock edge and latched on the opposite edge port pins. For the pins to behave as the serial port func- of the clock. Both processors should be programmed to tion, some must have their data direction bits (in the the same Clock Polarity (CKP), then both controllers TRIS register) appropriately programmed as follows: would send and receive data at the same time. Whether the data is meaningful (or dummy data) • SDI is automatically controlled by the SPI module depends on the application software. This leads to • SDO must have corresponding TRIS bit cleared three scenarios for data transmission: • SCK (Master mode) must have corresponding • Master sends data–Slave sends dummy data TRIS bit cleared • Master sends data–Slave sends data • SCK (Slave mode) must have corresponding TRIS bit set • Master sends dummy data–Slave sends data • SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 17-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK Processor 1 Processor 2 DS40001303H-page 184  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.3.5 MASTER MODE The clock polarity is selected by appropriately programming the CKP bit of the SSPCON1 register. The master can initiate the data transfer at any time This then, would give waveforms for SPI because it controls the SCK. The master determines communication as shown in Figure17-3, Figure17-5 when the slave (Processor 2, Figure17-2) is to and Figure17-6, where the MSB is transmitted first. In broadcast data by the software protocol. Master mode, the SPI clock rate (bit rate) is user In Master mode, the data is transmitted/received as programmable to be one of the following: soon as the SSPBUF register is written to. If the SPI is • FOSC/4 (or TCY) only going to receive, the SDO output could be dis- abled (programmed as an input). The SSPSR register • FOSC/16 (or 4 • TCY) will continue to shift in the signal present on the SDI pin • FOSC/64 (or 16 • TCY) at the programmed clock rate. As each byte is • Timer2 output/2 received, it will be loaded into the SSPBUF register as This allows a maximum data rate (at 64 MHz) of if a normal received byte (interrupts and Status bits 16.00Mbps. appropriately set). This could be useful in receiver applications as a “Line Activity Monitor” mode. Figure17-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2 SSPBUF  2010-2015 Microchip Technology Inc. DS40001303H-page 185

PIC18F2XK20/4XK20 17.3.6 SLAVE MODE must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When In Slave mode, the data is transmitted and received as the SS pin goes high, the SDO pin is no longer driven, the external clock pulses appear on SCK. When the even if in the middle of a transmitted byte and becomes last bit is latched, the SSPIF interrupt flag bit is set. a floating output. External pull-up/pull-down resistors Before enabling the module in SPI Slave mode, the clock may be desirable depending on the application. line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is Note 1: When the SPI is in Slave mode with SS pin determined by the CKP bit of the SSPCON1 register. control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is While in Slave mode, the external clock is supplied by set to VDD. the external clock source on the SCK pin. This external clock must meet the minimum high and low times as 2: When the SPI is used in Slave mode with specified in the electrical specifications. CKE set the SS pin control must also be enabled. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device will wake-up When the SPI module resets, the bit counter is forced from Sleep. to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. 17.3.7 SLAVE SELECT To emulate two-wire communication, the SDO pin can SYNCHRONIZATION be connected to the SDI pin. When the SPI needs to The SS pin allows a Synchronous Slave mode. The operate as a receiver, the SDO pin can be configured SPI must be in Slave mode with SS pin control enabled as an input. This disables transmissions from the SDO. (SSPCON1<3:0> = 04h). The pin must not be driven The SDI can always be left as an input (SDI function) low for the SS pin to function as an input. The data latch since it cannot create a bus conflict. FIGURE 17-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2 SSPBUF DS40001303H-page 186  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2 SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF  2010-2015 Microchip Technology Inc. DS40001303H-page 187

PIC18F2XK20/4XK20 17.3.8 OPERATION IN POWER-MANAGED Transmit/Receive Shift register. When all eight bits MODES have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in 17.3.9 EFFECTS OF A RESET the case of the Sleep mode, all clocks are halted. A Reset disables the MSSP module and terminates the In all Idle modes, a clock is provided to the peripherals. current transfer. That clock could be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or 17.3.10 BUS MODE COMPATIBILITY the INTOSC source. See Section3.0 “Power-Man- Table17-1 shows the compatibility between the aged Modes” for additional information. standard SPI modes and the states of the CKP and In most cases, the speed that the master clocks SPI CKE control bits. data is not important; however, this should be evaluated for each system. TABLE 17-1: SPI BUS MODES When MSSP interrupts are enabled, after the master Control Bits State Standard SPI Mode completes sending data, an MSSP interrupt will wake Terminology the controller: CKP CKE • from Sleep, in Slave mode 0, 0 0 1 • from Idle, in Slave or Master mode 0, 1 0 0 If an exit from Sleep or Idle mode is not desired, MSSP 1, 0 1 1 interrupts should be disabled. 1, 1 1 0 In SPI master mode, when the Sleep mode is selected, There is also an SMP bit which controls when the data all module clocks are halted and the transmis- is sampled. sion/reception will remain in that state until the devices wakes. After the device returns to Run mode, the mod- ule will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 TRISA TRISA7(2) TRISA6(2) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 59 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 59 SSPBUF SSP Receive Buffer/Transmit Register 57 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 57 SSPSTAT SMP CKE D/A P S R/W UA BF 57 Legend: Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. DS40001303H-page 188  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.4 I2C Mode 17.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has seven registers for I2C master and slave functions (including general call operation. These are: support) and provides interrupts on Start and Stop bits • MSSP Control Register 1 (SSPCON1) in hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPCON2) function). The MSSP module implements the standard • MSSP STATUS register (SSPSTAT) mode specifications as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPBUF) Two pins are used for data transfer: • MSSP Shift Register (SSPSR) – Not directly • Serial clock (SCL) – SCK/SCL accessible • Serial data (SDA) – SDI/SDA • MSSP Address Register (SSPADD) The user must configure these pins as inputs with the • MSSP Address Mask (SSPMSK) corresponding TRIS bits. SSPCON1, SSPCON2 and SSPSTAT are the control and STATUS registers in I2C mode operation. The FIGURE 17-7: MSSP BLOCK DIAGRAM SSPCON1 and SSPCON2 registers are readable and (I2C™ MODE) writable. The lower six bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are Internal read/write. Data Bus SSPSR is the shift register used for shifting data in or Read Write out. SSPBUF is the buffer register to which data bytes are written to or read from. SSPBUF Reg SCK/SCL When the SSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator Shift Clock reload value. When the SSP is configured for I2C slave mode the SSPADD register holds the slave device SSPSR Reg address. The SSP can be configured to respond to a SDI/SDA MSb LSb range of addresses by qualifying selected bits of the address register with the SSPMSK register. SSPMSK Reg In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR Match Detect Addr Match receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. SSPADD Reg During transmission, the SSPBUF is not Start and Set, Reset double-buffered. A write to SSPBUF will write to both Stop bit Detect S, P bits SSPBUF and SSPSR. (SSPSTAT Reg)  2010-2015 Microchip Technology Inc. DS40001303H-page 189

PIC18F2XK20/4XK20 REGISTER 17-3: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Master mode bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode: Most significant address byte bit 7-3 Not used: Unused for most significant address byte. Bit state of this register is a don’t care. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<9:8>: Two Most Significant bits of 10-bit Address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode: Least significant address byte bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit Address 7-Bit Slave mode bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. DS40001303H-page 190  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 17-4: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2, 3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit (I2C mode only)(2, 3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPBUF is full 0 = SSPBUF is empty In Receive mode: 1 = SSPBUF is full (does not include the ACK and Stop bits) 0 = SSPBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.  2010-2015 Microchip Technology Inc. DS40001303H-page 191

PIC18F2XK20/4XK20 REGISTER 17-5: SSPCON1: MSSP CONTROL 1 REGISTER (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a trans- mission to be started (must be cleared by software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared by software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared by software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins. When enabled, the SDA and SCL pins must be configured as inputs. 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. DS40001303H-page 192  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 17-6: SSPCON2: MSSP CONTROL REGISTER (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(2) ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Generate interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(2) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master mode only)(1) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only)(1) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(1) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit(1) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled for slave received. Slave transmit clock stretching remains enabled. Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). 2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.  2010-2015 Microchip Technology Inc. DS40001303H-page 193

PIC18F2XK20/4XK20 17.4.2 OPERATION 17.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for SSPEN bit of the SSPCON1 register. a Start condition to occur. Following the Start condition, The SSPCON1 register allows control of the I2C the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the operation. Four mode selection bits of the SSPCON1 register allow one of the following I2C modes to be clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The selected: address is compared on the falling edge of the eighth • I2C Master mode, clock = (FOSC/(4 x clock (SCL) pulse. If the addresses match and the BF (SSPADD+1)) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) 1. The SSPSR register value is loaded into the • I2C Slave mode (10-bit address) SSPBUF register. • I2C Slave mode (7-bit address) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Slave mode (10-bit address) with Start and 4. MSSP Interrupt Flag bit, SSPIF of the PIR1 reg- Stop bit interrupts enabled ister, is set (interrupt is generated, if enabled) on • I2C Firmware Controlled Master mode, slave is the falling edge of the ninth SCL pulse. Idle In 10-bit Address mode, two address bytes need to be Selection of any I2C mode with the SSPEN bit set, received by the slave. The five Most Significant bits forces the SCL and SDA pins to be open-drain, (MSbs) of the first address byte specify if this is a 10-bit provided these pins are programmed to inputs by address. Bit R/W of the SSPSTAT register must specify setting the appropriate TRIS bits. To ensure proper a write so the slave device will receive the second operation of the module, pull-up resistors must be address byte. For a 10-bit address, the first byte would provided externally to the SCL and SDA pins. equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the address. The sequence of events for 10-bit 17.4.3 SLAVE MODE address is as follows, with steps 7 through 9 for the In Slave mode, the SCL and SDA pins must be config- slave-transmitter: ured as inputs. The MSSP module will override the 1. Receive first (high) byte of address (bits SSPIF, input state with the output data when required BF and UA (of the SSPSTAT register are set). (slave-transmitter). 2. Update the SSPADD register with second (low) The I2C Slave mode hardware will always generate an byte of address (clears bit UA and releases the interrupt on an address match. Through the mode SCL line). select bits, the user can also choose to interrupt on 3. Read the SSPBUF register (clears bit BF) and Start and Stop bits clear flag bit, SSPIF. When an address is matched, or the data transfer after 4. Receive second (low) byte of address (bits an address match is received, the hardware SSPIF, BF and UA are set). If the address automatically will generate the Acknowledge (ACK) matches then the SCL is held until the next step. pulse and load the SSPBUF register with the received Otherwise the SCL line is not held. value currently in the SSPSR register. 5. Update the SSPADD register with the first (high) Any combination of the following conditions will cause byte of address. (This will clear bit UA and the MSSP module not to give this ACK pulse: release a held SCL line.) • The Buffer Full bit, BF bit of the SSPSTAT 6. Read the SSPBUF register (clears bit BF) and register, is set before the transfer is received. clear flag bit, SSPIF. • The overflow bit, SSPOV bit of the SSPCON1 7. Receive Repeated Start condition. register, is set before the transfer is received. 8. Receive first (high) byte of address (bits SSPIF and BF are set). In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF of the PIR1 register is 9. Read the SSPBUF register (clears bit BF) and set. The BF bit is cleared by reading the SSPBUF clear flag bit, SSPIF. register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101 (See Table26-20). DS40001303H-page 194  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.4.3.2 Reception 17.4.3.3 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPSTAT register is set. The received address is the SSPBUF register and the SDA line is held low loaded into the SSPBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin SCK/SCL is held low regardless of SEN (see Section17.4.4 “Clock When the address byte overflow condition exists, then Stretching” for more detail). By stretching the clock, the no Acknowledge (ACK) pulse is given. An overflow the master will be unable to assert another clock pulse condition is defined as either bit BF bit of the SSPSTAT until the slave is done preparing the transmit data. The register is set, or bit SSPOV bit of the SSPCON1 transmit data must be loaded into the SSPBUF register register is set. which also loads the SSPSR register. Then pin An MSSP interrupt is generated for each data transfer SCK/SCL should be enabled by setting the CKP bit of byte. Flag bit, SSPIF of the PIR1 register, must be the SSPCON1 register. The eight data bits are shifted cleared by software. The SSPSTAT register is used to out on the falling edge of the SCL input. This ensures determine the status of the byte. that the SDA signal is valid during the SCL high time When the SEN bit of the SSPCON2 register is set, (Figure17-9). SCK/SCL will be held low (clock stretch) following The ACK pulse from the master-receiver is latched on each data transfer. The clock must be released by the rising edge of the ninth SCL input pulse. If the SDA setting the CKP bit of the SSPCON1 register. See line is high (not ACK), then the data transfer is Section17.4.4 “Clock Stretching” for more detail. complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared by software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse.  2010-2015 Microchip Technology Inc. DS40001303H-page 195

PIC18F2XK20/4XK20 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 6 D 2 7 D 1 K C A 9 0 D 8 1 D 7 2 D 6 a 3 Receiving Dat D5D4D 345 ared by softwarePBUF is read D6 2 CleSS 7 D 1 K 9 C = 0 A W 8 R/ A1 7 2 )0 A 6 = ess EN ddr A3 5 n S A e Receiving A5A4 34 set to ‘’ wh0 e ot r A6 2 s n e A7 1 0>) ON1<6>) (CKP do SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP DS40001303H-page 196  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 2 FIGURE 17-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S ACK 9 PIF I S D0 8 m S o Data D1 7 Fr Transmitting D6D5D4D3D2 23456 Cleared by software SSPBUF is written by software KP is set by software C D7 1 R ACK 9 PIF IS S S D0 8 m o Fr D1 7 a Transmitting Dat D6D5D4D3D2 23456 Cleared by software SSPBUF is written by software CKP is set by software D7 1 PIF S SCL held lowwhile CPUresponds to S K C A 9 0 = W 8 R/ 1 A 7 ess A2 6 Addr A3 5 g n eivi A4 4 ec R A5 3 A6A7 12 Data in sampled >) 0>) 3 < < T 1 A R T DA CL S SPIF (PI F (SSPS KP S S S B C  2010-2015 Microchip Technology Inc. DS40001303H-page 197

PIC18F2XK20/4XK20 FIGURE 17-10: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 e ceive Data Byte D5D4D3D2 3456 Cleared by softwar e R D6 2 7 D 1 K AC 9 0 D 8 untilD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared by software Cleared by hardware whenSSPADD is updated with highbyte of address d low SPAD D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACK11110A9A8A7A6A5A4A3A2A1 1234567891234567 Cleared by softwareCleared by software AT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag PCON1<6>) AT<1>) UA is set indicating thatCleared by hardwarethe SSPADD needs to bewhen SSPADD is updatedupdatedwith low byte of address UA is set indicating thatSSPADD needs to beupdated (CKP does not reset to ‘’ when SEN = )00 SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C DS40001303H-page 198  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 2 FIGURE 17-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCL low w Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressTransmitting Data ByteR/W=1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared by softwareCleared by software Dummy read of SSPBUFWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address. CKP is set by software CKP is automatically cleared by hard Clock is held low untilupdate of SSPADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared by software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address UA is set indicating thatSSPADD needs to beupdated R/e First Byte of Address 110A9A8 345678 SSPBUF is written withcontents of SSPSR UA is set indicating thatthe SSPADD needs to beupdated Receiv 11 12 AT<0>) AT<1>) ON1<4>) SDA SCLS SSPIF (PIR1<3>) BF (SSPST UA (SSPST CKP (SSPC  2010-2015 Microchip Technology Inc. DS40001303H-page 199

PIC18F2XK20/4XK20 17.4.3.4 SSP Mask Register This register must be initiated prior to setting An SSP Mask (SSPMSK) register is available in I2C SSPM<3:0> bits to select the I2C Slave mode (7-bit or 10-bit address). Slave mode as a mask for the value held in the SSPSR register during an address comparison The SSP Mask register is active during: operation. A zero (‘0’) bit in the SSPMSK register has • 7-bit Address mode: address compare of A<7:1>. the effect of making the corresponding bit in the • 10-bit Address mode: address compare of A<7:0> SSPSR register a “don’t care”. only. The SSP mask has no effect during the This register is reset to all ‘1’s upon any Reset reception of the first (high) byte of the address. condition and, therefore, has no effect on standard SSP operation until written with a mask value. REGISTER 17-7: SSPMSK: SSP MASK REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address(1) I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111): 1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match Note1: The MSK0 bit is used only in 10-bit slave mode. In all other modes, this bit has no effect. DS40001303H-page 200  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.4.4 CLOCK STRETCHING 17.4.4.3 Clock Stretching for 7-bit Slave Transmit Mode Both 7-bit and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. 7-bit Slave Transmit mode implements clock stretching The SEN bit of the SSPCON2 register allows clock by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of of the state of the SEN bit. each data receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line 17.4.4.1 Clock Stretching for 7-bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPBUF before the master device can In 7-bit Slave Receive mode, on the falling edge of the initiate another data transfer sequence (see ninth clock at the end of the ACK sequence if the BF Figure17-9). bit is set, the CKP bit of the SSPCON1 register is Note1: If the user loads the contents of SSPBUF, automatically cleared, forcing the SCL output to be setting the BF bit before the falling edge held low. The CKP being cleared to ‘0’ will assert the of the ninth clock, the CKP bit will not be SCL line low. The CKP bit must be set in the user’s cleared and clock stretching will not ISR before reception is allowed to continue. By holding occur. the SCL line low, the user has time to service the ISR 2: The CKP bit can be set by software and read the contents of the SSPBUF before the regardless of the state of the BF bit. master device can initiate another data transfer sequence. This will prevent buffer overruns from occurring (see Figure17-13). 17.4.4.4 Clock Stretching for 10-bit Slave Transmit Mode Note1: If the user reads the contents of the SSPBUF before the falling edge of the In 10-bit Slave Transmit mode, clock stretching is con- ninth clock, thus clearing the BF bit, the trolled during the first two address sequences by the CKP bit will not be cleared and clock state of the UA bit, just as it is in 10-bit Slave Receive stretching will not occur. mode. The first two addresses are followed by a third address sequence which contains the high-order bits 2: The CKP bit can be set by software of the 10-bit address and the R/W bit set to ‘1’. After regardless of the state of the BF bit. The the third address sequence is performed, the UA bit is user should be careful to clear the BF bit not set, the module is now configured in Transmit in the ISR before the next receive mode and clock stretching is controlled by the BF flag sequence in order to prevent an overflow as in 7-bit Slave Transmit mode (see Figure17-11). condition. 17.4.4.2 Clock Stretching for 10-bit Slave Receive Mode (SEN = 1) In 10-bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence.  2010-2015 Microchip Technology Inc. DS40001303H-page 201

PIC18F2XK20/4XK20 17.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sam- pled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure17-12). FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX – 1 SCL Master device CKP asserts clock Master device deasserts clock WR SSPCON1 DS40001303H-page 202  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 2 FIGURE 17-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R D5 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared by software SPBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 A6 2 >) 6 A7 1 0>) ON1< SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP  2010-2015 Microchip Technology Inc. DS40001303H-page 203

PIC18F2XK20/4XK20 FIGURE 17-14: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) w ent. Clock is not held lobecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not s D 8 1 D 7 e Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared by softwareCleared by softwar Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1by software Note:An update of the SSPADD register beforethe falling edge of the ninth clock will haveno effect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of AddressW = 0 A7A6A5A4A3A2A1A0ACK 912345678 Cleared by software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address after falling edgeof ninth clock UA is set indicating thatSSPADD needs to beupdated Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. Receive First Byte of AddressR/ 1110A9A8 2345678 Cleared by software >) SSPBUF is written withcontents of SSPSR N1<6>) >) UA is set indicating thatthe SSPADD needs to beupdated 1 1 AT<0 PCO AT<1 SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C DS40001303H-page 204  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the The addressing procedure for the I2C bus is such that SSPIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the the master. The exception is the general call address interrupt can be checked by reading the contents of the which can address all devices. When this address is SSPBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device specific or a general call address. Acknowledge. In 10-bit mode, the SSPADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit of the SSPSTAT register is set. If the general call consists of all ‘0’s with R/W = 0. address is sampled when the GCEN bit is set, while the slave is configured in 10-bit Address mode, then the The general call address is recognized when the second half of the address is not necessary, the UA bit GCEN bit of the SSPCON2 is set. Following a Start bit will not be set and the slave will begin receiving data detect, eight bits are shifted into the SSPSR and the after the Acknowledge (Figure17-15). address is compared against the SSPADD. It is also compared to the general call address and fixed in hard- ware. FIGURE 17-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared by software SSPBUF is read SSPOV (SSPCON1<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’  2010-2015 Microchip Technology Inc. DS40001303H-page 205

PIC18F2XK20/4XK20 17.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queuing appropriate SSPM bits in SSPCON1 and by setting the of events. For instance, the user is not SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and are manipulated by the MSSP hardware. immediately write the SSPBUF register to initiate transmission before the Start Master mode of operation is supported by interrupt condition is complete. In this case, the generation on the detection of the Start and Stop con- SSPBUF will not be written to and the ditions. The Stop (P) and Start (S) bits are cleared from WCOL bit will be set, indicating that a write a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the to the SSPBUF did not occur. bus is Idle, with both the S and P bits clear. The following events will cause the SSP Interrupt Flag In Firmware Controlled Master mode, user code bit, SSPIF, to be set (SSP interrupt, if enabled): conducts all I2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options. • Acknowledge transmit 1. Assert a Start condition on SDA and SCL. • Repeated Start 2. Assert a Repeated Start condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. 2 FIGURE 17-16: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM<3:0> Data Bus SSPADD<7:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock ct e SSPSR Detce) MSb LSb L ur e Oo abl WCk s SCL Receive En StAarcGtk bneiont,we Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT) Clock Arbitration Set SSPIF, BCLIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV DS40001303H-page 206  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the SEN bit of the SSPCON2 register. ended with a Stop condition or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDA, while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all eight first byte transmitted contains the slave address of the bits are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted eight bits at a time. After each byte is trans- ACKSTAT bit of the SSPCON2 register. mitted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. bit. In Master Receive mode, the first byte transmitted con- 7. The user loads the SSPBUF with eight bits of tains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDA pin until all eight bits logic ‘1’. Thus, the first byte transmitted is a 7-bit slave are transmitted. address followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDA, while SCL outputs the slave device and writes its value into the serial clock. Serial data is received eight bits at a time. ACKSTAT bit of the SSPCON2 register. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the 10. The MSSP module generates an interrupt at the beginning and end of transmission. end of the ninth clock cycle by setting the SSPIF bit. The Baud Rate Generator used for the SPI mode 11. The user generates a Stop condition by setting operation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See the PEN bit of the SSPCON2 register. Section17.4.7 “Baud Rate” for more detail. 12. Interrupt is generated once the Stop condition is complete.  2010-2015 Microchip Technology Inc. DS40001303H-page 207

PIC18F2XK20/4XK20 17.4.7 BAUD RATE Once the given operation is complete (i.e., In I2C Master mode, the Baud Rate Generator (BRG) transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the reload value is placed in the SSPADD register SCL pin will remain in its last state. (Figure17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. Table17-3 demonstrates clock rates based on The BRG counts down to ‘0’ and stops until another instruction cycles and the BRG value loaded into reload has taken place. The BRG count is decre- SSPADD. mented twice per instruction cycle (TCY) on the Q2 and The minimum SSPADD value for baud rate generation Q4 clocks. In I2C Master mode, the BRG is reloaded is 0x03. automatically. One half of the SCL period is equal to [(SSPADD+1)  2]/FOSC. Therefore SSPADD = (FCY/FSCL) -1. FIGURE 17-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPADD<7:0> SSPM<3:0> Reload Reload SCL Control CLKOUT BRG Down Counter FOSC/2 TABLE 17-3: I2C™ CLOCK RATE W/BRG FSCL FOSC FCY BRG Value (2 Rollovers of BRG) 64 MHz 16 MHz 27h 400 kHz(1) 64 MHz 16 MHz 32h 313.7 kHz 64 MHz 16 MHz 3Fh 250 kHz 40 MHz 10 MHz 18h 400 kHz(1) 40 MHz 10 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 63h 100 kHz 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. DS40001303H-page 208  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure17-18). FIGURE 17-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload  2010-2015 Microchip Technology Inc. DS40001303H-page 209

PIC18F2XK20/4XK20 17.4.8 I2C MASTER MODE START Note: If at the beginning of the Start condition, CONDITION TIMING the SDA and SCL pins are already sam- To initiate a Start condition, the user sets the Start pled low, or if during the Start condition, Enable bit, SEN bit of the SSPCON2 register. If the the SCL line is sampled low before the SDA and SCL pins are sampled high, the Baud Rate SDA line is driven low, a bus collision Generator is reloaded with the contents of occurs, the Bus Collision Interrupt Flag, SSPADD<6:0> and starts its count. If SCL and SDA are BCLIF, is set, the Start condition is aborted both sampled high when the Baud Rate Generator and the I2C module is reset into its Idle times out (TBRG), the SDA pin is driven low. The action state. of the SDA being driven low while SCL is high is the 17.4.8.1 WCOL Status Flag Start condition and causes the S bit of the SSPSTAT1 register to be set. Following this, the Baud Rate Gener- If the user writes the SSPBUF when a Start sequence ator is reloaded with the contents of SSPADD<7:0> is in progress, the WCOL is set and the contents of the and resumes its count. When the Baud Rate Generator buffer are unchanged (the write does not occur). times out (TBRG), the SEN bit of the SSPCON2 register Note: Because queuing of events is not allowed, will be automatically cleared by hardware; the Baud writing to the lower five bits of SSPCON2 Rate Generator is suspended, leaving the SDA line is disabled until the Start condition is held low and the Start condition is complete. complete. FIGURE 17-19: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st bit 2nd bit SDA TBRG SCL TBRG S DS40001303H-page 210  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start of the SSPCON2 register is programmed high and the condition occurs if: I2C logic module is in the Idle state. When the RSEN bit • SDA is sampled low when SCL goes is set, the SCL pin is asserted low. When the SCL pin from low-to-high. is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. • SCL goes low before SDA is The SDA pin is released (brought high) for one Baud asserted low. This may indicate that Rate Generator count (TBRG). When the Baud Rate another master is attempting to Generator times out, if SDA is sampled high, the SCL transmit a data ‘1’. pin will be deasserted (brought high). When SCL is Immediately following the SSPIF bit getting set, the user sampled high, the Baud Rate Generator is reloaded may write the SSPBUF with the 7-bit address in 7-bit with the contents of SSPADD<7:0> and begins count- mode or the default first address in 10-bit mode. After the ing. SDA and SCL must be sampled high for one TBRG. first eight bits are transmitted and an ACK is received, This action is then followed by assertion of the SDA pin the user may then transmit an additional eight bits of (SDA = 0) for one TBRG while SCL is high. Following address (10-bit mode) or eight bits of data (7-bit mode). this, the RSEN bit of the SSPCON2 register will be automatically cleared and the Baud Rate Generator will 17.4.9.1 WCOL Status Flag not be reloaded, leaving the SDA pin held low. As soon If the user writes the SSPBUF when a Repeated Start as a Start condition is detected on the SDA and SCL sequence is in progress, the WCOL is set and the pins, the S bit of the SSPSTAT register will be set. The contents of the buffer are unchanged (the write does SSPIF bit will not be set until the Baud Rate Generator not occur). has timed out. Note: Because queuing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete. FIGURE 17-20: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPCON2 occurs here. SDA = 1, At completion of Start bit, SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change). and sets SSPIF TBRG TBRG TBRG SDA 1st bit RSEN bit set by hardware on falling edge of ninth clock, Write to SSPBUF occurs here end of Xmit TBRG SCL TBRG Sr = Repeated Start  2010-2015 Microchip Technology Inc. DS40001303H-page 211

PIC18F2XK20/4XK20 17.4.10 I2C MASTER MODE 17.4.10.3 ACKSTAT Status Flag TRANSMISSION In Transmit mode, the ACKSTAT bit of the SSPCON2 Transmission of a data byte, a 7-bit address or the register is cleared when the slave has sent an Acknowl- other half of a 10-bit address is accomplished by simply edge (ACK=0) and is set when the slave does not writing a value to the SSPBUF register. This action will Acknowledge (ACK = 1). A slave sends an Acknowl- set the Buffer Full flag bit, BF and allow the Baud Rate edge when it has recognized its address (including a Generator to begin counting and start the next trans- general call), or when the slave has properly received mission. Each bit of address/data will be shifted out its data. onto the SDA pin after the falling edge of SCL is 17.4.11 I2C MASTER MODE RECEPTION asserted (see data hold time specification parameter106). SCL is held low for one Baud Rate Master mode reception is enabled by programming the Generator rollover count (TBRG). Data should be valid Receive Enable bit, RCEN bit of the SSPCON2 before SCL is released high (see data setup time spec- register. ification parameter 107). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA Note: The MSSP module must be in an Idle pin must remain stable for that duration and some hold state before the RCEN bit is set or the time after the next falling edge of SCL. After the eighth RCEN bit will be disregarded. bit is shifted out (the falling edge of the eighth clock), The Baud Rate Generator begins counting and on each the BF flag is cleared and the master releases SDA. rollover, the state of the SCL pin changes This allows the slave device being addressed to (high-to-low/low-to-high) and data is shifted into the respond with an ACK bit during the ninth bit time if an SSPSR. After the falling edge of the eighth clock, the address match occurred, or if data was received prop- receive enable flag is automatically cleared, the con- erly. The status of ACK is written into the ACKDT bit on tents of the SSPSR are loaded into the SSPBUF, the the falling edge of the ninth clock. If the master receives BF flag bit is set, the SSPIF flag bit is set and the Baud an Acknowledge, the Acknowledge Status bit, Rate Generator is suspended from counting, holding ACKSTAT, is cleared. If not, the bit is set. After the ninth SCL low. The MSSP is now in Idle state awaiting the clock, the SSPIF bit is set and the master clock (Baud next command. When the buffer is read by the CPU, Rate Generator) is suspended until the next data byte the BF flag bit is automatically cleared. The user can is loaded into the SSPBUF, leaving SCL low and SDA then send an Acknowledge bit at the end of reception unchanged (Figure17-21). by setting the Acknowledge Sequence Enable, ACKEN After the write to the SSPBUF, each bit of the address bit of the SSPCON2 register. will be shifted out on the falling edge of SCL until all 17.4.11.1 BF Status Flag seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will In receive operation, the BF bit is set when an address deassert the SDA pin, allowing the slave to respond or data byte is loaded into SSPBUF from SSPSR. It is with an Acknowledge. On the falling edge of the ninth cleared when the SSPBUF register is read. clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the 17.4.11.2 SSPOV Status Flag ACK bit is loaded into the ACKSTAT Status bit of the In receive operation, the SSPOV bit is set when eight SSPCON2 register. Following the falling edge of the bits are received into the SSPSR and the BF flag bit is ninth clock transmission of the address, the SSPIF is already set from a previous reception. set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes 17.4.11.3 WCOL Status Flag place, holding SCL low and allowing SDA to float. If the user writes the SSPBUF when a receive is 17.4.10.1 BF Status Flag already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer In Transmit mode, the BF bit of the SSPSTAT register are unchanged (the write does not occur). is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 17.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software. DS40001303H-page 212  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 17-21: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) ACKSTAT in SSPCON2 = 1 P ared by software K e C 9 Cl A > <6 D0 8 e 2 n slave, clear ACKSTAT bit SSPCON Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared by software service routifrom SSP interrupt SSPBUF is written by software From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to CK re R/W = 0 A1A ss and R/W 789 d by hardware ave A2 ddre 6 eare PCON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPBUF written with 7-bit astart transmit 12345 Cleared by software SSPBUF written After Start condition, SEN cl Sn Write SStart co S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W  2010-2015 Microchip Technology Inc. DS40001303H-page 213

PIC18F2XK20/4XK20 FIGURE 17-22: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from Mastera receiverSDA = ACKDT = SDA = ACKDT = 10CON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveData from SlaveACKD0D2D5D2D3D4D6D7D3D4D1D1D0ACK Bus masterACK is not sentterminatestransfer967898756512344PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit wareCleared by softwareCleared by software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full er configured as ogramming SSP Receiving D5D6D7 312 Cleared by soft Mastby pr ACK from Slave R/W = 0A1ACK 798 Write to SSPCON2<0>(SEN = ),1begin Start condition SEN = 0Write to SSPBUF occurs here,start XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 361245SCLS SSPIF Cleared by softwareSDA = , SCL = 01while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN DS40001303H-page 214  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.4.12 ACKNOWLEDGE SEQUENCE 17.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPCON2 register. At the end of a SSPCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDA pin. If the user wishes to gen- the master will assert the SDA line low. When the SDA erate an Acknowledge, then the ACKDT bit should be line is sampled low, the Baud Rate Generator is cleared. If not, the user should set the ACKDT bit before reloaded and counts down to ‘0’. When the Baud Rate starting an Acknowledge sequence. The Baud Rate Generator times out, the SCL pin will be brought high Generator then counts for one rollover period (TBRG) and one TBRG (Baud Rate Generator rollover count) and the SCL pin is deasserted (pulled high). When the later, the SDA pin will be deasserted. When the SDA SCL pin is sampled high (clock arbitration), the Baud pin is sampled high while SCL is high, the P bit of the Rate Generator counts for TBRG. The SCL pin is then SSPSTAT register is set. A TBRG later, the PEN bit is pulled low. Following this, the ACKEN bit is automatically cleared and the SSPIF bit is set (Figure17-24). cleared, the Baud Rate Generator is turned off and the 17.4.13.1 WCOL Status Flag MSSP module then goes into Idle mode (Figure17-23). If the user writes the SSPBUF when a Stop sequence 17.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write does sequence is in progress, then WCOL is set and the not occur). contents of the buffer are unchanged (the write does not occur). FIGURE 17-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in SSPIF set at Cleared in software the end of receive software SSPIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 17-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period.  2010-2015 Microchip Technology Inc. DS40001303H-page 215

PIC18F2XK20/4XK20 17.4.14 SLEEP OPERATION 17.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or com- plete byte transfer occurs, wake the processor from Multi-Master mode support is achieved by bus arbitra- Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 17.4.15 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0, 17.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure17-25). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit of the SSPSTAT register is set, SSPBUF can be written to. When the user services the or the bus is Idle, with both the S and P bits clear. When bus collision Interrupt Service Routine and if the I2C the bus is busy, enabling the SSP interrupt will gener- bus is free, the user can resume communication by ate the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge condi- monitored for arbitration to see if the signal level is the tion was in progress when the bus collision occurred, the expected output level. This check is performed by condition is aborted, the SDA and SCL lines are deas- hardware with the result placed in the BCLIF bit. serted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus col- The states where arbitration can be lost are: lision Interrupt Service Routine and if the I2C bus is free, • Address Transfer the user can resume communication by asserting a Start • Data Transfer condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data does not match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF DS40001303H-page 216  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.4.17.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure17-28). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure17-26). counts down to 0; if the SCL pin is sampled as ‘0’ b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the (Figure17-27). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a fac- pins are monitored. tor during a Start condition is that no two bus masters can assert a Start condition If the SDA pin is already low, or the SCL pin is already at the exact same time. Therefore, one low, then all of the following occur: master will always assert SDA before the • the Start condition is aborted, other. This condition does not cause a bus • the BCLIF flag is set and collision because the two masters must be • the MSSP module is reset to its Idle state allowed to arbitrate the first address fol- (Figure17-26). lowing the Start condition. If the address is The Start condition begins with the SDA and SCL pins the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded from SSPADD<7:0> Start or Stop conditions. and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 17-26: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared by software S SSPIF SSPIF and BCLIF are cleared by software  2010-2015 Microchip Technology Inc. DS40001303H-page 217

PIC18F2XK20/4XK20 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared by software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable START sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF by software DS40001303H-page 218  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 17.4.17.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure17-29). If SDA is sampled high, the BRG is reloaded and begins During a Repeated Start condition, a bus collision counting. If SDA goes from high-to-low before the BRG occurs if: times out, no bus collision occurs because no two a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time. from low level to high level. If SCL goes from high-to-low before the BRG times out b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision indicating that another master is attempting to occurs. In this case, another master is attempting to transmit a data ‘1’. transmit a data ‘1’ during the Repeated Start condition, When the user deasserts SDA and the pin is allowed to see Figure17-30. float high, the BRG is loaded with SSPADD<7:0> and If, at the end of the BRG time-out, both SCL and SDA counts down to 0. The SCL pin is then deasserted and are still high, the SDA pin is driven low and the BRG is when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 17-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared by software S ‘0’ SSPIF ‘0’ FIGURE 17-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared by software RSEN S ‘0’ SSPIF  2010-2015 Microchip Technology Inc. DS40001303H-page 219

PIC18F2XK20/4XK20 17.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<7:0> a) After the SDA pin has been deasserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure17-31). If the SCL pin is low before SDA goes high. sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure17-32). FIGURE 17-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 17-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’ DS40001303H-page 220  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 17-4: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59 SSPADD SSP Address Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 57 SSPBUF SSP Receive Buffer/Transmit Register 57 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 57 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 57 SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 60 SSPSTAT SMP CKE D/A P S R/W UA BF 57 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by I2C. Note 1: Not implemented on PIC18F2XK20 devices  2010-2015 Microchip Technology Inc. DS40001303H-page 221

PIC18F2XK20/4XK20 18.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer • Half-duplex synchronous master independent of device program execution. The • Half-duplex synchronous slave EUSART, also known as a Serial Communications • Programmable clock and data polarity Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous The EUSART module implements the following system. Full-Duplex mode is useful for additional features, making it ideally suited for use in communications with peripheral systems, such as CRT Local Interconnect Network (LIN) bus systems: terminals and personal computers. Half-Duplex • Automatic detection and calibration of the baud rate Synchronous mode is intended for communications • Wake-up on Break reception with peripheral devices, such as A/D or D/A integrated • 13-bit Break character transmit circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for Block diagrams of the EUSART transmitter and baud rate generation and require the external clock receiver are shown in Figure18-1 and Figure18-2. signal provided by a master synchronous device. FIGURE 18-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREG Register TXIF 8 MSb LSb TX/CK pin (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT Baud Rate Generator FOSC ÷ n TX9 BRG16 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 X 0 0 0 SPBRGH SPBRG BRGH X 1 1 0 0 BRG16 X 1 0 1 0 DS40001303H-page 222  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 18-2: EUSART RECEIVE BLOCK DIAGRAM CREN OERR RCIDL RX/DT pin MSb RSR Register LSb Panind BCuoffnetrrol DReactaovery Stop (8) 7 • • • 1 0 START Baud Rate Generator FOSC RX9 ÷ n BRG16 n + 1 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 FIFO SPBRGH SPBRG BRGH X 1 1 0 0 FERR RX9D RCREG Register BRG16 X 1 0 1 0 8 Data Bus RCIF Interrupt RCIE The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These registers are detailed in Register18-1, Register18-2 and Register18-3, respectively. For all modes of EUSART operation, the TRIS control bits corresponding to the RX/DT and TX/CK pins should be set to ‘1’. The EUSART control will automatically reconfigure the pin from input to output, as needed. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output.  2010-2015 Microchip Technology Inc. DS40001303H-page 223

PIC18F2XK20/4XK20 18.1 EUSART Asynchronous Mode 18.1.1.2 Transmitting Data The EUSART transmits and receives data using the A transmission is initiated by writing a character to the standard non-return-to-zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the implemented with two levels: a VOH mark state which previous character has been completely flushed from represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXREG is immediately represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains consecutively transmitted data bits of the same value all or part of a previous character, the new character stay at the output level of that bit without returning to a data is held in the TXREG until the Stop bit of the neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending transmission port idles in the mark state. Each character character in the TXREG is then transferred to the TSR transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits or nine data bits and is always terminated by one or and Stop bit sequence commences immediately more Stop bits. The Start bit is always a space and the following the transfer of the data to the TSR from the Stop bits are always marks. The most common data TXREG. format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud 18.1.1.3 Transmit Data Polarity Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table18-5 The polarity of the transmit data can be controlled with for examples of baud rate configurations. the CKTXP bit of the BAUDCON register. The default state of this bit is ‘0’ which selects high true transmit The EUSART transmits and receives the LSb first. The idle and data bits. Setting the CKTXP bit to ‘1’ will invert EUSART’s transmitter and receiver are functionally the transmit data resulting in low true idle and data bits. independent, but share the same data format and baud The CKTXP bit controls transmit data polarity only in rate. Parity is not supported by the hardware, but can Asynchronous mode. In Synchronous mode the be implemented in software and stored as the ninth CKTXP bit has a different function. data bit. 18.1.1.4 Transmit Interrupt Flag 18.1.1 EUSART ASYNCHRONOUS TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no The EUSART transmitter block diagram is shown in character is being held for transmission in the TXREG. Figure18-1. The heart of the transmitter is the serial In other words, the TXIF bit is only clear when the TSR Transmit Shift Register (TSR), which is not directly is busy with a character and a new character has been accessible by software. The TSR obtains its data from queued for transmission in the TXREG. The TXIF flag bit the transmit buffer, which is the TXREG register. is not cleared immediately upon writing TXREG. TXIF 18.1.1.1 Enabling the Transmitter becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following The EUSART transmitter is enabled for asynchronous the TXREG write will return invalid results. The TXIF bit operations by configuring the following three control is read-only, it cannot be set or cleared by software. bits: The TXIF interrupt can be enabled by setting the TXIE • TXEN = 1 interrupt enable bit of the PIE1 register. However, the • SYNC = 0 TXIF flag bit will be set whenever the TXREG is empty, • SPEN = 1 regardless of the state of TXIE enable bit. All other EUSART control bits are assumed to be in To use interrupts when transmitting data, set the TXIE their default state. bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character Setting the TXEN bit of the TXSTA register enables the of the transmission to the TXREG. transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: The TXIF transmitter interrupt flag is set when the TXEN enable bit is set. DS40001303H-page 224  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 18.1.1.5 TSR Status 18.1.1.7 Asynchronous Transmission Set-up: The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH:SPBRG register pair and status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired TRMT bit is set when the TSR register is empty and is baud rate (see Section18.3 “EUSART Baud cleared when a character is transferred to the TSR Rate Generator (BRG)”). register from the TXREG. The TRMT bit remains clear 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. until all bits have been shifted out of the TSR register. 3. Enable the asynchronous serial port by clearing No interrupt logic is tied to this bit, so the user needs to the SYNC bit and setting the SPEN bit. poll this bit to determine the TSR status. 4. If 9-bit transmission is desired, set the TX9 con- Note: The TSR register is not mapped in data trol bit. A set ninth data bit will indicate that the memory, so it is not available to the user. eight Least Significant data bits are an address when the receiver is set for address detection. 18.1.1.6 Transmitting 9-Bit Characters 5. Set the CKTXP control bit if inverted transmit The EUSART supports 9-bit character transmissions. data polarity is desired. When the TX9 bit of the TXSTA register is set the 6. Enable the transmission by setting the TXEN EUSART will shift nine bits out for each character trans- control bit. This will cause the TXIF interrupt bit mitted. The TX9D bit of the TXSTA register is the ninth, to be set. and Most Significant, data bit. When transmitting 9-bit 7. If interrupts are desired, set the TXIE interrupt data, the TX9D data bit must be written before writing enable bit. An interrupt will occur immediately the eight Least Significant bits into the TXREG. All nine provided that the GIE and PEIE bits of the bits of data will be transferred to the TSR shift register INTCON register are also set. immediately after the TXREG is written. 8. If 9-bit transmission is selected, the ninth bit A special 9-bit Address mode is available for use with should be loaded into the TX9D data bit. multiple receivers. See Section18.1.2.8 “Address 9. Load 8-bit data into the TXREG register. This Detection” for more information on the Address mode. will start the transmission. FIGURE 18-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC4/C2OUT/TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag)  2010-2015 Microchip Technology Inc. DS40001303H-page 225

PIC18F2XK20/4XK20 FIGURE 18-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) RC4/C2OUT/TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY TRMT bit Word 1 Word 2 Reg(T. rEamnspmtyi tF Slahgif)t Transmit Shift Reg Transmit Shift Reg Note: This timing diagram shows two consecutive transmissions. TABLE 18-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58 TXREG EUSART Transmit Register 58 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58 BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 58 SPBRGH EUSART Baud Rate Generator Register, High Byte 58 SPBRG EUSART Baud Rate Generator Register, Low Byte 58 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear. DS40001303H-page 226  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 18.1.2 EUSART ASYNCHRONOUS 18.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode would typically be used in reception on the falling edge of the first bit. The first bit, RS-232 systems. The receiver block diagram is shown also known as the Start bit, is always a zero. The data in Figure18-2. The data is received on the RX/DT pin recovery circuit counts one-half bit time to the center of and drives the data recovery block. The data recovery the Start bit and verifies that the bit is still a zero. If it is block is actually a high-speed shifter operating at 16 not a zero then the data recovery circuit aborts times the baud rate, whereas the serial Receive Shift character reception, without generating an error, and Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data are immediately transferred to a two character recovery circuit counts a full bit time to the center of the First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. start of a third character before software must start This repeats until all data bits have been sampled and servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always Access to the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this 18.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this character. See Section18.1.2.5 “Receive Framing The EUSART receiver is enabled for asynchronous Error” for more information on framing errors. operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have • CREN = 1 been received, the character in the RSR is transferred • SYNC = 0 to the EUSART receive FIFO and the RCIF interrupt • SPEN = 1 flag bit of the PIR1 register is set. The top character in All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the their default state. RCREG register. Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun of the TXSTA register configures the EUSART for condition is cleared. See Section18.1.2.6 asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more RCSTA register enables the EUSART. The RX/DT I/O information on overrun errors. pin must be configured as an input by setting the corresponding TRIS control bit. If the RX/DT pin is 18.1.2.3 Receive Data Polarity shared with an analog peripheral the analog I/O function The polarity of the receive data can be controlled with must be disabled by clearing the corresponding ANSEL the DTRXP bit of the BAUDCON register. The default bit. state of this bit is ‘0’ which selects high true receive idle and data bits. Setting the DTRXP bit to ‘1’ will invert the receive data resulting in low true idle and data bits. The DTRXP bit controls receive data polarity only in Asynchronous mode. In synchronous mode the DTRXP bit has a different function.  2010-2015 Microchip Technology Inc. DS40001303H-page 227

PIC18F2XK20/4XK20 18.1.2.4 Receive Interrupts 18.1.2.7 Receiving 9-bit Characters The RCIF interrupt flag bit of the PIR1 register is set The EUSART supports 9-bit character reception. When whenever the EUSART receiver is enabled and there is the RX9 bit of the RCSTA register is set, the EUSART an unread character in the receive FIFO. The RCIF will shift nine bits into the RSR for each character interrupt flag bit is read-only, it cannot be set or cleared received. The RX9D bit of the RCSTA register is the by software. ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data RCIF interrupts are enabled by setting the following from the receive FIFO buffer, the RX9D data bit must bits: be read before reading the eight Least Significant bits • RCIE interrupt enable bit of the PIE1 register from the RCREG. • PEIE peripheral interrupt enable bit of the INTCON register 18.1.2.8 Address Detection • GIE global interrupt enable bit of the INTCON A special Address Detection mode is available for use register when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is The RCIF interrupt flag bit will be set when there is an enabled by setting the ADDEN bit of the RCSTA unread character in the FIFO, regardless of the state of register. interrupt enable bits. Address detection requires 9-bit character reception. 18.1.2.5 Receive Framing Error When address detection is enabled, only characters Each character in the receive FIFO buffer has a with the ninth data bit set will be transferred to the corresponding framing error Status bit. A framing error receive FIFO buffer, thereby setting the RCIF interrupt indicates that a Stop bit was not seen at the expected bit. All other characters will be ignored. time. The framing error status is accessed via the Upon receiving an address character, user software FERR bit of the RCSTA register. The FERR bit determines if the address matches its own. Upon represents the status of the top unread character in the address match, user software must disable address receive FIFO. Therefore, the FERR bit must be read detection by clearing the ADDEN bit before the next before reading the RCREG. Stop bit occurs. When user software detects the end of The FERR bit is read-only and only applies to the top the message, determined by the message protocol unread character in the receive FIFO. A framing error used, software places the receiver back into the (FERR = 1) does not preclude reception of additional Address Detection mode by setting the ADDEN bit. characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. 18.1.2.6 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated If a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. DS40001303H-page 228  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 18.1.2.9 Asynchronous Reception Set-up: 18.1.2.10 9-bit Address Detection Mode Set-up 1. Initialize the SPBRGH:SPBRG register pair and This mode would typically be used in RS-485 systems. the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section18.3 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRG register pair and 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. the BRGH and BRG16 bits to achieve the 3. Enable the serial port by setting the SPEN bit desired baud rate (see Section18.3 “EUSART and the RX/DT pin TRIS bit. The SYNC bit must Baud Rate Generator (BRG)”). be clear for asynchronous operation. 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. 4. If interrupts are desired, set the RCIE interrupt 3. Enable the serial port by setting the SPEN bit. enable bit and set the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous INTCON register. operation. 5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE interrupt 6. Set the DTRXP if inverted receive polarity is enable bit and set the GIE and PEIE bits of the desired. INTCON register. 7. Enable reception by setting the CREN bit. 5. Enable 9-bit reception by setting the RX9 bit. 8. The RCIF interrupt flag bit will be set when a 6. Enable address detection by setting the ADDEN character is transferred from the RSR to the bit. receive buffer. An interrupt will be generated if 7. Set the DTRXP if inverted receive polarity is the RCIE interrupt enable bit was also set. desired. 9. Read the RCSTA register to get the error flags 8. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 9. The RCIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 10. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit register. was also set. 11. If an overrun occurred, clear the OERR flag by 10. Read the RCSTA register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 11. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 12. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 13. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts.  2010-2015 Microchip Technology Inc. DS40001303H-page 229

PIC18F2XK20/4XK20 FIGURE 18-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 RCREG RCREG RCIDL Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. TABLE 18-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58 RCREG EUSART Receive Register 58 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 59 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58 BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 58 SPBRGH EUSART Baud Rate Generator Register, High Byte 58 SPBRG EUSART Baud Rate Generator Register, Low Byte 58 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear. DS40001303H-page 230  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 18.2 Clock Accuracy with The first (preferred) method uses the OSCTUNE Asynchronous Operation register to adjust the HFINTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution The factory calibrates the internal oscillator block out- changes to the system clock source. See Section2.5 put (HFINTOSC). However, the HFINTOSC frequency “Internal Clock Modes” for more information. may drift as VDD or temperature changes, and this The other method adjusts the value in the Baud Rate directly affects the asynchronous baud rate. Two meth- Generator. This can be done automatically with the ods may be used to adjust the baud rate clock, but both Auto-Baud Detect feature (see Section18.3.1 require a reference clock source of some kind. “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2010-2015 Microchip Technology Inc. DS40001303H-page 231

PIC18F2XK20/4XK20 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001303H-page 232  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been detected and the receiver is active Synchronous mode: Don’t care bit 5 DTRXP: Data/Receive Polarity Select bit Asynchronous mode: 1 = Receive data (RX) is inverted (active-low) 0 = Receive data (RX) is not inverted (active-high) Synchronous mode: 1 = Data (DT) is inverted (active-low) 0 = Data (DT) is not inverted (active-high) bit 4 CKTXP: Clock/Transmit Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TX) is low 0 = Idle state for transmit (TX) is high Synchronous mode: 1 = Data changes on the falling edge of the clock and is sampled on the rising edge of the clock 0 = Data changes on the rising edge of the clock and is sampled on the falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used (SPBRGH:SPBRG) 0 = 8-bit Baud Rate Generator is used (SPBRG) bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received but RCIF will be set on the falling edge. WUE will automatically clear on the rising edge. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2010-2015 Microchip Technology Inc. DS40001303H-page 233

PIC18F2XK20/4XK20 18.3 EUSART Baud Rate Generator If the system clock is changed during an active receive (BRG) operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to The Baud Rate Generator (BRG) is an 8-bit or 16-bit make sure that the receive operation is Idle before timer that is dedicated to the support of both the changing the system clock. asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the EXAMPLE 18-1: CALCULATING BAUD BRG16 bit of the BAUDCON register selects 16-bit RATE ERROR mode. For a device with FOSC of 16 MHz, desired baud rate The SPBRGH:SPBRG register pair determines the of 9600, Asynchronous mode, 8-bit BRG: period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate Desired Baud Rate = ----------------------------F----O----S---C------------------------------ 64[SPBRGH:SPBRG]+1 period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCON register. In Solving for SPBRGH:SPBRG: Synchronous mode, the BRGH bit is ignored. FOSC --------------------------------------------- Table18-3 contains the formulas for determining the Desired Baud Rate X = ---------------------------------------------–1 baud rate. Example18-1 provides a sample calculation 64 for determining the baud rate and baud rate error. 16000000 ------------------------ Typical baud rates and error values for various 9600 = ------------------------–1 asynchronous modes have been computed for your 64 convenience and are shown in Table18-5. It may be = 25.042 = 25 advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate Calculated Baud Rate = --1---6---0---0---0---0---0---0---- 6425+1 error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. = 9615 Writing a new value to the SPBRGH, SPBRG register Calc. Baud Rate–Desired Baud Rate pair causes the BRG timer to be reset (or cleared). This Error = -------------------------------------------------------------------------------------------- Desired Baud Rate ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. 9615–9600 = ---------------------------------- = 0.16% 9600 TABLE 18-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH, SPBRG register pair TABLE 18-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58 BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 58 SPBRGH EUSART Baud Rate Generator Register, High Byte 58 SPBRG EUSART Baud Rate Generator Register, Low Byte 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS40001303H-page 234  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 — — — 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9615 0.16 103 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 95 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.23k 0.16 51 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k 58.82k 2.12 16 57.60k 0.00 7 — — — 57.60k 0.00 2 115.2k 111.11k -3.55 8 — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 — — — 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 — — — 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 207 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.97k 0.64 68 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 114.29k -0.79 34 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5  2010-2015 Microchip Technology Inc. DS40001303H-page 235

PIC18F2XK20/4XK20 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRGH SPBRGH SPBRGH SPBRGH Actual % Actual % Actual % Actual % :SPBRG :SPBRG :SPBRG :SPBRG Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 13332 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200.1 0.01 3332 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.02 1666 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9592 -0.08 416 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 383 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 207 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.97k 0.64 68 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 114.29k -0.79 34 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRGH SPBRGH SPBRGH SPBRGH Actual % Actual % Actual % Actual % :SPBRG :SPBRG :SPBRG :SPBRG Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — DS40001303H-page 236  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRGH SPBRGH SPBRGH SPBRGH Actual % Actual % Actual % Actual % :SPBRG :SPBRG :SPBRG :SPBRG Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300 0.00 53332 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 0.00 13332 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.00 6666 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9598.1 -0.02 1666 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 1535 10425 0.08 441 10417 0.00 383 10433 0.16 264 19.2k 19.21k 0.04 832 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.55k -0.08 277 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 115.11k -0.08 138 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRGH SPBRGH SPBRGH SPBRGH Actual % Actual % Actual % Actual % :SPBRG :SPBRG :SPBRG :SPBRG Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —  2010-2015 Microchip Technology Inc. DS40001303H-page 237

PIC18F2XK20/4XK20 18.3.1 AUTO-BAUD DETECT and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the Note1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. following the Break character (see Section18.3.3 “Auto-Wake-up on The Baud Rate Generator is used to time the period of Break”). a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the that it has five rising edges including the Stop bit edge. incoming character baud rate is within the Setting the ABDEN bit of the BAUDCON register starts range of the selected BRG clock source. Some combinations of oscillator frequency the auto-baud calibration sequence (Figure18.3.2). While the ABD sequence takes place, the EUSART and EUSART baud rates are not possible. state machine is held in Idle. On the first rising edge of 3: During the auto-baud process, the the receive line, after the Start bit, the SPBRG begins auto-baud counter starts counting at 1. counting up using the BRG counter clock as shown in Upon completion of the auto-baud Table18-6. The fifth rising edge will occur on the RX pin sequence, to achieve maximum accuracy, at the end of the eighth bit period. At that time, an subtract 1 from the SPBRGH:SPBRG accumulated value totaling the proper BRG period is register pair. left in the SPBRGH:SPBRG register pair, the ABDEN bit is automatically cleared, and the RCIF interrupt flag TABLE 18-6: BRG COUNTER CLOCK RATES is set. A read operation on the RCREG needs to be BRG Base BRG ABD performed to clear the RCIF interrupt. RCREG content BRG16 BRGH Clock Clock should be discarded. When calibrating for modes that do not use the SPBRGH register the user can verify 0 0 FOSC/64 FOSC/512 that the SPBRG register did not overflow by checking for 00h in the SPBRGH register. 0 1 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 1 0 FOSC/16 FOSC/128 and BRGH bits as shown in Table18-6. During ABD, 1 1 FOSC/4 FOSC/32 both the SPBRGH and SPBRG registers are used as a Note: During the ABD sequence, SPBRG and 16-bit counter, independent of the BRG16 bit setting. SPBRGH registers are both used as a 16-bit While calibrating the baud rate period, the SPBRGH counter, independent of BRG16 setting. FIGURE 18-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRG XXh 1Ch SPBRGH XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. DS40001303H-page 238  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 18.3.2 AUTO-BAUD OVERFLOW 18.3.3.1 Special Considerations During the course of automatic baud detection, the Break Character ABDOVF bit of the BAUDCON register will be set if the To avoid character errors or character fragments during baud rate counter overflows before the fifth rising edge a wake-up event, the wake-up character must be all is detected on the RX pin. The ABDOVF bit indicates zeros. that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRG register When the wake-up is enabled the function works pair. After the ABDOVF has been set, the counter con- independent of the low time on the data stream. If the tinues to count until the fifth rising edge is detected on WUE bit is set and a valid non-zero character is the RX pin. Upon detecting the fifth RX edge, the hard- received, the low time from the Start bit to the first rising ware will set the RCIF interrupt flag and clear the edge will be interpreted as the wake-up event. The ABDEN bit of the BAUDCON register. The RCIF flag remaining bits in the character will be received as a can be subsequently cleared by reading the RCREG. fragmented character and subsequent characters can The ABDOVF flag can be cleared by software directly. result in framing or overrun errors. To terminate the auto-baud process before the RCIF Therefore, the initial character in the transmission must flag is set, clear the ABDEN bit then clear the ABDOVF be all ‘0’s. This must be ten or more bit times, 13-bit bit. The ABDOVF bit will remain set if the ABDEN bit is times recommended for LIN bus, or any number of bit not cleared first. times for standard RS-232 devices. Oscillator Startup Time 18.3.3 AUTO-WAKE-UP ON BREAK Oscillator start-up time must be considered, especially During Sleep mode, all clocks to the EUSART are in applications using oscillators with longer start-up suspended. Because of this, the Baud Rate Generator intervals (i.e., LP, XT or HS/PLL mode). The Sync is inactive and a proper character reception cannot be Break (or wake-up signal) character must be of performed. The Auto-Wake-up feature allows the sufficient length, and be followed by a sufficient controller to wake-up due to activity on the RX/DT line. interval, to allow enough time for the selected oscillator This feature is available only in Asynchronous mode. to start and provide proper initialization of the EUSART. The Auto-Wake-up feature is enabled by setting the WUE Bit WUE bit of the BAUDCON register. Once set, the normal The wake-up event causes a receive interrupt by receive sequence on RX/DT is disabled, and the setting the RCIF bit. The WUE bit is cleared by EUSART remains in an Idle state, monitoring for a hardware by a rising edge on RX/DT. The interrupt wake-up event independent of the CPU mode. A condition is then cleared by software by reading the wake-up event consists of a high-to-low transition on the RCREG register and discarding its contents. RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process The EUSART module generates an RCIF interrupt before setting the WUE bit. If a receive operation is not coincident with the wake-up event. The interrupt is occurring, the WUE bit may then be set just prior to generated synchronously to the Q clocks in normal CPU entering the Sleep mode. operating modes (Figure18-7), and asynchronously if the device is in Sleep mode (Figure18-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.  2010-2015 Microchip Technology Inc. DS40001303H-page 239

PIC18F2XK20/4XK20 FIGURE 18-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 18-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RX/DT Line Note 1 RCIF Cleared due to User Read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. DS40001303H-page 240  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 18.3.4 BREAK CHARACTER SEQUENCE When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. The EUSART module has the capability of sending the special Break character sequences that are required by 18.3.5 RECEIVING A BREAK CHARACTER the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. The Enhanced EUSART module can receive a Break character in two ways. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character trans- The first method to detect a Break character uses the mission is then initiated by a write to the TXREG. The FERR bit of the RCSTA register and the Received data value of data written to TXREG will be ignored and all as indicated by RCREG. The Baud Rate Generator is ‘0’s will be transmitted. assumed to have been initialized to the expected baud rate. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user A Break character has been received when; to preload the transmit FIFO with the next transmit byte • RCIF bit is set following the Break character (typically, the Sync • FERR bit is set character in the LIN specification). • RCREG = 00h The TRMT bit of the TXSTA register indicates when the The second method uses the Auto-Wake-up feature transmit operation is active or Idle, just as it does during described in Section18.3.3 “Auto-Wake-up on normal transmission. See Figure18-9 for the timing of Break”. By enabling this feature, the EUSART will the Break character sequence. sample the next two transitions on RX/DT, cause an 18.3.4.1 Break and Sync Transmit Sequence RCIF interrupt, and receive the next data byte followed by another interrupt. The following sequence will start a message frame header made up of a Break, followed by an auto-baud Note that following a Break character, the user will Sync byte. This sequence is typical of a LIN bus typically want to enable the Auto-Baud Detect feature. master. For both methods, the user can set the ABDEN bit of the BAUDCON register before placing the EUSART in 1. Configure the EUSART for the desired mode. Sleep mode. 2. Set the TXEN and SENDB bits to enable the Break sequence. 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. FIGURE 18-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit)  2010-2015 Microchip Technology Inc. DS40001303H-page 241

PIC18F2XK20/4XK20 18.4 EUSART Synchronous Mode 18.4.1.2 Clock Polarity Synchronous serial communications are typically used A clock polarity option is provided for Microwire in systems with a single master and one or more compatibility. Clock polarity is selected with the CKTXP slaves. The master device contains the necessary bit of the BAUDCON register. Setting the CKTXP bit circuitry for baud rate generation and supplies the clock sets the clock Idle state as high. When the CKTXP bit for all devices in the system. Slave devices can take is set, the data changes on the falling edge of each advantage of the master clock by eliminating the clock and is sampled on the rising edge of each clock. internal clock generation circuitry. Clearing the CKTXP bit sets the Idle state as low. When the CKTXP bit is cleared, the data changes on the There are two signal lines in Synchronous mode: a rising edge of each clock and is sampled on the falling bidirectional data line and a clock line. Slaves use the edge of each clock. external clock supplied by the master to shift the serial data into and out of their respective receive and 18.4.1.3 Synchronous Master Transmission transmit shift registers. Since the data line is Data is transferred out of the device on the RX/DT pin. bidirectional, synchronous operation is half-duplex The RX/DT and TX/CK pin output drivers are automat- only. Half-duplex refers to the fact that master and ically enabled when the EUSART is configured for slave devices can receive and transmit data but not synchronous master transmit operation. both simultaneously. The EUSART can operate as either a master or slave device. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a Start and Stop bits are not used in synchronous previous character the new character data is held in the transmissions. TXREG until the last bit of the previous character has 18.4.1 SYNCHRONOUS MASTER MODE been transmitted. If this is the first character, or the pre- vious character has been completely flushed from the The following bits are used to configure the EUSART TSR, the data in the TXREG is immediately transferred for Synchronous Master operation: to the TSR. The transmission of the character com- • SYNC = 1 mences immediately following the transfer of the data • CSRC = 1 to the TSR from the TXREG. • SREN = 0 (for transmit); SREN = 1 (for receive) Each data bit changes on the leading edge of the • CREN = 0 (for transmit); CREN = 1 (for receive) master clock and remains valid until the subsequent leading clock edge. • SPEN = 1 Setting the SYNC bit of the TXSTA register configures Note: The TSR register is not mapped in data the device for synchronous operation. Setting the CSRC memory, so it is not available to the user. bit of the TXSTA register configures the device as a 18.4.1.4 Data Polarity master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, The polarity of the transmit and receive data can be otherwise the device will be configured to receive. Setting controlled with the DTRXP bit of the BAUDCON regis- the SPEN bit of the RCSTA register enables the ter. The default state of this bit is ‘0’ which selects high EUSART. If the RX/DT or TX/CK pins are shared with an true transmit and receive data. Setting the DTRXP bit analog peripheral the analog I/O functions must be to ‘1’ will invert the data resulting in low true transmit disabled by clearing the corresponding ANSEL bits. and receive data. The TRIS bits corresponding to the RX/DT and TX/CK pins should be set. 18.4.1.1 Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. DS40001303H-page 242  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 18.4.1.5 Synchronous Master Transmission 4. Disable Receive mode by clearing bits SREN Set-up: and CREN. 5. Enable Transmit mode by setting the TXEN bit. 1. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the 6. If 9-bit transmission is desired, set the TX9 bit. desired baud rate (see Section18.3 “EUSART 7. If interrupts are desired, set the TXIE, GIE and Baud Rate Generator (BRG)”). PEIE interrupt enable bits. 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. 8. If 9-bit transmission is selected, the ninth bit 3. Enable the synchronous master serial port by should be loaded in the TX9D bit. setting bits SYNC, SPEN and CSRC. Set the 9. Start transmission by loading data to the TXREG TRIS bits corresponding to the RX/DT and register. TX/CK I/O pins. FIGURE 18-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. FIGURE 18-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit  2010-2015 Microchip Technology Inc. DS40001303H-page 243

PIC18F2XK20/4XK20 TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 59 TXREG EUSART Transmit Register 58 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58 BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 58 SPBRGH EUSART Baud Rate Generator Register, High Byte 58 SPBRG EUSART Baud Rate Generator Register, Low Byte 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear. DS40001303H-page 244  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 18.4.1.6 Synchronous Master Reception 18.4.1.8 Receive Overrun Error Data is received at the RX/DT pin. The RX/DT pin The receive FIFO buffer can hold two characters. An output driver must be disabled by setting the overrun error will be generated if a third character, in its corresponding TRIS bits when the EUSART is entirety, is received before RCREG is read to access configured for synchronous master receive operation. the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will In Synchronous mode, reception is enabled by setting not be overwritten. The two characters in the FIFO either the Single Receive Enable bit (SREN of the buffer can be read, however, no additional characters RCSTA register) or the Continuous Receive Enable bit will be received until the error is cleared. The OERR bit (CREN of the RCSTA register). can only be cleared by clearing the overrun condition. When SREN is set and CREN is clear, only as many If the overrun error occurred when the SREN bit is set clock cycles are generated as there are data bits in a and CREN is clear then the error is cleared by reading single character. The SREN bit is automatically cleared RCREG. If the overrun occurred when the CREN bit is at the completion of one character. When CREN is set, set then the error condition is cleared by either clearing clocks are continuously generated until CREN is the CREN bit of the RCSTA register or by clearing the cleared. If CREN is cleared in the middle of a character SPEN bit which resets the EUSART. the CK clock stops immediately and the partial charac- ter is discarded. If SREN and CREN are both set, then 18.4.1.9 Receiving 9-bit Characters SREN is cleared at the completion of the first character The EUSART supports 9-bit character reception. When and CREN takes precedence. the RX9 bit of the RCSTA register is set the EUSART To initiate reception, set either SREN or CREN. Data is will shift 9-bits into the RSR for each character sampled at the RX/DT pin on the trailing edge of the received. The RX9D bit of the RCSTA register is the TX/CK clock pin and is shifted into the Receive Shift ninth, and Most Significant, data bit of the top unread Register (RSR). When a complete character is character in the receive FIFO. When reading 9-bit data received into the RSR, the RCIF bit is set and the from the receive FIFO buffer, the RX9D data bit must character is automatically transferred to the two be read before reading the eight Least Significant bits character receive FIFO. The Least Significant eight bits from the RCREG. of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are 18.4.1.10 Synchronous Master Reception un-read characters in the receive FIFO. Set-up: 18.4.1.7 Slave Clock 1. Initialize the SPBRGH, SPBRG register pair for the appropriate baud rate. Set or clear the Synchronous data transfers use a separate clock line, BRGH and BRG16 bits, as required, to achieve which is synchronous with the data. A device configured the desired baud rate. as a slave receives the clock on the TX/CK line. The 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. TX/CK pin output driver must be disabled by setting the 3. Enable the synchronous master serial port by associated TRIS bit when the device is configured for setting bits SYNC, SPEN and CSRC. Disable synchronous slave transmit or receive operation. Serial RX/DT and TX/CK output drivers by setting the data bits change on the leading edge to ensure they are corresponding TRIS bits. valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock 4. Ensure bits CREN and SREN are clear. cycles should be received as there are data bits. 5. If using interrupts, set the GIE and PEIE bits of the INTCON register and set RCIE. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 9. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART.  2010-2015 Microchip Technology Inc. DS40001303H-page 245

PIC18F2XK20/4XK20 FIGURE 18-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58 RCREG EUSART Receive Register 58 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58 BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 58 SPBRGH EUSART Baud Rate Generator Register, High Byte 58 SPBRG EUSART Baud Rate Generator Register, Low Byte 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: Reserved in 28-pin devices; always maintain these bits clear. DS40001303H-page 246  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 18.4.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the EUSART for Synchronous slave operation: 1. The first character will immediately transfer to the TSR register and transmit. • SYNC = 1 2. The second word will remain in TXREG register. • CSRC = 0 3. The TXIF bit will not be set. • SREN = 0 (for transmit); SREN = 1 (for receive) 4. After the first character has been shifted out of • CREN = 0 (for transmit); CREN = 1 (for receive) TSR, the TXREG register will transfer the second • SPEN = 1 character to the TSR and the TXIF bit will now be Setting the SYNC bit of the TXSTA register configures the set. device for synchronous operation. Clearing the CSRC bit 5. If the PEIE and TXIE bits are set, the interrupt of the TXSTA register configures the device as a slave. will wake the device from Sleep and execute the Clearing the SREN and CREN bits of the RCSTA register next instruction. If the GIE bit is also set, the ensures that the device is in the Transmit mode, program will call the Interrupt Service Routine. otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the 18.4.2.2 Synchronous Slave Transmission EUSART. If the RX/DT or TX/CK pins are shared with an Set-up: analog peripheral the analog I/O functions must be 1. Set the SYNC and SPEN bits and clear the disabled by clearing the corresponding ANSEL bits. CSRC bit. RX/DT and TX/CK pin output drivers must be disabled 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. by setting the corresponding TRIS bits. 3. Clear the CREN and SREN bits. 18.4.2.1 EUSART Synchronous Slave 4. If using interrupts, ensure that the GIE and PEIE Transmit bits of the INTCON register are set and set the TXIE bit. The operation of the Synchronous Master and Slave 5. If 9-bit transmission is desired, set the TX9 bit. modes are identical (see Section18.4.1.3 “Synchronous Master Transmission”), except in the 6. Enable transmission by setting the TXEN bit. case of the Sleep mode. 7. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 8. Start transmission by writing the Least Significant 8 bits to the TXREG register. TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 59 TXREG EUSART Transmit Register 58 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58 BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 58 SPBRGH EUSART Baud Rate Generator Register, High Byte 58 SPBRG EUSART Baud Rate Generator Register, Low Byte 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.  2010-2015 Microchip Technology Inc. DS40001303H-page 247

PIC18F2XK20/4XK20 18.4.2.3 EUSART Synchronous Slave 18.4.2.4 Synchronous Slave Reception Reception Set-up: The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the modes is identical (Section18.4.1.6 “Synchronous CSRC bit. Master Reception”), with the following exceptions: 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. • Sleep 3. If using interrupts, ensure that the GIE and PEIE • CREN bit is always set, therefore the receiver is bits of the INTCON register are set and set the never Idle RCIE bit. • SREN bit, which is a “don't care” in Slave mode 4. If 9-bit reception is desired, set the RX9 bit. 5. Set the CREN bit to enable reception. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the 6. The RCIF bit will be set when reception is word is received, the RSR register will transfer the data complete. An interrupt will be generated if the to the RCREG register. If the RCIE enable bit is set, the RCIE bit was set. interrupt generated will wake the device from Sleep 7. If 9-bit mode is enabled, retrieve the Most and execute the next instruction. If the GIE bit is also Significant bit from the RX9D bit of the RCSTA set, the program will branch to the interrupt vector. register. 8. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 58 RCREG EUSART Receive Register 58 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58 BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 58 SPBRGH EUSART Baud Rate Generator Register, High Byte 58 SPBRG EUSART Baud Rate Generator Register, Low Byte 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: Reserved in 28-pin devices; always maintain these bits clear. DS40001303H-page 248  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 19.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. Figure19-1 shows the block diagram of the ADC. FIGURE 19-1: ADC BLOCK DIAGRAM VCFG1 = 0 AVSS VREF- VCFG1 = 1 AVDD VCFG0 = 0 VREF+ VCFG0 = 1 AN0 0000 AN1 0001 AN2 0010 AN3 0011 AN4 0100 AN5 0101 AN6 0110 AN7 0111 ADC AN8 1000 GO/DONE 10 AN9 1001 AN10 1010 0 = Left Justify ADFM AN11 1011 1 = Right Justify AN12 1100 ADON 10 Unused 1101 VSS ADRESH ADRESL Unused 1110 FVR 1111 CHS<3:0>  2010-2015 Microchip Technology Inc. DS40001303H-page 249

PIC18F2XK20/4XK20 19.1 ADC Configuration 19.1.4 SELECTING AND CONFIGURING ACQUISITION TIME When configuring and using the ADC the following functions must be considered: The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE • Port configuration bit is set. • Channel selection Acquisition time is set with the ACQT<2:0> bits of the • ADC voltage reference selection ADCON2 register. Acquisition delays cover a range of • ADC conversion clock source 2 to 20TAD. When the GO/DONE bit is set, the A/D • Interrupt control module continues to sample the input for the selected • Results formatting acquisition time, then automatically begins a conver- sion. Since the acquisition time is programmed, there is 19.1.1 PORT CONFIGURATION no need to wait for an acquisition time between select- ing a channel and setting the GO/DONE bit. The ANSEL, ANSELH, TRISA, TRISB and TRISE reg- isters all configure the A/D port pins. Any port pin Manual acquisition is selected when needed as an analog input should have its correspond- ACQT<2:0>=000. When the GO/DONE bit is set, ing ANSx bit set to disable the digital input buffer and sampling is stopped and a conversion begins. The user TRISx bit set to disable the digital output driver. If the is responsible for ensuring the required acquisition time TRISx bit is cleared, the digital output level (VOH or has passed between selecting the desired input VOL) will be converted. channel and setting the GO/DONE bit. This option is also the default Reset state of the ACQT<2:0> bits and The A/D operation is independent of the state of the is compatible with devices that do not offer ANSx bits and the TRIS bits. programmable acquisition times. Note1: When reading the PORT register, all pins In either case, when the conversion is completed, the with their corresponding ANSx bit set GO/DONE bit is cleared, the ADIF flag is set and the read as cleared (a low level). However, A/D begins sampling the currently selected channel analog conversion of pins configured as again. When an acquisition time is programmed, there digital inputs (ANSx bit cleared and is no indication of when the acquisition time ends and TRISx bit set) will be accurately the conversion begins. converted. 2: Analog levels on any pin with the 19.1.5 CONVERSION CLOCK corresponding ANSx bit cleared may The source of the conversion clock is software select- cause the digital input buffer to consume able via the ADCS bits of the ADCON2 register. There current out of the device’s specification are seven possible clock options: limits. • FOSC/2 3: The PBADEN bit in Configuration • FOSC/4 Register 3H configures PORTB pins to reset as analog or digital pins by • FOSC/8 controlling how the bits in ANSELH are • FOSC/16 reset. • FOSC/32 • FOSC/64 19.1.2 CHANNEL SELECTION • FRC (dedicated internal oscillator) The CHS bits of the ADCON0 register determine which The time to complete one bit conversion is defined as channel is connected to the sample and hold circuit. TAD. One full 10-bit conversion requires 11 TAD periods When changing channels, a delay is required before as shown in Figure19-3. starting the next conversion. Refer to Section19.2 For correct conversion, the appropriate TAD specification “ADC Operation” for more information. must be met. See A/D conversion requirements in Table 19.1.3 ADC VOLTAGE REFERENCE for more information. Table19-1 gives examples of appropriate ADC clock selections. The VCFG bits of the ADCON1 register provide independent control of the positive and negative Note: Unless using the FRC, any changes in the voltage references. The positive voltage reference can system clock frequency will change the be either VDD or an external voltage source. Likewise, ADC clock frequency, which may the negative voltage reference can be either VSS or an adversely affect the ADC result. external voltage source. DS40001303H-page 250  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 19.1.6 INTERRUPTS This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the The ADC module allows for the ability to generate an interrupt will wake-up the device. Upon waking from interrupt upon completion of an Analog-to-Digital Sleep, the next instruction following the SLEEP Conversion. The ADC interrupt flag is the ADIF bit in instruction is always executed. If the user is attempting the PIR1 register. The ADC interrupt enable is the ADIE to wake-up from Sleep and resume in-line code bit in the PIE1 register. The ADIF bit must be cleared by execution, the global interrupt must be disabled. If the software. global interrupt is enabled, execution will switch to the Note: The ADIF bit is set at the completion of Interrupt Service Routine. Please see Section19.1.6 every conversion, regardless of whether “Interrupts” for more information. or not the ADC interrupt is enabled. TABLE 19-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 64 MHz 16 MHz 4 MHz 1 MHz FOSC/2 000 31.25 ns(2) 125 ns(2) 500 ns(2) 2.0 s FOSC/4 100 62.5 ns(2) 250 ns(2) 1.0 s 4.0 s(3) FOSC/8 001 400 ns(2) 500 ns(2) 2.0 s 8.0 s(3) FOSC/16 101 250 ns(2) 1.0 s 4.0 s(3) 16.0 s(3) FOSC/32 010 500 ns(2) 2.0 s 8.0 s(3) 32.0 s(3) FOSC/64 110 1.0 s 4.0 s(3) 16.0 s(3) 64.0 s(3) FRC x11 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 1.7 s. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. 19.1.7 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON2 register controls the output format. Figure19-2 shows the two output formats. FIGURE 19-2: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result  2010-2015 Microchip Technology Inc. DS40001303H-page 251

PIC18F2XK20/4XK20 19.2 ADC Operation Figure19-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT<2:0> bits 19.2.1 STARTING A CONVERSION are cleared. A conversion is started after the following instruction to allow entry into SLEEP mode before the To enable the ADC module, the ADON bit of the conversion begins. ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will, depend- Figure19-4 shows the operation of the A/D converter ing on the ACQT bits of the ADCON2 register, either after the GO bit has been set and the ACQT<2:0> bits immediately start the Analog-to-Digital conversion or are set to ‘010’ which selects a 4 TAD acquisition time start an acquisition delay followed by the Analog-to- before the conversion starts. Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section19.2.9 “A/D Conver- sion Procedure”. FIGURE 19-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 2 TAD b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Discharge Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 19-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 2 TAD b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Discharge Time (Holding capacitor is disconnected from analog input) Set GO bit (Holding capacitor continues On the following cycle: acquiring input) ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS40001303H-page 252  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 19.2.2 COMPLETION OF A CONVERSION 19.2.7 ADC OPERATION DURING SLEEP When the conversion is complete, the ADC module will: The ADC module can operate during Sleep. This • Clear the GO/DONE bit requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the • Set the ADIF flag bit ADC waits one additional instruction before starting the • Update the ADRESH:ADRESL registers with new conversion. This allows the SLEEP instruction to be conversion result executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device 19.2.3 DISCHARGE will wake-up from Sleep when the conversion The discharge phase is used to initialize the value of completes. If the ADC interrupt is disabled, the ADC the capacitor array. The array is discharged after every module is turned off after the conversion completes, sample. This feature helps to optimize the unity-gain although the ADON bit remains set. amplifier, as the circuit always needs to charge the When the ADC clock source is something other than capacitor array, rather than charge/discharge based on FRC, a SLEEP instruction causes the present conver- previous measure values. sion to be aborted and the ADC module is turned off, although the ADON bit remains set. 19.2.4 TERMINATING A CONVERSION If a conversion must be terminated before completion, 19.2.8 SPECIAL EVENT TRIGGER the GO/DONE bit can be cleared by software. The The CCP2 Special Event Trigger allows periodic ADC ADRESH:ADRESL registers will not be updated with measurements without software intervention. When the partially complete Analog-to-Digital conversion this trigger occurs, the GO/DONE bit is set by hardware sample. Instead, the ADRESH:ADRESL register pair and the Timer1 or Timer3 counter resets to zero. will retain the value of the previous conversion. Using the Special Event Trigger does not assure proper Note: A device Reset forces all registers to their ADC timing. It is the user’s responsibility to ensure that Reset state. Thus, the ADC module is the ADC timing requirements are met. turned off and any pending conversion is See Section11.3.4 “Special Event Trigger” for more terminated. information. 19.2.5 DELAY BETWEEN CONVERSIONS After the A/D conversion is completed or aborted, a 2TAD wait is required before the next acquisition can be started. After this wait, the currently selected channel is reconnected to the charge holding capacitor commencing the next acquisition. 19.2.6 ADC OPERATION IN POWER- MANAGED MODES The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and ADCS<2:0> bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started. Once started, the device should continue to be clocked by the same clock source until the conversion has been completed. If desired, the device may be placed into the corresponding Idle mode during the conversion. If the device clock frequency is less than 1MHz, the A/D FRC clock source should be selected.  2010-2015 Microchip Technology Inc. DS40001303H-page 253

PIC18F2XK20/4XK20 19.2.9 A/D CONVERSION PROCEDURE EXAMPLE 19-1: A/D CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss as reference, Frc clock and AN0 input. 1. Configure Port: ; • Disable pin output driver (See TRIS register) ;Conversion start & polling for completion • Configure pin as analog ; are included. ; 2. Configure the ADC module: MOVLW B’10101111’ ;right justify, Frc, • Select ADC conversion clock MOVWF ADCON2 ; & 12 TAD ACQ time • Configure voltage reference MOVLW B’00000000’ ;ADC ref = Vdd,Vss MOVWF ADCON1 ; • Select ADC input channel BSF TRISA,0 ;Set RA0 to input • Select result format BSF ANSEL,0 ;Set RA0 to analog • Select acquisition delay MOVLW B’00000001’ ;AN0, ADC on • Turn on ADC module MOVWF ADCON0 ; BSF ADCON0,GO ;Start conversion 3. Configure ADC interrupt (optional): ADCPoll: • Clear ADC interrupt flag BTFSC ADCON0,GO ;Is conversion done? • Enable ADC interrupt BRA ADCPoll ;No, test again ; Result is complete - store 2 MSbits in • Enable peripheral interrupt ; RESULTHI and 8 LSbits in RESULTLO • Enable global interrupt(1) MOVFF ADRESH,RESULTHI 4. Wait the required acquisition time(2). MOVFF ADRESL,RESULTLO 5. Start conversion by setting the GO/DONE bit. 6. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Software delay required if ACQT bits are set to zero delay. See Section19.3 “A/D Acquisition Requirements”. DS40001303H-page 254  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 19.2.10 ADC REGISTER DEFINITIONS The following registers are used to control the opera- tion of the ADC. Note: Analog pin control is performed by the ANSEL and ANSELH registers. For ANSEL and ANSELH registers, see Register10-2 and Register10-3, respectively. REGISTER 19-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = AN0 0001 = AN1 0010 = AN2 0011 = AN3 0100 = AN4 0101 = AN5(1) 0110 = AN6(1) 0111 = AN7(1) 1000 = AN8 1001 = AN9 1010 = AN10 1011 = AN11 1100 = AN12 1101 = Reserved 1110 = Reserved 1111 = FVR (1.2 Volt Fixed Voltage Reference)(2) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: These channels are not implemented on PIC18F2XK20 devices. 2: Allow greater than 15s acquisition time when measuring the Fixed Voltage Reference.  2010-2015 Microchip Technology Inc. DS40001303H-page 255

PIC18F2XK20/4XK20 REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — — VCFG1 VCFG0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Negative Voltage Reference select bit 1 = Negative voltage reference supplied externally through VREF- pin. 0 = Negative voltage reference supplied internally by VSS. bit 4 VCFG0: Positive Voltage Reference select bit 1 = Positive voltage reference supplied externally through VREF+ pin. 0 = Positive voltage reference supplied internally by VDD. bit 3-0 Unimplemented: Read as ‘0’ DS40001303H-page 256  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 19-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition time select bits. Acquisition time is the duration that the A/D charge hold- ing capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until conver- sions begins. 000 = 0(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) Note 1: When the A/D clock source is selected as FRC then the start of conversion is delayed by one instruction cycle after the GO/DONE bit is set to allow the SLEEP instruction to be executed.  2010-2015 Microchip Technology Inc. DS40001303H-page 257

PIC18F2XK20/4XK20 REGISTER 19-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 19-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES1 ADRES0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 19-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — — — — ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 19-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result DS40001303H-page 258  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 19.3 A/D Acquisition Requirements an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition For the ADC to meet its specified accuracy, the charge time, Equation19-1 may be used. This equation holding capacitor (CHOLD) must be allowed to fully assumes that 1/2 LSb error is used (1024 steps for the charge to the input channel voltage level. The Analog ADC). The 1/2 LSb error is the maximum error allowed Input model is shown in Figure19-5. The source for the ADC to meet its specified resolution. impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure19-5. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), EQUATION 19-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 3.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 5µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– 2---0---4---7--- = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb –TC  ---------- VAPPLIED1–eRC = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– 2---0---4---7--- ;combining [1] and [2]   Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/2047) = –13.5pF1k+700+10k ln(0.0004885) = 1.20µs Therefore: TACQ = 5µs+1.20µs+50°C- 25°C0.05s/°C = 7.45µs Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification.  2010-2015 Microchip Technology Inc. DS40001303H-page 259

PIC18F2XK20/4XK20 FIGURE 19-5: ANALOG INPUT MODEL VDD Sampling Switch Rs ANx RIC  1k SS Rss VA CPIN I LEAKAGE(1) CHOLD = 13.5 pF 5 pF Discharge VSS/VREF- Switch 3.5V Legend: CPIN = Input Capacitance 3.0V I LEAKAGE = Lvaeraiokaugs eju cnucrtrieonnts at the pin due to DD 2.5V V RIC = Interconnect Resistance 2.0V SS = Sampling Switch 1.5V CHOLD = Sample/Hold Capacitance .1 1 10 100 Rss (k) Note 1: See Section26.0 “Electrical Specifications”. FIGURE 19-6: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh de 3FCh 1/2 LSB ideal o C 3FBh ut p ut Full-Scale O C 004h Transition D A 003h 002h 001h 000h Analog Input Voltage 1/2 LSB ideal VSS/VREF- Zero-Scale VDD/VREF+ Transition DS40001303H-page 260  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 19-2: REGISTERS ASSOCIATED WITH A/D OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59 ADRESH A/D Result Register, High Byte 58 ADRESL A/D Result Register, Low Byte 58 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 58 ADCON1 — — VCFG1 VCFG0 — — — — 58 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 58 ANSEL ANS7(1) ANS6(1) ANS5(1) ANS4 ANS3 ANS2 ANS1 ANS0 59 ANSELH — — — ANS12 ANS11 ANS10 ANS9 ANS8 59 PORTA RA7(2) RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 59 TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 59 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 59 TRISB PORTB Data Direction Control Register 59 LATB PORTB Data Latch Register (Read and Write to Data Latch) 59 PORTE(4) — — — — RE3(3) RE2 RE1 RE0 59 TRISE(4) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 59 LATE(4) — — — — — PORTE Data Latch Register 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These bits are unimplemented on PIC18F2XK20 devices; always maintain these bits clear. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’. 4: These registers are not implemented on PIC18F2XK20 devices.  2010-2015 Microchip Technology Inc. DS40001303H-page 261

PIC18F2XK20/4XK20 20.0 COMPARATOR MODULE FIGURE 20-1: SINGLE COMPARATOR Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and VIN+ + providing a digital indication of their relative magnitudes. Output The comparators are very useful mixed signal building VIN- – blocks because they provide analog functionality independent of the program execution. The analog comparator module includes the following features: • Independent comparator control VIN- • Programmable input selection VIN+ • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change Output • Wake-up from Sleep • Programmable Speed/Power optimization • PWM shutdown Note: The black areas of the output of the • Programmable and Fixed Voltage Reference comparator represents the uncertainty 20.1 Comparator Overview due to input offsets and response time. A single comparator is shown in Figure20-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. DS40001303H-page 262  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 20-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> 2 To D Q Data Bus Q1 C12IN0- 0 EN RD_CM1CON0 C12IN1- 1 MUX Set C1IF D Q C12IN2- 2 Q3*RD_CM1CON0 EN C12IN3- 3 CL To PWM Logic Reset C1ON(1) C1R C1OE C1VIN- - C1IN+ 0 C1 C1OUT MUX C1VIN+ + FVR 1 C1OUT pin(2) 0 C1SP C1POL MUX CVREF 1 C1VREF C1RSEL Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. 2: Output shown for reference only. See I/O port pin block diagram for more detail. 3: Q1 and Q3 are phases of the four-phase system clock (FOSC). 4: Q1 is held high during Sleep mode. FIGURE 20-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM To D Q Data Bus Q1 EN RD_CM2CON0 C2CH<1:0> Set C2IF 2 D Q Q3*RD_CM2CON0 C12IN0- 0 C2ON(1) ENCL To PWM Logic C2OE NRESET C12IN1- 1 MUX C2VIN- C12IN2- 2 C2VIN+ C2 C2OUT C2OUT pin(2) C12IN3- 3 C2SP C2POL C2R C2IN+ 0 MUX FVR 1 0 MUX CVREF 1 C2VREF Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate. C2RSEL 2: Output shown for reference only. See I/O port pin block diagram for more detail. 3: Q1 and Q3 are phases of the four-phase system clock (FOSC). 4: Q1 is held high during Sleep mode.  2010-2015 Microchip Technology Inc. DS40001303H-page 263

PIC18F2XK20/4XK20 20.2 Comparator Control Each comparator has a separate control and Configu- Note1: The CxOE bit overrides the PORT data ration register: CM1CON0 for Comparator C1 and latch. Setting the CxON has no impact on CM2CON0 for Comparator C2. In addition, Comparator the port override. C2 has a second control register, CM2CON1, for con- 2: The internal output of the comparator is trolling the interaction with Timer1 and simultaneous latched with each instruction cycle. reading of both comparator outputs. Unless otherwise specified, external The CM1CON0 and CM2CON0 registers (see Regis- outputs are not latched. ters 20-1 and 20-2, respectively) contain the control and Status bits for the following: 20.2.5 COMPARATOR OUTPUT POLARITY • Enable Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The • Input selection polarity of the comparator output can be inverted by • Reference selection setting the CxPOL bit of the CMxCON0 register. • Output selection Clearing the CxPOL bit results in a non-inverted output. • Output polarity Table20-1 shows the output state versus input • Speed selection conditions, including polarity control. 20.2.1 COMPARATOR ENABLE TABLE 20-1: COMPARATOR OUTPUT STATE VS. INPUT Setting the CxON bit of the CMxCON0 register enables CONDITIONS the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current Input Condition CxPOL CxOUT consumption. CxVIN- > CxVIN+ 0 0 20.2.2 COMPARATOR INPUT SELECTION CxVIN- < CxVIN+ 0 1 The CxCH<1:0> bits of the CMxCON0 register direct CxVIN- > CxVIN+ 1 1 one of four analog input pins to the comparator CxVIN- < CxVIN+ 1 0 inverting input. 20.2.6 COMPARATOR SPEED SELECTION Note: To use CxIN+ and C12INx- pins as analog inputs, the appropriate bits must be set in The trade-off between speed or power can be opti- the ANSEL register and the mized during program execution with the CxSP control corresponding TRIS bits must also be set bit. The default state for this bit is ‘1’ which selects the to disable the output drivers. normal speed mode. Device power consumption can be optimized at the cost of slower comparator propaga- 20.2.3 COMPARATOR REFERENCE tion delay by clearing the CxSP bit to ‘0’. SELECTION 20.3 Comparator Response Time Setting the CxR bit of the CMxCON0 register directs an internal voltage reference or an analog input pin to the The comparator output is indeterminate for a period of non-inverting input of the comparator. See time after the change of an input source or the selection Section21.0 “VOLTAGE REFERENCES” for more of a new reference voltage. This period is referred to as information on the Internal Voltage Reference module. the response time. The response time of the comparator differs from the settling time of the voltage 20.2.4 COMPARATOR OUTPUT reference. Therefore, both of these times must be SELECTION considered when determining the total response time The output of the comparator can be monitored by to a comparator input change. See the Comparator and reading either the CxOUT bit of the CMxCON0 register Voltage Reference Specifications in Section26.0 or the MCxOUT bit of the CM2CON1 register. In order “Electrical Specifications” for more details. to make the output available for an external connection, the following conditions must be true: • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set DS40001303H-page 264  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 20.4 Comparator Interrupt Operation 20.4.1 PRESETTING THE MISMATCH LATCHES The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. The comparator mismatch latches can be preset to the Changes are recognized by means of a mismatch desired state before the comparators are enabled. circuit which consists of two latches and an exclusive- When the comparator is off the CxPOL bit controls the or gate (see Figure20-2 and Figure20-3). One latch is CxOUT level. Set the CxPOL bit to the desired CxOUT updated with the comparator output level when the non-interrupt level while the CxON bit is cleared. Then, CMxCON0 register is read. This latch retains the value configure the desired CxPOL level in the same instruc- until the next read of the CMxCON0 register or the tion that the CxON bit is set. Since all register writes are occurrence of a Reset. The other latch of the mismatch performed as a Read-Modify-Write, the mismatch circuit is updated on every Q1 system clock. A latches will be cleared during the instruction Read mismatch condition will occur when a comparator phase and the actual configuration of the CxON and output change is clocked through the second latch on CxPOL bits will be occur in the final Write phase. the Q1 clock cycle. At this point the two mismatch latches have opposite output levels which is detected FIGURE 20-4: COMPARATOR by the exclusive-or gate and fed to the interrupt INTERRUPT TIMING W/O circuitry. The mismatch condition persists until either CMxCON0 READ the CMxCON0 register is read or the comparator output returns to the previous state. Q1 Q3 Note 1: A write operation to the CMxCON0 register will also clear the mismatch CxIN+ TRT condition because all writes include a read CxOUT operation at the beginning of the write Set CxIF (edge) cycle. CxIF 2: Comparator interrupts will operate reset by software correctly regardless of the state of CxOE. FIGURE 20-5: COMPARATOR The comparator interrupt is set by the mismatch edge and not the mismatch level. This means that the inter- INTERRUPT TIMING WITH rupt flag can be reset without the additional step of CMxCON0 READ reading or writing the CMxCON0 register to clear the mismatch registers. When the mismatch registers are Q1 cleared, an interrupt will occur upon the comparator’s Q3 return to the previous state, otherwise no interrupt will CxIN+ TRT be generated. CxOUT Software will need to maintain information about the Set CxIF (edge) status of the comparator output, as read from the CxIF CMxCON0 register, or CM2CON1 register, to determine cleared by CMxCON0 read reset by software the actual change that has occurred. See Figures20-4 and20-5. The CxIF bit of the PIR2 register is the comparator interrupt flag. This bit must be reset by software by Note1: If a change in the CMxCON0 register clearing it to ‘0’. Since it is also possible to write a ‘1’ to (CxOUT) should occur when a read oper- this register, an interrupt can be generated. ation is being executed (start of the Q2 cycle), then the CxIF interrupt flag of the In mid-range Compatibility mode the CxIE bit of the PIR2 register may not get set. PIE2 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. 2: When either comparator is first enabled, If any of these bits are cleared, the interrupt is not bias circuitry in the comparator module enabled, although the CxIF bit of the PIR2 register will may cause an invalid output from the still be set if an interrupt condition occurs. comparator until the bias circuitry is stable. Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts.  2010-2015 Microchip Technology Inc. DS40001303H-page 265

PIC18F2XK20/4XK20 20.5 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section26.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CxIE bit of the PIE2 register and the PEIE bit of the INTCON register must be set. The instruction following the SLEEP instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. 20.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their Off states. DS40001303H-page 266  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 20-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT = 0 when C1VIN+ > C1VIN- C1OUT = 1 when C1VIN+ < C1VIN- If C1POL = 0 (non-inverted polarity): C1OUT = 1 when C1VIN+ > C1VIN- C1OUT = 0 when C1VIN+ < C1VIN- bit 5 C1OE: Comparator C1 Output Enable bit 1 = C1OUT is present on the C1OUT pin(1) 0 = C1OUT is internal only bit 4 C1POL: Comparator C1 Output Polarity Select bit 1 = C1OUT logic is inverted 0 = C1OUT logic is not inverted bit 3 C1SP: Comparator C1 Speed/Power Select bit 1 = C1 operates in Normal Power, higher speed mode 0 = C1 operates in Low-Power, Low-Speed mode bit 2 C1R: Comparator C1 Reference Select bit (non-inverting input) 1 = C1VIN+ connects to C1VREF output 0 = C1VIN+ connects to C1IN+ pin bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit 00 = C12IN0- pin of C1 connects to C1VIN- 01 = C12IN1- pin of C1 connects to C1VIN- 10 = C12IN2- pin of C1 connects to C1VIN- 11 = C12IN3- pin of C1 connects to C1VIN- Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port TRIS bit = 0.  2010-2015 Microchip Technology Inc. DS40001303H-page 267

PIC18F2XK20/4XK20 REGISTER 20-2: CM2CON0: COMPARATOR 2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT = 0 when C2VIN+ > C2VIN- C2OUT = 1 when C2VIN+ < C2VIN- If C2POL = 0 (non-inverted polarity): C2OUT = 1 when C2VIN+ > C2VIN- C2OUT = 0 when C2VIN+ < C2VIN- bit 5 C2OE: Comparator C2 Output Enable bit 1 = C2OUT is present on C2OUT pin(1) 0 = C2OUT is internal only bit 4 C2POL: Comparator C2 Output Polarity Select bit 1 = C2OUT logic is inverted 0 = C2OUT logic is not inverted bit 3 C2SP: Comparator C2 Speed/Power Select bit 1 = C2 operates in Normal Power, higher speed mode 0 = C2 operates in Low-Power, Low-Speed mode bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input) 1 = C2VIN+ connects to C2VREF 0 = C2VIN+ connects to C2IN+ pin bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits 00 = C12IN0- pin of C2 connects to C2VIN- 01 = C12IN1- pin of C2 connects to C2VIN- 10 = C12IN2- pin of C2 connects to C2VIN- 11 = C12IN3- pin of C2 connects to C2VIN- Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port TRIS bit = 0. DS40001303H-page 268  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 20.7 Analog Input Connection Considerations Note1: When reading a PORT register, all pins configured as analog inputs will read as a A simplified circuit for an analog input is shown in ‘0’. Pins configured as digital inputs will Figure20-6. Since the analog input pins share their convert as an analog input, according to connection with a digital input, they have reverse the input specification. biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. 2: Analog levels on any pin defined as a If the input voltage deviates from this range by more digital input, may cause the input buffer to than 0.6V in either direction, one of the diodes is consume more current than is specified. forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. FIGURE 20-6: ANALOG INPUT MODEL VDD Rs < 10K RIC AIN VA CPIN ILEAKAGE(1) 5 pF Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage Note1: See Section26.0 “Electrical Specifications”.  2010-2015 Microchip Technology Inc. DS40001303H-page 269

PIC18F2XK20/4XK20 20.8 Additional Comparator Features 20.8.2 INTERNAL REFERENCE SELECTION There are two additional comparator features: There are two internal voltage references available to • Simultaneous read of comparator outputs the non-inverting input of each comparator. One of • Internal reference selection these is the 1.2V Fixed Voltage Reference (FVR) and the other is the variable Comparator Voltage Reference 20.8.1 SIMULTANEOUS COMPARATOR (CVREF). The CxRSEL bit of the CM2CON register OUTPUT READ determines which of these references is routed to the The MC1OUT and MC2OUT bits of the CM2CON1 Comparator Voltage reference output (CXVREF). register are mirror copies of both comparator outputs. Further routing to the comparator is accomplished by The ability to read both outputs simultaneously from a the CxR bit of the CMxCON0 register. See single register eliminates the timing skew of reading Section21.1 “Comparator Voltage Reference” and separate registers. Figure20-2 and Figure20-3 for more detail. Note1: Obtaining the status of C1OUT or C2OUT by reading CM2CON1 does not affect the comparator interrupt mismatch registers. REGISTER 20-3: CM2CON1: COMPARATOR 2 CONTROL REGISTER 1 R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 MC1OUT MC2OUT C1RSEL C2RSEL — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 C1RSEL: Comparator C1 Reference Select bit 1 = CVREF routed to C1VREF input 0 = FVR (1.2 Volt Fixed Voltage Reference) routed to C1VREF input bit 4 C2RSEL: Comparator C2 Reference Select bit 1 = CVREF routed to C2VREF input 0 = FVR (1.2 Volt Fixed Voltage Reference) routed to C2VREF input bit 3-0 Unimplemented: Read as ‘0’ DS40001303H-page 270  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 20-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 59 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 59 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — — — 60 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 58 CVRCON2 FVREN FVRST — — — — — — 58 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59 PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 59 LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 59 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’.  2010-2015 Microchip Technology Inc. DS40001303H-page 271

PIC18F2XK20/4XK20 21.0 VOLTAGE REFERENCES 21.1.3 OUTPUT CLAMPED TO VSS There are two independent voltage references The CVREF output voltage can be set to Vss with no power consumption by configuring CVRCON as available: follows: • Programmable Comparator Voltage Reference • CVREN=0 • 1.2V Fixed Voltage Reference • CVRR=1 21.1 Comparator Voltage Reference • CVR<3:0>=0000 This allows the comparator to detect a zero-crossing The Comparator Voltage Reference module provides while not consuming additional CVREF module current. an internally generated voltage reference for the com- parators. The following features are available: 21.1.4 OUTPUT RATIOMETRIC TO VDD • Independent from Comparator operation The comparator voltage reference is VDD derived and • Two 16-level voltage ranges therefore, the CVREF output changes with fluctuations in • Output clamped to VSS VDD. The tested absolute accuracy of the Comparator • Ratiometric with VDD Voltage Reference can be found in Section26.0 “Electrical Specifications”. • 1.2 Fixed Reference Voltage (FVR) The CVRCON register (Register21-1) controls the 21.1.5 VOLTAGE REFERENCE OUTPUT Voltage Reference module shown in Figure21-1. The CVREF voltage reference can be output to the 21.1.1 INDEPENDENT OPERATION device CVREF pin by setting the CVROE bit of the CVRCON register to ‘1’. Selecting the reference volt- The comparator voltage reference is independent of age for output on the CVREF pin automatically overrides the comparator configuration. Setting the CVREN bit of the digital output buffer and digital input threshold the CVRCON register will enable the voltage reference detector functions of that pin. Reading the CVREF pin by allowing current to flow in the CVREF voltage divider. when it has been configured for reference voltage out- When both the CVREN bit is cleared, current flow in the put will always return a ‘0’. CVREF voltage divider is disabled minimizing the power Due to the limited current drive capability, a buffer must drain of the voltage reference peripheral. be used on the voltage reference output for external 21.1.2 OUTPUT VOLTAGE SELECTION connections to CVREF. Figure21-2 shows an example buffering technique. The CVREF voltage reference has two ranges with 16 voltage levels in each range. Range selection is 21.1.6 OPERATION DURING SLEEP controlled by the CVRR bit of the CVRCON register. When the device wakes up from Sleep through an The 16 levels are set with the CVR<3:0> bits of the interrupt or a Watchdog Timer time-out, the contents of CVRCON register. the CVRCON register are not affected. To minimize The CVREF output voltage is determined by the following current consumption in Sleep mode, the voltage equations: reference should be disabled. EQUATION 21-1: CVREF OUTPUT VOLTAGE 21.1.7 EFFECTS OF A RESET CVRR = 1 (low range): A device Reset affects the following: CVREF = (CVRSRC/24) X CVR<3:0> + VREF- • Comparator voltage reference is disabled • Fixed Voltage Reference is disabled CVRR = 0 (high range): • CVREF is removed from the CVREF pin CVREF = (CVRSRC/32) X (8 + CVR<3:0>) + VREF- • The high-voltage range is selected CVRSRC = VDD or [(VREF+) - (VREF-)] • The CVR<3:0> range select bits are cleared Note: VREF- is 0 when CVRSS = 0 The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure21-1. DS40001303H-page 272  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 21.2 FVR Reference Module 21.2.1 FVR STABILIZATION PERIOD The FVR reference is a stable Fixed Voltage When the Fixed Voltage Reference module is enabled, it Reference, independent of VDD, with a nominal output will require some time for the reference and its amplifier voltage of 1.2V. This reference can be enabled by circuits to stabilize. The user program must include a setting the FVREN bit of the CVRCON2 register to ‘1’. small delay routine to allow the module to settle. The The FVR defaults to on when any one or more of the FVRST stable bit of the CVRCON2 register also indicates HFINTOSC, HLVD, BOR or ADC input channel that the FVR reference has been operating long enough selection functions are enabled. The FVR voltage to be stable. See Section26.0 “Electrical reference can be routed to the comparators or an ADC Specifications” for the minimum delay requirement. input channel. FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ VDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U 16 Steps M 1 CVREF o- 6-t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 FVR 1.2 Volt Fixed FVREN Reference FVRST From HVLD, BOR circuits EN and ADC channel selection (CHS<3:0> = 1111)  2010-2015 Microchip Technology Inc. DS40001303H-page 273

PIC18F2XK20/4XK20 FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F2XK20/4XK20 CVREF R(1) Module + Voltage CVREF – Buffered CVREF Output Reference Output Impedance Note 1: R is dependent upon the voltage reference Configuration bits, CVR<3:0> and CVRR. REGISTER 21-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the CVREF pin 0 = CVREF voltage is disconnected from the CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = VDD – VSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0  (CVR<3:0>)  15) When CVRR = 1: CVREF = ((CVR<3:0>)/24)  (CVRSRC) + VREF- When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32)  (CVRSRC) + VREF- Note 1: CVROE overrides the TRISA<2> bit setting. DS40001303H-page 274  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 21-2: CVRCON2: COMPARATOR VOLTAGE REFERENCE CONTROL 2 REGISTER R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 FVREN FVRST — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = FVR circuit powered on 0 = FVR circuit not enabled by FVREN. Other peripherals may enable FVR. bit 6 FVRST: Fixed Voltage Stable Status bit 1 = FVR is stable and can be used. 0 = FVR is not stable and should not be used. bit 5-0 Unimplemented: Read as ‘0’. TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 59 CVRCON2 FVREN FVRST — — — — — — 58 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 59 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 59 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — — — 60 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 59 Legend: Shaded cells are not used with the comparator voltage reference. Note 1: PORTA pins are enabled based on oscillator configuration.  2010-2015 Microchip Technology Inc. DS40001303H-page 275

PIC18F2XK20/4XK20 22.0 HIGH/LOW-VOLTAGE The block diagram for the HLVD module is shown in DETECT (HLVD) Figure22-1. The module is enabled by setting the HLVDEN bit. PIC18F2XK20/4XK20 devices have a High/Low-Voltage Each time that the HLVD module is enabled, the cir- Detect module (HLVD). This is a programmable circuit cuitry requires some time to stabilize. The IRVST bit is that allows the user to specify both a device voltage trip a read-only bit and is used to indicate when the circuit point and the direction of change from that point. If the is stable. The module can only generate an interrupt device experiences an excursion past the trip point in after the circuit is stable and IRVST is set. that direction, an interrupt flag is set. If the interrupt is The VDIRMAG bit determines the overall operation of enabled, the program execution will branch to the inter- the module. When VDIRMAG is cleared, the module rupt vector address and the software can then respond to the interrupt. monitors for drops in VDD below a predetermined set point. When the bit is set, the module monitors for rises The High/Low-Voltage Detect Control register in VDD above the set point. (Register22-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned off” by the user under software control, which minimizes the current consumption for the device. REGISTER 22-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL<3:0>: Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting Note 1: See Table26-4 for specifications. DS40001303H-page 276  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 22.1 Operation The trip point voltage is software programmable to any one of 16 values. The trip point is selected by When the HLVD module is enabled, a comparator uses programming the HLVDL<3:0> bits of the HLVDCON an internally generated reference voltage as the set register. point. The set point is compared with the trip point, The HLVD module has an additional feature that allows where each node in the resistor divider represents a the user to supply the trip voltage to the module from an trip point voltage. The “trip point” voltage is the voltage external source. This mode is enabled when bits level at which the device detects a high or low-voltage HLVDL<3:0> are set to ‘1111’. In this state, the event, depending on the configuration of the module. comparator input is multiplexed from the external input When the supply voltage is equal to the trip point, the pin, HLVDIN. This gives users flexibility because it voltage tapped off of the resistor array is equal to the allows them to configure the High/Low-Voltage Detect internal reference voltage generated by the voltage interrupt to occur at any voltage in the valid operating reference module. The comparator then generates an range. interrupt signal by setting the HLVDIF bit. FIGURE 22-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL<3:0> HLVDCON Register HLVDIN HLVDEN VDIRMAG HLVDIN X Set U M HLVDIF 1 o- 6-t 1 HLVDEN Internal Voltage BOREN Reference  2010-2015 Microchip Technology Inc. DS40001303H-page 277

PIC18F2XK20/4XK20 22.2 HLVD Setup Depending on the application, the HLVD module does not need to be operating constantly. To decrease the The following steps are needed to set up the HLVD current requirements, the HLVD circuitry may only module: need to be enabled for short periods where the voltage 1. Write the value to the HLVDL<3:0> bits that is checked. After doing the check, the HLVD module selects the desired HLVD trip point. may be disabled. 2. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). 22.4 HLVD Start-up Time 3. Enable the HLVD module by setting the The internal reference voltage of the HLVD module, HLVDEN bit. specified in electrical specification parameter D420, 4. Clear the HLVD interrupt flag bit of the PIR2 may be used by other internal circuitry, such as the register, which may have been set from a Programmable Brown-out Reset. If the HLVD or other previous interrupt. circuits using the voltage reference are disabled to 5. Enable the HLVD interrupt if interrupts are lower the device’s current consumption, the reference desired by setting the HLVDIE bit of the PIE2 voltage circuit will require time to become stable before register, and the GIE and PEIE bits of the a low or high-voltage condition can be reliably INTCON register. An interrupt will not be gener- detected. This start-up time, TIRVST, is an interval that ated until the IRVST bit is set. is independent of device clock speed. It is specified in electrical specification parameter 36. 22.3 Current Consumption The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For When the module is enabled, the HLVD comparator this reason, brief excursions beyond the set point may and voltage divider are enabled and will consume static not be detected during this interval. Refer to Figure22-2 current. The total current consumption, when enabled, or Figure22-3. is specified in electrical specification parameter D024B. FIGURE 22-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VHLVD HLVDIF Enable HLVD TIVRST IRVST HLVDIF cleared by software Internal Reference is stable CASE 2: VDD VHLVD HLVDIF Enable HLVD IRVST TIVRST Internal Reference is stable HLVDIF cleared by software HLVDIF cleared by software, HLVDIF remains set since HLVD condition still exists DS40001303H-page 278  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 22-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD IRVST TIVRST HLVDIF cleared by software Internal Reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD IRVST TIVRST Internal Reference is stable HLVDIF cleared by software HLVDIF cleared by software, HLVDIF remains set since HLVD condition still exists  2010-2015 Microchip Technology Inc. DS40001303H-page 279

PIC18F2XK20/4XK20 22.5 Applications FIGURE 22-4: TYPICAL LOW-VOLTAGE DETECT APPLICATION In many applications, the ability to detect a drop below, or rise above, a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach VA would indicate a high-voltage detect from, for example, VB 3.3V to 5V (the voltage on USB) and vice versa for a e g detach. This feature could save a design a few extra a t components and an attach signal (input pin). ol V For general battery applications, Figure22-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the HLVD logic generates an interrupt at time TA. The interrupt could cause the execution of an ISR, Time TA TB which would allow the application to perform “housekeeping tasks” and perform a controlled Legend: VA = HLVD trip point shutdown before the device voltage exits the valid VB = Minimum valid device operating range at TB. The HLVD, thus, would give the operating voltage application a time window, represented by the difference between TA and TB, to safely exit. TABLE 22-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 57 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 59 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 59 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. DS40001303H-page 280  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 23.0 SPECIAL FEATURES OF THE CPU PIC18F2XK20/4XK20 devices include several features intended to maximize reliability and minimize cost through elimination of external components. These are: • Oscillator Selection • Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Code Protection • ID Locations • In-Circuit Serial Programming™ The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section2.0 “Oscillator Module (With Fail-Safe Clock Monitor)”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F2XK20/4XK20 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. Two- Speed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits.  2010-2015 Microchip Technology Inc. DS40001303H-page 281

PIC18F2XK20/4XK20 23.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes. Programming the Configuration registers is done in a manner similar to programming the Flash memory. The WR bit in the EECON1 register starts a self-timed write to the Configuration register. In Normal Operation mode, a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and the data for the Configuration register write. Setting the WR bit starts a long write to the Configuration register. The Configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a ‘1’ or a ‘0’ into the cell. For additional details on Flash programming, refer to Section6.5 “Writing to Flash Program Memory”. TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs Default/ Unprogramme File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 d Value 300001h CON- IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111 FIG1H 300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111 300003h CON- — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111 FIG2H 300005h CON- MCLRE — — — HFOFST LPT1OS PBADEN CCP2MX 1--- 1011 FIG3H C 300006h CONFIG4L DEBUG XINST — — — LVP — STVREN 10-- -1-1 300008h CONFIG5L — — — — CP3(1) CP2(1) CP1 CP0 ---- 1111 300009h CON- CPD CPB — — — — — — 11-- ---- FIG5H 30000Ah CONFIG6L — — — — WRT3(1) WRT2(1) WRT1 WRT0 ---- 1111 30000Bh CON- WRTD WRTB WRTC — — — — — 111- ---- FIG6H 30000Ch CONFIG7L — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 ---- 1111 30000Dh CON- — EBTRB — — — — — — -1-- ---- FIG7H 3FFFFEh DEVID1(2) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 qqqq qqqq(2) 3FFFFFh DEVID2(2) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1100 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Implemented but not used in PIC18FX3K20 and PIC18FX4K20 devices; maintain this bit set. 2: See Register23-12 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. DS40001303H-page 282  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 FOSC<3:0>: Oscillator Selection bits 11xx = External RC oscillator, CLKOUT function on RA6 101x = External RC oscillator, CLKOUT function on RA6 1001 = Internal oscillator block, CLKOUT function on RA6, port function on RA7 1000 = Internal oscillator block, port function on RA6 and RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKOUT function on RA6 0011 = External RC oscillator, CLKOUT function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator  2010-2015 Microchip Technology Inc. DS40001303H-page 283

PIC18F2XK20/4XK20 REGISTER 23-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — BORV1(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1) 11 = VBOR set to 1.8V nominal 10 = VBOR set to 2.2V nominal 01 = VBOR set to 2.7V nominal 00 = VBOR set to 3.0V nominal bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits(2) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled Note 1: See Section 26.1 “DC Characteristics: Supply Voltage” for specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT is always enabled. SWDTEN bit has no effect 0 = WDT is controlled by SWDTEN bit of the WDTCON register DS40001303H-page 284  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 R EGISTER 23-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH R/P-1 U-0 U-0 U-0 R/P-1 R/P-0 R/P-1 R/P-1 MCLRE — — — HFOFST LPT1OSC PBADEN CCP2MX bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 HFOFST: HFINTOSC Fast Start-up 1 = HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize. 0 = The system clock is held off until the HFINTOSC is stable. bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation bit 1 PBADEN: PORTB A/D Enable bit (Affects ANSELH Reset state. ANSELH controls PORTB<4:0> pin configuration.) 1 = PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset bit 0 CCP2MX: CCP2 MUX bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 REGISTER 23-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW R/P-1 R/P-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG XINST — — — LVP(1) — STVREN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5-3 Unimplemented: Read as ‘0’ bit 2 LVP: Single-Supply ICSP Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Note 1: Can only be changed by a programmer in High-Voltage Programming mode.  2010-2015 Microchip Technology Inc. DS40001303H-page 285

PIC18F2XK20/4XK20 REGISTER 23-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2(1) CP1 CP0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 not code-protected 0 = Block 3 code-protected bit 2 CP2: Code Protection bit(1) 1 = Block 2 not code-protected 0 = Block 2 code-protected bit 1 CP1: Code Protection bit 1 = Block 1 not code-protected 0 = Block 1 code-protected bit 0 CP0: Code Protection bit 1 = Block 0 not code-protected 0 = Block 0 code-protected Note 1: Implemented, but not used in PIC18FX3K20 and PIC18FX4K20 devices. REGISTER 23-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot Block not code-protected 0 = Boot Block code-protected bit 5-0 Unimplemented: Read as ‘0’ DS40001303H-page 286  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 23-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3(1) WRT2(1) WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 not write-protected 0 = Block 3 write-protected bit 2 WRT2: Write Protection bit(1) 1 = Block 2 not write-protected 0 = Block 2 write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 not write-protected 0 = Block 1 write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 not write-protected 0 = Block 0 write-protected Note 1: Implemented, but not used in PIC18FX3K20 and PIC18FX4K20 devices. REGISTER 23-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot Block not write-protected 0 = Boot Block write-protected bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers not write-protected 0 = Configuration registers write-protected bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is read-only in Normal Execution mode; it can be written only in Program mode.  2010-2015 Microchip Technology Inc. DS40001303H-page 287

PIC18F2XK20/4XK20 REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 not protected from table reads executed in other blocks 0 = Block 3 protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit(1) 1 = Block 2 not protected from table reads executed in other blocks 0 = Block 2 protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 not protected from table reads executed in other blocks 0 = Block 1 protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 not protected from table reads executed in other blocks 0 = Block 0 protected from table reads executed in other blocks Note 1: Implemented, but not used in PIC18FX3K20 and PIC18FX4K20 devices. REGISTER 23-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot Block not protected from table reads executed in other blocks 0 = Boot Block protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ DS40001303H-page 288  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 REGISTER 23-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2XK20/4XK20 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-5 DEV<2:0>: Device ID bits 000 = PIC18F46K20 001 = PIC18F26K20 010 = PIC18F45K20 011 = PIC18F25K20 100 = PIC18F44K20 101 = PIC18F24K20 110 = PIC18F43K20 111 = PIC18F23K20 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. REGISTER 23-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2XK20/4XK20 R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-0 DEV<10:3>: Device ID bits These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. 0010 0000 = PIC18F2XK20/4XK20 devices Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified by using the entire DEV<10:0> bit sequence.  2010-2015 Microchip Technology Inc. DS40001303H-page 289

PIC18F2XK20/4XK20 23.2 Watchdog Timer (WDT) For PIC18F2XK20/4XK20 devices, the WDT is driven by the LFINTOSC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4ms and has the same stability as the LFINTOSC oscillator. The 4ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configu- ration Register 2H. Available periods range from 4ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: a SLEEP or CLRWDT instruction is executed, the IRCF bits of the OSCCON register are changed or a clock failure has occurred. Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits of the OSCCON register clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared. FIGURE 23-1: WDT BLOCK DIAGRAM SWDTEN Enable WDT WDTEN WDT Counter LFINTOSC Source 128 Wake-up from Power Managed Modes Change on IRCF bits Programmable Postscaler Reset WDT CLRWDT Reset 1:1 to 1:32,768 All Device Resets 4 WDTPS<3:0> Sleep DS40001303H-page 290  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 23.2.1 CONTROL REGISTER Register23-14 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable Configuration bit, but only if the Configuration bit has disabled the WDT. REGISTER 23-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note1: This bit has no effect if the Configuration bit, WDTEN, is enabled. TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page RCON IPEN SBOREN — RI TO PD POR BOR 55 WDTCON — — — — — — — SWDTEN 57 CONFIG2H WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN 284 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.  2010-2015 Microchip Technology Inc. DS40001303H-page 291

PIC18F2XK20/4XK20 23.3 Program Verification and Each of the blocks has three code protection bits Code Protection associated with them. They are: • Code-Protect bit (CPn) The overall structure of the code protection on the • Write-Protect bit (WRTn) PIC18 Flash devices differs significantly from other PIC® microcontroller devices. • External Block Table Read bit (EBTRn) The user program memory is divided into three or five Figure23-2 shows the program memory organization blocks, depending on the device. One of these is a for 8, 16 and 32-Kbyte devices and the specific code Boot Block of 0.5K or 2K bytes, depending on the protection bit associated with each block. The actual device. The remainder of the memory is divided into locations of the bits are summarized in Table. individual blocks on binary boundaries. FIGURE 23-2: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2XK20/4XK20 MEMORY SIZE/DEVICE Block Code Protection 8Kbytes 16Kbytes 32Kbytes 64Kbytes Controlled By: (PIC18FX3K20) (PIC18FX4K20) (PIC18FX5K20) (PIC18FX6K20) Boot Block Boot Block Boot Block Boot Block CPB, WRTB, EBTRB (000h-1FFh) (000h-7FFh) (000h-7FFh) (000h-7FFh) Block 0 Block 0 Block 0 Block 0 CP0, WRT0, EBTR0 (200h-FFFh) (800h-1FFFh) (800h-1FFFh) (800h-3FFFh) Block 1 Block 1 Block 1 Block 1 CP1, WRT1, EBTR1 (1000h-1FFFh) (2000h-3FFFh) (2000h-3FFFh) (4000h-7FFFh) Block 2 Block 2 CP2, WRT2, EBTR2 (4000h-5FFFh) (8000h-BFFFh) Block 3 Block 3 CP3, WRT3, EBTR3 (6000h-7FFFh) (C000h-FFFFh) Unimplemented Unimplemented Read ‘0’s Read ‘0’s (2000h-1FFFFFh) (4000h-1FFFFFh) Unimplemented Unimplemented (Unimplemented Read ‘0’s Read ‘0’s Memory Space) (8000h-1FFFFFh) (10000h-1FFFFFh) TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3(1) CP2(1) CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3(1) WRT2(1) WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. Note 1: Implemented, but not used in PIC18FX3K20 and PIC18FX4K20 devices. DS40001303H-page 292  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 23.3.1 PROGRAM MEMORY instruction that executes from a location outside of that CODE PROTECTION block is not allowed to read and will result in reading ‘0’s. Figures23-3 through23-5 illustrate table write and table The program memory may be read to or written from read protection. any location using the table read and table write instructions. The device ID may be read with table Note: Code protection bits may only be written reads. The Configuration registers may be read and to a ‘0’ from a ‘1’ state. It is not possible to written with the table read and table write instructions. write a ‘1’ to a bit in the ‘0’ state. Code pro- tection bits are only set to ‘1’ by a full chip In normal execution mode, the CPn bits have no direct erase or block erase function. The full chip effect. CPn bits inhibit external reads and writes. A block erase and block erase functions can only of user memory may be protected from table writes if the be initiated via ICSP or an external WRTn Configuration bit is ‘0’. The EBTRn bits control programmer. table reads. For a block of user memory with the EBTRn bit cleared to ‘0’, a table READ instruction that executes from within that block is allowed to read. A table read FIGURE 23-3: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 01 PC = 001FFEh TBLWT* 001FFFh 002000h WRT1, EBTR1 = 11 003FFFh 004000h PC = 005FFEh TBLWT* WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table writes disabled to Blockn whenever WRTn = 0.  2010-2015 Microchip Technology Inc. DS40001303H-page 293

PIC18F2XK20/4XK20 FIGURE 23-4: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 001FFFh 002000h PC = 003FFEh TBLRD* WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. FIGURE 23-5: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 PC = 001FFEh TBLRD* 001FFFh 002000h WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. DS40001303H-page 294  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 23.3.2 DATA EEPROM To use the In-Circuit Debugger function of the micro- CODE PROTECTION controller, the design must implement In-Circuit Serial Programming connections to the following pins: The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD • MCLR/VPP/RE3 inhibits external reads and writes of data EEPROM. • VDD WRTD inhibits internal and external writes to data • VSS EEPROM. The CPU can always read data EEPROM • RB7 under normal operation, regardless of the protection bit • RB6 settings. This will interface to the In-Circuit Debugger module 23.3.3 CONFIGURATION REGISTER available from Microchip or one of the third party devel- PROTECTION opment tool companies. The Configuration registers can be write-protected. 23.7 Single-Supply ICSP Programming The WRTC bit controls protection of the Configuration registers. In Normal Execution mode, the WRTC bit is The LVP Configuration bit enables Single-Supply ICSP readable only. WRTC can only be written via ICSP or Programming (formerly known as Low-Voltage ICSP an external programmer. Programming or LVP). When Single-Supply Program- ming is enabled, the microcontroller can be programmed 23.4 ID Locations without requiring high voltage being applied to the MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then Eight memory locations (200000h-200007h) are dedicated to controlling Program mode entry and is not designated as ID locations, where the user can store available as a general purpose I/O pin. checksum or other code identification numbers. These locations are both readable and writable during normal While programming, using Single-Supply Programming execution through the TBLRD and TBLWT instructions mode, VDD is applied to the MCLR/VPP/RE3 pin as in or during program/verify. The ID locations can be read normal execution mode. To enter Programming mode, when the device is code-protected. VDD is applied to the PGM pin. Note1: High-voltage programming is always 23.5 In-Circuit Serial Programming available, regardless of the state of the PIC18F2XK20/4XK20 devices can be serially LVP bit or the PGM pin, by applying VIHH to the MCLR pin. programmed while in the end application circuit. This is simply done with two lines for clock and data and three 2: By default, Single-Supply ICSP is other lines for power, ground and the programming enabled in unprogrammed devices (as voltage. This allows customers to manufacture boards supplied from Microchip) and erased with unprogrammed devices and then program the devices. microcontroller just before shipping the product. This 3: When Single-Supply Programming is also allows the most recent firmware or a custom enabled, the RB5 pin can no longer be firmware to be programmed. used as a general purpose I/O pin. 4: When LVP is enabled, externally pull the 23.6 In-Circuit Debugger PGM pin to VSS to allow normal program When the DEBUG Configuration bit is programmed to execution. a ‘0’, the In-Circuit Debugger functionality is enabled. If Single-Supply ICSP Programming mode will not be This function allows simple debugging functions when used, the LVP bit can be cleared. RB5/KBI1/PGM then used with MPLAB® IDE. When the microcontroller has becomes available as the digital I/O pin, RB5. The LVP this feature enabled, some resources are not available bit may be set or cleared only when using standard for general use. Table23-4 shows which resources are high-voltage programming (VIHH applied to the MCLR/ required by the background debugger. VPP/RE3 pin). Once LVP has been disabled, only the standard high-voltage programming is available and TABLE 23-4: DEBUGGER RESOURCES must be used to program the device. I/O pins: RB6, RB7 Memory that is not code-protected can be erased using Stack: 2 levels either a block erase, or erased row by row, then written Program Memory: 512 bytes at any specified VDD. If code-protected memory is to be erased, a block erase is required. Data Memory: 10 bytes  2010-2015 Microchip Technology Inc. DS40001303H-page 295

PIC18F2XK20/4XK20 24.0 INSTRUCTION SET SUMMARY The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register PIC18F2XK20/4XK20 devices incorporate the standard designator ‘f’ represents the number of the file in which set of 75 PIC18 core instructions, as well as an extended the bit is located. set of eight new instructions, for the optimization of code The literal instructions may use some of the following that is recursive or that utilizes a software stack. The operands: extended set is discussed later in this section. • A literal value to be loaded into a file register 24.1 Standard Instruction Set (specified by ‘k’) • The desired FSR register to load the literal value The standard PIC18 instruction set adds many into (specified by ‘f’) enhancements to the previous PIC® MCU instruction • No operand required sets, while maintaining an easy migration from these (specified by ‘—’) PIC® MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are The control instructions may use some of the following four instructions that require two program memory operands: locations. • A program memory address (specified by ‘n’) Each single-word instruction is a 16-bit word divided • The mode of the CALL or RETURN instructions into an opcode, which specifies the instruction type and (specified by ‘s’) one or more operands, which further specify the • The mode of the table read and table write operation of the instruction. instructions (specified by ‘m’) The instruction set is highly orthogonal and is grouped • No operand required into four basic categories: (specified by ‘—’) • Byte-oriented operations All instructions are a single word, except for four • Bit-oriented operations double-word instructions. These instructions were made double-word to contain the required information • Literal operations in 32 bits. In the second word, the 4 MSbs are ‘1’s. If • Control operations this second word is executed as an instruction (by The PIC18 instruction set summary in Table24-2 lists itself), it will execute as a NOP. byte-oriented, bit-oriented, literal and control All single-word instructions are executed in a single operations. Table shows the opcode field descriptions. instruction cycle, unless a conditional test is true or the Most byte-oriented instructions have three operands: program counter is changed as a result of the instruc- 1. The file register (specified by ‘f’) tion. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed 2. The destination of the result (specified by ‘d’) as a NOP. 3. The accessed memory (specified by ‘a’) The double-word instructions execute in two instruction The file register designator ‘f’ specifies which file cycles. register is to be used by the instruction. The destination designator ‘d’ specifies where the result of the opera- One instruction cycle consists of four oscillator periods. tion is to be placed. If ‘d’ is zero, the result is placed in Thus, for an oscillator frequency of 4MHz, the normal the WREG register. If ‘d’ is one, the result is placed in instruction execution time is 1s. If a conditional test is true, or the program counter is changed as a result of the file register specified in the instruction. an instruction, the instruction execution time is 2 s. All bit-oriented instructions have three operands: Two-word branch instructions (if true) would take 3 s. 1. The file register (specified by ‘f’) Figure shows the general formats that the instructions 2. The bit in the file register (specified by ‘b’) can have. All examples use the convention ‘nnh’ to rep- 3. The accessed memory (specified by ‘a’) resent a hexadecimal number. TABLE 24-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. DS40001303G-page 296  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 24-1: OPCODE FIELD DESCRIPTIONS (CONTINUED) Field Description d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). f 12-bit Register file address (000h to FFFh). This is the source address. s f 12-bit Register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for CALL/BRANCH and RETURN instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for indirect addressing of register files (source). s z 7-bit offset value for indirect addressing of register files (destination). d { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr.  Assigned to. < > Register bit field.  In the set of. italics User defined term (font is Courier).  2010-2015 Microchip Technology Inc. DS40001303G-page 297

PIC18F2XK20/4XK20 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC DS40001303G-page 298  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 24-2: PIC18FXXXX INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and CARRY bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N borrow SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem- ory locations have a valid instruction.  2010-2015 Microchip Technology Inc. DS40001303G-page 299

PIC18F2XK20/4XK20 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call subroutine 1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software device Reset 1 0000 0000 1111 1111 All RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem- ory locations have a valid instruction. DS40001303G-page 300  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY  PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem- ory locations have a valid instruction.  2010-2015 Microchip Technology Inc. DS40001303G-page 301

PIC18F2XK20/4XK20 24.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) + k  W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f)  dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: ADDLW 15h Section24.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. W = 10h After Instruction Words: 1 W = 25h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS40001303G-page 302  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 ADDWFC ADD W and CARRY bit to f ANDLW AND literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0  f  255 Operands: 0  k  255 d [0,1] Operation: (W) .AND. k  W a [0,1] Status Affected: N, Z Operation: (W) + (f) + (C)  dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are AND’ed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the CARRY flag and data mem- Words: 1 ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Decode Read literal Process Write to W If ‘a’ is ‘0’ and the extended instruction ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ANDLW 05Fh mode whenever f 95 (5Fh). See Section24.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = A3h Literal Offset Mode” for details. After Instruction Words: 1 W = 03h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction CARRY bit= 1 REG = 02h W = 4Dh After Instruction CARRY bit= 0 REG = 02h W = 50h  2010-2015 Microchip Technology Inc. DS40001303G-page 303

PIC18F2XK20/4XK20 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0  f  255 Operands: -128  n  127 d [0,1] Operation: if CARRY bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: (W) .AND. (f)  dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the CARRY bit is ‘1’, then the program Description: The contents of W are AND’ed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’ (default). incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC+2+2n. This instruction is then a GPR bank. two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Q Cycle Activity: Section24.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to PC Words: 1 ‘n’ Data Cycles: 1 No No No No operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If CARRY = 1; W = 02h PC = address (HERE + 12) REG = C2h If CARRY = 0; PC = address (HERE + 2) DS40001303G-page 304  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0  f  255 Operands: -128  n  127 0  b  7 Operation: if NEGATIVE bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: 0  f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the NEGATIVE bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank. incremented to fetch the next If ‘a’ is ‘0’ and the extended instruction instruction, the new address will be set is enabled, this instruction operates PC+2+2n. This instruction is then a in Indexed Literal Offset Addressing two-cycle instruction. mode whenever f 95 (5Fh). See Words: 1 Section24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1(2) Literal Offset Mode” for details. Q Cycle Activity: Words: 1 If Jump: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC Q Cycle Activity: ‘n’ Data Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No Before Instruction ‘n’ Data operation FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If NEGATIVE = 1; PC = address (Jump) If NEGATIVE = 0; PC = address (HERE + 2)  2010-2015 Microchip Technology Inc. DS40001303G-page 305

PIC18F2XK20/4XK20 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128  n  127 Operands: -128  n  127 Operation: if CARRY bit is ‘0’ Operation: if NEGATIVE bit is ‘0’ (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the CARRY bit is ‘0’, then the program Description: If the NEGATIVE bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a 2-cycle instruction. 2-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If CARRY = 0; If NEGATIVE = 0; PC = address (Jump) PC = address (Jump) If CARRY = 1; If NEGATIVE = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS40001303G-page 306  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128  n  127 Operands: -128  n  127 Operation: if OVERFLOW bit is ‘0’ Operation: if ZERO bit is ‘0’ (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the OVERFLOW bit is ‘0’, then the Description: If the ZERO bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a 2-cycle instruction. 2-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If OVERFLOW= 0; If ZERO = 0; PC = address (Jump) PC = address (Jump) If OVERFLOW= 1; If ZERO = 1; PC = address (HERE + 2) PC = address (HERE + 2)  2010-2015 Microchip Technology Inc. DS40001303G-page 307

PIC18F2XK20/4XK20 BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024  n  1023 Operands: 0  f  255 0  b  7 Operation: (PC) + 2 + 2n  PC a [0,1] Status Affected: None Operation: 1  f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incre- mented to fetch the next instruction, the Description: Bit ‘b’ in register ‘f’ is set. new address will be PC+2+2n. This If ‘a’ is ‘0’, the Access Bank is selected. instruction is a 2-cycle instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section24.2.3 “Byte-Oriented and Decode Read literal Process Write to PC Bit-Oriented Instructions in Indexed ‘n’ Data Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah DS40001303G-page 308  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0  f  255 Operands: 0  f  255 0  b  7 0  b < 7 a [0,1] a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a 2-cycle instruction. this a 2-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in set is enabled, this instruction operates Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). mode whenever f 95 (5Fh). See Section24.2.3 “Byte-Oriented and See Section24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE)  2010-2015 Microchip Technology Inc. DS40001303G-page 309

PIC18F2XK20/4XK20 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0  f  255 Operands: -128  n  127 0  b < 7 Operation: if OVERFLOW bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: (f<b>)  f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the OVERFLOW bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank. instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC+2+2n. This instruction is then a set is enabled, this instruction operates 2-cycle instruction. in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Section24.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: PORTC = 0110 0101 [65h] Before Instruction PC = address (HERE) After Instruction If OVERFLOW= 1; PC = address (Jump) If OVERFLOW= 0; PC = address (HERE + 2) DS40001303G-page 310  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128  n  127 Operands: 0  k  1048575 s [0,1] Operation: if ZERO bit is ‘1’ (PC) + 2 + 2n  PC Operation: (PC) + 4  TOS, k  PC<20:1>, Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (W)  WS, Description: If the ZERO bit is ‘1’, then the program (Status)  STATUSS, will branch. (BSR)  BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will Encoding: have incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk PC+2+2n. This instruction is then a 19 8 2-cycle instruction. Description: Subroutine call of entire 2-Mbyte memory range. First, return address Words: 1 (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, Status and BSR Q Cycle Activity: registers are also pushed into their If Jump: respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs (default). Then, the Decode Read literal Process Write to PC 20-bit value ‘k’ is loaded into PC<20:1>. ‘n’ Data CALL is a 2-cycle instruction. No No No No Words: 2 operation operation operation operation If No Jump: Cycles: 2 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process No Q1 Q2 Q3 Q4 ‘n’ Data operation Decode Read literal PUSH PC to Read literal ‘k’<7:0>, stack ‘k’<19:8>, Example: HERE BZ Jump Write to PC No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction If ZERO = 1; Example: HERE CALL THERE, 1 PC = address (Jump) If ZERO = 0; Before Instruction PC = address (HERE + 2) PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= Status  2010-2015 Microchip Technology Inc. DS40001303G-page 311

PIC18F2XK20/4XK20 CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0  f  255 Operands: None a [0,1] Operation: 000h  WDT, Operation: 000h  f 000h  WDT postscaler, 1  Z 1  TO, 1  PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the post- If ‘a’ is ‘1’, the BSR is used to select the scaler of the WDT. Status bits, TO and GPR bank. PD, are set. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1 mode whenever f 95 (5Fh). See Q Cycle Activity: Section24.2.3 “Byte-Oriented and Q1 Q2 Q3 Q4 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Decode No Process No operation Data operation Words: 1 Cycles: 1 Example: CLRWDT Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 WDT Counter = ? Decode Read Process Write After Instruction register ‘f’ Data register ‘f’ WDT Counter = 00h WDT Postscaler = 0 TO = 1 Example: CLRF FLAG_REG, 1 PD = 1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h DS40001303G-page 312  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: (f)  dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a 2-cycle GPR bank. instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank. mode whenever f 95 (5Fh). See If ‘a’ is ‘0’ and the extended instruction Section24.2.3 “Byte-Oriented and set is enabled, this instruction operates Bit-Oriented Instructions in Indexed in Indexed Literal Offset Addressing Literal Offset Mode” for details. mode whenever f 95 (5Fh). See Words: 1 Section24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process Write to Note: 3 cycles if skip and followed register ‘f’ Data destination by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h Q1 Q2 Q3 Q4 W = ECh No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG  W; PC = Address (NEQUAL)  2010-2015 Microchip Technology Inc. DS40001303G-page 313

PIC18F2XK20/4XK20 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0  f  255 Operands: 0  f  255 a  [0,1] a  [0,1] Operation: (f) –W), Operation: (f) –W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory Description: Compares the contents of data memory location ‘f’ to the contents of the W by location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the , If the contents of ‘f’ are less than the contents of WREG then the fetched contents of W, then the fetched instruction is discarded and a NOP is instruction is discarded and a NOP is executed instead, making this a executed instead, making this a 2-cycle instruction. 2-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Note: 3 cycles if skip and followed Section24.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process No Cycles: 1(2) Note: 3 cycles if skip and followed register ‘f’ Data operation by a 2-word instruction. If skip: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No Decode Read Process No operation operation operation operation register ‘f’ Data operation If skip and followed by 2-word instruction: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; Before Instruction PC = Address (LESS) PC = Address (HERE) If REG  W; W = ? PC = Address (NLESS) After Instruction If REG  W; PC = Address (GREATER) If REG  W; PC = Address (NGREATER) DS40001303G-page 314  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0  f  255 d  [0,1] Operation: If [W<3:0> > 9] or [DC = 1] then a  [0,1] (W<3:0>) + 6  W<3:0>; else Operation: (f) – 1  dest ( W<3:0>)  W<3:0>; Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then Encoding: 0000 01da ffff ffff ( W<7:4>) + 6 + DC  W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the else result is stored in W. If ‘d’ is ‘1’, the (W<7:4>) + DC  W<7:4> result is stored back in register ‘f’ Status Affected: C (default). If ‘a’ is ‘0’, the Access Bank is selected. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the Description: DAW adjusts the 8-bit value in W, result- GPR bank. ing from the earlier addition of two vari- If ‘a’ is ‘0’ and the extended instruction ables (each in packed BCD format) and set is enabled, this instruction operates produces a correct packed BCD result. in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Words: 1 Section24.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write Cycles: 1 register W Data W Q Cycle Activity: Example1: Q1 Q2 Q3 Q4 DAW Decode Read Process Write to Before Instruction register ‘f’ Data destination W = A5h C = 0 DC = 0 Example: DECF CNT, 1, 0 After Instruction Before Instruction W = 05h CNT = 01h Z = 0 C = 1 DC = 0 After Instruction Example 2: CNT = 00h Z = 1 Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0  2010-2015 Microchip Technology Inc. DS40001303G-page 315

PIC18F2XK20/4XK20 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – 1  dest, Operation: (f) – 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, If the result is not ‘0’, the next which is already fetched, is discarded instruction, which is already fetched, is and a NOP is executed instead, making discarded and a NOP is executed it a 2-cycle instruction. instead, making it a 2-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank. set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing Section24.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See Bit-Oriented Instructions in Indexed Section24.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT - 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT  0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP  0; PC = Address (NZERO) DS40001303G-page 316  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0  k  1048575 Operands: 0  f  255 d  [0,1] Operation: k  PC<20:1> a  [0,1] Status Affected: None Operation: (f) + 1  dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire incremented. If ‘d’ is ‘0’, the result is 2-Mbyte memory range. The 20-bit placed in W. If ‘d’ is ‘1’, the result is value ‘k’ is loaded into PC<20:1>. placed back in register ‘f’ (default). GOTO is always a 2-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 2 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section24.2.3 “Byte-Oriented and Decode Read literal No Read literal Bit-Oriented Instructions in Indexed ‘k’<7:0>, operation ‘k’<19:8>, Literal Offset Mode” for details. Write to PC Words: 1 No No No No operation operation operation operation Cycles: 1 Q Cycle Activity: Example: GOTO THERE Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to PC = Address (THERE) register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1  2010-2015 Microchip Technology Inc. DS40001303G-page 317

PIC18F2XK20/4XK20 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) + 1  dest, Operation: (f) + 1  dest, skip if result  0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is not ‘0’, the next If the result is ‘0’, the next instruction, instruction, which is already fetched, is which is already fetched, is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a 2-cycle it a 2-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section24.2.3 “Byte-Oriented and Section24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG  0; PC = Address (ZERO) PC = Address (NZERO) If CNT  0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) DS40001303G-page 318  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) .OR. k  W a  [0,1] Status Affected: N, Z Operation: (W) .OR. (f)  dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is Words: 1 ‘0’, the result is placed in W. If ‘d’ is ‘1’, Cycles: 1 the result is placed back in register ‘f’ Q Cycle Activity: (default). If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to W GPR bank. literal ‘k’ Data If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: IORLW 35h in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Before Instruction Section24.2.3 “Byte-Oriented and W = 9Ah Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = BFh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h  2010-2015 Microchip Technology Inc. DS40001303G-page 319

PIC18F2XK20/4XK20 LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0  f  2 Operands: 0  f  255 0  k  4095 d  [0,1] a  [0,1] Operation: k  FSRf Operation: f  dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to File Select Register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’ (default). Q Cycle Activity: Location ‘f’ can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read literal Process Write If ‘a’ is ‘1’, the BSR is used to select the ‘k’ MSB Data literal ‘k’ GPR bank. MSB to If ‘a’ is ‘0’ and the extended instruction FSRfH set is enabled, this instruction operates Decode Read literal Process Write literal in Indexed Literal Offset Addressing ‘k’ LSB Data ‘k’ to FSRfL mode whenever f 95 (5Fh). See Section24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Example: LFSR 2, 3ABh Literal Offset Mode” for details. After Instruction Words: 1 FSR2H = 03h FSR2L = ABh Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write W register ‘f’ Data Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h DS40001303G-page 320  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0  f  4095 Operands: 0  k  255 s 0  f  4095 d Operation: k  BSR Operation: (f )  f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The 8-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffffs Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffffd of BSR<7:4> always remains ‘0’, Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Either source or destination can be W Decode Read Process Write literal (a useful special situation). literal ‘k’ Data ‘k’ to BSR MOVFF is particularly useful for transferring a data memory location to a Example: MOVLB 5 peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h The MOVFF instruction cannot use the After Instruction PCL, TOSU, TOSH or TOSL as the BSR Register = 05h destination register. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h  2010-2015 Microchip Technology Inc. DS40001303G-page 321

PIC18F2XK20/4XK20 MOVLW Move literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: k  W Operation: (W)  f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The 8-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: MOVLW 5Ah mode whenever f 95 (5Fh). See Section24.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 5Ah Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh DS40001303G-page 322  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 MULLW Multiply literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: (W) x k  PRODH:PRODL Operation: (W) x (f)  PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried 8-bit literal ‘k’. The 16-bit result is out between the contents of W and the placed in the PRODH:PRODL register register file location ‘f’. The 16-bit pair. PRODH contains the high byte. result is stored in the PRODH:PRODL W is unchanged. register pair. PRODH contains the None of the Status flags are affected. high byte. Both W and ‘f’ are Note that neither overflow nor carry is unchanged. possible in this operation. A zero result None of the Status flags are affected. is possible but not detected. Note that neither overflow nor carry is possible in this operation. A zero Words: 1 result is possible but not detected. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is Q Cycle Activity: selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write set is enabled, this instruction literal ‘k’ Data registers operates in Indexed Literal Offset PRODH: Addressing mode whenever PRODL f 95 (5Fh). See Section24.2.3 “Byte-Oriented and Bit-Oriented Example: MULLW 0C4h Instructions in Indexed Literal Offset Mode” for details. Before Instruction Words: 1 W = E2h PRODH = ? Cycles: 1 PRODL = ? Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = E2h PRODH = ADh Decode Read Process Write PRODL = 08h register ‘f’ Data registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h  2010-2015 Microchip Technology Inc. DS40001303G-page 323

PIC18F2XK20/4XK20 NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0  f  255 Operands: None a  [0,1] Operation: No operation Operation: (f) + 1  f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Decode No No No in Indexed Literal Offset Addressing operation operation operation mode whenever f 95 (5Fh). See Section24.2.3 “Byte-Oriented and Example: Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] DS40001303G-page 324  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC+2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah  2010-2015 Microchip Technology Inc. DS40001303G-page 325

PIC18F2XK20/4XK20 RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n  PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset by software. address (PC+2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC+2+2n. This instruction is a 2-cycle instruction. Decode Start No No Reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to PC Flags* = Reset Value ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2) DS40001303G-page 326  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 RETFIE Return from Interrupt RETLW Return literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, Operation: k  W, 1  GIE/GIEH or PEIE/GIEL, (TOS)  PC, if s = 1 PCLATU, PCLATH are unchanged (WS)  W, Status Affected: None (STATUSS)  Status, (BSRS)  BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged. Description: W is loaded with the 8-bit literal ‘k’. The Status Affected: GIE/GIEH, PEIE/GIEL. program counter is loaded from the top of the stack (the return address). The Encoding: 0000 0000 0001 000s high address latch (PCLATH) remains Description: Return from interrupt. Stack is popped unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers, WS, Q1 Q2 Q3 Q4 STATUSS and BSRS, are loaded into their corresponding registers, W, Decode Read Process POP PC Status and BSR. If ‘s’ = 0, no update of literal ‘k’ Data from stack, these registers occurs (default). Write to W No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS W = WS RETLW kn ; End of table BSR = BSRS Status = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn  2010-2015 Microchip Technology Inc. DS40001303G-page 327

PIC18F2XK20/4XK20 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s  [0,1] Operands: 0  f  255 d  [0,1] Operation: (TOS)  PC, a  [0,1] if s = 1 (WS)  W, Operation: (f<n>)  dest<n + 1>, (STATUSS)  Status, (f<7>)  C, (BSRS)  BSR, (C)  dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the CARRY popped and the top of the stack (TOS) flag. If ‘d’ is ‘0’, the result is placed in is loaded into the program counter. If W. If ‘d’ is ‘1’, the result is stored back ‘s’= 1, the contents of the shadow in register ‘f’ (default). registers, WS, STATUSS and BSRS, If ‘a’ is ‘0’, the Access Bank is are loaded into their corresponding selected. If ‘a’ is ‘1’, the BSR is used to registers, W, Status and BSR. If select the GPR bank. ‘s’ = 0, no update of these registers If ‘a’ is ‘0’ and the extended instruction occurs (default). set is enabled, this instruction operates in Indexed Literal Offset Words: 1 Addressing mode whenever Cycles: 2 f 95 (5Fh). See Section24.2.3 Q Cycle Activity: “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Q1 Q2 Q3 Q4 Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 DS40001303G-page 328  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f<n>)  dest<n + 1>, Operation: (f<n>)  dest<n – 1>, (f<7>)  dest<0> (f<0>)  C, (C)  dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the CARRY stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W. If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘1’, the BSR is used to select the register ‘f’ (default). GPR bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the set is enabled, this instruction operates GPR bank. in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f 95 (5Fh). See set is enabled, this instruction operates Section24.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f 95 (5Fh). See Literal Offset Mode” for details. Section24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0  2010-2015 Microchip Technology Inc. DS40001303G-page 329

PIC18F2XK20/4XK20 RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a [0,1] a  [0,1] Operation: FFh  f Operation: (f<n>)  dest<n – 1>, Status Affected: None (f<0>)  dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank. placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected (default), overriding the BSR in Indexed Literal Offset Addressing value. If ‘a’ is ‘1’, then the bank will be mode whenever f 95 (5Fh). See selected as per the BSR value. Section24.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Section24.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG, 1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 DS40001303G-page 330  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 SLEEP Enter Sleep mode SUBFWB Subtract f from W with borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 f 255 d  [0,1] Operation: 00h  WDT, a  [0,1] 0  WDT postscaler, 1  TO, Operation: (W) – (f) – (C) dest 0  PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and CARRY flag Description: The Power-down Status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out Status bit (TO) method). If ‘d’ is ‘0’, the result is stored is set. Watchdog Timer and its in W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’ (default). The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is with the oscillator stopped. selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction Q Cycle Activity: operates in Indexed Literal Offset Addressing mode whenever Q1 Q2 Q3 Q4 f 95 (5Fh). See Section24.2.3 Decode No Process Go to “Byte-Oriented and Bit-Oriented operation Data Sleep Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? After Instruction Q1 Q2 Q3 Q4 TO = 1 † Decode Read Process Write to PD = 0 register ‘f’ Data destination Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0  2010-2015 Microchip Technology Inc. DS40001303G-page 331

PIC18F2XK20/4XK20 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 k 255 Operands: 0 f 255 d  [0,1] Operation: k – (W) W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description W is subtracted from the 8-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the Q Cycle Activity: result is stored back in register ‘f’ (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is Decode Read Process Write to W selected. If ‘a’ is ‘1’, the BSR is used literal ‘k’ Data to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction Before Instruction operates in Indexed Literal Offset W = 01h Addressing mode whenever C = ? f 95 (5Fh). See Section24.2.3 After Instruction W = 01h “Byte-Oriented and Bit-Oriented C = 1 ; result is positive Instructions in Indexed Literal Offset Z = 0 Mode” for details. N = 0 Words: 1 Example 2: SUBLW 02h Cycles: 1 Before Instruction W = 02h Q Cycle Activity: C = ? Q1 Q2 Q3 Q4 After Instruction W = 00h Decode Read Process Write to C = 1 ; result is zero register ‘f’ Data destination Z = 1 N = 0 Example 1: SUBWF REG, 1, 0 Example 3: SUBLW 02h Before Instruction REG = 3 Before Instruction W = 2 W = 03h C = ? C = ? After Instruction After Instruction REG = 1 W = FFh ; (2’s complement) W = 2 C = 0 ; result is negative C = 1 ; result is positive Z = 0 Z = 0 N = 1 N = 0 Example 2: SUBWF REG, 0, 0 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 DS40001303G-page 332  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: (f<3:0>)  dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>)  dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the CARRY flag Encoding: 0011 10da ffff ffff (borrow) from register ‘f’ (2’s comple- Description: The upper and lower nibbles of register ment method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is ‘f’ are exchanged. If ‘d’ is ‘0’, the result stored back in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section24.2.3 “Byte-Oriented and Section24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1100) After Instruction W = 0Dh (0000 1101) C = 1 REG = 35h Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1110) C = 1 After Instruction REG = F5h (1111 0101) ; [2’s comp] W = 0Eh (0000 1110) C = 0 Z = 0 N = 1 ; result is negative  2010-2015 Microchip Technology Inc. DS40001303G-page 333

PIC18F2XK20/4XK20 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR))  TABLAT; MEMORY (00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR))  TABLAT; TBLPTR = 00A357h (TBLPTR) + 1  TBLPTR; Example2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR))  TABLAT; Before Instruction (TBLPTR) – 1  TBLPTR; TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY (01A357h) = 12h (TBLPTR) + 1  TBLPTR; MEMORY (01A358h) = 34h (Prog Mem (TBLPTR))  TABLAT; After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write TABLAT) Memory) DS40001303G-page 334  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT)  Holding Register; TBLPTR = 00A356h TBLPTR – No Change; HOLDING REGISTER (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT)  Holding Register; TABLAT = 55h (TBLPTR) + 1  TBLPTR; TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT)  Holding Register; (00A356h) = 55h (TBLPTR) – 1  TBLPTR; Example 2: TBLWT +*; if TBLWT+*, (TBLPTR) + 1  TBLPTR; Before Instruction (TABLAT)  Holding Register; TABLAT = 34h TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER 8 holding registers the TABLAT is written (01389Bh) = 34h to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section6.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register )  2010-2015 Microchip Technology Inc. DS40001303G-page 335

PIC18F2XK20/4XK20 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0  f  255 Operands: 0 k 255 a  [0,1] Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a 2-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Decode Read Process Write to W in Indexed Literal Offset Addressing literal ‘k’ Data mode whenever f 95 (5Fh). See Section24.2.3 “Byte-Oriented and Example: XORLW 0AFh Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Before Instruction W = B5h Words: 1 After Instruction Cycles: 1(2) W = 1Ah Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT  00h, PC = Address (NZERO) DS40001303G-page 336  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h  2010-2015 Microchip Technology Inc. DS40001303G-page 337

PIC18F2XK20/4XK20 24.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table24-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section24.2.2 “Extended Instruction instruction set, PIC18F2XK20/4XK20 devices also Set”. The opcode field descriptions in Table apply to provide an optional extension to the core CPU both the standard and extended PIC18 instruction sets. functionality. The added features include eight additional instructions that augment indirect and Note: The instruction set extension and the indexed addressing operations and the implementation Indexed Literal Offset Addressing mode of Indexed Literal Offset Addressing mode for many of were designed for optimizing applications the standard PIC18 instructions. written in C; the user may likely never use these instructions directly in assembler. The additional features of the extended instruction set The syntax for these commands is pro- are disabled by default. To enable them, users must set vided as a reference for users who may be the XINST Configuration bit. reviewing code that has been generated The instructions in the extended set can all be by a compiler. classified as literal operations, which either manipulate the File Select Registers, or use them for indexed 24.2.1 EXTENDED INSTRUCTION SYNTAX addressing. Two of the instructions, ADDFSR and Most of the extended instructions use indexed SUBFSR, each have an additional special instantiation arguments, using one of the File Select Registers and for using FSR2. These versions (ADDULNK and some offset to specify a source or destination register. SUBULNK) allow for automatic return after execution. When an argument for an instruction serves as part of The extended instructions are specifically implemented indexed addressing, it is enclosed in square brackets to optimize re-entrant program code (that is, code that (“[ ]”). This is done to indicate that the argument is used is recursive or that uses a software stack) written in as an index or offset. MPASM™ Assembler will flag an high-level languages, particularly C. Among other error if it determines that an index or offset value is not things, they allow users working in high-level bracketed. languages to perform certain operations on data When the extended instruction set is enabled, brackets structures more efficiently. These include: are also used to indicate index arguments in byte- • dynamic allocation and deallocation of software oriented and bit-oriented instructions. This is in addition stack space when entering and leaving to other changes in their syntax. For more details, see subroutines Section24.2.3.1 “Extended Instruction Syntax with • function pointer invocation Standard PIC18 Commands”. • software Stack Pointer manipulation Note: In the past, square brackets have been • manipulation of variables located in a software used to denote optional arguments in the stack PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 24-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add literal to FSR2 and return 2 1110 1000 11kk kkkk None CALLW Call subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz PUSHL k Store literal at FSR2, 1 1110 1010 kkkk kkkk None decrement FSR2 SUBFSR f, k Subtract literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract literal from FSR2 and 2 1110 1001 11kk kkkk None return DS40001303G-page 338  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 24.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 + k  FSR2, Operation: FSR(f) + k  FSR(f) (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during Q1 Q2 Q3 Q4 the second cycle. Decode Read Process Write to This may be thought of as a special literal ‘k’ Data FSR case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Example: ADDFSR 2, 23h Words: 1 Before Instruction Cycles: 2 FSR2 = 03FFh After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).  2010-2015 Microchip Technology Inc. DS40001303G-page 339

PIC18F2XK20/4XK20 CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0  z  127 s 0  f  4095 Operation: (PC + 2)  TOS, d (W)  PCL, Operation: ((FSR2) + z )  f s d (PCLATH)  PCH, Status Affected: None (PCLATU)  PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’ in the first word to the value of s latched into PCH and PCU, FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘f ’ in the second word. Both addresses d new next instruction is fetched. can be anywhere in the 4096-byte data Unlike CALL, there is no option to space (000h to FFFh). update W, Status or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an indirect addressing register, the value returned will be 00h. Q1 Q2 Q3 Q4 Decode Read PUSH PC to No Words: 2 WREG stack operation Cycles: 2 No No No No Q Cycle Activity: operation operation operation operation Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Decode No No Write Before Instruction operation operation register ‘f’ PC = address (HERE) PCLATH = 10h No dummy (dest) PCLATU = 00h read W = 06h After Instruction PC = 001006h Example: MOVSF [05h], REG2 TOS = address (HERE + 2) PCLATH = 10h Before Instruction PCLATU = 00h FSR2 = 80h W = 06h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h DS40001303G-page 340  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0  zs  127 Operands: 0k  255 0  z  127 d Operation: k  (FSR2), Operation: ((FSR2) + zs)  ((FSR2) + zd) FSR2 – 1  FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1111 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. FSR2 Description The contents of the source register are is decremented by 1 after the operation. moved to the destination register. The This instruction allows users to push values addresses of the source and destination onto a software stack. registers are determined by adding the 7-bit literal offsets ‘z ’ or ‘z ’, Words: 1 s d respectively, to the value of FSR2. Both Cycles: 1 registers can be located anywhere in the 4096-byte data memory space Q Cycle Activity: (000h to FFFh). Q1 Q2 Q3 Q4 The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to PCL, TOSU, TOSH or TOSL as the data destination destination register. If the resultant source address points to an indirect addressing register, the Example: PUSHL 08h value returned will be 00h. If the resultant destination address points to Before Instruction an indirect addressing register, the FSR2H:FSR2L = 01ECh Memory (01ECh) = 00h instruction will execute as a NOP. Words: 2 After Instruction FSR2H:FSR2L = 01EBh Cycles: 2 Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h  2010-2015 Microchip Technology Inc. DS40001303G-page 341

PIC18F2XK20/4XK20 SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 – k  FSR2 Operation: FSR(f) – k  FSRf (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified by contents of the FSR2. A RETURN is then ‘f’. executed by loading the PC with the TOS. Words: 1 The instruction takes two cycles to execute; a NOP is performed during the Cycles: 1 second cycle. Q Cycle Activity: This may be thought of as a special case of Q1 Q2 Q3 Q4 the SUBFSR instruction, where f = 3 (binary Decode Read Process Write to ‘11’); it operates only on FSR2. register ‘f’ Data destination Words: 1 Cycles: 2 Q Cycle Activity: Example: SUBFSR 2, 23h Q1 Q2 Q3 Q4 Before Instruction FSR2 = 03FFh Decode Read Process Write to register ‘f’ Data destination After Instruction FSR2 = 03DCh No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) DS40001303G-page 342  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 24.2.3 BYTE-ORIENTED AND 24.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file register argument, ‘f’, in the standard byte-oriented and Note: Enabling the PIC18 instruction set bit-oriented commands is replaced with the literal offset extension may cause legacy applications value, ‘k’. As already noted, this occurs only when ‘f’ is to behave erratically or fail entirely. less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing mode (Section5.5.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within brackets, will generate an the standard PIC18 instruction set are interpreted. error in the MPASM Assembler. When the extended set is disabled, addresses If the index argument is properly bracketed for Indexed embedded in opcodes are treated as literal memory Literal Offset Addressing, the Access RAM argument is locations: either as a location in the Access Bank (‘a’ = never specified; it will automatically be assumed to be 0), or in a GPR bank designated by the BSR (‘a’ = 1). ‘0’. This is in contrast to standard operation (extended When the extended instruction set is enabled and ‘a’ = instruction set disabled) when ‘a’ is set on the basis of 0, however, a file register argument of 5Fh or less is the target address. Declaring the Access RAM bit in interpreted as an offset from the pointer value in FSR2 this mode will also generate an error in the MPASM and not as a literal address. For practical purposes, this Assembler. means that all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bit- The destination argument, ‘d’, functions as before. oriented instructions, or almost half of the core PIC18 In the latest versions of the MPASM™ assembler, instructions – may behave differently when the language support for the extended instruction set must extended instruction set is enabled. be explicitly invoked. This is done with either the When the content of FSR2 is 00h, the boundaries of the command line option, /y, or the PE directive in the Access RAM are essentially remapped to their original source listing. values. This may be useful in creating backward 24.2.4 CONSIDERATIONS WHEN compatible code. If this technique is used, it may be ENABLING THE EXTENDED necessary to save the value of FSR2 and restore it INSTRUCTION SET when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users It is important to note that the extensions to the instruc- must also keep in mind the syntax requirements of the tion set may not be beneficial to all users. In particular, extended instruction set (see Section24.2.3.1 users who are not writing code that uses a software “Extended Instruction Syntax with Standard PIC18 stack may not benefit from using the extensions to the Commands”). instruction set. Although the Indexed Literal Offset Addressing mode Additionally, the Indexed Literal Offset Addressing can be very useful for dynamic stack and pointer mode may create issues with legacy applications manipulation, it can also be very annoying if a simple written to the PIC18 assembler. This is because arithmetic operation is carried out on the wrong instructions in the legacy code may attempt to address register. Users who are accustomed to the PIC18 registers in the Access Bank below 5Fh. Since these programming must keep in mind that, when the addresses are interpreted as literal offsets to FSR2 extended instruction set is enabled, register addresses when the instruction set extension is enabled, the of 5Fh or less are used for Indexed Literal Offset application may read or write to the wrong data Addressing. addresses. Representative examples of typical byte-oriented and When porting an application to the PIC18F2XK20/ bit-oriented instructions in the Indexed Literal Offset 4XK20, it is very important to consider the type of code. Addressing mode are provided on the following page to A large, re-entrant application that is written in ‘C’ and show how execution is affected. The operand condi- would benefit from efficient compilation will do well tions shown in the examples are applicable to all when using the instruction set extensions. Legacy instructions of these types. applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set.  2010-2015 Microchip Technology Inc. DS40001303G-page 343

PIC18F2XK20/4XK20 ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0  k  95 Operands: 0  f  95 d  [0,1] 0  b  7 Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in Cycles: 1 register ‘f’ (default). Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Example: ADDWF [OFST], 0 Contents of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction W = 37h Set Indexed Contents SETF of 0A2Ch = 20h (Indexed Literal Offset mode) Syntax: SETF [k] Operands: 0  k  95 Operation: FFh  ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh DS40001303G-page 344  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 24.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18F2XK20/4XK20 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is ‘0’, disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: • A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project • A command line option • A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information.  2010-2015 Microchip Technology Inc. DS40001303G-page 345

PIC18F2XK20/4XK20 25.0 DEVELOPMENT SUPPORT 25.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker DS40001303H-page 346  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 25.2 MPLAB XC Compilers 25.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 25.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 25.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process  2010-2015 Microchip Technology Inc. DS40001303H-page 347

PIC18F2XK20/4XK20 25.6 MPLAB X SIM Software Simulator 25.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 25.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 25.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 25.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS40001303H-page 348  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 25.11 Demonstration/Development 25.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2010-2015 Microchip Technology Inc. DS40001303H-page 349

PIC18F2XK20/4XK20 26.0 ELECTRICAL SPECIFICATIONS 26.1 Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on pins with respect to VSS (except VDD, and MCLR)........................................................-0.3V to (VDD + 0.3V) on VDD pin .............................................................................................................................. -0.3V to +4.5V on MCLR(2).................................................................................................................................0V to +11.0V Total power dissipation(1)..........................................................................................................................................1.0W Maximum current PIC18F2XK20/4XK20 out of VSS pin, -40°C to +85°C for industrial...................................................................................... 350mA out of VSS pin, +85°C to +125°C for extended................................................................................... 120 mA PIC18F4XK20 into VDD pin, -40°C to +85°C for industrial......................................................................................... 350mA into VDD pin, +85°C to +125°C for extended.......................................................................................120 mA PIC18F2XK20 into VDD pin, -40°C to +85°C for industrial......................................................................................... 250mA into VDD pin, +85°C to +125°C for extended.........................................................................................85 mA Input clamp current, IIK (VI < 0 or VI > VDD)20mA Maximum output current sunk by any I/O pin...............................................................................................................................50mA sourced by any I/O pin..........................................................................................................................50mA Note1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL). 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP/RE3 pin, rather than pulling this pin directly to VSS. 3: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations. See Table26-15 to calculate device specifications. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001303H-page 350  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 26.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: VDDMIN VDD VDDMAX Operating Temperature: TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC18F2XK20/4XK20 VDDMIN (Fosc < = 16 MHz)...................................................................................................... +1.8V VDDMIN (Fosc < = 20 MHz)...................................................................................................... +2.0V VDDMIN (Fosc < = 48 MHz, Extended Temperature)................................................................ +3.0V VDDMIN (Fosc < = 64 MHz, Industrial Temperature)................................................................ +3.0V VDDMAX.................................................................................................................................... +3.6V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN...................................................................................................................................... -40°C TA_MAX.................................................................................................................................... +85°C Extended Temperature TA_MIN...................................................................................................................................... -40°C TA_MAX.................................................................................................................................. +125°C Note1: See Parameter D001 in DC Characteristics: Supply Voltage.  2010-2015 Microchip Technology Inc. DS40001303H-page 351

PIC18F2XK20/4XK20 FIGURE 26-1: PIC18F2XK20/4XK20 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 3.5V 3.0V 2.7V e g a 2.0V t ol V 1.8V 10 16 20 30 32 40 4850 60 64 Frequency (MHz) Note: Maximum Frequency 16 MHz, 1.8V to 2.0V, -40°C to +125°C Maximum Frequency 20 MHz, 2.0V to 3.0V, -40°C to +125°C Maximum Frequency 48 MHz, 3.0V to 3.6V, -40°C to +125°C FIGURE 26-2: PIC18F2XK20/4XK20 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.5V 3.0V 2.7V e g a 2.0V t ol V 1.8V 10 16 20 30 32 40 50 60 64 Frequency (MHz) Note: Maximum Frequency 16 MHz, 1.8V to 2.0V, -40°C to +85°C Maximum Frequency 20 MHz, 2.0V to 3.0V, -40°C to +85°C Maximum Frequency 64 MHz, 3.0V to 3.6V, -40°C to +85°C DS40001303H-page 352  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 26.3 DC Characteristics TABLE 26-1: SUPPLY VOLTAGE, PIC18F2XK20/4XK20 PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. D001 VDD Supply Voltage 1.8 — 3.6 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See section on Power-on Reset for to ensure internal details Power-on Reset signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See section on Power-on Reset for to ensure internal details Power-on Reset signal D005 VBOR Brown-out Reset Voltage BORV<1:0> = 11(2) 1.72 1.82 1.95 V BORV<1:0> = 10 2.15 2.27 2.40 V BORV<1:0> = 01 2.65 2.75 2.90 V BORV<1:0> = 00(3) 2.98 3.08 3.25 V Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: With BOR enabled, operation is supported until a BOR occurs. This is valid although VDD may be below the minimum rated supply voltage. 3: With BOR enabled, full-speed operation (FOSC = 64 MHZ) is supported until a BOR occurs. This is valid although VDD may be below the minimum voltage for this frequency. TABLE 26-2: POWER-DOWN CURRENT, PIC18F2XK20/4XK20 PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D006 Power-down Current (IPD)(1) 0.05 1.0 A -40°C 0.05 1.0 A +25°C VDD = 1.8V, (Sleep mode) 0.6 3.0 A +85°C 4 20 A +125°C D007 0.1 1.0 A -40°C 0.1 1.0 A +25°C VDD = 3.0V, (Sleep mode) 0.7 3.0 A +85°C 5 20 A +125°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).  2010-2015 Microchip Technology Inc. DS40001303H-page 353

PIC18F2XK20/4XK20 TABLE 26-3: RC RUN SUPPLY CURRENT, PIC18F2XK20/4XK20 PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D008 Supply Current (IDD)(1, 2) 5.5 9 A -40°C 6.0 10 A +25°C VDD = 1.8V 6.5 14 A +85°C 9.0 30 A +125°C FOSC = 31kHz (RC_RUN mode, D008A 10.0 15 A -40°C LFINTOSC source) 10.5 16 A +25°C VDD = 3.0V 11.0 20 A +85°C 14.0 40 A +125°C D009 0.40 0.50 mA -40°C TO +125°C VDD = 1.8V FOSC = 1MHz (RC_RUN mode, D009A 0.60 0.80 mA -40°C TO +125°C VDD = 3.0V HF-INTOSC source) D010 2.2 3.0 mA -40°C TO +125°C VDD = 1.8V FOSC = 16MHz (RC_RUN mode, D010A 3.8 4.4 mA -40°C TO +125°C VDD = 3.0V HF-INTOSC source) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS40001303H-page 354  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 26-4: RC IDLE SUPPLY CURRENT, PIC18F2XK20/4XK20 PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D011 Supply Current (IDD)(1, 2) 2.0 5 A -40°C 2.0 5 A +25°C VDD = 1.8V 2.5 9 A +85°C 5.0 25 A +125°C FOSC = 31kHz (RC_IDLE mode, D011A 3.5 8 A -40°C LFINTOSC source) 3.5 8 A +25°C VDD = 3.0V 4.0 12 A +85°C 7.0 30 A +125°C D012 0.30 0.40 mA -40°C to +125°C VDD = 1.8V FOSC = 1MHz (RC_IDLE mode, D012A 0.40 0.60 mA -40°C to +125°C VDD = 3.0V HF-INTOSC source) D013 1.0 1.2 mA -40°C to +125°C VDD = 1.8V FOSC = 16MHz (RC_IDLE mode, D013A 1.6 2.0 mA -40°C to +125°C VDD = 3.0V HF-INTOSC source) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2010-2015 Microchip Technology Inc. DS40001303H-page 355

PIC18F2XK20/4XK20 TABLE 26-5: PRIMARY RUN SUPPLY CURRENT, PIC18F2XK20/4XK20 PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D014 Supply Current (IDD)(1, 2) 0.25 0.45 mA -40°C to +125°C VDD = 1.8V FOSC = 1MHz D014A (PRI_RUN, 0.50 0.75 mA -40°C to +125°C VDD = 3.0V EC oscillator) D015 2.7 3.2 mA -40°C to +125°C VDD = 2V FOSC = 20MHz (PRI_RUN, D015A 4.3 5.0 mA -40°C to +125°C VDD = 3.0V EC oscillator) D016 FOSC = 64MHz 12.2 14.0 mA -40°C to +85°C VDD = 3.0V (PRI_RUN, EC oscillator) D017 2.1 2.9 mA -40°C to +125°C VDD = 1.8V FOSC = 4MHz D017A 16MHz Internal 4.2 5.0 mA -40°C to +125°C VDD = 3.0V (PRI_RUN HS+PLL) D018 FOSC = 16MHz 12.2 15.0 mA -40°C to +85°C VDD = 3.0V 64MHz Internal (PRI_RUN HS+PLL) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). TABLE 26-6: PRIMARY IDLE SUPPLY CURRENT, PIC18F2XK20/4XK20 PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D019 Supply Current (IDD)(1, 2) 0.05 0.07 mA -40°C to +125°C VDD = 1.8V FOSC = 1MHz (PRI_IDLE mode, D019A 0.09 0.15 mA -40°C to +125°C VDD = 3.0V EC oscillator) D020 1.2 1.6 mA -40°C to +125°C VDD = 2.0V FOSC = 20MHz (PRI_IDLEmode, D020A 1.8 2.5 mA -40°C to +125°C VDD = 3.0V EC oscillator) D021 FOSC = 64MHz 5.6 7.0 mA -40°C to +85°C VDD = 3.0V (PRI_IDLEmode, EC oscillator) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS40001303H-page 356  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 26-7: SECONDARY OSCILLATOR SUPPLY CURRENT, PIC18F2XK20/4XK20 PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D022 Supply Current (IDD)(1, 2) 5.5 9 A -40°C 5.5 10 A +25°C VDD = 1.8V 6.5 14 A +85°C FOSC = 32kHz(3) (SEC_RUN mode, D022A 10.0 15 A -40°C Timer1 as clock) 10.0 16 A +25°C VDD = 3.0V 11.0 20 A +85°C D023 2.0 5 A -40°C 2.0 5 A +25°C VDD = 1.8V 2.5 9 A +85°C FOSC = 32kHz(3) (SEC_IDLE mode, D023A 3.5 8 A -40°C Timer1 as clock) 3.5 8 A +25°C VDD = 3.0V 4.0 12 A +85°C Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). 3: Low-Power mode on T1 osc. Low-Power mode is limited to 85°C.  2010-2015 Microchip Technology Inc. DS40001303H-page 357

PIC18F2XK20/4XK20 TABLE 26-8: PERIPHERAL SUPPLY CURRENT, PIC18F2XK20/4XK20 PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. Module Differential Currents D024 Watchdog Timer 0.7 2.0 A -40°C to +125°C VDD = 1.8V (IWDT) 1.1 3.0 A -40°C to +125°C VDD = 3.0V D024A Brown-out Reset(2) 21 50 A -40C to +125C VDD = 2.0V (IBOR) 25 60 A -40C to +125C VDD = 3.3V — Sleep mode, 0 A -40C to +125C VDD = 3.3V BOREN<1:0> = 10 D024B High/Low-Voltage Detect(2) 13 30 A -40C to +125C VDD = 1.8-3.0V (IHLVD) D025 Timer1 Oscillator 0.5 2.0 A -40C (IOSCB) 0.5 2.0 A +25C VDD = 1.8V 32kHz on Timer1(1) LP 0.7 2.0 A +85C 0.7 3.0 A -40C 0.7 3.0 A +25C VDD = 3.0V 32kHz on Timer1(1) 0.9 3.0 A +85C D025A Timer1 Oscillator 11 30 A -40C (IOSCB) 13 33 A +25C VDD = 1.8V 32kHz on Timer1(3) HP 15 35 A +85C 14 33 A -40C 17 37 A +25C VDD = 3.0V 32kHz on Timer1(3) 19 40 A +85C D026 A/D Converter(4) 200 360 A -40C to +125C VDD = 1.8V (IAD) 260 500 A -40C to +125C VDD = 3.0V A/D on, not converting IFRC 2 5 A -40C to +125C VDD = 1.8V Adder for FRC 11 18 A -40C to +125C VDD = 3.0V Note 1: Low-Power mode on T1 osc. Low-Power mode is limited to 85°C. 2: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 3: High-Power mode in T1 osc. 4: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the FRC turn off as soon as conversion (if any) is complete. DS40001303H-page 358  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 26-9: INPUT/OUTPUT CHARACTERISTICS, PIC18F2XK20/4XK20 DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Typ.† Max. Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS — 0.15 VDD V D031 with Schmitt Trigger VSS — 0.2 VDD V D032 MCLR VSS — 0.2 VDD V D033 OSC1 VSS — 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS — 0.2 VDD V RC, EC modes(1) D033B OSC1 VSS — 0.3 VDD V XT, LP modes D034 T13CKI VSS — 0.3 VDD V VIH Input High Voltage I/O ports: D040 with TTL buffer 0.25 VDD + — VDD V 0.8V D041 VIH with Schmitt Trigger: 0.8 VDD — VDD V 2.4V < VDD < 3.6V 0.9 VDD — VDD V VDD < 2.4V D042 VIH MCLR 0.8 VDD — VDD V 2.4V < VDD < 3.6V 0.9 VDD — VDD V VDD < 2.4V D043 OSC1 0.7 VDD — VDD V HS, HSPLL modes D043A OSC1 0.8 VDD — VDD V EC mode D043B OSC1 0.9 VDD — VDD V RC mode(1) D043C OSC1 1.6 — VDD V XT, LP modes D044 T13CKI 1.6 — VDD V IIL Input Leakage I/O and VSS VPIN VDD, MCLR(2,3) Pin at high-impedance D060 I/O ports — 5 50 nA +25°C — 10 100 nA +60°C — 30 200 nA +85°C — 100 1000 nA +125°C Input Leakage RA2 D061 IIL — 10 100 nA +25°C — 35 250 nA +60°C — 200 750 nA +85°C — 400 2000 nA +125°C Input Leakage RA3 D062 IIL — 10 80 nA +25°C — 25 200 nA +60°C — 70 500 nA +85°C — 300 1500 nA +125°C IPU Weak Pull-up Current Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested.  2010-2015 Microchip Technology Inc. DS40001303H-page 359

PIC18F2XK20/4XK20 TABLE 26-9: INPUT/OUTPUT CHARACTERISTICS, PIC18F2XK20/4XK20 (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Typ.† Max. Units Conditions No. D070 IPURB PORTB weak pull-up 50 90 400 A VDD = 3.0V, VPIN = current VSS Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. DS40001303H-page 360  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 26-9: INPUT/OUTPUT CHARACTERISTICS, PIC18F2XK20/4XK20 (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Typ.† Max. Units Conditions No. VOL Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 3.0V, -40C to +85C D083 OSC2/CLKOUT — — 0.6 V IOL = 1.6 mA, VDD (RC, RCIO, EC, ECIO = 3.0V, modes) -40C to +85C VOH Output High Voltage(3) D090 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 3.0V, -40C to +85C D092 OSC2/CLKOUT VDD – 0.7 — — V IOH = -1.3 mA, VDD (RC, RCIO, EC, ECIO = 3.0V, modes) -40C to +85C Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 — — 50 pF To meet the AC (in RC mode) Timing Specifications D102 CB SCL, SDA — — 400 pF I2C™ Specification Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested.  2010-2015 Microchip Technology Inc. DS40001303H-page 361

PIC18F2XK20/4XK20 TABLE 26-10: MEMORY PROGRAMMING REQUIREMENTS DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Min. Typ.† Max. Units Conditions No. Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP/RE3 pin VDD + 8 — 9 V (Note 3, Note 4) D113 IDDP Supply Current during — — 10 mA Programming Data EEPROM Memory D120 ED Byte Endurance 100K — — E/W -40C to +85C D121 VDRW VDD for Read/Write 1.8 — 3.6 V Using EECON to read/write D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +85°C Cycles before Refresh(2) Program Flash Memory D130 EP Cell Endurance 10K — — E/W -40C to +85C (Note 5) D131 VPR VDD for Read 1.8 — 3.6 V D132 VIW VDD for Row Erase or Write 2.2 — 3.6 V D133 TIW Self-timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2. 5: Self-write and Block Erase. DS40001303H-page 362  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 26.4 Analog Characteristics TABLE 26-11: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated). Param. Sym. Characteristics Min. Typ. Max. Units Comments No. CM01 VIOFF Input Offset Voltage — 10 50 mV VREF = VDD/2, High-Power mode — 12 80 mV VREF = VDD/2, Low-Power mode CM02 VICM Input Common-mode Voltage VSS — VDD V CM04 TRESP Response Time — 200 400 ns High-Power mode — 300 600 ns Low-Power mode CM05 TMC2OV Comparator Mode Change to — — 10 s Output Valid* * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. TABLE 26-12: CVREF VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated). Param. Sym. Characteristics Min. Typ. Max. Units Comments No. CV01* CLSB Step Size(2) — VDD/24 — V Low Range (VRR = 1) — VDD/32 — V High Range (VRR = 0) CV02* CACC Absolute Accuracy — — 1/2 LSb CV03* CR Unit Resistor Value (R) — 3k —  CV04* CST Settling Time(1) — 7.5 10 s * These parameters are characterized but not tested. Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. 2: See Section21.1 “Comparator Voltage Reference” for more information. TABLE 26-13: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Operating Conditions: 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated). VR Voltage Reference Specifications Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristics Min. Typ. Max. Units Comments No. VR01 VROUT VR voltage output 1.15 1.20 1.25 V -40°C to +85°C 1.10 1.20 1.30 V +85°C to +125°C VR02* TCVOUT Voltage drift temperature — <50 — ppm/C -40°C to +40°C (See coefficient Figure27-34) VR03* VROUT/ Voltage drift with respect to — <2000 — V/V 25°C, 2.0 to 3.3V (See VDD VDD regulation Figure27-33) VR04* TSTABLE Settling Time — 25 100 s 0 to 125°C * These parameters are characterized but not tested.  2010-2015 Microchip Technology Inc. DS40001303H-page 363

PIC18F2XK20/4XK20 FIGURE 26-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be VHLVD cleared by software) (HLVDIF set by hardware) HLVDIF TABLE 26-14: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Typ.† Max. Units Conditions No. D420 HLVD Voltage on HLVDL<3:0> = 0000 1.70 1.85 2.00 V VDD Transition HLVDL<3:0> = 0001 1.80 1.95 2.10 V High-to-Low HLVDL<3:0> = 0010 1.91 2.06 2.21 V HLVDL<3:0> = 0011 2.02 2.17 2.32 V HLVDL<3:0> = 0100 2.15 2.30 2.45 V HLVDL<3:0> = 0101 2.22 2.37 2.52 V HLVDL<3:0> = 0110 2.38 2.53 2.68 V HLVDL<3:0> = 0111 2.46 2.61 2.76 V HLVDL<3:0> = 1000 2.55 2.70 2.85 V HLVDL<3:0> = 1001 2.65 2.80 2.95 V HLVDL<3:0> = 1010 2.75 2.90 3.05 V HLVDL<3:0> = 1011 2.87 3.02 3.17 V HLVDL<3:0> = 1100 2.98 3.13 3.28 V HLVDL<3:0> = 1101 3.26 3.41 3.56 V HLVDL<3:0> = 1110 3.42 3.57 3.72 V † Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization. DS40001303H-page 364  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 26-15: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance Junction to 60.0 C/W 28-pin SPDIP package Ambient 80.3 C/W 28-pin SOIC package 90.0 C/W 28-pin SSOP package 36.0 C/W 28-pin QFN 6x6 mm package 48.0 C/W 28-pin UQFN 4x4 mm package 47.2 C/W 40-pin PDIP package 46.0 C/W 44-pin TQFP package 24.4 C/W 44-pin QFN package 41.0 C/W 40-pin UQFN 5x5 mm package TH02 JC Thermal Resistance Junction to 31.4 C/W 28-pin SPDIP package Case 24.0 C/W 28-pin SOIC package 24.0 C/W 28-pin SSOP package 6.0 C/W 28-pin QFN 6x6 mm package 12.0 C/W 28-pin UQFN 4x4 mm package 24.7 C/W 40-pin PDIP package 14.5 C/W 44-pin TQFP package 20.0 C/W 44-pin QFN package 50.5 C/W 40-pin UQFN 5x5 mm package TH03 TJMAX Maximum Junction Temperature 150 C — TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD X VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =(IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature, TJ = Junction Temperature  2010-2015 Microchip Technology Inc. DS40001303H-page 365

PIC18F2XK20/4XK20 26.5 AC (Timing) Characteristics 26.5.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C™ specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS40001303H-page 366  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 26.5.2 TIMING CONDITIONS The temperature and voltages specified in Table26-16 apply to all timing specifications unless otherwise noted. Figure26-4 specifies the load conditions for the timing specifications. TABLE 26-16: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section 26-1 and Section 26-9. FIGURE 26-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKOUT and including D and E outputs as ports 26.5.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT  2010-2015 Microchip Technology Inc. DS40001303H-page 367

PIC18F2XK20/4XK20 TABLE 26-17: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 1A FOSC External CLKIN DC 48 MHz EC, ECIO Oscillator mode, Frequency(1) (Extended Range Devices) DC 64 MHz EC, ECIO Oscillator mode, (Industrial Range Devices) Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 25 MHz HS Oscillator mode 4 16 MHz HS + PLL Oscillator mode, (Industrial Range Devices) 4 12 MHz HS + PLL Oscillator mode, (Extended Range Devices) 5 200 kHz LP Oscillator mode 1 TOSC External CLKIN Period(1) 20.8 — ns EC, ECIO, Oscillator mode (Extended Range Devices) 15.6 — ns EC, ECIO, Oscillator mode, (Industrial Range Devices) Oscillator Period(1) 250 — ns RC Oscillator mode 250 10,000 ns XT Oscillator mode 40 250 ns HS Oscillator mode 62.5 250 ns HS + PLL Oscillator mode, (Industrial range devices) 83.3 250 ns HS + PLL Oscillator mode, (Extended Range Devices) 5 200 s LP Oscillator mode 2 TCY Instruction Cycle Time(1) 62.5 — ns TCY = 4/FOSC 3 TOSL, External Clock in (OSC1) 30 — ns XT Oscillator mode TOSH High or Low Time 2.5 — s LP Oscillator mode 10 — ns HS Oscillator mode 4 TOSR, External Clock in (OSC1) — 20 ns XT Oscillator mode TOSF Rise or Fall Time — 50 ns LP Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS40001303H-page 368  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 26-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 3.6V) Param. Sym. Characteristic Min. Typ.† Max. Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 4 MHz VDD = 1.8-2.0V 4 — 5 MHz VDD = 2.0-3.0V 4 — 16 MHz VDD = 3.0-3.6V, Industrial Range Devices 4 — 12 MHz VDD = 3.0-3.6V, Extended Range Devices F11 FSYS On-Chip VCO System Frequency 16 — 16 MHz VDD = 1.8-2.0V 16 — 20 MHz VDD = 2.0-3.0V 16 — 64 MHz VDD = 3.0-3.6V, Industrial Range Devices 16 — 48 MHz VDD = 3.0-3.6V, Extended Range Devices F12 t PLL Start-up Time (Lock Time) — — 2 ms rc F13 CLK CLKOUT Stability (Jitter) -2 — +2 % TABLE 26-19: INTERNAL OSCILLATORS ACCURACY, PIC18F2XK20/4XK20 PIC18F2XK20/4XK20 Standard Operating Conditions (unless otherwise stated) Param. Characteristic Min. Typ. Max. Units Conditions No. OA1 HFINTOSC Accuracy @ Freq = 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz(1) -2 0 +2 % +0°C to +70°C VDD = 1.8-3.6V -3 — +2 % +70°C to +85°C VDD = 1.8-3.6V -5 — +5 % -40°C to 0°C and VDD = 1.8-3.6V +85°C to 125°C OA2 LFINTOSC Accuracy @ Freq = 31.25 kHz -15 — +15 % -40°C to +125°C VDD = 1.8-3.6V Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.  2010-2015 Microchip Technology Inc. DS40001303H-page 369

PIC18F2XK20/4XK20 FIGURE 26-6: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure26-4 for load conditions. TABLE 26-20: CLKOUT AND I/O TIMING REQUIREMENTS Param. Unit Condition Symbol Characteristic Min. Typ. Max. No. s s 10 TosH2ckL OSC1  to CLKOUT  — 75 200 ns (Note 1) 11 TosH2ck OSC1  to CLKOUT  — 75 200 ns (Note 1) H 12 TckR CLKOUT Rise Time — 35 100 ns (Note 1) 13 TckF CLKOUT Fall Time — 35 100 ns (Note 1) 14 TckL2ioV CLKOUT  to Port Out Valid — — 0.5 TCY + ns (Note 1) 20 15 TioV2ckH Port In Valid before CLKOUT  0.25 TCY + — — ns (Note 1) 25 16 TckH2ioI Port In Hold after CLKOUT  0 — — ns (Note 1) 17 TosH2ioV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns 18 TosH2ioI OSC1  (Q2 cycle) to Port Input Invalid 100 — — ns (I/O in hold time) 19 TioV2osH Port Input Valid to OSC1 (I/O in setup 0 — — ns time) 20 TioR Port Output Rise Time — 10 25 ns 21 TioF Port Output Fall Time — 10 25 ns 22† TINP INTx pin High or Low Time 20 — — ns 23† TRBP RB<7:4> Change KBIx High or Low Time TCY — — ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC. DS40001303H-page 370  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 26-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure26-4 for load conditions. FIGURE 26-8: BROWN-OUT RESET TIMING VDD BVDD 35 VBGAP = 1.2V VIVRST Enable Internal Reference Voltage Internal Reference Voltage Stable 36  2010-2015 Microchip Technology Inc. DS40001303H-page 371

PIC18F2XK20/4XK20 TABLE 26-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — s 31 TWDT Watchdog Timer Time-out Period 3.5 4.1 4.7 ms 1:1 prescaler (no postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 54.8 64.4 74.1 ms 34 TIOZ I/O High-Impedance from MCLR — 2 — s Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — s VDD  BVDD (see D005) 36 TIVRST Internal Reference Voltage Stable — 25 35 s 37 THLVD High/Low-Voltage Detect Pulse 200 — — s VDD  VHLVD Width 38 TCSD CPU Start-up Time 5 — 10 s 39 TIOBST Time for HF-INTOSC to Stabilize — 0.25 1 ms FIGURE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure26-4 for load conditions. DS40001303H-page 372  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 26-22: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param . Symbol Characteristic Min. Max. Units Conditions No. 40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 Tt0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 Tt1H T13CKI Synchronous, no prescaler 0.5 TCY + 20 — ns High Time Synchronous, 10 — ns with prescaler Asynchronous 30 — ns 46 Tt1L T13CKI Synchronous, no prescaler 0.5 TCY + 5 — ns Low Time Synchronous, 10 — ns with prescaler Asynchronous 30 — ns 47 Tt1P T13CKI Synchronous Greater of: — ns N = prescale Input Period 20ns or value (1, 2, 4, 8) (TCY + 40)/N Asynchronous 60 — ns Ft1 T13CKI Clock Input Frequency Range DC 50 kHz 48 Tcke2tmrI Delay from External T13CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment FIGURE 26-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure26-4 for load conditions.  2010-2015 Microchip Technology Inc. DS40001303H-page 373

PIC18F2XK20/4XK20 TABLE 26-23: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param. Symbol Characteristic Min. Max. Units Conditions No. 50 TccL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With 10 — ns prescaler 51 TccH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With 10 — ns prescaler 52 TccP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TccR CCPx Output Fall Time — 25 ns 54 TccF CCPx Output Fall Time — 25 ns FIGURE 26-11: PARALLEL SLAVE PORT TIMING (PIC18F4XK20) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure26-4 for load conditions. TABLE 26-24: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4XK20) Param. Symbol Characteristic Min. Max. Units Conditions No. 62 TdtV2wrH Data In Valid before WR  or CS  20 — ns (setup time) 63 TwrH2dtI WR  or CS  to Data–In Invalid (hold time) 20 — ns 64 TrdL2dtV RD  and CS  to Data–Out Valid — 80 ns 65 TrdH2dtI RD  or CS  to Data–Out Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being cleared from — 3 TCY WR  or CS  DS40001303H-page 374  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 26-12: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure26-4 for load conditions. TABLE 26-25: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param. Symbol Characteristic Min. Max. Units Conditions No. 70 TssL2scH, SS  to SCK  or SCK  Input TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns (Slave mode) 72A Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 100 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2) of Byte 2 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 100 — ns TscL2diL 75 TdoR SDO Data Output Rise Time — 25 ns 76 TdoF SDO Data Output Fall Time — 25 ns 78 TscR SCK Output Rise Time — 25 ns (Master mode) 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after SCK Edge — 50 ns TscL2doV Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used.  2010-2015 Microchip Technology Inc. DS40001303H-page 375

PIC18F2XK20/4XK20 FIGURE 26-13: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure26-4 for load conditions. TABLE 26-26: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min. Max. Units Conditions No. 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 100 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2) of Byte 2 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 100 — ns TscL2diL 75 TdoR SDO Data Output Rise Time — 25 ns 76 TdoF SDO Data Output Fall Time — 25 ns 78 TscR SCK Output Rise Time — 25 ns (Master mode) 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after SCK Edge — 50 ns TscL2doV 81 TdoV2scH, SDO Data Output Setup to SCK Edge TCY — ns TdoV2scL Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS40001303H-page 376  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 26-14: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure26-4 for load conditions. TABLE 26-27: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param. Symbol Characteristic Min. Max. Units Conditions No. 70 TssL2scH, SS  to SCK  or SCK  Input TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 100 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of 1.5 TCY + 40 — ns (Note 2) Byte 2 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 100 — ns TscL2diL 75 TdoR SDO Data Output Rise Time — 25 ns 76 TdoF SDO Data Output Fall Time — 25 ns 77 TssH2doZ SS to SDO Output High-Impedance 10 50 ns 78 TscR SCK Output Rise Time (Master mode) — 25 ns 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after SCK Edge — 50 ns TscL2doV 83 TscH2ssH, SS  after SCK edge 1.5 TCY + 40 — ns TscL2ssH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used.  2010-2015 Microchip Technology Inc. DS40001303H-page 377

PIC18F2XK20/4XK20 FIGURE 26-15: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure26-4 for load conditions. TABLE 26-28: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param. Symbol Characteristic Min. Max. Units Conditions No. 70 TssL2scH, SS  to SCK  or SCK  Input TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 1.25 TCY + — ns (Slave mode) 30 71A Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + — ns (Slave mode) 30 72A Single Byte 40 — ns (Note 1) 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of 1.5 TCY + 40 — ns (Note 2) Byte 2 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 100 — ns TscL2diL 75 TdoR SDO Data Output Rise Time — 25 ns 76 TdoF SDO Data Output Fall Time — 25 ns 77 TssH2doZ SS to SDO Output High-Impedance 10 50 ns 78 TscR SCK Output Rise Time — 25 ns (Master mode) 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after SCK Edge — 50 ns TscL2doV 82 TssL2doV SDO Data Output Valid after SS  Edge — 50 ns Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS40001303H-page 378  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 26-28: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) (CONTINUED) Param. Symbol Characteristic Min. Max. Units Conditions No. 83 TscH2ssH, SS  after SCK Edge 1.5 TCY + 40 — ns TscL2ssH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. FIGURE 26-16: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure26-4 for load conditions. TABLE 26-29: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min. Max. Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 —  2010-2015 Microchip Technology Inc. DS40001303H-page 379

PIC18F2XK20/4XK20 FIGURE 26-17: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure26-4 for load conditions. DS40001303H-page 380  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 26-30: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min. Max. Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s PIC18FXXXX must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — s PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s PIC18FXXXX must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 102 TR SDA and SCL Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 91 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time 400 kHz mode 0.6 — s clock pulse is generated 106 THD:DAT Data Input Hold 100 kHz mode 0 — ns Time 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup 100 kHz mode 250 — ns (Note 2) Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 109 TAA Output Valid from 100 kHz mode — 3500 ns (Note 1) Clock 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT=1000+250=1250ns (according to the standard mode I2C bus specification), before the SCL line is released.  2010-2015 Microchip Technology Inc. DS40001303H-page 381

PIC18F2XK20/4XK20 FIGURE 26-18: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure26-4 for load conditions. TABLE 26-31: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins. FIGURE 26-19: MASTER SSP I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure26-4 for load conditions. DS40001303H-page 382  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 26-32: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free before a new 400 kHz mode 1.3 — ms transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter 107250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter 102 + parameter 107=1000+250=1250ns (for 100 kHz mode), before the SCL line is released.  2010-2015 Microchip Technology Inc. DS40001303H-page 383

PIC18F2XK20/4XK20 FIGURE 26-20: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure26-4 for load conditions. TABLE 26-33: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid — 40 ns 121 Tckrf Clock Out Rise Time and Fall Time — 20 ns (Master mode) 122 Tdtrf Data Out Rise Time and Fall Time — 20 ns FIGURE 26-21: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure26-4 for load conditions. TABLE 26-34: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 125 TdtV2ckl SYNC RCV (MASTER & SLAVE) Data Setup before CK  (DT setup time) 10 — ns 126 TckL2dtl Data Hold after CK  (DT hold time) 15 — ns DS40001303H-page 384  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 TABLE 26-35: A/D CONVERTER CHARACTERISTICS:PIC18F2XK20/4XK20 Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. A01 NR Resolution — — 10 bits -40°C to +85°C, VREF  2.0V A03 EIL Integral Linearity Error — ±0.5 ±1 LSb -40°C to +85°C, VREF  2.0V A04 EDL Differential Linearity Error — ±0.4 ±1 LSb -40°C to +85°C, VREF  2.0V A06 EOFF Offset Error — 0.4 ±2 LSb -40°C to +85°C, VREF  2.0V A07 EGN Gain Error — 0.3 ±2 LSb -40°C to +85°C, VREF  2.0V A08 ETOTL Total Error — 1 ±3 LSb -40°C to +85°C, VREF  2.0V A20 VREF Reference Voltage Range 1.8 — — V ABsolute Minimum (VREFH – VREFL) 2.0 — — V Minimum for 1LSb Accuracy A21 VREFH Reference Voltage High VDD/2 — VDD + 0.3 V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD/2 V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 3 k -40°C to +85°C Analog Voltage Source Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.  2010-2015 Microchip Technology Inc. DS40001303H-page 385

PIC18F2XK20/4XK20 FIGURE 26-22: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 .. . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 26-36: A/D CONVERSION REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 130 TAD A/D Clock Period 0.7 25.0(1) s TOSC based, -40C to +85C 0.7 4.0(1) s TOSC based, +85C to +125C 1.0 4.0 s FRC mode, VDD2.0V 131 TCNV Conversion Time 12 12 TAD (not including acquisition time) (Note 2) 132 TACQ Acquisition Time (Note 3) 1.4 — s VDD = 3V, Rs = 50 135 TSWC Switching Time from Convert  Sample — (Note 4) 136 TDIS Discharge Time 2 2 TAD Legend: TBD = To Be Determined Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES register may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (Rs) on the input channels is 50 4: On the following cycle of the device clock. DS40001303H-page 386  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 27.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FIGURE 27-1: PIC18F4XK20/PIC18F2XK20 TYPICAL BASE IPD 10 125°C 1 85°C A) u (D P I 0.1 40°C Limited Accuracy 25°C -40°C 0.01 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-2: PIC184XK20/PIC18F2XK20 MAXIMUM BASE IPD 100 125°C uA) 10 (D P I 85°C 40°C 1 25°C 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V)  2010-2015 Microchip Technology Inc. DS40001303H-page 387

PIC18F2XK20/4XK20 FIGURE 27-3: PIC18F4XK20/PIC18F2XK20 TYPICAL RC_RUN 31 kHz IDD 16 14 125°C 12 85°C 25°C uA) 10 -40°C (D D I 8 6 4 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-4: PIC18F4XK20/PIC18F2XK20 MAXIMUM RC_RUN 31 kHz IDD 45 125°C 40 35 30 uA) 25 (D D I 20 85°C 25°C 15 -40°C 10 5 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) DS40001303H-page 388  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 27-5: PIC18F4XK20/PIC18F2XK20 TYPICAL RC_RUN IDD 5.0 4.5 4.0 16 MHz 3.5 3.0 A) 2.5 m 8 MHz (D ID 2.0 1.5 4 M Hz 1.0 1 MHz 0.5 0.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-6: PIC18F4XK20/PIC18F2XK20 MAXIMUM RC_RUN IDD 6 5 16 MHz 4 A) m 3 8 MHz (D D I 2 4 MHz 1 1 MHz 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V)  2010-2015 Microchip Technology Inc. DS40001303H-page 389

PIC18F2XK20/4XK20 FIGURE 27-7: PIC18F4XK20/PIC18F2XK20 TYPICAL RC_IDLE 31 kHz IDD 7 125°C 6 5 uA) 4 85°C (D D 25°C I -40°C 3 2 1 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-8: PIC18F4XK20/PIC18F2XK20 MAXIMUM RC_IDLE 31 kHz IDD 35 125°C 30 25 20 A) u (DD 15 I 85°C 10 25°C -40°C 5 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) DS40001303H-page 390  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 27-9: PIC18F4XK20/PIC18F2XK20 TYPICAL RC_IDLE IDD 2.5 2.0 16 MHz 1.5 A) m (DD 8 MHz I 1.0 4 MHz 0.5 1 MHz 0.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-10: PIC18F4XK20/PIC18F2XK20 MAXIMUM RC_IDLE IDD 3.0 2.5 16 MHz 2.0 A) m 1.5 (D D 8 MHz I 1.0 4 MHz 1 MHz 0.5 0.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V)  2010-2015 Microchip Technology Inc. DS40001303H-page 391

PIC18F2XK20/4XK20 FIGURE 27-11: PIC18F4XK20/PIC18F2XK20 TYPICAL PRI_RUN IDD (EC) 16 14 64 MHz 12 10 mA) 8 40 MHz (D D I 6 20 MHz 4 16 MHz 10 MHz 2 4 MHz 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-12: PIC18F4XK20/PIC18F2XK20 MAXIMUM PRI_RUN IDD (EC) 18 16 64 MHz 14 12 10 40 MHz A) m (D 8 D I 6 20 MHz 16 MHz 4 10 MHz 2 4 MHz 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) DS40001303H-page 392  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 27-13: PIC18F4XK20/PIC18F2XK20 TYPICAL PRI_RUN IDD (HS + PLL) 16 14 64 MHz 12 (16 MHz Input) 10 40 MHz mA) 8 (10 MHz Input) (D D I 6 4 16 MHz (4 MHz Input) 2 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-14: PIC18F4XK20/PIC18F2XK20 MAXIMUM PRI_RUN IDD (HS + PLL) 20 18 16 64 MHz (16 MHz Input) 14 12 40 MHz mA) 10 (10 MHz Input) (D D I 8 6 16 MHz 4 (4 MHz Input) 2 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V)  2010-2015 Microchip Technology Inc. DS40001303H-page 393

PIC18F2XK20/4XK20 FIGURE 27-15: PIC18F4XK20/PIC18F2XK20 TYPICAL PRI_IDLE IDD (EC) 7 6 64 MHz 5 4 A) 40 MHz m (DD 3 I 2 20 MHz 16 MHz 1 10 MHz 4 MHz 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-16: PIC18F4XK20/PIC18F2XK20 MAXIMUM PRI_IDLE IDD (EC) 9 8 64 MHz 7 6 5 A) m 40 MHz (D 4 D I 3 20 MHz 2 16 MHz 10 MHz 1 4 MHz 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) DS40001303H-page 394  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 27-17: PIC18F4XK20/PIC18F2XK20 IWDT – Delta IPD for Watchdog Timer, -40°C to +125°C 4.0 3.5 Max. 3.0 2.5 A) u 2.0 (D P I 1.5 Typ. 1.0 0.5 0.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-18: PIC18F4XK20/PIC18F2XK20 IBOR and IHLVD – Delta IPD for Brown-out Reset and High/Low Voltage Detect, -40°C to +125°C 70 60 Max. BOR 50 40 A) u (D P 30 Max. HLVD I Typ. BOR 20 Typ. HLVD 10 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V)  2010-2015 Microchip Technology Inc. DS40001303H-page 395

PIC18F2XK20/4XK20 FIGURE 27-19: PIC18F4XK20/PIC18F2XK20 IOCSB – Delta IPD for Low-Power Timer1 Oscillator 3.5 3.0 Max. -40°C to +85°C 2.5 2.0 A) u (D IP 1.5 1.0 Typ. 85°C Typ. 25°C 0.5 0.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-20: PIC18F4XK20/PIC18F2XK20 IOCSB – Typical Delta IPD for High-Power Timer1 Oscillator 20 85°C 18 25°C 16 A) u (D P I 14 -40°C 12 10 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) DS40001303H-page 396  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 27-21: PIC18F4XK20/PIC18F2XK20 IOCSB – Maximum Delta IPD for High-Power Timer1 Oscillator 42 40 85°C 38 25°C 36 A) u (D IP 34 -40°C 32 30 28 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-22: PIC18F4XK20/PIC18F2XK20 ICVREF – Delta IPD for Comparator Voltage Reference, -40°C to +125°C 80 70 Max. 60 50 A) (uD 40 IP Typ. 30 20 10 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V)  2010-2015 Microchip Technology Inc. DS40001303H-page 397

PIC18F2XK20/4XK20 FIGURE 27-23: PIC18F4XK20/PIC18F2XK20 IAD – Typical Delta IDD for ADC, 25°C to +125°C (Run Mode, ADC on, but not converting) 340 320 125°C 300 85°C 280 A) 25°C (uD 260 D I 240 220 200 180 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-24: PIC18F4XK20/PIC18F2XK20 IAD – Maximum Delta IDD for ADC, 25°C to +125°C (Run Mode, ADC on, but not converting) 440 125°C 420 85°C 400 380 25°C 360 A) 340 u (D 320 D I 300 280 260 240 220 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) DS40001303H-page 398  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 27-25: PIC18F4XK20/PIC18F2XK20 ICOMP – Typical Delta IPD for Comparator in Low- Power Mode, -40°C to +125°C 7.0 125°C 6.5 85°C 6.0 5.5 uA) 25°C (D IP 5.0 4.5 -40°C 4.0 3.5 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-26: PIC18F4XK20/PIC18F2XK20 ICOMP – Maximum Delta IPD for Comparator in Low-Power Mode, -40°C to +125°C 16 125°C 15 85°C 14 A) 25°C u 13 (D P I 12 -40°C 11 10 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V)  2010-2015 Microchip Technology Inc. DS40001303H-page 399

PIC18F2XK20/4XK20 FIGURE 27-27: PIC18F4XK20/PIC18F2XK20 ICOMP – Typical Delta IPD for Comparator in High- Power Mode, -40°C to +125°C 55 50 125°C 85°C 45 A) u (D 25°C P I 40 35 -40°C 30 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-28: PIC18F4XK20/PIC18F2XK20 ICOMP – Maximum Delta IPD for Comparator in High-Power Mode, -40°C to +125°C 95 125°C 90 85 85°C 80 uA) 25°C (D P 75 I 70 -40°C 65 60 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) DS40001303H-page 400  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 27-29: PIC18F4XK20/PIC18F2XK20 COMPARATOR OFFSET (LOW POWER, VDD = 1.8V) 70 60 -40°C 3 sigma 50 V) 25°C 3 sigma m set ( 40 85°C 3 sigma bs. Off 125°C 3 sigma A 30 Typical 20 10 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VREF (V) FIGURE 27-30: PIC18F4XK20/PIC18F2XK20 COMPARATOR OFFSET (LOW POWER, VDD = 3.6V) 70 -40°C 3 sigma 60 50 2 5°C 3 sig m a V) ma Abs. Offset (m 3400 85°1C2 53° sCiT g3 ysipgicmaal 20 10 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 VREF (V)  2010-2015 Microchip Technology Inc. DS40001303H-page 401

PIC18F2XK20/4XK20 FIGURE 27-31: PIC18F4XK20/PIC18F2XK20 COMPARATOR OFFSET (HIGH POWER, VDD = 1.8V) 45 40 35 -40°C 3 sigma 25°C 3 sigma 30 et (mV) 25 85°C 3 sigm1a25°C 3 sigma s Off s. 20 b A Typical 15 10 5 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VREF (V) FIGURE 27-32: PIC18F4XK20/PIC18F2XK20 COMPARATOR OFFSET (HIGH POWER, VDD = 3.6V) 45 -40°C 3 sigma 40 35 25°C 3 sigma set (mV) 2350 8152°5C° C3 3 sisiggmmaa Off bs. 20 Typical A 15 10 5 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 VREF (V) DS40001303H-page 402  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 27-33: PIC18F4XK20/PIC18F2XK20 TYPICAL FIXED VOLTAGE REFERENCE 1.205 1.200 25°C -40°C 85°C 1.195 V) R ( 1.190 V F 1.185 125°C 1.180 1.175 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-34: PIC18F4XK20/PIC18F2XK20 TYPICAL FIXED VOLTAGE REFERENCE (MAX./MIN. = 1.2V +/- 50MV FROM -40°C TO +85°C) 1.205 1.200 3.6V 2.0V 1.195 V) R ( 1.190 V 1.8V F 1.185 1.180 1.175 -40 -20 0 20 40 60 80 100 120 Temp. (°C)  2010-2015 Microchip Technology Inc. DS40001303H-page 403

PIC18F2XK20/4XK20 FIGURE 27-35: PIC18F4XK20/PIC18F2XK20 TTL BUFFER VIH 1.8 Min. 1.6 1.4 1.2 V) (H -40°C VI 25°C 1.0 85°C 125°C 0.8 0.6 0.4 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) FIGURE 27-36: PIC18F4XK20/PIC18F2XK20 SCHMITT TRIGGER BUFFER VIH 3.0 2.8 Min. 2.6 2.4 2.2 V (V)IH 2.0 8-450°C°C25°C125°C 1.8 1.6 1.4 1.2 1.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) DS40001303H-page 404  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 27-37: PIC18F4XK20/PIC18F2XK20 TTL BUFFER VIL 1.2 -40°C 1.0 25°C 85°C 125°C 0.8 V) (L 0.6 VI Max. 0.4 0.2 0.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) FIGURE 27-38: PIC18F4XK20/PIC18F2XK20 SCHMITT TRIGGER BUFFER VIL 1.6 1.4 -40°C25°C 85°C 125°C 1.2 1.0 V) (L VI 0.8 Max. 0.6 0.4 0.2 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V)  2010-2015 Microchip Technology Inc. DS40001303H-page 405

PIC18F2XK20/4XK20 FIGURE 27-39: PIC18F4XK20/PIC18F2XK20 VOH VS. IOH (-40°C TO +125°C) 3.6 3 2.4 Typ. 3.0V V) 1.8 (H Typ. 3.6V O V Min. 3.0V 1.2 Typ. 1.8V 0.6 Min. 3.6V Min. 1.8V 0 0 5 10 15 20 25 IOH (mA) FIGURE 27-40: PIC18F4XK20/PIC18F2XK20 VOL VS. IOL (-40°C TO +125°C) 1.8 Max. 1.8V Max. 3.0V 1.5 Max. 3.6V 1.2 V) 0.9 (L O V 0.6 1.8V 3.0V 3.6V 0.3 0 0 5 10 15 20 25 IOL (mA) DS40001303H-page 406  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 27-41: PIC18F4XK20/PIC18F2XK20 PIN INPUT LEAKAGE 1000 RA2 Max. RA3 Max. I/O Ports Max. 100 A) RA2 Typ. n e ( RA3 Typ. g a k a e L I/O Ports Typ. ut p n I 10 1 25 30 35 40 45 50 55 60 65 70 75 80 85 Temp. (°C)  2010-2015 Microchip Technology Inc. DS40001303H-page 407

PIC18F2XK20/4XK20 FIGURE 27-42: PIC18F4XK20/PIC18F2XK20 TYPICAL HF-INTOSC FREQUENCY 16.08 16.00 25°C z) 15.92 H M 85°C y ( c n e equ 15.84 -40°C Fr 15.76 125°C 15.68 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-43: PIC18F4XK20/PIC18F2XK20 TYPICAL HF-INTOSC FREQUENCY 16.80 16.64 16.48 16.32 Max z) 16.16 H M cy ( 16.00 3.0V n e u eq 15.84 Fr 15.68 Min 15.52 15.36 15.20 -40 -20 0 20 40 60 80 100 120 Temp. (°C) DS40001303H-page 408  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 FIGURE 27-44: PIC18F4XK20/PIC18F2XK20 TYPICAL LF-INTOSC FREQUENCY (MAX./MIN. = 31.25 kHz +/-15%) 33.25 32.25 Hz) 31.25 25°C k y ( nc -40°C e u eq 30.25 85°C Fr 29.25 125°C 28.25 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 27-45: PIC18F4XK20/PIC18F2XK20 TYPICAL LF-INTOSC FREQUENCY (MAX./MIN. = 31.25 kHz +/-15%) 33.25 32.25 1.8V z) 31.25 H 2.5V k y ( nc 3.6V 3.0V e u eq 30.25 Fr 29.25 28.25 -40 -20 0 20 40 60 80 100 120 Temp. (°C)  2010-2015 Microchip Technology Inc. DS40001303H-page 409

PIC18F2XK20/4XK20 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC18F25K20 -E/SP e3 1519017 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX PIC18F25K20 XXXXXXXXXXXXXXXXXXXX -E/SO e3 YYWWNNN 1519017 28-Lead SSOP (5.30 mm) Example PIC18F25K20 -E/SS e3 1519017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC® designator e( 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS40001303H-page 410  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 XXXXXXXX 18F24K20 XXXXXXXX -E/ML e3 YYWWNNN 1519017 28-Lead UQFN (4x4x0.5 mm) Example PIC18 PIN 1 PIN 1 F23K20 -E/MV e3 519017 40-Lead PDIP (600 mil) Example XXXXXXXXXXXXXXXXXX PIC18F45K20 XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX -E/Pe3 YYWWNNN 1519017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC® designator e( 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2015 Microchip Technology Inc. DS40001303H-page 411

PIC18F2XK20/4XK20 Package Marking Information (Continued) 40-Lead UQFN (5x5x0.5 mm) Example PIN 1 PIN 1 PIC18F 45K20 -I/MV e3 1519017 44-Lead QFN (8x8x0.9 mm) Example PIN 1 PIN 1 XXXXXXXXXXX PIC18F45K20 XXXXXXXXXXX -E/ML XXXXXXXXXXX 1519017 YYWWNNN 44-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX PIC18F44K20 XXXXXXXXXX -E/PT YYWWNNN 1519017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC® designator e( 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS40001303H-page 412  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 28.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)(cid:26)(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1  2010-2015 Microchip Technology Inc. DS40001303H-page 413

PIC18F2XK20/4XK20 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001303H-page 414  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001303H-page 415

PIC18F2XK20/4XK20 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001303H-page 416  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)#$(cid:12)(cid:13)(cid:11)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)%(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:10)(cid:24)(cid:9)(cid:25)(cid:9)&’(cid:26)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:10)%(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:30)(cid:4)(cid:20)(cid:3)(cid:4) (cid:30)(cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)-1  2010-2015 Microchip Technology Inc. DS40001303H-page 417

PIC18F2XK20/4XK20 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001303H-page 418  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20  2010-2015 Microchip Technology Inc. DS40001303H-page 419

PIC18F2XK20/4XK20 DS40001303H-page 420  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)((cid:21)(cid:7)(cid:8)(cid:9))(cid:16)(cid:7)(cid:18)*(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)+(cid:6)(cid:9)(cid:23),(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)-.-(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)()! /(cid:12)(cid:18)#(cid:9)(cid:27)’&&(cid:9)(cid:28)(cid:28)(cid:9)0(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13)+(cid:18)# !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2010-2015 Microchip Technology Inc. DS40001303H-page 421

PIC18F2XK20/4XK20 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001303H-page 422  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001303H-page 423

PIC18F2XK20/4XK20 DS40001303H-page 424  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 1(cid:27)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)-(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c b1 A1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:29) = (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:29)(cid:24)(cid:4) = (cid:20)?(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:23)<(cid:29) = (cid:20)(cid:29)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)(cid:24)<(cid:4) = (cid:3)(cid:20)(cid:4)(cid:24)(cid:29) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) = (cid:20)(cid:3)(cid:4)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< = (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)-(cid:4) = (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) = (cid:20)(cid:4)(cid:3)- : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:5)(cid:4)(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)?1  2010-2015 Microchip Technology Inc. DS40001303H-page 425

PIC18F2XK20/4XK20 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001303H-page 426  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001303H-page 427

PIC18F2XK20/4XK20 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001303H-page 428  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20  2010-2015 Microchip Technology Inc. DS40001303H-page 429

PIC18F2XK20/4XK20 DS40001303H-page 430  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20  2010-2015 Microchip Technology Inc. DS40001303H-page 431

PIC18F2XK20/4XK20 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A D1 B NOTE 2 (DATUM A) (DATUM B) E1 E A A NOTE 1 2X N 0.20 H A B 2X 1 2 3 0.20 H A B TOP VIEW 4X 11 TIPS 0.20 C A B A A2 C SEATING PLANE 0.10 C A1 SIDE VIEW 1 2 3 N NOTE 1 44 X b 0.20 C A B e BOTTOM VIEW Microchip Technology Drawing C04-076C Sheet 1 of 2 DS40001303H-page 432  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging H c θ L (L1) SECTION A-A Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 44 Lead Pitch e 0.80 BSC Overall Height A - - 1.20 Standoff A1 0.05 - 0.15 Molded Package Thickness A2 0.95 1.00 1.05 Overall Width E 12.00 BSC Molded Package Width E1 10.00 BSC Overall Length D 12.00 BSC Molded Package Length D1 10.00 BSC Lead Width b 0.30 0.37 0.45 Lead Thickness c 0.09 - 0.20 Lead Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle θ 0° 3.5° 7° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Exact shape of each corner is optional. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076C Sheet 2 of 2  2010-2015 Microchip Technology Inc. DS40001303H-page 433

PIC18F2XK20/4XK20 44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 44 1 2 G C2 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.80 BSC Contact Pad Spacing C1 11.40 Contact Pad Spacing C2 11.40 Contact Pad Width (X44) X1 0.55 Contact Pad Length (X44) Y1 1.50 Distance Between Pads G 0.25 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2076B DS40001303H-page 434  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 APPENDIX A: REVISION HISTORY Revision E (04/2009) Revised data sheet title; Revised Power-Managed Revision A (07/2006) Modes, Peripheral Highlights, and Analog Features; Original data sheet for PIC18F2XK20/4XK20 devices. Revised 26.2, DC Char. table. Revision F (09/2009) Revision B (03/2007) Changed the values in the “Extreme Low-Power Added part numbers PIC18F26K20 and Management with XLP” section; Added new Note 2 to PIC18F46K20; Replaced Development Support Pin Diagrams; Updated Electrical Characteristics Section; Replaced Package Drawings. section; Added charts to the DS Characteristics section; Removed Preliminary label; Added UQFN to Revision C (10/2007) Pin Diagrams; Added the 28-pin UQFN to Table 3-1; Revised Table 1, DIL Pins 34 and 35; Table 2, Pins 22 Updated MSSP section (Register 17-3; changing and 24; Table 1-2, Pins RB1 and RB3; Table 1-3, Pins SSPADD<6:0> to SSPADD<7:0>); Updated the RB1 and RB3; Revised Sections 4.3, 4.4, 4.4.1, 4.4.2, Development Support section deleting section 25.7; 4.4.4; Revised Table 4-3, Note 2; Revised Table 6-1; Added the 28-Lead UQFN package marking diagrams Revise Section 7.8: Revised Section 9.2; Revised and the 28-Lead Plastic Ultra Thin Quad Flat, No Lead Examples 10-1 and 10-2; Revised Table 10-3, Pins Package (MV) - 4X4X0.5 mm Body (UQFN) package to RB1 and RB3; Revised Sections 12.2 through 12.5; Packaging Information section; Other minor Revised Register 16-1, bit 3-0; Revised Sections 16.1, corrections. 16.2, 16.4.4; Revised Register 16-2, bit 6-4; Revised Revision G (01/2010) Table 16-2, Note 2; Revised Register 17-1, bit 6; Revised Register 17-3; Revised Table 17-4; Revised Updated Figure 9-1; Reviewed Section 26 (Electrical Register 19-1, added Note 2; Revised Register 20-3, Characteristics); Added Figures 27-29, 27-30, 27-31 bits 5 and 4; Revised Register 23-4, bit 1; Revised and 27-32 to Section 27 (DC and AC Characteristics Register 23-12, bit 7-5; Revised Section 23.3; Revised Graphs and Tables); Reviewed Product Identification Section 24.1.1, instruction set descriptions; Revised System section. Section 26.0, voltage on MCLR; Revised DC Characteristics 26.2, 26.3, 26.4 26.5, 26.6, 26.7, 26.8 Revision H (06/2015) and 26.10; Revised Tables 26-1, 26-6, 26-7, 26-9, 26- 23. Updated Figures 1 to 6 to new pin diagrams format; Added pin diagram for 40-Pin UQFN; Updated pin Revision D (08/2008) allocation Table 2 for 40-Pin UQFN; Revised pin allocation tables; Updated Table 1-1 for 40-Pin UQFN; Update to Peripheral Highlights (EUSART module); Updated Table 1-3 for 40-Pin UQFN; Updated chapter Deleted Section 2.2.6 (Oscillator Transitions); Revised 26.0 Electrical Specifications to new format; Updated Sections 2.5.3, 2.9; Added Section 2.9.3 (Clock Switch Table 26-18 in Electrical Specifications; Updated Timing); Deleted Section 2.10.4 (Clock Switching Section 21.2, FVR Reference Module; Updated Figure Timing); Replaced BAUDCTL with BAUDCON 21-1; Updated Table B-1 in Appendix B for 40-Pin throughout; Revised Table 5-2 (PLUSW0, PLUSW1, UQFN; Updated Packaging Information chapter; PLUSW2); Add Note 1 to Table 7-1 (EEADRH); Revised Product Identification System section. Revised Section 6.4.4 and Register 16-2 (FLT0 pin); Revised Registers 17-2 and 17-5 (SSPEN); Revised Register 17-6 (SEN); Added new paragraph after Figure 18-2; Revised Note, Section 18.1.1; Deleted Note, Section 18.1.2; Added new Note 2, Sections 18.1.2.9 and 18.1.2.10; Revised Note 1, Section 18.3.1; Added Section 18.3.2; Revised Section 18.3.5; Added new Note 2, Sections 18.4.1.5, 18.4.1.10, 18.4.2.2, 18.4.2.4; Revised Register 21-1 (CVR); Revised Note 1, Registers 23-6, 23.8, 23-10, Table 23- 3; Added new Figure 26-1; Revised 26.2, 26.6, 26.7 (Note 3), 26.8, 26.9, 26.10; Revised Tables 26-1, 26-2, 26-3, 26-6, 26-7, 26-8, 26-25; Updated Package Drawings.  2010-2015 Microchip Technology Inc. DS40001303H-page 435

PIC18F2XK20/4XK20 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in TableB-1. TABLE B-1: DEVICE DIFFERENCES Features PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K20 Program Memory 8192 16384 32768 65536 8192 16384 32768 65536 (Bytes) Program Memory 4096 8192 16384 32768 4096 8192 16384 32768 (Instructions) Interrupt Sources 19 19 19 19 20 20 20 20 I/O Ports Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, (E) (E) (E) (E) D, E D, E D, E D, E Capture/ 1 1 1 1 1 1 1 1 Compare/PWM Modules Enhanced 1 1 1 1 1 1 1 1 Capture/ Compare/PWM Modules Parallel No No No No Yes Yes Yes Yes Communications (PSP) 10-bit Analog-to- 11 input 11 input 11 input 11 input 14 input 14 input 14 input 14 input Digital Module channels channels channels channels channels channels channels channels Packages 28-pin PDIP 28-pin PDIP 28-pin PDIP 28-pin PDIP 40-pin PDIP 40-pin PDIP 40-pin PDIP 40-pin PDIP 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin SOIC 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 44-pin QFN 44-pin QFN 44-pin QFN 44-pin QFN 28-pin QFN 28-pin QFN 28-pin QFN 28-pin QFN 40-pin UQFN 40-pin UQFN 40-pin UQFN 40-pin UQFN 28-pin UQFN DS40001303H-page 436  2010-2015 Microchip Technology Inc.

PIC18F2XK20/4XK20 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://www.microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2010-2015 Microchip Technology Inc. DS40001303H-page 437

PIC18F2XK20/4XK20 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC18F45K20 - E/P 301 = Industrial temp., Option Range PDIP package, QTP pattern #301. b) PIC18F23K20 - I/SO = Industrial temp., SOIC package. Device: PIC18F23K20; PIC18F24K20; PIC18F25K20; PIC18F26K20; c) PIC18F44K20 - E/P = Extended temp., PDIP PIC18F43K20; PIC18F44K20; PIC18F45K20; PIC18F46K20. package. d) PIC18F46K20 - I/PT = Industrial temp., TQFP package, tape and reel. Tape and Reel Blank = Standard packaging (tube or tray) Option: T = Tape and Reel(1) Temperature I = -40C to +125C (Industrial) Range: E = -65C to +150C (Extended) Package: PT = TQFP (Thin Quad Flatpack) SS = SSOP SO = SOIC Note1: Tape and Reel identifier only appears in the SP = SPDIP (Skinny Plastic DIP) catalog part number description. This P = PDIP identifier is used for ordering purposes and ML = QFN is not printed on the device package. Check MV = UQFN with your Microchip Sales Office for package availability with the Tape and Reel option. Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) DS40001303H-page 438  2010-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights unless otherwise stated. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2010-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-505-4 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2010-2015 Microchip Technology Inc. DS40001303H-page 439

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