PIC18(L)F2X/4XK22 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology High-Performance RISC CPU: eXtreme Low-Power Features (XLP) (PIC18(L)F2X/4XK22): • C Compiler Optimized Architecture: - Optional extended instruction set designed to • Sleep mode: 20 nA, typical optimize re-entrant code • Watchdog Timer: 300 nA, typical • Up to 1024 Bytes Data EEPROM • Timer1 Oscillator: 800 nA @ 32 kHz • Up to 64Kbytes Linear Program Memory • Peripheral Module Disable Addressing • Up to 3896 Bytes Linear Data Memory Address- Special Microcontroller Features: ing • Up to 16 MIPS Operation • 2.3V to 5.5V Operation – PIC18FXXK22 devices • 16-bit Wide Instructions, 8-bit Wide Data Path • 1.8V to 3.6V Operation – PIC18LFXXK22 devices • Priority Levels for Interrupts • Self-Programmable under Software Control • 31-Level, Software Accessible Hardware Stack • High/Low-Voltage Detection (HLVD) module: • 8 x 8 Single-Cycle Hardware Multiplier - Programmable 16-Level - Interrupt on High/Low-Voltage Detection Flexible Oscillator Structure: • Programmable Brown-out Reset (BOR): • Precision 16MHz Internal Oscillator Block: - With software enable option - Factory calibrated to ± 1% - Configurable shutdown in Sleep - Selectable frequencies, 31kHz to 16MHz • Extended Watchdog Timer (WDT): - 64MHz performance available using PLL – - Programmable period from 4ms to 131s no external components required • In-Circuit Serial Programming™ (ICSP™): • Four Crystal modes up to 64MHz - Single-Supply 3V • Two External Clock modes up to 64MHz • In-Circuit Debug (ICD) • 4X Phase Lock Loop (PLL) • Secondary Oscillator using Timer1 @ 32kHz Peripheral Highlights: • Fail-Safe Clock Monitor: • Up to 35 I/O Pins plus 1 Input-Only Pin: - Allows for safe shutdown if peripheral clock - High-Current Sink/Source 25mA/25mA stops - Three programmable external interrupts - Two-Speed Oscillator Start-up - Four programmable interrupt-on-change - Nine programmable weak pull-ups Analog Features: - Programmable slew rate • Analog-to-Digital Converter (ADC) module: • SR Latch: - 10-bit resolution, up to 30 external channels - Multiple Set/Reset input options - Auto-acquisition capability • Two Capture/Compare/PWM (CCP) modules - Conversion available during Sleep • Three Enhanced CCP (ECCP) modules: - Fixed Voltage Reference (FVR) channel - One, two or four PWM outputs - Independent input multiplexing - Selectable polarity • Analog Comparator module: - Programmable dead time - Two rail-to-rail analog comparators - Auto-Shutdown and Auto-Restart - Independent input multiplexing - PWM steering • Digital-to-Analog Converter (DAC) module: • Two Master Synchronous Serial Port (MSSP) modules: - Fixed Voltage Reference (FVR) with 1.024V, - 3-wire SPI (supports all 4 modes) 2.048V and 4.096V output levels - I2C Master and Slave modes with address - 5-bit rail-to-rail resistive DAC with positive mask and negative reference selection • Charge Time Measurement Unit (CTMU) module: - Supports capacitive touch sensing for touch screens and capacitive switches  2010-2016 Microchip Technology Inc. DS40001412G-page 1

PIC18(L)F2X/4XK22 • Two Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) modules: - Supports RS-485, RS-232 and LIN - RS-232 operation using internal oscillator - Auto-Wake-up on Break - Auto-Baud Detect TABLE 1: PIC18(L)F2X/4XK22 FAMILY TYPES Program Data MSSP Memory Memory 2) Device Flash(Bytes) Single-Wordnstructions SRAM(Bytes) EEPROM(Bytes) (1)I/O 10-bit(A/D Channels CCP ECCP(Full-Bridge) ECCP(Half-Bridge) SPI 2CI EUSART Comparator CTMU BOR/LVD SR Latch 8-bit Timer 16-bit Timer # I PIC18(L)F23K22 8K 4096 512 256 25 19 2 1 2 2 2 2 2 Y Y Y 3 4 PIC18(L)F24K22 16K 8192 768 256 25 19 2 1 2 2 2 2 2 Y Y Y 3 4 PIC18(L)F25K22 32K 16384 1536 256 25 19 2 1 2 2 2 2 2 Y Y Y 3 4 PIC18(L)F26K22 64k 32768 3896 1024 25 19 2 1 2 2 2 2 2 Y Y Y 3 4 PIC18(L)F43K22 8K 4096 512 256 36 30 2 2 1 2 2 2 2 Y Y Y 3 4 PIC18(L)F44K22 16K 8192 768 256 36 30 2 2 1 2 2 2 2 Y Y Y 3 4 PIC18(L)F45K22 32K 16384 1536 256 36 30 2 2 1 2 2 2 2 Y Y Y 3 4 PIC18(L)F46K22 64k 32768 3896 1024 36 30 2 2 1 2 2 2 2 Y Y Y 3 4 Note 1: One pin is input only. 2: Channel count includes internal FVR and DAC channels. DS40001412G-page 2  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 1: 28-PIN PDIP, SOIC, SSOP DIAGRAM MCLR/VPP/RE3 1 28 RB7/PGD RA0 2 27 RB6/PGC RA1 3 26 RB5 RA2 4 25 RB4 2 RA3 5 2 24 RB3 K RA4 6 X 23 RB2 RA5 7 2 22 RB1 F VSS 8 L) 21 RB0 RA7 9 8( 20 VDD RA6 10 C1 19 VSS RC0 11 PI 18 RC7 RC1 12 17 RC6 RC2 13 16 RC5 RC3 14 15 RC4 FIGURE 2: 28-PIN QFN, UQFN(1) DIAGRAM 3 E R /P PDC VGG R/PP A1A0CLB7/B6/B5B4 RRMRRRR 28272625242322 RA2 1 21 RB3 RA3 2 20 RB2 RA4 3 19 RB1 RA5/ 4PIC18(L)F2XK22 18 RB0 VSS 5 17 VDD RA7 6 16 VSS RA6 7 15 RC7 8 91011121314 0123456 CCCCCCC RRRRRRR Note 1: The 28-pin UQFN package is available only for PIC18(L)F23K22 and PIC18(L)F24K22.  2010-2016 Microchip Technology Inc. DS40001412G-page 3

PIC18(L)F2X/4XK22 FIGURE 3: 40-PIN PDIP DIAGRAM MCLR/VPP/RE3 1 40 RB7/PGD RA0 2 39 RB6/PGC RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 7 34 RB1 RE0 8 2 33 RB0 2 RE1 9 K 32 VDD RE2 10 4X 31 VSS VDD 11 F 30 RD7 VSS 12 L) 29 RD6 ( RA7 13 18 28 RD5 RA6 14 C 27 RD4 RC0 15 PI 26 RC7 RC1 16 25 RC6 RC2 17 24 RC5 RC3 18 23 RC4 RD0 19 22 RD3 RD1 20 21 RD2 FIGURE 4: 40-PIN UQFN DIAGRAM 6543210321 CCCDDDDCCC RRRRRRRRRR 0987654321 4333333333 RC7 1 30 RC0 RD4 2 29 RA6 RD5 3 28 RA7 RD6 4 27 VSS RD7 5 PIC18(L)F4XK22 26 VDD VSS 6 25 RE2 VDD 7 24 RE1 RB0 8 23 RE0 RB1 9 22 RA5 RB2 10 21 RA4 1234567890 1111111112 3456730123 BBBBBEAAAA RRRRRRRRRR C/D//P GGVP PPR/ L C M DS40001412G-page 4  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 5: 44-PIN TQFP DIAGRAM 6543210321 CCCDDDDCCCC RRRRRRRRRRN 43210987654 44444333333 RC7 1 33 NC RD4 2 32 RC0 RD5 3 31 RA6 RD6 4 30 RA7 RD7 5 29 VSS PIC18(L)F4XK22 VSS 6 28 VDD VDD 7 27 RE2 RB0 8 26 RE1 RB1 9 25 RE0 RB2 10 24 RA5 RB3 11 23 RA4 11111111222 23456789012 CC456730123 NNBBBBEAAAA RRRRRRRRR C/D//P GGVP PP/R L C M FIGURE 6: 44-PIN QFN DIAGRAM 65432103210 CCCDDDDCCCC RRRRRRRRRRR 43210987654 RC7 14444433333333 RA6 RD4 2 32 RA7 RD5 3 31 VSS RD6 4 30 VSS RD7 5 29 VDD VSS 6PIC18(L)F4XK22 28 VDD VDD 7 27 RE2 VDD 8 26 RE1 RB0 9 25 RE0 RB1 10 24 RA5 RB2 11 23 RA4 11111111222 23456789012 3C456730123 BNBBBBEAAAA R RRRRRRRRR C/D//P GGVP PPR/ L C M  2010-2016 Microchip Technology Inc. DS40001412G-page 5

PIC18(L)F2X/4XK22 TABLE 2: PIC18(L)F2XK22 PIN SUMMARY C N 8-SSOP, SOI28-SPDIP 8-QFN, UQF I/O Analog Comparator CTMU SR Latch Reference (E)CCP EUSART MSSP Timers Interrupts Pull-up Basic 2 2 2 27 RA0 AN0 C12IN0- 3 28 RA1 AN1 C12IN1- 4 1 RA2 AN2 C2IN+ VREF- DACOUT 5 2 RA3 AN3 C1IN+ VREF+ 6 3 RA4 C1OUT SRQ CCP5 T0CKI 7 4 RA5 AN4 C2OUT SRNQ HLVDIN SS1 10 7 RA6 OSC2 CLKO 9 6 RA7 OSC1 CLKI 21 18 RB0 AN12 SRI CCP4 SS2 INT0 Y FLT0 22 19 RB1 AN10 C12IN3- P1C SCK2 INT1 Y SCL2 23 20 RB2 AN8 CTED1 P1B SDI2 INT2 Y SDA2 24 21 RB3 AN9 C12IN2- CTED2 CCP2 SDO2 Y P2A(1) 25 22 RB4 AN11 P1D T5G IOC Y 26 23 RB5 AN13 CCP3 T1G IOC Y P3A(4) T3CKI(2) P2B(3) 27 24 RB6 TX2/CK2 IOC Y PGC 28 25 RB7 RX2/DT2 IOC Y PGD 11 8 RC0 P2B(3) SOSCO T1CKI T3CKI(2) T3G 12 9 RC1 CCP2 SOSCI P2A(1) 13 10 RC2 AN14 CTPLS CCP1 T5CKI P1A 14 11 RC3 AN15 SCK1 SCL1 15 12 RC4 AN16 SDI1 SDA1 16 13 RC5 AN17 SDO1 17 14 RC6 AN18 CCP3 TX1/CK1 P3A(4) 18 15 RC7 AN19 P3B RX1/DT1 1 26 RE3 MCLR VPP 8, 19 5, 16 VSS VSS 19 16 20 17 VDD VDD Note 1: CCP2/P2A multiplexed in fuses. 2: T3CKI multiplexed in fuses. 3: P2B multiplexed in fuses. 4: CCP3/P3A multiplexed in fuses. DS40001412G-page 6  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 3: PIC18(L)F4XK22 PIN SUMMARY 40-PDIP 40-UQFN 44-TQFP 44-QFN I/O Analog Comparator CTMU SR Latch Reference (E)CCP EUSART MSSP Timers Interrupts Pull-up Basic 2 17 19 19 RA0 AN0 C12IN0- 3 18 20 20 RA1 AN1 C12IN1- 4 19 21 21 RA2 AN2 C2IN+ VREF- DACOU T 5 20 22 22 RA3 AN3 C1IN+ VREF+ 6 21 23 23 RA4 C1OUT SRQ T0CKI 7 22 24 24 RA5 AN4 C2OUT SRNQ HLVDIN SS1 14 29 31 33 RA6 OSC2 CLKO 13 28 30 32 RA7 OSC1 CLKI 33 8 8 9 RB0 AN12 SRI FLT0 INT0 Y 34 9 9 10 RB1 AN10 C12IN3- INT1 Y 35 10 10 11 RB2 AN8 CTED1 INT2 Y 36 11 11 12 RB3 AN9 C12IN2- CTED2 CCP2 Y P2A(1) 37 12 14 14 RB4 AN11 T5G IOC Y 38 13 15 15 RB5 AN13 CCP3 T1G IOC Y P3A(3) T3CKI(2) 39 14 16 16 RB6 IOC Y PGC 40 15 17 17 RB7 IOC Y PGD 15 30 32 34 RC0 P2B(4) SOSCO T1CKI T3CKI(2) T3G 16 31 35 35 RC1 CCP2(1) SOSCI P2A 17 32 36 36 RC2 AN14 CTPLS CCP1 T5CKI P1A 18 33 37 37 RC3 AN15 SCK1 SCL1 23 38 42 42 RC4 AN16 SDI1 SDA1 24 39 43 43 RC5 AN17 SDO1 25 40 44 44 RC6 AN18 TX1 CK1 26 1 1 1 RC7 AN19 RX1 DT1 19 34 38 38 RD0 AN20 SCK2 SCL2 20 35 39 39 RD1 AN21 CCP4 SDI2 SDA2 21 36 40 40 RD2 AN22 P2B(4) 22 37 41 41 RD3 AN23 P2C SS2 27 2 2 2 RD4 AN24 P2D SD02 28 3 3 3 RD5 AN25 P1B 29 4 4 4 RD6 AN26 P1C TX2 CK2 30 5 5 5 RD7 AN27 P1D RX2 DT2 8 23 25 25 RE0 AN5 CCP3 P3A(3) Note 1: CCP2 multiplexed in fuses. 2: T3CKI multiplexed in fuses. 3: CCP3/P3A multiplexed in fuses. 4: P2B multiplexed in fuses.  2010-2016 Microchip Technology Inc. DS40001412G-page 7

PIC18(L)F2X/4XK22 TABLE 3: PIC18(L)F4XK22 PIN SUMMARY (CONTINUED) 40-PDIP 40-UQFN 44-TQFP 44-QFN I/O Analog Comparator CTMU SR Latch Reference (E)CCP EUSART MSSP Timers Interrupts Pull-up Basic 9 24 26 26 RE1 AN6 P3B 10 25 27 27 RE2 AN7 CCP5 1 16 18 18 RE3 Y MCLR VPP 11, 7, 26 7, 7,8 VDD VDD 32 28 28, 29 12, 6, 27 6, 6, VSS VSS 31 29 30, 31 — — 12, 13 13 NC 33, 34 Note 1: CCP2 multiplexed in fuses. 2: T3CKI multiplexed in fuses. 3: CCP3/P3A multiplexed in fuses. 4: P2B multiplexed in fuses. DS40001412G-page 8  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Table of Contents 1.0 Device Overview........................................................................................................................................................................ 11 2.0 Oscillator Module (With Fail-Safe Clock Monitor)).................................................................................................................... 25 3.0 Power-Managed Modes............................................................................................................................................................ 44 4.0 Reset......................................................................................................................................................................................... 55 5.0 Memory Organization................................................................................................................................................................ 64 6.0 Flash Program Memory............................................................................................................................................................. 90 7.0 Data EEPROM Memory............................................................................................................................................................ 99 8.0 8 x 8 Hardware Multiplier......................................................................................................................................................... 104 9.0 Interrupts................................................................................................................................................................................. 106 10.0 I/O Ports.................................................................................................................................................................................. 127 11.0 Timer0 Module........................................................................................................................................................................ 154 12.0 Timer1/3/5 Module with Gate Control...................................................................................................................................... 157 13.0 Timer2/4/6 Module.................................................................................................................................................................. 169 14.0 Capture/Compare/PWM Modules........................................................................................................................................... 173 15.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module............................................................................................. 204 16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART).............................................................. 259 17.0 Analog-to-Digital Converter (ADC) Module............................................................................................................................. 288 18.0 Comparator Module................................................................................................................................................................. 302 19.0 Charge Time Measurement Unit (CTMU)................................................................................................................................. 311 20.0 SR LATCH................................................................................................................................................................................. 326 21.0 Fixed Voltage Reference (FVR).............................................................................................................................................. 331 22.0 Digital-to-Analog Converter (DAC) Module............................................................................................................................. 333 23.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................ 337 24.0 Special Features of the CPU................................................................................................................................................... 343 25.0 Instruction Set Summary......................................................................................................................................................... 360 26.0 Development Support.............................................................................................................................................................. 410 27.0 Electrical Specifications........................................................................................................................................................... 414 28.0 DC and AC Characteristics Graphs and Tables...................................................................................................................... 453 29.0 Packaging Information............................................................................................................................................................. 509 Appendix A: Revision History............................................................................................................................................................ 534 Appendix B: Device Differences........................................................................................................................................................ 535 The Microchip Web Site.................................................................................................................................................................... 536 Customer Change Notification Service............................................................................................................................................. 536 Customer Support............................................................................................................................................................................. 536 Product Identification System........................................................................................................................................................... 537  2010-2016 Microchip Technology Inc. DS40001412G-page 9

PIC18(L)F2X/4XK22 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. DS40001412G-page 10  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 1.0 DEVICE OVERVIEW 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES This document contains device specific information for the following devices: All of the devices in the PIC18(L)F2X/4XK22 family offer ten different oscillator options, allowing users a • PIC18F23K22 • PIC18LF23K22 wide range of choices in developing application • PIC18F24K22 • PIC18LF24K22 hardware. These include: • PIC18F25K22 • PIC18LF25K22 • Four Crystal modes, using crystals or ceramic resonators • PIC18F26K22 • PIC18LF26K22 • Two External Clock modes, offering the option of • PIC18F43K22 • PIC18LF43K22 using two pins (oscillator input and a divide-by-4 • PIC18F44K22 • PIC18LF44K22 clock output) or one pin (oscillator input, with the • PIC18F45K22 • PIC18LF45K22 second pin reassigned as general I/O) • PIC18F46K22 • PIC18LF46K22 • Two External RC Oscillator modes with the same pin options as the External Clock modes This family offers the advantages of all PIC18 microcontrollers – namely, high computational • An internal oscillator block which contains a performance at an economical price – with the addition 16MHz HFINTOSC oscillator and a 31kHz of high-endurance, Flash program memory. On top of LFINTOSC oscillator, which together provide eight these features, the PIC18(L)F2X/4XK22 family user selectable clock frequencies, from 31kHz to introduces design enhancements that make these 16MHz. This option frees the two oscillator pins microcontrollers a logical choice for many high- for use as additional general purpose I/O. performance, power sensitive applications. • A Phase Lock Loop (PLL) frequency multiplier, available to both external and internal oscillator 1.1 New Core Features modes, which allows clock speeds of up to 64MHz. Used with the internal oscillator, the PLL 1.1.1 XLP TECHNOLOGY gives users a complete selection of clock speeds, from 31kHz to 64MHz – all without using an All of the devices in the PIC18(L)F2X/4XK22 family external crystal or clock circuit. incorporate a range of features that can significantly reduce power consumption during operation. Key Besides its availability as a clock source, the internal items include: oscillator block provides a stable reference source that gives the family additional features for robust • Alternate Run Modes: By clocking the controller operation: from the Timer1 source or the internal oscillator block, power consumption during code execution • Fail-Safe Clock Monitor: This option constantly can be reduced by as much as 90%. monitors the main clock source against a • Multiple Idle Modes: The controller can also run reference signal provided by the LFINTOSC. If a with its CPU core disabled but the peripherals still clock failure occurs, the controller is switched to active. In these states, power consumption can be the internal oscillator block, allowing for continued reduced even further, to as little as 4% of normal operation or a safe application shutdown. operation requirements. • Two-Speed Start-up: This option allows the • On-the-fly Mode Switching: The power- internal oscillator to serve as the clock source managed modes are invoked by user code during from Power-on Reset, or Wake-up from Sleep operation, allowing the user to incorporate power- mode, until the primary clock source is available. saving ideas into their application’s software design. • Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section27.0 “Electrical Specifications” for values.  2010-2016 Microchip Technology Inc. DS40001412G-page 11

PIC18(L)F2X/4XK22 1.2 Other Special Features 1.3 Details on Individual Family Members • Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to Devices in the PIC18(L)F2X/4XK22 family are last for many thousands of erase/write cycles – up to available in 28-pin and 40/44-pin packages. The block 10K for program memory and 100K for EEPROM. diagram for the device family is shown in Figure1-1. Data retention without refresh is conservatively The devices have the following differences: estimated to be greater than 40 years. 1. Flash program memory • Self-programmability: These devices can write to their own program memory spaces under inter- 2. Data Memory SRAM nal software control. By using a bootloader routine 3. Data Memory EEPROM located in the protected Boot Block at the top of 4. A/D channels program memory, it becomes possible to create 5. I/O ports an application that can update itself in the field. 6. ECCP modules (Full/Half Bridge) • Extended Instruction Set: The PIC18(L)F2X/ 7. Input Voltage Range/Power Consumption 4XK22 family introduces an optional extension to the PIC18 instruction set, which adds eight new All other features for devices in this family are identical. instructions and an Indexed Addressing mode. These are summarized in Table1-1. This extension, enabled as a device configuration The pinouts for all devices are listed in the pin summary option, has been specifically designed to optimize tables: Table2 and Table3, and I/O description tables: re-entrant application code originally developed in Table1-2 and Table1-3. high-level languages, such as C. • Enhanced CCP module: In PWM mode, this module provides one, two or four modulated outputs for controlling half-bridge and full-bridge drivers. Other features include: - Auto-Shutdown, for disabling PWM outputs on interrupt or other select conditions - Auto-Restart, to reactivate outputs once the condition has cleared - Output steering to selectively enable one or more of four outputs to provide the PWM signal. • Enhanced Addressable EUSART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit postscaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section27.0 “Electrical Specifications” for time-out periods. • Charge Time Measurement Unit (CTMU) • SR Latch Output: DS40001412G-page 12  2010-2016 Microchip Technology Inc.

 TABLE 1-1: DEVICE FEATURES 2 0 1 0 -20 Features PPIICC1188LFF2233KK2222 PPIICC1188LFF2244KK2222 PPICIC181(8LF)2F52K5K2222 PPIICC1188LFF2266KK2222 PPIICC1188LFF4433KK2222 PPIICC1188LFF4444KK2222 PPIICC1188LFF4455KK2222 PPIICC1188LFF4466KK2222 1 6 M Program Memory (Bytes) 8192 16384 32768 65536 8192 16384 32768 65536 ic ro Program Memory 4096 8192 16384 32768 4096 8192 16384 32768 c (Instructions) h ip T Data Memory (Bytes) 512 768 1536 3896 512 768 1536 3896 ec Data EEPROM Memory (Bytes) 256 256 256 1024 256 256 256 1024 h no I/O Ports A, B, C, E(1) A, B, C, E(1) A, B, C, E(1) A, B, C, E(1) A, B, C, D, E A, B, C, D, E A, B, C, D, E A, B, C, D, E lo g Capture/Compare/PWM Modules 2 2 2 2 2 2 2 2 y In (CCP) c. Enhanced CCP Modules (ECCP) - 2 2 2 2 1 1 1 1 Half Bridge Enhanced CCP Modules (ECCP) - 1 1 1 1 2 2 2 2 Full Bridge 10-bit Analog-to-Digital Module (ADC) 2 internal 2 internal 2 internal 2 internal 2 internal 2 internal 2 internal 2 internal 17 input 17 input 17 input 17 input 28 input 28 input 28 input 28 input Packages 28-pin PDIP 28-pin PDIP 28-pin PDIP 28-pin PDIP 40-pin PDIP 40-pin PDIP 40-pin PDIP 40-pin PDIP 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin SOIC 40-pin UQFN 40-pin UQFN 40-pin UQFN 40-pin UQFN 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 44-pin QFN 44-pin QFN 44-pin QFN 44-pin QFN 28-pin QFN 28-pin QFN 28-pin QFN 28-pin QFN 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP 28-pin UQFN 28-pin UQFN Interrupt Sources 33 Timers (16-bit) 4 Serial Communications 2 MSSP, P 2 EUSART I SR Latch Yes C Charge Time Measurement Unit Yes Module (CTMU) 1 Programmable Yes 8 High/Low-Voltage Detect (HLVD) ( L Programmable Brown-out Reset Yes (BOR) ) Resets (and Delays) POR, BOR, F RESET Instruction, 2 Stack Overflow, D Stack Underflow X S (PWRT, OST), 400 MCLR, WDT /4 01 Instruction Set 75 Instructions; X 4 83 with Extended Instruction Set enabled 1 2G Operating Frequency DC - 64 MHz K -pa Note 1: PORTE contains the single RE3 read-only bit. 2 g e 1 2 3

PIC18(L)F2X/4XK22 FIGURE 1-1: PIC18(L)F2X/4XK22 FAMILY BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 8 Data Latch inc/dec logic Data Memory 21 PCLAT U PCLATH 20 Address Latch PORTA PCU PCH PCL RA0:RA7 Program Counter 12 Data Address<12> 31-Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (8/16/32/64Kbytes) FSR1 PORTB Data Latch FSR2 12 RB0:RB7 inc/dec 8 logic Table Latch Address ROM Latch Instruction Bus <16> Decode PORTC IR RC0:RC7 8 Instruction State machine Decode and control signals Control PRODH PRODL PORTD 8 x 8 Multiply RD0:RD7 3 8 BITOP W 8 8 8 OSC1(2) Internal Power-up Oscillator Timer 8 8 Block PORTE OSC2(2) Oscillator ALU<8> LFINTOSC Start-up Timer RE0:RE2 SOSCI Oscillator Power-on 8 RE3(1) Reset 16 MHz SOSCO Oscillator Watchdog Timer MCLR(1) Single-Supply Brown-out BParencdi sGioanp FVR Programming Reset Reference In-Circuit Fail-Safe Debugger Clock Monitor BOR Data Timer1 Timer2 HLVD EEPROM Timer0 Timer3 Timer4 CTMU DAC Timer5 Timer6 FVR ECCP1 Comparators ECCP2(3) CCP4 MSSP1 EUSART1 SR Latch ADC FVR DAC C1/C2 CCP5 MSSP2 EUSART2 10-bit ECCP3 Note 1: RE3 is only available when MCLR functionality is disabled. 2: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information. 3: Full-Bridge operation for PIC18(L)F4XK22, half-bridge operation for PIC18(L)F2XK22. DS40001412G-page 14  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description PDIP, QFN, Type Type SOIC UQFN 2 27 RA0/C12IN0-/AN0 RA0 I/O TTL Digital I/O. C12IN0- I Analog Comparators C1 and C2 inverting input. AN0 I Analog Analog input 0. 3 28 RA1/C12IN1-/AN1 RA1 I/O TTL Digital I/O. C12IN1- I Analog Comparators C1 and C2 inverting input. AN1 I Analog Analog input 1. 4 1 RA2/C2IN+/AN2/DACOUT/VREF- RA2 I/O TTL Digital I/O. C2IN+ I Analog Comparator C2 non-inverting input. AN2 I Analog Analog input 2. DACOUT O Analog DAC Reference output. VREF- I Analog A/D reference voltage (low) input. 5 2 RA3/C1IN+/AN3/VREF+ RA3 I/O TTL Digital I/O. C1IN+ I Analog Comparator C1 non-inverting input. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. 6 3 RA4/CCP5/C1OUT/SRQ/T0CKI RA4 I/O ST Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output. C1OUT O CMOS Comparator C1 output. SRQ O TTL SR latch Q output. T0CKI I ST Timer0 external clock input. 7 4 RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4 RA5 I/O TTL Digital I/O. C2OUT O CMOS Comparator C2 output. SRNQ O TTL SR latch Q output. SS1 I TTL SPI slave select input (MSSP). HLVDIN I Analog High/Low-Voltage Detect input. AN4 I Analog Analog input 4. 10 7 RA6/CLKO/OSC2 RA6 I/O TTL Digital I/O. CLKO O In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. OSC2 O Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010-2016 Microchip Technology Inc. DS40001412G-page 15

PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP, QFN, Type Type SOIC UQFN 9 6 RA7/CLKI/OSC1 RA7 I/O TTL Digital I/O. CLKI I CMOS External clock source input. Always associated with pin function OSC1. OSC1 I ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. 21 18 RB0/INT0/CCP4/FLT0/SRI/SS2/AN12 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM 4 output. FLT0 I ST PWM Fault input for ECCP Auto-Shutdown. SRI I ST SR latch input. SS2 I TTL SPI slave select input (MSSP). AN12 I Analog Analog input 12. 22 19 RB1/INT1/P1C/SCK2/SCL2/C12IN3-/AN10 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. P1C O CMOS Enhanced CCP1 PWM output. SCK2 I/O ST Synchronous serial clock input/output for SPI mode (MSSP). SCL2 I/O ST Synchronous serial clock input/output for I2C mode (MSSP). C12IN3- I Analog Comparators C1 and C2 inverting input. AN10 I Analog Analog input 10. 23 20 RB2/INT2/CTED1/P1B/SDI2/SDA2/AN8 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. CTED1 I ST CTMU Edge 1 input. P1B O CMOS Enhanced CCP1 PWM output. SDI2 I ST SPI data in (MSSP). SDA2 I/O ST I2C data I/O (MSSP). AN8 I Analog Analog input 8. 24 21 RB3/CTED2/P2A/CCP2/SDO2/C12IN2-/AN9 RB3 I/O TTL Digital I/O. CTED2 I ST CTMU Edge 2 input. P2A O CMOS Enhanced CCP2 PWM output. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. SDO2 O — SPI data out (MSSP). C12IN2- I Analog Comparators C1 and C2 inverting input. AN9 I Analog Analog input 9. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. DS40001412G-page 16  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP, QFN, Type Type SOIC UQFN 25 22 RB4/IOC0/P1D/T5G/AN11 RB4 I/O TTL Digital I/O. IOC0 I TTL Interrupt-on-change pin. P1D O CMOS Enhanced CCP1 PWM output. T5G I ST Timer5 external clock gate input. AN11 I Analog Analog input 11. 26 23 RB5/IOC1/P2B/P3A/CCP3/T3CKI/T1G/AN13 RB5 I/O TTL Digital I/O. IOC1 I TTL Interrupt-on-change pin. P2B(1) O CMOS Enhanced CCP2 PWM output. P3A(1) O CMOS Enhanced CCP3 PWM output. CCP3(1) I/O ST Capture 3 input/Compare 3 output/PWM 3 output. T3CKI(2) I ST Timer3 clock input. T1G I ST Timer1 external clock gate input. AN13 I Analog Analog input 13. 27 24 RB6/IOC2/TX2/CK2/PGC RB6 I/O TTL Digital I/O. IOC2 I TTL Interrupt-on-change pin. TX2 O — EUSART asynchronous transmit. CK2 I/O ST EUSART synchronous clock (see related RXx/DTx). PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. 28 25 RB7/IOC3/RX2/DT2/PGD RB7 I/O TTL Digital I/O. IOC3 I TTL Interrupt-on-change pin. RX2 I ST EUSART asynchronous receive. DT2 I/O ST EUSART synchronous data (see related TXx/CKx). PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. 11 8 RC0/P2B/T3CKI/T3G/T1CKI/SOSCO RC0 I/O ST Digital I/O. P2B(2) O CMOS Enhanced CCP1 PWM output. T3CKI(1) I ST Timer3 clock input. T3G I ST Timer3 external clock gate input. T1CKI I ST Timer1 clock input. SOSCO O — Secondary oscillator output. 12 9 RC1/P2A/CCP2/SOSCI RC1 I/O ST Digital I/O. P2A O CMOS Enhanced CCP2 PWM output. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. SOSCI I Analog Secondary oscillator input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010-2016 Microchip Technology Inc. DS40001412G-page 17

PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP, QFN, Type Type SOIC UQFN 13 10 RC2/CTPLS/P1A/CCP1/T5CKI/AN14 RC2 I/O ST Digital I/O. CTPLS O — CTMU pulse generator output. P1A O CMOS Enhanced CCP1 PWM output. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output. T5CKI I ST Timer5 clock input. AN14 I Analog Analog input 14. 14 11 RC3/SCK1/SCL1/AN15 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode (MSSP). SCL1 I/O ST Synchronous serial clock input/output for I2C mode (MSSP). AN15 I Analog Analog input 15. 15 12 RC4/SDI1/SDA1/AN16 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in (MSSP). SDA1 I/O ST I2C data I/O (MSSP). AN16 I Analog Analog input 16. 16 13 RC5/SDO1/AN17 RC5 I/O ST Digital I/O. SDO1 O — SPI data out (MSSP). AN17 I Analog Analog input 17. 17 14 RC6/P3A/CCP3/TX1/CK1/AN18 RC6 I/O ST Digital I/O. P3A(2) O CMOS Enhanced CCP3 PWM output. CCP3(2) I/O ST Capture 3 input/Compare 3 output/PWM 3 output. TX1 O — EUSART asynchronous transmit. CK1 I/O ST EUSART synchronous clock (see related RXx/DTx). AN18 I Analog Analog input 18. 18 15 RC7/P3B/RX1/DT1/AN19 RC7 I/O ST Digital I/O. P3B O CMOS Enhanced CCP3 PWM output. RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data (see related TXx/CKx). AN19 I Analog Analog input 19. 1 26 RE3/VPP/MCLR RE3 I ST Digital input. VPP P Programming voltage input. MCLR I ST Active-Low Master Clear (device Reset) input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. DS40001412G-page 18  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP, QFN, Type Type SOIC UQFN 20 17 VDD P — Positive supply for logic and I/O pins. 8, 19 5, 16 VSS P — Ground reference for logic and I/O pins. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type PDIP TQFP QFN UQFN 2 19 19 17 RA0/C12IN0-/AN0 RA0 I/O TTL Digital I/O. C12IN0- I Analog Comparators C1 and C2 inverting input. AN0 I Analog Analog input 0. 3 20 20 18 RA1/C12IN1-/AN1 RA1 I/O TTL Digital I/O. C12IN1- I Analog Comparators C1 and C2 inverting input. AN1 I Analog Analog input 1. 4 21 21 19 RA2/C2IN+/AN2/DACOUT/VREF- RA2 I/O TTL Digital I/O. C2IN+ I Analog Comparator C2 non-inverting input. AN2 I Analog Analog input 2. DACOUT O Analog DAC Reference output. VREF- I Analog A/D reference voltage (low) input. 5 22 22 20 RA3/C1IN+/AN3/VREF+ RA3 I/O TTL Digital I/O. C1IN+ I Analog Comparator C1 non-inverting input. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. 6 23 23 21 RA4/C1OUT/SRQ/T0CKI RA4 I/O ST Digital I/O. C1OUT O CMOS Comparator C1 output. SRQ O TTL SR latch Q output. T0CKI I ST Timer0 external clock input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010-2016 Microchip Technology Inc. DS40001412G-page 19

PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP TQFP QFN UQFN 7 24 24 22 RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4 RA5 I/O TTL Digital I/O. C2OUT O CMOS Comparator C2 output. SRNQ O TTL SR latch Q output. SS1 I TTL SPI slave select input (MSSP1). HLVDIN I Analog High/Low-Voltage Detect input. AN4 I Analog Analog input 4. 14 31 33 29 RA6/CLKO/OSC2 RA6 I/O TTL Digital I/O. CLKO O — In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. 13 30 32 28 RA7/CLKI/OSC1 RA7 I/O TTL Digital I/O. CLKI I CMOS External clock source input. Always associated with pin function OSC1. OSC1 I ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. 33 8 9 8 RB0/INT0/FLT0/SRI/AN12 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input for ECCP Auto-Shutdown. SRI I ST SR latch input. AN12 I Analog Analog input 12. 34 9 10 9 RB1/INT1/C12IN3-/AN10 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. C12IN3- I Analog Comparators C1 and C2 inverting input. AN10 I Analog Analog input 10. 35 10 11 10 RB2/INT2/CTED1/AN8 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. CTED1 I ST CTMU Edge 1 input. AN8 I Analog Analog input 8. 36 11 12 11 RB3/CTED2/P2A/CCP2/C12IN2-/AN9 RB3 I/O TTL Digital I/O. CTED2 I ST CTMU Edge 2 input. P2A(2) O CMOS Enhanced CCP2 PWM output. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. C12IN2- I Analog Comparators C1 and C2 inverting input. AN9 I Analog Analog input 9. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. DS40001412G-page 20  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP TQFP QFN UQFN 37 14 14 12 RB4/IOC0/T5G/AN11 RB4 I/O TTL Digital I/O. IOC0 I TTL Interrupt-on-change pin. T5G I ST Timer5 external clock gate input. AN11 I Analog Analog input 11. 38 15 15 13 RB5/IOC1/P3A/CCP3/T3CKI/T1G/AN13 RB5 I/O TTL Digital I/O. IOC1 I TTL Interrupt-on-change pin. P3A(1) O CMOS Enhanced CCP3 PWM output. CCP3(1) I/O ST Capture 3 input/Compare 3 output/PWM 3 output. T3CKI(2) I ST Timer3 clock input. T1G I ST Timer1 external clock gate input. AN13 I Analog Analog input 13. 39 16 16 14 RB6/IOC2/PGC RB6 I/O TTL Digital I/O. IOC2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. 40 17 17 15 RB7/IOC3/PGD RB7 I/O TTL Digital I/O. IOC3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. 15 32 34 30 RC0/P2B/T3CKI/T3G/T1CKI/SOSCO RC0 I/O ST Digital I/O. P2B(2) O CMOS Enhanced CCP1 PWM output. T3CKI(1) I ST Timer3 clock input. T3G I ST Timer3 external clock gate input. T1CKI I ST Timer1 clock input. SOSCO O — Secondary oscillator output. 16 35 35 31 RC1/P2A/CCP2/SOSCI RC1 I/O ST Digital I/O. P2A(1) O CMOS Enhanced CCP2 PWM output. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. SOSCI I Analog Secondary oscillator input. 17 36 36 32 RC2/CTPLS/P1A/CCP1/T5CKI/AN14 RC2 I/O ST Digital I/O. CTPLS O — CTMU pulse generator output. P1A O CMOS Enhanced CCP1 PWM output. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output. T5CKI I ST Timer5 clock input. AN14 I Analog Analog input 14. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010-2016 Microchip Technology Inc. DS40001412G-page 21

PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP TQFP QFN UQFN 18 37 37 33 RC3/SCK1/SCL1/AN15 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode (MSSP). SCL1 I/O ST Synchronous serial clock input/output for I2C mode (MSSP). AN15 I Analog Analog input 15. 23 42 42 38 RC4/SDI1/SDA1/AN16 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in (MSSP). SDA1 I/O ST I2C data I/O (MSSP). AN16 I Analog Analog input 16. 24 43 43 39 RC5/SDO1/AN17 RC5 I/O ST Digital I/O. SDO1 O — SPI data out (MSSP). AN17 I Analog Analog input 17. 25 44 44 40 RC6/TX1/CK1/AN18 RC6 I/O ST Digital I/O. TX1 O — EUSART asynchronous transmit. CK1 I/O ST EUSART synchronous clock (see related RXx/ DTx). AN18 I Analog Analog input 18. 26 1 1 1 RC7/RX1/DT1/AN19 RC7 I/O ST Digital I/O. RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data (see related TXx/ CKx). AN19 I Analog Analog input 19. 19 38 38 34 RD0/SCK2/SCL2/AN20 RD0 I/O ST Digital I/O. SCK2 I/O ST Synchronous serial clock input/output for SPI mode (MSSP). SCL2 I/O ST Synchronous serial clock input/output for I2C mode (MSSP). AN20 I Analog Analog input 20. 20 39 39 35 RD1/CCP4/SDI2/SDA2/AN21 RD1 I/O ST Digital I/O. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM 4 output. SDI2 I ST SPI data in (MSSP). SDA2 I/O ST I2C data I/O (MSSP). AN21 I Analog Analog input 21. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. DS40001412G-page 22  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP TQFP QFN UQFN 21 40 40 36 RD2/P2B/AN22 RD2 I/O ST Digital I/O P2B(1) O CMOS Enhanced CCP2 PWM output. AN22 I Analog Analog input 22. 22 41 41 37 RD3/P2C/SS2/AN23 RD3 I/O ST Digital I/O. P2C O CMOS Enhanced CCP2 PWM output. SS2 I TTL SPI slave select input (MSSP). AN23 I Analog Analog input 23. 27 2 2 2 RD4/P2D/SDO2/AN24 RD4 I/O ST Digital I/O. P2D O CMOS Enhanced CCP2 PWM output. SDO2 O — SPI data out (MSSP). AN24 I Analog Analog input 24. 28 3 3 3 RD5/P1B/AN25 RD5 I/O ST Digital I/O. P1B O CMOS Enhanced CCP1 PWM output. AN25 I Analog Analog input 25. 29 4 4 4 RD6/P1C/TX2/CK2/AN26 RD6 I/O ST Digital I/O. P1C O CMOS Enhanced CCP1 PWM output. TX2 O — EUSART asynchronous transmit. CK2 I/O ST EUSART synchronous clock (see related RXx/ DTx). AN26 I Analog Analog input 26. 30 5 5 5 RD7/P1D/RX2/DT2/AN27 RD7 I/O ST Digital I/O. P1D O CMOS Enhanced CCP1 PWM output. RX2 I ST EUSART asynchronous receive. DT2 I/O ST EUSART synchronous data (see related TXx/ CKx). AN27 I Analog Analog input 27. 8 25 25 23 RE0/P3A/CCP3/AN5 RE0 I/O ST Digital I/O. P3A(2) O CMOS Enhanced CCP3 PWM output. CCP3(2) I/O ST Capture 3 input/Compare 3 output/PWM 3 output. AN5 I Analog Analog input 5. 9 26 26 24 RE1/P3B/AN6 RE1 I/O ST Digital I/O. P3B O CMOS Enhanced CCP3 PWM output. AN6 I Analog Analog input 6. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010-2016 Microchip Technology Inc. DS40001412G-page 23

PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP TQFP QFN UQFN 10 27 27 25 RE2/CCP5/AN7 RE2 I/O ST Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output AN7 I Analog Analog input 7. 1 18 18 16 RE3/VPP/MCLR RE3 I ST Digital input. VPP P Programming voltage input. MCLR I ST Active-low Master Clear (device Reset) input. 11,32 7, 28 7, 8, 7, 26 VDD P — Positive supply for logic and I/O pins. 28, 29 12,31 6, 29 6,30, 6, 27 VSS P — Ground reference for logic and I/O pins. 31 12,13, 13 NC 33,34 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. DS40001412G-page 24  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 2.0 OSCILLATOR MODULE (WITH The primary clock module can be configured to provide FAIL-SAFE CLOCK MONITOR) one of six clock sources as the primary clock. 1. RC External Resistor/Capacitor 2.1 Overview 2. LP Low-Power Crystal 3. XT Crystal/Resonator The oscillator module has a wide variety of clock 4. INTOSC Internal Oscillator sources and selection features that allow it to be used in a wide range of applications while maximizing 5. HS High-Speed Crystal/Resonator performance and minimizing power consumption. 6. EC External Clock Figure2-1 illustrates a block diagram of the oscillator The HS and EC oscillator circuits can be optimized for module. power consumption and oscillator speed using settings Clock sources can be configured from external in FOSC<3:0>. Additional FOSC<3:0> selections oscillators, quartz crystal resonators, ceramic resonators enable RA6 to be used as I/O or CLKO (FOSC/4) for and Resistor-Capacitor (RC) circuits. In addition, the RC, EC and INTOSC Oscillator modes. system clock source can be configured from one of three Primary Clock modes are selectable by the internal oscillators, with a choice of speeds selectable via FOSC<3:0> bits of the CONFIG1H Configuration software. Additional clock features include: register. The primary clock operation is further defined • Selectable system clock source between external by these Configuration and register bits: or internal sources via software. 1. PRICLKEN (CONFIG1H<5>) • Two-Speed Start-up mode, which minimizes 2. PRISD (OSCCON2<2>) latency between external oscillator start-up and 3. PLLCFG (CONFIG1H<4>) code execution. 4. PLLEN (OSCTUNE<6>) • Fail-Safe Clock Monitor (FSCM) designed to 5. HFOFST (CONFIG3H<3>) detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch 6. IRCF<2:0> (OSCCON<6:4>) automatically to the internal oscillator. 7. MFIOSEL (OSCCON2<4>) • Oscillator Start-up Timer (OST) ensures stability 8. INTSRC (OSCTUNE<7>) of crystal oscillator sources. The HFINTOSC, MFINTOSC and LFINTOSC are factory calibrated high, medium and low-frequency oscillators, respectively, which are used as the internal clock sources.  2010-2016 Microchip Technology Inc. DS40001412G-page 25

PIC18(L)F2X/4XK22 FIGURE 2-1: SIMPLIFIED OSCILLATOR SYSTEM BLOCK DIAGRAM Secondary Oscillator(1) Low-Power Mode SOSCO Secondary SOSCOUT Event Switch Oscillator (SCS<1:0>) (SOSC) SOSCI 2 Primary Clock Module Secondary Oscillator PRICLKEN 01 PRISD PLL_Select ( 3) (4) EN FOSC<3:0>(5) C lo OSC2 OPsrciimllaatroyr(2) Primary Oscillator 0 4xPLL 0 Primary ck Sw OSC1 (OSC) Clock 00itch INTOSC M 1 1 U X INTOSC 1x Internal Oscillator IRCF<2:0> MFIOSEL INTSRC 3 3 HF-16 MHZ HFINTOSC HF-8 MHZ (16 MHz) HHFF--24 MMHHZZ Inte HF-1 MHZ rn a INTOSC HF-500 kHZ l O Divide HF-250 kHZ sc Circuit HF-31.25 kHZ illato INTOSC MFINTOSC r M U (500 kHz) X MF-500 kHZ (3) MF-250 kHZ MF-31.25 kHZ LFINTOSC LF-31.25 kHz (31.25 kHz) Note1: Details in Figure2-4. 2: Details in Figure2-2. 3: Details in Figure2-3. 4: Details in Table2-1. 5: The Primary Oscillator MUX uses the INTOSC branch when FOSC<3:0> = 100x. DS40001412G-page 26  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 2.2 Oscillator Control 2.2.3 LOW FREQUENCY SELECTION The OSCCON, OSCCON2 and OSCTUNE registers When a nominal output frequency of 31.25kHz is (Register2-1 to Register2-3) control several aspects selected (IRCF<2:0> = 000), users may choose of the device clock’s operation, both in full-power which internal oscillator acts as the source. This is operation and in power-managed modes. done with the INTSRC bit of the OSCTUNE register and MFIOSEL bit of the OSCCON2 register. See • Main System Clock Selection (SCS) Figure2-2 and Register2-1 for specific 31.25kHz • Primary Oscillator Circuit Shutdown (PRISD) selection. This option allows users to select a • Secondary Oscillator Enable (SOSCGO) 31.25kHz clock (MFINTOSC or HFINTOSC) that can • Primary Clock Frequency 4x multiplier (PLLEN) be tuned using the TUN<5:0> bits in OSCTUNE register, while maintaining power savings with a very • Internal Frequency selection bits (IRCF, INTSRC) low clock speed. LFINTOSC always remains the • Clock Status bits (OSTS, HFIOFS, MFIOFS, clock source for features such as the Watchdog Timer LFIOFS. SOSCRUN, PLLRDY) and the Fail-Safe Clock Monitor, regardless of the • Power management selection (IDLEN) setting of INTSRC and MFIOSEL bits 2.2.1 MAIN SYSTEM CLOCK SELECTION This option allows users to select the tunable and more precise HFINTOSC as a clock source, while The System Clock Select bits, SCS<1:0>, select the maintaining power savings with a very low clock speed. main clock source. The available clock sources are • Primary clock defined by the FOSC<3:0> bits of 2.2.4 POWER MANAGEMENT CONFIG1H. The primary clock can be the primary The IDLEN bit of the OSCCON register determines oscillator, an external clock, or the internal whether the device goes into Sleep mode or one of the oscillator block. Idle modes when the SLEEP instruction is executed. • Secondary clock (secondary oscillator) • Internal oscillator block (HFINTOSC, MFINTOSC and LFINTOSC). The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared to select the primary clock on all forms of Reset. 2.2.2 INTERNAL FREQUENCY SELECTION The Internal Oscillator Frequency Select bits (IRCF<2:0>) select the frequency output of the internal oscillator block. The choices are the LFINTOSC source (31.25kHz), the MFINTOSC source (31.25kHz, 250kHz or 500kHz) and the HFINTOSC source (16MHz) or one of the frequencies derived from the HFINTOSC postscaler (31.25kHz to 8MHz). If the internal oscillator block is supplying the main clock, changing the states of these bits will have an immedi- ate change on the internal oscillator’s output. On device Resets, the output frequency of the internal oscillator is set to the default frequency of 1MHz.  2010-2016 Microchip Technology Inc. DS40001412G-page 27

PIC18(L)F2X/4XK22 FIGURE 2-2: INTERNAL OSCILLATOR FIGURE 2-3: PLL_SELECT BLOCK MUX BLOCK DIAGRAM DIAGRAM IRCF<2:0> FOSC<3:0> = 100x MFIOSEL PLLCFG INTSRC 3 PLLEN PLL_Select HF-16 MHZ 111 HF-8 MHZ 110 HF-4 MHZ 101 HF-2 MHZ 100 HF-1 MHZ 011 MF-500 KHZ HF-500 KHZ 1 500 kHZ 010 INTOSC 0 MF-250 KHZ 1 250 kHZ 001 HF-250 KHZ 0 HF-31.25 KHZ 11 MF-31.25 KHZ 10 31.25 kHZ 000 LF-31.25 KHZ 0X TABLE 2-1: PLL_SELECT TRUTH TABLE Primary Clock MUX Source FOSC<3:0> PLLCFG PLLEN PLL_Select FOSC (any source) 0000-1111 0 0 0 OSC1/OSC2 (external source) 0000-0111 1 x 1 1010-1111 0 1 1 INTOSC (internal source) 1000-1001 x 0 0 x 1 1 DS40001412G-page 28  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 2-4: SECONDARY OSCILLATOR AND EXTERNAL CLOCK INPUTS SOSCEN SOSCGO T1SOSCEN T3SOSCEN T5SOSCEN To Clock Switch Module EN SOSCI Secondary SOSCOUT Oscillator SOSCO T1CKI 1 T3G SOSCEN T1CLK_EXT_SRC T3CKI 0 T1SOSCEN SOSCEN T3G SOSCEN 1 0 T3CLK_EXT_SRC 0 T3CKI 1 T3SOSCEN T1G T3CMX T1G 1 T5CLK_EXT_SRC T5CKI 0 T5SOSCEN T5G T5G  2010-2016 Microchip Technology Inc. DS40001412G-page 29

PIC18(L)F2X/4XK22 2.3 Register Definitions: Oscillator Control REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R-q R-0 R/W-0 R/W-0 IDLEN IRCF<2:0> OSTS(1) HFIOFS SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF<2:0>: Internal RC Oscillator Frequency Select bits(2) 111 = HFINTOSC – (16 MHz) 110 = HFINTOSC/2 – (8 MHz) 101 = HFINTOSC/4 – (4 MHz) 100 = HFINTOSC/8 – (2 MHz) 011 = HFINTOSC/16 – (1 MHz)(3) If INTSRC = 0 and MFIOSEL = 0: 010 = HFINTOSC/32 – (500 kHz) 001 = HFINTOSC/64 – (250 kHz) 000 = LFINTOSC – (31.25 kHz) If INTSRC = 1 and MFIOSEL = 0: 010 = HFINTOSC/32 – (500 kHz) 001 = HFINTOSC/64 – (250 kHz) 000 = HFINTOSC/512 – (31.25 kHz) If INTSRC = 0 and MFIOSEL = 1: 010 = MFINTOSC – (500 kHz) 001 = MFINTOSC/2 – (250 kHz) 000 = LFINTOSC – (31.25 kHz) If INTSRC = 1 and MFIOSEL = 1: 010 = MFINTOSC – (500 kHz) 001 = MFINTOSC/2 – (250 kHz) 000 = MFINTOSC/16 – (31.25 kHz) bit 3 OSTS: Oscillator Start-up Time-out Status bit 1 = Device is running from the clock defined by FOSC<3:0> of the CONFIG1H register 0 = Device is running from the internal oscillator (HFINTOSC, MFINTOSC or LFINTOSC) bit 2 HFIOFS: HFINTOSC Frequency Stable bit 1 = HFINTOSC frequency is stable 0 = HFINTOSC frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bit 1x = Internal oscillator block 01 = Secondary (SOSC) oscillator 00 = Primary clock (determined by FOSC<3:0> in CONFIG1H). Note 1: Reset state depends on state of the IESO Configuration bit. 2: INTOSC source may be determined by the INTSRC bit in OSCTUNE and the MFIOSEL bit in OSCCON2. 3: Default output frequency of HFINTOSC on Reset. DS40001412G-page 30  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 2-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 R-0/0 R-0/q U-0 R/W-0/0 R/W-0/u R/W-1/1 R-x/u R-0/0 PLLRDY SOSCRUN — MFIOSEL SOSCGO(1) PRISD MFIOFS LFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7 PLLRDY: PLL Run Status bit 1 = System clock comes from 4xPLL 0 = System clock comes from an oscillator, other than 4xPLL bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from secondary SOSC 0 = System clock comes from an oscillator, other than SOSC bit 5 Unimplemented: Read as ‘0’. bit 4 MFIOSEL: MFINTOSC Select bit 1 = MFINTOSC is used in place of HFINTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz 0 = MFINTOSC is not used bit 3 SOSCGO(1): Secondary Oscillator Start Control bit 1 = Secondary oscillator is enabled. 0 = Secondary oscillator is shut off if no other sources are requesting it. bit 2 PRISD: Primary Oscillator Drive Circuit Shutdown bit 1 = Oscillator drive circuit on 0 = Oscillator drive circuit off (zero power) bit 1 MFIOFS: MFINTOSC Frequency Stable bit 1 = MFINTOSC is stable 0 = MFINTOSC is not stable bit 0 LFIOFS: LFINTOSC Frequency Stable bit 1 = LFINTOSC is stable 0 = LFINTOSC is not stable Note 1: The SOSCGO bit is only reset on a POR Reset.  2010-2016 Microchip Technology Inc. DS40001412G-page 31

PIC18(L)F2X/4XK22 2.4 Clock Source Modes 2.5 External Clock Modes Clock Source modes can be classified as external or 2.5.1 OSCILLATOR START-UP TIMER (OST) internal. When the oscillator module is configured for LP, XT or • External Clock modes rely on external circuitry for HS modes, the Oscillator Start-up Timer (OST) counts the clock source. Examples are: Clock modules 1024 oscillations from OSC1. This occurs following a (EC mode), quartz crystal resonators or ceramic Power-on Reset (POR) and when the Power-up Timer resonators (LP, XT and HS modes) and Resistor- (PWRT) has expired (if configured), or a wake-up from Capacitor (RC mode) circuits. Sleep. During this time, the program counter does not • Internal clock sources are contained internally increment and program execution is suspended. The within the Oscillator block. The Oscillator block OST ensures that the oscillator circuit, using a quartz has three internal oscillators: the 16MHz High- crystal resonator or ceramic resonator, has started and Frequency Internal Oscillator (HFINTOSC), is providing a stable system clock to the oscillator 500kHz Medium-Frequency Internal Oscillator module. When switching between clock sources, a (MFINTOSC) and the 31.25kHz Low-Frequency delay is required to allow the new clock to stabilize. Internal Oscillator (LFINTOSC). These oscillator delays are shown in Table2-2. The system clock can be selected between external or In order to minimize latency between external oscillator internal clock sources via the System Clock Select start-up and code execution, the Two-Speed Clock (SCS<1:0>) bits of the OSCCON register. See Start-up mode can be selected (see Section2.12 Section2.11 “Clock Switching” for additional “Two-Speed Clock Start-up Mode”). information. TABLE 2-2: OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Oscillator Delay LFINTOSC 31.25kHz Sleep/POR/BOR MFINTOSC 31.25kHz to 500kHz Oscillator Start-up Delay (TIOSC_ST) HFINTOSC 31.25kHz to 16MHz Sleep/POR/BOR EC, RC DC – 64MHz 2 instruction cycles LFINTOSC (31.25kHz) EC, RC DC – 64MHz 1 cycle of each Sleep/POR/BOR LP, XT, HS 32kHz to 40MHz 1024 Clock Cycles (OST) Sleep/POR/BOR 4xPLL 32MHz to 64MHz 1024 Clock Cycles (OST) + 2 ms LFINTOSC (31.25kHz) LFINTOSC 31.25kHz to 16MHz 1s (approx.) HFINTOSC 2.5.2 EC MODE Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the The External Clock (EC) mode allows an externally device while leaving all data intact. Upon restarting the generated logic level as the system clock source. When external clock, the device will resume operation as if no operating in this mode, an external clock source is time had elapsed. connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure2-5 shows the pin FIGURE 2-5: EXTERNAL CLOCK (EC) connections for EC mode. MODE OPERATION The External Clock (EC) offers different power modes, Low Power (ECLP), Medium Power (ECMP) and High Power (ECHP), selectable by the FOSC<3:0> bits. Clock from OSC1/CLKIN Each mode is best suited for a certain range of Ext. System PIC® MCU frequencies. The ranges are: • ECLP – below 500kHz I/O OSC2/CLKOUT(1) • ECMP – between 500kHz and 16MHz • ECHP – above 16MHz Note 1: Alternate pin functions are listed in The Oscillator Start-up Timer (OST) is disabled when Section1.0 “Device Overview”. EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. DS40001412G-page 32  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 2.5.3 LP, XT, HS MODES Note 1: Quartz crystal characteristics vary The LP, XT and HS modes support the use of quartz according to type, package and crystal resonators or ceramic resonators connected to manufacturer. The user should consult the OSC1 and OSC2 (Figure2-6). The mode selects a low, manufacturer data sheets for specifications medium or high gain setting of the internal inverter- and recommended application. amplifier to support various resonator types and speed. 2: Always verify oscillator performance over LP Oscillator mode selects the lowest gain setting of the the VDD and temperature range that is internal inverter-amplifier. LP mode current consumption expected for the application. is the least of the three modes. This mode is best suited 3: For oscillator design assistance, refer to the to drive resonators with a low drive level specification, for following Microchip Application Notes: example, tuning fork type crystals. • AN826, “Crystal Oscillator Basics and XT Oscillator mode selects the intermediate gain Crystal Selection for rfPIC® and PIC® setting of the internal inverter-amplifier. XT mode Devices” (DS00826) current consumption is the medium of the three modes. • AN849, “Basic PIC® Oscillator Design” This mode is best suited to drive resonators with a (DS00849) medium drive level specification. • AN943, “Practical PIC® Oscillator HS Oscillator mode offers a Medium Power (MP) and a Analysis and Design” (DS00943) High Power (HP) option selectable by the FOSC<3:0> • AN949, “Making Your Oscillator Work” bits. The MP selections are best suited for oscillator (DS00949) frequencies between 4 MHz and 16MHz. The HP selection has the highest gain setting of the internal inverter-amplifier and is best suited for frequencies FIGURE 2-7: CERAMIC RESONATOR above 16MHz. HS mode is best suited for resonators OPERATION that require a high drive setting. (XT OR HS MODE) FIGURE 2-6: QUARTZ CRYSTAL PIC® MCU OPERATION (LP, XT OR HS MODE) OSC1/CLKIN C1 To Internal PIC® MCU Logic OSC1/CLKIN RP(3) RF(2) Sleep C1 To Internal Logic Quartz RF(2) Sleep C2 Ceramic RS(1) OSC2/CLKOUT Crystal Resonator Note 1: A series resistor (RS) may be required for C2 RS(1) OSC2/CLKOUT ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator 2: The value of RF varies with the Oscillator mode operation. selected (typically between 2M to 10M.  2010-2016 Microchip Technology Inc. DS40001412G-page 33

PIC18(L)F2X/4XK22 2.5.4 EXTERNAL RC MODES 2.6 Internal Clock Modes The external Resistor-Capacitor (RC) modes support The oscillator module has three independent, internal the use of an external RC circuit. This allows the oscillators that can be configured or selected as the designer maximum flexibility in frequency choice while system clock source. keeping costs to a minimum when clock accuracy is not 1. The HFINTOSC (High-Frequency Internal required. There are two modes: RC and RCIO. Oscillator) is factory calibrated and operates at 2.5.4.1 RC Mode 16MHz. The frequency of the HFINTOSC can be user-adjusted via software using the In RC mode, the RC circuit connects to OSC1. OSC2/ OSCTUNE register (Register2-3). CLKOUT outputs the RC oscillator frequency divided 2. The MFINTOSC (Medium-Frequency Internal by four. This signal may be used to provide a clock for Oscillator) is factory calibrated and operates external circuitry, synchronization, calibration, test or at 500kHz. The frequency of the MFINTOSC other application requirements. Figure2-8 shows the can be user-adjusted via software using the external RC mode connections. OSCTUNE register (Register2-3). FIGURE 2-8: EXTERNAL RC MODES 3. The LFINTOSC (Low-Frequency Internal Oscillator) is factory calibrated and operates at 31.25kHz. The LFINTOSC cannot be user- VDD PIC® MCU adjusted, but is designed to be stable over temperature and voltage. REXT The system clock speed can be selected via software OSC1/CLKIN Internal using the Internal Oscillator Frequency select bits Clock IRCF<2:0> of the OSCCON register. CEXT The system clock can be selected between external or VSS internal clock sources via the System Clock Selection FOSC/4 or OSC2/CLKOUT(1) (SCS<1:0>) bits of the OSCCON register. See I/O(2) Section2.11 “Clock Switching” for more information. 2.6.1 INTOSC WITH I/O OR CLOCKOUT Recommended values: 10 k  REXT  100 k CEXT > 20 pF Two of the clock modes selectable with the FOSC<3:0> bits of the CONFIG1H Configuration register configure the internal oscillator block as the primary oscillator. Note 1: Alternate pin functions are listed in Mode selection determines whether the OSC2/ Section1.0 “Device Overview”. CLKOUT pin will be configured as general purpose I/O 2: Output depends upon RC or RCIO clock mode. or FOSC/4 (CLKOUT). In both modes, the OSC1/CLKIN pin is configured as general purpose I/O. See 2.5.4.2 RCIO Mode Section24.0 “Special Features of the CPU” for more In RCIO mode, the RC circuit is connected to OSC1. information. OSC2 becomes a general purpose I/O pin. The CLKOUT signal may be used to provide a clock for The RC oscillator frequency is a function of the supply external circuitry, synchronization, calibration, test or voltage, the resistor (REXT) and capacitor (CEXT) values other application requirements. and the operating temperature. Other factors affecting the oscillator frequency are: • input threshold voltage variation • component tolerances • packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. DS40001412G-page 34  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 2.6.1.1 OSCTUNE Register The OSCTUNE register also implements the INTSRC and PLLEN bits, which control certain features of the The HFINTOSC/MFINTOSC oscillator circuits are internal oscillator block. factory calibrated but can be adjusted in software by writing to the TUN<5:0> bits of the OSCTUNE register The INTSRC bit allows users to select which internal (Register2-3). oscillator provides the clock source when the 31.25kHz frequency option is selected. This is covered The default value of the TUN<5:0> is ‘000000’. The in greater detail in Section2.2.3 “Low Frequency value is a 6-bit two’s complement number. Selection”. When the OSCTUNE register is modified, the The PLLEN bit controls the operation of the frequency HFINTOSC/MFINTOSC frequency will begin shifting to multiplier, PLL, for all primary external clock sources the new frequency. Code execution continues during this and internal oscillator modes. However, the PLL is shift. There is no indication that the shift has occurred. intended for operation with clock sources between The TUN<5:0> bits in OSCTUNE do not affect the 4MHz and 16MHz. For more details about the function LFINTOSC frequency. Operation of features that of the PLLEN bit, see Section2.8.2 “PLL in HFIN- depend on the LFINTOSC clock source frequency, such TOSC Modes” as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. 2.7 Register Definitions: Oscillator Tuning REGISTER 2-3: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock derived from the MFINTOSC or HFINTOSC source 0 = 31.25kHz device clock derived directly from LFINTOSC internal oscillator bit 6 PLLEN: Frequency Multiplier 4xPLL for HFINTOSC Enable bit(1) 1 = PLL enabled 0 = PLL disabled bit 5-0 TUN<5:0>: Frequency Tuning bits – use to adjust MFINTOSC and HFINTOSC frequencies 011111 = Maximum frequency 011110 = • • • 000001 = 000000 = Oscillator module (HFINTOSC and MFINTOSC) are running at the factory calibrated frequency. 111111 = • • • 100000 = Minimum frequency Note 1: The PLLEN bit is active for all the primary clock sources (internal or external) and is designed to operate with clock frequencies between 4MHz and 16MHz.  2010-2016 Microchip Technology Inc. DS40001412G-page 35

PIC18(L)F2X/4XK22 2.7.1 LFINTOSC 2.7.3.1 Compensating with the EUSART The Low-Frequency Internal Oscillator (LFINTOSC) is An adjustment may be required when the EUSART a 31.25kHz internal clock source. The LFINTOSC is begins to generate framing errors or receives data with not tunable, but is designed to be stable across errors while in Asynchronous mode. Framing errors temperature and voltage. See Section27.0 indicate that the device clock frequency is too high; to “Electrical Specifications” for the LFINTOSC adjust for this, decrement the value in OSCTUNE to accuracy specifications. reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to The output of the LFINTOSC can be a clock source to compensate, increment OSCTUNE to increase the the primary clock or the INTOSC clock (see Figure2-1). clock frequency. The LFINTOSC is also the clock source for the Power- up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe 2.7.3.2 Compensating with the Timers Clock Monitor (FSCM). This technique compares device clock speed to some 2.7.2 FREQUENCY SELECT BITS (IRCF) reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is The HFINTOSC (16MHz) and MFINTOSC (500MHz) clocked by a fixed reference source, such as the outputs connect to a divide circuit that provides Timer1 oscillator. frequencies of 16MHz to 31.25kHz. These divide circuit frequencies, along with the 31.25kHz Both timers are cleared, but the timer clocked by the LFINTOSC output, are multiplexed to provide a single reference generates interrupts. When an interrupt INTOSC clock output (see Figure2-1). The IRCF<2:0> occurs, the internally clocked timer is read and both bits of the OSCCON register, the MFIOSEL bit of the timers are cleared. If the internally clocked timer value OSCCON2 register and the INTSRC bit of the is greater than expected, then the internal oscillator OSCTUNE register, select the output frequency of the block is running too fast. To adjust for this, decrement internal oscillators. One of eight frequencies can be the OSCTUNE register. selected via software: 2.7.3.3 Compensating with the CCP Module • 16 MHz in Capture Mode • 8 MHz A CCP module can use free running Timer1, Timer3 or • 4 MHz Timer5 clocked by the internal oscillator block and an • 2 MHz external event with a known period (i.e., AC power • 1 MHz (default after Reset) frequency). The time of the first event is captured in the • 500 kHz (MFINTOSC or HFINTOSC) CCPRxH:CCPRxL registers and is recorded for use later. • 250 kHz (MFINTOSC or HFINTOSC) When the second event causes a capture, the time of the first event is subtracted from the time of the second • 31 kHz (LFINTOSC, MFINTOSC or HFINTOSC) event. Since the period of the external event is known, 2.7.3 INTOSC FREQUENCY DRIFT the time difference between events can be calculated. The factory calibrates the internal oscillator block outputs If the measured time is much greater than the (HFINTOSC/MFINTOSC) for 16MHz/500kHz. However, calculated time, the internal oscillator block is running this frequency may drift as VDD or temperature changes. too fast; to compensate, decrement the OSCTUNE It is possible to adjust the HFINTOSC/MFINTOSC register. If the measured time is much less than the frequency by modifying the value of the TUN<5:0> bits in calculated time, the internal oscillator block is running the OSCTUNE register. This has no effect on the too slow; to compensate, increment the OSCTUNE LFINTOSC clock source frequency. register. Tuning the HFINTOSC/MFINTOSC source requires knowing when to make the adjustment, in which direction it should be made and, in some cases, how large a change is needed. Three possible compensation techniques are discussed in the following sections. However, other techniques may be used. DS40001412G-page 36  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 2.8 PLL Frequency Multiplier A Phase-Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from the crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 2.8.1 PLL IN EXTERNAL OSCILLATOR MODES The PLL can be enabled for any of the external oscillator modes using the OSC1/OSC2 pins by either setting the PLLCFG bit (CONFIG1H<4>), or setting the PLLEN bit (OSCTUNE<6>). The PLL is designed for input frequencies of 4 MHz up to 16 MHz. The PLL then multiplies the oscillator output frequency by four to produce an internal clock frequency up to 64 MHz. Oscillator frequencies below 4 MHz should not be used with the PLL. 2.8.2 PLL IN HFINTOSC MODES The 4x frequency multiplier can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with the internal oscillator. When enabled, the PLL multiplies the HFINTOSC by four to produce clock rates up to 64MHz. Unlike external clock modes, when internal clock modes are enabled, the PLL can only be controlled through software. The PLLEN control bit of the OSCTUNE register is used to enable or disable the PLL operation when the HFINTOSC is used. The PLL is designed for input frequencies of 4MHz up to 16MHz.  2010-2016 Microchip Technology Inc. DS40001412G-page 37

PIC18(L)F2X/4XK22 2.9 Effects of Power-Managed Modes 2.10 Power-up Delays on the Various Clock Sources Power-up delays are controlled by two timers, so that For more information about the modes discussed in this no external Reset circuitry is required for most section see Section3.0 “Power-Managed Modes”. A applications. The delays ensure that the device is kept quick reference list is also available in Table3-1. in Reset until the device power supply is stable under normal circumstances and the primary clock is When PRI_IDLE mode is selected, the designated operating and stable. For additional information on primary oscillator continues to run without interruption. power-up delays, see Section4.6 “Device Reset For all other power-managed modes, the oscillator Timers”. using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up. It is enabled by In secondary clock modes (SEC_RUN and clearing (= 0) the PWRTEN Configuration bit. SEC_IDLE), the secondary oscillator (SOSC) is operating and providing the device clock. The The second timer is the Oscillator Start-up Timer secondary oscillator may also run in all power- (OST), intended to keep the chip in Reset until the managed modes if required to clock Timer1, Timer3 or crystal oscillator is stable (LP, XT and HS modes). The Timer5. OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. In internal oscillator modes (INTOSC_RUN and INTOSC_IDLE), the internal oscillator block provides When the PLL is enabled with external oscillator the device clock source. The 31.25kHz LFINTOSC modes, the device is kept in Reset for an additional output can be used directly to provide the clock and 2ms, following the OST delay, so the PLL can lock to may be enabled to support various special features, the incoming clock frequency. regardless of the power-managed mode (see There is a delay of interval TCSD, following POR, while Section24.3 “Watchdog Timer (WDT)”, the controller becomes ready to execute instructions. Section2.12 “Two-Speed Clock Start-up Mode” and This delay runs concurrently with any other delays. Section2.13 “Fail-Safe Clock Monitor” for more This may be the only delay that occurs when any of the information on WDT, Fail-Safe Clock Monitor and Two- EC, RC or INTIOSC modes are used as the primary Speed Start-up). The HFINTOSC and MFINTOSC clock source. outputs may be used directly to clock the device or may When the HFINTOSC is selected as the primary clock, be divided down by the postscaler. The HFINTOSC the main system clock can be delayed until the and MFINTOSC outputs are disabled when the clock is HFINTOSC is stable. This is user selectable by the provided directly from the LFINTOSC output. HFOFST bit of the CONFIG3H Configuration register. When the Sleep mode is selected, all clock sources are When the HFOFST bit is cleared, the main system stopped. Since all the transistor switching currents clock is delayed until the HFINTOSC is stable. When have been stopped, Sleep mode achieves the lowest the HFOFST bit is set, the main system clock starts current consumption of the device (only leakage immediately. currents). In either case, the HFIOFS bit of the OSCCON register Enabling any on-chip feature that will operate during can be read to determine whether the HFINTOSC is Sleep will increase the current consumed during Sleep. operating and stable. The LFINTOSC is required to support WDT operation. Other features may be operating that do not require a device clock source (i.e., SSP slave, PSP, INTn pins and others). Peripherals that may add significant current consumption are listed in Section27.8 “DC Characteristics: Input/Output Characteristics, PIC18(L)F2X/4XK22”. DS40001412G-page 38  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTOSC with CLKOUT Floating, external resistor should pull high At logic low (clock/4 output) RC with IO Floating, external resistor should pull high Configured as PORTA, bit 6 INTOSC with IO Configured as PORTA, bit 7 Configured as PORTA, bit 6 EC with IO Floating, pulled by external clock Configured as PORTA, bit 6 EC with CLKOUT Floating, pulled by external clock At logic low (clock/4 output) LP, XT, HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table4-2 in Section4.0 “Reset” for time-outs due to Sleep and MCLR Reset. 2.11 Clock Switching After a Reset, the SCS<1:0> bits of the OSCCON register are always cleared. The system clock source can be switched between external and internal clock sources via software using Note: Any automatic clock switch, which may the System Clock Select (SCS<1:0>) bits of the occur from Two-Speed Start-up or Fail- OSCCON register. Safe Clock Monitor, does not update the SCS<1:0> bits of the OSCCON register. PIC18(L)F2X/4XK22 devices contain circuitry to pre- The user can monitor the SOSCRUN, vent clock “glitches” when switching between clock MFIOFS and LFIOFS bits of the sources. A short pause in the device clock occurs OSCCON2 register, and the HFIOFS and during the clock switch. The length of this pause is the OSTS bits of the OSCCON register to sum of two cycles of the old clock source and three to determine the current system clock source. four cycles of the new clock source. This formula assumes that the new clock source is stable. 2.11.2 OSCILLATOR START-UP TIME-OUT Clock transitions are discussed in greater detail in STATUS (OSTS) BIT Section3.1.2 “Entering Power-Managed Modes”. The Oscillator Start-up Time-out Status (OSTS) bit of 2.11.1 SYSTEM CLOCK SELECT the OSCCON register indicates whether the system (SCS<1:0>) BITS clock is running from the external clock source, as defined by the FOSC<3:0> bits in the CONFIG1H The System Clock Select (SCS<1:0>) bits of the Configuration register, or from the internal clock OSCCON register select the system clock source that source. In particular, when the primary oscillator is the is used for the CPU and peripherals. source of the primary clock, OSTS indicates that the • When SCS<1:0> = 00, the system clock source is Oscillator Start-up Timer (OST) has timed out for LP, determined by configuration of the FOSC<3:0> XT or HS modes. bits in the CONFIG1H Configuration register. • When SCS<1:0> = 10, the system clock source is chosen by the internal oscillator frequency selected by the INTSRC bit of the OSCTUNE register, the MFIOSEL bit of the OSCCON2 register and the IRCF<2:0> bits of the OSCCON register. • When SCS<1:0> = 01, the system clock source is the 32.768 kHz secondary oscillator shared with Timer1, Timer3 and Timer5.  2010-2016 Microchip Technology Inc. DS40001412G-page 39

PIC18(L)F2X/4XK22 2.11.3 CLOCK SWITCH TIMING 2.12 Two-Speed Clock Start-up Mode When switching between one oscillator and another, Two-Speed Start-up mode provides additional power the new oscillator may not be operating which saves savings by minimizing the latency between external power (see Figure2-9). If this is the case, there is a oscillator start-up and code execution. In applications delay after the SCS<1:0> bits of the OSCCON register that make heavy use of the Sleep mode, Two-Speed are modified before the frequency change takes place. Start-up will remove the external oscillator start-up The OSTS and IOFS bits of the OSCCON register will time from the time spent awake and can reduce the reflect the current active status of the external and overall power consumption of the device. HFINTOSC oscillators. The timing of a frequency This mode allows the application to wake-up from selection is as follows: Sleep, perform a few instructions using the HFINTOSC 1. SCS<1:0> bits of the OSCCON register are mod- as the clock source and go back to Sleep without ified. waiting for the primary oscillator to become stable. 2. The old clock continues to operate until the new clock is ready. 3. Clock switch circuitry waits for two consecutive Note: Executing a SLEEP instruction will abort rising edges of the old clock after the new clock the oscillator start-up time and will cause ready signal goes true. the OSTS bit of the OSCCON register to remain clear. 4. The system clock is held low starting at the next falling edge of the old clock. When the oscillator module is configured for LP, XT or 5. Clock switch circuitry waits for an additional two HS modes, the Oscillator Start-up Timer (OST) is rising edges of the new clock. enabled (see Section2.5.1 “Oscillator Start-up Timer 6. On the next falling edge of the new clock the low (OST)”). The OST will suspend program execution until hold on the system clock is released and new 1024 oscillations are counted. Two-Speed Start-up clock is switched in as the system clock. mode minimizes the delay in code execution by operating from the internal oscillator as the OST is 7. Clock switch is complete. counting. When the OST count reaches 1024 and the See Figure2-1 for more details. OSTS bit of the OSCCON register is set, program If the HFINTOSC is the source of both the old and new execution switches to the external oscillator. frequency, there is no start-up delay before the new 2.12.1 TWO-SPEED START-UP MODE frequency is active. This is because the old and new frequencies are derived from the HFINTOSC via the CONFIGURATION postscaler and multiplexer. Two-Speed Start-up mode is enabled when all of the Start-up delay specifications are located in following settings are configured as noted: Section27.0 “Electrical Specifications”, under AC • Two-Speed Start-up mode is enabled when the Specifications (Oscillator Module). IESO of the CONFIG1H Configuration register is set. • SCS<1:0> (of the OSCCON register) = 00. • FOSC<2:0> bits of the CONFIG1H Configuration register are configured for LP, XT or HS mode. Two-Speed Start-up mode becomes active after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep. DS40001412G-page 40  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 2.12.2 TWO-SPEED START-UP 2.12.3 CHECKING TWO-SPEED CLOCK SEQUENCE STATUS 1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCCON 2. Instructions begin executing by the internal register will confirm if the microcontroller is running oscillator at the frequency set in the IRCF<2:0> from the external clock source, as defined by the bits of the OSCCON register. FOSC<2:0> bits in CONFIG1H Configuration register, or the internal oscillator. OSTS = 0 when the external 3. OST enabled to count 1024 external clock oscillator is not ready, which indicates that the system cycles. is running from the internal oscillator. 4. OST timed out. External clock is ready. 5. OSTS is set. 6. Clock switch finishes according to Figure2-9 FIGURE 2-9: CLOCK SWITCH TIMING High Speed Low Speed Old Clock Start-up Time(1) Clock Sync Running New Clock New Clk Ready IRCF <2:0> Select Old Select New System Clock Low Speed High Speed Old Clock Start-up Time(1) Clock Sync Running New Clock New Clk Ready IRCF <2:0>Select Old Select New System Clock Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.  2010-2016 Microchip Technology Inc. DS40001412G-page 41

PIC18(L)F2X/4XK22 2.13 Fail-Safe Clock Monitor 2.13.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared by either one of the to continue operating should the external oscillator fail. following: The FSCM can detect oscillator failure any time after • Any Reset the Oscillator Start-up Timer (OST) has expired. The • By toggling the SCS1 bit of the OSCCON register FSCM is enabled by setting the FCMEN bit in the Both of these conditions restart the OST. While the CONFIG1H Configuration register. The FSCM is OST is running, the device continues to operate from applicable to all external oscillator modes (LP, XT, HS, the INTOSC selected in OSCCON. When the OST EC, RC and RCIO). times out, the Fail-Safe condition is cleared and the device automatically switches over to the external clock FIGURE 2-10: FSCM BLOCK DIAGRAM source. The Fail-Safe condition need not be cleared before the OSCFIF flag is cleared. Clock Monitor Latch External 2.13.4 RESET OR WAKE-UP FROM SLEEP S Q Clock The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after LFINTOSC Oscillator ÷ 64 R Q any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as 31 kHz 488 Hz soon as the Reset or wake-up has completed. (~32 s) (~2 ms) Sample Clock Clock Note: Due to the wide range of oscillator start-up Failure times, the Fail-Safe circuit is not active Detected during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate 2.13.1 FAIL-SAFE DETECTION amount of time, the user should check the OSTS bit of the OSCCON register to verify The FSCM module detects a failed oscillator by the oscillator start-up and that the system comparing the external oscillator to the FSCM sample clock switchover has successfully clock. The sample clock is generated by dividing the completed. LFINTOSC by 64 (see Figure2-10). Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The Note: When the device is configured for Fail- sample clock clears the latch on each rising edge of the Safe clock monitoring in either HS, XT, or sample clock. A failure is detected when an entire half- LS Oscillator modes then the IESO config- cycle of the sample clock elapses before the primary uration bit should also be set so that the clock goes low. clock will automatically switch from the internal clock to the external oscillator 2.13.2 FAIL-SAFE OPERATION when the OST times out. When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSCFIF of the PIR2 register. The OSCFIF flag will generate an interrupt if the OSCFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. An automatic transition back to the failed clock source will not occur. The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. DS40001412G-page 42  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 2-11: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 2-4: REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 OSCCON IDLEN IRCF<2:0> OSTS HFIOFS SCS<1:0> 30 OSCCON2 PLLRDY SOSCRUN — MFIOSEL SOSCGO PRISD MFIOFS LFIOFS 31 OSCTUNE INTSRC PLLEN TUN<5:0> 35 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by clock sources. TABLE 2-5: CONFIGURATION REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG1H IESO FCMEN PRICLKEN PLLCFG FOSC<3:0> 345 CONFIG2L — — — BORV<1:0> BOREN<1:0> PWRTEN 346 CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for clock sources.  2010-2016 Microchip Technology Inc. DS40001412G-page 43

PIC18(L)F2X/4XK22 3.0 POWER-MANAGED MODES 3.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three PIC18(L)F2X/4XK22 devices offer a total of seven clock sources for power-managed modes. They are: operating modes for more efficient power management. These modes provide a variety of • the primary clock, as defined by the FOSC<3:0> options for selective power conservation in applications Configuration bits where resources may be limited (i.e., battery-powered • the secondary clock (the SOSC oscillator) devices). • the internal oscillator block There are three categories of power-managed modes: 3.1.2 ENTERING POWER-MANAGED • Run modes MODES • Idle modes Switching from one power-managed mode to another • Sleep mode begins by loading the OSCCON register. The These categories define which portions of the device SCS<1:0> bits select the clock source and determine are clocked and sometimes, what speed. The Run and which Run or Idle mode is to be used. Changing these Idle modes may use any of the three available clock bits causes an immediate switch to the new clock sources (primary, secondary or internal oscillator source, assuming that it is running. The switch may block). The Sleep mode does not use a clock source. also be subject to clock transition delays. Refer to The power-managed modes include several power- Section2.11 “Clock Switching” for more information. saving features offered on previous PIC® microcontroller Entry to the power-managed Idle or Sleep modes is devices. One of the clock switching features allows the triggered by the execution of a SLEEP instruction. The controller to use the secondary oscillator (SOSC) in actual mode that results depends on the status of the place of the primary oscillator. Also included is the Sleep IDLEN bit. mode, offered by all PIC microcontroller devices, where Depending on the current mode and the mode being all device clocks are stopped. switched to, a change to a power-managed mode does not always require setting all of these bits. Many 3.1 Selecting Power-Managed Modes transitions may be done by changing the oscillator select Selecting a power-managed mode requires two bits, or changing the IDLEN bit, prior to issuing a SLEEP decisions: instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP • Whether or not the CPU is to be clocked instruction to switch to the desired mode. • The selection of a clock source The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table3-1. TABLE 3-1: POWER-MANAGED MODES OSCCON Bits Module Clocking Mode Available Clock and Oscillator Source IDLEN(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, RC, EC and Internal Oscillator Block(2). This is the normal full-power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – SOSC Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – SOSC Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source. DS40001412G-page 44  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 3.1.3 MULTIPLE FUNCTIONS OF THE Figure3-2). When the clock switch is complete, the SLEEP COMMAND SOSCRUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and The power-managed mode that is invoked with the SCS bits are not affected by the wake-up and the SLEEP instruction is determined by the value of the SOSC oscillator continues to run. IDLEN bit at the time the instruction is executed. If IDLEN = 0, when SLEEP is executed, the device enters the Sleep mode and all clocks stop and minimum 3.2.3 RC_RUN MODE power is consumed. If IDLEN = 1, when SLEEP is In RC_RUN mode, the CPU and peripherals are executed, the device enters the IDLE mode and the clocked from the internal oscillator block using the system clock continues to supply a clock to the INTOSC multiplexer. In this mode, the primary clock is peripherals but is disconnected from the CPU. shut down. When using the LFINTOSC source, this mode provides the best power conservation of all the 3.2 Run Modes Run modes, while still executing code. It works well for user applications which are not highly timing-sensitive In the Run modes, clocks to both the core and or do not require high-speed clocks at all times. If the peripherals are active. The difference between these primary clock source is the internal oscillator block – modes is the clock source. either LFINTOSC or INTOSC (MFINTOSC or 3.2.1 PRI_RUN MODE HFINTOSC) – there are no distinguishable differences between the PRI_RUN and RC_RUN modes during The PRI_RUN mode is the normal, full-power execution. Entering or exiting RC_RUN mode, execution mode of the microcontroller. This is also the however, causes a clock switch delay. Therefore, if the default mode upon a device Reset, unless Two-Speed primary clock source is the internal oscillator block, Start-up is enabled (see Section2.12 “Two-Speed using RC_RUN mode is not recommended. Clock Start-up Mode” for details). In this mode, the This mode is entered by setting the SCS1 bit to ‘1’. To device is operated off the oscillator defined by the maintain software compatibility with future devices, it is FOSC<3:0> bits of the CONFIG1H Configuration recommended that the SCS0 bit also be cleared, even register. though the bit is ignored. When the clock source is 3.2.2 SEC_RUN MODE switched to the INTOSC multiplexer (see Figure3-1), the primary oscillator is shut down and the OSTS bit is In SEC_RUN mode, the CPU and peripherals are cleared. The IRCF<2:0> bits (OSCCON<6:4>) may be clocked from the secondary external oscillator. This modified at any time to immediately change the clock gives users the option of lower power consumption speed. while still using a high accuracy clock source. When the IRCF bits and the INTSRC bit are all clear, SEC_RUN mode is entered by setting the SCS<1:0> the INTOSC output (HFINTOSC/MFINTOSC) is not bits to ‘01’. When SEC_RUN mode is active, all of the enabled and the HFIOFS and MFIOFS bits will remain following are true: clear. There will be no indication of the current clock • The device clock source is switched to the SOSC source. The LFINTOSC source is providing the device oscillator (see Figure3-1) clocks. • The primary oscillator is shut down If the IRCF bits are changed from all clear (thus, • The SOSCRUN bit (OSCCON2<6>) is set enabling the INTOSC output) or if INTSRC or MFIOSEL • The OSTS bit (OSCCON2<3>) is cleared is set, then the HFIOFS or MFIOFS bit is set after the INTOSC output becomes stable. For details, see Table3-2. Note: The secondary external oscillator should Clocks to the device continue while the INTOSC source already be running prior to entering stabilizes after an interval of TIOBST. SEC_RUN mode. If the SOSCGO bit or If the IRCF bits were previously at a non-zero value, or any of the TxSOSCEN bits are not set if INTSRC was set before setting SCS1 and the when the SCS<1:0> bits are set to ‘01’, INTOSC source was already stable, then the HFIOFS entry to SEC_RUN mode will not occur or MFIOFS bit will remain set. until SOSCGO bit is set and secondary external oscillator is ready. On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the SOSC oscillator, while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see  2010-2016 Microchip Technology Inc. DS40001412G-page 45

PIC18(L)F2X/4XK22 On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the pri- mary clock occurs (see Figure3-3). When the clock switch is complete, the HFIOFS or MFIOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The LFINTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 SOSCI 1 2 3 n-1 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 SOSC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> bits Changed OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS40001412G-page 46  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 3-2: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS IRCF<2:0> INTSRC MFIOSEL Selected Oscillator Selected Oscillator Stable when: 000 0 x LFINTOSC LFIOFS = 1 000 1 0 HFINTOSC HFIOFS = 1 000 1 1 MFINTOSC MFIOFS = 1 010 or 001 x 0 HFINTOSC HFIOFS = 1 010 or 001 x 1 MFINTOSC MFIOFS = 1 011 – 111 x x HFINTOSC HFIOFS = 1 FIGURE 3-3: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> bits Changed OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC.  2010-2016 Microchip Technology Inc. DS40001412G-page 47

PIC18(L)F2X/4XK22 3.3 Sleep Mode 3.4 Idle Modes The Power-Managed Sleep mode in the PIC18(L)F2X/ The Idle modes allow the controller’s CPU to be 4XK22 devices is identical to the legacy Sleep mode selectively shut down while the peripherals continue to offered in all other PIC microcontroller devices. It is operate. Selecting a particular Idle mode allows users entered by clearing the IDLEN bit of the OSCCON to further manage power consumption. register and executing the SLEEP instruction. This shuts If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is down the selected oscillator (Figure3-4) and all clock executed, the peripherals will be clocked from the clock source Status bits are cleared. source selected by the SCS<1:0> bits; however, the CPU Entering the Sleep mode from either Run or Idle mode will not be clocked. The clock source status bits are not does not require a clock switch. This is because no affected. Setting IDLEN and executing a SLEEP instruc- clocks are needed once the controller has entered tion provides a quick method of switching from a given Sleep. If the WDT is selected, the LFINTOSC source Run mode to its corresponding Idle mode. will continue to operate. If the SOSC oscillator is If the WDT is selected, the LFINTOSC source will enabled, it will also continue to run. continue to operate. If the SOSC oscillator is enabled, When a wake event occurs in Sleep mode (by interrupt, it will also continue to run. Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only until the clock source selected by the SCS<1:0> bits exits from any of the Idle modes are by interrupt, WDT becomes ready (see Figure3-5), or it will be clocked time-out, or a Reset. When a wake event occurs, CPU from the internal oscillator block if either the Two-Speed execution is delayed by an interval of TCSD while it Start-up or the Fail-Safe Clock Monitor are enabled becomes ready to execute code. When the CPU (see Section24.0 “Special Features of the CPU”). In begins executing code, it resumes with the same clock either case, the OSTS bit is set when the primary clock source for the current Idle mode. For example, when is providing the device clocks. The IDLEN and SCS bits waking from RC_IDLE mode, the internal oscillator are not affected by the wake-up. block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 3-4: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 DS40001412G-page 48  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 3-5: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS bit set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 3.4.1 PRI_IDLE MODE 3.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes, in that it does not disable the primary device peripherals continue to be clocked from the SOSC clock. For timing sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by the fastest resumption of device operation with its more setting the IDLEN bit and executing a SLEEP accurate primary clock source, since the clock source instruction. If the device is in another Run mode, set the does not have to “warm-up” or transition from another IDLEN bit first, then set the SCS<1:0> bits to ‘01’ and oscillator. execute SLEEP. When the clock source is switched to the SOSC oscillator, the primary oscillator is shut down, PRI_IDLE mode is entered from PRI_RUN mode by the OSTS bit is cleared and the SOSCRUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then clear the SCS bits and execute SLEEP. be clocked from the SOSC oscillator. After an interval Although the CPU is disabled, the peripherals continue of TCSD following the wake event, the CPU begins exe- to be clocked from the primary clock source specified cuting code being clocked by the SOSC oscillator. The by the FOSC<3:0> Configuration bits. The OSTS bit IDLEN and SCS bits are not affected by the wake-up; remains set (see Figure3-6). the SOSC oscillator continues to run (see Figure3-7). When a wake event occurs, the CPU is clocked from the Note: The SOSC oscillator should already be primary clock source. A delay of interval TCSD is running prior to entering SEC_IDLE required between the wake event and when code mode. At least one of the secondary execution starts. This is required to allow the CPU to oscillator enable bits (SOSCGO, become ready to execute instructions. After the wake- T1SOSCEN, T3SOSCEN or T5SOSCEN) up, the OSTS bit remains set. The IDLEN and SCS bits must be set when the SLEEP instruction is are not affected by the wake-up (see Figure3-7). executed. Otherwise, the main system clock will continue to operate in the previously selected mode and the corresponding IDLE mode will be entered (i.e., PRI_IDLE or RC_IDLE). FIGURE 3-6: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter  2010-2016 Microchip Technology Inc. DS40001412G-page 49

PIC18(L)F2X/4XK22 FIGURE 3-7: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event 3.4.3 RC_IDLE MODE Clocks to the peripherals continue while the HFINTOSC source stabilizes. The HFIOFS and In RC_IDLE mode, the CPU is disabled but the periph- MFIOFS bits will remain set if the IRCF bits were erals continue to be clocked from the internal oscillator previously set at a non-zero value or if INTSRC was set block from the HFINTOSC multiplexer output. This before the SLEEP instruction was executed and the mode allows for controllable power conservation during HFINTOSC source was already stable. If the IRCF bits Idle periods. and INTSRC are all clear, the HFINTOSC output will From RC_RUN, this mode is entered by setting the not be enabled, the HFIOFS and MFIOFS bits will IDLEN bit and executing a SLEEP instruction. If the remain clear and there will be no indication of the device is in another Run mode, first set IDLEN, then set current clock source. the SCS1 bit and execute SLEEP. It is recommended When a wake event occurs, the peripherals continue to that SCS0 also be cleared, although its value is be clocked from the HFINTOSC multiplexer output. ignored, to maintain software compatibility with future After a delay of TCSD following the wake event, the CPU devices. The HFINTOSC multiplexer may be used to begins executing code being clocked by the select a higher clock frequency by modifying the IRCF HFINTOSC multiplexer. The IDLEN and SCS bits are bits before executing the SLEEP instruction. When the not affected by the wake-up. The LFINTOSC source clock source is switched to the HFINTOSC multiplexer, will continue to run if either the WDT or the Fail-Safe the primary oscillator is shut down and the OSTS bit is Clock Monitor is enabled. cleared. If the IRCF bits are set to any non-zero value, or either the INTSRC or MFIOSEL bits are set, the HFINTOSC output is enabled. Either the HFIOFS or the MFIOFS bits become set, after the HFINTOSC output stabilizes after an interval of TIOBST. For information on the HFIOFS and MFIOFS bits, see Table3-2. DS40001412G-page 50  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 3.5 Exiting Idle and Sleep Modes 3.5.2 EXIT BY WDT TIME-OUT An exit from Sleep mode or any of the Idle modes is A WDT time-out will cause different actions depending triggered by any one of the following: on which power-managed mode the device is in when the time-out occurs. • an interrupt If the device is not executing code (all Idle modes and • a Reset Sleep mode), the time-out will result in an exit from the • a Watchdog Time-out power-managed mode (see Section3.2 “Run This section discusses the triggers that cause exits Modes” and Section3.3 “Sleep Mode”). If the device from power-managed modes. The clocking subsystem is executing code (all Run modes), the time-out will actions are discussed in each of the power-managed result in a WDT Reset (see Section24.3 “Watchdog modes (see Section3.2 “Run Modes”, Section3.3 Timer (WDT)”). “Sleep Mode” and Section3.4 “Idle Modes”). The WDT timer and postscaler are cleared by any one of the following: 3.5.1 EXIT BY INTERRUPT • executing a SLEEP instruction Any of the available interrupt sources can cause the • executing a CLRWDT instruction device to exit from an Idle mode or the Sleep mode to a Run mode. To enable this functionality, an interrupt • the loss of the currently selected clock source source must be enabled by setting its enable bit in one when the Fail-Safe Clock Monitor is enabled of the INTCON or PIE registers. The exit sequence is • modifying the IRCF bits in the OSCCON register initiated when the corresponding interrupt flag bit is set. when the internal oscillator block is the device clock source The instruction immediately following the SLEEP instruction is executed on all exits by interrupt from Idle 3.5.3 EXIT BY RESET or Sleep modes. Code execution then branches to the interrupt vector if the GIE/GIEH bit of the INTCON Exiting Sleep and Idle modes by Reset causes code register is set, otherwise code execution continues execution to restart at address ‘0’. See Section4.0 without branching (see Section9.0 “Interrupts”). “Reset” for more details. A fixed delay of interval TCSD following the wake event The exit delay time from Reset to the start of code is required when leaving Sleep and Idle modes. This execution depends on both the clock sources before delay is required for the CPU to prepare for execution. and after the wake-up and the type of oscillator. Instruction execution resumes on the first clock cycle 3.5.4 EXIT WITHOUT AN OSCILLATOR following this delay. START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped and • the primary clock source is not any of the LP, XT, HS or HSPLL modes. In these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC, INTOSC, and INTOSCIO modes). However, a fixed delay of interval TCSD following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.  2010-2016 Microchip Technology Inc. DS40001412G-page 51

PIC18(L)F2X/4XK22 3.6 Selective Peripheral Module Setting the PMD bit for a module disables all clock Control sources to that module, reducing its power consumption to an absolute minimum. In this state, Idle mode allows users to substantially reduce power power to the control and status registers associated consumption by stopping the CPU clock. Even so, with the peripheral is removed. Writes to these peripheral modules still remain clocked, and thus, registers have no effect and read values are invalid. consume power. There may be cases where the Clearing a set PMD bit restores power to the application needs what IDLE mode does not provide: associated control and status registers, thereby setting the allocation of power resources to the CPU those registers to their default values. processing with minimal power consumption from the peripherals. PIC18(L)F2X/4XK22 family devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with control bits in the Peripheral Module Disable (PMD) registers. These bits generically named XXXMD are located in control registers PMD0, PMD1 or PMD2. 3.7 Register Definitions: Peripheral Module Disable REGISTER 3-1: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UART2MD: UART2 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 6 UART1MD: UART1 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 5 TMR6MD: Timer6 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 4 TMR5MD: Timer5 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 3 TMR4MD: Timer4 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 2 TMR3MD: Timer3 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 1 TMR2MD: Timer2 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 0 TMR1MD: Timer1 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power DS40001412G-page 52  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 3-2: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MSSP2MD: MSSP2 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 6 MSSP1MD: MSSP1 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 5 Unimplemented: Read as ‘0’ bit 4 CCP5MD: CCP5 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 3 CCP4MD: CCP4 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 2 CCP3MD: CCP3 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 1 CCP2MD: CCP2 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 0 CCP1MD: CCP1 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power  2010-2016 Microchip Technology Inc. DS40001412G-page 53

PIC18(L)F2X/4XK22 REGISTER 3-3: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CTMUMD CMP2MD CMP1MD ADCMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUMD: CTMU Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 2 CMP2MD: Comparator C2 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 1 CMP1MD: Comparator C1 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 0 ADCMD: ADC Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power DS40001412G-page 54  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 4.0 RESET A simplified block diagram of the On-Chip Reset Circuit is shown in Figure4-1. The PIC18(L)F2X/4XK22 devices differentiate between various kinds of Reset: 4.1 RCON Register a) Power-on Reset (POR) Device Reset events are tracked through the RCON b) MCLR Reset during normal operation register (Register4-1). The lower five bits of the c) MCLR Reset during power-managed modes register indicate that a specific Reset event has d) Watchdog Timer (WDT) Reset (during occurred. In most cases, these bits can only be cleared execution) by the event and must be set by the application after e) Programmable Brown-out Reset (BOR) the event. The state of these flag bits, taken together, f) RESET Instruction can be read to indicate the type of Reset that just occurred. This is described in more detail in g) Stack Full Reset Section4.7 “Reset State of Registers”. h) Stack Underflow Reset The RCON register also has control bits for setting This section discusses Resets generated by MCLR, interrupt priority (IPEN) and software control of the POR and BOR and covers the operation of the various BOR (SBOREN). Interrupt priority is discussed in start-up timers. Stack Reset events are covered in Section9.0 “Interrupts”. BOR is covered in Section5.2.0.1 “Stack Full and Underflow Resets”. Section4.5 “Brown-out Reset (BOR)”. WDT Resets are covered in Section24.3 “Watchdog Timer (WDT)”. FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD POR Detect VDD Brown-out Reset BOREN S OST/PWRT OST(2) 1024 Cycles Chip_Reset 10-bit Ripple Counter R Q OSC1 32 s PWRT(2) 65.5 ms LFINTOSC 11-bit Ripple Counter Enable PWRT Enable OST(1) Note 1: See Table4-2 for time-out situations. 2: PWRT and OST counters are reset by POR and BOR. See Sections 4.4 and 4.5.  2010-2016 Microchip Technology Inc. DS40001412G-page 55

PIC18(L)F2X/4XK22 4.2 Register Definitions: Reset Control REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0/0 R/W-q/u U-0 R/W-1/q R-1/q R-1/q R/W-q/u R/W-0/q IPEN SBOREN(1) — RI TO PD POR(2) BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets x = Bit is unknown u = unchanged q = depends on condition bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN<1:0> = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN<1:0> = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware or Power-on Reset) 0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a code-executed Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit(3) 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs) Note 1: When CONFIG2L[2:1] = 01, then the SBOREN Reset state is ‘1’; otherwise, it is ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section4.7 “Reset State of Registers” for additional information. 3: See Table4-1. Note1: Brown-out Reset is indicated when BOR is ‘0’ and POR is ‘1’ (assuming that both POR and BOR were set to ‘1’ by firmware immediately after POR). 2: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. DS40001412G-page 56  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 4.3 Master Clear (MCLR) FIGURE 4-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering an SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small VDD VDD pulses. An internal weak pull-up is enabled when the pin is configured as the MCLR input. PIC® MCU D R The MCLR pin is not driven low by any internal Resets, R1 including the WDT. MCLR In PIC18(L)F2X/4XK22 devices, the MCLR input can C be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section10.6 “PORTE Registers” for more Note 1: External Power-on Reset circuit is required information. only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor 4.4 Power-on Reset (POR) quickly when VDD powers down. A Power-on Reset pulse is generated on-chip 2: 15 k < R < 40k is recommended to make sure that the voltage drop across R does not whenever VDD rises above a certain threshold. This violate the device’s electrical specification. allows the device to start in the initialized state when VDD is adequate for operation. 3: R1  1 k will limit any current flowing into MCLR from external capacitor C, in the event To take advantage of the POR circuitry either leave the of MCLR/VPP pin breakdown, due to pin floating, or tie the MCLR pin through a resistor to Electrostatic Discharge (ESD) or Electrical VDD. This will eliminate external RC components Overstress (EOS). usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified. For a slow rise time, see Figure4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure proper operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit of the RCON register. The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user must manually set the bit to ‘1’ by software following any POR.  2010-2016 Microchip Technology Inc. DS40001412G-page 57

PIC18(L)F2X/4XK22 4.5 Brown-out Reset (BOR) 4.5.2 SOFTWARE ENABLED BOR PIC18(L)F2X/4XK22 devices implement a BOR circuit When BOREN<1:0> = 01, the BOR can be enabled or that provides the user with a number of configuration and disabled by the user in software. This is done with the power-saving options. The BOR is controlled by the SBOREN control bit of the RCON register. Setting BORV<1:0> and BOREN<1:0> bits of the CONFIG2L SBOREN enables the BOR to function as previously Configuration register. There are a total of four BOR described. Clearing SBOREN disables the BOR configurations which are summarized in Table4-1. entirely. The SBOREN bit operates only in this mode; otherwise it is read as ‘0’. The BOR threshold is set by the BORV<1:0> bits. If BOR is enabled (any values of BOREN<1:0>, except Placing the BOR under software control gives the user ‘00’), any drop of VDD below VBOR for greater than the additional flexibility of tailoring the application to the TBOR will reset the device. A Reset may or may not environment without having to reprogram the device to occur if VDD falls below VBOR for less than TBOR. The change BOR configuration. It also allows the user to chip will remain in Brown-out Reset until VDD rises tailor device power consumption in software by above VBOR. eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, If the Power-up Timer is enabled, it will be invoked after it may have some impact in low-power applications. VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT. If VDD drops below VBOR while the Power-up Timer is running, the Note: Even when BOR is under software chip will go back into a Brown-out Reset and the control, the BOR Reset voltage level is still Power-up Timer will be initialized. Once VDD rises set by the BORV<1:0> Configuration bits. above VBOR, the Power-up Timer will execute the It cannot be changed by software. additional time delay. BOR and the Power-on Timer (PWRT) are 4.5.3 DISABLING BOR IN SLEEP MODE independently configured. Enabling BOR Reset does When BOREN<1:0> = 10, the BOR remains under not automatically enable the PWRT. hardware control and operates as previously The BOR circuit has an output that feeds into the POR described. Whenever the device enters Sleep mode, circuit and rearms the POR within the operating range however, the BOR is automatically disabled. When the of the BOR. This early rearming of the POR ensures device returns to any other operating mode, BOR is that the device will remain in Reset in the event that VDD automatically re-enabled. falls below the operating range of the BOR circuitry. This mode allows for applications to recover from brown-out situations, while actively executing code, 4.5.1 DETECTING BOR when the device requires BOR protection the most. At When BOR is enabled, the BOR bit always resets to ‘0’ the same time, it saves additional power in Sleep mode on any BOR or POR event. This makes it difficult to by eliminating the small incremental BOR current. determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to 4.5.4 MINIMUM BOR ENABLE TIME simultaneously check the state of both POR and BOR. Enabling the BOR also enables the Fixed Voltage This assumes that the POR and BOR bits are reset to Reference (FVR) when no other peripheral requiring the ‘1’ by software immediately after any POR event. If FVR is active. The BOR becomes active only after the BOR is ‘0’ while POR is ‘1’, it can be reliably assumed FVR stabilizes. Therefore, to ensure BOR protection, that a BOR event has occurred. the FVR settling time must be considered when enabling the BOR in software or when the BOR is automatically enabled after waking from Sleep. If the BOR is disabled, in software or by reentering Sleep before the FVR stabilizes, the BOR circuit will not sense a BOR condition. The FVRST bit of the VREFCON0 register can be used to determine FVR stability. DS40001412G-page 58  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 4-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN BOR Operation BOREN1 BOREN0 (RCON<6>) 0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR enabled by software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled by hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled by hardware; must be disabled by reprogramming the Configuration bits. 4.6 Device Reset Timers 4.6.3 PLL LOCK TIME-OUT PIC18(L)F2X/4XK22 devices incorporate three With the PLL enabled, the time-out sequence following a separate on-chip timers that help regulate the Power- Power-on Reset is slightly different from other oscillator on Reset process. Their main function is to ensure that modes. A separate timer is used to provide a fixed time- the device clock is stable before code is executed. out that is sufficient for the PLL to lock to the main These timers are: oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) 4.6.4 TIME-OUT SEQUENCE • PLL Lock Time-out On power-up, the time-out sequence is as follows: 4.6.1 POWER-UP TIMER (PWRT) 1. After the POR pulse has cleared, PWRT time-out is invoked (if enabled). The Power-up Timer (PWRT) of PIC18(L)F2X/4XK22 2. Then, the OST is activated. devices is an 11-bit counter which uses the LFINTOSC source as the clock input. This yields an The total time-out will vary based on oscillator approximate time interval of 2048x32s=65.6ms. configuration and the status of the PWRT. Figure4-3, While the PWRT is counting, the device is held in Figure4-4, Figure4-5, Figure4-6 and Figure4-7 all Reset. depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in The power-up time delay depends on the LFINTOSC HS Oscillator mode. Figures 4-3 through 4-6 also clock and will vary from chip-to-chip due to temperature apply to devices operating in XT or LP modes. For and process variation. devices in RC mode and with the PWRT disabled, on The PWRT is enabled by clearing the PWRTEN the other hand, there will be no time-out at all. Configuration bit. Since the time-outs occur from the POR pulse, if MCLR 4.6.2 OSCILLATOR START-UP TIMER is kept low long enough, all time-outs will expire, after which, bringing MCLR high will allow program (OST) execution to begin immediately (Figure4-5). This is The Oscillator Start-up Timer (OST) provides a 1024 useful for testing purposes or to synchronize more than oscillator cycle (from OSC1 input) delay after the one PIC® MCU device operating in parallel. PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset, or on exit from all power-managed modes that stop the external oscillator.  2010-2016 Microchip Technology Inc. DS40001412G-page 59

PIC18(L)F2X/4XK22 TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Exit from Configuration Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) — — RC, RCIO 66 ms(1) — — INTIO1, INTIO2 66 ms(1) — — Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS40001412G-page 60  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL  2 ms max. First three stages of the PWRT timer.  2010-2016 Microchip Technology Inc. DS40001412G-page 61

PIC18(L)F2X/4XK22 4.7 Reset State of Registers Table5-2 describes the Reset states for all of the Special Function Registers. The table identifies Some registers are unaffected by a Reset. Their status differences between Power-On Reset is unknown on POR and unchanged by all other (POR)/Brown-Out Reset (BOR) and all other Resets, Resets. All other registers are forced to a “Reset state” (i.e., Master Clear, WDT Resets, STKFUL, STKUNF, depending on the type of Reset that occurred. etc.). Additionally, the table identifies register bits that Most registers are not affected by a WDT wake-up, are changed when the device receives a wake-up from since this is viewed as the resumption of normal WDT or other interrupts. operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table4-3. These bits are used by software to determine the nature of the Reset. TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter SBOREN RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u(2) 0 u u u u u u Brown-out Reset 0000h u(2) 1 1 1 u 0 u u MCLR during Power-Managed 0000h u(2) u 1 u u u u u Run Modes MCLR during Power-Managed 0000h u(2) u 1 0 u u u u Idle Modes and Sleep Mode WDT Time-out during Full Power 0000h u(2) u 0 u u u u u or Power-Managed Run Mode MCLR during Full Power 0000h u(2) u u u u u u u Execution Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset 0000h u(2) u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u(2) u u u u u u 1 actual Reset, STVREN = 0) WDT Time-out during Power- PC + 2 u(2) u 0 0 u u u u Managed Idle or Sleep Modes Interrupt Exit from Power- PC + 2(1) u(2) u u 0 u u u u Managed Modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled (BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’. TABLE 4-4: REGISTERS ASSOCIATED WITH RESETS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page RCON IPEN SBOREN — RI TO PD POR BOR 56 STKPTR STKFUL STKUNF — STKPTR<4:0> 67 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets. DS40001412G-page 62  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 4-5: CONFIGURATION REGISTERS ASSOCIATED WITH RESETS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG2L — — — BORV<1:0> BOREN<1:0> PWRTEN 346 CONFIG2H — — WDPS<3:0> WDTEN<1:0> 347 CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 CONFIG4L DEBUG XINST — — — LVP — STRVEN 349 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.  2010-2016 Microchip Technology Inc. DS40001412G-page 63

PIC18(L)F2X/4XK22 5.0 MEMORY ORGANIZATION 5.1 Program Memory Organization There are three types of memory in PIC18 Enhanced PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address will return all ‘0’s (a • Data EEPROM NOP instruction). As Harvard architecture devices, the data and program This family of devices contain the following: memories use separate buses; this allows for • PIC18(L)F23K22, PIC18(L)F43K22: 8Kbytes of concurrent access of the two memory spaces. The data Flash Memory, up to 4,096 single-word instructions EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed • PIC18(L)F24K22, PIC18(L)F44K22: 16Kbytes of through a set of control registers. Flash Memory, up to 8,192 single-word instructions • PIC18(L)F25K22, PIC18(L)F45K22: 32Kbytes of Additional detailed information on the operation of the Flash Memory, up to 16,384 single-word Flash program memory is provided in Section6.0 instructions “Flash Program Memory”. Data EEPROM is • PIC18(L)F26K22, PIC18(L)F46K22: 64Kbytes of discussed separately in Section7.0 “Data EEPROM Flash Memory, up to 37,768 single-word Memory”. instructions PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory map for PIC18(L)F2X/4XK22 devices is shown in Figure5-1. Memory block details are shown in Figure20-2. DS40001412G-page 64  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18(L)F2X/4XK22 DEVICES PC<20:0> CALL,RCALL,RETURN 21 RETFIE,RETLW Stack Level 1    Stack Level 31 Reset Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory 1FFFh On-Chip Program Memory 2000h 3FFFh On-Chip PIC18(L)F23K22 Program Memory 4000h PIC18(L)F43K22 e On-Chip c PIC18(L)F24K22 a Program Memory p S PIC18(L)F44K22 y 7FFFh or 8000h m e M PIC18(L)F25K22 er s U PIC18(L)F45K22 FFFFh 10000h Read ‘0’ Read ‘0’ Read ‘0’ PIC18(L)F26K22 PIC18(L)F46K22 Read ‘0’ 1FFFFFh 200000h 5.1.1 PROGRAM COUNTER The PC increments by two to address sequential instructions in the program memory. The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide The CALL, RCALL, GOTO and program branch and is contained in three separate 8-bit registers. The instructions write to the program counter directly. For low byte, known as the PCL register, is both readable these instructions, the contents of PCLATH and and writable. The high byte, or PCH register, contains PCLATU are not transferred to the program counter. the PC<15:8> bits; it is not directly readable or writable. 5.1.2 RETURN ADDRESS STACK Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This The return address stack allows any combination of up register contains the PC<20:16> bits; it is also not to 31 program calls and interrupts to occur. The PC is directly readable or writable. Updates to the PCU pushed onto the stack when a CALL or RCALL register are performed through the PCLATU register. instruction is executed or an interrupt is Acknowledged. The contents of PCLATH and PCLATU are transferred The PC value is pulled off the stack on a RETURN, to the program counter by any operation that writes RETLW or a RETFIE instruction. PCLATU and PCLATH PCL. Similarly, the upper two bytes of the program are not affected by any of the RETURN or CALL counter are transferred to PCLATH and PCLATU by an instructions. operation that reads PCL. This is useful for computed The stack operates as a 31-word by 21-bit RAM and a offsets to the PC (see Section5.2.2.1 “Computed 5-bit Stack Pointer, STKPTR. The stack space is not GOTO”). part of either program or data space. The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of ‘0’.  2010-2016 Microchip Technology Inc. DS40001412G-page 65

PIC18(L)F2X/4XK22 The Stack Pointer is readable and writable and the 5.1.2.1 Top-of-Stack Access address on the top of the stack is readable and writable Only the top of the return address stack (TOS) is readable through the Top-of-Stack (TOS) Special File Registers. and writable. A set of three registers, TOSU:TOSH:TOSL, Data can also be pushed to, or popped from the stack, hold the contents of the stack location pointed to by the using these registers. STKPTR register (Figure5-2). This allows users to A CALL type instruction causes a push onto the stack; implement a software stack if necessary. After a CALL, the Stack Pointer is first incremented and the location RCALL or interrupt, the software can read the pushed pointed to by the Stack Pointer is written with the value by reading the TOSU:TOSH:TOSL registers. These contents of the PC (already pointing to the instruction values can be placed on a user defined software stack. At following the CALL). A RETURN type instruction causes return time, the software can return these values to a pop from the stack; the contents of the location TOSU:TOSH:TOSL and do a return. pointed to by the STKPTR are transferred to the PC The user must disable the Global Interrupt Enable (GIE) and then the Stack Pointer is decremented. bits while accessing the stack to prevent inadvertent The Stack Pointer is initialized to ‘00000’ after all stack corruption. Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is full or has overflowed or has underflowed. FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> 11111 11110 Top-of-Stack Registers Stack Pointer 11101 TOSU TOSH TOSL STKPTR<4:0> 00h 1Ah 34h 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 5.1.2.2 Return Stack Pointer (STKPTR) onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack The STKPTR register (Register5-1) contains the Stack Pointer will be set to zero. Pointer value, the STKFUL (stack full) Status bit and the STKUNF (Stack Underflow) Status bits. The value If STVREN is cleared, the STKFUL bit will be set on the of the Stack Pointer can be 0 through 31. The Stack 31st push and the Stack Pointer will increment to 31. Pointer increments before values are pushed onto the Any additional pushes will not overwrite the 31st push stack and decrements after values are popped off the and STKPTR will remain at 31. stack. On Reset, the Stack Pointer value will be zero. When the stack has been popped enough times to The user may read and write the Stack Pointer value. unload the stack, the next pop will return a value of zero This feature can be used by a Real-Time Operating to the PC and sets the STKUNF bit, while the Stack System (RTOS) for return stack maintenance. Pointer remains at zero. The STKUNF bit will remain After the PC is pushed onto the stack 31 times (without set until cleared by software or until a POR occurs. popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the The action that takes place when the stack becomes program to the Reset vector, where the full depends on the state of the STVREN (Stack Over- stack conditions can be verified and flow Reset Enable) Configuration bit. (Refer to appropriate actions can be taken. This is Section24.1 “Configuration Bits” for a description of not the same as a Reset, as the contents the device Configuration bits.) If STVREN is set of the SFRs are not affected. (default), the 31st push will push the (PC + 2) value DS40001412G-page 66  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 5.1.2.3 PUSH and POP Instructions The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads Since the Top-of-Stack is readable and writable, the the current PC value onto the stack. ability to push values onto the stack and pull values off the stack without disturbing normal program execution The POP instruction discards the current TOS by is a desirable feature. The PIC18 instruction set decrementing the Stack Pointer. The previous value includes two instructions, PUSH and POP, that permit pushed onto the stack then becomes the TOS value. the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. 5.2 Register Definitions: Stack Pointer REGISTER 5-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — STKPTR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack Underflow occurred 0 = Stack Underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 STKPTR<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. 5.2.0.1 Stack Full and Underflow Resets If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from Device Resets on Stack Overflow and Stack Underflow low priority interrupts. If a high priority interrupt occurs conditions are enabled by setting the STVREN bit in while servicing a low priority interrupt, the stack register Configuration Register 4L. When STVREN is set, a full values stored by the low priority interrupt will be or underflow will set the appropriate STKFUL or overwritten. In these cases, users must save the key STKUNF bit and then cause a device Reset. When registers by software during a low priority interrupt. STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause If interrupt priority is not used, all interrupts may use the a device Reset. The STKFUL or STKUNF bits are fast register stack for returns from interrupt. If no cleared by the user software or a Power-on Reset. interrupts are used, the fast register stack can be used to restore the Status, WREG and BSR registers at the 5.2.1 FAST REGISTER STACK end of a subroutine call. To use the fast register stack for a subroutine call, a CALL label, FAST instruction A fast register stack is provided for the Status, WREG must be executed to save the Status, WREG and BSR and BSR registers, to provide a “fast return” option for registers to the fast register stack. A RETURN, FAST interrupts. The stack for each register is only one level instruction is then executed to restore these registers deep and is neither readable nor writable. It is loaded from the fast register stack. with the current value of the corresponding register when the processor vectors for an interrupt. All Example5-1 shows a source code example that uses interrupt sources will push values into the stack the fast register stack during a subroutine call and registers. The values in the registers are then loaded return. back into their associated registers if the RETFIE,FAST instruction is used to return from the interrupt.  2010-2016 Microchip Technology Inc. DS40001412G-page 67

PIC18(L)F2X/4XK22 EXAMPLE 5-1: FAST REGISTER STACK EXAMPLE 5-2: COMPUTED GOTO USING CODE EXAMPLE AN OFFSET VALUE CALL SUB1, FAST ;STATUS, WREG, BSR MOVF OFFSET, W ;SAVED IN FAST REGISTER CALL TABLE ;STACK ORG nn00h  TABLE ADDWF PCL  RETLW nnh RETLW nnh SUB1  RETLW nnh  . RETURN, FAST ;RESTORE VALUES SAVED . ;IN FAST REGISTER STACK . 5.2.2 LOOK-UP TABLES IN PROGRAM 5.2.2.2 Table Reads and Table Writes MEMORY A better method of storing data in program memory There may be programming situations that require the allows two bytes of data to be stored in each instruction creation of data structures, or look-up tables, in location. program memory. For PIC18 devices, look-up tables Look-up table data may be stored two bytes per can be implemented in two ways: program word by using table reads and writes. The • Computed GOTO Table Pointer (TBLPTR) register specifies the byte • Table Reads address and the Table Latch (TABLAT) register contains the data that is read from or written to program 5.2.2.1 Computed GOTO memory. Data is transferred to or from program memory one byte at a time. A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Table read and table write operations are discussed Example5-2. further in Section6.1 “Table Reads and Table Writes”. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value ‘nn’ to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of two (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. DS40001412G-page 68  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 5.3 PIC18 Instruction Cycle 5.3.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 5.3.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are The microcontroller clock input, whether from an pipelined in such a manner that a fetch takes one internal or external source, is internally divided by four instruction cycle, while the decode and execute take to generate four non-overlapping quadrature clocks another instruction cycle. However, due to the (Q1, Q2, Q3 and Q4). Internally, the program counter is pipelining, each instruction effectively executes in one incremented on every Q1; the instruction is fetched cycle. If an instruction causes the program counter to from the program memory and latched into the change (e.g., GOTO), then two cycles are required to instruction register during Q4. The instruction is complete the instruction (Example5-3). decoded and executed during the following Q1 through A fetch cycle begins with the Program Counter (PC) Q4. The clocks and instruction execution flow are incrementing in Q1. shown in Figure5-3. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 5-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKOUT (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.  2010-2016 Microchip Technology Inc. DS40001412G-page 69

PIC18(L)F2X/4XK22 5.3.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruction. Since instructions are always stored on word The program memory is addressed in bytes. boundaries, the data contained in the instruction is a Instructions are stored as either two bytes or four bytes word address. The word address is written to PC<20:1>, in program memory. The Least Significant Byte of an which accesses the desired byte address in program instruction word is always stored in a program memory memory. Instruction #2 in Figure5-4 shows how the location with an even address (LSb = 0). To maintain instruction GOTO 0006h is encoded in the program alignment with instruction boundaries, the PC memory. Program branch instructions, which encode a increments in steps of two and the LSb will always read relative address offset, operate in the same manner. The ‘0’ (see Section5.1.1 “Program Counter”). offset value stored in a branch instruction represents the Figure5-4 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section25.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0  Program Memory 000000h Byte Locations  000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 5.3.4 TWO-WORD INSTRUCTIONS If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed The standard PIC18 instruction set has four two-word instead. This is necessary for cases when the two-word instructions: CALL, MOVFF, GOTO and LSFR. In all instruction is preceded by a conditional instruction that cases, the second word of the instruction always has changes the PC. Example5-4 shows how this works. ‘1111’ as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of ‘1111’ in the 4 MSbs of an instruction Note: See Section5.8 “PIC18 Instruction specifies a special form of NOP. If the instruction is Execution and the Extended executed in proper sequence – immediately after the Instruction Set” for information on first word – the data in the second word is accessed two-word instructions in the extended and used by the instruction sequence. instruction set. EXAMPLE 5-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code DS40001412G-page 70  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 5.4 Data Memory Organization 5.4.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any Note: The operation of some aspects of data address possible. Ideally, this means that an entire memory are changed when the PIC18 address does not need to be provided for each read or extended instruction set is enabled. See write operation. For PIC18 devices, this is accom- Section5.7 “Data Memory and the plished with a RAM banking scheme. This divides the Extended Instruction Set” for more memory space into 16 contiguous banks of 256 bytes. information. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit The data memory in PIC18 devices is implemented as low-order address and a 4-bit Bank Pointer. static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data Most instructions in the PIC18 instruction set make use memory. The memory space is divided into as many as of the Bank Pointer, known as the Bank Select Register 16banks that contain 256 bytes each. Figures 5-5 (BSR). This SFR holds the 4 Most Significant bits of a through 5-7 show the data memory organization for the location’s address; the instruction itself includes the PIC18(L)F2X/4XK22 devices. 8Least Significant bits. Only the four lower bits of the BSR are implemented (BSR<3:0>). The upper four bits The data memory contains Special Function Registers are unused; they will always read ‘0’ and cannot be (SFRs) and General Purpose Registers (GPRs). The written to. The BSR can be loaded directly by using the SFRs are used for control and status of the controller MOVLB instruction. and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s The value of the BSR indicates the bank in data application. Any read of an unimplemented location will memory; the eight bits in the instruction show the read as ‘0’s. location in the bank and can be thought of as an offset from the bank’s lower boundary. The relationship The instruction set and architecture allow operations between the BSR’s value and the bank division in data across all banks. The entire data memory may be memory is shown in Figures 5-5 through 5-7. accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this Since up to 16 registers may share the same low-order subsection. address, the user must always be careful to ensure that the proper bank is selected before performing a data To ensure that commonly used registers (SFRs and read or write. For example, writing what should be select GPRs) can be accessed in a single cycle, PIC18 program data to an 8-bit address of F9h while the BSR devices implement an Access Bank. This is a 256-byte is 0Fh will end up resetting the program counter. memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the Bank While any bank can be selected, only those banks that Select Register (BSR). Section5.4.2 “Access Bank” are actually implemented can be read or written to. provides a detailed description of the Access RAM. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory maps in Figures 5-5 through 5-7 indicate which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers.  2010-2016 Microchip Technology Inc. DS40001412G-page 71

PIC18(L)F2X/4XK22 FIGURE 5-5: DATA MEMORY MAP FOR PIC18(L)F23K22 AND PIC18(L)F43K22 DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 96 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 160 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 FFh 2FFh When ‘a’ = 1: = 0011 00h 300h Bank 3 The BSR specifies the Bank used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 FFh 4FFh = 0101 00h 500h Bank 5 FFh 5FFh = 0110 00h 600h Bank 6 Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low 5Fh FFh 7FFh Access RAM High 60h = 1000 00h 800h (SFRs) FFh Bank 8 FFh 8FFh = 1001 00h Unused 900h Bank 9 Read 00h FFh 9FFh = 1010 00h A00h Bank 10 FFh AFFh = 1011 00h B00h Bank 11 FFh BFFh C00h = 1100 00h Bank 12 CFFh FFh D00h = 1101 00h Bank 13 DFFh FFh 00h E00h = 1110 Bank 14 FFh EFFh 00h F00h = 1111 Unused Bank 15 F37h F38h SFR(1) Note 1: Addresses F38h through F5Fh are F5Fh also used by SFRs, but are not F60h part of the Access RAM. Users must always use the complete SFR address or load the proper BSR FFh FFFh value to access these registers. DS40001412G-page 72  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 5-6: DATA MEMORY MAP FOR PIC18(L)F24K22 AND PIC18(L)F44K22 DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 96 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 160 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 FFh 4FFh = 0101 00h 500h Bank 5 FFh 5FFh = 0110 00h 600h Bank 6 Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low 5Fh FFh 7FFh Access RAM High 60h = 1000 00h 800h (SFRs) FFh Bank 8 FFh 8FFh = 1001 00h Unused 900h Bank 9 Read 00h FFh 9FFh = 1010 00h A00h Bank 10 FFh AFFh = 1011 00h B00h Bank 11 FFh BFFh C00h = 1100 00h Bank 12 CFFh FFh D00h = 1101 00h Bank 13 DFFh FFh 00h E00h = 1110 Bank 14 FFh EFFh = 1111 00h Unused FF0307hh Bank 15 F38h SFR(1) F5Fh Note 1: Addresses F38h through F5Fh are also used by SFRs, but are not F60h part of the Access RAM. Users must always use the complete SFR address or load the proper BSR FFh FFFh value to access these registers.  2010-2016 Microchip Technology Inc. DS40001412G-page 73

PIC18(L)F2X/4XK22 FIGURE 5-7: DATA MEMORY MAP FOR PIC18(L)F25K22 AND PIC18(L)F45K22 DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 96 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 160 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank GPR used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 GPR FFh 4FFh = 0101 00h 500h Bank 5 GPR FFh 5FFh = 0110 00h 600h Bank 6 Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low 5Fh FFh 7FFh Access RAM High 60h = 1000 00h 800h (SFRs) FFh Bank 8 FFh 8FFh = 1001 00h 900h Bank 9 FFh 9FFh = 1010 00h Unused A00h Bank 10 Read 00h FFh AFFh = 1011 00h B00h Bank 11 FFh BFFh C00h = 1100 00h Bank 12 CFFh FFh D00h = 1101 00h Bank 13 DFFh FFh 00h E00h = 1110 Bank 14 FFh EFFh 00h F00h = 1111 Unused Bank 15 F37h SFR(1) F38h Note 1: Addresses F38h through F5Fh are F5Fh also used by SFRs, but are not F60h part of the Access RAM. Users must always use the complete SFR address or load the proper BSR value to access these registers. FFh FFFh DS40001412G-page 74  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 5-8: DATA MEMORY MAP FOR PIC18(L)F26K22 AND PIC18(L)F46K22 DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 96 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 160 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank GPR used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 GPR FFh 4FFh = 0101 00h 500h Bank 5 GPR FFh 5FFh = 0110 00h 600h Bank 6 GPR Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 GPR Access RAM Low 5Fh FFh 7FFh Access RAM High 60h = 1000 00h 800h (SFRs) FFh Bank 8 GPR FFh 8FFh = 1001 00h 900h Bank 9 GPR FFh 9FFh = 1010 00h A00h Bank 10 GPR FFh AFFh = 1011 00h B00h Bank 11 GPR FFh BFFh C00h = 1100 00h Bank 12 GPR CFFh FFh D00h = 1101 00h Bank 13 GPR DFFh FFh 00h E00h = 1110 Bank 14 GPR FFh 00h F00h = 1111 GPR F37h Bank 15 SFR(1) FF358Fhh Note 1: Addresses F38h through F5Fh are F60h also used by SFRs, but are not part of the Access RAM. Users SFR must always use the complete address or load the proper BSR value to access these registers. FFh FFFh  2010-2016 Microchip Technology Inc. DS40001412G-page 75

PIC18(L)F2X/4XK22 FIGURE 5-9: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) Data Memory From Opcode(2) 7 0 000h 00h 7 0 0 0 0 0 0 0 1 1 Bank 0 FFh 1 1 1 1 1 1 1 1 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS40001412G-page 76  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 5.4.2 ACCESS BANK 5.4.3 GENERAL PURPOSE REGISTER FILE While the use of the BSR with an embedded 8-bit address allows users to address the entire range of PIC18 devices may have banked memory in the GPR data memory, it also means that the user must always area. This is data RAM, which is available for use by all ensure that the correct bank is selected. Otherwise, instructions. GPRs start at the bottom of Bank 0 data may be read from or written to the wrong location. (address 000h) and grow upwards towards the bottom of This can be disastrous if a GPR is the intended target the SFR area. GPRs are not initialized by a Power-on of an operation, but an SFR is written to instead. Reset and are unchanged on all other Resets. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. 5.4.4 SPECIAL FUNCTION REGISTERS To streamline access for the most commonly used data The Special Function Registers (SFRs) are registers memory locations, the data memory is configured with used by the CPU and peripheral modules for controlling an Access Bank, which allows users to access a the desired operation of the device. These registers are mapped block of memory without specifying a BSR. implemented as static RAM. SFRs start at the top of The Access Bank consists of the first 96 bytes of mem- data memory (FFFh) and extend downward to occupy ory (00h-5Fh) in Bank 0 and the last 160 bytes of mem- the top portion of Bank 15 (F38h to FFFh). A list of ory (60h-FFh) in Block 15. The lower half is known as these registers is given in Table5-1 and Table5-2. the “Access RAM” and is composed of GPRs. This The SFRs can be classified into two sets: those upper half is also where the device’s SFRs are associated with the “core” device functionality (ALU, mapped. These two areas are mapped contiguously in Resets and interrupts) and those related to the the Access Bank and can be addressed in a linear peripheral functions. The Reset and interrupt registers fashion by an 8-bit address (Figures 5-5 through 5-7). are described in their respective chapters, while the The Access Bank is used by core PIC18 instructions ALU’s STATUS register is described later in this that include the Access RAM bit (the ‘a’ parameter in section. Registers related to the operation of a the instruction). When ‘a’ is equal to ‘1’, the instruction peripheral feature are described in the chapter for that uses the BSR and the 8-bit address included in the peripheral. opcode for the data memory address. When ‘a’ is ‘0’, The SFRs are typically distributed among the however, the instruction is forced to use the Access peripherals whose functions they control. Unused SFR Bank address map; the current value of the BSR is locations are unimplemented and read as ‘0’s. ignored entirely. Using this “forced” addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section5.7.3 “Mapping the Access Bank in Indexed Literal Offset Mode”.  2010-2016 Microchip Technology Inc. DS40001412G-page 77

PIC18(L)F2X/4XK22 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F2X/4XK22 DEVICES Address Name Address Name Address Name Address Name Address Name FFFh TOSU FD7h TMR0H FAFh SPBRG1 F87h —(2) F5Fh CCPR3H FFEh TOSH FD6h TMR0L FAEh RCREG1 F86h —(2) F5Eh CCPR3L FFDh TOSL FD5h T0CON FADh TXREG1 F85h —(2) F5Dh CCP3CON FFCh STKPTR FD4h —(2) FACh TXSTA1 F84h PORTE F5Ch PWM3CON FFBh PCLATU FD3h OSCCON FABh RCSTA1 F83h PORTD(3) F5Bh ECCP3AS FFAh PCLATH FD2h OSCCON2 FAAh EEADRH(4) F82h PORTC F5Ah PSTR3CON FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB F59h CCPR4H FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA F58h CCPR4L FF7h TBLPTRH FCFh TMR1H FA7h EECON2(1) F7Fh IPR5 F57h CCP4CON FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh PIR5 F56h CCPR5H FF5h TABLAT FCDh T1CON FA5h IPR3 F7Dh PIE5 F55h CCPR5L FF4h PRODH FCCh T1GCON FA4h PIR3 F7Ch IPR4 F54h CCP5CON FF3h PRODL FCBh SSP1CON3 FA3h PIE3 F7Bh PIR4 F53h TMR4 FF2h INTCON FCAh SSP1MSK FA2h IPR2 F7Ah PIE4 F52h PR4 FF1h INTCON2 FC9h SSP1BUF FA1h PIR2 F79h CM1CON0 F51h T4CON FF0h INTCON3 FC8h SSP1ADD FA0h PIE2 F78h CM2CON0 F50h TMR5H FEFh INDF0(1) FC7h SSP1STAT F9Fh IPR1 F77h CM2CON1 F4Fh TMR5L FEEh POSTINC0(1) FC6h SSP1CON1 F9Eh PIR1 F76h SPBRGH2 F4Eh T5CON FEDh POSTDEC0(1) FC5h SSP1CON2 F9Dh PIE1 F75h SPBRG2 F4Dh T5GCON FECh PREINC0(1) FC4h ADRESH F9Ch HLVDCON F74h RCREG2 F4Ch TMR6 FEBh PLUSW0(1) FC3h ADRESL F9Bh OSCTUNE F73h TXREG2 F4Bh PR6 FEAh FSR0H FC2h ADCON0 F9Ah —(2) F72h TXSTA2 F4Ah T6CON FE9h FSR0L FC1h ADCON1 F99h —(2) F71h RCSTA2 F49h CCPTMRS0 FE8h WREG FC0h ADCON2 F98h —(2) F70h BAUDCON2 F48h CCPTMRS1 FE7h INDF1(1) FBFh CCPR1H F97h —(2) F6Fh SSP2BUF F47h SRCON0 FE6h POSTINC1(1) FBEh CCPR1L F96h TRISE F6Eh SSP2ADD F46h SRCON1 FE5h POSTDEC1(1) FBDh CCP1CON F95h TRISD(3) F6Dh SSP2STAT F45h CTMUCONH FE4h PREINC1(1) FBCh TMR2 F94h TRISC F6Ch SSP2CON1 F44h CTMUCONL FE3h PLUSW1(1) FBBh PR2 F93h TRISB F6Bh SSP2CON2 F43h CTMUICON FE2h FSR1H FBAh T2CON F92h TRISA F6Ah SSP2MSK F42h VREFCON0 FE1h FSR1L FB9h PSTR1CON F91h —(2) F69h SSP2CON3 F41h VREFCON1 FE0h BSR FB8h BAUDCON1 F90h —(2) F68h CCPR2H F40h VREFCON2 FDFh INDF2(1) FB7h PWM1CON F8Fh —(2) F67h CCPR2L F3Fh PMD0 FDEh POSTINC2(1) FB6h ECCP1AS F8Eh —(2) F66h CCP2CON F3Eh PMD1 FDDh POSTDEC2(1) FB5h —(2) F8Dh LATE(3) F65h PWM2CON F3Dh PMD2 FDCh PREINC2(1) FB4h T3GCON F8Ch LATD(3) F64h ECCP2AS F3Ch ANSELE FDBh PLUSW2(1) FB3h TMR3H F8Bh LATC F63h PSTR2CON F3Bh ANSELD FDAh FSR2H FB2h TMR3L F8Ah LATB F62h IOCB F3Ah ANSELC FD9h FSR2L FB1h T3CON F89h LATA F61h WPUB F39h ANSELB FD8h STATUS FB0h SPBRGH1 F88h —(2) F60h SLRCON F38h ANSELA Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: PIC18(L)F4XK22 devices only. 4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only. DS40001412G-page 78  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR FFFh TOSU — — — Top-of-Stack, Upper Byte (TOS<20:16>) ---0 0000 FFEh TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 FFDh TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 FFCh STKPTR STKFUL STKUNF — STKPTR<4:0> 00-0 0000 FFBh PCLATU — — — Holding Register for PC<20:16> ---0 0000 FFAh PCLATH Holding Register for PC<15:8> 0000 0000 FF9h PCL Holding Register for PC<7:0> 0000 0000 FF8h TBLPTRU — — Program Memory Table Pointer Upper Byte(TBLPTR<21:16>) --00 0000 FF7h TBLPTRH Program Memory Table Pointer High Byte(TBLPTR<15:8>) 0000 0000 FF6h TBLPTRL Program Memory Table Pointer Low Byte(TBLPTR<7:0>) 0000 0000 FF5h TABLAT Program Memory Table Latch 0000 0000 FF4h PRODH Product Register, High Byte xxxx xxxx FF3h PRODL Product Register, Low Byte xxxx xxxx FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x FF1h INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 FF0h INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) ---- ---- FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) ---- ---- FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) ---- ---- FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) ---- ---- FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – ---- ---- value of FSR0 offset by W FEAh FSR0H — — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000 FE9h FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx FE8h WREG Working Register xxxx xxxx FE7h INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) ---- ---- FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ---- FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) ---- ---- FE4h PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) ---- ---- FE3h PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – ---- ---- value of FSR1 offset by W FE2h FSR1H — — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000 FE1h FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx FE0h BSR — — — — Bank Select Register ---- 0000 FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) ---- ---- FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) ---- ---- FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)---- ---- FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) ---- ---- FDBh PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – ---- ---- value of FSR2 offset by W FDAh FSR2H — — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000 FD9h FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx FD8h STATUS — — — N OV Z DC C ---x xxxx FD7h TMR0H Timer0 Register, High Byte 0000 0000 FD6h TMR0L Timer0 Register, Low Byte xxxx xxxx FD5h T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS<2:0> 1111 1111 FD3h OSCCON IDLEN IRCF<2:0> OSTS HFIOFS SCS<1:0> 0011 q000 FD2h OSCCON2 PLLRDY SOSCRUN — MFIOSEL SOSCGO PRISD MFIOFS LFIOFS 00-0 01x0 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: PIC18(L)F4XK22 devices only. 2: PIC18(L)F2XK22 devices only. 3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. 4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.  2010-2016 Microchip Technology Inc. DS40001412G-page 79

PIC18(L)F2X/4XK22 TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED) Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR FD1h WDTCON — — — — — — — SWDTEN ---- ---0 FD0h RCON IPEN SBOREN — RI TO PD POR BOR 01-1 1100 FCFh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx FCEh TMR1L Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx FCDh T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSCEN T1SYNC T1RD16 TMR1ON 0000 0000 FCCh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 xx00 DONE FCBh SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 FCAh SSP1MSK SSP1 MASK Register bits 1111 1111 FC9h SSP1BUF SSP1 Receive Buffer/Transmit Register xxxx xxxx FC8h SSP1ADD SSP1 Address Register in I2C Slave Mode. SSP1 Baud Rate Reload Register in I2C Master Mode 0000 0000 FC7h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 FC6h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 FC5h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 FC4h ADRESH A/D Result, High Byte xxxx xxxx FC3h ADRESL A/D Result, Low Byte xxxx xxxx FC2h ADCON0 — CHS<4:0> GO/DONE ADON --00 0000 FC1h ADCON1 TRIGSEL — — — PVCFG<1:0> NVCFG<1:0> 0--- 0000 FC0h ADCON2 ADFM — ACQT<2:0> ADCS<2:0> 0-00 0000 FBFh CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxx FBEh CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx FBDh CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 FBCh TMR2 Timer2 Register 0000 0000 FBBh PR2 Timer2 Period Register 1111 1111 FBAh T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 FB9h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 FB8h BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 0100 0-00 FB7h PWM1CON P1RSEN P1DC<6:0> 0000 0000 FB6h ECCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 FB4h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS<1:0> 0000 0x00 DONE FB3h TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx FB2h TMR3L Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx FB1h T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 0000 0000 FB0h SPBRGH1 EUSART1 Baud Rate Generator, High Byte 0000 0000 FAFh SPBRG1 EUSART1 Baud Rate Generator, Low Byte 0000 0000 FAEh RCREG1 EUSART1 Receive Register 0000 0000 FADh TXREG1 EUSART1 Transmit Register 0000 0000 FACh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 FABh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x FAAh EEADRH(5) — — — — — — EEADR<9:8> ---- --00 FA9h EEADR EEADR<7:0> 0000 0000 FA8h EEDATA EEPROM Data Register 0000 0000 FA7h EECON2 EEPROM Control Register 2 (not a physical register) ---- --00 FA6h EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 FA5h IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 0000 0000 FA4h PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 0000 0000 FA3h PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 0000 0000 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: PIC18(L)F4XK22 devices only. 2: PIC18(L)F2XK22 devices only. 3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. 4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only. DS40001412G-page 80  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED) Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR FA2h IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 1111 1111 FA1h PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 0000 0000 FA0h PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 0000 0000 F9Fh IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP -111 1111 F9Eh PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF -000 0000 F9Dh PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE -000 0000 F9Ch HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> 0000 0000 F9Bh OSCTUNE INTSRC PLLEN TUN<5:0> 00xx xxxx F96h TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 1--- -111 F95h TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 F94h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 F92h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 F8Dh LATE(1) — — — — — LATE2 LATE1 LATE0 ---- -xxx F8Ch LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx F8Bh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx F89h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx PORTE(2) — — — — RE3 — — — ---- x--- F84h PORTE(1) — — — — RE3 RE2 RE1 RE0 ---- x000 F83h PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 F82h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 0000 00xx F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxx0 0000 F80h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 F7Fh IPR5 — — — — — TMR6IP TMR5IP TMR4IP ---- -111 F7Eh PIR5 — — — — — TMR6IF TMR5IF TMR4IF ---- -111 F7Dh PIE5 — — — — — TMR6IE TMR5IE TMR4IE ---- -000 F7Ch IPR4 — — — — — CCP5IP CCP4IP CCP3IP ---- -000 F7Bh PIR4 — — — — — CCP5IF CCP4IF CCP3IF ---- -000 F7Ah PIE4 — — — — — CCP5IE CCP4IE CCP3IE ---- -000 F79h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH<1:0> 0000 1000 F78h CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH<1:0> 0000 1000 F77h CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 0000 0000 F76h SPBRGH2 EUSART2 Baud Rate Generator, High Byte 0000 0000 F75h SPBRG2 EUSART2 Baud Rate Generator, Low Byte 0000 0000 F74h RCREG2 EUSART2 Receive Register 0000 0000 F73h TXREG2 EUSART2 Transmit Register 0000 0000 F72h TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 F71h RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x F70h BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 01x0 0-00 F6Fh SSP2BUF SSP2 Receive Buffer/Transmit Register xxxx xxxx F6Eh SSP2ADD SSP2 Address Register in I2C Slave Mode. SSP2 Baud Rate Reload Register in I2C Master Mode 0000 0000 F6Dh SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 F6Ch SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 F6Bh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 F6Ah SSP2MSK SSP1 MASK Register bits 1111 1111 F69h SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: PIC18(L)F4XK22 devices only. 2: PIC18(L)F2XK22 devices only. 3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. 4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.  2010-2016 Microchip Technology Inc. DS40001412G-page 81

PIC18(L)F2X/4XK22 TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED) Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR F68h CCPR2H Capture/Compa re/PWM Register 2, High Byte xxxx xxxx F67h CCPR2L Capture/Compare/PWM Register 2, Low Byte xxxx xxxx F66h CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 0000 0000 F65h PWM2CON P2RSEN P2DC<6:0> 0000 0000 F64h ECCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 0000 0000 F63h PSTR2CON — — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 F62h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 1111 ---- F61h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 SLRCON(2) — — — — — SLRC SLRB SLRA ---- -111 F60h SLRCON(1) — — — SLRE SLRD SLRC SLRB SLRA ---1 1111 F5Fh CCPR3H Capture/Comp are/PWM Register 3, High Byte xxxx xxxx F5Eh CCPR3L Capture/Comp are/PWM Register 3, Low Byte xxxx xxxx F5Dh CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 0000 0000 F5Ch PWM3CON P3RSEN P3DC<6:0> 0000 0000 F5Bh ECCP3AS CCP3ASE CCP3AS<2:0> PSS3AC<1:0> PSS3BD<1:0> 0000 0000 F5Ah PSTR3CON — — — STR3SYNC STR3D STR3C STR3B STR3A ---0 0001 F59h CCPR4H Capture/Comp are/PWM Register 4, High Byte xxxx xxxx F58h CCPR4L Capture/Compare/PWM Register 4, Low Byte xxxx xxxx F57h CCP4CON — — DC4B<1:0> CCP4M<3:0> --00 0000 F56h CCPR5H Capture/Comp are/PWM Register 5, High Byte xxxx xxxx F55h CCPR5L Capture/Com pare/PWM Register 5, Low Byte xxxx xxxx F54h CCP5CON — — DC5B<1:0> CCP5M<3:0> --00 0000 F53h TMR4 Timer4 Register 0000 0000 F52h PR4 Timer4 Period Register 1111 1111 F51h T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 F50h TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register 0000 0000 F4Fh TMR5L Least Significant Byte of the 16-bit TMR5 Register 0000 0000 F4Eh T5CON TMR5CS<1:0> T5CKPS<1:0> T5SOSCEN T5SYNC T5RD16 TMR5ON 0000 0000 F4Dh T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/ T5GVAL T5GSS<1:0> 0000 0x00 DONE F4Ch TMR6 Timer6 Register 0000 0000 F4Bh PR6 Timer6 Period Register 1111 1111 F4Ah T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000 F49h CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 00-0 0-00 F48h CCPTMRS1 — — — — C5TSEL<1:0> C4TSEL<1:0> ---- 0000 F47h SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 0000 0000 F46h SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 F45h CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 0000 0000 F44h CTMUCONL EDG2POL EDG2SEL<1:0> EDG1POL EDG1SEL<1:0> EDG2STAT EDG1STAT 0000 0000 F43h CTMUICON ITRIM<5:0> IRNG<1:0> 0000 0000 F42h VREFCON0 FVREN FVRST FVRS<1:0> — — — — 0001 ---- F41h VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 000- 00-0 F40h VREFCON2 — — — DACR<4:0> ---0 0000 F3Fh PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 0000 0000 F3Eh PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 00-0 0000 F3Dh PMD2 — — — — CTMUMD CMP2MD CMP1MD ADCMD ---- 0000 F3Ch ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 ---- -111 F3Bh ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: PIC18(L)F4XK22 devices only. 2: PIC18(L)F2XK22 devices only. 3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. 4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only. DS40001412G-page 82  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED) Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR F3Ah ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 1111 11-- F39h ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 F38h ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: PIC18(L)F4XK22 devices only. 2: PIC18(L)F2XK22 devices only. 3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. 4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.  2010-2016 Microchip Technology Inc. DS40001412G-page 83

PIC18(L)F2X/4XK22 5.4.5 STATUS REGISTER It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS The STATUS register, shown in Register5-2, contains register, because these instructions do not affect the Z, the arithmetic status of the ALU. As with any other SFR, C, DC, OV or N bits in the STATUS register. it can be the operand for any instruction. For other instructions that do not affect Status bits, see If the STATUS register is the destination for an instruc- the instruction set summaries in Section25.2 tion that affects the Z, DC, C, OV or N bits, the results “Extended Instruction Set” and Table25-3. of the instruction are not written; instead, the STATUS register is updated according to the instruction per- Note: The C and DC bits operate as the borrow formed. Therefore, the result of an instruction with the and digit borrow bits, respectively, in STATUS register as its destination may be different subtraction. than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). 5.5 Register Definitions: Status REGISTER 5-2: STATUS: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (two’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS40001412G-page 84  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 5.6 Data Addressing Modes Purpose Register File”) or a location in the Access Bank (Section5.4.2 “Access Bank”) as the data source for the instruction. Note: The execution of some instructions in the The Access RAM bit ‘a’ determines how the address is core PIC18 instruction set are changed interpreted. When ‘a’ is ‘1’, the contents of the BSR when the PIC18 extended instruction set is (Section5.4.1 “Bank Select Register (BSR)”) are enabled. See Section5.7 “Data Memory used with the address to determine the complete 12-bit and the Extended Instruction Set” for address of the register. When ‘a’ is ‘0’, the address is more information. interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes While the program memory can be addressed in only also known as Direct Forced Addressing mode. one way – through the program counter – information in the data memory space can be addressed in several A few instructions, such as MOVFF, include the entire ways. For most instructions, the addressing mode is 12-bit address (either source or destination) in their fixed. Other instructions may use up to three modes, opcodes. In these cases, the BSR is ignored entirely. depending on which operands are used and whether or The destination of the operation’s results is determined not the extended instruction set is enabled. by the destination bit ‘d’. When ‘d’ is ‘1’, the results are The addressing modes are: stored back in the source register, overwriting its origi- nal contents. When ‘d’ is ‘0’, the results are stored in • Inherent the W register. Instructions without the ‘d’ argument • Literal have a destination that is implicit in the instruction; their • Direct destination is either the target register being operated • Indirect on or the W register. An additional addressing mode, Indexed Literal Offset, 5.6.3 INDIRECT ADDRESSING is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is Indirect addressing allows the user to access a location discussed in greater detail in Section5.7.1 “Indexed in data memory without giving a fixed address in the Addressing with Literal Offset”. instruction. This is done by using File Select Registers (FSRs) as pointers to the locations which are to be read 5.6.1 INHERENT AND LITERAL or written. Since the FSRs are themselves located in ADDRESSING RAM as Special File Registers, they can also be directly manipulated under program control. This Many PIC18 control instructions do not need any argu- makes FSRs very useful in implementing data struc- ment at all; they either perform an operation that glob- tures, such as tables and arrays in data memory. ally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent The registers for indirect addressing are also Addressing. Examples include SLEEP, RESET and DAW. implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with Other instructions work in a similar way but require an auto-incrementing, auto-decrementing or offsetting additional explicit argument in the opcode. This is with another value. This allows for efficient code, using known as Literal Addressing mode because they loops, such as the example of clearing an entire RAM require some literal value as an argument. Examples bank in Example5-5. include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples EXAMPLE 5-5: HOW TO CLEAR RAM include CALL and GOTO, which include a 20-bit (BANK 1) USING program memory address. INDIRECT ADDRESSING 5.6.2 DIRECT ADDRESSING LFSR FSR0, 100h ; Direct addressing specifies all or part of the source NEXT CLRF POSTINC0 ; Clear INDF ; register then and/or destination address of the operation within the ; inc pointer opcode itself. The options are specified by the BTFSS FSR0H,1 ; All done with arguments accompanying the instruction. ; Bank1? In the core PIC18 instruction set, bit-oriented and byte- BRA NEXT ; NO, clear next oriented instructions use some version of direct CONTINUE ; YES, continue addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section5.4.3 “General  2010-2016 Microchip Technology Inc. DS40001412G-page 85

PIC18(L)F2X/4XK22 5.6.3.1 FSR Registers and the INDF 5.6.3.2 FSR Registers and POSTINC, Operand POSTDEC, PREINC and PLUSW At the core of indirect addressing are three sets of reg- In addition to the INDF operand, each FSR register pair isters: FSR0, FSR1 and FSR2. Each represents a pair also has four additional indirect operands. Like INDF, of 8-bit registers, FSRnH and FSRnL. Each FSR pair these are “virtual” registers which cannot be directly holds a 12-bit value, therefore, the four upper bits of the read or written. Accessing these registers actually FSRnH register are not used. The 12-bit FSR value can accesses the location to which the associated FSR address the entire range of the data memory in a linear register pair points, and also performs a specific action fashion. The FSR register pairs, then, serve as pointers on the FSR value. They are: to data memory locations. • POSTDEC: accesses the location to which the Indirect addressing is accomplished with a set of FSR points, then automatically decrements the Indirect File Operands, INDF0 through INDF2. These FSR by 1 afterwards can be thought of as “virtual” registers: they are • POSTINC: accesses the location to which the mapped in the SFR space but are not physically FSR points, then automatically increments the implemented. Reading or writing to a particular INDF FSR by 1 afterwards register actually accesses its corresponding FSR • PREINC: automatically increments the FSR by register pair. A read from INDF1, for example, reads one, then uses the location to which the FSR the data at the address indicated by FSR1H:FSR1L. points in the operation Instructions that use the INDF registers as operands • PLUSW: adds the signed value of the W register actually use the contents of their corresponding FSR as (range of -127 to 128) to that of the FSR and uses a pointer to the instruction’s target. The INDF operand the location to which the result points in the is just a convenient way of using the pointer. operation. Because indirect addressing uses a full 12-bit address, In this context, accessing an INDF register uses the data RAM banking is not necessary. Thus, the current value in the associated FSR register without changing contents of the BSR and the Access RAM bit have no it. Similarly, accessing a PLUSW register gives the effect on determining the target address. FSR value an offset by that in the W register; however, neither W nor the FSR is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR register. FIGURE 5-10: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 indirect addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 0 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains E00h ECCh. This means the contents of Bank 14 location ECCh will be added to that F00h of the W register and stored back in Bank 15 ECCh. FFFh Data Memory DS40001412G-page 86  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Operations on the FSRs with POSTDEC, POSTINC 5.7.1 INDEXED ADDRESSING WITH and PREINC affect the entire register pair; that is, LITERAL OFFSET rollovers of the FSRnL register from FFh to 00h carry Enabling the PIC18 extended instruction set changes over to the FSRnH register. On the other hand, results the behavior of indirect addressing using the FSR2 of these operations do not change the value of any register pair within Access RAM. Under the proper flags in the STATUS register (e.g., Z, N, OV, etc.). conditions, instructions that use the Access Bank – that The PLUSW register can be used to implement a form is, most bit-oriented and byte-oriented instructions – of indexed addressing in the data memory space. By can invoke a form of indexed addressing using an manipulating the value in the W register, users can offset specified in the instruction. This special reach addresses that are fixed offsets from pointer addressing mode is known as Indexed Addressing with addresses. In some applications, this can be used to Literal Offset, or Indexed Literal Offset mode. implement some powerful program control structure, When using the extended instruction set, this such as software stacks, inside of data memory. addressing mode requires the following: 5.6.3.3 Operations by FSRs on FSRs • The use of the Access Bank is forced (‘a’ = 0) and Indirect addressing operations that target other FSRs • The file address argument is less than or equal to or virtual registers represent special cases. For 5Fh. example, using an FSR to point to one of the virtual Under these conditions, the file address of the registers will not result in successful operations. As a instruction is not interpreted as the lower byte of an specific case, assume that FSR0H:FSR0L contains address (used with the BSR in direct addressing), or as FE7h, the address of INDF1. Attempts to read the an 8-bit address in the Access Bank. Instead, the value value of the INDF1 using INDF0 as an operand will is interpreted as an offset value to an Address Pointer, return 00h. Attempts to write to INDF1 using INDF0 as specified by FSR2. The offset and the contents of the operand will result in a NOP. FSR2 are added to obtain the target address of the On the other hand, using the virtual registers to write to operation. an FSR pair may not occur as planned. In these cases, 5.7.2 INSTRUCTIONS AFFECTED BY the value will be written to the FSR pair but without any INDEXED LITERAL OFFSET MODE incrementing or decrementing. Thus, writing to either the INDF2 or POSTDEC2 register will write the same Any of the core PIC18 instructions that can use direct value to the FSR2H:FSR2L. addressing are potentially affected by the Indexed Since the FSRs are physical registers mapped in the Literal Offset Addressing mode. This includes all SFR space, they can be manipulated through all direct byte-oriented and bit-oriented instructions, or almost operations. Users should proceed cautiously when one-half of the standard PIC18 instruction set. working on these registers, particularly if their code Instructions that only use Inherent or Literal Addressing uses indirect addressing. modes are unaffected. Similarly, operations by indirect addressing are generally Additionally, byte-oriented and bit-oriented instructions permitted on all other SFRs. Users should exercise the are not affected if they do not use the Access Bank appropriate caution that they do not inadvertently change (Access RAM bit is ‘1’), or include a file address of 60h settings that might affect the operation of the device. or above. Instructions meeting these criteria will continue to execute as before. A comparison of the 5.7 Data Memory and the Extended different possible addressing modes when the extended instruction set is enabled is shown in Instruction Set Figure5-11. Enabling the PIC18 extended instruction set (XINST Those who desire to use byte-oriented or bit-oriented Configuration bit = 1) significantly changes certain instructions in the Indexed Literal Offset mode should aspects of data memory and its addressing. Specifi- note the changes to assembler syntax for this mode. cally, the use of the Access Bank for many of the core This is described in more detail in Section25.2.1 PIC18 instructions is different; this is due to the intro- “Extended Instruction Syntax”. duction of a new addressing mode for the data memory space. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged.  2010-2016 Microchip Technology Inc. DS40001412G-page 87

PIC18(L)F2X/4XK22 FIGURE 5-11: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When ‘a’ = 0 and f  60h: The instruction executes in 060h Direct Forced mode. ‘f’ is inter- Bank 0 preted as a location in the 100h Access RAM between 060h 00h and 0FFh. This is the same as Bank 1 through 60h locations F60h to FFFh Bank 14 (Bank15) of data memory. Valid range for ‘f’ Locations below 60h are not FFh available in this addressing F00h Access RAM mode. Bank 15 F60h SFRs FFFh Data Memory When ‘a’ = 0 and f5Fh: 000h The instruction executes in Indexed Literal Offset mode. ‘f’ 060h Bank 0 is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F60h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When ‘a’ = 1 (all values of f): 000h 00000000 The instruction executes in 060h Direct mode (also known as Bank 0 Direct Long mode). ‘f’ is inter- 100h preted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F60h SFRs FFFh Data Memory DS40001412G-page 88  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 5.7.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue The use of Indexed Literal Offset Addressing mode to use direct addressing as before. effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing 5.8 PIC18 Instruction Execution and just the contents of the bottom section of Bank 0, this the Extended Instruction Set mode maps the contents from a user defined “window” that can be located anywhere in the data memory Enabling the extended instruction set adds eight space. The value of FSR2 establishes the lower bound- additional commands to the existing PIC18 instruction ary of the addresses mapped into the window, while the set. These instructions are executed as described in upper boundary is defined by FSR2 plus 95 (5Fh). Section25.2 “Extended Instruction Set”. Addresses in the Access RAM above 5Fh are mapped as previously described (see Section5.4.2 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure5-12. FIGURE 5-12: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a FSR2H:FSR2L = 120h Bank 0 Locations in the region from the FSR2 pointer 100h (120h) to the pointer plus Bank 1 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Access RAM (000h-05Fh). 200h Bank 1 “Window” 5Fh Special File Registers at 60h F60h through FFFh are mapped to 60h through Bank 2 FFh, as usual. through SFRs Bank 0 addresses below Bank 14 5Fh can still be addressed FFh by using the BSR. Access Bank F00h Bank 15 F60h SFRs FFFh Data Memory  2010-2016 Microchip Technology Inc. DS40001412G-page 89

PIC18(L)F2X/4XK22 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed one byte at • Table Read (TBLRD) a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 64 bytes at a time. Program memory is The program memory space is 16 bits wide, while the erased in blocks of 64 bytes at a time. A bulk erase data RAM space is 8 bits wide. Table reads and table operation cannot be issued from user code. writes move data between these two memory spaces Writing or erasing program memory will cease through an 8-bit register (TABLAT). instruction fetches until the operation is complete. The The table read operation retrieves one byte of data program memory cannot be accessed during the write directly from program memory and places it into the or erase, therefore, code cannot execute. An internal TABLAT register. Figure6-1 shows the operation of a programming timer terminates program memory writes table read. and erases. The table write operation stores one byte of data from the A value written to program memory does not need to be TABLAT register into a write block holding register. The a valid instruction. Executing a program memory procedure to write the contents of the holding registers location that forms an invalid instruction results in a into program memory is detailed in Section6.6 “Writing NOP. to Flash Program Memory”. Figure6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. Tables containing data, rather than program instructions, are not required to be word aligned. Therefore, a table can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. DS40001412G-page 90  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR<MSBs>) Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL actually point to an address within the write block holding registers. The MSBs of the Table Pointer deter- mine where the write block will eventually be written. The process for writing the holding registers to the program memory array is discussed in Section6.6 “Writing to Flash Program Memory”. 6.2 Control Registers The FREE bit allows the program memory erase operation. When FREE is set, an erase operation is Several control registers are used in conjunction with initiated on the next WR command. When FREE is the TBLRD and TBLWT instructions. These include the: clear, only writes are enabled. • EECON1 register The WREN bit, when set, will allow a write operation. • EECON2 register The WREN bit is clear on power-up. • TABLAT register The WRERR bit is set by hardware when the WR bit is • TBLPTR registers set and cleared when the internal programming timer expires and the write operation is complete. 6.2.1 EECON1 AND EECON2 REGISTERS The EECON1 register (Register6-1) is the control register for memory accesses. The EECON2 register is Note: During normal operation, the WRERR is not a physical register; it is used exclusively in the read as ‘1’. This can indicate that a write memory write and erase sequences. Reading operation was prematurely terminated by EECON2 will read all ‘0’s. a Reset, or a write operation was attempted improperly. The EEPGD control bit determines if the access will be a program or data EEPROM memory access. When The WR control bit initiates write operations. The WR EEPGD is clear, any subsequent operations will bit cannot be cleared, only set, by firmware. Then WR operate on the data EEPROM memory. When EEPGD bit is cleared by hardware at the completion of the write is set, any subsequent operations will operate on the operation. program memory. The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program Note: The EEIF interrupt flag bit of the PIR2 memory/data EEPROM memory. When CFGS is set, register is set when the write is complete. subsequent operations will operate on Configuration The EEIF flag stays set until cleared by registers regardless of EEPGD (see Section24.0 firmware. “Special Features of the CPU”). When CFGS is clear, memory selection access is determined by EEPGD.  2010-2016 Microchip Technology Inc. DS40001412G-page 91

PIC18(L)F2X/4XK22 6.3 Register Definitions: Memory Control REGISTER 6-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row (Block) Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) by software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS40001412G-page 92  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 6.3.1 TABLAT – TABLE LATCH REGISTER When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory The Table Latch (TABLAT) is an 8-bit register mapped directly into the TABLAT register. into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program When a TBLWT is executed the byte in the TABLAT memory and data RAM. register is written, not to Flash memory but, to a holding register in preparation for a program memory write. The 6.3.2 TBLPTR – TABLE POINTER holding registers constitute a write block which varies REGISTER depending on the device (see Table6-1).The 3, 4, or 5 LSbs of the TBLPTRL register determine which specific The Table Pointer (TBLPTR) register addresses a byte address within the holding register block is written to. within the program memory. The TBLPTR is comprised The MSBs of the Table Pointer have no effect during of three SFR registers: Table Pointer Upper Byte, Table TBLWT operations. Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three When a program memory write is executed the entire registers join to form a 22-bit wide pointer. The holding register block is written to the Flash memory at low-order 21bits allow the device to address up to 2 the address determined by the MSbs of the TBLPTR. Mbytes of program memory space. The 22nd bit allows The 3, 4, or 5 LSBs are ignored during Flash memory access to the device ID, the user ID and the writes. For more detail, see Section6.6 “Writing to Configuration bits. Flash Program Memory”. The Table Pointer register, TBLPTR, is used by the When an erase of program memory is executed, the TBLRD and TBLWT instructions. These instructions can 16MSbs of the Table Pointer register (TBLPTR<21:6>) update the TBLPTR in one of four ways based on the point to the 64-byte block that will be erased. The Least table operation. These operations on the TBLPTR Significant bits (TBLPTR<5:0>) are ignored. affect only the low-order 21bits. Figure6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. 6.3.3 TABLE POINTER BOUNDARIES TBLPTR is used in reads, writes and erases of the Flash program memory. TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 TABLE ERASE/WRITE TABLE WRITE TBLPTR<21:n+1>(1) TBLPTR<n:0>(1) TABLE READ – TBLPTR<21:0> Note1: n = 6 for block sizes of 64 bytes.  2010-2016 Microchip Technology Inc. DS40001412G-page 93

PIC18(L)F2X/4XK22 6.4 Reading the Flash Program The internal program memory is typically organized by Memory words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure6-4 The TBLRD instruction retrieves data from program shows the interface between the internal program memory and places it into data RAM. Table reads from memory and the TABLAT. program memory are performed one byte at a time. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT (IR) FETCH TBLRD Read Register EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVFW TABLAT, W ; get data MOVF WORD_ODD DS40001412G-page 94  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 6.5 Erasing Flash Program Memory 6.5.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through The sequence of events for erasing a block of internal ICSP™ control, can larger blocks of program memory program memory is: be bulk erased. Word erase in the Flash array is not 1. Load Table Pointer register with address of supported. block being erased. When initiating an erase sequence from the 2. Set the EECON1 register for the erase operation: microcontroller itself, a block of 64 bytes of program • set EEPGD bit to point to program memory; memory is erased. The Most Significant 16 bits of the • clear the CFGS bit to access program memory; TBLPTR<21:6> point to the block being erased. The • set WREN bit to enable writes; TBLPTR<5:0> bits are ignored. • set FREE bit to enable the erase. The EECON1 register commands the erase operation. 3. Disable interrupts. The EEPGD bit must be set to point to the Flash 4. Write 55h to EECON2. program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase 5. Write 0AAh to EECON2. operation. 6. Set the WR bit. This will begin the block erase cycle. The write initiate sequence for EECON2, shown as steps 4 through 6 in Section6.5.1 “Flash Program 7. The CPU will stall for duration of the erase Memory Erase Sequence”, is used to guard against (about 2ms using internal timer). accidental writes. This is sometimes referred to as a 8. Re-enable interrupts. long write. A long write is necessary for erasing the internal Flash. Instruction execution is halted during the long write cycle. The long write is terminated by the internal programming timer. EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable block Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts  2010-2016 Microchip Technology Inc. DS40001412G-page 95

PIC18(L)F2X/4XK22 6.6 Writing to Flash Program Memory The long write is necessary for programming the internal Flash. Instruction execution is halted during a The programming block size is 64 bytes. Word or byte long write cycle. The long write will be terminated by programming is not supported. the internal programming timer. Table writes are used internally to load the holding The EEPROM on-chip timer controls the write time. registers needed to program the Flash memory. There The write/erase voltages are generated by an on-chip are only as many holding registers as there are bytes charge pump, rated to operate over the voltage range in a write block (64 bytes). of the device. Since the Table Latch (TABLAT) is only a single byte, Note: The default value of the holding registers on the TBLWT instruction needs to be executed 64 times device Resets and after write operations is for each programming operation. All of the table write FFh. A write of FFh to a holding register operations will essentially be short writes because only does not modify that byte. This means that the holding registers are written. After all the holding individual bytes of program memory may registers have been written, the programming be modified, provided that the change does operation of that block of memory is started by not attempt to change any bit from a ‘0’ to a configuring the EECON1 register for a program ‘1’. When modifying individual bytes, it is memory write and performing the long write sequence. not necessary to load all holding registers before executing a long write operation. FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxx00 TBLPTR = xxxx01 TBLPTR = xxxx02 TBLPTR = xxxxYY(1) Holding Register Holding Register Holding Register Holding Register Program Memory Note1: YY = 3F for 64 byte write blocks. 6.6.1 FLASH PROGRAM MEMORY WRITE 8. Disable interrupts. SEQUENCE 9. Write 55h to EECON2. The sequence of events for programming an internal 10. Write 0AAh to EECON2. program memory location should be: 11. Set the WR bit. This will begin the write cycle. 1. Read 64 bytes into RAM. 12. The CPU will stall for duration of the write (about 2ms using internal timer). 2. Update data values in RAM as necessary. 13. Re-enable interrupts. 3. Load Table Pointer register with address being erased. 14. Verify the memory (table read). 4. Execute the block erase procedure. This procedure will require about 6ms to update each 5. Load Table Pointer register with address of first write block of memory. An example of the required code byte being written. is given in Example6-3. 6. Write the 64-byte block into the holding registers with auto-increment. Note: Before setting the WR bit, the Table 7. Set the EECON1 register for the write operation: Pointer address needs to be within the • set EEPGD bit to point to program memory; intended address range of the bytes in the • clear the CFGS bit to access program memory; holding registers. • set WREN to enable byte writes. DS40001412G-page 96  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64’ ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L WRITE_BUFFER_BACK MOVLW BlockSize ; number of bytes in holding register MOVWF COUNTER MOVLW D’64’/BlockSize ; number of write blocks in 64 bytes MOVWF COUNTER2 WRITE_BYTE_TO_HREGS MOVF POSTINC0, W ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register.  2010-2016 Microchip Technology Inc. DS40001412G-page 97

PIC18(L)F2X/4XK22 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) DECFSZ COUNTER ; loop until holding registers are full BRA WRITE_WORD_TO_HREGS PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) DCFSZ COUNTER2 ; repeat for remaining write blocks BRA WRITE_BYTE_TO_HREGS ; BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory 6.6.2 WRITE VERIFY 6.6.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the To protect against spurious writes to Flash program memory should be verified against the original value. memory, the write initiate sequence must also be This should be used in applications where excessive followed. See Section24.0 “Special Features of the writes can stress bits near the specification limit. CPU” for more detail. 6.6.3 UNEXPECTED TERMINATION OF 6.7 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section24.5 “Program Verification and Code location just programmed should be verified and Protection” for details on code protection of Flash reprogrammed if needed. If the write operation is program memory. interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the WRERR bit will be set which the user can check to decide whether a rewrite of the location(s) is needed. TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TBLPTRU — — Program Memory Table Pointer Upper Byte (TBLPTR<21:16>) — TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) — TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) — TABLAT Program Memory Table Latch — INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 EECON2 EEPROM Control Register 2 (not a physical register) — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 92 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during Flash/EEPROM access. DS40001412G-page 98  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 7.0 DATA EEPROM MEMORY 7.2 EECON1 and EECON2 Registers The data EEPROM is a nonvolatile memory array, Access to the data EEPROM is controlled by two separate from the data RAM and program memory, registers: EECON1 and EECON2. These are the same which is used for long-term storage of program data. It registers which control access to the program memory is not directly mapped in either the register file or and are used in a similar manner for the data program memory space but is indirectly addressed EEPROM. through the Special Function Registers (SFRs). The The EECON1 register (Register7-1) is the control EEPROM is readable and writable during normal register for data and program memory access. Control operation over the entire VDD range. bit EEPGD determines if the access will be to program Four SFRs are used to read and write to the data or data EEPROM memory. When the EEPGD bit is EEPROM as well as the program memory. They are: clear, operations will access the data EEPROM memory. When the EEPGD bit is set, program memory • EECON1 is accessed. • EECON2 Control bit, CFGS, determines if the access will be to • EEDATA the Configuration registers or to program memory/data • EEADR EEPROM memory. When the CFGS bit is set, • EEADRH subsequent operations access Configuration registers. The data EEPROM allows byte read and write. When When the CFGS bit is clear, the EEPGD bit selects interfacing to the data memory block, EEDATA holds either program Flash or data EEPROM memory. the 8-bit data for read/write and the EEADR:EEADRH The WREN bit, when set, will allow a write operation. register pair hold the address of the EEPROM location On power-up, the WREN bit is clear. being accessed. The WRERR bit is set by hardware when the WR bit is The EEPROM data memory is rated for high erase/write set and cleared when the internal programming timer cycle endurance. A byte write automatically erases the expires and the write operation is complete. location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer; it will vary with voltage and temperature as well as from chip- Note: During normal operation, the WRERR to-chip. Please refer to the Data EEPROM Memory may read as ‘1’. This can indicate that a parameters in Section27.0 “Electrical Specifica- write operation was prematurely termi- tions” for limits. nated by a Reset, or a write operation was attempted improperly. 7.1 EEADR and EEADRH Registers The WR control bit initiates write operations. The bit The EEADR register is used to address the data can be set but not cleared by software. It is cleared only EEPROM for read and write operations. The 8-bit by hardware at the completion of the write operation. range of the register can address a memory range of 256 bytes (00h to FFh). The EEADRH register expands the range to 1024 bytes by adding an additional two Note: The EEIF interrupt flag bit of the PIR2 address bits. register is set when the write is complete. It must be cleared by software. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section6.1 “Table Reads and Table Writes” regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s.  2010-2016 Microchip Technology Inc. DS40001412G-page 99

PIC18(L)F2X/4XK22 REGISTER 7-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row (Block) Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) by software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS40001412G-page 100  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 7.3 Reading the Data EEPROM Additionally, the WREN bit in EECON1 must be set to Memory enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code To read a data memory location, the user must write the execution (i.e., runaway programs). The WREN bit address to the EEADR register, clear the EEPGD con- should be kept clear at all times, except when updating trol bit of the EECON1 register and then set control bit, the EEPROM. The WREN bit is not cleared by RD. The data is available on the very next instruction hardware. cycle; therefore, the EEDATA register can be read by After a write sequence has been initiated, EECON1, the next instruction. EEDATA will hold this value until EEADR and EEDATA cannot be modified. The WR bit another read operation, or until it is written to by the will be inhibited from being set unless the WREN bit is user (during a write operation). set. Both WR and WREN cannot be set with the same The basic process is shown in Example7-1. instruction. At the completion of the write cycle, the WR bit is 7.4 Writing to the Data EEPROM cleared by hardware and the EEPROM Interrupt Flag Memory bit, EEIF, is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by To write an EEPROM data location, the address must software. first be written to the EEADR register and the data writ- ten to the EEDATA register. The sequence in 7.5 Write Verify Example7-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly Depending on the application, good programming followed (write 55h to EECON2, write 0AAh to practice may dictate that the value written to the EECON2, then set WR bit) for each byte. It is strongly memory should be verified against the original value. recommended that interrupts be disabled during this This should be used in applications where excessive code segment. writes can stress bits near the specification limit. EXAMPLE 7-1: DATA EEPROM READ MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA EXAMPLE 7-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDR_LOW ; MOVWF EEADR ; Data Memory Address to write MOVLW DATA_EE_ADDR_HI ; MOVWF EEADRH ; MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable Interrupts ; User code execution BCF EECON1, WREN ; Disable writes on write complete (EEIF set)  2010-2016 Microchip Technology Inc. DS40001412G-page 101

PIC18(L)F2X/4XK22 7.6 Operation During Code-Protect 7.8 Using the Data EEPROM Data EEPROM memory has its own code-protect bits in The data EEPROM is a high-endurance, byte Configuration Words. External read and write addressable array that has been optimized for the operations are disabled if code protection is enabled. storage of frequently changing information (e.g., program variables or other data that are updated often). The microcontroller itself can both read and write to the When variables in one section change frequently, while internal data EEPROM, regardless of the state of the variables in another section do not change, it is possible code-protect Configuration bit. Refer to Section24.0 to exceed the total number of write cycles to the “Special Features of the CPU” for additional EEPROM without exceeding the total number of write information. cycles to a single byte. Refer to the Data EEPROM Memory parameters in Section27.0 “Electrical 7.7 Protection Against Spurious Write Specifications” for write cycle limits. If this is the case, There are conditions when the user may not want to then an array refresh must be performed. For this write to the data EEPROM memory. To protect against reason, variables that change infrequently (such as spurious EEPROM writes, various mechanisms have constants, IDs, calibration, etc.) should be stored in been implemented. On power-up, the WREN bit is Flash program memory. cleared. In addition, writes to the EEPROM are blocked A simple data EEPROM refresh routine is shown in during the Power-up Timer period (TPWRT).The write Example7-3. initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification. EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE CLRF EEADR ; Start at address 0 CLRF EEADRH ; if > 256 bytes EEPROM BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes Loop ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA LOOP ; Not zero, do it again INCFSZ EEADRH, F ; if > 256 bytes, Increment address BRA LOOP ; if > 256 bytes, Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts DS40001412G-page 102  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 — EEADRH(1) — — — — — — EEADR9 EEADR8 — EEDATA EEPROM Data Register — EECON2 EEPROM Control Register 2 (not a physical register) — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 100 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during EEPROM access. Note 1: PIC18(L)F26K22 and PIC18(L)F46K22 only.  2010-2016 Microchip Technology Inc. DS40001412G-page 103

PIC18(L)F2X/4XK22 8.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 8-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 8.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY operation does not affect any flags in the STATUS ROUTINE register. MOVF ARG1, W Making multiplication a hardware operation allows it to MULWF ARG2 ; ARG1 * ARG2 -> be completed in a single instruction cycle. This has the ; PRODH:PRODL advantages of higher computational throughput and BTFSC ARG2, SB ; Test Sign Bit reduced code size for multiplication algorithms and SUBWF PRODH, F ; PRODH = PRODH allows the PIC18 devices to be used in many applica- ; - ARG1 tions previously reserved for digital signal processors. MOVF ARG2, W BTFSC ARG1, SB ; Test Sign Bit A comparison of various hardware and software SUBWF PRODH, F ; PRODH = PRODH multiply operations, along with the savings in memory ; - ARG2 and execution time, is shown in Table8-1. 8.2 Operation Example8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example8-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 4.3 s 6.9 s 27.6 s 69 s 8 x 8 unsigned Hardware multiply 1 1 62.5 ns 100 ns 400 ns 1 s Without hardware multiply 33 91 5.7 s 9.1 s 36.4 s 91 s 8 x 8 signed Hardware multiply 6 6 375 ns 600 ns 2.4 s 6 s Without hardware multiply 21 242 15.1 s 24.2 s 96.8 s 242 s 16 x 16 unsigned Hardware multiply 28 28 1.8 s 2.8 s 11.2 s 28 s Without hardware multiply 52 254 15.9 s 25.4 s 102.6 s 254 s 16 x 16 signed Hardware multiply 35 40 2.5 s 4.0 s 16.0 s 40 s DS40001412G-page 104  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Example8-3 shows the sequence to do a 16 x 16 EQUATION 8-2: 16 x 16 SIGNED unsigned multiplication. Equation8-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES<3:0>). RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L = (ARG1H  ARG2H  216) + EQUATION 8-1: 16 x 16 UNSIGNED (ARG1H  ARG2L  28) + MULTIPLICATION (ARG1L  ARG2H  28) + ALGORITHM (ARG1L  ARG2L) + (-1  ARG2H<7>  ARG1H:ARG1L  216) + RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L (-1  ARG1H<7>  ARG2H:ARG2L  216) = (ARG1H  ARG2H  216) + (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + EXAMPLE 8-4: 16 x 16 SIGNED (ARG1L  ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 8-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> ; PRODH:PRODL MULTIPLY ROUTINE MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example8-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation8-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers ; SIGN_ARG1 (RES<3:0>). To account for the sign bits of the argu- BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? ments, the MSb for each argument pair is tested and BRA CONT_CODE ; no, done the appropriate subtractions are done. MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE :  2010-2016 Microchip Technology Inc. DS40001412G-page 105

PIC18(L)F2X/4XK22 9.0 INTERRUPTS 9.2 Interrupt Priority The PIC18(L)F2X/4XK22 devices have multiple The interrupt priority feature is enabled by setting the interrupt sources and an interrupt priority feature that IPEN bit of the RCON register. When interrupt priority allows most interrupt sources to be assigned a high or is enabled the GIE/GIEH and PEIE/GIEL global low priority level (INT0 does not have a priority bit, it is interrupt enable bits of Compatibility mode are replaced always a high priority). The high priority interrupt vector by the GIEH high priority, and GIEL low priority, global is at 0008h and the low priority interrupt vector is at interrupt enables. When set, the GIEH bit of the 0018h. A high priority interrupt event will interrupt a low INTCON register enables all interrupts that have their priority interrupt that may be in progress. associated IPRx register or INTCONx register priority bit set (high priority). When clear, the GIEH bit disables There are 19 registers used to control interrupt all interrupt sources including those selected as low operation. priority. When clear, the GIEL bit of the INTCON These registers are: register disables only the interrupts that have their • INTCON, INTCON2, INTCON3 associated priority bit cleared (low priority). When set, the GIEL bit enables the low priority sources when the • PIR1, PIR2, PIR3, PIR4, PIR5 GIEH bit is also set. • PIE1, PIE2, PIE3, PIE4, PIE5 When the interrupt flag, enable bit and appropriate • IPR1, IPR2, IPR3, IPR4, IPR5 Global Interrupt Enable (GIE) bit are all set, the • RCON interrupt will vector immediately to address 0008h for It is recommended that the Microchip header files high priority, or 0018h for low priority, depending on supplied with MPLAB® IDE be used for the symbolic bit level of the interrupting source’s priority bit. Individual names in these registers. This allows the assembler/ interrupts can be disabled through their corresponding compiler to automatically take care of the placement of interrupt enable bits. these bits within the specified register. In general, interrupt sources have three bits to control 9.3 Interrupt Response their operation. They are: When an interrupt is responded to, the Global Interrupt • Flag bit to indicate that an interrupt event Enable bit is cleared to disable further interrupts. The occurred GIE/GIEH bit is the Global Interrupt Enable when the • Enable bit that allows program execution to IPEN bit is cleared. When the IPEN bit is set, enabling branch to the interrupt vector address when the interrupt priority levels, the GIEH bit is the high priority flag bit is set global interrupt enable and the GIEL bit is the low • Priority bit to select high priority or low priority priority Global Interrupt Enable. High priority interrupt sources can interrupt a low priority interrupt. Low 9.1 Mid-Range Compatibility priority interrupts are not processed while high priority interrupts are in progress. When the IPEN bit is cleared (default state), the interrupt The return address is pushed onto the stack and the priority feature is disabled and interrupts are compatible PC is loaded with the interrupt vector address (0008h with PIC® microcontroller mid-range devices. In or 0018h). Once in the Interrupt Service Routine, the Compatibility mode, the interrupt priority bits of the IPRx source(s) of the interrupt can be determined by polling registers have no effect. The PEIE/GIEL bit of the the interrupt flag bits in the INTCONx and PIRx INTCON register is the global interrupt enable for the registers. The interrupt flag bits must be cleared by peripherals. The PEIE/GIEL bit disables only the software before re-enabling interrupts to avoid peripheral interrupt sources and enables the peripheral repeating the same interrupt. interrupt sources when the GIE/GIEH bit is also set. The GIE/GIEH bit of the INTCON register is the global The “return from interrupt” instruction, RETFIE, exits interrupt enable which enables all non-peripheral the interrupt routine and sets the GIE/GIEH bit (GIEH interrupt sources and disables all interrupt sources, or GIEL if priority levels are used), which re-enables including the peripherals. All interrupts branch to interrupts. address 0008h in Compatibility mode. For external interrupt events, such as the INT pins or the PORTB interrupt-on-change, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one-cycle or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bits or the Global Interrupt Enable bit. DS40001412G-page 106  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. FIGURE 9-1: PIC18 INTERRUPT LOGIC Wake-up if in INT0IF Idle or Sleep modes INT0IE TMR0IF TMR0IE TMR0IP RBIF (1) RBIE RBIP INT1IF Interrupt to CPU PPIPIIRER111 <<<666:::000>>> IINNTT11IIEP 0V0e0c8tohr to Location INT2IF PIR2<7:0> INT2IE PIE2<7:0> INT2IP IPR2<7:0> GIEH/GIE PIR3<7:0> PIE3<7:0> IPR3<7:0> IPEN PIR4<2:0> PIE4<2:0> IPEN IPR4<2:0> GIEL/PEIE PPIIRE55 <<22::00>> IPEN IPR5 <2:0> High Priority Interrupt Generation Low Priority Interrupt Generation PIR1<6:0> PIE1 <6:0> IPR1 <6:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> Interrupt to CPU TMR0IF Vector to Location PPIIRE44<<22::00>> TTMMRR00IIEP 0018h IPR4<2:0> PIR5 <2:0> RBIF (1) PIE5 <2:0> RBIE IPR5<2:0> RBIP GIEH/GIE GIEL/PEIE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Note 1: The RBIF interrupt also requires the individual pin IOCB enables.  2010-2016 Microchip Technology Inc. DS40001412G-page 107

PIC18(L)F2X/4XK22 9.4 INTCON Registers The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. 9.5 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are five Peripheral Interrupt Request Flag registers (PIR1, PIR2, PIR3, PIR4 and PIR5). 9.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are five Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3, PIE4 and PIE5). When IPEN = 0, the PEIE/GIEL bit must be set to enable any of these peripheral interrupts. 9.7 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are five Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3, IPR4 and IPR5). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. DS40001412G-page 108  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 9.8 Register Definitions: Interrupt Control REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts including peripherals When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts including low priority bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority interrupts 0 = Disables all low priority interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: Port B Interrupt-On-Change (IOCx) Interrupt Enable bit(2) 1 = Enables the IOCx port change interrupt 0 = Disables the IOCx port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared by software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared by software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: Port B Interrupt-On-Change (IOCx) Interrupt Flag bit(1) 1 = At least one of the IOC<3:0> (RB<7:4>) pins changed state (must be cleared by software) 0 = None of the IOC<3:0> (RB<7:4>) pins have changed state Note 1: A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. 2: RB port change interrupts also require the individual pin IOCB enables. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2010-2016 Microchip Technology Inc. DS40001412G-page 109

PIC18(L)F2X/4XK22 REGISTER 9-2: INTCON2: INTERRUPT CONTROL 2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled provided that the pin is an input and the corresponding WPUB bit is set. bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS40001412G-page 110  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 9-3: INTCON3: INTERRUPT CONTROL 3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared by software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared by software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2010-2016 Microchip Technology Inc. DS40001412G-page 111

PIC18(L)F2X/4XK22 REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’. bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared by software) 0 = The A/D conversion is not complete or has not been started bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART1 receive buffer is empty bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART1 transmit buffer is full bit 3 SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared by software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR register capture occurred (must be cleared by software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared by software) 0 = No TMR register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared by software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared by software) 0 = TMR1 register did not overflow Note1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE/ GIEH of the INTCON register. Note: User software should ensure the appro- priate interrupt flag bits are cleared prior to enabling an interrupt and after servic- ing that interrupt. DS40001412G-page 112  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software) 0 = Device clock operating bit 6 C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator C1 output has changed (must be cleared by software) 0 = Comparator C1 output has not changed bit 5 C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator C2 output has changed (must be cleared by software) 0 = Comparator C2 output has not changed bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared by software) 0 = The write operation is not complete or has not been started bit 3 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared by software) 0 = No bus collision occurred bit 2 HLVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (direction determined by the VDIRMAG bit of the HLVDCON register) 0 = A low-voltage condition has not occurred bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared by software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR register capture occurred (must be cleared by software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared by software) 0 = No TMR register compare match occurred PWM mode: Unused in this mode.  2010-2016 Microchip Technology Inc. DS40001412G-page 113

PIC18(L)F2X/4XK22 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 6 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = A bus collision has occurred while the SSP2 module configured in I2C master was transmitting (must be cleared in software) 0 = No bus collision occurred bit 5 RC2IF: EUSART2 Receive Interrupt Flag bit 1 = The EUSART2 receive buffer, RCREG2, is full (cleared by reading RCREG2) 0 = The EUSART2 receive buffer is empty bit 4 TX2IF: EUSART2 Transmit Interrupt Flag bit 1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared by writing TXREG2) 0 = The EUSART2 transmit buffer is full bit 3 CTMUIF: CTMU Interrupt Flag bit 1 = CTMU interrupt occurred (must be cleared in software) 0 = No CTMU interrupt occurred bit 2 TMR5GIF: TMR5 Gate Interrupt Flag bits 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate occurred bit 1 TMR3GIF: TMR3 Gate Interrupt Flag bits 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate occurred bit 0 TMR1GIF: TMR1 Gate Interrupt Flag bits 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate occurred DS40001412G-page 114  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 9-7: PIR4: PERIPHERAL INTERRUPT (FLAG) REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 CCP5IF: CCP5 Interrupt Flag bits Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Unused in PWM mode. bit 1 CCP4IF: CCP4 Interrupt Flag bits Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Unused in PWM mode. bit 0 CCP3IF: ECCP3 Interrupt Flag bits Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Unused in PWM mode.  2010-2016 Microchip Technology Inc. DS40001412G-page 115

PIC18(L)F2X/4XK22 REGISTER 9-8: PIR5: PERIPHERAL INTERRUPT (FLAG) REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TMR6IF TMR5IF TMR4IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = TMR6 to PR6 match occurred (must be cleared in software) 0 = No TMR6 to PR6 match occurred bit 1 TMR5IF: TMR5 Overflow Interrupt Flag bit 1 = TMR5 register overflowed (must be cleared in software) 0 = TMR5 register did not overflow bit 0 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred DS40001412G-page 116  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 9-9: PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’. bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enables the EUSART1 receive interrupt 0 = Disables the EUSART1 receive interrupt bit 4 TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enables the EUSART1 transmit interrupt 0 = Disables the EUSART1 transmit interrupt bit 3 SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt  2010-2016 Microchip Technology Inc. DS40001412G-page 117

PIC18(L)F2X/4XK22 REGISTER 9-10: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 C1IE: Comparator C1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 C2IE: Comparator C2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS40001412G-page 118  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 9-11: PIE3: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt bit 6 BCL2IE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 CTMUIE: CTMU Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 TMR5GIE: TMR5 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3GIE: TMR3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1GIE: TMR1 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled  2010-2016 Microchip Technology Inc. DS40001412G-page 119

PIC18(L)F2X/4XK22 REGISTER 9-12: PIE4: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 CCP5IE: CCP5 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: CCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled REGISTER 9-13: PIE5: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TMR6IE TMR5IE TMR4IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the TMR6 to PR6 match interrupt 0 = Disables the TMR6 to PR6 match interrupt bit 1 TMR5IE: TMR5 Overflow Interrupt Enable bit 1 = Enables the TMR5 overflow interrupt 0 = Disables the TMR5 overflow interrupt bit 0 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 match interrupt 0 = Disables the TMR4 to PR4 match interrupt DS40001412G-page 120  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 9-14: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority  2010-2016 Microchip Technology Inc. DS40001412G-page 121

PIC18(L)F2X/4XK22 REGISTER 9-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 C1IP: Comparator C1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 C2IP: Comparator C2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCL1IP: MSSP1 Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority DS40001412G-page 122  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 9-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IP: Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 CTMUIP: CTMU Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 TMR5GIP: TMR5 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1GIP: TMR1 Gate Interrupt Priority bit 1 = High priority 0 = Low priority  2010-2016 Microchip Technology Inc. DS40001412G-page 123

PIC18(L)F2X/4XK22 REGISTER 9-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 CCP5IP: CCP5 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP3IP: CCP3 Interrupt Priority bit 1 = High priority 0 = Low priority REGISTER 9-18: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TMR6IP TMR5IP TMR4IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 TMR6IP: TMR6 to PR6 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR5IP: TMR5 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit 1 = High priority 0 = Low priority DS40001412G-page 124  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 9.9 INTn Pin Interrupts 9.10 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1 and In 8-bit mode (which is the default), an overflow in the RB2/INT2 pins are edge-triggered. If the corresponding TMR0 register (FFh00h) will set flag bit, TMR0IF. In INTEDGx bit in the INTCON2 register is set (= 1), the 16-bit mode, an overflow in the TMR0H:TMR0L regis- interrupt is triggered by a rising edge; if the bit is clear, ter pair (FFFFh 0000h) will set TMR0IF. The interrupt the trigger is on the falling edge. When a valid edge can be enabled/disabled by setting/clearing enable bit, appears on the RBx/INTx pin, the corresponding flag TMR0IE of the INTCON register. Interrupt priority for bit, INTxF, is set. This interrupt can be disabled by Timer0 is determined by the value contained in the clearing the corresponding enable bit, INTxE. Flag bit, interrupt priority bit, TMR0IP of the INTCON2 register. INTxF, must be cleared by software in the Interrupt See Section11.0 “Timer0 Module” for further details Service Routine before re-enabling the interrupt. on the Timer0 module. All external interrupts (INT0, INT1 and INT2) can wake- 9.11 PORTB Interrupt-on-Change up the processor from Idle or Sleep modes if bit INTxE was set prior to going into those modes. If the Global An input change on PORTB<7:4> sets flag bit, RBIF of Interrupt Enable bit, GIE/GIEH, is set, the processor the INTCON register. The interrupt can be enabled/ will branch to the interrupt vector following wake-up. disabled by setting/clearing enable bit, RBIE of the Interrupt priority for INT1 and INT2 is determined by INTCON register. Pins must also be individually the value contained in the interrupt priority bits, INT1IP enabled with the IOCB register. Interrupt priority for and INT2IP of the INTCON3 register. There is no prior- PORTB interrupt-on-change is determined by the value ity bit associated with INT0. It is always a high priority contained in the interrupt priority bit, RBIP of the interrupt source. INTCON2 register. 9.12 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section5.2.1 “Fast Register Stack”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS  2010-2016 Microchip Technology Inc. DS40001412G-page 125

PIC18(L)F2X/4XK22 TABLE 9-1: REGISTERS ASSOCIATED WITH INTERRUPTS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 110 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 111 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 153 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 IPR4 — — — — — CCP5IP CCP4IP CCP3IP 124 IPR5 — — — — — TMR6IP TMR5IP TMR4IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIE4 — — — — — CCP5IE CCP4IE CCP3IE 120 PIE5 — — — — — TMR6IE TMR5IE TMR4IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PIR4 — — — — — CCP5IF CCP4IF CCP3IF 115 PIR5 — — — — — TMR6IF TMR5IF TMR4IF 116 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 148 RCON IPEN SBOREN — RI TO PD POR BOR 56 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts. TABLE 9-2: CONFIGURATION REGISTERS ASSOCIATED WITH INTERRUPTS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 CONFIG4L DEBUG XINST — — — LVP — STRVEN 349 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts. DS40001412G-page 126  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 10.0 I/O PORTS 10.1 PORTA Registers Depending on the device selected and features PORTA is an 8-bit wide, bidirectional port. The enabled, there are up to five ports available. All pins of corresponding data direction register is TRISA. Setting the I/O ports are multiplexed with one or more alternate a TRISA bit (= 1) will make the corresponding PORTA functions from the peripheral features on the device. In pin an input (i.e., disable the output driver). Clearing a general, when a peripheral is enabled, that pin may not TRISA bit (= 0) will make the corresponding PORTA pin be used as a general purpose I/O pin. an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Each port has five registers for its operation. These registers are: Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the PORT latch. • TRIS register (data direction register) • PORT register (reads the levels on the pins of the The Data Latch (LATA) register is also memory mapped. device) Read-modify-write operations on the LATA register read and write the latched output value for PORTA. • LAT register (output latch) • ANSEL register (analog input control) The RA4 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to • SLRCON register (port slew rate control) become the RA4/T0CKI/C1OUT pin. Pins RA6 and The Data Latch (LAT register) is useful for read-modify- RA7 are multiplexed with the main oscillator pins; they write operations on the value that the I/O pins are are enabled as oscillator or I/O pins by the selection of driving. the main oscillator in the Configuration register (see A simplified model of a generic I/O port, without the Section24.1 “Configuration Bits” for details). When interfaces to other peripherals, is shown in Figure10-1. they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’. FIGURE 10-1: GENERIC I/O PORT The other PORTA pins are multiplexed with analog OPERATION inputs, the analog VREF+ and VREF- inputs, and the comparator voltage reference output. The operation of pins RA<3:0> and RA5 as analog is selected by setting RD LAT the ANSELA<5, 3:0> bits in the ANSELA register which is the default setting after a Power-on Reset. Data Bus Pins RA0 through RA5 may also be used as comparator D Q inputs or outputs by setting the appropriate bits in the WR LAT I/O pin(1) orPort CM1CON0 and CM2CON0 registers. CK Data Latch Note: On a Power-on Reset, RA5 and RA<3:0> TRISx are configured as analog inputs and read D Q ANSELx as ‘0’. RA4 is configured as a digital input. WR TRIS The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input. CK All other PORTA pins have TTL input levels and full TRIS Latch Input CMOS output drivers. Buffer The TRISA register controls the drivers of the PORTA RD TRIS pins, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register Q D are maintained set when using them as analog inputs. ENEN EXAMPLE 10-1: INITIALIZING PORTA RD Port MOVLB 0xF ; Set BSR for banked SFRs CLRF PORTA ; Initialize PORTA by Note1: I/O pins have diode protection to VDD and VSS. ; clearing output ; data latches CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW E0h ; Configure I/O MOVWF ANSELA ; for digital inputs MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs  2010-2016 Microchip Technology Inc. DS40001412G-page 127

PIC18(L)F2X/4XK22 TABLE 10-1: PORTA I/O SUMMARY TRIS ANSEL Pin Buffer Pin Name Function Description Setting Setting Type Type RA0/C12IN0-/AN0 RA0 0 0 O DIG LATA<0> data output; not affected by analog input. 1 0 I TTL PORTA<0> data input; disabled when analog input enabled. C12IN0- 1 1 I AN Comparators C1 and C2 inverting input. AN0 1 1 I AN Analog input 0. RA1/C12IN1-/AN1 RA1 0 0 O DIG LATA<1> data output; not affected by analog input. 1 0 I TTL PORTA<1> data input; disabled when analog input enabled. C12IN1- 1 1 I AN Comparators C1 and C2 inverting input. AN1 1 1 I AN Analog input 1. RA2/C2IN+/AN2/ RA2 0 0 O DIG LATA<2> data output; not affected by analog input; disabled when DACOUT/VREF- DACOUT enabled. 1 0 I TTL PORTA<2> data input; disabled when analog input enabled; disabled when DACOUT enabled. C2IN+ 1 1 I AN Comparator C2 non-inverting input. AN2 1 1 I AN Analog output 2. DACOUT x 1 O AN DAC Reference output. VREF- 1 1 I AN A/D reference voltage (low) input. RA3/C1IN+/AN3/ RA3 0 O DIG LATA<3> data output; not affected by analog input. VREF+ 1 0 I TTL PORTA<3> data input; disabled when analog input enabled. C1IN+ 1 1 I AN Comparator C1 non-inverting input. AN3 1 1 I AN Analog input 3. VREF+ 1 1 I AN A/D reference voltage (high) input. RA4/CCP5/C1OUT/ RA4 0 — O DIG LATA<4> data output. SRQ/T0CKI 1 — I ST PORTA<4> data input; default configuration on POR. CCP5 0 — O DIG CCP5 Compare output/PWM output, takes priority over RA4 output. 1 — I ST Capture 5 input/Compare 5 output/ PWM 5 output. C1OUT 0 — O DIG Comparator C1 output. SRQ 0 — O DIG SR latch Q output; take priority over CCP 5 output. T0CKI 1 — I ST Timer0 external clock input. RA5/C2OUT/SRNQ/ RA5 0 0 O DIG LATA<5> data output; not affected by analog input. SS1/ 1 0 I TTL PORTA<5> data input; disabled when analog input enabled. HLVDIN/AN4 C2OUT 0 0 O DIG Comparator C2 output. SRNQ 0 0 O DIG SR latch Q output. SS1 1 0 I TTL SPI slave select input (MSSP1). HLVDIN 1 1 I AN High/Low-Voltage Detect input. AN4 1 1 I AN A/D input 4. RA6/CLKO/OSC2 RA6 0 — O DIG LATA<6> data output; enabled in INTOSC modes when CLKO is not enabled. 1 — I TTL PORTA<6> data input; enabled in INTOSC modes when CLKO is not enabled. CLKO x — O DIG In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the fre- quency of OSC1 and denotes the instruction cycle rate. OSC2 x — O XTAL Oscillator crystal output; connects to crystal or resonator in Crystal Oscillator mode. RA7/CLKI/OSC1 RA7 0 — O DIG LATA<7> data output; disabled in external oscillator modes. 1 — I TTL PORTA<7> data input; disabled in external oscillator modes. CLKI x — I AN External clock source input; always associated with pin function OSC1. OSC1 x — I XTAL Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. DS40001412G-page 128  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 10-2: REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 149 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH<1:0> 308 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH<1:0> 308 LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 152 VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 335 VREFCON2 — — — DACR<4:0> 336 HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> 337 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 148 SLRCON — — — SLRE SLRD SLRC SLRB SLRA 153 SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 329 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 253 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS<2:0> 154 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTA. TABLE 10-3: CONFIGURATION REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG1H IESO FCMEN PRICLKEN PLLCFG FOSC<3:0> 345 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTA.  2010-2016 Microchip Technology Inc. DS40001412G-page 129

PIC18(L)F2X/4XK22 10.1.1 PORTA OUTPUT PRIORITY Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table10-4 lists the PORTA pin functions from the highest to the lowest priority. Analog input functions, such as ADC and comparator, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. TABLE 10-4: PORT PIN FUNCTION PRIORITY Port Function Priority by Port Pin Port bit PORTA PORTB PORTC PORTD(2) PORTE(2) 0 RA0 CCP4(1) SOSCO SCL2 CCP3(8) RB0 P2B(6) SCK2 P3A(8) RC0 RD0 RE0 1 RA1 SCL2(1) SOSCI SDA2 P3B SCK2(1) CCP2(3) CCP4 RE1 P1C(1) P2A(3) RD1 RB1 RC1 2 RA2 SDA2(1) CCP1 P2B CCP5 P1B(1) P1A RD2(4) RE2 RB2 CTPLS RC2 3 RA3 SDO2(1) SCL1 P2C MCLR CCP2(6) SCK1 RD3 VPP P2A(6) RC3 RE3 RB3 4 SRQ P1D(1) SDA1 SDO2 C1OUT RB4 RC4 P2D CCP5(1) RD4 RA4 Note 1: PIC18(L)F2XK22 devices. 2: PIC18(L)F4XK22 devices. 3: Function default pin. 4: Function default pin (28-pin devices). 5: Function default pin (40/44-pin devices). 6: Function alternate pin. 7: Function alternate pin (28-pin devices). 8: Function alternate pin (40/44-pin devices) DS40001412G-page 130  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 10-4: PORT PIN FUNCTION PRIORITY (CONTINUED) Port Function Priority by Port Pin Port bit PORTA PORTB PORTC PORTD(2) PORTE(2) 5 SRNQ CCP3(3) SDO1 P1B C2OUT P3A(3) RC5 RD5 RA5 P2B(1)(4) RB5 6 OSC2 PGC TX1/CK1 TX2/CK2 CLKO TX2/CK2(1) CCP3(1)(7) P1C RA6 RB6 P3A(1)(7) RD6 ICDCK RC6 7 RA7 OSC1 PGD RX1/DT1 RX2/DT2 RA7 RX2/DT2(1) P3B(1) P1D RB7 RC7 RD7 ICDDT Note 1: PIC18(L)F2XK22 devices. 2: PIC18(L)F4XK22 devices. 3: Function default pin. 4: Function default pin (28-pin devices). 5: Function default pin (40/44-pin devices). 6: Function alternate pin. 7: Function alternate pin (28-pin devices). 8: Function alternate pin (40/44-pin devices)  2010-2016 Microchip Technology Inc. DS40001412G-page 131

PIC18(L)F2X/4XK22 10.2 PORTB Registers 10.3 Additional PORTB Pin Functions PORTB is an 8-bit wide, bidirectional port. The PORTB pins RB<7:4> have an interrupt-on-change corresponding data direction register is TRISB. Setting option. All PORTB pins have a weak pull-up option. a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a 10.3.1 WEAK PULL-UPS TRISB bit (= 0) will make the corresponding PORTB Each of the PORTB pins has an individually controlled pin an output (i.e., enable the output driver and put the weak internal pull-up. When set, each bit of the WPUB contents of the output latch on the selected pin). register enables the corresponding pin pull-up. When The Data Latch register (LATB) is also memory cleared, the RBPU bit of the INTCON2 register enables mapped. Read-modify-write operations on the LATB pull-ups on all pins which also have their corresponding register read and write the latched output value for WPUB bit set. When set, the RBPU bit disables all PORTB. weak pull-ups. The weak pull-up is automatically turned off when the port pin is configured as an output. The EXAMPLE 10-2: INITIALIZING PORTB pull-ups are disabled on a Power-on Reset. MOVLB 0xF ; Set BSR for banked SFRs CLRF PORTB ; Initialize PORTB by ; clearing output Note: On a Power-on Reset, RB<5:0> are ; data latches configured as analog inputs by default and CLRF LATB ; Alternate method read as ‘0’; RB<7:6> are configured as ; to clear output digital inputs. ; data latches MOVLW 0F0h ; Value for init When the PBADEN Configuration bit is MOVWF ANSELB ; Enable RB<3:0> for set to ‘1’, RB<5:0> will alternatively be ; digital input pins configured as digital inputs on POR. ; (not required if config bit ; PBADEN is clear) 10.3.2 INTERRUPT-ON-CHANGE MOVLW 0CFh ; Value used to ; initialize data Four of the PORTB pins (RB<7:4>) are individually ; direction configurable as interrupt-on-change pins. Control bits MOVWF TRISB ; Set RB<3:0> as inputs in the IOCB register enable (when set) or disable (when ; RB<5:4> as outputs clear) the interrupt function for each pin. ; RB<7:6> as inputs When set, the RBIE bit of the INTCON register enables interrupts on all pins which also have their 10.2.1 PORTB OUTPUT PRIORITY corresponding IOCB bit set. When clear, the RBIE bit Each PORTB pin is multiplexed with other functions. disables all interrupt-on-changes. The pins, their combined functions and their output Only pins configured as inputs can cause this interrupt priorities are briefly described here. For additional to occur (i.e., any RB<7:4> pin configured as an output information, refer to the appropriate section in this data is excluded from the interrupt-on-change comparison). sheet. For enabled interrupt-on-change pins, the values are When multiple outputs are enabled, the actual pin compared with the old value latched on the last read of control goes to the peripheral with the higher priority. PORTB. The ‘mismatch’ outputs of the last read are Table10-4 lists the PORTB pin functions from the OR’d together to set the PORTB Change Interrupt flag highest to the lowest priority. bit (RBIF) in the INTCON register. Analog input functions, such as ADC, comparator and This interrupt can wake the device from the Sleep SR latch inputs, are not shown in the priority lists. mode, or any of the Idle modes. The user, in the These inputs are active when the I/O pin is set for Interrupt Service Routine, can clear the interrupt in the Analog mode using the ANSELx registers. Digital following manner: output functions may control the pin when it is in Analog a) Any read or write of PORTB to clear the mis- mode with the priority shown below. match condition (except when PORTB is the source or destination of a MOVFF instruction). b) Execute at least one instruction after reading or writing PORTB, then clear the flag bit, RBIF. DS40001412G-page 132  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 A mismatch condition will continue to set the RBIF flag bit. 10.3.3 ALTERNATE FUNCTIONS Reading or writing PORTB will end the mismatch PORTB is multiplexed with several peripheral functions condition and allow the RBIF bit to be cleared. The latch (Table10-5). The pins have TTL input buffers. Some of holding the last read value is not affected by a MCLR nor these pin functions can be relocated to alternate pins Brown-out Reset. After either one of these Resets, the using the Control fuse bits in CONFIG3H. RB5 is the RBIF flag will continue to be set if a mismatch is present. default pin for P2B (28-pin devices). Clearing the P2BMX bit moves the pin function to RC0. RB5 is also the default pin for the CCP3/P3A peripheral pin. Clear- Note: If a change on the I/O pin should occur ing the CCP3MX bit moves the pin function to the RC6 when the read operation is being executed pin (28-pin devices) or RE0 (40/44-pin devices). (start of the Q2 cycle), then the RBIF interrupt flag may not getset. Furthermore, Two other pin functions, T3CKI and CCP2/P2A, can be since a read or write on a port affects all relocated from their default pins to PORTB pins by bits of that port, care must be taken when clearing the control fuses in CONFIG3H. Clearing using multiple pins in Interrupt-on-change T3CMX and CCP2MX moves the pin functions to RB5 mode. Changes on one pin may not be and RB3, respectively. seen while servicing changes on another pin. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. TABLE 10-5: PORTB I/O SUMMARY TRIS ANSEL Pin Buffer Pin Function Description Setting Setting Type Type RB0/INT0/CCP4/ RB0 0 0 O DIG LATB<0> data output; not affected by analog input. FLT0/SRI/SS2/ 1 0 I TTL PORTB<0> data input; disabled when analog input AN12 enabled. INT0 1 0 I ST External interrupt 0. CCP4(3) 0 0 O DIG Compare 4 output/PWM 4 output. 1 0 I ST Capture 4 input. FLT0 1 0 I ST PWM Fault input for ECCP auto-shutdown. SRI 1 0 I ST SR latch input. SS2(3) 1 0 I TTL SPI slave select input (MSSP2). AN12 1 1 I AN Analog input 12. RB1/INT1/P1C/ RB1 0 0 O DIG LATB<1> data output; not affected by analog input. SCK2/SCL2/ 1 0 I TTL PORTB<1> data input; disabled when analog input C12IN3-/AN10 enabled. INT1 1 0 I ST External Interrupt 1. P1C(3) 0 0 O DIG Enhanced CCP1 PWM output 3. SCK2(3) 0 0 O DIG MSSP2 SPI Clock output. 1 0 I ST MSSP2 SPI Clock input. SCL2(3) 0 0 O DIG MSSP2 I2C Clock output. 1 0 I I2C MSSP2 I2C Clock input. C12IN3- 1 1 I AN Comparators C1 and C2 inverting input. AN10 1 1 I AN Analog input 10. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. 3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.  2010-2016 Microchip Technology Inc. DS40001412G-page 133

PIC18(L)F2X/4XK22 TABLE 10-5: PORTB I/O SUMMARY (CONTINUED) TRIS ANSEL Pin Buffer Pin Function Description Setting Setting Type Type RB2/INT2/CTED1/ RB2 0 0 O DIG LATB<2> data output; not affected by analog input. P1B/SDI2/SDA2/ 1 0 I TTL PORTB<2> data input; disabled when analog input AN8 enabled. INT2 1 0 I ST External interrupt 2. CTED1 1 0 I ST CTMU Edge 1 input. P1B(3) 0 0 O DIG Enhanced CCP1 PWM output 2. SDI2(3) 1 0 I ST MSSP2 SPI data input. SDA2(3) 0 0 O DIG MSSP2 I2C data output. 1 0 I I2C MSSP2 I2C data input. AN8 1 1 I AN Analog input 8. RB3/CTED2/P2A/ RB3 0 0 O DIG LATB<3> data output; not affected by analog input. CCP2/SDO2/ 1 0 I TTL PORTB<3> data input; disabled when analog input C12IN2-/AN9 enabled. CTED2 1 0 I ST CTMU Edge 2 input. P2A 0 0 O DIG Enhanced CCP1 PWM output 1. CCP2(2) 0 0 O DIG Compare 2 output/PWM 2 output. 1 0 I ST Capture 2 input. SDO2(2) 0 0 O DIG MSSP2 SPI data output. C12IN2- 1 1 I AN Comparators C1 and C2 inverting input. AN9 1 1 I AN Analog input 9. RB4/IOC0/P1D/ RB4 0 0 O DIG LATB<4> data output; not affected by analog input. T5G/AN11 1 0 I TTL PORTB<4> data input; disabled when analog input enabled. IOC0 1 0 I TTL Interrupt-on-change pin. P1D 0 0 O DIG Enhanced CCP1 PWM output 4. T5G 1 0 I ST Timer5 external clock gate input. AN11 1 1 I AN Analog input 11. RB5/IOC1/P2B/ RB5 0 0 O DIG LATB<5> data output; not affected by analog input. P3A/CCP3/T3CKI/ 1 0 I TTL PORTB<5> data input; disabled when analog input T1G/AN13 enabled. IOC1 1 0 I TTL Interrupt-on-change pin 1. P2B(1)(3) 0 0 O DIG Enhanced CCP2 PWM output 2. P3A(1) 0 0 O DIG Enhanced CCP3 PWM output 1. CCP3(1) 0 0 O DIG Compare 3 output/PWM 3 output. 1 0 I ST Capture 3 input. T3CKI(2) 1 0 I ST Timer3 clock input. T1G 1 0 I ST Timer1 external clock gate input. AN13 1 1 I AN Analog input 13. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. 3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices. DS40001412G-page 134  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 10-5: PORTB I/O SUMMARY (CONTINUED) TRIS ANSEL Pin Buffer Pin Function Description Setting Setting Type Type RB6/KBI2/PGC RB6 0 — O DIG LATB<6> data output; not affected by analog input. 1 — I TTL PORTB<6> data input; disabled when analog input enabled. IOC2 1 — I TTL Interrupt-on-change pin. TX2(3) 1 — O DIG EUSART asynchronous transmit data output. CK2(3) 1 — O DIG EUSART synchronous serial clock output. 1 — I ST EUSART synchronous serial clock input. PGC x — I ST In-Circuit Debugger and ICSPTM programming clock input. RB7/KBI3/PGD RB7 0 — O DIG LATB<7> data output; not affected by analog input. 1 — I TTL PORTB<7> data input; disabled when analog input enabled. IOC3 1 — I TTL Interrupt-on-change pin. RX2(2), (3) 1 — I ST EUSART asynchronous receive data input. DT2(2), (3) 1 — O DIG EUSART synchronous serial data output. 1 — I ST EUSART synchronous serial data input. PGD x — O DIG In-Circuit Debugger and ICSPTM programming data output. x — I ST In-Circuit Debugger and ICSPTM programming data input. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. 3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.  2010-2016 Microchip Technology Inc. DS40001412G-page 135

PIC18(L)F2X/4XK22 TABLE 10-6: REGISTERS ASSOCIATED WITH PORTB Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150 ECCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 202 CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 198 ECCP3AS CCP3ASE CCP3AS<2:0> PSS3AC<1:0> PSS3BD<1:0> 202 CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 198 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 110 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 111 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 153 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 152 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 148 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 153 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 167 T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 166 T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL T5GSS<1:0> 167 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 152 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB. Note 1: Available on PIC18(L)F4XK22 devices. TABLE 10-7: CONFIGURATION REGISTERS ASSOCIATED WITH PORTB Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 CONFIG4L DEBUG XINST — — — LVP(1) — STRVEN 349 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB. Note 1: Can only be changed when in high voltage programming mode. DS40001412G-page 136  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 10.4 PORTC Registers EXAMPLE 10-3: INITIALIZING PORTC MOVLB 0xF ; Set BSR for banked SFRs PORTC is an 8-bit wide, bidirectional port. The CLRF PORTC ; Initialize PORTC by corresponding data direction register is TRISC. Setting ; clearing output a TRISC bit (= 1) will make the corresponding PORTC ; data latches pin an input (i.e., disable the output driver). Clearing a CLRF LATC ; Alternate method TRISC bit (= 0) will make the corresponding PORTC ; to clear output pin an output (i.e., enable the output driver and put the ; data latches contents of the output latch on the selected pin). MOVLW 0CFh ; Value used to ; initialize data The Data Latch register (LATC) is also memory ; direction mapped. Read-modify-write operations on the LATC MOVWF TRISC ; Set RC<3:0> as inputs register read and write the latched output value for ; RC<5:4> as outputs PORTC. ; RC<7:6> as inputs PORTC is multiplexed with several peripheral functions MOVLW 30h ; Value used to ; enable digital inputs (Table10-8). The pins have Schmitt Trigger input MOVWF ANSELC ; RC<3:2> dig input enable buffers. ; No ANSEL bits for RC<1:0> Some of these pin functions can be relocated to ; RC<7:6> dig input enable alternate pins using the Control fuse bits in CONFIG3H. RC0 is the default pin for T3CKI. Clearing 10.4.1 PORTC OUTPUT PRIORITY the T3CMX bit moves the pin function to RB5. RC1 is Each PORTC pin is multiplexed with other functions. the default pin for the CCP2 peripheral pin. Clearing the The pins, their combined functions and their output CCP2MX bit moves the pin function to the RB3 pin. priorities are briefly described here. For additional Two other pin functions, P2B and CCP3, can be information, refer to the appropriate section in this data relocated from their default pins to PORTC pins by sheet. clearing the control fuses in CONFIG3H. Clearing When multiple outputs are enabled, the actual pin P2BMX and CCP3MX moves the pin functions to RC0 and RC6(1)/RE0(2), respectively. control goes to the peripheral with the higher priority. Table10-4 lists the PORTC pin functions from the When enabling peripheral functions, care should be highest to the lowest priority. taken in defining TRIS bits for each PORTC pin. The Analog input functions, such as ADC, comparator and EUSART and MSSP peripherals override the TRIS bit SR latch inputs, are not shown in the priority lists. to make a pin an output or an input, depending on the peripheral configuration. Refer to the corresponding These inputs are active when the I/O pin is set for peripheral section for additional information. Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. Note: On a Power-on Reset, these pins are configured as analog inputs. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins.  2010-2016 Microchip Technology Inc. DS40001412G-page 137

PIC18(L)F2X/4XK22 TABLE 10-8: PORTC I/O SUMMARY TRIS ANSEL Pin Buffer Pin Name Function Description Setting setting Type Type RC0/P2B/T3CKI/T3G/ RC0 0 — O DIG LATC<0> data output; not affected by analog input. T1CKI/SOSCO 1 — I ST PORTC<0> data input; disabled when analog input enabled. P2B(2) 0 — O DIG Enhanced CCP2 PWM output 2. T3CKI(1) 1 — I ST Timer3 clock input. T3G 1 — I ST Timer3 external clock gate input. T1CKI 1 — I ST Timer1 clock input. SOSCO x — O XTAL Secondary oscillator output. RC1/P2A/CCP2/SOSCI RC1 0 — O DIG LATC<1> data output; not affected by analog input. 1 — I ST PORTC<1> data input; disabled when analog input enabled. P2A 0 — O DIG Enhanced CCP2 PWM output 1. CCP2(1) 0 — O DIG Compare 2 output/PWM 2 output. 1 — I ST Capture 2 input. SOSCI x — I XTAL Secondary oscillator input. RC2/CTPLS/P1A/ RC2 0 0 O DIG LATC<2> data output; not affected by analog input. CCP1/T5CKI/AN14 1 0 I ST PORTC<2> data input; disabled when analog input enabled. CTPLS 0 0 O DIG CTMU pulse generator output. P1A 0 0 O DIG Enhanced CCP1 PWM output 1. CCP1 0 0 O DIG Compare 1 output/PWM 1 output. 1 0 I ST Capture 1 input. T5CKI 1 0 I ST Timer5 clock input. AN14 1 1 I AN Analog input 14. RC3/SCK1/SCL1/AN15 RC3 0 0 O DIG LATC<3> data output; not affected by analog input. 1 0 I ST PORTC<3> data input; disabled when analog input enabled. SCK1 0 0 O DIG MSSP1 SPI Clock output. 1 0 I ST MSSP1 SPI Clock input. SCL1 0 0 O DIG MSSP1 I2C Clock output. 1 0 I I2C MSSP1 I2C Clock input. AN15 1 1 I AN Analog input 15. RC4/SDI1/SDA1/AN16 RC4 0 0 O DIG LATC<4> data output; not affected by analog input. 1 0 I ST PORTC<4> data input; disabled when analog input enabled. SDI1 1 0 I ST MSSP1 SPI data input. SDA1 0 0 O DIG MSSP1 I2C data output. 1 0 I I2C MSSP1 I2C data input. AN16 1 1 I AN Analog input 16. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. 3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices. DS40001412G-page 138  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 10-8: PORTC I/O SUMMARY (CONTINUED) TRIS ANSEL Pin Buffer Pin Name Function Description Setting setting Type Type RC5/SDO1/AN17 RC5 0 0 O DIG LATC<5> data output; not affected by analog input. 1 0 I ST PORTC<5> data input; disabled when analog input enabled. SDO1 0 0 O DIG MSSP1 SPI data output. AN17 1 1 I AN Analog input 17. RC6/P3A/CCP3/TX1/ RC6 0 0 O DIG LATC<6> data output; not affected by analog input. CK1/AN18 1 0 I ST PORTC<6> data input; disabled when analog input enabled. P3A(2), (3) 0 0 O CMOS Enhanced CCP3 PWM output 1. CCP3(2), (3) 0 0 O DIG Compare 3 output/PWM 3 output. 1 0 I ST Capture 3 input. TX1 1 0 O DIG EUSART asynchronous transmit data output. CK1 1 0 O DIG EUSART synchronous serial clock output. 1 0 I ST EUSART synchronous serial clock input. AN18 1 1 I AN Analog input 18. RC7/P3B/RX1/DT1/ RC7 0 0 O DIG LATC<7> data output; not affected by analog input. AN19 1 0 I ST PORTC<7> data input; disabled when analog input enabled. P3B 0 0 O CMOS Enhanced CCP3 PWM output 2. RX1 1 0 I ST EUSART asynchronous receive data in. DT1 1 0 O DIG EUSART synchronous serial data output. 1 0 I ST EUSART synchronous serial data input. AN19 1 1 I AN Analog input 19. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. 3: Function on PORTD and PORTE for PIC18FXXK22 devices.  2010-2016 Microchip Technology Inc. DS40001412G-page 139

PIC18(L)F2X/4XK22 TABLE 10-9: REGISTERS ASSOCIATED WITH PORTC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ECCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 202 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 198 ECCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 202 CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 198 CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 323 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 152 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 148 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 153 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 253 T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSCEN T1SYNC T1RD16 TMR1ON 166 T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 166 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 167 T5CON TMR5CS<1:0> T5CKPS<1:0> T5SOSCEN T5SYNC T5RD16 TMR5ON 166 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC. Note 1: Available on PIC18(L)F4XK22 devices. TABLE 10-10: CONFIGURATION REGISTERS ASSOCIATED WITH PORTC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC. DS40001412G-page 140  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 10.5 PORTD Registers 10.5.1 PORTD OUTPUT PRIORITY Each PORTD pin is multiplexed with other functions. The pins, their combined functions and their output Note: PORTD is only available on 40-pin and priorities are briefly described here. For additional 44-pin devices. information, refer to the appropriate section in this data sheet. PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting When multiple outputs are enabled, the actual pin a TRISD bit (= 1) will make the corresponding PORTD control goes to the peripheral with the higher priority. pin an input (i.e., disable the output driver). Clearing a Table10-4 lists the PORTD pin functions from the TRISD bit (= 0) will make the corresponding PORTD highest to the lowest priority. pin an output (i.e., enable the output driver and put the Analog input functions, such as ADC, comparator and contents of the output latch on the selected pin). SR latch inputs, are not shown in the priority lists. The Data Latch register (LATD) is also memory These inputs are active when the I/O pin is set for mapped. Read-modify-write operations on the LATD Analog mode using the ANSELx registers. Digital register read and write the latched output value for output functions may control the pin when it is in Analog PORTD. mode with the priority shown below. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. All of the PORTD pins are multiplexed with analog and digital peripheral modules. See Table10-11. Note: On a Power-on Reset, these pins are configured as analog inputs. EXAMPLE 10-4: INITIALIZING PORTD MOVLB 0xF ; Set BSR for banked SFRs CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs MOVLW 30h ; Value used to ; enable digital inputs MOVWF ANSELD ; RD<3:0> dig input enable ; RC<7:6> dig input enable  2010-2016 Microchip Technology Inc. DS40001412G-page 141

PIC18(L)F2X/4XK22 TABLE 10-11: PORTD I/O SUMMARY TRIS ANSEL Pin Buffer Pin Name Function Description Setting setting Type Type RD0/SCK2/SCL2/AN20 RD0 0 0 O DIG LATD<0> data output; not affected by analog input. 1 0 I ST PORTD<0> data input; disabled when analog input enabled. SCK2 0 0 O DIG MSSP2 SPI Clock output. 1 0 I ST MSSP2 SPI Clock input. SCL2 0 0 O DIG MSSP2 I2C Clock output. 1 0 I I2C MSSP2 I2C Clock input. AN20 1 1 I AN Analog input 20. RD1/CCP4/SDI2/SDA2/ RD1 0 0 O DIG LATD<1> data output; not affected by analog input. AN21 1 0 I ST PORTD<1> data input; disabled when analog input enabled. CCP4 0 0 O DIG Compare 4 output/PWM 4 output. 1 0 I ST Capture 4 input. SDI2 1 0 I ST MSSP2 SPI data input. SDA2 0 0 O DIG MSSP2 I2C data output. 1 0 I I2C MSSP2 I2C data input. AN21 1 1 I AN Analog input 21. RD2/P2B/AN22 RD2 0 0 O DIG LATD<2> data output; not affected by analog input. 1 0 I ST PORTD<2> data input; disabled when analog input enabled. P2B(1) 0 0 O DIG Enhanced CCP2 PWM output 2. AN22 1 1 I AN Analog input 22. RD3/P2C/SS2/AN23 RD3 0 0 O DIG LATD<3> data output; not affected by analog input. 1 0 I ST PORTD<3> data input; disabled when analog input enabled. P2C 0 0 O DIG Enhanced CCP2 PWM output 4. SS2 1 0 I TTL MSSP2 SPI slave select input. AN23 1 1 I AN Analog input 23. RD4/P2D/SDO2/AN24 RD4 0 0 O DIG LATD<4> data output; not affected by analog input. 1 0 I ST PORTD<4> data input; disabled when analog input enabled. P2D 0 0 O DIG Enhanced CCP2 PWM output 3. SDO2 0 0 O DIG MSSP2 SPI data output. AN24 1 1 I AN Analog input 24. RD5/P1B/AN25 RD5 0 0 O DIG LATD<5> data output; not affected by analog input. 1 0 I ST PORTD<5> data input; disabled when analog input enabled. P1B 0 0 O DIG Enhanced CCP1 PWM output 2. AN25 1 1 I AN Analog input 25. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. DS40001412G-page 142  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 10-11: PORTD I/O SUMMARY (CONTINUED) TRIS ANSEL Pin Buffer Pin Name Function Description Setting setting Type Type RD6/P1C/TX2/CK2/ RD6 0 0 O DIG LATD<6> data output; not affected by analog input. AN26 1 0 I ST PORTD<6> data input; disabled when analog input enabled. P1C 0 0 O DIG Enhanced CCP1 PWM output 3. TX2 1 0 O DIG EUSART asynchronous transmit data output. CK2 1 0 O DIG EUSART synchronous serial clock output. 1 0 I ST EUSART synchronous serial clock input. AN26 1 1 I AN Analog input 26. RD7/P1D/RX2/DT2/ RD7 0 0 O DIG LATD<7> data output; not affected by analog input. AN27 1 0 I ST PORTD<7> data input; disabled when analog input enabled. P1D 0 0 O DIG Enhanced CCP1 PWM output 4. RX2 1 0 I ST EUSART asynchronous receive data in. DT2 1 0 O DIG EUSART synchronous serial data output. 1 0 I ST EUSART synchronous serial data input. AN27 1 1 I AN Analog input 27. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set.  2010-2016 Microchip Technology Inc. DS40001412G-page 143

PIC18(L)F2X/4XK22 TABLE 10-12: REGISTERS ASSOCIATED WITH PORTD Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 150 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 198 CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 198 CCP4CON — — DC4B<1:0> CCP4M<3:0> 198 LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 152 PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 148 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 SLRCON(1) — — — SLRE SLRD SLRC SLRB SLRA 153 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 253 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD. Note 1: Available on PIC18(L)F4XK22 devices. TABLE 10-13: CONFIGURATION REGISTERS ASSOCIATED WITH PORTD Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD. DS40001412G-page 144  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 10.6 PORTE Registers EXAMPLE 10-5: INITIALIZING PORTE CLRF PORTE ; Initialize PORTE by Depending on the particular PIC18(L)F2X/4XK22 ; clearing output device selected, PORTE is implemented in two ; data latches different ways. CLRF LATE ; Alternate method ; to clear output 10.6.1 PORTE ON 40/44-PIN DEVICES ; data latches For PIC18(L)F2X/4XK22 devices, PORTE is a 4-bit CLRF ANSELE ; Configure analog pins ; for digital only wide port. Three pins (RE0/P3A/CCP3/AN5, RE1/P3B/ MOVLW 05h ; Value used to AN6 and RE2/CCP5/AN7) are individually configurable ; initialize data as inputs or outputs. These pins have Schmitt Trigger ; direction input buffers. When selected as an analog input, these MOVWF TRISE ; Set RE<0> as input pins will read as ‘0’s. ; RE<1> as output The corresponding data direction register is TRISE. ; RE<2> as input Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., disable the output driver). 10.6.2 PORTE ON 28-PIN DEVICES Clearing a TRISE bit (= 0) will make the corresponding For PIC18F2XK22 devices, PORTE is only available PORTE pin an output (i.e., enable the output driver and when Master Clear functionality is disabled put the contents of the output latch on the selected pin). (MCLR=0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates TRISE controls the direction of the REx pins, even as previously described. when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs 10.6.3 RE3 WEAK PULL-UP when using them as analog inputs. The port RE3 pin has an individually controlled weak The Data Latch register (LATE) is also memory internal pull-up. When set, the WPUE3 (TRISE<7>) bit mapped. Read-modify-write operations on the LATE enables the RE3 pin pull-up. The RBPU bit of the INT- register read and write the latched output value for CON2 register controls pull-ups on both PORTB and PORTE. PORTE. When RBPU = 0, the weak pull-ups become active on all pins which have the WPUE3 or WPUBx bits set. When set, the RBPU bit disables all weak pull- Note: On a Power-on Reset, RE<2:0> are ups. The pull-ups are disabled on a Power-on Reset. configured as analog inputs. When the RE3 port pin is configured as MCLR, (CON- The fourth pin of PORTE (MCLR/VPP/RE3) is an input FIG3H<7>, MCLRE=1 and CONFIG4L<2>, LVP=0), or only pin. Its operation is controlled by the MCLRE configured for Low Voltage Programming, (MCLRE=x Configuration bit. When selected as a port pin and LVP=1), the pull-up is always enabled and the (MCLRE=0), it functions as a digital input only pin; as WPUE3 bit has no effect. such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device’s Master 10.6.4 PORTE OUTPUT PRIORITY Clear input. In either configuration, RE3 also functions as Each PORTE pin is multiplexed with other functions. the programming voltage input during programming. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data Note: On a Power-on Reset, RE3 is enabled as sheet. a digital input only if Master Clear When multiple outputs are enabled, the actual pin functionality is disabled. control goes to the peripheral with the higher priority. Table10-4 lists the PORTE pin functions from the highest to the lowest priority. Analog input functions, such as ADC, comparator and SR latch inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below.  2010-2016 Microchip Technology Inc. DS40001412G-page 145

PIC18(L)F2X/4XK22 TABLE 10-14: PORTE I/O SUMMARY TRIS ANSEL Pin Buffer Pin Function Description Setting Setting Type Type RE0/P3A/CCP3/AN5 RE0 0 0 O DIG LATE<0> data output; not affected by analog input. 1 0 I ST PORTE<0> data input; disabled when analog input enabled. P3A(1) 0 0 O DIG Enhanced CCP3 PWM output. CCP3(1) 0 0 O DIG Compare 3 output/PWM 3 output. 1 0 I ST Capture 3 input. AN5 1 1 I AN Analog input 5. RE1/P3B/AN6 RE1 0 0 O DIG LATE<1> data output; not affected by analog input. 1 0 I ST PORTE<1> data input; disabled when analog input enabled. P3B 0 0 O DIG Enhanced CCP3 PWM output. AN6 1 1 I AN Analog input 6. RE2/CCP5/AN7 RE2 0 0 O DIG LATE<2> data output; not affected by analog input. 1 0 I ST PORTE<2> data input; disabled when analog input enabled. CCP5 0 0 O DIG Compare 5 output/PWM 5 output. 1 0 I ST Capture 5 input. AN7 1 1 I AN Analog input 7. RE3/VPP/MCLR RE3 — — I ST PORTE<3> data input; enabled when Configuration bit MCLRE = 0. VPP — — P AN Programming voltage input; always available MCLR — — I ST Active-low Master Clear (device Reset) input; enabled when configuration bit MCLRE = 1. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Note 1: Alternate pin assignment for P3A/CCP3 when Configuration bit CCP3MX is clear. DS40001412G-page 146  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 10-15: REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 151 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 110 LATE(1) — — — — — LATE2 LATE1 LATE0 152 PORTE — — — — RE3 RE2(1) RE1(1) RE0(1) 149 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 153 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 151 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTE. Note 1: Available on PIC18(L)F4XK22 devices. TABLE 10-16: CONFIGURATION REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 CONFIG4L DEBUG XINST — — — LVP(1) — STRVEN 349 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts. Note 1: Can only be changed when in high voltage programming mode.  2010-2016 Microchip Technology Inc. DS40001412G-page 147

PIC18(L)F2X/4XK22 10.7 Port Analog Control 10.8 Port Slew Rate Control Most port pins are multiplexed with analog functions The output slew rate of each port is programmable to such as the Analog-to-Digital Converter and select either the standard transition rate or a reduced comparators. When these I/O pins are to be used as transition rate of approximately 0.1 times the standard analog inputs it is necessary to disable the digital input to minimize EMI. The reduced transition time is the buffer to avoid excessive current caused by improper default slew rate for all ports. biasing of the digital input. Individual control of the digital input buffers on pins which share analog functions is provided by the ANSELA, ANSELB, ANSELC, ANSELD and ANSELE registers. Setting an ANSx bit high will disable the associated digital input buffer and cause all reads of that pin to return ‘0’ while allowing analog functions of that pin to operate correctly. The state of the ANSx bits has no affect on digital output functions. A pin with the associated TRISx bit clear and ANSx bit set will still operate as a digital output but the input mode will be analog. This can cause unexpected behavior when performing read- modify-write operations on the affected port. All ANSEL register bits default to ‘1’ upon POR and BOR, disabling digital inputs for their associated port pins. All TRIS register bits default to ‘1’ upon POR or BOR, disabling digital outputs for their associated port pins. As a result, all port pins that have an ANSEL register will default to analog inputs upon POR or BOR. 10.9 Register Definitions – Port Control REGISTER 10-1: PORTX(1): PORTx REGISTER R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 Rx<7:0>: PORTx I/O bit values(2) Note 1: Register Description for PORTA, PORTB, PORTC and PORTD. 2: Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O pin values. DS40001412G-page 148  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 10-2: PORTE: PORTE REGISTER U-0 U-0 U-0 U-0 R/W-u/x R/W-u/x R/W-u/x R/W-u/x — — — — RE3(1) RE2(2), (3) RE1(2), (3) RE0(2), (3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 Unimplemented: Read as ‘0’ bit 3 RE3: PORTE Input bit value(1) bit 2-0 RE<2:0>: PORTE I/O bit values(2), (3) Note 1: Port is available as input only when MCLRE = 0. 2: Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O pin values. 3: Available on PIC18(L)F4XK22 devices. REGISTER 10-3: ANSELA – PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 ANSA5: RA5 Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled bit 4 Unimplemented: Read as ‘0’ bit 3-0 ANSA<3:0>: RA<3:0> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled  2010-2016 Microchip Technology Inc. DS40001412G-page 149

PIC18(L)F2X/4XK22 REGISTER 10-4: ANSELB – PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: RB<5:0> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled REGISTER 10-5: ANSELC – PORTC ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 ANSC<7:2>: RC<7:2> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled bit 1-0 Unimplemented: Read as ‘0’ REGISTER 10-6: ANSELD – PORTD ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ANSD<7:0>: RD<7:0> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled DS40001412G-page 150  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 10-7: ANSELE – PORTE ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 — — — — — ANSE2(1) ANSE1(1) ANSE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSE<2:0>: RE<2:0> Analog Select bit(1) 1 = Digital input buffer disabled 0 = Digital input buffer enabled Note 1: Available on PIC18(L)F4XK22 devices only. REGISTER 10-8: TRISx: PORTx TRI-STATE REGISTER(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISx7 TRISx6 TRISx5 TRISx4 TRISx3 TRISx2 TRISx1 TRISx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TRISx<7:0>: PORTx Tri-State Control bit 1 = PORTx pin configured as an input (tri-stated) 0 = PORTx pin configured as an output Note 1: Register description for TRISA, TRISB, TRISC and TRISD. REGISTER 10-9: TRISE: PORTE TRI-STATE REGISTER R/W-1 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WPUE3: Weak Pull-up Register bits 1 = Pull-up enabled on PORT pin 0 = Pull-up disabled on PORT pin bit 6-3 Unimplemented: Read as ‘0’ bit 2-0 TRISE<7:0>: PORTE Tri-State Control bit(1) 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output Note 1: Available on PIC18(L)F4XK22 devices only.  2010-2016 Microchip Technology Inc. DS40001412G-page 151

PIC18(L)F2X/4XK22 REGISTER 10-10: LATx: PORTx OUTPUT LATCH REGISTER(1) R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATx7 LATx6 LATx5 LATx4 LATx3 LATx2 LATx1 LATx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 LATx<7:0>: PORTx Output Latch bit value(2) Note 1: Register Description for LATA, LATB, LATC and LATD. 2: Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O pin values. REGISTER 10-11: LATE: PORTE OUTPUT LATCH REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u — — — — — LATE2 LATE1 LATE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LATE<2:0>: PORTE Output Latch bit value(2) Note 1: Available on PIC18(L)F4XK22 devices only. 2: Writes to PORTE are written to corresponding LATE register. Reads from PORTE register is return of I/O pin values. REGISTER 10-12: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled on PORT pin 0 = Pull-up disabled on PORT pin DS40001412G-page 152  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 10-13: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 IOCB7 IOCB6 IOCB5 IOCB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTB control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled Note 1: Interrupt-on-change requires that the RBIE bit (INTCON<3>) is set. REGISTER 10-14: SLRCON: SLEW RATE CONTROL REGISTER U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SLRE(1) SLRD(1) SLRC SLRB SLRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 SLRE: PORTE Slew Rate Control bit(1) 1 = All outputs on PORTE slew at a limited rate 0 = All outputs on PORTE slew at the standard rate bit 3 SLRD: PORTD Slew Rate Control bit(1) 1 = All outputs on PORTD slew at a limited rate 0 = All outputs on PORTD slew at the standard rate bit 2 SLRC: PORTC Slew Rate Control bit 1 = All outputs on PORTC slew at a limited rate 0 = All outputs on PORTC slew at the standard rate bit 1 SLRB: PORTB Slew Rate Control bit 1 = All outputs on PORTB slew at a limited rate 0 = All outputs on PORTB slew at the standard rate bit 0 SLRA: PORTA Slew Rate Control bit 1 = All outputs on PORTA slew at a limited rate(2) 0 = All outputs on PORTA slew at the standard rate Note 1: These bits are available on PIC18(L)F4XK22 devices. 2: The slew rate of RA6 defaults to standard rate when the pin is used as CLKOUT.  2010-2016 Microchip Technology Inc. DS40001412G-page 153

PIC18(L)F2X/4XK22 11.0 TIMER0 MODULE The T0CON register (Register11-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or A simplified block diagram of the Timer0 module in 8-bit counter in both 8-bit or 16-bit modes mode is shown in Figure11-1. Figure11-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow 11.1 Register Definitions: Timer0 Control REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA TOPS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value DS40001412G-page 154  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 11.2 Timer0 Operation 11.3 Timer0 Reads and Writes in 16-Bit Mode Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit of the T0CON TMR0H is not the actual high byte of Timer0 in 16-bit register. In Timer mode (T0CS = 0), the module mode; it is actually a buffered version of the real high increments on every clock by default unless a different byte of Timer0 which is neither directly readable nor prescaler value is selected (see Section11.4 writable (refer to Figure11-2). TMR0H is updated with “Prescaler”). Timer0 incrementing is inhibited for two the contents of the high byte of Timer0 during a read of instruction cycles following a TMR0 register write. The TMR0L. This provides the ability to read all 16 bits of user can work around this by adjusting the value written Timer0 without the need to verify that the read of the to the TMR0 register to compensate for the anticipated high and low byte were valid. Invalid reads could missing increments. otherwise occur due to a rollover between successive The Counter mode is selected by setting the T0CS bit reads of the high and low byte. (= 1). In this mode, Timer0 increments either on every Similarly, a write to the high byte of Timer0 must also rising or falling edge of pin RA4/T0CKI. The increment- take place through the TMR0H Buffer register. Writing ing edge is determined by the Timer0 Source Edge to TMR0H does not directly affect Timer0. Instead, the Select bit, T0SE of the T0CON register; clearing this bit high byte of Timer0 is updated with the contents of selects the rising edge. Restrictions on the external TMR0H when a write occurs to TMR0L. This allows all clock input are discussed below. 16 bits of Timer0 to be updated at once. An external clock source can be used to drive Timer0; however, it must meet certain requirements (see Table27-12) to ensure that the external clock can be synchronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) 8 T0CS 3 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.  2010-2016 Microchip Technology Inc. DS40001412G-page 155

PIC18(L)F2X/4XK22 FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 1 SIynntecr nwaitlh TMR0L HTigMh RB0yte STMetR 0IF T0CKI pin ProPgrreasmcamlearble 0 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 11.4 Prescaler 11.4.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software its value is set by the PSA and T0PS<2:0> bits of the control and can be changed “on-the-fly” during program T0CON register which determine the prescaler execution. assignment and prescale ratio. 11.5 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When the prescaler is assigned, The TMR0 interrupt is generated when the TMR0 reg- prescale values from 1:2 through 1:256 in integer ister overflows from FFh to 00h in 8-bit mode, or from power-of-2 increments are selectable. FFFFh to 0000h in 16-bit mode. This overflow sets the When assigned to the Timer0 module, all instructions TMR0IF flag bit. The interrupt can be masked by clear- writing to the TMR0 register (e.g., CLRF TMR0, MOVWF ing the TMR0IE bit of the INTCON register. Before TMR0, BSF TMR0, etc.) clear the prescaler count. re-enabling the interrupt, the TMR0IF bit must be cleared by software in the Interrupt Service Routine. Since Timer0 is shut down in Sleep mode, the TMR0 Note: Writing to TMR0 when the prescaler is interrupt cannot awaken the processor from Sleep. assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 110 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS<2:0> 154 TMR0H Timer0 Register, High Byte — TMR0L Timer0 Register, Low Byte — TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Timer0. DS40001412G-page 156  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 12.0 TIMER1/3/5 MODULE WITH • Special Event Trigger (with CCP/ECCP) GATE CONTROL • Selectable Gate Source Polarity • Gate Toggle mode The Timer1/3/5 module is a 16-bit timer/counter with • Gate Single-pulse mode the following features: • Gate Value Status • 16-bit timer/counter register pair (TMRxH:TMRxL) • Gate Event Interrupt • Programmable internal or external clock source Figure12-1 is a block diagram of the Timer1/3/5 • 2-bit prescaler module. • Dedicated Secondary 32 kHz oscillator circuit • Optionally synchronized comparator out • Multiple Timer1/3/5 gate (count enable) sources • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • 16-Bit Read/Write Operation • Time base for the Capture/Compare function FIGURE 12-1: TIMER1/3/5 BLOCK DIAGRAM TxGSS<1:0> TxG 00 TxGSPM TimPRer22//44//66 Match 01 TxG_IN 0 0 TxGVAL D Q Data Bus sync_C1OUT(7) 10 SAicnqg.l eC Ponutlrsoel 1 Q1 EN TXGRCDON D Q 1 sync_C2OUT(7) 11 CK Q TxGGO/DONE Interrupt Set TMRxON R det TMRxGIF TxGPOL TxGTM TMRxGE Set flag bit TMRxON TMRxIF on To Comparator Module Overflow TMRx(2),(4) EN Synchronized TMRxH TMRxL TxCLK 0 clock input Q D 1 Secondary TMRxCS<1:0> TxSYNC Oscillator SOSCOUT Module See Figure 2-4 Reserved 11 Prescaler Synchronize(3),(7) 1 1, 2, 4, 8 TxCLK_EXT_SRC det (5),(6) (1) 10 2 TxCKI 0 FOSC TxCKPS<1:0> Internal 01 TxSOSCEN Clock IFnOteSrCn/a2l Sleep input FOSC/4 Clock Internal 00 Clock Note 1: ST Buffer is high speed type when using TxCKI. 2: Timer1/3/5 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 4: See Figure12-2 for 16-Bit Read/Write Mode Block Diagram. 5: T1CKI is not available when the secondary oscillator is enabled. (SOSCGO = 1 or TXSOSCEN = 1) 6: T3CKI is not available when the secondary oscillator is enabled, unless T3CMX = 1. 7: Synchronized comparator output should not be used in conjunction with synchronized TxCKI.  2010-2016 Microchip Technology Inc. DS40001412G-page 157

PIC18(L)F2X/4XK22 12.1 Timer1/3/5 Operation 12.2.1 INTERNAL CLOCK SOURCE The Timer1/3/5 module is a 16-bit incrementing When the internal clock source is selected the counter which is accessed through the TMRxH:TMRxL TMRxH:TMRxL register pair will increment on multiples register pair. Writes to TMRxH or TMRxL directly of FOSC as determined by the Timer1/3/5 prescaler. update the counter. When the FOSC internal clock source is selected, the Timer1/3/5 register value will increment by four counts When used with an internal clock source, the module is every instruction clock cycle. Due to this condition, a a timer and increments on every instruction cycle. 2LSB error in resolution will occur when reading the When used with an external clock source, the module Timer1/3/5 value. To utilize the full resolution of can be used as either a timer or counter and Timer1/3/5, an asynchronous input signal must be used increments on every selected edge of the external to gate the Timer1/3/5 clock input. source. The following asynchronous sources may be used: Timer1/3/5 is enabled by configuring the TMRxON and TMRxGE bits in the TxCON and TxGCON registers, • Asynchronous event on the TxG pin to Timer1/3/5 respectively. Table12-1 displays the Timer1/3/5 enable Gate selections. • C1 or C2 comparator input to Timer1/3/5 Gate 12.2.2 EXTERNAL CLOCK SOURCE TABLE 12-1: TIMER1/3/5 ENABLE SELECTIONS When the external clock source is selected, the Tim- er1/3/5 module may work as a timer or a counter. Timer1/3/5 TMRxON TMRxGE Operation When enabled to count, Timer1/3/5 is incremented on the rising edge of the external clock input of the TxCKI 0 0 Off pin. This external clock source can be synchronized to 0 1 Off the microcontroller system clock or it can run 1 0 Always On asynchronously. 1 1 Count Enabled When used as a timer with a clock oscillator, an external 32.768kHz crystal can be used in conjunction with the dedicated secondary internal oscillator circuit. 12.2 Clock Source Selection The TMRxCS<1:0> and TxSOSCEN bits of the TxCON register are used to select the clock source for Note: In Counter mode, a falling edge must be Timer1/3/5. The dedicated Secondary Oscillator circuit registered by the counter prior to the first can be used as the clock source for Timer1, Timer3 and incrementing rising edge after any one or Timer5, simultaneously. Any of the TxSOSCEN bits will more of the following conditions: enable the Secondary Oscillator circuit and select it as • Timer1/3/5 enabled after POR the clock source for that particular timer. Table12-2 • Write to TMRxH or TMRxL displays the clock source selections. • Timer1/3/5 is disabled • Timer1/3/5 is disabled (TMRxON = 0) when TxCKI is high then Timer1/3/5 is enabled (TMRxON=1) when TxCKI is low. TABLE 12-2: CLOCK SOURCE SELECTIONS TMRxCS1 TMRxCS0 TxSOSCEN Clock Source 0 1 x System Clock (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 0 0 External Clocking on TxCKI Pin 1 0 1 Osc.Circuit On SOSCI/SOSCO Pins DS40001412G-page 158  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 12.3 Timer1/3/5 Prescaler 12.5.1 READING AND WRITING TIMER1/3/5 IN ASYNCHRONOUS Timer1/3/5 has four prescaler options allowing 1, 2, 4 or COUNTER MODE 8 divisions of the clock input. The TxCKPS bits of the TxCON register control the prescale counter. The Reading TMRxH or TMRxL while the timer is running prescale counter is not directly readable or writable; from an external asynchronous clock will ensure a valid however, the prescaler counter is cleared upon a write to read (taken care of in hardware). However, the user TMRxH or TMRxL. should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the 12.4 Secondary Oscillator timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and A dedicated secondary low-power 32.768kHz write the desired values. A write contention may occur oscillator circuit is built-in between pins SOSCI (input) by writing to the timer registers, while the register is and SOSCO (amplifier output). This internal circuit is to incrementing. This may produce an unpredictable be used in conjunction with an external 32.768kHz value in the TMRxH:TMRxL register pair. crystal. The oscillator circuit is enabled by setting the 12.6 Timer1/3/5 16-Bit Read/Write Mode TxSOSCEN bit of the TxCON register, the SOSCGO bit Timer1/3/5 can be configured to read and write all 16 of the OSCCON2 register or by selecting the bits of data, to and from, the 8-bit TMRxL and TMRxH secondary oscillator as the system clock by setting registers, simultaneously. The 16-bit read and write SCS<1:0> = 01 in the OSCCON register. The oscillator operations are enabled by setting the RD16 bit of the will continue to run during Sleep. TxCON register. To accomplish this function, the TMRxH register value Note: The oscillator requires a start-up and is mapped to a buffer register called the TMRxH buffer stabilization time before use. Thus, register. While in 16-Bit mode, the TMRxH register is TxSOSCEN should be set and a suitable not directly readable or writable and all read and write delay observed prior to enabling operations take place through the use of this TMRxH Timer1/3/5. buffer register. When a read from the TMRxL register is requested, the 12.5 Timer1/3/5 Operation in value of the TMRxH register is simultaneously loaded Asynchronous Counter Mode into the TMRxH buffer register. When a read from the TMRxH register is requested, the value is provided If control bit TxSYNC of the TxCON register is set, the from the TMRxH buffer register instead. This provides external clock input is not synchronized. The timer the user with the ability to accurately read all 16 bits of increments asynchronously to the internal phase the Timer1/3/5 value from a single instance in time. clocks. If external clock source is selected then the In contrast, when not in 16-Bit mode, the user must timer will continue to run during Sleep and can read each register separately and determine if the generate an interrupt on overflow, which will wake-up values have become invalid due to a rollover that may the processor. However, special precautions in have occurred between the read operations. software are needed to read/write the timer (see Section12.5.1 “Reading and Writing Timer1/3/5 in When a write request of the TMRxL register is Asynchronous Counter Mode”). requested, the TMRxH buffer register is simultaneously updated with the contents of the TMRxH register. The value of TMRxH must be preloaded into the TMRxH buffer register prior to the write request for the TMRxL Note: When switching from synchronous to register. This provides the user with the ability to write asynchronous operation, it is possible to all 16 bits to the TMRxL:TMRxH register pair at the skip an increment. When switching from same time. asynchronous to synchronous operation, it is possible to produce an additional Any requests to write to the TMRxH directly does not increment. clear the Timer1/3/5 prescaler value. The prescaler value is only cleared through write requests to the TMRxL register.  2010-2016 Microchip Technology Inc. DS40001412G-page 159

PIC18(L)F2X/4XK22 FIGURE 12-2: TIMER1/3/5 16-BIT 12.7.2 TIMER1/3/5 GATE SOURCE READ/WRITE MODE SELECTION BLOCK DIAGRAM The Timer1/3/5 Gate source can be selected from one of four different sources. Source selection is controlled From by the TxGSS bits of the TxGCON register. The polarity Timer1 Circuitry for each available source is also selectable. Polarity TMR1 Set selection is controlled by the TxGPOL bit of the TMR1L High Byte TMR1IF TxGCON register. on Overflow 8 TABLE 12-4: TIMER1/3/5 GATE SOURCES Read TMR1L Write TMR1L TxGSS Timer1/3/5 Gate Source 8 8 00 Timer1/3/5 Gate Pin TMR1H 01 Timer2/4/6 Match to PR2/4/6 (TMR2/4/6 increments to match PR2/4/6) 8 8 10 Comparator 1 Output sync_C1OUT Internal Data Bus (optionally Timer1/3/5 synchronized out- put) Block Diagram of Timer1 Example of TIMER1/3/5 11 Comparator 2 Output sync_C2OUT (optionally Timer1/3/5 synchronized out- 12.7 Timer1/3/5 Gate put) The Gate resource, Timer2 Match to PR2, changes Timer1/3/5 can be configured to count freely or the between Timer2, Timer4 and Timer6 depending on count can be enabled and disabled using Timer1/3/5 which of the three 16-bit Timers, Timer1, Timer3 or Gate circuitry. This is also referred to as Timer1/3/5 Timer5, is selected. See Table12-5 to determine which Gate Enable. Timer2/4/6 Match to PR2/4/6 combination is available Timer1/3/5 Gate can also be driven by multiple for the 16-bit timer being used. selectable sources. 12.7.1 TIMER1/3/5 GATE ENABLE TABLE 12-5: GATE RESOURCES FOR TIMER2/4/6 MATCH TO The Timer1/3/5 Gate Enable mode is enabled by PR2/4/6 setting the TMRxGE bit of the TxGCON register. The polarity of the Timer1/3/5 Gate Enable mode is Timer1/3/5 Gate Match Timer1/3/5 Resource configured using the TxGPOL bit of the TxGCON Selection register. Timer1 TMR2 Match to PR2 When Timer1/3/5 Gate Enable mode is enabled, Timer3 TMR4 Match to PR4 Timer1/3/5 will increment on the rising edge of the Timer1/3/5 clock source. When Timer1/3/5 Gate Timer5 TMR6 Match to PR6 Enable mode is disabled, no incrementing will occur 12.7.2.1 TxG Pin Gate Operation and Timer1/3/5 will hold the current count. See Figure12-4 for timing details. The TxG pin is one source for Timer1/3/5 Gate Control. It can be used to supply an external source to the Tim- er1/3/5 Gate circuitry. TABLE 12-3: TIMER1/3/5 GATE ENABLE SELECTIONS 12.7.2.2 Timer2/4/6 Match Gate Operation TxCLK TxGPOL TxG Timer1/3/5 The TMR2/4/6 register will increment until it matches Operation the value in the PR2/4/6 register. On the very next  0 0 Counts increment cycle, TMR2/4/6 will be reset to 00h. When this Reset occurs, a low-to-high pulse will automatically  0 1 Holds Count be generated and internally supplied to the Timer1/3/5  1 0 Holds Count Gate circuitry. When both TMR2/4/6 and Timer 1/3/5  1 1 Counts use FOSC/4 as the clock source then Timer 1/3/5 will increment once during the TMR2/4/6 overflow pulse. This concatenation creates a 24-bit timer. When used in conjunction with the CCP special event trigger very long periodic interrupts can be generated. DS40001412G-page 160  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 12.7.2.3 Comparator C1 Gate Operation 12.7.4 TIMER1/3/5 GATE SINGLE-PULSE MODE The output resulting from a Comparator 1 operation can be selected as a source for Timer1/3/5 Gate Control. When Timer1/3/5 Gate Single-Pulse mode is enabled, The Comparator 1 output (sync_C1OUT) can be it is possible to capture a single-pulse gate event. synchronized to the Timer1/3/5 clock or left Timer1/3/5 Gate Single-Pulse mode is first enabled by asynchronous. For more information see Section18.8.4 setting the TxGSPM bit in the TxGCON register. Next, “Synchronizing Comparator Output to Timer1”. the TxGGO/DONE bit in the TxGCON register must be set. The Timer1/3/5 will be fully enabled on the next 12.7.2.4 Comparator C2 Gate Operation incrementing edge. On the next trailing edge of the The output resulting from a Comparator 2 operation pulse, the TxGGO/DONE bit will automatically be can be selected as a source for Timer1/3/5 Gate cleared. No other gate events will be allowed to Control. The Comparator 2 output (sync_C2OUT) can increment Timer1/3/5 until the TxGGO/DONE bit is be synchronized to the Timer1/3/5 clock or left once again set in software. asynchronous. For more information see Clearing the TxGSPM bit of the TxGCON register will Section18.8.4 “Synchronizing Comparator Output also clear the TxGGO/DONE bit. See Figure12-6 for to Timer1”. timing details. 12.7.3 TIMER1/3/5 GATE TOGGLE MODE Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work When Timer1/3/5 Gate Toggle mode is enabled, it is together. This allows the cycle times on the Timer1/3/5 possible to measure the full-cycle length of a Tim- Gate source to be measured. See Figure12-7 for er1/3/5 gate signal, as opposed to the duration of a sin- timing details. gle level pulse. 12.7.5 TIMER1/3/5 GATE VALUE STATUS The Timer1/3/5 Gate source is routed through a flip-flop that changes state on every incrementing edge of the When Timer1/3/5 Gate Value Status is utilized, it is signal. See Figure12-5 for timing details. possible to read the most current level of the gate Timer1/3/5 Gate Toggle mode is enabled by setting the control value. The value is stored in the TxGVAL bit in TxGTM bit of the TxGCON register. When the TxGTM the TxGCON register. The TxGVAL bit is valid even bit is cleared, the flip-flop is cleared and held clear. This when the Timer1/3/5 Gate is not enabled (TMRxGE bit is necessary in order to control which edge is is cleared). measured. 12.7.6 TIMER1/3/5 GATE EVENT INTERRUPT Note: Enabling Toggle mode at the same time When Timer1/3/5 Gate Event Interrupt is enabled, it is as changing the gate polarity may result in possible to generate an interrupt upon the completion indeterminate operation. of a gate event. When the falling edge of TxGVAL occurs, the TMRxGIF flag bit in the PIR3 register will be set. If the TMRxGIE bit in the PIE3 register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Timer1/3/5 Gate is not enabled (TMRxGE bit is cleared). For more information on selecting high or low priority status for the Timer1/3/5 Gate Event Interrupt see Section9.0 “Interrupts”.  2010-2016 Microchip Technology Inc. DS40001412G-page 161

PIC18(L)F2X/4XK22 12.8 Timer1/3/5 Interrupt 12.10 ECCP/CCP Capture/Compare Time Base The Timer1/3/5 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When The CCP modules use the TMRxH:TMRxL register pair Timer1/3/5 rolls over, the Timer1/3/5 interrupt flag bit of as the time base when operating in Capture or the PIR1/2/5 register is set. To enable the interrupt on Compare mode. rollover, you must set these bits: In Capture mode, the value in the TMRxH:TMRxL • TMRxON bit of the TxCON register register pair is copied into the CCPRxH:CCPRxL • TMRxIE bits of the PIE1, PIE2 or PIE5 registers register pair on a configured event. • PEIE/GIEL bit of the INTCON register In Compare mode, an event is triggered when the value • GIE/GIEH bit of the INTCON register CCPRxH:CCPRxL register pair matches the value in the TMRxH:TMRxL register pair. This event can be a The interrupt is cleared by clearing the TMRxIF bit in Special Event Trigger. the Interrupt Service Routine. For more information, see Section14.0 For more information on selecting high or low priority “Capture/Compare/PWM Modules”. status for the Timer1/3/5 Overflow Interrupt, see Section9.0 “Interrupts”. 12.11 ECCP/CCP Special Event Trigger When any of the CCP’s are configured to trigger a Note: The TMRxH:TMRxL register pair and the special event, the trigger will clear the TMRxH:TMRxL TMRxIF bit should be cleared before register pair. This special event does not cause a enabling interrupts. Timer1/3/5 interrupt. The CCP module may still be configured to generate a CCP interrupt. 12.9 Timer1/3/5 Operation During Sleep In this mode of operation, the CCPRxH:CCPRxL register pair becomes the period register for Timer1/3/5 can only operate during Sleep when set up Timer1/3/5. in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to Timer1/3/5 should be synchronized and FOSC/4 should increment the counter. To set up the timer to wake the be selected as the clock source in order to utilize the device: Special Event Trigger. Asynchronous operation of Timer1/3/5 can cause a Special Event Trigger to be • TMRxON bit of the TxCON register must be set missed. • TMRxIE bit of the PIE1/2/5 register must be set In the event that a write to TMRxH or TMRxL coincides • PEIE/GIEL bit of the INTCON register must be set with a Special Event Trigger from the CCP, the write will • TxSYNC bit of the TxCON register must be set take precedence. • TMRxCS bits of the TxCON register must be For more information, see Section17.2.8 “Special configured Event Trigger”. • TxSOSCEN bit of the TxCON register must be configured The device will wake-up on an overflow and execute the next instruction. If the GIE/GIEH bit of the INTCON register is set, the device will call the Interrupt Service Routine. The secondary oscillator will continue to operate in Sleep regardless of the TxSYNC bit setting. DS40001412G-page 162  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 12-3: TIMER1/3/5 INCREMENTING EDGE TXCKI = 1 when TMRx Enabled TXCKI = 0 when TMRX Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. FIGURE 12-4: TIMER1/3/5 GATE ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3/5 N N + 1 N + 2 N + 3 N + 4  2010-2016 Microchip Technology Inc. DS40001412G-page 163

PIC18(L)F2X/4XK22 FIGURE 12-5: TIMER1/3/5 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxTxG_IN TxCKI TxGVAL TIMER1/3/5 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 FIGURE 12-6: TIMER1/3/5 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM Cleared by hardware on TxGGO/ Set by software falling edge of TxGVAL DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5 N N + 1 N + 2 Cleared by TMRxGIF Cleared by software Set by hardware on software falling edge of TxGVAL DS40001412G-page 164  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 12-7: TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM Cleared by hardware on TxGGO/ Set by software falling edge of TxGVAL DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5 N N + 1 N + 2 N + 3 N + 4 Set by hardware on Cleared by TMRxGIF Cleared by software falling edge of TxGVAL software 12.12 Peripheral Module Disable When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power con- sumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bits for Timer1 (TMR1MD), Timer3 (TMR3MD) and Timer5 (TMR5MD) are in the PMD0 Register. See Section3.0 “Power-Managed Modes” for more information.  2010-2016 Microchip Technology Inc. DS40001412G-page 165

PIC18(L)F2X/4XK22 12.13 Register Definitions: Timer1/3/5 Control REGISTER 12-1: TXCON: TIMER1/3/5 CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/0 R/W-0/u TMRxCS<1:0> TxCKPS<1:0> TxSOSCEN TxSYNC TxRD16 TMRxON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMRxCS<1:0>: Timer1/3/5 Clock Source Select bits 11 =Reserved. Do not use. 10 =Timer1/3/5 clock source is pin or oscillator: If TxSOSCEN = 0: External clock from TxCKI pin (on the rising edge) If TxSOSCEN = 1: Crystal oscillator on SOSCI/SOSCO pins 01 =Timer1/3/5 clock source is system clock (FOSC) 00 =Timer1/3/5 clock source is instruction clock (FOSC/4) bit 5-4 TxCKPS<1:0>: Timer1/3/5 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 TxSOSCEN: Secondary Oscillator Enable Control bit 1 = Dedicated Secondary oscillator circuit enabled 0 = Dedicated Secondary oscillator circuit disabled bit 2 TxSYNC: Timer1/3/5 External Clock Input Synchronization Control bit TMRxCS<1:0> = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMRxCS<1:0> = 0X This bit is ignored. Timer1/3/5 uses the internal clock when TMRxCS<1:0> = 1X. bit 1 TxRD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1/3/5 in one 16-bit operation 0 = Enables register read/write of Timer1/3/5 in two 8-bit operation bit 0 TMRxON: Timer1/3/5 On bit 1 = Enables Timer1/3/5 0 = Stops Timer1/3/5 Clears Timer1/3/5 Gate flip-flop DS40001412G-page 166  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 12-2: TXGCON: TIMER1/3/5 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u TMRxGE TxGPOL TxGTM TxGSPM TxGGO/DONE TxGVAL TxGSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMRxGE: Timer1/3/5 Gate Enable bit If TMRxON = 0: This bit is ignored If TMRxON = 1: 1 = Timer1/3/5 counting is controlled by the Timer1/3/5 gate function 0 = Timer1/3/5 counts regardless of Timer1/3/5 gate function bit 6 TxGPOL: Timer1/3/5 Gate Polarity bit 1 = Timer1/3/5 gate is active-high (Timer1/3/5 counts when gate is high) 0 = Timer1/3/5 gate is active-low (Timer1/3/5 counts when gate is low) bit 5 TxGTM: Timer1/3/5 Gate Toggle Mode bit 1 = Timer1/3/5 Gate Toggle mode is enabled 0 = Timer1/3/5 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1/3/5 gate flip-flop toggles on every rising edge. bit 4 TxGSPM: Timer1/3/5 Gate Single-Pulse Mode bit 1 = Timer1/3/5 gate Single-Pulse mode is enabled and is controlling Timer1/3/5 gate 0 = Timer1/3/5 gate Single-Pulse mode is disabled bit 3 TxGGO/DONE: Timer1/3/5 Gate Single-Pulse Acquisition Status bit 1 = Timer1/3/5 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1/3/5 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when TxGSPM is cleared. bit 2 TxGVAL: Timer1/3/5 Gate Current State bit Indicates the current state of the Timer1/3/5 gate that could be provided to TMRxH:TMRxL. Unaffected by Timer1/3/5 Gate Enable (TMRxGE). bit 1-0 TxGSS<1:0>: Timer1/3/5 Gate Source Select bits 00 = Timer1/3/5 Gate pin 01 = Timer2/4/6 Match PR2/4/6 output (See Table12-5 for proper timer match selection) 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 11 = Comparator 2 optionally synchronized output (sync_C2OUT)  2010-2016 Microchip Technology Inc. DS40001412G-page 167

PIC18(L)F2X/4XK22 TABLE 12-6: REGISTERS ASSOCIATED WITH TIMER1/3/5 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 IPR5 — — — — — TMR6IP TMR5IP TMR4IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIE5 — — — — — TMR6IE TMR5IE TMR4IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PIR5 — — — — — TMR6IF TMR5IF TMR4IF 116 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSCEN T1SYNC T1RD16 TMR1ON 166 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 167 T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 166 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 167 T5CON TMR5CS<1:0> T5CKPS<1:0> T5SOSCEN T5SYNC T5RD16 TMR5ON 166 T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL T5GSS<1:0> 167 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — TMR1L Least Significant Byte of the 16-bit TMR1 Register — TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register — TMR3L Least Significant Byte of the 16-bit TMR3 Register — TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register — TMR5L Least Significant Byte of the 16-bit TMR5 Register — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TABLE 12-7: CONFIGURATION REGISTERS ASSOCIATED WITH TIMER1/3/5 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 DS40001412G-page 168  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 13.0 TIMER2/4/6 MODULE There are three identical 8-bit Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also Timer2/4/6). Note: The ‘x’ variable used in this section is used to designate Timer2, Timer4, or Timer6. For example, TxCON references T2CON, T4CON, or T6CON. PRx references PR2, PR4, or PR6. The Timer2/4/6 module incorporates the following features: • 8-bit Timer and Period registers (TMRx and PRx, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMRx match with PRx, respectively • Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure13-1 for a block diagram of Timer2/4/6. FIGURE 13-1: TIMER2/4/6 BLOCK DIAGRAM Sets Flag TMRx bit TMRxIF Output Prescaler Reset FOSC/4 TMRx 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 TxCKPS<1:0> PRx 4 TxOUTPS<3:0>  2010-2016 Microchip Technology Inc. DS40001412G-page 169

PIC18(L)F2X/4XK22 13.1 Timer2/4/6 Operation 13.2 Timer2/4/6 Interrupt The clock input to the Timer2/4/6 module is the system Timer2/4/6 can also generate an optional device instruction clock (FOSC/4). interrupt. The Timer2/4/6 output signal (TMRx-to-PRx match) provides the input for the 4-bit TMRx increments from 00h on each clock edge. counter/postscaler. This counter generates the TMRx A 4-bit counter/prescaler on the clock input allows direct match interrupt flag which is latched in TMRxIF of the input, divide-by-4 and divide-by-16 prescale options. PIR1/PIR5 registers. The interrupt is enabled by setting These options are selected by the prescaler control bits, the TMRx Match Interrupt Enable bit, TMRxIE of the TxCKPS<1:0> of the TxCON register. The value of PIE1/PIE5 registers. Interrupt Priority is selected with TMRx is compared to that of the Period register, PRx, on the TMRxIP bit in the IPR1/IPR5 registers. each clock cycle. When the two values match, the A range of 16 postscale options (from 1:1 through 1:16 comparator generates a match signal as the timer inclusive) can be selected with the postscaler control output. This signal also resets the value of TMRx to 00h bits, TxOUTPS<3:0>, of the TxCON register. on the next cycle and drives the output counter/postscaler (see Section13.2 “Timer2/4/6 13.3 Timer2/4/6 Output Interrupt”). The TMRx and PRx registers are both directly readable The unscaled output of TMRx is available primarily to and writable. The TMRx register is cleared on any the CCP modules, where it is used as a time base for device Reset, whereas the PRx register initializes to operations in PWM mode. The timer to be used with a FFh. Both the prescaler and postscaler counters are specific CCP module is selected using the cleared on the following events: CxTSEL<1:0> bits in the CCPTMRS0 and CCPTMRS1 registers. • a write to the TMRx register • a write to the TxCON register Timer2 can be optionally used as the shift clock source for the MSSPx modules operating in SPI mode by • Power-on Reset (POR) setting SSPM<3:0> = 0011 in the SSPxCON1 register. • Brown-out Reset (BOR) Additional information is provided in Section15.0 • MCLR Reset “Master Synchronous Serial Port (MSSP1 and • Watchdog Timer (WDT) Reset MSSP2) Module”. • Stack Overflow Reset • Stack Underflow Reset 13.4 Timer2/4/6 Operation During Sleep • RESET Instruction The Timer2/4/6 timers cannot be operated while the processor is in Sleep mode. The contents of the TMRx and PRx registers will remain unchanged while the Note: TMRx is not cleared when TxCON is processor is in Sleep mode. written. 13.5 Peripheral Module Disable When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power con- sumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bits for Timer2 (TMR2MD), Timer4 (TMR4MD) and Timer6 (TMR6MD) are in the PMD0 Register. See Section3.0 “Power-Managed Modes” for more information. DS40001412G-page 170  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 13.6 Register Definitions: Timer2/4/6 Control REGISTER 13-1: TxCON: TIMER2/TIMER4/TIMER6 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TxOUTPS<3:0> TMRxON TxCKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TxOUTPS<3:0>: TimerX Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler bit 2 TMRxON: TimerX On bit 1 = TimerX is on 0 = TimerX is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 =Prescaler is 1 01 =Prescaler is 4 1x =Prescaler is 16  2010-2016 Microchip Technology Inc. DS40001412G-page 171

PIC18(L)F2X/4XK22 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 201 CCPTMRS1 — — — — C5TSEL<1:0> C4TSEL<1:0> 201 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR5 — — — — — TMR6IP TMR5IP TMR4IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE5 — — — — — TMR6IE TMR5IE TMR4IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR5 — — — — — TMR6IF TMR5IF TMR4IF 116 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 PR2 Timer2 Period Register — PR4 Timer4 Period Register — PR6 Timer6 Period Register — T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 166 T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> 166 T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> 166 TMR2 Timer2 Register — TMR4 Timer4 Register — TMR6 Timer6 Register — Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Timer2/4/6. DS40001412G-page 172  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 14.0 CAPTURE/COMPARE/PWM MODULES Note1: In devices with more than one CCP The Capture/Compare/PWM module is a peripheral module, it is very important to pay close which allows the user to time and control different attention to the register names used. A events, and to generate Pulse-Width Modulation number placed after the module acronym (PWM) signals. In Capture mode, the peripheral allows is used to distinguish between separate the timing of the duration of an event. The Compare modules. For example, the CCP1CON mode allows the user to trigger an external event when and CCP2CON control the same a predetermined amount of time has expired. The operational aspects of two completely PWM mode can generate Pulse-Width Modulated different CCP modules. signals of varying frequency and duty cycle. 2: Throughout this section, generic This family of devices contains three Enhanced references to a CCP module in any of its Capture/Compare/PWM modules (ECCP1, ECCP2, operating modes may be interpreted as and ECCP3) and two standard Capture/Compare/PWM being equally applicable to ECCP1, modules (CCP4 and CCP5). ECCP2, ECCP3, CCP4 and CCP5. Register names, module signals, I/O pins, The Capture and Compare functions are identical for all and bit names may use the generic CCP/ECCP modules. The difference between CCP designator ‘x’ to indicate the use of a and ECCP modules are in the Pulse-Width Modulation numeral to distinguish a particular module, (PWM) function. In CCP modules, the standard PWM when required. function is identical. In ECCP modules, the Enhanced PWM function has either full-bridge or half-bridge PWM output. Full-bridge ECCP modules have four available I/O pins while half-bridge ECCP modules only have two available I/O pins. ECCP PWM modules are backward compatible with CCP PWM modules and can be configured as standard PWM modules. See Table14-1 to determine the CCP/ECCP functionality available on each device in this family. TABLE 14-1: PWM RESOURCES Device Name ECCP1 ECCP2 ECCP3 CCP4 CCP5 PIC18(L)F23K22 PIC18(L)F24K22 Enhanced PWM Enhanced PWM Enhanced PWM Standard PWM Standard PWM PIC18(L)F25K22 Full-Bridge Half-Bridge Half-Bridge (Special Event Trigger) PIC18(L)F26K22 PIC18(L)F43K22 PIC18(L)F44K22 Enhanced PWM Enhanced PWM Enhanced PWM Standard PWM Standard PWM PIC18(L)F45K22 Full-Bridge Full-Bridge Half-Bridge (Special Event Trigger) PIC18(L)F46K22  2010-2016 Microchip Technology Inc. DS40001412G-page 173

PIC18(L)F2X/4XK22 14.1 Capture Mode Figure14-1 shows a simplified diagram of the Capture operation. The Capture mode function described in this section is identical for all CCP and ECCP modules available on FIGURE 14-1: CAPTURE MODE this device family. OPERATION BLOCK Capture mode makes use of the 16-bit Timer DIAGRAM resources, Timer1, Timer3 and Timer5. The timer Set Flag bit CCPxIF resources for each CCP capture function are (PIR1/2/4 register) independent and are selected using the CCPTMRS0 Prescaler  1, 4, 16 and CCPTMRS1 registers. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register CCPx CCPRxH CCPRxL pin pair captures and stores the 16-bit value of the TMRxH:TMRxL register pair, respectively. An event is and Capture Edge Detect Enable defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register: TMR1/3/5H TMR1/3/5L CCPxM<3:0> • Every falling edge System Clock (FOSC) • Every rising edge • Every 4th rising edge 14.1.1 CCP PIN CONFIGURATION • Every 16th rising edge In Capture mode, the CCPx pin should be configured When a capture is made, the corresponding Interrupt as an input by setting the associated TRIS control bit. Request Flag bit CCPxIF of the PIR1, PIR2 or PIR4 Some CCPx outputs are multiplexed on a couple of register is set. The interrupt flag must be cleared in pins. Table14-2 shows the CCP output pin software. If another capture occurs before the value in multiplexing. Selection of the output pin is determined the CCPRxH:CCPRxL register pair is read, the old by the CCPxMX bits in Configuration register 3H captured value is overwritten by the new captured (CONFIG3H). Refer to Register24-4 for more details. value. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. TABLE 14-2: CCP PIN MULTIPLEXING CCP OUTPUT CONFIG 3H Control Bit Bit Value PIC18(L)F2XK22 I/O pin PIC18(L)F4XK22 I/O pin 0 RB3 RB3 CCP2 CCP2MX 1(*) RC1 RC1 0(*) RC6 RE0 CCP3 CCP3MX 1 RB5 RB5 Legend: * = Default 14.1.2 TIMER1 MODE RESOURCE 14.1.3 SOFTWARE INTERRUPT MODE The 16-bit Timer resource must be running in Timer When the Capture mode is changed, a false capture mode or Synchronized Counter mode for the CCP interrupt may be generated. The user should keep the module to use the capture feature. In Asynchronous CCPxIE interrupt enable bit of the PIE1, PIE2 or PIE4 Counter mode, the capture operation may not work. register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the See Section12.0 “Timer1/3/5 Module with Gate PIR1, PIR2 or PIR4 register following any change in Control” for more information on configuring the 16-bit Operating mode. Timers. Note: Clocking the 16-bit Timer resource from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, the Timer resource must be clocked from the instruction clock (FOSC/4) or from an external clock source. DS40001412G-page 174  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 14.1.4 CCP PRESCALER 14.1.5 CAPTURE DURING SLEEP There are four prescaler settings specified by the Capture mode requires a 16-bit TimerX module for use CCPxM<3:0> bits of the CCPxCON register. Whenever as a time base. There are four options for driving the the CCP module is turned off, or the CCP module is not 16-bit TimerX module in Capture mode. It can be driven in Capture mode, the prescaler counter is cleared. Any by the system clock (FOSC), the instruction clock (FOSC/ Reset will clear the prescaler counter. 4), or by the external clock sources, the Secondary Switching from one capture prescaler to another does Oscillator (SOSC), or the TxCKI clock input. When the not clear the prescaler and may generate a false 16-bit TimerX resource is clocked by FOSC or FOSC/4, TimerX will not increment during Sleep. When the interrupt. To avoid this unexpected operation, turn the device wakes from Sleep, TimerX will continue from its module off by clearing the CCPxCON register before previous state. Capture mode will operate during Sleep changing the prescaler. Example14-1 demonstrates when the 16-bit TimerX resource is clocked by one of the code to perform this function. the external clock sources (SOSC or the TxCKI pin). EXAMPLE 14-1: CHANGING BETWEEN CAPTURE PRESCALERS #define NEW_CAPT_PS 0x06 //Capture // Prescale 4th ... // rising edge CCPxCON = 0; // Turn the CCP // Module Off CCPxCON = NEW_CAPT_PS; // Turn CCP module // on with new // prescale value TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 198 CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 198 CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 198 CCP4CON — — DC4B<1:0> CCP4M<3:0> 198 CCP5CON — — DC5B<1:0> CCP5M<3:0> 198 CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) — CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) — CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) — CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) — CCPR3H Capture/Compare/PWM Register 3 High Byte (MSB) — CCPR3L Capture/Compare/PWM Register 3 Low Byte (LSB) — CCPR4H Capture/Compare/PWM Register 4 High Byte (MSB) — CCPR4L Capture/Compare/PWM Register 4 Low Byte (LSB) — CCPR5H Capture/Compare/PWM Register 5 High Byte (MSB) — CCPR5L Capture/Compare/PWM Register 5 Low Byte (LSB) — CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 201 CCPTMRS1 — — — — C5TSEL<1:0> C4TSEL<1:0> 201 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR4 — — — — — CCP5IP CCP4IP CCP3IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices.  2010-2016 Microchip Technology Inc. DS40001412G-page 175

PIC18(L)F2X/4XK22 TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE (CONTINUED) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE4 — — — — — CCP5IE CCP4IE CCP3IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR4 — — — — — CCP5IF CCP4IF CCP3IF 115 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSCEN T1SYNC T1RD16 TMR1ON 166 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 167 T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 166 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 167 T5CON TMR5CS<1:0> T5CKPS<1:0> T5SOSCEN T5SYNC T5RD16 TMR5ON 166 T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL T5GSS<1:0> 167 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — TMR1L Least Significant Byte of the 16-bit TMR1 Register — TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register — TMR3L Least Significant Byte of the 16-bit TMR3 Register — TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register — TMR5L Least Significant Byte of the 16-bit TMR5 Register — TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 151 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices. TABLE 14-4: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. DS40001412G-page 176  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 14.2 Compare Mode 14.2.1 CCP PIN CONFIGURATION The Compare mode function described in this section The user must configure the CCPx pin as an output by is identical for all CCP and ECCP modules available on clearing the associated TRIS bit. this device family. Some CCPx outputs are multiplexed on a couple of Compare mode makes use of the 16-bit TimerX pins. Table14-2 shows the CCP output pin resources, Timer1, Timer3 and Timer5. The 16-bit Multiplexing. Selection of the output pin is determined value of the CCPRxH:CCPRxL register pair is by the CCPxMX bits in Configuration register 3H constantly compared against the 16-bit value of the (CONFIG3H). Refer to Register24-4 for more details. TMRxH:TMRxL register pair. When a match occurs, one of the following events can occur: Note: Clearing the CCPxCON register will force • Toggle the CCPx output the CCPx compare output latch to the • Set the CCPx output default low level. This is not the PORT I/O • Clear the CCPx output data latch. • Generate a Special Event Trigger • Generate a Software Interrupt 14.2.2 TimerX MODE RESOURCE The action on the pin is based on the value of the In Compare mode, 16-bit TimerX resource must be CCPxM<3:0> control bits of the CCPxCON register. At running in either Timer mode or Synchronized Counter the same time, the interrupt flag CCPxIF bit is set. mode. The compare operation may not work in Asynchronous Counter mode. All Compare modes can generate an interrupt. See Section12.0 “Timer1/3/5 Module with Gate Figure14-2 shows a simplified diagram of the Control” for more information on configuring the 16-bit Compare operation. TimerX resources. FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM Note: Clocking TimerX from the system clock (FOSC) should not be used in Compare CCPxM<3:0> mode. In order for Compare mode to Mode Select recognize the trigger event on the CCPx pin, TimerX must be clocked from the Set CCPxIF Interrupt Flag (PIR1/2/4) instruction clock (FOSC/4) or from an CCPx 4 external clock source. Pin CCPRxH CCPRxL Q S Output Comparator 14.2.3 SOFTWARE INTERRUPT MODE Logic Match R When Generate Software Interrupt mode is chosen TMRxH TMRxL (CCPxM<3:0>=1010), the CCPx module does not TRIS assert control of the CCPx pin (see the CCPxCON Output Enable register). Special Event Trigger Special Event Trigger function on • ECCP1, ECCP2, ECCP3, CCP4 and CCP5 will: - Reset TimerX – TMRxH:TMRxL = 0x0000 - TimerX Interrupt Flag, (TMRxIF) is not set Additional Function on • CCP5 will - Set ADCON0<1>, GO/DONE bit to start an ADC Conversion if ADCON<0>, ADON = 1.  2010-2016 Microchip Technology Inc. DS40001412G-page 177

PIC18(L)F2X/4XK22 14.2.4 SPECIAL EVENT TRIGGER 14.2.5 COMPARE DURING SLEEP When Special Event Trigger mode is selected The Compare mode is dependent upon the system (CCPxM<3:0>=1011), and a match of the clock (FOSC) for proper operation. Since FOSC is shut TMRxH:TMRxL and the CCPRxH:CCPRxL registers down during Sleep mode, the Compare mode will not occurs, all CCPx and ECCPx modules will immediately: function properly during Sleep. • Set the CCP interrupt flag bit – CCPxIF • CCP5 will start an ADC conversion, if the ADC is enabled On the next TimerX rising clock edge: • A Reset of TimerX register pair occurs – TMRxH:TMRxL = 0x0000, This Special Event Trigger mode does not: • Assert control over the CCPx or ECCPx pins. • Set the TMRxIF interrupt bit when the TMRxH:TMRxL register pair is reset. (TMRxIF gets set on a TimerX overflow.) If the value of the CCPRxH:CCPRxL registers are modified when a match occurs, the user should be aware that the automatic reset of TimerX occurs on the next rising edge of the clock. Therefore, modifying the CCPRxH:CCPRxL registers before this reset occurs will allow the TimerX to continue without being reset, inadvertently resulting in the next event being advanced or delayed. The Special Event Trigger mode allows the CCPRxH:CCPRxL register pair to effectively provide a 16-bit programmable period register for TimerX. TABLE 14-5: REGISTERS ASSOCIATED WITH COMPARE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 198 CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 198 CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 198 CCP4CON — — DC4B<1:0> CCP4M<3:0> 198 CCP5CON — — DC5B<1:0> CCP5M<3:0> 198 CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) — CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) — CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) — CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) — CCPR3H Capture/Compare/PWM Register 3 High Byte (MSB) — CCPR3L Capture/Compare/PWM Register 3 Low Byte (LSB) — CCPR4H Capture/Compare/PWM Register 4 High Byte (MSB) — CCPR4L Capture/Compare/PWM Register 4 Low Byte (LSB) — CCPR5H Capture/Compare/PWM Register 5 High Byte (MSB) — CCPR5L Capture/Compare/PWM Register 5 Low Byte (LSB) — CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 201 CCPTMRS1 — — — — C5TSEL<1:0> C4TSEL<1:0> 201 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Compare mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices. DS40001412G-page 178  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 14-5: REGISTERS ASSOCIATED WITH COMPARE (CONTINUED) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR4 — — — — — CCP5IP CCP4IP CCP3IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE4 — — — — — CCP5IE CCP4IE CCP3IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR4 — — — — — CCP5IF CCP4IF CCP3IF 115 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSCEN T1SYNC T1RD16 TMR1ON 166 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 167 T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 166 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 167 T5CON TMR5CS<1:0> T5CKPS<1:0> T5SOSCEN T5SYNC T5RD16 TMR5ON 166 T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL T5GSS<1:0> 167 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — TMR1L Least Significant Byte of the 16-bit TMR1 Register — TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register — TMR3L Least Significant Byte of the 16-bit TMR3 Register — TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register — TMR5L Least Significant Byte of the 16-bit TMR5 Register — TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 151 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Compare mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices. TABLE 14-6: CONFIGURATION REGISTERS ASSOCIATED WITH COMPARE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Compare mode.  2010-2016 Microchip Technology Inc. DS40001412G-page 179

PIC18(L)F2X/4XK22 14.3 PWM Overview FIGURE 14-3: CCP PWM OUTPUT SIGNAL Pulse-Width Modulation (PWM) is a scheme that Period provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles Pulse Width a square wave where the high portion of the signal is TMRx = PRx considered the on state and the low portion of the signal TMRx = CCPRxH:CCPxCON<5:4> is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in TMRx = 0 steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to FIGURE 14-4: SIMPLIFIED PWM BLOCK the load. Lowering the number of steps applied, which DIAGRAM shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete CCPxCON<5:4> cycle or the total amount of on and off time combined. Duty Cycle Registers PWM resolution defines the maximum number of steps CCPRxL that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. CCPRxH(2) (Slave) CCPx The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, Comparator R Q where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher S TMRx (1) duty cycle corresponds to more power applied. TRIS Figure14-3 shows a typical waveform of the PWM signal. Comparator Clear Timer, toggle CCPx pin and 14.3.1 STANDARD PWM OPERATION latch duty cycle PRx The standard PWM function described in this section is Note 1: The 8-bit timer TMRx register is concatenated available and identical for CCP and ECCP modules. with the 2-bit internal system clock (FOSC), or The standard PWM mode generates a Pulse-Width 2 bits of the prescaler, to create the 10-bit time modulation (PWM) signal on the CCPx pin with up to 10 base. bits of resolution. The period, duty cycle, and resolution 2: In PWM mode, CCPRxH is a read-only register. are controlled by the following registers: • PRx registers 14.3.2 SETUP FOR PWM OPERATION • TxCON registers The following steps should be taken when configuring • CCPRxL registers the CCP module for standard PWM operation: • CCPxCON registers 1. Disable the CCPx pin output driver by setting the Figure14-4 shows a simplified block diagram of PWM associated TRIS bit. operation. 2. Select the 8-bit TimerX resource, (Timer2, Timer4 or Timer6) to be used for PWM generation by setting the CxTSEL<1:0> bits in Note1: The corresponding TRIS bit must be the CCPTMRSx register.(1) cleared to enable the PWM output on the 3. Load the PRx register for the selected TimerX CCPx pin. with the PWM period value. 2: Clearing the CCPxCON register will 4. Configure the CCP module for the PWM mode relinquish control of the CCPx pin. by loading the CCPxCON register with the appropriate values. 5. Load the CCPRxL register and the DCxB<1:0> bits of the CCPxCON register, with the PWM duty cycle value. DS40001412G-page 180  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 6. Configure and start the 8-bit TimerX resource: 14.3.5 PWM DUTY CYCLE • Clear the TMRxIF interrupt flag bit of the The PWM duty cycle is specified by writing a 10-bit PIR2 or PIR4 register. See Note1 below. value to multiple registers: CCPRxL register and • Configure the TxCKPS bits of the TxCON DCxB<1:0> bits of the CCPxCON register. The register with the Timer prescale value. CCPRxL contains the eight MSbs and the DCxB<1:0> • Enable the Timer by setting the TMRxON bits of the CCPxCON register contain the two LSbs. bit of the TxCON register. CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle 7. Enable PWM output pin: value is not latched into CCPRxH until after the period • Wait until the Timer overflows and the completes (i.e., a match between PRx and TMRx TMRxIF bit of the PIR2 or PIR4 register is registers occurs). While using the PWM, the CCPRxH set. See Note1 below. register is read-only. • Enable the CCPx pin output driver by clearing the associated TRIS bit. Equation14-2 is used to calculate the PWM pulse width. Equation14-3 is used to calculate the PWM duty cycle Note1: In order to send a complete duty cycle ratio. and period on the first PWM output, the above steps must be included in the EQUATION 14-2: PULSE WIDTH setup sequence. If it is not critical to start with a complete PWM signal on the first Pulse Width = CCPRxL:CCPxCON<5:4>  output, then step 6 may be ignored. TOSC  (TMRx Prescale Value) 14.3.3 PWM TIMER RESOURCE The PWM standard mode makes use of one of the 8-bit Timer2/4/6 timer resources to specify the PWM period. EQUATION 14-3: DUTY CYCLE RATIO Configuring the CxTSEL<1:0> bits in the CCPTMRS0 CCPRxL:CCPxCON<5:4> or CCPTMRS1 register selects which Timer2/4/6 timer Duty Cycle Ratio = ----------------------------------------------------------------------- 4PRx+1 is used. 14.3.4 PWM PERIOD The CCPRxH register and a 2-bit internal latch are The PWM period is specified by the PRx register of 8-bit used to double buffer the PWM duty cycle. This double TimerX. The PWM period can be calculated using the buffering is essential for glitchless PWM operation. formula of Equation14-1. The 8-bit timer TMRx register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the EQUATION 14-1: PWM PERIOD prescaler, to create the 10-bit time base. The system clock is used if the TimerX prescaler is set to 1:1. PWM Period = PRx+14TOSC When the 10-bit time base matches the CCPRxH and (TMRx Prescale Value) 2-bit latch, then the CCPx pin is cleared (see Figure14-4). Note 1: TOSC = 1/FOSC When TMRx is equal to PRx, the following three events occur on the next increment cycle: • TMRx is cleared • The CCPx pin is set. (Exception: If the PWM duty cycle=0%, the pin will not be set.) • The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: The Timer postscaler (see Section13.0 “Timer2/4/6 Module”) is not used in the determination of the PWM frequency.  2010-2016 Microchip Technology Inc. DS40001412G-page 181

PIC18(L)F2X/4XK22 14.3.6 PWM RESOLUTION EQUATION 14-4: PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution log4PRx+1 Resolution = ------------------------------------------ bits will result in 1024 discrete duty cycles, whereas an 8-bit log2 resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PRx is Note: If the pulse width value is greater than the 255. The resolution is a function of the PRx register period the assigned PWM pin(s) will value as shown by Equation14-4. remain unchanged. TABLE 14-7: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz) PWM Frequency 1.95 kHz 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 14-8: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 14-9: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PRx Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 14.3.7 OPERATION IN SLEEP MODE 14.3.9 EFFECTS OF RESET In Sleep mode, the TMRxregister will not increment Any Reset will force all ports to Input mode and the and the state of the module will not change. If the CCPx CCP registers to their Reset states. pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. 14.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. DS40001412G-page 182  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 14-10: REGISTERS ASSOCIATED WITH STANDARD PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 198 CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 198 CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 198 CCP4CON — — DC4B<1:0> CCP4M<3:0> 198 CCP5CON — — DC5B<1:0> CCP5M<3:0> 198 CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 201 CCPTMRS1 — — — — C5TSEL<1:0> C4TSEL<1:0> 201 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR4 — — — — — CCP5IP CCP4IP CCP3IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE4 — — — — — CCP5IE CCP4IE CCP3IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR4 — — — — — CCP5IF CCP4IF CCP3IF 115 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 PR2 Timer2 Period Register — PR4 Timer4 Period Register — PR6 Timer6 Period Register — T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 166 T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> 166 T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> 166 TMR2 Timer2 Register — TMR4 Timer4 Register — TMR6 Timer6 Register — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 151 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Standard PWM mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices. TABLE 14-11: CONFIGURATION REGISTERS ASSOCIATED WITH STANDARD PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Standard PWM mode.  2010-2016 Microchip Technology Inc. DS40001412G-page 183

PIC18(L)F2X/4XK22 14.4 PWM (Enhanced Mode) To select an Enhanced PWM Output mode, the PxM<1:0> bits of the CCPxCON register must be The enhanced PWM function described in this section is configured appropriately. available for CCP modules ECCP1, ECCP2 and The PWM outputs are multiplexed with I/O pins and are ECCP3, with any differences between modules noted. designated PxA, PxB, PxC and PxD. The polarity of the The enhanced PWM mode generates a Pulse-Width PWM pins is configurable and is selected by setting the Modulation (PWM) signal on up to four different output CCPxM bits in the CCPxCON register appropriately. pins with up to ten bits of resolution. The period, duty Figure14-5 shows an example of a simplified block cycle, and resolution are controlled by the following diagram of the Enhanced PWM module. registers: Table14-12 shows the pin assignments for various • PRx registers Enhanced PWM modes. • TxCON registers • CCPRxL registers • CCPxCON registers Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the The ECCP modules have the following additional PWM CCPx pin. registers which control Auto-shutdown, Auto-restart, Dead-band Delay and PWM Steering modes: 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. • ECCPxAS registers • PSTRxCON registers 3: Any pin not used in the enhanced PWM mode is available for alternate pin • PWMxCON registers functions, if applicable. The enhanced PWM module can generate the following 4: To prevent the generation of an five PWM Output modes: incomplete waveform when the PWM is • Single PWM first enabled, the ECCP module waits • Half-Bridge PWM until the start of a new PWM period • Full-Bridge PWM, Forward mode before generating a PWM signal. • Full-Bridge PWM, Reverse mode • Single PWM with PWM Steering mode FIGURE 14-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DCxB<1:0> PxM<1:0> CCPxM<3:0> Duty Cycle Registers 2 4 CCPRxL CCPx/PxA CCPx/PxA TRISx CCPRxH (Slave) PxB PxB Output TRISx Comparator R Q Controller PxC PxC(2) TMRx (1) S TRISx PxD PxD(2) Comparator Clear Timer, TRISx toggle PWM pin and latch duty cycle PRx PWMxCON Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. 2: PxC and PxD are not available on half-bridge ECCP modules. DS40001412G-page 184  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 14-12: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> CCPx/PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: PWM Steering enables outputs in Single mode. FIGURE 14-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse PRX+1 PxM<1:0> Signal 0 Width Period 00 (Single Output) PxA Modulated Delay(1) Delay(1) PxA Modulated 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>) Note 1: Dead-band delay is programmed using the PWMxCON register (Section14.4.5 “Programmable Dead-Band Delay Mode”).  2010-2016 Microchip Technology Inc. DS40001412G-page 185

PIC18(L)F2X/4XK22 FIGURE 14-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal 0 Pulse PRx+1 Width Period 00 (Single Output) PxA Modulated PxA Modulated Delay(1) Delay(1) 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>) Note 1: Dead-band delay is programmed using the PWMxCON register (Section14.4.5 “Programmable Dead-Band Delay Mode”). DS40001412G-page 186  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 14.4.1 HALF-BRIDGE MODE Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be In Half-Bridge mode, two pins are used as outputs to cleared to configure PxA and PxB as outputs. drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM FIGURE 14-8: EXAMPLE OF HALF- output signal is output on the PxB pin (see Figure14-9). BRIDGE PWM OUTPUT This mode can be used for half-bridge applications, as shown in Figure14-9, or for full-bridge applications, Period Period where four power switches are being modulated with two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay PxA(2) can be used to prevent shoot-through current in half- td bridge power devices. The value of the PDC<6:0> bits of td the PWMxCON register sets the number of instruction PxB(2) cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output (1) (1) (1) remains inactive during the entire cycle. See Section14.4.5 “Programmable Dead-Band Delay td = Dead-Band Delay Mode” for more details of the dead-band delay Note 1: At this time, the TMRx register is equal to the operations. PRx register. 2: Output signals are shown as active-high. FIGURE 14-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA - Load FET Driver + PxB - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver PxA Load FET FET Driver Driver PxB  2010-2016 Microchip Technology Inc. DS40001412G-page 187

PIC18(L)F2X/4XK22 14.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of full-bridge application is shown in Figure14-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure14-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure14-11. PxA, PxB, PxC and PxD outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs. FIGURE 14-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver PxA Load PxB FET FET Driver Driver PxC QB QD V- PxD DS40001412G-page 188  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 14-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA(2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) (1) Note 1: At this time, the TMRx register is equal to the PRx register. 2: Output signal is shown as active-high.  2010-2016 Microchip Technology Inc. DS40001412G-page 189

PIC18(L)F2X/4XK22 14.4.2.1 Direction Change in Full-Bridge This situation occurs when both of the following Mode conditions are true: In the Full-Bridge mode, the PxM1 bit in the CCPxCON 1. The direction of the PWM output changes when register allows users to control the forward/reverse the duty cycle of the output is at or near 100%. direction. When the application firmware changes this 2. The turn off time of the power switch, including direction control bit, the module will change to the new the power device and driver circuit, is greater direction on the next PWM cycle. than the turn on time. A direction change is initiated in software by changing Figure14-13 shows an example of the PWM direction the PxM1 bit of the CCPxCON register. The following changing from forward to reverse, at a near 100% duty sequence occurs four Timer cycles prior to the end of cycle. In this example, at time t1, the output PxA and the current PWM period: PxD become inactive, while output PxC becomes active. Since the turn off time of the power devices is • The modulated outputs (PxB and PxD) are placed longer than the turn on time, a shoot-through current in their inactive state. will flow through power devices QC and QD (see • The associated unmodulated outputs (PxA and Figure14-10) for the duration of ‘t’. The same PxC) are switched to drive in the opposite phenomenon will occur to power devices QA and QB direction. for PWM direction change from reverse to forward. • PWM modulation resumes at the beginning of the If changing PWM direction at high duty cycle is required next period. for an application, two possible solutions for eliminating See Figure14-12 for an illustration of this sequence. the shoot-through current are: The Full-Bridge mode does not provide dead-band 1. Reduce PWM duty cycle for one PWM period delay. As one output is modulated at a time, dead-band before changing directions. delay is generally not required. There is a situation 2. Use switch drivers that can drive the switches off where dead-band delay is required. faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 14-12: EXAMPLE OF PWM DIRECTION CHANGE Signal Period(1) Period PxA (Active-High) PxB (Active-High) Pulse Width PxC (Active-High) (2) PxD (Active-High) Pulse Width Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle. 2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is (TimerX Prescale)/FOSC, where TimerX is Timer2, Timer4 or Timer6. DS40001412G-page 190  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 14-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential T = TOFF – TON Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver. 14.4.3 ENHANCED PWM AUTO- The state of each pin pair is determined by the SHUTDOWN MODE PSSxAC<1:0> and PSSxBD<1:0> bits of the ECCPxAS register. Each pin pair may be placed into one of three The PWM mode supports an Auto-Shutdown mode that states: will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places • Drive logic ‘1’ the PWM output pins into a predetermined state. This • Drive logic ‘0’ mode is used to help prevent the PWM from damaging • Tri-state (high-impedance) the application. The auto-shutdown sources are selected using the Note1: The auto-shutdown condition is a level- CCPxAS<2:0> bits of the ECCPxAS register. A based signal, not an edge-based signal. shutdown event may be generated by: As long as the level is present, the auto- • A logic ‘0’ on the INT pin shutdown will persist. • Comparator Cx (async_CxOUT) 2: Writing to the CCPxASE bit is disabled • Setting the CCPxASE bit in firmware while an auto-shutdown condition A shutdown condition is indicated by the CCPxASE persists. (Auto-Shutdown Event Status) bit of the ECCPxAS 3: Once the auto-shutdown condition has register. If the bit is a ‘0’, the PWM pins are operating been removed and the PWM restarted normally. If the bit is a ‘1’, the PWM outputs are in the (either through firmware or auto-restart), shutdown state. the PWM signal will always restart at the When a shutdown event occurs, two things happen: beginning of the next PWM period. The CCPxASE bit is set to ‘1’. The CCPxASE will remain set until cleared in firmware or an auto-restart occurs (see Section14.4.4 “Auto-Restart Mode”). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [PxA/PxC] and [PxB/PxD].  2010-2016 Microchip Technology Inc. DS40001412G-page 191

PIC18(L)F2X/4XK22 FIGURE 14-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0) Missing Pulse Missing Pulse (Auto-Shutdown) (CCPxASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent CCPxASE bit PWM Shutdown Shutdown Resumes Event Occurs Event Clears CCPxASE Cleared by Firmware 14.4.4 AUTO-RESTART MODE If auto-restart is enabled, the CCPxASE bit will remain set as long as the auto-shutdown condition is active. The Enhanced PWM can be configured to When the auto-shutdown condition is removed, the automatically restart the PWM signal once the auto- CCPxASE bit will be cleared via hardware and normal shutdown condition has been removed. Auto-restart is operation will resume. enabled by setting the PxRSEN bit in the PWMxCON register. FIGURE 14-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1) Missing Pulse Missing Pulse (Auto-Shutdown) (CCPxASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent CCPxASE bit PWM Shutdown Resumes Event Occurs Shutdown CCPxASE Event Clears Cleared by Hardware DS40001412G-page 192  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 14.4.5 PROGRAMMABLE DEAD-BAND FIGURE 14-16: EXAMPLE OF HALF- DELAY MODE BRIDGE PWM OUTPUT In half-bridge applications where all power switches are Period Period modulated at the PWM frequency, the power switches Pulse Width normally require more time to turn off than to turn on. If both the upper and lower power switches are switched PxA(2) at the same time (one turned on, and the other turned td off), both switches may be on for a short period of time td until one switch completely turns off. During this brief PxB(2) interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge (1) (1) (1) supply. To avoid this potentially destructive shoot- through current from flowing during switching, turning td = Dead-Band Delay on either of the power switches is normally delayed to allow the other switch to completely turn off. Note 1: At this time, the TMRx register is equal to the PRx register. In Half-Bridge mode, a digitally programmable dead- band delay is available to avoid shoot-through current 2: Output signals are shown as active-high. from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure14-16 for illustration. The lower seven bits of the associated PWMxCON register (Register14-6) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 14-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA V - Load FET Driver + PxB V - V-  2010-2016 Microchip Technology Inc. DS40001412G-page 193

PIC18(L)F2X/4XK22 14.4.6 PWM STEERING MODE FIGURE 14-18: SIMPLIFIED STEERING BLOCK DIAGRAM In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the STRxA same PWM signal can be simultaneously available on multiple pins. PxA Signal PxA pin CCPxM1 1 Once the Single Output mode is selected (CCPxM<3:2>=11 and PxM<1:0>=00 of the PORT Data CCPxCON register), the user firmware can bring out 0 TRIS the same PWM signal to one, two, three or four output STRxB pins by setting the appropriate Steering Enable bits (STRxA, STRxB, STRxC and/or STRxD) of the CCPxM0 1 PxB pin PSTRxCON register, as shown in Table14-13. PORT Data 0 TRIS Note: The associated TRIS bits must be set to STRxC output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. CCPxM1 1 PxC pin PORT Data 0 While the PWM Steering mode is active, CCPxM<1:0> TRIS bits of the CCPxCON register select the PWM output STRxD polarity for the PxD, PxC, PxB and PxA pins. PxD pin The PWM auto-shutdown operation also applies to CCPxM0 1 PWM Steering mode as described in Section14.4.3 PORT Data “Enhanced PWM Auto-shutdown Mode”. An auto- 0 TRIS shutdown event will only affect pins that have PWM outputs enabled. Note 1: Port outputs are configured as shown when the CCPxCON register bits PxM<1:0>=00 and CCPxM<3:2>=11. 2: Single PWM output requires setting at least one of the STRx bits. 14.4.6.1 Steering Synchronization The STRxSYNC bit of the PSTRxCON register gives the user two selections of when the steering event will happen. When the STRxSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the PxA, PxB, PxC and PxD pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. When the STRxSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. Figures 14-19 and 14-20 illustrate the timing diagrams of the PWM steering depending on the STRxSYNC setting. DS40001412G-page 194  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 14.4.7 START-UP CONSIDERATIONS The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle When any PWM mode is used, the application before enabling the PWM pin output drivers. The hardware must use the proper external pull-up and/or completion of a full PWM cycle is indicated by the pull-down resistors on the PWM output pins. TMRxIF bit of the PIR1, PIR2 or PIR5 register being set The CCPxM<1:0> bits of the CCPxCON register allow as the second PWM period begins. the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (PxA/PxC and PxB/PxD). The PWM output Note: When the microcontroller is released from polarities must be selected before the PWM pin output Reset, all of the I/O pins are in the high- drivers are enabled. Changing the polarity impedance state. The external circuits configuration while the PWM pin output drivers are must keep the power switch devices in the enable is not recommended since it may result in Off state until the microcontroller drives damage to the application circuits. the I/O pins with the proper signal levels or activates the PWM output(s). The PxA, PxB, PxC and PxD output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. FIGURE 14-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0) PWM Period PWM STRx P1<D:A> PORT Data PORT Data P1n = PWM FIGURE 14-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRxSYNC = 1) PWM STRx P1<D:A> PORT Data PORT Data P1n = PWM  2010-2016 Microchip Technology Inc. DS40001412G-page 195

PIC18(L)F2X/4XK22 14.4.8 SETUP FOR ECCP PWM 10. Configure and start TMR2: OPERATION USING ECCP1 AND • Set the TMR2 prescale value by loading the TIMER2 T2CKPS bits of the T2CON register. • Start Timer2 by setting the TMR2ON bit. The following steps should be taken when configuring the ECCP1 module for PWM operation using Timer2: 11. Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. 1. Configure the PWM pins to be used (P1A, P1B, 12. Start the PWM: P1C, and P1D): • If shutdown auto-restart is used, then set the • Configure PWM outputs to be used as inputs P1RSEN bit of the PWM1CON register. by setting the corresponding TRIS bits. This prevents spurious outputs during setup. • If shutdown auto-restart is not used, then clear the CCP1ASE bit of the ECCP1AS • Set the PSTR1CON bits for each PWM register. output to be used. 2. Select Timer2 as the period timer by configuring CCPTMR0 register bits C1TSEL<1:0> = ‘00’. 3. Set the PWM period by loading the PR2 register. 4. Configure auto-shutdown as OFF or select the source with the CCP1AS<2:0> bits of the ECCP1AS register. 5. Configure the auto-shutdown sources as needed: • Configure each comparator used. • Configure the comparator inputs as analog. • Configure the FLT0 input pin and clear ANSB0. 6. Force a shutdown condition (OFF included): • Configure safe starting output levels by setting the default shutdown drive states with the PSS1AC<1:0> and PSS1BD<1:0> bits of the ECCP1AS register. • Clear the P1RSEN bit of the PWM1CON register. • Set the CCP1AS bit of the ECCP1AS register. 7. Configure the ECCP1 module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: • Select one of the available output configura- tions and direction with the P1M<1:0> bits. • Select the polarities of the PWM output signals with the CCP1M<3:0> bits. 8. Set the 10-bit PWM duty cycle: • Load the eight MSbs into the CCPR1L register. • Load the two LSbs into the DC<1:0> bits of the CCP1CON register. 9. For Half-Bridge Output mode, set the dead- band delay by loading P1DC<6:0> bits of the PWM1CON register with the appropriate value. DS40001412G-page 196  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 14-13: REGISTERS ASSOCIATED WITH ENHANCED PWM Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ECCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 202 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 198 ECCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 202 CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 198 ECCP3AS CCP3ASE CCP3AS<2:0> PSS3AC<1:0> PSS3BD<1:0> 202 CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 198 CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 201 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR4 — — — — — CCP5IP CCP4IP CCP3IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE4 — — — — — CCP5IE CCP4IE CCP3IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR4 — — — — — CCP5IF CCP4IF CCP3IF 115 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 PR2 Timer2 Period Register — PR4 Timer4 Period Register — PR6 Timer6 Period Register — PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A 203 PSTR2CON — — — STR2SYNC STR2D STR2C STR2B STR2A 203 PSTR3CON — — — STR3SYNC STR3D STR3C STR3B STR3A 203 PWM1CON P1RSEN P1DC<6:0> 203 PWM2CON P2RSEN P2DC<6:0> 203 PWM3CON P3RSEN P3DC<6:0> 203 T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 166 T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> 166 T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> 166 TMR2 Timer2 Register — TMR4 Timer4 Register — TMR6 Timer6 Register — TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 151 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Enhanced PWM mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices. TABLE 14-14: CONFIGURATION REGISTERS ASSOCIATED WITH ENHANCED PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Enhanced PWM mode.  2010-2016 Microchip Technology Inc. DS40001412G-page 197

PIC18(L)F2X/4XK22 14.5 Register Definitions: ECCP Control REGISTER 14-1: CCPxCON: STANDARD CCPx CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB<1:0> CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unused bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets the module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set) 1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set) 1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected, CCPxIF is set) 1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set) TimerX (selected by CxTSEL bits) is reset ADON is set, starting A/D conversion if A/D module is enabled(1) 11xx =: PWM mode Note 1: This feature is available on CCP5 only. DS40001412G-page 198  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 14-2: CCPxCON: ENHANCED CCPx CONTROL REGISTER R/x-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM<1:0> DCxB<1:0> CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: (Capture/Compare modes) xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins Half-Bridge ECCP Modules(1): If CCPxM<3:2> = 11: (PWM modes) 0x = Single output; PxA modulated; PxB assigned as port pin 1x = Half-Bridge output; PxA, PxB modulated with dead-band control Full-Bridge ECCP Modules(1): If CCPxM<3:2> = 11: (PWM modes) 00 = Single output; PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive 10 = Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins 11 = Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. Note 1: See Table14-1 to determine full-bridge and half-bridge ECCPs for the device being used.  2010-2016 Microchip Technology Inc. DS40001412G-page 199

PIC18(L)F2X/4XK22 REGISTER 14-2: CCPxCON: ENHANCED CCPx CONTROL REGISTER (CONTINUED) bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets the module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set) 1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set) 1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected, CCPxIF is set) 1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set) TimerX is reset Half-Bridge ECCP Modules(1): 1100 = PWM mode: PxA active-high; PxB active-high 1101 = PWM mode: PxA active-high; PxB active-low 1110 = PWM mode: PxA active-low; PxB active-high 1111 = PWM mode: PxA active-low; PxB active-low Full-Bridge ECCP Modules(1): 1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low Note 1: See Table14-1 to determine full-bridge and half-bridge ECCPs for the device being used. DS40001412G-page 200  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 14-3: CCPTMRS0: PWM TIMER SELECTION CONTROL REGISTER 0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C3TSEL<1:0>: CCP3 Timer Selection bits 00 =CCP3 – Capture/Compare modes use Timer1, PWM modes use Timer2 01 =CCP3 – Capture/Compare modes use Timer3, PWM modes use Timer4 10 =CCP3 – Capture/Compare modes use Timer5, PWM modes use Timer6 11 =Reserved bit 5 Unused bit 4-3 C2TSEL<1:0>: CCP2 Timer Selection bits 00 =CCP2 – Capture/Compare modes use Timer1, PWM modes use Timer2 01 =CCP2 – Capture/Compare modes use Timer3, PWM modes use Timer4 10 =CCP2 – Capture/Compare modes use Timer5, PWM modes use Timer6 11 =Reserved bit 2 Unused bit 1-0 C1TSEL<1:0>: CCP1 Timer Selection bits 00 =CCP1 – Capture/Compare modes use Timer1, PWM modes use Timer2 01 =CCP1 – Capture/Compare modes use Timer3, PWM modes use Timer4 10 =CCP1 – Capture/Compare modes use Timer5, PWM modes use Timer6 11 =Reserved REGISTER 14-4: CCPTMRS1: PWM TIMER SELECTION CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — C5TSEL<1:0> C4TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 C5TSEL<1:0>: CCP5 Timer Selection bits 00 =CCP5 – Capture/Compare modes use Timer1, PWM modes use Timer2 01 =CCP5 – Capture/Compare modes use Timer3, PWM modes use Timer4 10 =CCP5 – Capture/Compare modes use Timer5, PWM modes use Timer6 11 =Reserved bit 1-0 C4TSEL<1:0>: CCP4 Timer Selection bits 00 =CCP4 – Capture/Compare modes use Timer1, PWM modes use Timer2 01 =CCP4 – Capture/Compare modes use Timer3, PWM modes use Timer4 10 =CCP4 – Capture/Compare modes use Timer5, PWM modes use Timer6 11 =Reserved  2010-2016 Microchip Technology Inc. DS40001412G-page 201

PIC18(L)F2X/4XK22 REGISTER 14-5: ECCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCPxASE CCPxAS<2:0> PSSxAC<1:0> PSSxBD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCPxASE: CCPx Auto-shutdown Event Status bit if PxRSEN = 1; 1 = An Auto-shutdown event occurred; CCPxASE bit will automatically clear when event goes away; CCPx outputs in shutdown state 0 = CCPx outputs are operating if PxRSEN = 0; 1 = An Auto-shutdown event occurred; bit must be cleared in software to restart PWM; CCPx outputs in shutdown state 0 = CCPx outputs are operating bit 6-4 CCPxAS<2:0>: CCPx Auto-Shutdown Source Select bits (1) 000 =Auto-shutdown is disabled 001 =Comparator C1 (async_C1OUT) – output high will cause shutdown event 010 =Comparator C2 (async_C2OUT) – output high will cause shutdown event 011 =Either Comparator C1 or C2 – output high will cause shutdown event 100 =FLT0 pin – low level will cause shutdown event 101 =FLT0 pin – low level or Comparator C1 (async_C1OUT) – high level will cause shutdown event 110 =FLT0 pin – low level or Comparator C2 (async_C2OUT) – high level will cause shutdown event 111 =FLT0 pin – low level or Comparators C1 or C2 – high level will cause shutdown event bit 3-2 PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits 00 = Drive pins PxA and PxC to ‘0’ 01 = Drive pins PxA and PxC to ‘1’ 1x = Pins PxA and PxC tri-state bit 1-0 PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits 00 = Drive pins PxB and PxD to ‘0’ 01 = Drive pins PxB and PxD to ‘1’ 1x = Pins PxB and PxD tri-state Note 1: If C1SYNC or C2SYNC bits in the CM2CON1 register are enabled, the shutdown will be delayed by Tim- er1. DS40001412G-page 202  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 14-6: PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM bit 6-0 PxDC<6:0>: PWM Delay Count bits PxDCx = Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active REGISTER 14-7: PSTRxCON: PWM STEERING CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — — STRxSYNC STRxD STRxC STRxB STRxA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRxSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRxD: Steering Enable bit D 1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxD pin is assigned to port pin bit 2 STRxC: Steering Enable bit C 1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxC pin is assigned to port pin bit 1 STRxB: Steering Enable bit B 1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxB pin is assigned to port pin bit 0 STRxA: Steering Enable bit A 1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxA pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2>=11 and PxM<1:0>=00.  2010-2016 Microchip Technology Inc. DS40001412G-page 203

PIC18(L)F2X/4XK22 15.0 MASTER SYNCHRONOUS The SPI interface supports the following modes and SERIAL PORT (MSSP1 AND features: MSSP2) MODULE • Master mode • Slave mode 15.1 Master SSPx (MSSPx) Module • Clock Parity Overview • Slave Select Synchronization (Slave mode only) • Daisy chain connection of slave devices The Master Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other Figure15-1 is a block diagram of the SPI interface peripheral or microcontroller devices. These peripheral module. devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSPx module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) FIGURE 15-1: MSSPx BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SDIx SSPxSR Reg SDOx bit 0 Shift Clock SSx SSxControl 2 (CKP, CKE) Enable Clock Select Edge Select SSPxM<3:0> 4 ( T M R 2 O u tp u t ) 2 SCKx Edge Prescaler TOSC Select 4, 16, 64 Baud Rate Generator TRIS bit (SSPxADD) DS40001412G-page 204  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 The I2C interface supports the following modes and The PIC18(L)F2X/4XK22 has two MSSP modules, features: MSSP1 and MSSP2, each module operating independently from the other. • Master mode • Slave mode • Byte NACKing (Slave mode) Note1: In devices with more than one MSSP • Limited Multi-master support module, it is very important to pay close • 7-bit and 10-bit addressing attention to SSPxCONx register names. SSP1CON1 and SSP1CON2 registers • Start and Stop interrupts control different operational aspects of • Interrupt masking the same module, while SSP1CON1 and • Clock stretching SSP2CON1 control the same features for • Bus collision detection two different modules. • General call address matching 2: Throughout this section, generic • Address masking references to an MSSP module in any of • Address Hold and Data Hold modes its operating modes may be interpreted • Selectable SDAx hold times as being equally applicable to MSSP1 or MSSP2. Register names, module I/O Figure15-2 is a block diagram of the I2C interface signals, and bit names may use the module in Master mode. Figure15-3 is a diagram of the generic designator ‘x’ to indicate the use I2C interface module in Slave mode. of a numeral to distinguish a particular module when required. FIGURE 15-2: MSSPx BLOCK DIAGRAM (I2C MASTER MODE) Internal Data Bus [SSPxM 3:0] Read Write SSPxBUF Baud Rate Generator (SSPxADD) SDAx Shift SDAx in Clock SSPxSR ect MSb LSb ntl Det e) Enable (RCEN) GenSetAararcttk ebn i(otS,w SSletPodxpgC ebOit,N2) Clock C Arbitrate/BCOL d off clock sourc SCLx ceive Clock (Hol e R Start bit Detect, Stop bit Detect SCLx in Write Collision Detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV Clock Arbitration Reset SEN, PEN (SSPxCON2) Bus Collision State Counter for Set SSPxIF, BCLxIF end of XMIT/RCV Address Match Detect  2010-2016 Microchip Technology Inc. DS40001412G-page 205

PIC18(L)F2X/4XK22 FIGURE 15-3: MSSPx BLOCK DIAGRAM (I2C SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCLx Shift Clock SSPxSR Reg SDAx MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Set, Reset Stop bit Detect S, P bits (SSPxSTAT Reg) DS40001412G-page 206  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 15.2 SPI Mode Overview During each SPI clock cycle, a full-duplex data transmission occurs. This means that at the same time, The Serial Peripheral Interface (SPI) bus is a the slave device is sending out the MSb from its shift synchronous serial data communication bus that register and the master device is reading this bit from operates in Full-Duplex mode. Devices communicate that same line and saving it as the LSb of its shift in a master/slave environment where the master device register. initiates the communication. A slave device is After 8 bits have been shifted out, the master and slave controlled through a chip select known as Slave Select. have exchanged register values. The SPI bus specifies four signal connections: If there is more data to exchange, the shift registers are • Serial Clock (SCKx) loaded with new data and the process repeats itself. • Serial Data Out (SDOx) Whether the data is meaningful or not (dummy data), • Serial Data In (SDIx) depends on the application software. This leads to • Slave Select (SSx) three scenarios for data transmission: Figure15-1 shows the block diagram of the MSSPx • Master sends useful data and slave sends dummy module when operating in SPI Mode. data. The SPI bus operates with a single master device and • Master sends useful data and slave sends useful one or more slave devices. When multiple slave data. devices are used, an independent Slave Select • Master sends dummy data and slave sends useful connection is required from the master device to each data. slave device. Transmissions may involve any number of clock Figure15-4 shows a typical connection between a cycles. When there is no more data to be transmitted, master device and multiple slave devices. the master stops sending the clock signal and it The master selects only one slave at a time. Most slave deselects the slave. devices have tri-state outputs so their output signal Every slave device connected to the bus that has not appears disconnected from the bus when they are not been selected through its slave select line must disre- selected. gard the clock and transmission signals and must not Transmissions involve two shift registers, eight bits in transmit out any data of its own. size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure15-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDOx output pin which is connected to, and received by, the slave’s SDIx input pin. The slave device transmits information out on its SDOx output pin, which is connected to, and received by, the master’s SDIx input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register.  2010-2016 Microchip Technology Inc. DS40001412G-page 207

PIC18(L)F2X/4XK22 FIGURE 15-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SCLK SCLK SPI Master SDOx SDIx SPI Slave SDIx SDOx #1 General I/O SSx General I/O General I/O SCLK SDIx SPI Slave SDOx #2 SSx SCLK SDIx SPI Slave SDOx #3 SSx 15.2.1 SPI MODE REGISTERS 15.2.2 SPI MODE OPERATION The MSSPx module has five registers for SPI mode When initializing the SPI, several options need to be operation. These are: specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). • MSSPx STATUS register (SSPxSTAT) These control bits allow the following to be specified: • MSSPx Control register 1 (SSPxCON1) • Master mode (SCKx is the clock output) • MSSPx Control register 3 (SSPxCON3) • Slave mode (SCKx is the clock input) • MSSPx Data Buffer register (SSPxBUF) • Clock Polarity (Idle state of SCKx) • MSSPx Address register (SSPxADD) • Data Input Sample Phase (middle or end of data • MSSPx Shift register (SSPxSR) output time) (Not directly accessible) • Clock Edge (output data on rising/falling edge of SSPxCON1 and SSPxSTAT are the control and SCKx) STATUS registers in SPI mode operation. The • Clock Rate (Master mode only) SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper • Slave Select mode (Slave mode only) two bits of the SSPxSTAT are read/write. To enable the serial port, SSPx Enable bit, SSPxEN of In one SPI Master mode, SSPxADD can be loaded the SSPxCON1 register, must be set. To reset or with a value used in the Baud Rate Generator. More reconfigure SPI mode, clear the SSPxEN bit, information on the Baud Rate Generator is available in re-initialize the SSPxCONx registers and then set the Section15.7 “Baud Rate Generator”. SSPxEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins. For the pins to behave SSPxSR is the shift register used for shifting data in as the serial port function, some must have their data and out. SSPxBUF provides indirect access to the direction bits (in the TRIS register) appropriately SSPxSR register. SSPxBUF is the buffer register to programmed as follows: which data bytes are written, and from which data bytes are read. • SDIx must have corresponding TRIS bit set • SDOx must have corresponding TRIS bit cleared In receive operations, SSPxSR and SSPxBUF together create a buffered receiver. When SSPxSR • SCKx (Master mode) must have corresponding receives a complete byte, it is transferred to SSPxBUF TRIS bit cleared and the SSPxIF interrupt is set. • SCKx (Slave mode) must have corresponding TRIS bit set During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and • SSx must have corresponding TRIS bit set SSPxSR. DS40001412G-page 208  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Any serial port function that is not desired may be set. User software must clear the WCOL bit to allow the overridden by programming the corresponding data following write(s) to the SSPxBUF register to complete direction (TRIS) register to the opposite value. successfully. The MSSPx consists of a transmit/receive shift register When the application software is expecting to receive (SSPxSR) and a buffer register (SSPxBUF). The valid data, the SSPxBUF should be read before the SSPxSR shifts the data in and out of the device, MSb next byte of data to transfer is written to the SSPxBUF. first. The SSPxBUF holds the data that was written to The Buffer Full bit, BF of the SSPxSTAT register, the SSPxSR until the received data is ready. Once the indicates when SSPxBUF has been loaded with the 8 bits of data have been received, that byte is moved to received data (transmission is complete). When the the SSPxBUF register. Then, the Buffer Full Detect bit, SSPxBUF is read, the BF bit is cleared. This data may BF of the SSPxSTAT register, and the interrupt flag bit, be irrelevant if the SPI is only a transmitter. Generally, SSPxIF, are set. This double-buffering of the received the MSSPx interrupt is used to determine when the data (SSPxBUF) allows the next byte to start reception transmission/reception has completed. If the interrupt before reading the data that was just received. Any method is not going to be used, then software polling write to the SSPxBUF register during transmission/ can be done to ensure that a write collision does not reception of data will be ignored and the write collision occur. detect bit, WCOL of the SSPxCON1 register, will be FIGURE 15-5: SPI MASTER/SLAVE CONNECTION SPI Master SSPxM<3:0> = 00xx SPI Slave SSPxM<3:0> = 010x = 1010 SDOx SDIx Serial Input Buffer Serial Input Buffer (BUF) (SSPxBUF) SDIx SDOx Shift Register Shift Register (SSPxSR) (SSPxSR) MSb LSb MSb LSb Serial Clock SCKx SCKx Slave Select General I/O SSx Processor 1 (optional) Processor 2  2010-2016 Microchip Technology Inc. DS40001412G-page 209

PIC18(L)F2X/4XK22 15.2.3 SPI MASTER MODE This then, would give waveforms for SPI communication as shown in Figure15-6, Figure15-8, The master can initiate the data transfer at any time Figure15-9 and Figure15-10, where the MSB is because it controls the SCKx line. The master transmitted first. In Master mode, the SPI clock rate (bit determines when the slave (Processor 2, Figure15-5) rate) is user programmable to be one of the following: is to broadcast data by the software protocol. • FOSC/4 (or TCY) In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI • FOSC/16 (or 4 * TCY) is only going to receive, the SDOx output could be dis- • FOSC/64 (or 16 * TCY) abled (programmed as an input). The SSPxSR register • Timer2 output/2 will continue to shift in the signal present on the SDIx • FOSC/(4 * (SSPxADD + 1)) pin at the programmed clock rate. As each byte is Figure15-6 shows the waveforms for Master mode. received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits When the CKE bit is set, the SDOx data is valid before appropriately set). there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The The clock polarity is selected by appropriately time when the SSPxBUF is loaded with the received programming the CKP bit of the SSPxCON1 register data is shown. and the CKE bit of the SSPxSTAT register. FIGURE 15-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDIx (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF DS40001412G-page 210  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 15.2.4 SPI SLAVE MODE 15.2.5 SLAVE SELECT SYNCHRONIZATION In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last The Slave Select can also be used to synchronize bit is latched, the SSPxIF interrupt flag bit is set. communication. The Slave Select line is held high until the master device is ready to communicate. When the Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a new transmission is starting. be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. If the slave fails to receive the communication properly, While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the the external clock source on the SCKx pin. This Slave Select line returns to a high state. The slave is external clock must meet the minimum high and low then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select times as specified in the electrical specifications. line is not used, there is a risk that the slave will even- While in Sleep mode, the slave can transmit/receive tually become out of sync with the master. If the slave data. The shift register is clocked from the SCKx pin misses a bit, it will always be one bit off in future trans- input and when a byte is received, the device will missions. Use of the Slave Select line allows the slave generate an interrupt. If enabled, the device will wake and master to align themselves at the beginning of up from Sleep. each transmission (Figure15-8). 15.2.4.1 Daisy-Chain Configuration The SSx pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SSx pin control The SPI bus can sometimes be connected in a daisy- enabled (SSPxCON1<3:0> = 0100). chain configuration. The first slave output is connected to the second slave input, the second slave output is When the SSx pin is low, transmission and reception connected to the third slave input, and so on. The final are enabled and the SDOx pin is driven. slave output is connected to the master input. Each When the SSx pin goes high, the SDOx pin is no longer slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down first group of clock pulses. The whole chain acts as resistors may be desirable depending on the one large communication shift register. The daisy- application. chain feature only requires a single Slave Select line from the master device. Note 1: When the SPI is in Slave mode with SSx Figure15-7 shows the block diagram of a typical pin control enabled (SSPxCON1<3:0> = daisy-chain connection when operating in SPI Mode. 0100), the SPI module will reset if the SSx In a daisy-chain configuration, only the most recent pin is set to VDD. byte on the bus is required by the slave. Setting the 2: When the SPI is used in Slave mode with BOEN bit of the SSPxCON3 register will enable writes CKE set; the user must enable SSx pin to the SSPxBUF register, even if the previous byte has control. not been read. This allows the software to ignore data that may not apply to it. 3: While operated in SPI Slave mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SSx pin to a high level or clearing the SSPxEN bit.  2010-2016 Microchip Technology Inc. DS40001412G-page 211

PIC18(L)F2X/4XK22 FIGURE 15-7: SPI DAISY-CHAIN CONNECTION SCLK SCLK SPI Master SDOx SDIx SPI Slave SDIx SDOx #1 General I/O SSx SCLK SDIx SPI Slave SDOx #2 SSx SCLK SDIx SPI Slave SDOx #3 SSx FIGURE 15-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDOx bit 7 bit 6 bit 7 bit 6 bit 0 SDIx bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF DS40001412G-page 212  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 15-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE=0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 7 bit 0 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 15-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 7 bit 0 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active  2010-2016 Microchip Technology Inc. DS40001412G-page 213

PIC18(L)F2X/4XK22 15.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/ In SPI Master mode, module clocks may be operating reception will remain in that state until the device at a different speed than when in Full-Power mode; in wakes. After the device returns to Run mode, the the case of the Sleep mode, all clocks are halted. module will resume transmitting and receiving data. Special care must be taken by the user when the In SPI Slave mode, the SPI Transmit/Receive Shift MSSPx clock is much faster than the system clock. register operates asynchronously to the device. This In Slave mode, when MSSPx interrupts are enabled, allows the device to be placed in Sleep mode and data after the master completes sending data, an MSSPx to be shifted into the SPI Transmit/Receive Shift interrupt will wake the controller from Sleep. register. When all eight bits have been received, the MSSPx interrupt flag bit will be set and if enabled, will If an exit from Sleep mode is not desired, MSSPx wake the device. interrupts should be disabled. TABLE 15-1: REGISTERS ASSOCIATED WITH SPI OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 149 ANSELB — — ANSB5 ANSB4 ANSB3(1) ANSB2(1) ANSB1(1) ANSB0(1) 150 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD ANSD7 ANSD6 ANSD5 ANSD4(2) ANSD3(2) ANSD2 ANSD1(2) ANSD0(2) 150 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 SSP1BUF SSP1 Receive Buffer/Transmit Register — SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 253 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 256 SSP1STAT SMP CKE D/A P S R/W UA BF 252 SSP2BUF SSP2 Receive Buffer/Transmit Register — SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 253 SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 256 SSP2STAT SMP CKE D/A P S R/W UA BF 252 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3(1) TRISB2(1) TRISB1(1) TRISB0(1) 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD TRISD7 TRISD6 TRISD5 TRISD4(2) TRISD3(2) TRISD2 TRISD1(2) TRISD0(2) 151 Legend: Shaded bits are not used by the MSSPx in SPI mode. Note 1: PIC18(L)F2XK22 devices. 2: PIC18(L)F4XK22 devices. DS40001412G-page 214  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 15.3 I2C Mode Overview FIGURE 15-11: I2C MASTER/ SLAVE CONNECTION The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master VDD devices initiate the communication. A slave device is controlled through addressing. SCLK SCLK The I2C bus specifies two signal connections: VDD • Serial Clock (SCLx) Master Slave • Serial Data (SDAx) SDIx SDOx Figure15-2 shows the block diagram of the MSSPx module when operating in I2C mode. Both the SCLx and SDAx connections are bidirectional open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal, supply voltage. Pulling the line to ground is considered which holds the SDAx line low to indicate to the a logical zero and letting the line float is considered a transmitter that the slave device has received the logical one. transmitted data and is ready to receive more. Figure15-11 shows a typical connection between two The transition of data bits is always performed while the processors configured as master and slave devices. SCLx line is held low. Transitions that occur while the The I2C bus can operate with one or more master SCLx line is held high are used to indicate Start and devices and one or more slave devices. Stop bits. There are four potential modes of operation for a given If the master intends to write to the slave, then it device: repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this • Master Transmit mode example, the master device is in Master Transmit mode (master is transmitting data to a slave) and the slave is in Slave Receive mode. • Master Receive mode If the master intends to read from the slave, then it (master is receiving data from a slave) repeatedly receives a byte of data from the slave, and • Slave Transmit mode responds after each byte with an ACK bit. In this (slave is transmitting data to a master) example, the master device is in Master Receive mode • Slave Receive mode and the slave is Slave Transmit mode. (slave is receiving data from the master) On the last byte of data communicated, the master To begin communication, a master device starts out in device may end the transmission by sending a Stop bit. Master Transmit mode. The master device sends out a If the master device is in Receive mode, it sends the Start bit followed by the address byte of the slave it Stop bit in place of the last ACK bit. A Stop bit is intends to communicate with. This is followed by a sin- indicated by a low-to-high transition of the SDAx line gle Read/Write bit, which determines whether the mas- while the SCLx line is held high. ter intends to transmit to or receive data from the slave In some cases, the master may want to maintain con- device. trol of the bus and re-initiate another transmission. If If the requested slave exists on the bus, it will respond so, the master device may send another Start bit in with an Acknowledge bit, otherwise known as an ACK. place of the Stop bit or last ACK bit when it is in receive The master then continues in either Transmit mode or mode. Receive mode and the slave continues in the comple- The I2C bus specifies three message protocols; ment, either in Receive mode or Transmit mode, respectively. • Single message where a master writes data to a slave. A Start bit is indicated by a high-to-low transition of the SDAx line while the SCLx line is held high. Address and • Single message where a master reads data from data bytes are sent out, Most Significant bit (MSb) first. a slave. The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a out as a logical zero when it intends to write data to the combination of writes and reads, to one or more slave. slaves.  2010-2016 Microchip Technology Inc. DS40001412G-page 215

PIC18(L)F2X/4XK22 When one device is transmitting a logical one, or letting 15.3.2 ARBITRATION the line float, and a second device is transmitting a Each master device must monitor the bus for Start and logical zero, or holding the line low, the first device can Stop bits. If the device detects that the bus is busy, it detect that the line is not a logical one. This detection, cannot begin a new message until the bus returns to an when used on the SCLx line, is called clock stretching. Idle state. Clock stretching give slave devices a mechanism to control the flow of data. When this detection is used on However, two master devices may try to initiate a the SDAx line, it is called arbitration. Arbitration transmission on or about the same time. When this ensures that there is only one master device occurs, the process of arbitration begins. Each communicating at any single time. transmitter checks the level of the SDAx data line and compares it to the level that it expects to find. The first 15.3.1 CLOCK STRETCHING transmitter to observe that the two levels don’t match, loses arbitration, and must stop transmitting on the When a slave device has not completed processing SDAx line. data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device For example, if one transmitter holds the SDAx line to may hold the SCLx clock line low after receiving or a logical one (lets it float) and a second transmitter sending a bit, indicating that it is not yet ready to holds it to a logical zero (pulls it low), the result is that continue. The master that is communicating with the the SDAx line will be low. The first transmitter then slave will attempt to raise the SCLx line in order to observes that the level of the line is different than transfer the next bit, but will detect that the clock line expected and concludes that another transmitter is has not yet been released. Because the SCLx communicating. connection is open-drain, the slave has the ability to The first transmitter to notice this difference is the one hold that line low until it is ready to continue that loses arbitration and must stop driving the SDAx communicating. line. If this transmitter is also a master device, it also Clock stretching allows receivers that cannot keep up must stop driving the SCLx line. It then can monitor the with a transmitter to control the flow of incoming data. lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDAx line continues with its original transmission. It can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. DS40001412G-page 216  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 15.4 I2C Mode Operation TABLE 15-1: I2C BUS TERMS All MSSPx I2C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt TERM Description flags interface the module with the PIC microcontroller Transmitter The device which shifts data out and user software. Two pins, SDAx and SCLx, are onto the bus. exercised by the module to communicate with other external I2C devices. Receiver The device which shifts data in from the bus. 15.4.1 BYTE FORMAT Master The device that initiates a transfer, generates clock signals and termi- All communication in I2C is done in 9-bit segments. A nates a transfer. byte is sent from a master to a slave or vice-versa, Slave The device addressed by the mas- followed by an Acknowledge bit sent back. After the 8th falling edge of the SCLx line, the device outputting ter. data on the SDAx changes that pin to an input and Multi-master A bus with more than one device reads in an acknowledge value on the next clock that can initiate data transfers. pulse. Arbitration Procedure to ensure that only one The clock signal, SCLx, is provided by the master. master at a time controls the bus. Data is valid to change while the SCLx signal is low, Winning arbitration ensures that and sampled on the rising edge of the clock. Changes the message is not corrupted. on the SDAx line while the SCLx line is high define Synchronization Procedure to synchronize the special conditions on the bus, explained below. clocks of two or more devices on 15.4.2 DEFINITION OF I2C TERMINOLOGY the bus. Idle No master is controlling the bus, There is language and terminology in the description and both SDAx and SCLx lines are of I2C communication that have definitions specific to high. I2C. That word usage is defined below and may be Active Any time one or more master used in the rest of this document without explanation. devices are controlling the bus. This table was adapted from the Phillips I2C Addressed Slave device that has received a specification. Slave matching address and is actively 15.4.3 SDAx AND SCLx PINS being clocked by a master. Selection of any I2C mode with the SSPxEN bit set, Matching Address byte that is clocked into a Address slave that matches the value forces the SCLx and SDAx pins to be open-drain. stored in SSPxADD. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Note: Data is tied to output zero when an I2C Read Request Master sends an address byte with mode is enabled. the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all 15.4.4 SDAx HOLD TIME following bytes until a Restart or Stop. The hold time of the SDAx pin is selected by the Clock Stretching When a device on the bus holds SDAHT bit of the SSPxCON3 register. Hold time is the SCLx low to stall communication. time SDAx is held valid after the falling edge of SCLx. Setting the SDAHT bit selects a longer 300ns mini- Bus Collision Any time the SDAx line is sampled mum hold time and may help on buses with large low by the module while it is out- capacitance. putting and expected high state.  2010-2016 Microchip Technology Inc. DS40001412G-page 217

PIC18(L)F2X/4XK22 15.4.5 START CONDITION 15.4.7 RESTART CONDITION The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid. transition of SDAx from a high-to -low state while SCLx A master can issue a Restart if it wishes to hold the line is high. A Start condition is always generated by bus after terminating the current transfer. A Restart the master and signifies the transition of the bus from has the same effect on the slave that a Start would, an Idle to an active state. Figure15-12 shows wave resetting all slave logic and preparing it to clock in an forms for Start and Stop conditions. address. The master may want to address the same or another slave. Figure15-13 shows the wave form for a A bus collision can occur on a Start condition if the Restart condition. module samples the SDAx line low before asserting it low. This does not conform to the I2C specification that In 10-bit Addressing Slave mode a Restart is required states no bus collision can occur on a Start. for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both 15.4.6 STOP CONDITION high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. A Stop condition is a transition of the SDAx line from a The slave logic will then hold the clock and prepare to low-to-high state while the SCLx line is high. clock out data. After a full match with R/W clear in 10-bit mode, a prior Note: At least one SCLx low time must appear match flag is set and maintained. Until a Stop before a Stop is valid, therefore, if the SDAx condition, a high address with R/W clear, or high line goes low then high again while the SCLx address match fails. line stays high, only the Start condition is 15.4.8 START/STOP CONDITION INTERRUPT detected. MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 15-12: I2C START AND STOP CONDITIONS SDAx SCLx S P Change of Change of Data Allowed Data Allowed Start Stop Condition Condition FIGURE 15-13: I2C RESTART CONDITION Sr Change of Change of Data Allowed Data Allowed Restart Condition DS40001412G-page 218  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 15.4.9 ACKNOWLEDGE SEQUENCE 15.5 I2C Slave Mode Operation The 9th SCLx pulse for any transferred byte in I2C is The MSSPx Slave mode operates in one of four dedicated as an Acknowledge. It allows receiving modes selected in the SSPxM bits of SSPxCON1 devices to respond back to the transmitter by pulling register. The modes can be divided into 7-bit and 10-bit the SDAx line low. The transmitter must release con- Addressing mode. 10-bit Addressing modes operate trol of the line during this time to shift in the response. the same as 7-bit with some additional overhead for The Acknowledge (ACK) is an active-low signal, pull- handling the larger addresses. ing the SDAx line low indicated to the transmitter that Modes with Start and Stop bit interrupts operated the the device has received the transmitted data and is same as the other modes with SSPxIF additionally ready to receive more. getting set upon detection of a Start, Restart, or Stop The result of an ACK is placed in the ACKSTAT bit of condition. the SSPxCON2 register. 15.5.1 SLAVE MODE ADDRESSES Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to The SSPxADD register (Register15-7) contains the the transmitter. The ACKDT bit of the SSPxCON2 Slave mode address. The first byte received after a register is set/cleared to determine the response. Start or Restart condition is compared against the Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the AHEN and DHEN bits of the SSPxCON3 register are value is loaded into the SSPxBUF register and an clear. interrupt is generated. If the value does not match, the module goes Idle and no indication is given to the There are certain conditions where an ACK will not be software that anything happened. sent by the slave. If the BF bit of the SSPxSTAT register or the SSPxOV bit of the SSPxCON1 register The SSPx Mask register (Register15-6) affects the are set when a byte is received. address matching process. See Section15.5.9 “SSPx Mask Register” for more information. When the module is addressed, after the 8th falling edge of SCLx on the bus, the ACKTIM bit of the SSPx- 15.5.1.1 I2C Slave 7-bit Addressing Mode CON3 register is set. The ACKTIM bit indicates the In 7-bit Addressing mode, the LSb of the received data acknowledge time of the active bus. byte is ignored when determining if there is an address The ACKTIM Status bit is only active when the AHEN match. bit or DHEN bit is enabled. 15.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCLx is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCLx is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match.  2010-2016 Microchip Technology Inc. DS40001412G-page 219

PIC18(L)F2X/4XK22 15.5.2 SLAVE RECEPTION 15.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte Slave device reception with AHEN and DHEN set is clear, the R/W bit of the SSPxSTAT register is operate the same as without these options with extra cleared. The received address is loaded into the interrupts and clock stretching added after the 8th fall- SSPxBUF register and acknowledged. ing edge of SCLx. These additional interrupts allow the slave software to decide whether it wants to ACK the When the overflow condition exists for a received receive address or data byte, rather than the hard- address, then not Acknowledge is given. An overflow ware. This functionality adds support for PMBus™ that condition is defined as either bit BF of the SSPxSTAT was not present on previous versions of this module. register is set, or bit SSPxOV of the SSPxCON1 regis- ter is set. The BOEN bit of the SSPxCON3 register This list describes the steps that need to be taken by modifies this operation. For more information see slave software to use these options for I2C Register15-5. communication. Figure15-16 displays a module using both address and data holding. Figure15-17 includes An MSSPx interrupt is generated for each transferred the operation with the SEN bit of the SSPxCON2 data byte. Flag bit, SSPxIF, must be cleared by register set. software. 1. S bit of SSPxSTAT is set; SSPxIF is set if When the SEN bit of the SSPxCON2 register is set, interrupt on Start detect is enabled. SCLx will be held low (clock stretch) following each received byte. The clock must be released by setting 2. Matching address with R/W bit clear is clocked the CKP bit of the SSPxCON1 register, except in. SSPxIF is set and CKP cleared after the 8th sometimes in 10-bit mode. See Section15.2.3 “SPI falling edge of SCLx. Master Mode” for more detail. 3. Slave clears the SSPxIF. 4. Slave can look at the ACKTIM bit of the SSPx- 15.5.2.1 7-bit Addressing Reception CON3 register to determine if the SSPxIF was This section describes a standard sequence of events after or before the ACK. for the MSSPx module configured as an I2C slave in 5. Slave reads the address value from SSPxBUF, 7-bit Addressing mode. All decisions made by hard- clearing the BF flag. ware or software and their effect on reception. 6. Slave sets ACK value clocked out to the master Figure15-14 and Figure15-5 are used as a visual by setting ACKDT. reference for this description. 7. Slave releases the clock by setting CKP. This is a step by step process of what typically must 8. SSPxIF is set after an ACK, not after a NACK. be done to accomplish I2C communication. 9. If SEN=1 the slave hardware will stretch the 1. Start bit detected. clock after the ACK. 2. S bit of SSPxSTAT is set; SSPxIF is set if 10. Slave clears SSPxIF interrupt on Start detect is enabled. . 3. Matching address with R/W bit clear is received. Note: SSPxIF is still set after the 9th falling edge of 4. The slave pulls SDAx low sending an ACK to the SCLx even if there is no clock stretching and master, and sets SSPxIF bit. BF has been cleared. Only if NACK is sent 5. Software clears the SSPxIF bit. to master is SSPxIF not set. 6. Software reads received address from SSPxBUF clearing the BF flag. 7. If SEN=1; Slave software sets CKP bit to 11. SSPxIF set and CKP cleared after 8th falling release the SCLx line. edge of SCLx for a received data byte. 8. The master clocks out a data byte. 12. Slave looks at ACKTIM bit of SSPxCON3 to 9. Slave drives SDAx low sending an ACK to the determine the source of the interrupt. master, and sets SSPxIF bit. 13. Slave reads the received data from SSPxBUF 10. Software clears SSPxIF. clearing BF. 11. Software reads the received byte from 14. Steps 7-14 are the same for each received data SSPxBUF clearing BF. byte. 12. Steps 8-12 are repeated for all received bytes 15. Communication is ended by either the slave from the master. sending an ACK=1, or the master sending a Stop condition. If a Stop is sent and Interrupt on 13. Master sends Stop condition, setting P bit of Stop detect is disabled, the slave will only know SSPxSTAT, and the bus goes Idle. by polling the P bit of the SSTSTAT register. DS40001412G-page 220  2010-2016 Microchip Technology Inc.

D FIGURE 15-14: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=0, DHEN=0) P S 4 0 I 0 C 0 1 41 Bus Master sends 1 2 Stop condition G 8 -p From Slave to Master a ( g e Receiving Address Receiving Data Receiving Data ACK=1 L 2 SDAx 21 A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ) F 2 SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 X S P / 4 X K SSPxIF 2 SSPxIF set on 9th Cleared by software Cleared by software falling edge of 2 SCLx BF First byte SSPxBUF is read of data is available in SSPxBUF SSPxOV SSPxOV set because SSPxBUF is still full. ACK is not sent.  2 0 1 0 -2 0 1 6 M ic ro c h ip T e c h n o lo g y In c .

 FIGURE 15-15: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) 2 0 1 0 -2 0 1 6 M Bus Master sends ic Stop condition ro c h ip T Receive Address Receive Data Receive Data ACK e ch SDAx A7 A6 A5 A4 A3 A2 A1 R/W=0ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 n o lo g y In c. SCLx S 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 P Clock is held low until CKP is set to ‘1’ SSPxIF SSPxIF set on 9th Cleared by software Cleared by software falling edge of SCLx BF First byte of data is SSPxBUF is read available in SSPxBUF P SSPxOV I C SSPxOV set because SSPxBUF is still full. 1 ACK is not sent. 8 CKP ( L rCeKlePa sisin wg rSittCeLnx to ‘1’ in software, CreKlePa issi nwgr iSttCenL xto 1 in software, SloCwL bxe icsa nuoste held )F ACK=1 2 D X S 4 0 / 00 4 1 4 X 1 2 G K -p a g 2 e 2 2 2 2

D FIGURE 15-16: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=1) P S 4 0 I 0 C 0 1 41 Master Releases SDAx Master sends 1 2G to slave for ACK sequence Stop condition 8 -p age 2 SDAx A7 RAe6ceAiv5ingA A4ddAr3essA2 A1 ACK D7 D6 DR5eceDi4vinDg 3DaDta2 D1 D0 ACKD7 D6 D5ReDce4iveDd3 DDat2a D1 D0 ACK=1 (L 2 ) 3 F SCLx 2 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P X / SSPxIF 4 If AHEN= 1: SSPxIF is set on X SSPxIF is set 9th falling edge of Cleared by software No interrupt SCLx, after ACK after not ACK K BF from Slave 2 Address is read from Data is read from SSPxBUF 2 ACKDT SSBUF Slave software clears ACKDT to Slave software ACK the received sets ACKDT to CKP byte not ACK When AHEN=1: CKP is cleared by hardware When DHEN=1: CKP set by software, CKP is cleared by and SCLx is stretched SCLx is released hardware on 8th falling edge of SCLx ACKTIM  ACKTIM set by hardware ACKTIM cleared by ACKTIM set by hardware 2 on 8th falling edge of SCLx hardware in 9th on 8th falling edge of SCLx 0 rising edge of SCLx 1 0 -2 0 1 6 S M icro P c h ip T e c h n o lo g y In c .

 FIGURE 15-17: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN= 1, AHEN=1, DHEN=1) 2 0 1 0 -20 Master sends 1 Stop condition 6 Master releases M R/W = 0 SDAx to slave for ACK sequence icroch SDAx A7 A6ReAc5eivAin4g AA3ddAre2ssA1 ACK D7 D6 D5ReDc4eivDe3 DDat2aD1 D0 ACK D7 D6 D5ReDc4eivDe3 DDat2aD1 D0 ACK ip T e c h SCLx no 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P lo S g y In c . SSPxIF Cleared by software No interrupt after if not ACK from Slave BF Received address is loaded into Received data is SSPxBUF can be SSPxBUF available on SSPxBUF read any time before next byte is loaded ACKDT Slave software clears Slave sends ACKDT to ACK not ACK the received byte CKP When AHEN=1; When DHEN = 1; CKP is not cleared P on the 8th falling edge on the 8th falling edge Set by software, if not ACK of SCLx of an address of SCLx of a received release SCLx I byte, CKP is cleared data byte, CKP is cleared C 1 ACKTIM 8 ( ACKTIM is set by hardware ACKTIM is cleared by hardware L on 8th falling edge of SCLx on 9th rising edge of SCLx ) S F 2 D P X S 4 0 / 00 4 1 4 X 1 2 G K -p a g 2 e 2 2 2 4

PIC18(L)F2X/4XK22 15.5.3 SLAVE TRANSMISSION 15.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set A master device can transmit a read request to a and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list SSPxSTAT register is set. The received address is below outlines what software for a slave will need to do loaded into the SSPxBUF register, and an ACK pulse is to accomplish a standard transmission. Figure15-18 sent by the slave on the ninth bit. can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDAx and and the SCLx pin is held low (see Section15.5.6 SCLx. “Clock Stretching” for more detail). By stretching the 2. S bit of SSPxSTAT is set; SSPxIF is set if inter- clock, the master will be unable to assert another clock rupt on Start detect is enabled. pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by data. the slave setting SSPxIF bit. The transmit data must be loaded into the SSPxBUF 4. Slave hardware generates an ACK and sets register which also loads the SSPxSR register. Then SSPxIF. the SCLx pin should be released by setting the CKP bit 5. SSPxIF bit is cleared by user. of the SSPxCON1 register. The eight data bits are 6. Software reads the received address from shifted out on the falling edge of the SCLx input. This SSPxBUF, clearing BF. ensures that the SDAx signal is valid during the SCLx 7. R/W is set so CKP was automatically cleared high time. after the ACK. The ACK pulse from the master-receiver is latched on 8. The slave software loads the transmit data into the rising edge of the ninth SCLx input pulse. This ACK SSPxBUF. value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data 9. CKP bit is set releasing SCLx, allowing the transfer is complete. In this case, when the not ACK is master to clock the data out of the slave. latched by the slave, the slave goes Idle and waits for 10. SSPxIF is set after the ACK response from the another occurrence of the Start bit. If the SDAx line was master is loaded into the ACKSTAT register. low (ACK), the next transmit data must be loaded into 11. SSPxIF bit is cleared. the SSPxBUF register. Again, the SCLx pin must be 12. The slave software checks the ACKSTAT bit to released by setting bit CKP. see if the master wants to clock out more data. An MSSPx interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status Note 1: If the master ACKs the clock will be of the byte. The SSPxIF bit is set on the falling edge of stretched. the ninth clock pulse. 2: ACKSTAT is the only bit updated on the rising edge of SCLx (9th) rather than the 15.5.3.1 Slave Mode Bus Collision falling. A slave receives a Read request and begins shifting data out on the SDAx line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, 13. Steps 9-13 are repeated for each transmitted the BCLxIF bit of the PIRx register is set. Once a bus byte. collision is detected, the slave goes Idle and waits to be 14. If the master sends a not ACK; the clock is not addressed again. User software can use the BCLxIF bit held, but SSPxIF is still set. to handle a slave bus collision. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed.  2010-2016 Microchip Technology Inc. DS40001412G-page 225

 FIGURE 15-18: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=0) 2 0 1 0 -2 0 1 Master sends 6 M Stop condition ic roc Receiving Address R/W=1 Automatic Transmitting Data Automatic Transmitting Data ACK hip SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 T e SCLx c h 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 no S P lo g y In SSPxIF c . Cleared by software BF BF is automatically Received address Data to transmit is cleared after 8th falling is read from SSPxBUF loaded into SSPxBUF edge of SCLx CKP When R/W is set CKP is not SCLx is always held for not held low after 9th SCLx Set by software ACK falling edge ACKSTAT P Masters not ACK is copied to I C ACKSTAT R/W 1 R/W is copied from the 8 matching address byte ( D/A L ) Indicates an address F has been received 2 D S X S 4 0 / 00 P 4 1 4 X 1 2 G K -p a g 2 e 2 2 2 6

PIC18(L)F2X/4XK22 15.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure15-19 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. Bus starts Idle. 2. Master sends Start condition; the S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCLx line the CKP bit is cleared and SSPxIF interrupt is generated. 4. Slave software clears SSPxIF. 5. Slave software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSPxCON2 register accordingly. 8. Slave sets the CKP bit releasing SCLx. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Slave software clears SSPxIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCLx pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCLx line to receive a Stop.  2010-2016 Microchip Technology Inc. DS40001412G-page 227

 FIGURE 15-19: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=1) 2 0 1 0 -2 0 1 Master sends 6 M Master releases SDAx Stop condition ic to slave for ACK sequence roc Receiving Address R/W=1 Automatic Transmitting Data Automatic Transmitting Data ACK hip SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 T e c SCLx hn S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 o P lo g y In SSPxIF c Cleared by software . BF BF is automatically Received address Data to transmit is cleared after 8th falling is read from SSPxBUF loaded into SSPxBUF edge of SCLx ACKDT Slave clears ACKDT to ACK address ACKSTAT Master’s ACK response is copied P to SSPxSTAT I CKP C When AHEN = 1; CKP not cleared CKP is cleared by hardware When R/W = 1; Set by software, after not ACK 1 after receiving matching CKP is always releases SCLx 8 address. cleared after ACK ( L ACKTIM ACKTIM is set on 8th falling ACKTIM is cleared ) edge of SCLx on 9th rising edge of SCLx F 2 D R/W X S 4 0 D/A / 00 4 1 4 X 1 2 G K -p a g 2 e 2 2 2 8

PIC18(L)F2X/4XK22 15.5.4 SLAVE MODE 10-BIT ADDRESS 15.5.5 10-BIT ADDRESSING WITH ADDRESS RECEPTION OR DATA HOLD This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or for the MSSPx module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only 10-bit Addressing mode (Figure15-20) and is used as difference is the need to update the SSPxADD register a visual reference for this description. using the UA bit. All functionality, specifically when the CKP bit is cleared and SCLx line is held low are the This is a step by step process of what must be done by slave software to accomplish I2C communication. same. Figure15-21 can be used as a reference of a slave in 10-bit addressing with AHEN set. 1. Bus starts Idle. Figure15-22 shows a standard waveform for a slave 2. Master sends Start condition; S bit of SSPxSTAT transmitter in 10-bit Addressing mode. is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. 4. Slave sends ACK and SSPxIF is set. 5. Software clears the SSPxIF bit. 6. Software reads received address from SSPxBUF clearing the BF flag. 7. Slave loads low address into SSPxADD, releasing SCLx. 8. Master sends matching low address byte to the slave; UA bit is set. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPxIF is set. Note: If the low address does not match, SSPxIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPxIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCLx pulse; SSPxIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPxIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCLx. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission.  2010-2016 Microchip Technology Inc. DS40001412G-page 229

 FIGURE 15-20: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) 2 0 1 0 -2 0 1 Master sends 6 M Stop condition ic ro chip Receive First Address Byte Receive Second Address Byte Receive Data Receive Data T SDAx ec 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK h n o lo SCLx g 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P y In S c SCLx is held low . while CKP = 0 SSPxIF Set by hardware Cleared by software on 9th falling edge BF If address matches Receive address is Data is read SSPxADD it is loaded into read from SSPxBUF from SSPxBUF SSPxBUF P UA I When UA = 1; Software updates SSPxADD C SCLx is held low and releases SCLx 1 8 CKP ( L ) When SEN = 1; Set by software, F CKP is cleared after releasing SCLx 9th falling edge of received byte 2 D X S 4 0 / 00 4 1 4 X 1 2 G K -p a g 2 e 2 2 3 0

D FIGURE 15-21: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=0) P S 4 0 I 0 C 0 1 4 12G Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data 18 -p SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 a ( g e L 2 3 ) 1 F SCLx S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2 2 X / 4 SSPxIF X Set by hardware Cleared by software Cleared by software K on 9th falling edge 2 2 BF SSPxBUF can be Received data read anytime before is read from the next received byte SSPxBUF ACKDT Slave software clears ACKDT to ACK the received byte UA Update to SSPxADD is Update of SSPxADD, not allowed until 9th clears UA and releases  falling edge of SCLx 2 SCLx 0 1 0 -2 0 CKP If when AHEN=1; 16 on the 8th falling edge Set CKP with software M of SCLx of an address releases SCLx ic byte, CKP is cleared ro ACKTIM c h ip ACKTIM is set by hardware T on 8th falling edge of SCLx e c h n o lo g y In c .

 FIGURE 15-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN=0, AHEN=0, DHEN=0) 2 0 1 0 -2 01 Master sends 6 Master sends Stop condition M Restart event Master sends ic not ACK ro c hip Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1 T SDAx 1 1 1 1 0 A9A8 ACK A7A6 A5A4A3A2 A1A0 ACK 1 1 1 1 0 A9A8 ACK D7D6D5D4D3D2D1D0 e c h n o lo gy SCLx S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P In Sr c . SSPxIF Set by hardware Cleared by software Set by hardware BF SSPxBUF loaded Received address is Data to transmit is with received address read from SSPxBUF loaded into SSPxBUF UA High address is loaded UA indicates SSPxADD After SSPxADD is back into SSPxADD must be updated updated, UA is cleared CKP and SCLx is released P When R/W = 1; Set by software I ACKSTAT CKP is cleared on releases SCLx C 9th falling edge of SCLx 1 Masters not ACK is copied 8 R/W ( L R/W is copied from the matching address byte ) D/A F Indicates an address 2 D has been received X S 4 0 / 00 4 1 4 X 1 2 G K -p a g 2 e 2 2 3 2

PIC18(L)F2X/4XK22 15.5.6 CLOCK STRETCHING 15.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set, the holds the SCLx line low effectively pausing communi- clock is always stretched. This is the only time the cation. The slave may stretch the clock to allow more SCLx is stretched without CKP being cleared. SCLx is time to handle data or prepare a response for the mas- released immediately after a write to SSPxADD. ter device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done Note: Previous versions of the module did not by a slave is invisible to the master software and han- stretch the clock if the second address byte dled by the hardware that generates SCLx. did not match. The CKP bit of the SSPxCON1 register is used to 15.5.6.3 Byte NACKing control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCLx line to go When the AHEN bit of SSPxCON3 is set; CKP is low and then hold it. Setting CKP will release SCLx cleared by hardware after the 8th falling edge of SCLx and allow more communication. for a received matching address byte. When the DHEN bit of SSPxCON3 is set; CKP is cleared after 15.5.6.1 Normal Clock Stretching the 8th falling edge of SCLx for received data. Following an ACK if the R/W bit of SSPxSTAT is set, a Stretching after the 8th falling edge of SCLx allows the read request, the slave hardware will clear CKP. This slave to look at the received address or data and allows the slave time to update SSPxBUF with data to decide if it wants to ACK the received data. transfer to the master. If the SEN bit of SSPxCON2 is 15.5.7 CLOCK SYNCHRONIZATION AND set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP THE CKP BIT is set by software and communication resumes. Any time the CKP bit is cleared, the module will wait Note 1: The BF bit has no effect on whether the for the SCLx line to go low and then hold it. However, clock will be stretched or not. This is clearing the CKP bit will not assert the SCLx output different than previous versions of the low until the SCLx output is already sampled low. module that would not stretch the clock, Therefore, the CKP bit will not assert the SCLx line clear CKP, if SSPxBUF was read before until an external I2C master device has already the 9th falling edge of SCLx. asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the 2: Previous versions of the module did not I2C bus have released SCLx. This ensures that a write stretch the clock for a transmission if to the CKP bit will not violate the minimum high time SSPxBUF was loaded before the 9th fall- requirement for SCLx (see Figure15-23). ing edge of SCLx. It is now always cleared for read requests. FIGURE 15-23: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX DX ‚ – 1 SCLx Master device CKP asserts clock Master device releases clock WR SSPxCON1  2010-2016 Microchip Technology Inc. DS40001412G-page 233

PIC18(L)F2X/4XK22 15.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave The addressing procedure for the I2C bus is such that will prepare to receive the second byte as data, just as the first byte after the Start condition usually it would in 7-bit mode. determines which device will be the slave addressed If the AHEN bit of the SSPxCON3 register is set, just by the master device. The exception is the general call as with any other address reception, the slave address which can address all devices. When this hardware will stretch the clock after the 8th falling address is used, all devices should, in theory, respond edge of SCLx. The slave must then set its ACKDT with an acknowledge. value and release the clock with communication The general call address is a reserved address in the progressing as it would normally. I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave soft- ware can read SSPxBUF and respond. Figure15-24 shows a general call reception sequence. FIGURE 15-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDAx General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPxIF BF (SSPxSTAT<0>) Cleared by software SSPxBUF is read GCEN (SSPxCON2<7>) ’1’ 15.5.9 SSPx MASK REGISTER An SSPx Mask (SSPxMSK) register (Register15-6) is available in I2C Slave mode as a mask for the value held in the SSPxSR register during an address comparison operation. A zero (‘0’) bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSPx operation until written with a mask value. The SSPx Mask register is active during: • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSPx mask has no effect during the reception of the first (high) byte of the address. DS40001412G-page 234  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 15.6 I2C Master Mode 15.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the The master device generates all of the serial clock appropriate SSPxM bits in the SSPxCON1 register and pulses and the Start and Stop conditions. A transfer is by setting the SSPxEN bit. In Master mode, the SCLx ended with a Stop condition or with a Repeated Start and SDAx lines are set as inputs and are manipulated condition. Since the Repeated Start condition is also by the MSSPx hardware. the beginning of the next serial transfer, the I2C bus will not be released. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop con- In Master Transmitter mode, serial data is output ditions. The Stop (P) and Start (S) bits are cleared from through SDAx, while SCLx outputs the serial clock. The a Reset or when the MSSPx module is disabled. Con- first byte transmitted contains the slave address of the trol of the I2C bus may be taken when the P bit is set, receiving device (7 bits) and the Read/Write (R/W) bit. or the bus is Idle. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is In Firmware Controlled Master mode, user code transmitted, an Acknowledge bit is received. Start and conducts all I2C bus operations based on Start and Stop conditions are output to indicate the beginning Stop bit condition detection. Start and Stop condition and the end of a serial transfer. detection is the only active circuitry in this mode. All other communication is done by the user software In Master Receive mode, the first byte transmitted directly manipulating the SDAx and SCLx lines. contains the slave address of the transmitting device (7bits) and the R/W bit. In this case, the R/W bit will be The following events will cause the SSPx Interrupt Flag logic ‘1’. Thus, the first byte transmitted is a 7-bit slave bit, SSPxIF, to be set (SSPx interrupt, if enabled): address followed by a ‘1’ to indicate the receive bit. • Start condition detected Serial data is received via SDAx, while SCLx outputs the serial clock. Serial data is received eight bits at a • Stop condition detected time. After each byte is received, an Acknowledge bit is • Data transfer byte transmitted/received transmitted. Start and Stop conditions indicate the • Acknowledge transmitted/received beginning and end of transmission. • Repeated Start generated A Baud Rate Generator is used to set the clock frequency output on SCLx. See Section15.7 “Baud Rate Generator” for more detail. Note 1: The MSSPx module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete.  2010-2016 Microchip Technology Inc. DS40001412G-page 235

PIC18(L)F2X/4XK22 15.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure15-25). FIGURE 15-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX DX ‚ – 1 SCLx deasserted but slave holds SCLx allowed to transition high SCLx low (clock arbitration) SCLx BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCLx is sampled high, reload takes place and BRG starts its count BRG Reload 15.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not Idle. Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPxCON2 is disabled until the Start con- dition is complete. DS40001412G-page 236  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 15.6.4 I2C MASTER MODE START When the Baud Rate Generator times out (TBRG), the CONDITION TIMING SEN bit of the SSPxCON2 register will be automatically cleared by hardware; the Baud Rate To initiate a Start condition (Figure15-26), the user Generator is suspended, leaving the SDAx line held sets the Start Enable bit, SEN, of the SSPxCON2 reg- low and the Start condition is complete. ister. If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count. If SCLx and Note 1: If at the beginning of the Start condition, SDAx are both sampled high when the Baud Rate the SDAx and SCLx pins are already sam- Generator times out (TBRG), the SDAx pin is driven pled low, or if during the Start condition, low. The action of the SDAx being driven low while the SCLx line is sampled low before the SCLx is high is the Start condition and causes the S bit SDAx line is driven low, a bus collision of the SSPxSTAT1 register to be set. Following this, occurs, the Bus Collision Interrupt Flag, the Baud Rate Generator is reloaded with the contents BCLxIF, is set, the Start condition is of SSPxADD<7:0> and resumes its count. aborted and the I2C module is reset into its Idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start. FIGURE 15-26: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPxSTAT<3>) At completion of Start bit, SDAx = 1, hardware clears SEN bit SCLx = 1 and sets SSPxIF bit TBRG TBRG Write to SSPxBUF occurs here SDAx 1st bit 2nd bit TBRG SCLx S TBRG  2010-2016 Microchip Technology Inc. DS40001412G-page 237

PIC18(L)F2X/4XK22 15.6.5 I2C MASTER MODE REPEATED Following this, the RSEN bit of the SSPxCON2 register START CONDITION TIMING will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin A Repeated Start condition (Figure15-27) occurs when held low. As soon as a Start condition is detected on the the RSEN bit of the SSPxCON2 register is SDAx and SCLx pins, the S bit of the SSPxSTAT programmed high and the master state machine is no register will be set. The SSPxIF bit will not be set until longer active. When the RSEN bit is set, the SCLx pin the Baud Rate Generator has timed out. is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDAx pin is released (brought high) for one Baud Note1: If RSEN is programmed while any other Rate Generator count (TBRG). When the Baud Rate event is in progress, it will not take effect. Generator times out, if SDAx is sampled high, the SCLx 2: A bus collision during the Repeated Start pin will be deasserted (brought high). When SCLx is condition occurs if: sampled high, the Baud Rate Generator is reloaded and begins counting. SDAx and SCLx must be • SDAx is sampled low when SCLx sampled high for one TBRG. This action is then followed goes from low-to-high. by assertion of the SDAx pin (SDAx=0) for one TBRG • SCLx goes low before SDAx is while SCLx is high. SCLx is asserted low. asserted low. This may indicate that another master is attempting to transmit a data ‘1’. FIGURE 15-27: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here At completion of Start bit, SDAx = 1, SDAx = 1, hardware clears RSEN bit SCLx (no change) SCLx = 1 and sets SSPxIF TBRG TBRG TBRG SDAx 1st bit Write to SSPxBUF occurs here TBRG SCLx Sr TBRG Repeated Start DS40001412G-page 238  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 15.6.6 I2C MASTER MODE TRANSMISSION 15.6.6.3 ACKSTAT Status Flag Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit of the SSPxCON2 other half of a 10-bit address is accomplished by simply register is cleared when the slave has sent an writing a value to the SSPxBUF register. This action will Acknowledge (ACK=0) and is set when the slave set the Buffer Full flag bit, BF, and allow the Baud Rate does not Acknowledge (ACK=1). A slave sends an Generator to begin counting and start the next trans- Acknowledge when it has recognized its address (including a general call), or when the slave has mission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is properly received its data. asserted. SCLx is held low for one Baud Rate Genera- 15.6.6.4 Typical Transmit Sequence: tor rollover count (TBRG). Data should be valid before SCLx is released high. When the SCLx pin is released 1. The user generates a Start condition by setting high, it is held that way for TBRG. The data on the SDAx the SEN bit of the SSPxCON2 register. pin must remain stable for that duration and some hold 2. SSPxIF is set by hardware on completion of the time after the next falling edge of SCLx. After the eighth Start. bit is shifted out (the falling edge of the eighth clock), 3. SSPxIF is cleared by software. the BF flag is cleared and the master releases SDAx. 4. The MSSPx module will wait the required start This allows the slave device being addressed to time before any other operation takes place. respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received prop- 5. The user loads the SSPxBUF with the slave erly. The status of ACK is written into the ACKSTAT bit address to transmit. on the rising edge of the ninth clock. If the master 6. Address is shifted out the SDAx pin until all eight receives an Acknowledge, the Acknowledge Status bit, bits are transmitted. Transmission begins as ACKSTAT, is cleared. If not, the bit is set. After the ninth soon as SSPxBUF is written to. clock, the SSPxIF bit is set and the master clock (Baud 7. The MSSPx module shifts in the ACK bit from Rate Generator) is suspended until the next data byte the slave device and writes its value into the is loaded into the SSPxBUF, leaving SCLx low and ACKSTAT bit of the SSPxCON2 register. SDAx unchanged (Figure15-28). 8. The MSSPx module generates an interrupt at After the write to the SSPxBUF, each bit of the address the end of the ninth clock cycle by setting the will be shifted out on the falling edge of SCLx until all SSPxIF bit. seven address bits and the R/W bit are completed. On 9. The user loads the SSPxBUF with eight bits of the falling edge of the eighth clock, the master will data. release the SDAx pin, allowing the slave to respond 10. Data is shifted out the SDAx pin until all eight with an Acknowledge. On the falling edge of the ninth bits are transmitted. clock, the master will sample the SDAx pin to see if the 11. The MSSPx module shifts in the ACK bit from address was recognized by a slave. The status of the the slave device and writes its value into the ACK bit is loaded into the ACKSTAT Status bit of the ACKSTAT bit of the SSPxCON2 register. SSPxCON2 register. Following the falling edge of the 12. Steps 8-11 are repeated for all transmitted data ninth clock transmission of the address, the SSPxIF is bytes. set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes 13. The user generates a Stop or Restart condition place, holding SCLx low and allowing SDAx to float. by setting the PEN or RSEN bits of the SSPx- CON2 register. Interrupt is generated once the 15.6.6.1 BF Status Flag Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all 8 bits are shifted out. 15.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission.  2010-2016 Microchip Technology Inc. DS40001412G-page 239

 FIGURE 15-28: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 2 0 1 0 -2 0 Write SSPxCON2<0> SEN = 1 ACKSTAT in 1 6 Start condition begins SSPxCON2 = 1 M From slave, clear ACKSTAT bit SSPxCON2<6> ic SEN = 0 ro Transmitting Data or Second Half ch Transmit Address to Slave R/W = 0 of 10-bit Address ACK ip T SDAx A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0 e c h SSPxBUF written with 7-bit address and R/W no start transmit lo gy In SCLx S 1 2 3 4 5 6 7 8 9 SCLx held low 1 2 3 4 5 6 7 8 9 P c. while CPU responds to SSPxIF SSPxIF Cleared by software service routine Cleared by software from SSPx interrupt Cleared by software BF (SSPxSTAT<0>) SSPxBUF written SSPxBUF is written by software SEN After Start condition, SEN cleared by hardware P PEN I C 1 R/W 8 ( L ) F 2 D X S 4 0 / 00 4 1 4 X 1 2 G K -p a g 2 e 2 2 4 0

PIC18(L)F2X/4XK22 15.6.7 I2C MASTER MODE RECEPTION 15.6.7.4 Typical Receive Sequence: Master mode reception (Figure15-29) is enabled by 1. The user generates a Start condition by setting programming the Receive Enable bit, RCEN, of the the SEN bit of the SSPxCON2 register. SSPxCON2 register. 2. SSPxIF is set by hardware on completion of the Start. Note: The MSSPx module must be in an Idle 3. SSPxIF is cleared by software. state before the RCEN bit is set or the 4. User writes SSPxBUF with the slave address to RCEN bit will be disregarded. transmit and the R/W bit set. 5. Address is shifted out the SDAx pin until all eight The Baud Rate Generator begins counting and on each bits are transmitted. Transmission begins as rollover, the state of the SCLx pin changes (high-to-low/ soon as SSPxBUF is written to. low-to-high) and data is shifted into the SSPxSR. After 6. The MSSPx module shifts in the ACK bit from the falling edge of the eighth clock, the receive enable the slave device and writes its value into the flag is automatically cleared, the contents of the ACKSTAT bit of the SSPxCON2 register. SSPxSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate 7. The MSSPx module generates an interrupt at Generator is suspended from counting, holding SCLx the end of the ninth clock cycle by setting the low. The MSSPx is now in Idle state awaiting the next SSPxIF bit. command. When the buffer is read by the CPU, the BF 8. User sets the RCEN bit of the SSPxCON2 regis- flag bit is automatically cleared. The user can then ter and the Master clocks in a byte from the slave. send an Acknowledge bit at the end of reception by set- 9. After the 8th falling edge of SCLx, SSPxIF and ting the Acknowledge Sequence Enable bit, ACKEN, of BF are set. the SSPxCON2 register. 10. Master clears SSPxIF and reads the received byte from SSPxUF, clears BF. 15.6.7.1 BF Status Flag 11. Master sets ACK value sent to slave in ACKDT In receive operation, the BF bit is set when an address bit of the SSPxCON2 register and initiates the or data byte is loaded into SSPxBUF from SSPxSR. It ACK by setting the ACKEN bit. is cleared when the SSPxBUF register is read. 12. Masters ACK is clocked out to the slave and 15.6.7.2 SSPxOV Status Flag SSPxIF is set. 13. User clears SSPxIF. In receive operation, the SSPxOV bit is set when eight bits are received into the SSPxSR and the BF flag bit is 14. Steps 8-13 are repeated for each received byte from the slave. already set from a previous reception. 15. Master sends a not ACK or Stop to end 15.6.7.3 WCOL Status Flag communication. If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).  2010-2016 Microchip Technology Inc. DS40001412G-page 241

 FIGURE 15-29: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2 0 1 0 -2 Write to SSPxCON2<4> 0 to start Acknowledge sequence 1 6 SDAx = ACKDT (SSPxCON2<5>) = 0 M Write to SSPxCON2<0>(SEN = 1), icro begin Start condition Master configured as a receiver SADCAKx f r=o mAC MKaDsTte =r 0 Set ACKEN,S sDtaArxt A=c AknCoKwDleTd =g e1 sequence ch SEN = 0 by programming SSPxCON2<3> (RCEN = 1) ip Te sWtarirtte X tMo ISTSPxBUF occurs here, ACK from Slave RauCtoEmNa ctilceaalrleyd RneCxEt Nre c=e 1iv,e start RauCtoEmNa ctilecaalrleyd PwEritNte bni th =e r1e c h Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave n olo SDAx A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK g y Inc ACK is not sent Bteurms minaatsetesr . transfer SCLx S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Data shifted in on falling edge of CLK Set SSPxIF at end of receive Set SSPxIF interrupt Set SSPxIF interrupt at end of Acknow- at end of receive Sate et nSdS oPfx AIFc kinntoewrrluepdtge ledge sequence SSPxIF sequence Set P bit SDAx = 0, SCLx = 1 Cleared by software Cleared by software Cleared by software Cleared by software Cleared in (SSPxSTAT<4>) while CPU software and SSPxIF responds to SSPxIF BF (SSPxSTAT<0>) Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF P I C SSPxOV 1 SSPxOV is set because 8 SSPxBUF is still full ( L ACKEN ) F 2 D RCEN X S 4 0 / 00 Master configured as a receiver RCEN cleared ACK from Master RCEN cleared 4 14 by programming SSPxCON2<3> (RCEN = 1) automatically SDAx = ACKDT = 0 automatically X 1 2 G K -p a g 2 e 2 2 4 2

PIC18(L)F2X/4XK22 15.6.8 ACKNOWLEDGE SEQUENCE 15.6.9 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDAx pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN, of the bit, PEN, of the SSPxCON2 register. At the end of a SSPxCON2 register. When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDAx pin. If the user wishes to the master will assert the SDAx line low. When the generate an Acknowledge, then the ACKDT bit should SDAx line is sampled low, the Baud Rate Generator is be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate before starting an Acknowledge sequence. The Baud Generator times out, the SCLx pin will be brought high Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count) (TBRG) and the SCLx pin is deasserted (pulled high). later, the SDAx pin will be deasserted. When the SDAx When the SCLx pin is sampled high (clock arbitration), pin is sampled high while SCLx is high, the P bit of the the Baud Rate Generator counts for TBRG. The SCLx pin SSPxSTAT register is set. A TBRG later, the PEN bit is is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure15-31). matically cleared, the Baud Rate Generator is turned off 15.6.9.1 WCOL Status Flag and the MSSPx module then goes into Idle mode (Figure15-30). If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the 15.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does If the user writes the SSPxBUF when an Acknowledge not occur). sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 15-30: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPxCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDAx D0 ACK SCLx 8 9 SSPxIF Cleared in SSPxIF set at Cleared in software the end of receive software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period.  2010-2016 Microchip Technology Inc. DS40001412G-page 243

PIC18(L)F2X/4XK22 FIGURE 15-31: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPxCON2, SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG set PEN after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Falling edge of PEN bit (SSPxCON2<2>) is cleared by 9th clock hardware and the SSPxIF bit is set TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. 15.6.10 SLEEP OPERATION 15.6.12 MULTI-MASTER MODE While in Sleep mode, the I2C slave module can receive In Multi-Master mode, the interrupt generation on the addresses or data and when an address match or detection of the Start and Stop conditions allows the complete byte transfer occurs, wake the processor determination of when the bus is free. The Stop (P) and from Sleep (if the MSSPx interrupt is enabled). Start (S) bits are cleared from a Reset or when the MSSPx module is disabled. Control of the I2C bus may 15.6.11 EFFECTS OF A RESET be taken when the P bit of the SSPxSTAT register is A Reset disables the MSSPx module and terminates set, or the bus is Idle, with both the S and P bits clear. the current transfer. When the bus is busy, enabling the SSPx interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDAx line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: • Address Transfer • Data Transfer • A Start Condition • A Repeated Start Condition • An Acknowledge Condition DS40001412G-page 244  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 15.6.13 MULTI -MASTER COMMUNICATION, If a Start, Repeated Start, Stop or Acknowledge BUS COLLISION AND BUS condition was in progress when the bus collision ARBITRATION occurred, the condition is aborted, the SDAx and SCLx lines are deasserted and the respective control bits in Multi-Master mode support is achieved by bus the SSPxCON2 register are cleared. When the user arbitration. When the master outputs address/data bits services the bus collision Interrupt Service Routine and onto the SDAx pin, arbitration takes place when the if the I2C bus is free, the user can resume master outputs a ‘1’ on SDAx, by letting SDAx float high communication by asserting a Start condition. and another master asserts a ‘0’. When the SCLx pin The master will continue to monitor the SDAx and SCLx floats high, data should be stable. If the expected data on SDAx is a ‘1’ and the data sampled on the SDAx pin pins. If a Stop condition occurs, the SSPxIF bit will be set. is ‘0’, then a bus collision has taken place. The master A write to the SSPxBUF will start the transmission of will set the Bus Collision Interrupt Flag, BCLxIF, and data at the first data bit, regardless of where the reset the I2C port to its Idle state (Figure15-32). transmitter left off when the bus collision occurred. If a transmit was in progress when the bus collision In Multi-Master mode, the interrupt generation on the occurred, the transmission is halted, the BF flag is detection of Start and Stop conditions allows the cleared, the SDAx and SCLx lines are deasserted and determination of when the bus is free. Control of the I2C the SSPxBUF can be written to. When the user bus can be taken when the P bit is set in the SSPxSTAT services the bus collision Interrupt Service Routine and register, or the bus is Idle and the S and P bits are if the I2C bus is free, the user can resume cleared. communication by asserting a Start condition. FIGURE 15-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDAx. While SCLx is high, Data changes SDAx line pulled low data does not match what is driven while SCLx = 0 by another source by the master. Bus collision has occurred. SDAx released by master SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF  2010-2016 Microchip Technology Inc. DS40001412G-page 245

PIC18(L)F2X/4XK22 15.6.13.1 Bus Collision During a Start If the SDAx pin is sampled low during this count, the Condition BRG is reset and the SDAx line is asserted early (Figure15-35). If, however, a ‘1’ is sampled on the During a Start condition, a bus collision occurs if: SDAx pin, the SDAx pin is asserted low at the end of a) SDAx or SCLx are sampled low at the beginning the BRG count. The Baud Rate Generator is then of the Start condition (Figure15-33). reloaded and counts down to zero; if the SCLx pin is b) SCLx is sampled low before SDAx is asserted sampled as ‘0’ during this time, a bus collision does not low (Figure15-34). occur. At the end of the BRG count, the SCLx pin is asserted low. During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is already low, or the SCLx pin is Note: The reason that bus collision is not a fac- already low, then all of the following occur: tor during a Start condition is that no two • the Start condition is aborted, bus masters can assert a Start condition at the exact same time. Therefore, one • the BCLxIF flag is set and master will always assert SDAx before the • the MSSPx module is reset to its Idle state other. This condition does not cause a bus (Figure15-33). collision because the two masters must be The Start condition begins with the SDAx and SCLx allowed to arbitrate the first address fol- pins deasserted. When the SDAx pin is sampled high, lowing the Start condition. If the address is the Baud Rate Generator is loaded and counts down. If the same, arbitration must be allowed to the SCLx pin is sampled low while SDAx is high, a bus continue into the data portion, Repeated collision occurs because it is assumed that another Start or Stop conditions. master is attempting to drive a data ‘1’ during the Start condition. FIGURE 15-33: BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDAx = 1, SCLx = 1 SSPx module reset into Idle state. SEN SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because BCLxIF SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared by software S SSPxIF SSPxIF and BCLxIF are cleared by software DS40001412G-page 246  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 15-34: BUS COLLISION DURING START CONDITION (SCLx=0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start SCLx sequence if SDAx = 1, SCLx = 1 SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared by software S ’0’ ’0’ SSPxIF ’0’ ’0’ FIGURE 15-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Set SSPxIF Less than TBRG TBRG SDAx SDAx pulled low by other master. Reset BRG and assert SDAx. SCLx S SCLx pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 BCLxIF ’0’ S SSPxIF SDAx = 0, SCLx = 1, Interrupts cleared set SSPxIF by software  2010-2016 Microchip Technology Inc. DS40001412G-page 247

PIC18(L)F2X/4XK22 15.6.13.2 Bus Collision During a Repeated If SDAx is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure15-36). If SDAx is sampled high, the BRG is reloaded and During a Repeated Start condition, a bus collision begins counting. If SDAx goes from high-to-low before occurs if: the BRG times out, no bus collision occurs because no a) A low level is sampled on SDAx when SCLx two masters can assert SDAx at exactly the same time. goes from low level to high level (Case 1). If SCLx goes from high-to-low before the BRG times b) SCLx goes low before SDAx is asserted low, out and SDAx has not already been asserted, a bus indicating that another master is attempting to collision occurs. In this case, another master is transmit a data ‘1’ (Case 2). attempting to transmit a data ‘1’ during the Repeated When the user releases SDAx and the pin is allowed to Start condition, see Figure15-37. float high, the BRG is loaded with SSPxADD and If, at the end of the BRG time-out, both SCLx and SDAx counts down to zero. The SCLx pin is then deasserted are still high, the SDAx pin is driven low and the BRG and when sampled high, the SDAx pin is sampled. is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. FIGURE 15-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared by software S ’0’ SSPxIF ’0’ FIGURE 15-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx SCLx goes low before SDAx, BCLxIF set BCLxIF. Release SDAx and SCLx. Interrupt cleared by software RSEN ’0’ S SSPxIF DS40001412G-page 248  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 15.6.13.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low. Condition When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPxADD and a) After the SDAx pin has been deasserted and counts down to zero. After the BRG times out, SDAx is allowed to float high, SDAx is sampled low after sampled. If SDAx is sampled low, a bus collision has the BRG has timed out (Case 1). occurred. This is due to another master attempting to b) After the SCLx pin is deasserted, SCLx is drive a data ‘0’ (Figure15-38). If the SCLx pin is sampled low before SDAx goes high (Case 2). sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure15-39). FIGURE 15-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDAx sampled low after TBRG, set BCLxIF SDAx SDAx asserted low SCLx PEN BCLxIF P ’0’ SSPxIF ’0’ FIGURE 15-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes low before SDAx goes high, Assert SDAx set BCLxIF SCLx PEN BCLxIF P ’0’ SSPxIF ’0’  2010-2016 Microchip Technology Inc. DS40001412G-page 249

PIC18(L)F2X/4XK22 TABLE 15-2: REGISTERS ASSOCIATED WITH I2C OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 149 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1(1) ANSB0(1) 150 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1(2) ANSD0(2) 150 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 SSP1ADD SSP1 Address Register in I2C Slave mode. SSP1 Baud Rate Reload Register in I2C Master mode. 258 SSP1BUF SSP1 Receive Buffer/Transmit Register — SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 253 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 255 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 256 SSP1MSK SSP1 MASK Register bits 257 SSP1STAT SMP CKE D/A P S R/W UA BF 252 SSP2ADD SSP2 Address Register in I2C Slave mode. SSP2 Baud Rate Reload Register in I2C Master mode. 258 SSP2BUF SSP2 Receive Buffer/Transmit Register — SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 253 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 255 SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 256 SSP2MSK SSP1 MASK Register bits 257 SSP2STAT SMP CKE D/A P S R/W UA BF 252 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1(1) TRISB0(1) 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1(2) TRISD0(2) 151 Legend: Shaded bits are not used by the MSSPx in I2C mode. Note 1: PIC18(L)F2XK22 devices. 2: PIC18(L)F4XK22 devices. DS40001412G-page 250  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 15.7 Baud Rate Generator This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is The MSSPx module has a Baud Rate Generator asserted depends on the mode the MSSPx is being available for clock generation in both I2C and SPI operated in. Master modes. The Baud Rate Generator (BRG) Table15-3 demonstrates clock rates based on reload value is placed in the SSPxADD register instruction cycles and the BRG value loaded into (Register15-7). When a write occurs to SSPxBUF, the SSPxADD. Baud Rate Generator will automatically begin counting down. EQUATION 15-1: FCLOCK FORMULA Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will FOSC remain in its last state. FCLOCK = ------------------------------------------------- SSPxADD+14 An internal signal “Reload” in Figure15-40 triggers the value from SSPxADD to be loaded into the BRG counter. FIGURE 15-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPxM<3:0> SSPxADD<7:0> SSPxM<3:0> Reload Reload SCLx Control SSPxCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 15-3: MSSPx CLOCK RATE W/BRG FCLOCK FOSC FCY BRG Value (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz(1) 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application.  2010-2016 Microchip Technology Inc. DS40001412G-page 251

PIC18(L)F2X/4XK22 15.8 Register Definitions: MSSP Control REGISTER 15-2: SSPxSTAT: SSPx STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I 2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I 2 C mode only: 1 = Enable input logic so that thresholds are compliant with SMbus specification 0 = Disable SMbus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I 2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty DS40001412G-page 252  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 15-3: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0 R/C/HS-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPxOV SSPxEN CKP SSPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPxOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new recep- tion (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software). 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPxEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I 2 C Slave mode: SCLx release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C Master mode: Unused in this mode  2010-2016 Microchip Technology Inc. DS40001412G-page 253

PIC18(L)F2X/4XK22 REGISTER 15-3: SSPxCON1: SSPx CONTROL REGISTER 1 (CONTINUED) bit 3-0 SSPxM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPxADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1)) 1011 = I2C firmware controlled Master mode (slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: When enabled, the SDAx and SCLx pins must be configured as inputs. 4: SSPxADD values of 0, 1 or 2 are not supported for I2C mode. DS40001412G-page 254  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 15-4: SSPxCON2: SSPx CONTROL REGISTER 2 R/W-0 R-0 R/W-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/W/HC-0 GCEN ACKSTAT ACKDT ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN(1): Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN(1): Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN(1): Stop Condition Enable bit (in I2C Master mode only) SCKx Release Control: 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN(1): Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN(1): Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).  2010-2016 Microchip Technology Inc. DS40001412G-page 255

PIC18(L)F2X/4XK22 REGISTER 15-5: SSPxCON3: SSPx CONTROL REGISTER 3 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCLx clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCLx clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPxOV bit of the SSPxCON1 register is set, and the buffer is not updated In I2C Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPxOV bit only if the BF bit = 0. 0 = SSPxBUF is only updated when SSPxOV is clear bit 3 SDAHT: SDAx Hold Time Selection bit (I2C mode only) 1 = Minimum of 300ns hold time on SDAx after the falling edge of SCLx 0 = Minimum of 100ns hold time on SDAx after the falling edge of SCLx bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the BCLxIF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the SSPx- CON1 register will be cleared and the SCLx will be held low. 0 = Address holding is disabled Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still set when a new byte is received and BF=1, but hardware continues to write the most recent byte to SSPxBUF. 2: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as enabled. 3: The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set. DS40001412G-page 256  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 15-5: SSPxCON3: SSPx CONTROL REGISTER 3 (CONTINUED) bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCLx is held low. 0 = Data holding is disabled Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still set when a new byte is received and BF=1, but hardware continues to write the most recent byte to SSPxBUF. 2: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as enabled. 3: The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set. REGISTER 15-6: SSPxMSK: SSPx MASK REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPxM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored  2010-2016 Microchip Technology Inc. DS40001412G-page 257

PIC18(L)F2X/4XK22 REGISTER 15-7: SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCLx pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode — Least Significant Address byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. DS40001412G-page 258  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 16.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer • Half-duplex synchronous master independent of device program execution. The • Half-duplex synchronous slave EUSART, also known as a Serial Communications • Programmable clock and data polarity Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous The EUSART module implements the following system. Full-Duplex mode is useful for additional features, making it ideally suited for use in communications with peripheral systems, such as CRT Local Interconnect Network (LIN) bus systems: terminals and personal computers. Half-Duplex • Automatic detection and calibration of the baud rate Synchronous mode is intended for communications • Wake-up on Break reception with peripheral devices, such as A/D or D/A integrated • 13-bit Break character transmit circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for Block diagrams of the EUSART transmitter and baud rate generation and require the external clock receiver are shown in Figure16-1 and Figure16-2. signal provided by a master synchronous device. FIGURE 16-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIE Interrupt TXREGx Register TXxIF 8 MSb LSb TXx/CKx pin (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT Baud Rate Generator FOSC ÷ n TX9 BRG16 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 X 0 0 0 SPBRGHx SPBRGx BRGH X 1 1 0 0 BRG16 X 1 0 1 0  2010-2016 Microchip Technology Inc. DS40001412G-page 259

PIC18(L)F2X/4XK22 FIGURE 16-2: EUSART RECEIVE BLOCK DIAGRAM CREN OERR RCIDL RXx/DTx pin MSb RSR Register LSb Panind BCuoffnetrrol DReactaovery Stop (8) 7 • • • 1 0 START Baud Rate Generator FOSC RX9 ÷ n BRG16 n + 1 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 FIFO SPBRGHx SPBRGx BRGH X 1 1 0 0 FERR RX9D RCREGx Register BRG16 X 1 0 1 0 8 Data Bus RCxIF Interrupt RCxIE The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTAx) • Receive Status and Control (RCSTAx) • Baud Rate Control (BAUDCONx) These registers are detailed in Register16-1, Register16-2 and Register16-3, respectively. For all modes of EUSART operation, the TRIS control bits corresponding to the RXx/DTx and TXx/CKx pins should be set to ‘1’. The EUSART control will automatically reconfigure the pin from input to output, as needed. When the receiver or transmitter section is not enabled then the corresponding RXx/DTx or TXx/CKx pin may be used for general purpose input and output. DS40001412G-page 260  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 16.1 EUSART Asynchronous Mode 16.1.1.2 Transmitting Data The EUSART transmits and receives data using the A transmission is initiated by writing a character to the standard non-return-to-zero (NRZ) format. NRZ is TXREGx register. If this is the first character, or the implemented with two levels: a VOH Mark state which previous character has been completely flushed from represents a ‘1’ data bit, and a VOL Space state which the TSR, the data in the TXREGx is immediately represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains consecutively transmitted data bits of the same value all or part of a previous character, the new character stay at the output level of that bit without returning to a data is held in the TXREGx until the Stop bit of the neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending transmission port idles in the Mark state. Each character character in the TXREGx is then transferred to the TSR transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits or nine data bits and is always terminated by one or and Stop bit sequence commences immediately more Stop bits. The Start bit is always a space and the following the transfer of the data to the TSR from the Stop bits are always marks. The most common data TXREGx. format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16- 16.1.1.3 Transmit Data Polarity bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See The polarity of the transmit data can be controlled with Table16-5 for examples of baud rate configurations. the CKTXP bit of the BAUDCONx register. The default state of this bit is ‘0’ which selects high true transmit The EUSART transmits and receives the LSb first. The idle and data bits. Setting the CKTXP bit to ‘1’ will invert EUSART’s transmitter and receiver are functionally the transmit data resulting in low true idle and data bits. independent, but share the same data format and baud The CKTXP bit controls transmit data polarity only in rate. Parity is not supported by the hardware, but can Asynchronous mode. In Synchronous mode the be implemented in software and stored as the ninth CKTXP bit has a different function. data bit. 16.1.1.4 Transmit Interrupt Flag 16.1.1 EUSART ASYNCHRONOUS TRANSMITTER The TXxIF interrupt flag bit of the PIR1/PIR3 register is set whenever the EUSART transmitter is enabled and The EUSART transmitter block diagram is shown in no character is being held for transmission in the Figure16-1. The heart of the transmitter is the serial TXREGx. In other words, the TXxIF bit is only clear Transmit Shift Register (TSR), which is not directly when the TSR is busy with a character and a new accessible by software. The TSR obtains its data from character has been queued for transmission in the the transmit buffer, which is the TXREGx register. TXREGx. The TXxIF flag bit is not cleared immediately 16.1.1.1 Enabling the Transmitter upon writing TXREGx. TXxIF becomes valid in the second instruction cycle following the write execution. The EUSART transmitter is enabled for asynchronous Polling TXxIF immediately following the TXREGx write operations by configuring the following three control will return invalid results. The TXxIF bit is read-only, it bits: cannot be set or cleared by software. • TXEN = 1 The TXxIF interrupt can be enabled by setting the • SYNC = 0 TXxIE interrupt enable bit of the PIE1/PIE3 register. • SPEN = 1 However, the TXxIF flag bit will be set whenever the TXREGx is empty, regardless of the state of TXxIE All other EUSART control bits are assumed to be in enable bit. their default state. To use interrupts when transmitting data, set the TXxIE Setting the TXEN bit of the TXSTAx register enables the bit only when there is more data to send. Clear the transmitter circuitry of the EUSART. Clearing the SYNC TXxIE interrupt enable bit upon writing the last bit of the TXSTAx register configures the EUSART for character of the transmission to the TXREGx. asynchronous operation. Setting the SPEN bit of the RCSTAx register enables the EUSART and automatically configures the TXx/CKx I/O pin as an output. If the TXx/CKx pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: The TXxIF transmitter interrupt flag is set when the TXEN enable bit is set.  2010-2016 Microchip Technology Inc. DS40001412G-page 261

PIC18(L)F2X/4XK22 16.1.1.5 TSR Status 16.1.1.7 Asynchronous Transmission Setup: The TRMT bit of the TXSTAx register indicates the 1. Initialize the SPBRGHx:SPBRGx register pair status of the TSR register. This is a read-only bit. The and the BRGH and BRG16 bits to achieve the TRMT bit is set when the TSR register is empty and is desired baud rate (see Section16.4 “EUSART cleared when a character is transferred to the TSR Baud Rate Generator (BRG)”). register from the TXREGx. The TRMT bit remains clear 2. Set the RXx/DTx and TXx/CKx TRIS controls to until all bits have been shifted out of the TSR register. ‘1’. No interrupt logic is tied to this bit, so the user needs to 3. Enable the asynchronous serial port by clearing poll this bit to determine the TSR status. the SYNC bit and setting the SPEN bit. 4. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that Note: The TSR register is not mapped in data the eight Least Significant data bits are an memory, so it is not available to the user. address when the receiver is set for address detection. 5. Set the CKTXP control bit if inverted transmit 16.1.1.6 Transmitting 9-Bit Characters data polarity is desired. The EUSART supports 9-bit character transmissions. 6. Enable the transmission by setting the TXEN When the TX9 bit of the TXSTAx register is set the control bit. This will cause the TXxIF interrupt bit EUSART will shift nine bits out for each character to be set. transmitted. The TX9D bit of the TXSTAx register is the 7. If interrupts are desired, set the TXxIE interrupt ninth, and Most Significant, data bit. When transmitting enable bit. An interrupt will occur immediately 9-bit data, the TX9D data bit must be written before provided that the GIE/GIEH and PEIE/GIEL bits writing the eight Least Significant bits into the TXREGx. of the INTCON register are also set. All nine bits of data will be transferred to the TSR shift 8. If 9-bit transmission is selected, the ninth bit register immediately after the TXREGx is written. should be loaded into the TX9D data bit. A special 9-bit Address mode is available for use with 9. Load 8-bit data into the TXREGx register. This multiple receivers. See Section16.1.2.8 “Address will start the transmission. Detection” for more information on the Address mode. FIGURE 16-3: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx/CKxpin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) DS40001412G-page 262  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx/CKx pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXxIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY TRMT bit Word 1 Word 2 Reg(T. rEamnspmtyi tF Slahgif)t Transmit Shift Reg Transmit Shift Reg Note: This timing diagram shows two consecutive transmissions. TABLE 16-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — TXREG1 EUSART1 Transmit Register — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 TXREG2 EUSART2 Transmit Register — TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission.  2010-2016 Microchip Technology Inc. DS40001412G-page 263

PIC18(L)F2X/4XK22 16.1.2 EUSART ASYNCHRONOUS 16.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode would typically be used in reception on the falling edge of the first bit. The first bit, RS-232 systems. The receiver block diagram is shown also known as the Start bit, is always a zero. The data in Figure16-2. The data is received on the RXx/DTx recovery circuit counts one-half bit time to the center of pin and drives the data recovery block. The data the Start bit and verifies that the bit is still a zero. If it is recovery block is actually a high-speed shifter not a zero then the data recovery circuit aborts operating at 16 times the baud rate, whereas the serial character reception, without generating an error, and Receive Shift Register (RSR) operates at the bit rate. resumes looking for the falling edge of the Start bit. If When all eight or nine bits of the character have been the Start bit zero verification succeeds then the data shifted in, they are immediately transferred to a two recovery circuit counts a full bit time to the center of the character First-In-First-Out (FIFO) memory. The FIFO next bit. The bit is then sampled by a majority detect buffering allows reception of two complete characters circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. and the start of a third character before software must This repeats until all data bits have been sampled and start servicing the EUSART receiver. The FIFO and shifted into the RSR. One final bit time is measured and RSR registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always Access to the received data is via the RCREGx a ‘1’. If the data recovery circuit samples a ‘0’ in the register. Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this 16.1.2.1 Enabling the Receiver character. See Section16.1.2.5 “Receive Framing Error” for more information on framing errors. The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred • CREN = 1 to the EUSART receive FIFO and the RCxIF interrupt • SYNC = 0 flag bit of the PIR1/PIR3 register is set. The top • SPEN = 1 character in the FIFO is transferred out of the FIFO by All other EUSART control bits are assumed to be in reading the RCREGx register. their default state. Setting the CREN bit of the RCSTAx register enables Note: If the receive FIFO is overrun, no additional the receiver circuitry of the EUSART. Clearing the characters will be received until the overrun SYNC bit of the TXSTAx register configures the condition is cleared. See Section16.1.2.6 EUSART for asynchronous operation. Setting the “Receive Overrun Error” for more SPEN bit of the RCSTAx register enables the information on overrun errors. EUSART. The RXx/DTx I/O pin must be configured as an input by setting the corresponding TRIS control bit. If the RXx/DTx pin is shared with an analog peripheral the analog I/O function must be disabled by clearing 16.1.2.3 Receive Data Polarity the corresponding ANSEL bit. The polarity of the receive data can be controlled with the DTRXP bit of the BAUDCONx register. The default state of this bit is ‘0’ which selects high true receive idle and data bits. Setting the DTRXP bit to ‘1’ will invert the receive data resulting in low true idle and data bits. The DTRXP bit controls receive data polarity only in Asynchronous mode. In Synchronous mode the DTRXP bit has a different function. DS40001412G-page 264  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 16.1.2.4 Receive Interrupts 16.1.2.6 Receive Overrun Error The RCxIF interrupt flag bit of the PIR1/PIR3 register is The receive FIFO buffer can hold two characters. An set whenever the EUSART receiver is enabled and overrun error will be generated if a third character, in its there is an unread character in the receive FIFO. The entirety, is received before the FIFO is accessed. When RCxIF interrupt flag bit is read-only, it cannot be set or this happens the OERR bit of the RCSTAx register is cleared by software. set. The characters already in the FIFO buffer can be read but no additional characters will be received until RCxIF interrupts are enabled by setting the following the error is cleared. The error must be cleared by either bits: clearing the CREN bit of the RCSTAx register or by • RCxIE interrupt enable bit of the PIE1/PIE3 resetting the EUSART by clearing the SPEN bit of the register RCSTAx register. • PEIE/GIEL peripheral interrupt enable bit of the INTCON register 16.1.2.7 Receiving 9-bit Characters • GIE/GIEH global interrupt enable bit of the The EUSART supports 9-bit character reception. When INTCON register the RX9 bit of the RCSTAx register is set, the EUSART The RCxIF interrupt flag bit will be set when there is an will shift nine bits into the RSR for each character unread character in the FIFO, regardless of the state of received. The RX9D bit of the RCSTAx register is the interrupt enable bits. ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data 16.1.2.5 Receive Framing Error from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits Each character in the receive FIFO buffer has a from the RCREGx. corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected 16.1.2.8 Address Detection time. The framing error status is accessed via the FERR bit of the RCSTAx register. The FERR bit A special Address Detection mode is available for use represents the status of the top unread character in the when multiple receivers share the same transmission receive FIFO. Therefore, the FERR bit must be read line, such as in RS-485 systems. Address detection is before reading the RCREG.x enabled by setting the ADDEN bit of the RCSTAx register. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error Address detection requires 9-bit character reception. (FERR = 1) does not preclude reception of additional When address detection is enabled, only characters characters. It is not necessary to clear the FERR bit. with the ninth data bit set will be transferred to the Reading the next character from the FIFO buffer will receive FIFO buffer, thereby setting the RCxIF interrupt advance the FIFO to the next character and the next bit. All other characters will be ignored. corresponding framing error. Upon receiving an address character, user software The FERR bit can be forced clear by clearing the SPEN determines if the address matches its own. Upon bit of the RCSTAx register which resets the EUSART. address match, user software must disable address Clearing the CREN bit of the RCSTAx register does not detection by clearing the ADDEN bit before the next affect the FERR bit. A framing error by itself does not Stop bit occurs. When user software detects the end of generate an interrupt. the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREGx will not clear the FERR bit.  2010-2016 Microchip Technology Inc. DS40001412G-page 265

PIC18(L)F2X/4XK22 16.1.2.9 Asynchronous Reception Setup: 16.1.2.10 9-bit Address Detection Mode Setup 1. Initialize the SPBRGHx:SPBRGx register pair This mode would typically be used in RS-485 systems. and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section16.4 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGHx, SPBRGx register pair 2. Set the RXx/DTx and TXx/CKx TRIS controls to and the BRGH and BRG16 bits to achieve the ‘1’. desired baud rate (see Section16.4 “EUSART 3. Enable the serial port by setting the SPEN bit Baud Rate Generator (BRG)”). and the RXx/DTx pin TRIS bit. The SYNC bit 2. Set the RXx/DTx and TXx/CKx TRIS controls to must be clear for asynchronous operation. ‘1’. 4. If interrupts are desired, set the RCxIE interrupt 3. Enable the serial port by setting the SPEN bit. enable bit and set the GIE/GIEH and PEIE/GIEL The SYNC bit must be clear for asynchronous bits of the INTCON register. operation. 5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCxIE interrupt 6. Set the DTRXP if inverted receive polarity is enable bit and set the GIE/GIEH and PEIE/GIEL desired. bits of the INTCON register. 7. Enable reception by setting the CREN bit. 5. Enable 9-bit reception by setting the RX9 bit. 8. The RCxIF interrupt flag bit will be set when a 6. Enable address detection by setting the ADDEN character is transferred from the RSR to the bit. receive buffer. An interrupt will be generated if 7. Set the DTRXP if inverted receive polarity is the RCxIE interrupt enable bit was also set. desired. 9. Read the RCSTAx register to get the error flags 8. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 9. The RCxIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 10. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREGx will be generated if the RCxIE interrupt enable register. bit was also set. 11. If an overrun occurred, clear the OERR flag by 10. Read the RCSTAx register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 11. Get the received eight Least Significant data bits from the receive buffer by reading the RCREGx register. Software determines if this is the device’s address. 12. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 13. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. DS40001412G-page 266  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 16-5: ASYNCHRONOUS RECEPTION Start Start Start RXx/DTx pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 RCREGx RCREGx RCIDL Read Rcv Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx/DTx input. The RCREGx (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. TABLE 16-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 RCREG1 EUSART1 Receive Register — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 RCREG2 EUSART2 Receive Register — RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 150 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception. Note 1: PIC18(L)F4XK22 devices. 2: PIC18(L)F2XK22 devices.  2010-2016 Microchip Technology Inc. DS40001412G-page 267

PIC18(L)F2X/4XK22 16.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section2.6 “Internal Clock Modes” for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section16.4.1 “Auto- Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. DS40001412G-page 268  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 16.3 Register Definitions: EUSART Control REGISTER 16-1: TxSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2010-2016 Microchip Technology Inc. DS40001412G-page 269

PIC18(L)F2X/4XK22 REGISTER 16-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREGx register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001412G-page 270  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 16-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been detected and the receiver is active Synchronous mode: Don’t care bit 5 DTRXP: Data/Receive Polarity Select bit Asynchronous mode: 1 = Receive data (RXx) is inverted (active-low) 0 = Receive data (RXx) is not inverted (active-high) Synchronous mode: 1 = Data (DTx) is inverted (active-low) 0 = Data (DTx) is not inverted (active-high) bit 4 CKTXP: Clock/Transmit Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TXx) is low 0 = Idle state for transmit (TXx) is high Synchronous mode: 1 = Data changes on the falling edge of the clock and is sampled on the rising edge of the clock 0 = Data changes on the rising edge of the clock and is sampled on the falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used (SPBRGHx:SPBRGx) 0 = 8-bit Baud Rate Generator is used (SPBRGx) bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received but RCxIF will be set on the falling edge. WUE will automatically clear on the rising edge. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2010-2016 Microchip Technology Inc. DS40001412G-page 271

PIC18(L)F2X/4XK22 16.4 EUSART Baud Rate Generator If the system clock is changed during an active receive (BRG) operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to The Baud Rate Generator (BRG) is an 8-bit or 16-bit make sure that the receive operation is Idle before timer that is dedicated to the support of both the changing the system clock. asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the EXAMPLE 16-1: CALCULATING BAUD BRG16 bit of the BAUDCONx register selects 16-bit RATE ERROR mode. For a device with FOSC of 16 MHz, desired baud rate The SPBRGHx:SPBRGx register pair determines the of 9600, Asynchronous mode, 8-bit BRG: period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate Desired Baud Rate = -------------------------------F----O----S--C--------------------------------- 64[SPBRGHx:SPBRGx]+1 period is determined by both the BRGH bit of the TXSTAx register and the BRG16 bit of the BAUDCONx Solving for SPBRGHx:SPBRGx: register. In Synchronous mode, the BRGH bit is ignored. FOSC --------------------------------------------- Table16-3 contains the formulas for determining the Desired Baud Rate X = ---------------------------------------------–1 baud rate. Example16-1 provides a sample calculation 64 for determining the baud rate and baud rate error. 16000000 ------------------------ Typical baud rates and error values for various 9600 = ------------------------–1 Asynchronous modes have been computed for your 64 convenience and are shown in Table16-5. It may be = 25.042 = 25 advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate Calculated Baud Rate = --1---6---0---0---0---0---0---0---- 6425+1 error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. = 9615 Writing a new value to the SPBRGHx, SPBRGx Calc. Baud Rate–Desired Baud Rate register pair causes the BRG timer to be reset (or Error = -------------------------------------------------------------------------------------------- Desired Baud Rate cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. 9615–9600 = ---------------------------------- = 0.16% 9600 TABLE 16-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGHx, SPBRGx register pair. DS40001412G-page 272  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 16-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the BRG. TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRxG SPBRGx SPBRGx SPBRGx Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 — — — 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9615 0.16 103 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 95 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.23k 0.16 51 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k 58.82k 2.12 16 57.60k 0.00 7 — — — 57.60k 0.00 2 115.2k 111.11k -3.55 8 — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRGx SPBRGx SPBRGx SPBRGx Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — —  2010-2016 Microchip Technology Inc. DS40001412G-page 273

PIC18(L)F2X/4XK22 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRGx SPBRGx SPBRGx SPBRGx Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 — — — 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 — — — 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 207 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.97k 0.64 68 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 114.29k -0.79 34 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5 SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRGx SPBRGx SxBRGx SPBRGx Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRGHx: SPBRGHx: SPBRGHx SPBRGHx: Actual % Actual % Actual % Actual % SPBRGx SPBRGx :SPBRGx SPBRGx Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 13332 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200.1 0.01 3332 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.02 1666 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9592 -0.08 416 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 383 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 207 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.97k 0.64 68 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 114.29k -0.79 34 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 DS40001412G-page 274  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRGHx: SPBRGHx: SPBRGHx SPBRGHx: Actual % Actual % Actual % Actual % SPBRGx SPBRGx :SPBRGx SPBRGx Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRGHx: SPBRGHx: SPBRGHx SPBRGHx: Actual % Actual % Actual % Actual % SPBRGx SPBRGx :SPBRGx SPBRGx Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300 0.00 53332 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 0.00 13332 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.00 6666 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9598.1 -0.02 1666 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 1535 10425 0.08 441 10417 0.00 383 10433 0.16 264 19.2k 19.21k 0.04 832 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.55k -0.08 277 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 115.11k -0.08 138 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRGHx: SPBRGHx: SPBRGHx SPBRGHx: Actual % Actual % Actual % Actual % SPBRGx SPBRGx :SPBRGx SPBRGx Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —  2010-2016 Microchip Technology Inc. DS40001412G-page 275

PIC18(L)F2X/4XK22 16.4.1 AUTO-BAUD DETECT and SPBRGx registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the Note1: If the WUE bit is set with the ABDEN bit, incoming RXx signal, the RXx signal is timing the BRG. auto-baud detection will occur on the byte The Baud Rate Generator is used to time the period of following the Break character (see a received 55h (ASCII “U”) which is the Sync character Section16.4.3 “Auto-Wake-up on for the LIN bus. The unique feature of this character is Break”). that it has five rising edges including the Stop bit edge. 2: It is up to the user to determine that the Setting the ABDEN bit of the BAUDCONx register incoming character baud rate is within the starts the auto-baud calibration sequence range of the selected BRG clock source. (Section16.4.2 “Auto-baud Overflow”). While the Some combinations of oscillator frequency ABD sequence takes place, the EUSART state and EUSART baud rates are not possible. machine is held in Idle. On the first rising edge of the 3: During the auto-baud process, the auto- receive line, after the Start bit, the SPBRGx begins baud counter starts counting at one. Upon counting up using the BRG counter clock as shown in completion of the auto-baud sequence, to Table16-6. The fifth rising edge will occur on the RXx/ achieve maximum accuracy, subtract one DTx pin at the end of the eighth bit period. At that time, from the SPBRGHx:SPBRGx register pair. an accumulated value totaling the proper BRG period is left in the SPBRGHx:SPBRGx register pair, the ABDEN bit is automatically cleared, and the RCxIF TABLE 16-6: BRG COUNTER CLOCK interrupt flag is set. A read operation on the RCREGx RATES needs to be performed to clear the RCxIF interrupt. RCREGx content should be discarded. When BRG Base BRG ABD BRG16 BRGH calibrating for modes that do not use the SPBRGHx Clock Clock register the user can verify that the SPBRGx register 0 0 FOSC/64 FOSC/512 did not overflow by checking for 00h in the SPBRGHx register. 0 1 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 1 0 FOSC/16 FOSC/128 and BRGH bits as shown in Table16-6. During ABD, 1 1 FOSC/4 FOSC/32 both the SPBRGHx and SPBRGx registers are used as Note: During the ABD sequence, SPBRGx and a 16-bit counter, independent of the BRG16 bit setting. SPBRGHx registers are both used as a While calibrating the baud rate period, the SPBRGHx 16-bit counter, independent of BRG16 setting. FIGURE 16-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RXx/DTx pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCxIF bit (Interrupt) Read RCREGx SPBRGx XXh 1Ch SPBRGHx XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. DS40001412G-page 276  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 16.4.2 AUTO-BAUD OVERFLOW 16.4.3.1 Special Considerations During the course of automatic baud detection, the Break Character ABDOVF bit of the BAUDCONx register will be set if the To avoid character errors or character fragments during baud rate counter overflows before the fifth rising edge a wake-up event, the wake-up character must be all is detected on the RX pin. The ABDOVF bit indicates zeros. that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGHx:SPBRGx register When the wake-up is enabled the function works pair. After the ABDOVF has been set, the counter con- independent of the low time on the data stream. If the tinues to count until the fifth rising edge is detected on WUE bit is set and a valid non-zero character is the RXx/DTx pin. Upon detecting the fifth RXx/DTx received, the low time from the Start bit to the first rising edge, the hardware will set the RCxIF interrupt flag and edge will be interpreted as the wake-up event. The clear the ABDEN bit of the BAUDCONx register. The remaining bits in the character will be received as a RCxIF flag can be subsequently cleared by reading the fragmented character and subsequent characters can RCREGx. The ABDOVF flag can be cleared by soft- result in framing or overrun errors. ware directly. Therefore, the initial character in the transmission must To terminate the auto-baud process before the RCxIF be all ‘0’s. This must be 10 or more bit times, 13-bit flag is set, clear the ABDEN bit then clear the ABDOVF times recommended for LIN bus, or any number of bit bit. The ABDOVF bit will remain set if the ABDEN bit is times for standard RS-232 devices. not cleared first. Oscillator Start-up Time Oscillator start-up time must be considered, especially 16.4.3 AUTO-WAKE-UP ON BREAK in applications using oscillators with longer start-up During Sleep mode, all clocks to the EUSART are intervals (i.e., LP, XT or HS/PLL mode). The Sync suspended. Because of this, the Baud Rate Generator Break (or wake-up signal) character must be of is inactive and a proper character reception cannot be sufficient length, and be followed by a sufficient performed. The Auto-Wake-up feature allows the interval, to allow enough time for the selected oscillator controller to wake-up due to activity on the RXx/DTx to start and provide proper initialization of the EUSART. line. This feature is available only in Asynchronous WUE Bit mode. The wake-up event causes a receive interrupt by The Auto-Wake-up feature is enabled by setting the setting the RCxIF bit. The WUE bit is cleared by WUE bit of the BAUDCONx register. Once set, the hardware by a rising edge on RXx/DTx. The interrupt normal receive sequence on RXx/DTx is disabled, and condition is then cleared by software by reading the the EUSART remains in an Idle state, monitoring for a RCREGx register and discarding its contents. wake-up event independent of the CPU mode. A wake- up event consists of a high-to-low transition on the To ensure that no actual data is lost, check the RCIDL RXx/DTx line. (This coincides with the start of a Sync bit to verify that a receive operation is not in process Break or a wake-up signal character for the LIN before setting the WUE bit. If a receive operation is not protocol.) occurring, the WUE bit may then be set just prior to entering the Sleep mode. The EUSART module generates an RCxIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure16-7), and asynchronously if the device is in Sleep mode (Figure16-8). The interrupt condition is cleared by reading the RCREGx register. The WUE bit is automatically cleared by the low-to-high transition on the RXx line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.  2010-2016 Microchip Technology Inc. DS40001412G-page 277

PIC18(L)F2X/4XK22 FIGURE 16-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto Cleared WUE bit RXx/DTx Line RCxIF Cleared due to User Read of RCREGx Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 16-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RXx/DTx Line Note 1 RCxIF Cleared due to User Read of RCREGx Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. DS40001412G-page 278  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 16.4.4 BREAK CHARACTER SEQUENCE When the TXREGx becomes empty, as indicated by the TXxIF, the next data byte can be written to The EUSART module has the capability of sending the TXREGx. special Break character sequences that are required by the LIN bus standard. A Break character consists of a 16.4.5 RECEIVING A BREAK CHARACTER Start bit, followed by 12 ‘0’ bits and a Stop bit. The Enhanced EUSART module can receive a Break To send a Break character, set the SENDB and TXEN character in two ways. bits of the TXSTAx register. The Break character trans- mission is then initiated by a write to the TXREGx. The The first method to detect a Break character uses the value of data written to TXREGx will be ignored and all FERR bit of the RCSTAx register and the Received ‘0’s will be transmitted. data as indicated by RCREGx. The Baud Rate Generator is assumed to have been initialized to the The SENDB bit is automatically reset by hardware after expected baud rate. the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte A Break character has been received when; following the Break character (typically, the Sync • RCxIF bit is set character in the LIN specification). • FERR bit is set The TRMT bit of the TXSTAx register indicates when the • RCREGx = 00h transmit operation is active or Idle, just as it does during The second method uses the Auto-Wake-up feature normal transmission. See Figure16-9 for the timing of described in Section16.4.3 “Auto-Wake-up on the Break character sequence. Break”. By enabling this feature, the EUSART will 16.4.4.1 Break and Sync Transmit Sequence sample the next two transitions on RXx/DTx, cause an RCxIF interrupt, and receive the next data byte The following sequence will start a message frame followed by another interrupt. header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus Note that following a Break character, the user will master. typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of 1. Configure the EUSART for the desired mode. the BAUDCONx register before placing the EUSART in 2. Set the TXEN and SENDB bits to enable the Sleep mode. Break sequence. 3. Load the TXREGx with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREGx to load the Sync charac- ter into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. FIGURE 16-9: SEND BREAK CHARACTER SEQUENCE Write to TXREGx Dummy Write BRG Output (Shift Clock) TXx/CKx (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXxIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit)  2010-2016 Microchip Technology Inc. DS40001412G-page 279

PIC18(L)F2X/4XK22 16.5 EUSART Synchronous Mode 16.5.1.2 Clock Polarity Synchronous serial communications are typically used A clock polarity option is provided for Microwire in systems with a single master and one or more compatibility. Clock polarity is selected with the CKTXP slaves. The master device contains the necessary bit of the BAUDCONx register. Setting the CKTXP bit circuitry for baud rate generation and supplies the clock sets the clock Idle state as high. When the CKTXP bit for all devices in the system. Slave devices can take is set, the data changes on the falling edge of each advantage of the master clock by eliminating the clock and is sampled on the rising edge of each clock. internal clock generation circuitry. Clearing the CKTXP bit sets the Idle state as low. When the CKTXP bit is cleared, the data changes on the There are two signal lines in Synchronous mode: a rising edge of each clock and is sampled on the falling bidirectional data line and a clock line. Slaves use the edge of each clock. external clock supplied by the master to shift the serial data into and out of their respective receive and 16.5.1.3 Synchronous Master Transmission transmit shift registers. Since the data line is Data is transferred out of the device on the RXx/DTx bidirectional, synchronous operation is half-duplex pin. The RXx/DTx and TXx/CKx pin output drivers are only. Half-duplex refers to the fact that master and automatically enabled when the EUSART is configured slave devices can receive and transmit data but not for synchronous master transmit operation. both simultaneously. The EUSART can operate as either a master or slave device. A transmission is initiated by writing a character to the TXREGx register. If the TSR still contains all or part of Start and Stop bits are not used in synchronous a previous character the new character data is held in transmissions. the TXREGx until the last bit of the previous character 16.5.1 SYNCHRONOUS MASTER MODE has been transmitted. If this is the first character, or the previous character has been completely flushed from The following bits are used to configure the EUSART the TSR, the data in the TXREGx is immediately trans- for Synchronous Master operation: ferred to the TSR. The transmission of the character • SYNC = 1 commences immediately following the transfer of the • CSRC = 1 data to the TSR from the TXREGx. • SREN = 0 (for transmit); SREN = 1 (for receive) Each data bit changes on the leading edge of the • CREN = 0 (for transmit); CREN = 1 (for receive) master clock and remains valid until the subsequent leading clock edge. • SPEN = 1 Setting the SYNC bit of the TXSTAx register configures the device for synchronous operation. Setting the CSRC Note: The TSR register is not mapped in data bit of the TXSTAx register configures the device as a memory, so it is not available to the user. master. Clearing the SREN and CREN bits of the RCSTAx register ensures that the device is in the Transmit mode, otherwise the device will be configured 16.5.1.4 Data Polarity to receive. Setting the SPEN bit of the RCSTAx register enables the EUSART. If the RXx/DTx or TXx/CKx pins The polarity of the transmit and receive data can be are shared with an analog peripheral the analog I/O controlled with the DTRXP bit of the BAUDCONx functions must be disabled by clearing the corresponding register. The default state of this bit is ‘0’ which selects ANSEL bits. high true transmit and receive data. Setting the DTRXP bit to ‘1’ will invert the data resulting in low true transmit The TRIS bits corresponding to the RXx/DTx and and receive data. TXx/CKx pins should be set. 16.5.1.1 Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TXx/CKx line. The TXx/CKx pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. DS40001412G-page 280  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 16.5.1.5 Synchronous Master Transmission 4. Disable Receive mode by clearing bits SREN Setup: and CREN. 5. Enable Transmit mode by setting the TXEN bit. 1. Initialize the SPBRGHx, SPBRGx register pair and the BRGH and BRG16 bits to achieve the 6. If 9-bit transmission is desired, set the TX9 bit. desired baud rate (see Section16.4 “EUSART 7. If interrupts are desired, set the TXxIE, GIE/ Baud Rate Generator (BRG)”). GIEH and PEIE/GIEL interrupt enable bits. 2. Set the RXx/DTx and TXx/CKx TRIS controls to 8. If 9-bit transmission is selected, the ninth bit ‘1’. should be loaded in the TX9D bit. 3. Enable the synchronous master serial port by 9. Start transmission by loading data to the setting bits SYNC, SPEN and CSRC. Set the TXREGx register. TRIS bits corresponding to the RXx/DTx and TXx/CKx I/O pins. FIGURE 16-10: SYNCHRONOUS TRANSMISSION RXx/DTx pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TXx/CKx pin (SCKP = 0) TXx/CKx pin (SCKP = 1) Write to TXREGx Reg Write Word 1 Write Word 2 TXxIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. FIGURE 16-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RXx/DTx pin bit 0 bit 1 bit 2 bit 6 bit 7 TXx/CKx pin Write to TXREGx reg TXxIF bit TRMT bit TXEN bit  2010-2016 Microchip Technology Inc. DS40001412G-page 281

PIC18(L)F2X/4XK22 TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 150 TXREG1 EUSART1 Transmit Register — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 TXREG2 EUSART2 Transmit Register — TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master transmission. Note 1: PIC18(L)F4XK22 devices. 2: PIC18(L)F2XK22 devices. DS40001412G-page 282  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 16.5.1.6 Synchronous Master Reception If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the Data is received at the RXx/DTx pin. The RXx/DTx pin CREN bit of the RCSTAx register or by clearing the output driver must be disabled by setting the SPEN bit which resets the EUSART. corresponding TRIS bits when the EUSART is configured for synchronous master receive operation. 16.5.1.9 Receiving 9-bit Characters In Synchronous mode, reception is enabled by setting The EUSART supports 9-bit character reception. When either the Single Receive Enable bit (SREN of the the RX9 bit of the RCSTAx register is set the EUSART RCSTAx register) or the Continuous Receive Enable will shift 9-bits into the RSR for each character bit (CREN of the RCSTAx register). received. The RX9D bit of the RCSTAx register is the When SREN is set and CREN is clear, only as many ninth, and Most Significant, data bit of the top unread clock cycles are generated as there are data bits in a character in the receive FIFO. When reading 9-bit data single character. The SREN bit is automatically cleared from the receive FIFO buffer, the RX9D data bit must at the completion of one character. When CREN is set, be read before reading the eight Least Significant bits clocks are continuously generated until CREN is from the RCREGx. cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial charac- 16.5.1.10 Synchronous Master Reception ter is discarded. If SREN and CREN are both set, then Setup: SREN is cleared at the completion of the first character 1. Initialize the SPBRGHx, SPBRGx register pair and CREN takes precedence. for the appropriate baud rate. Set or clear the To initiate reception, set either SREN or CREN. Data is BRGH and BRG16 bits, as required, to achieve sampled at the RXx/DTx pin on the trailing edge of the the desired baud rate. TXx/CKx clock pin and is shifted into the Receive Shift 2. Set the RXx/DTx and TXx/CKx TRIS controls to Register (RSR). When a complete character is ‘1’. received into the RSR, the RCxIF bit is set and the 3. Enable the synchronous master serial port by character is automatically transferred to the two setting bits SYNC, SPEN and CSRC. Disable character receive FIFO. The Least Significant eight bits RXx/DTx and TXx/CKx output drivers by setting of the top character in the receive FIFO are available in the corresponding TRIS bits. RCREGx. The RCxIF bit remains set as long as there 4. Ensure bits CREN and SREN are clear. are un-read characters in the receive FIFO. 5. If using interrupts, set the GIE/GIEH and PEIE/ 16.5.1.7 Slave Clock GIEL bits of the INTCON register and set RCxIE. Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured 6. If 9-bit reception is desired, set bit RX9. as a slave receives the clock on the TXx/CKx line. The 7. Start reception by setting the SREN bit or for TXx/CKx pin output driver must be disabled by setting continuous reception, set the CREN bit. the associated TRIS bit when the device is configured 8. Interrupt flag bit RCxIF will be set when recep- for synchronous slave transmit or receive operation. tion of a character is complete. An interrupt will Serial data bits change on the leading edge to ensure be generated if the enable bit RCxIE was set. they are valid at the trailing edge of each clock. One data 9. Read the RCSTAx register to get the ninth bit (if bit is transferred for each clock cycle. Only as many enabled) and determine if any error occurred clock cycles should be received as there are data bits. during reception. 10. Read the 8-bit received data by reading the 16.5.1.8 Receive Overrun Error RCREGx register. The receive FIFO buffer can hold two characters. An 11. If an overrun error occurs, clear the error by overrun error will be generated if a third character, in its either clearing the CREN bit of the RCSTAx entirety, is received before RCREGx is read to access register or by clearing the SPEN bit which resets the FIFO. When this happens the OERR bit of the the EUSART. RCSTAx register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREGx.  2010-2016 Microchip Technology Inc. DS40001412G-page 283

PIC18(L)F2X/4XK22 FIGURE 16-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RXx/DTx pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TXx/CKx pin (SCKP = 0) TXx/CKx pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCxIF bit (Interrupt) Read RCREGx Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 RCREG1 EUSART1 Receive Register — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 RCREG2 EUSART2 Receive Register — RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception. DS40001412G-page 284  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 16.5.2 SYNCHRONOUS SLAVE MODE 16.5.2.1 EUSART Synchronous Slave Transmit The following bits are used to configure the EUSART for Synchronous slave operation: The operation of the Synchronous Master and Slave • SYNC = 1 modes are identical (see Section16.5.1.3 “Synchronous Master Transmission”), except in the • CSRC = 0 case of the Sleep mode. • SREN = 0 (for transmit); SREN = 1 (for receive) If two words are written to the TXREGx and then the • CREN = 0 (for transmit); CREN = 1 (for receive) SLEEP instruction is executed, the following will occur: • SPEN = 1 1. The first character will immediately transfer to Setting the SYNC bit of the TXSTAx register configures the TSR register and transmit. the device for synchronous operation. Clearing the 2. The second word will remain in TXREGx CSRC bit of the TXSTAx register configures the device as register. a slave. Clearing the SREN and CREN bits of the RCSTAx register ensures that the device is in the 3. The TXxIF bit will not be set. Transmit mode, otherwise the device will be configured to 4. After the first character has been shifted out of receive. Setting the SPEN bit of the RCSTAx register TSR, the TXREGx register will transfer the enables the EUSART. If the RXx/DTx or TXx/CKx pins second character to the TSR and the TXxIF bit are shared with an analog peripheral the analog I/O will now be set. functions must be disabled by clearing the corresponding 5. If the PEIE/GIEL and TXxIE bits are set, the ANSEL bits. interrupt will wake the device from Sleep and RXx/DTx and TXx/CKx pin output drivers must be execute the next instruction. If the GIE/GIEH bit disabled by setting the corresponding TRIS bits. is also set, the program will call the Interrupt Service Routine. 16.5.2.2 Synchronous Slave Transmission Setup: 1. Set the SYNC and SPEN bits and clear the CSRC bit. 2. Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. 3. Clear the CREN and SREN bits. 4. If using interrupts, ensure that the GIE/GIEH and PEIE/GIEL bits of the INTCON register are set and set the TXxIE bit. 5. If 9-bit transmission is desired, set the TX9 bit. 6. Enable transmission by setting the TXEN bit. 7. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 8. Start transmission by writing the Least Significant eight bits to the TXREGx register.  2010-2016 Microchip Technology Inc. DS40001412G-page 285

PIC18(L)F2X/4XK22 TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 150 TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 TXREG1 EUSART1 Transmit Register — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 TXREG2 EUSART2 Transmit Register — TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave transmission. Note 1: PIC18(L)F4XK22 devices. 2: PIC18(L)F2XK22 devices. DS40001412G-page 286  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 16.5.2.3 EUSART Synchronous Slave 16.5.2.4 Synchronous Slave Reception Reception Setup: The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the modes is identical (Section16.5.1.6 “Synchronous CSRC bit. Master Reception”), with the following exceptions: 2. Set the RXx/DTx and TXx/CKx TRIS controls to • Sleep ‘1’. • CREN bit is always set, therefore the receiver is 3. If using interrupts, ensure that the GIE/GIEH never Idle and PEIE/GIEL bits of the INTCON register are set and set the RCxIE bit. • SREN bit, which is a “don't care” in Slave mode 4. If 9-bit reception is desired, set the RX9 bit. A character may be received while in Sleep mode by 5. Set the CREN bit to enable reception. setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data 6. The RCxIF bit will be set when reception is to the RCREGx register. If the RCxIE enable bit is set, complete. An interrupt will be generated if the the interrupt generated will wake the device from Sleep RCxIE bit was set. and execute the next instruction. If the GIE/GIEH bit is 7. If 9-bit mode is enabled, retrieve the Most also set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTAx register. 8. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREGx register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTAx register or by clearing the SPEN bit which resets the EUSART. TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 RCREG1 EUSART1 Receive Register — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 RCREG2 EUSART2 Receive Register — RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception.  2010-2016 Microchip Technology Inc. DS40001412G-page 287

PIC18(L)F2X/4XK22 17.0 ANALOG-TO-DIGITAL The ADC voltage reference is software selectable to CONVERTER (ADC) MODULE either VDD or a voltage applied to the external reference pins. The Analog-to-Digital Converter (ADC) allows The ADC can generate an interrupt upon completion of conversion of an analog input signal to a 10-bit binary a conversion. This interrupt can be used to wake-up the representation of that signal. This device uses analog device from Sleep. inputs, which are multiplexed into a single sample and Figure17-1 shows the block diagram of the ADC. hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). FIGURE 17-1: ADC BLOCK DIAGRAM 5 CHS<4:0> 11111 FVR BUF2 11110 DAC 11101 CTMU 11100 AN28(1) 11011 AN27(1) ADCMD AN5(1) 00101 ADON 10-Bit ADC GO/DONE 00100 AN4 10 00011 AN3 00010 AN2 0 = Left Justify ADFM 00001 1 = Right Justify AN1 00000 AN0 10 2 PVCFG<1:0> ADRESH ADRESL AVDD 00 01 VREF+/AN3 10 FVR BUF2 Reserved 11 2 NVCFG<1:0> AVSS 00 01 VREF-/AN2 10 Reserved Reserved 11 Note: Additional ADC channels AN5-AN7 and AN20-AN27 are only available on PIC18(L)F4XK22 devices. DS40001412G-page 288  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 17.1 ADC Configuration 17.1.3 ADC VOLTAGE REFERENCE When configuring and using the ADC the following The PVCFG<1:0> and NVCFG<1:0> bits of the functions must be considered: ADCON1 register provide independent control of the positive and negative voltage references. • Port configuration The positive voltage reference can be: • Channel selection • ADC voltage reference selection • VDD • ADC conversion clock source • the fixed voltage reference (FVR BUF2) • Interrupt control • an external voltage source (VREF+) • Results formatting The negative voltage reference can be: • VSS 17.1.1 PORT CONFIGURATION • an external voltage source (VREF-) The ANSELx and TRISx registers configure the A/D port pins. Any port pin needed as an analog input 17.1.4 SELECTING AND CONFIGURING should have its corresponding ANSx bit set to disable ACQUISITION TIME the digital input buffer and TRISx bit set to disable the The ADCON2 register allows the user to select an digital output driver. If the TRISx bit is cleared, the acquisition time that occurs each time the GO/DONE digital output level (VOH or VOL) will be converted. bit is set. The A/D operation is independent of the state of the Acquisition time is set with the ACQT<2:0> bits of the ANSx bits and the TRIS bits. ADCON2 register. Acquisition delays cover a range of 2 to 20TAD. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected Note1: When reading the PORT register, all pins acquisition time, then automatically begins a with their corresponding ANSx bit set conversion. Since the acquisition time is programmed, read as cleared (a low level). However, there is no need to wait for an acquisition time between analog conversion of pins configured as selecting a channel and setting the GO/DONE bit. digital inputs (ANSx bit cleared and TRISx bit set) will be accurately Manual acquisition is selected when converted. ACQT<2:0>=000. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user 2: Analog levels on any pin with the corre- is responsible for ensuring the required acquisition time sponding ANSx bit cleared may cause has passed between selecting the desired input the digital input buffer to consume current channel and setting the GO/DONE bit. This option is out of the device’s specification limits. also the default Reset state of the ACQT<2:0> bits and 3: The PBADEN bit in Configuration is compatible with devices that do not offer Register 3H configures PORTB pins to programmable acquisition times. reset as analog or digital pins by In either case, when the conversion is completed, the controlling how the bits in ANSELB are GO/DONE bit is cleared, the ADIF flag is set and the reset. A/D begins sampling the currently selected channel again. When an acquisition time is programmed, there is no indication of when the acquisition time ends and 17.1.2 CHANNEL SELECTION the conversion begins. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section17.2 “ADC Operation” for more information.  2010-2016 Microchip Technology Inc. DS40001412G-page 289

PIC18(L)F2X/4XK22 17.1.5 CONVERSION CLOCK 17.1.6 INTERRUPTS The source of the conversion clock is software The ADC module allows for the ability to generate an selectable via the ADCS bits of the ADCON2 register. interrupt upon completion of an Analog-to-Digital There are seven possible clock options: Conversion. The ADC interrupt enable is the ADIE bit in the PIE1 register and the interrupt priority is the ADIP • FOSC/2 bit in the IPR1 register. The ADC interrupt flag is the • FOSC/4 ADIF bit in the PIR1 register. The ADIF bit must be • FOSC/8 cleared by software. • FOSC/16 • FOSC/32 Note: The ADIF bit is set at the completion of • FOSC/64 every conversion, regardless of whether • FRC (dedicated internal oscillator) or not the ADC interrupt is enabled. The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods as shown in Figure17-3. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the For correct conversion, the appropriate TAD specification interrupt will wake-up the device. Upon waking from must be met. See A/D conversion requirements in Sleep, the next instruction following the SLEEP Table27-22 for more information. Table17-1 gives instruction is always executed. If the user is attempting examples of appropriate ADC clock selections. to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the Note: Unless using the FRC, any changes in the global interrupt is enabled, execution will switch to the system clock frequency will change the Interrupt Service Routine. ADC clock frequency, which may adversely affect the ADC result. TABLE 17-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 64 MHz 16 MHz 4 MHz 1 MHz FOSC/2 000 31.25 ns(2) 125 ns(2) 500 ns(2) 2.0 s FOSC/4 100 62.5 ns(2) 250 ns(2) 1.0 s 4.0 s(3) FOSC/8 001 400 ns(2) 500 ns(2) 2.0 s 8.0 s(3) FOSC/16 101 250 ns(2) 1.0 s 4.0 s(3) 16.0 s(3) FOSC/32 010 500 ns(2) 2.0 s 8.0 s(3) 32.0 s(3) FOSC/64 110 1.0 s 4.0 s(3) 16.0 s(3) 64.0 s(3) FRC x11 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 1.7 s. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode. DS40001412G-page 290  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 17.1.7 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON2 register controls the output format. Figure17-2 shows the two output formats. FIGURE 17-2: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result  2010-2016 Microchip Technology Inc. DS40001412G-page 291

PIC18(L)F2X/4XK22 17.2 ADC Operation Figure17-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT<2:0> bits 17.2.1 STARTING A CONVERSION are cleared. A conversion is started after the following instruction to allow entry into SLEEP mode before the To enable the ADC module, the ADON bit of the conversion begins. ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will, depend- Figure17-4 shows the operation of the A/D converter ing on the ACQT bits of the ADCON2 register, either after the GO bit has been set and the ACQT<2:0> bits immediately start the Analog-to-Digital conversion or are set to ‘010’ which selects a 4 TAD acquisition time start an acquisition delay followed by the Analog-to- before the conversion starts. Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section17.2.10 “A/D Conversion Procedure”. FIGURE 17-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 1 TCY b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Discharge Holding capacitor is disconnected from analog input (0.5 TAD) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 17-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 1 TCY b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Discharge Time (Holding capacitor is disconnected from analog input) Set GO bit (Holding capacitor continues On the following cycle: acquiring input) ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS40001412G-page 292  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 17.2.2 COMPLETION OF A CONVERSION 17.2.7 ADC OPERATION DURING SLEEP When the conversion is complete, the ADC module will: The ADC module can operate during Sleep. This • Clear the GO/DONE bit requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the • Set the ADIF flag bit ADC waits one additional instruction before starting the • Update the ADRESH:ADRESL registers with new conversion. This allows the SLEEP instruction to be conversion result executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device 17.2.3 DISCHARGE will wake-up from Sleep when the conversion The discharge phase is used to initialize the value of completes. If the ADC interrupt is disabled, the ADC the capacitor array. The array is discharged after every module is turned off after the conversion completes, sample. This feature helps to optimize the unity-gain although the ADON bit remains set. amplifier, as the circuit always needs to charge the When the ADC clock source is something other than capacitor array, rather than charge/discharge based on FRC, a SLEEP instruction causes the present previous measure values. conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 17.2.4 TERMINATING A CONVERSION If a conversion must be terminated before completion, 17.2.8 SPECIAL EVENT TRIGGER the GO/DONE bit can be cleared by software. The Two Special Event Triggers are available to start an A/D ADRESH:ADRESL registers will not be updated with conversion: CTMU and CCP5. The Special Event the partially complete Analog-to-Digital conversion Trigger source is selected using the TRIGSEL bit in sample. Instead, the ADRESH:ADRESL register pair ADCON1. will retain the value of the previous conversion. When TRIGSEL = 0, the CCP5 module is selected as the Special Event Trigger source. To enable the Special Note: A device Reset forces all registers to their Event Trigger in the CCP module, set CCP5M<3:0> = Reset state. Thus, the ADC module is 1011, in the CCP5CON register. turned off and any pending conversion is When TRIGSEL = 1, the CTMU module is selected. terminated. The CTMU module requires that the CTTRIG bit in CTMUCONH is set to enable the Special Event Trigger. In addition to TRIGSEL bit, the following steps are 17.2.5 DELAY BETWEEN CONVERSIONS required to start an A/D conversion: After the A/D conversion is completed or aborted, a • The A/D module must be enabled (ADON = 1) 2TAD wait is required before the next acquisition can • The appropriate analog input channel selected be started. After this wait, the currently selected • The minimum acquisition period set one of these channel is reconnected to the charge holding capacitor ways: commencing the next acquisition. - Timing provided by the user - Selection made of an appropriate TACQ time 17.2.6 ADC OPERATION IN POWER- With these conditions met, the trigger sets the GO/DONE MANAGED MODES bit and the A/D acquisition starts. The selection of the automatic acquisition time and A/D If the A/D module is not enabled (ADON = 0), the conversion clock is determined in part by the clock module ignores the Special Event Trigger. source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in 17.2.9 PERIPHERAL MODULE DISABLE a power-managed mode, the ACQT<2:0> and When a peripheral module is not used or inactive, the ADCS<2:0> bits in ADCON2 should be updated in module can be disabled by setting the Module Disable accordance with the clock source to be used in that bit in the PMD registers. This will reduce power mode. After entering the mode, an A/D acquisition or consumption to an absolute minimum. Setting the PMD conversion may be started. Once started, the device bits holds the module in Reset and disconnects the should continue to be clocked by the same clock module’s clock source. The Module Disable bit for the source until the conversion has been completed. ADC module is ADCMD in the PMD2 Register. See If desired, the device may be placed into the Section3.0 “Power-Managed Modes” for more corresponding Idle mode during the conversion. If the information. device clock frequency is less than 1MHz, the A/D FRC clock source should be selected.  2010-2016 Microchip Technology Inc. DS40001412G-page 293

PIC18(L)F2X/4XK22 17.2.10 A/D CONVERSION PROCEDURE EXAMPLE 17-1: A/D CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss as reference, Frc clock and AN0 input. 1. Configure Port: ; • Disable pin output driver (See TRIS register) ;Conversion start & polling for completion • Configure pin as analog ; are included. ; 2. Configure the ADC module: MOVLW B’10101111’ ;right justify, Frc, • Select ADC conversion clock MOVWF ADCON2 ; & 12 TAD ACQ time • Configure voltage reference MOVLW B’00000000’ ;ADC ref = Vdd,Vss MOVWF ADCON1 ; • Select ADC input channel BSF TRISA,0 ;Set RA0 to input • Select result format BSF ANSEL,0 ;Set RA0 to analog • Select acquisition delay MOVLW B’00000001’ ;AN0, ADC on • Turn on ADC module MOVWF ADCON0 ; BSF ADCON0,GO ;Start conversion 3. Configure ADC interrupt (optional): ADCPoll: • Clear ADC interrupt flag BTFSC ADCON0,GO ;Is conversion done? • Enable ADC interrupt BRA ADCPoll ;No, test again ; Result is complete - store 2 MSbits in • Enable peripheral interrupt ; RESULTHI and 8 LSbits in RESULTLO • Enable global interrupt(1) MOVFF ADRESH,RESULTHI 4. Wait the required acquisition time(2). MOVFF ADRESL,RESULTLO 5. Start conversion by setting the GO/DONE bit. 6. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Software delay required if ACQT bits are set to zero delay. See Section17.4 “A/D Acquisition Requirements”. DS40001412G-page 294  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 17.3 Register Definitions: ADC Control Note: Analog pin control is determined by the ANSELx registers (see Register10-2) REGISTER 17-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CHS<4:0> GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4 00101 = AN5(1) 00110 = AN6(1) 00111 = AN7(1) 01000 = AN8 01001 = AN9 01010 = AN10 01011 = AN11 01100 = AN12 01101 = AN13 01110 = AN14 01111 = AN15 10000 = AN16 10001 = AN17 10010 = AN18 10011 = AN19 10100 = AN20(1) 10101 = AN21(1) 10110 = AN22(1) 10111 = AN23(1) 11000 = AN24(1) 11001 = AN25(1) 11010 = AN26(1) 11011 = AN27(1) 11100 = Reserved 11101 = CTMU 11110 = DAC 11111 = FVR BUF2 (1.024V/2.048V/2.096V Volt Fixed Voltage Reference)(2) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: Available on PIC18(L)F4XK22 devices only. 2: Allow greater than 15s acquisition time when measuring the Fixed Voltage Reference.  2010-2016 Microchip Technology Inc. DS40001412G-page 295

PIC18(L)F2X/4XK22 REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 TRIGSEL — — — PVCFG<1:0> NVCFG<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TRIGSEL: Special Trigger Select bit 1 = Selects the special trigger from CTMU 0 = Selects the special trigger from CCP5 bit 6-4 Unimplemented: Read as ‘0’ bit 3-2 PVCFG<1:0>: Positive Voltage Reference Configuration bits 00 = A/D VREF+ connected to internal signal, AVDD 01 = A/D VREF+ connected to external pin, VREF+ 10 = A/D VREF+ connected to internal signal, FVR BUF2 11 = Reserved (by default, A/D VREF+ connected to internal signal, AVDD) bit 1-0 NVCFG<1:0>: Negative Voltage Reference Configuration bits 00 = A/D VREF- connected to internal signal, AVSS 01 = A/D VREF- connected to external pin, VREF- 10 = Reserved (by default, A/D VREF- connected to internal signal, AVSS) 11 = Reserved (by default, A/D VREF- connected to internal signal, AVSS) DS40001412G-page 296  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT<2:0> ADCS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition time select bits. Acquisition time is the duration that the A/D charge holding capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until conversions begins. 000 = 0(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) Note 1: When the A/D clock source is selected as FRC then the start of conversion is delayed by one instruction cycle after the GO/DONE bit is set to allow the SLEEP instruction to be executed.  2010-2016 Microchip Technology Inc. DS40001412G-page 297

PIC18(L)F2X/4XK22 REGISTER 17-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 17-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES<1:0> — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 17-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — — — — ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 17-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result DS40001412G-page 298  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 17.4 A/D Acquisition Requirements acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, For the ADC to meet its specified accuracy, the charge Equation17-1 may be used. This equation assumes holding capacitor (CHOLD) must be allowed to fully that 1/2 LSb error is used (1024 steps for the ADC). The charge to the input channel voltage level. The Analog 1/2 LSb error is the maximum error allowed for the ADC Input model is shown in Figure17-5. The source to meet its specified resolution. impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure17-5. The maximum recommended impedance for analog sources is 3 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D EQUATION 17-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 3.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 5µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– 2---0---4---7--- = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb –TC  ---------- VAPPLIED1–eRC = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– 2---0---4---7--- ;combining [1] and [2]   Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/2047) = –13.5pF1k+700+10k ln(0.0004885) = 1.20µs Therefore: TACQ = 5µs+1.20µs+50°C- 25°C0.05s/°C = 7.45µs Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification.  2010-2016 Microchip Technology Inc. DS40001412G-page 299

PIC18(L)F2X/4XK22 FIGURE 17-5: ANALOG INPUT MODEL VDD Sampling Switch Rs ANx RIC  1k SS Rss VA CPIN I LEAKAGE(1) CHOLD = 13.5 pF 5 pF Discharge VSS/VREF- Switch 3.5V Legend: CPIN = Input Capacitance 3.0V I LEAKAGE = Lvaeraiokaugs eju cnucrtrieonnts at the pin due to DD 2.5V V RIC = Interconnect Resistance 2.0V SS = Sampling Switch 1.5V CHOLD = Sample/Hold Capacitance .1 1 10 100 Rss (k) Note 1: See Section27.0 “Electrical Specifications”. FIGURE 17-6: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh de 3FCh 1/2 LSB ideal o C 3FBh ut p ut Full-Scale O C 004h Transition D A 003h 002h 001h 000h Analog Input Voltage 1/2 LSB ideal VSS/VREF- Zero-Scale VDD/VREF+ Transition DS40001412G-page 300  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 17-2: REGISTERS ASSOCIATED WITH A/D OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — CHS<4:0> GO/DONE ADON 295 ADCON1 TRIGSEL — — — PVCFG<1:0> NVCFG<1:0> 296 ADCON2 ADFM — ACQT<2:0> ADCS<2:0> 297 ADRESH A/D Result, High Byte 298 ADRESL A/D Result, Low Byte 298 ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 149 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 150 ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 151 CCP5CON — — DC5B<1:0> CCP5M<3:0> 198 CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 323 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 IPR4 — — — — — CCP5IP CCP4IP CCP3IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIE4 — — — — — CCP5IE CCP4IE CCP3IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PIR4 — — — — — CCP5IF CCP4IF CCP3IF 115 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 PMD2 — — — — CTMUMD CMP2MD CMP1MD ADCMD 54 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 151 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by this module. Note 1: Available on PIC18(L)F4XK22 devices. TABLE 17-3: CONFIGURATION REGISTERS ASSOCIATED WITH THE ADC MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by the ADC module.  2010-2016 Microchip Technology Inc. DS40001412G-page 301

PIC18(L)F2X/4XK22 18.0 COMPARATOR MODULE FIGURE 18-1: SINGLE COMPARATOR Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and VIN+ + providing a digital indication of their relative magnitudes. Output The comparators are very useful mixed signal building VIN- – blocks because they provide analog functionality independent of the program execution. The analog comparator module includes the following features: • Independent comparator control VIN- • Programmable input selection VIN+ • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change Output • Wake-up from Sleep • Programmable Speed/Power optimization • PWM shutdown Note: The black areas of the output of the • Programmable and fixed voltage reference comparator represents the uncertainty • Selectable Hysteresis due to input offsets and response time. 18.1 Comparator Overview A single comparator is shown in Figure18-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. DS40001412G-page 302  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 18-2: COMPARATOR C1/C2 SIMPLIFIED BLOCK DIAGRAM CxCH<1:0> 2 CxON(1) To CMxCON0 (CxOUT) CxSP C12IN0- 0 CM2CON1 (MCxOUT) D Q C12IN1- 1 CxVIN- Q1(2),(3) EN - C12IN2- 2 Cx CxVIN+ + C12IN3- 3 D Q Q3(2) To Interrupts EN (CxIF) CxR CL Read or Write of CMxCON0 CxIN+ 0 Reset async_CXOUT DAC Output 0 1 CxPOL to PWM Logic CxSYNC CxOE TRIS bit FVR BUF1 1 CXVREF 0 CXRSEL D Q 1 CxOUT Timer1 Clock sync_CxOUT - to SR Latch - to TxG MUX(4) Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. 4: Synchronized comparator output should not be used to gate Timer1 in conjunction with synchronized T1CKI.  2010-2016 Microchip Technology Inc. DS40001412G-page 303

PIC18(L)F2X/4XK22 18.2 Comparator Control Each comparator has a separate control and Note1: The CxOE bit overrides the PORT data Configuration register: CM1CON0 for Comparator C1 latch. Setting the CxON has no impact on and CM2CON0 for Comparator C2. In addition, the port override. Comparator C2 has a second control register, 2: The internal output of the comparator is CM2CON1, for controlling the interaction with Timer1 and latched with each instruction cycle. simultaneous reading of both comparator outputs. Unless otherwise specified, external The CM1CON0 and CM2CON0 registers (see outputs are not latched. Register18-1) contain the control and status bits for the following: 18.2.5 COMPARATOR OUTPUT POLARITY • Enable Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The • Input selection polarity of the comparator output can be inverted by • Reference selection setting the CxPOL bit of the CMxCON0 register. • Output selection Clearing the CxPOL bit results in a non-inverted output. • Output polarity Table18-1 shows the output state versus input • Speed selection conditions, including polarity control. 18.2.1 COMPARATOR ENABLE TABLE 18-1: COMPARATOR OUTPUT Setting the CxON bit of the CMxCON0 register enables STATE VS. INPUT the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current CONDITIONS consumption. Input Condition CxPOL CxOUT 18.2.2 COMPARATOR INPUT SELECTION CxVIN- > CxVIN+ 0 0 The CxCH<1:0> bits of the CMxCON0 register direct CxVIN- < CxVIN+ 0 1 one of four analog input pins to the comparator CxVIN- > CxVIN+ 1 1 inverting input. CxVIN- < CxVIN+ 1 0 18.2.6 COMPARATOR SPEED SELECTION Note: To use CxIN+ and C12INx- pins as analog The trade-off between speed or power can be inputs, the appropriate bits must be set in optimized during program execution with the CxSP the ANSEL register and the control bit. The default state for this bit is ‘1’ which corresponding TRIS bits must also be set selects the normal speed mode. Device power to disable the output drivers. consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit 18.2.3 COMPARATOR REFERENCE to ‘0’. SELECTION Setting the CxR bit of the CMxCON0 register directs an 18.3 Comparator Response Time internal voltage reference or an analog input pin to the The comparator output is indeterminate for a period of non-inverting input of the comparator. See time after the change of an input source or the selection Section21.0 “Fixed Voltage Reference (FVR)” for of a new reference voltage. This period is referred to as more information on the Internal Voltage Reference the response time. The response time of the module. comparator differs from the settling time of the voltage 18.2.4 COMPARATOR OUTPUT reference. Therefore, both of these times must be SELECTION considered when determining the total response time to a comparator input change. See the Comparator and The output of the comparator can be monitored by Voltage Reference Specifications in Section27.0 reading either the CxOUT bit of the CMxCON0 register “Electrical Specifications” for more details. or the MCxOUT bit of the CM2CON1 register. In order to make the output available for an external connection, the following conditions must be true: • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set DS40001412G-page 304  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 18.4 Comparator Interrupt Operation 18.4.1 PRESETTING THE MISMATCH LATCHES The comparator interrupt flag will be set whenever there is a change in the output value of the comparator. The comparator mismatch latches can be preset to the Changes are recognized by means of a mismatch desired state before the comparators are enabled. circuit which consists of two latches and an exclusive- When the comparator is off the CxPOL bit controls the or gate (see Figure18-2). The first latch is updated with CxOUT level. Set the CxPOL bit to the desired CxOUT the comparator output value, when the CMxCON0 non-interrupt level while the CxON bit is cleared. Then, register is read or written. The value is latched on the configure the desired CxPOL level in the same third cycle of the system clock, also known as Q3. This instruction that the CxON bit is set. Since all register first latch retains the comparator value until another writes are performed as a read-modify-write, the read or write of the CMxCON0 register occurs or a mismatch latches will be cleared during the instruction Reset takes place. The second latch is updated with read phase and the actual configuration of the CxON the comparator output value on every first cycle of the and CxPOL bits will be occur in the final write phase. system clock, also known as Q1. When the output value of the comparator changes, the second latch is FIGURE 18-3: COMPARATOR updated and the output values of both latches no INTERRUPT TIMING W/O longer match one another, resulting in a mismatch CMxCON0 READ condition. The latch outputs are fed directly into the inputs of an exclusive-or gate. This mismatch condition Q1 is detected by the exclusive-or gate and sent to the Q3 interrupt circuitry. The mismatch condition will persist CxIN+ TRT until the first latch value is updated by performing a CxIN read of the CMxCON0 register or the comparator Set CxIF (edge) output returns to the previous state. CxIF Note 1: A write operation to the CMxCON0 Reset by Software register will also clear the mismatch condition because all writes include a read FIGURE 18-4: COMPARATOR operation at the beginning of the write INTERRUPT TIMING WITH cycle. CMxCON0 READ 2: Comparator interrupts will operate correctly regardless of the state of CxOE. Q1 When the mismatch condition occurs, the comparator Q3 interrupt flag is set. The interrupt flag is triggered by the CxIN+ TRT edge of the changing value coming from the exclusive- CxOUT or gate. This means that the interrupt flag can be reset Set CxIF (edge) once it is triggered without the additional step of CxIF reading or writing the CMxCON0 register to clear the mismatch latches. When the mismatch registers are Cleared by CMxCON0 Read Reset by Software cleared, an interrupt will occur upon the comparator’s return to the previous state, otherwise no interrupt will be generated. Note1: If a change in the CMxCON0 register Software will need to maintain information about the (CxOUT) should occur when a read status of the comparator output, as read from the operation is being executed (start of the CMxCON0 register, or CM2CON1 register, to determine Q2 cycle), then the CxIF interrupt flag of the actual change that has occurred. See Figures18-3 the PIR2 register may not get set. and18-4. 2: When either comparator is first enabled, The CxIF bit of the PIR2 register is the comparator bias circuitry in the comparator module interrupt flag. This bit must be reset by software by may cause an invalid output from the clearing it to ‘0’. Since it is also possible to write a ‘1’ to comparator until the bias circuitry is this register, an interrupt can be generated. stable. Allow about 1 s for bias settling then clear the mismatch condition and In mid-range Compatibility mode the CxIE bit of the interrupt flags before enabling comparator PIE2 register and the PEIE/GIEL and GIE/GIEH bits of interrupts. the INTCON register must all be set to enable compar- ator interrupts. If any of these bits are cleared, the inter- rupt is not enabled, although the CxIF bit of the PIR2 register will still be set if an interrupt condition occurs.  2010-2016 Microchip Technology Inc. DS40001412G-page 305

PIC18(L)F2X/4XK22 18.5 Operation During Sleep 18.7 Analog Input Connection Considerations The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current A simplified circuit for an analog input is shown in consumed by the comparator is shown separately in Figure18-5. Since the analog input pins share their Section27.0 “Electrical Specifications”. If the connection with a digital input, they have reverse comparator is not used to wake the device, power biased ESD protection diodes to VDD and VSS. The consumption can be minimized while in Sleep mode by analog input, therefore, must be between VSS and VDD. turning off the comparator. Each comparator is turned off If the input voltage deviates from this range by more by clearing the CxON bit of the CMxCON0 register. than 0.6V in either direction, one of the diodes is A change to the comparator output can wake-up the forward biased and a latch-up may occur. device from Sleep. To enable the comparator to wake A maximum source impedance of 10 k is recommended the device from Sleep, the CxIE bit of the PIE2 register for the analog sources. Also, any external component and the PEIE/GIEL bit of the INTCON register must be connected to an analog input pin, such as a capacitor or set. The instruction following the SLEEP instruction a Zener diode, should have very little leakage current to always executes following a wake from Sleep. If the minimize inaccuracies introduced. GIE/GIEH bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. Note1: When reading a PORT register, all pins 18.6 Effects of a Reset configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will A device Reset forces the CMxCON0 and CM2CON1 convert as an analog input, according to registers to their Reset states. This forces both the input specification. comparators and the voltage references to their Off 2: Analog levels on any pin defined as a states.Comparator Control Registers. digital input, may cause the input buffer to consume more current than is specified. FIGURE 18-5: ANALOG INPUT MODEL VDD Rs < 10K VT  0.6V RIC To Comparator AIN VA C5 PpIFN VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage Note1: See Section27.0 “Electrical Specifications”. DS40001412G-page 306  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 18.8 Additional Comparator Features 18.8.3 COMPARATOR HYSTERESIS There are four additional comparator features: Each Comparator has a selectable hysteresis feature. The hysteresis can be enabled by setting the CxHYS • Simultaneous read of comparator outputs bit of the CM2CON1 register. See Section27.0 • Internal reference selection “Electrical Specifications” for more details. • Hysteresis selection 18.8.4 SYNCHRONIZING COMPARATOR • Output Synchronization OUTPUT TO TIMER1 18.8.1 SIMULTANEOUS COMPARATOR The Comparator Cx output can be synchronized with OUTPUT READ Timer1 by setting the CxSYNC bit of the CM2CON1 The MC1OUT and MC2OUT bits of the CM2CON1 register. When enabled, the Cx output is latched on register are mirror copies of both comparator outputs. the falling edge of the Timer1 source clock. To prevent The ability to read both outputs simultaneously from a a race condition when gating Timer1 clock with the single register eliminates the timing skew of reading comparator output, Timer1 increments on the rising separate registers. edge of its clock source, and the falling edge latches the comparator output. See the Comparator Block Diagram (Figure18-2) and the Timer1 Block Diagram Note1: Obtaining the status of C1OUT or (Figure12-1) for more information. C2OUT by reading CM2CON1 does not affect the comparator interrupt mismatch registers. Note1: The comparator synchronized output should not be used to gate the external 18.8.2 INTERNAL REFERENCE Timer1 clock when the Timer1 SELECTION synchronizer is enabled. There are two internal voltage references available to 2: The Timer1 prescale should be set to 1:1 the non-inverting input of each comparator. One of when synchronizing the comparator these is the Fixed Voltage Reference (FVR) and the output as unexpected results may occur other is the variable Digital-to-Analog Converter (DAC). with other prescale values. The CxRSEL bit of the CM2CON1 register determines which of these references is routed to the Comparator Voltage reference output (CXVREF). Further routing to the comparator is accomplished by the CxR bit of the CMxCON0 register. See Section21.0 “Fixed Voltage Reference (FVR)” and Figure18-2 for more detail.  2010-2016 Microchip Technology Inc. DS40001412G-page 307

PIC18(L)F2X/4XK22 18.9 Register Definitions: Comparator Control REGISTER 18-1: CMxCON0: COMPARATOR x CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 CxON CxOUT CxOE CxPOL CxSP CxR CxCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CxON: Comparator Cx Enable bit 1 = Comparator Cx is enabled 0 = Comparator Cx is disabled bit 6 CxOUT: Comparator Cx Output bit If CxPOL = 1 (inverted polarity): CxOUT = 0 when CxVIN+ > CxVIN- CxOUT = 1 when CxVIN+ < CxVIN- If CxPOL = 0 (non-inverted polarity): CxOUT = 1 when CxVIN+ > CxVIN- CxOUT = 0 when CxVIN+ < CxVIN- bit 5 CxOE: Comparator Cx Output Enable bit 1 =CxOUT is present on the CxOUT pin(1) 0 =CxOUT is internal only bit 4 CxPOL: Comparator Cx Output Polarity Select bit 1 = CxOUT logic is inverted 0 = CxOUT logic is not inverted bit 3 CxSP: Comparator Cx Speed/Power Select bit 1 = Cx operates in Normal-Power, Higher Speed mode 0 = Cx operates in Low-Power, Low-Speed mode bit 2 CxR: Comparator Cx Reference Select bit (non-inverting input) 1 = CxVIN+ connects to CXVREF output 0 = CxVIN+ connects to C12IN+ pin bit 1-0 CxCH<1:0>: Comparator Cx Channel Select bit 00 = C12IN0- pin of Cx connects to CxVIN- 01 = C12IN1- pin of Cx connects to CXVIN- 10 = C12IN2- pin of Cx connects to CxVIN- 11 = C12IN3- pin of Cx connects to CxVIN- Note 1: Comparator output requires the following three conditions: CxOE = 1, CxON = 1 and corresponding port TRIS bit = 0. DS40001412G-page 308  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 18-2: CM2CON1: COMPARATOR 1 AND 2 CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 C1RSEL: Comparator C1 Reference Select bit 1 = FVR BUF1 routed to C1VREF input 0 = DAC routed to C1VREF input bit 4 C2RSEL: Comparator C2 Reference Select bit 1 = FVR BUF1 routed to C2VREF input 0 = DAC routed to C2VREF input bit 3 C1HYS: Comparator C1 Hysteresis Enable bit 1 = Comparator C1 hysteresis enabled 0 = Comparator C1 hysteresis disabled bit 2 C2HYS: Comparator C2 Hysteresis Enable bit 1 = Comparator C2 hysteresis enabled 0 = Comparator C2 hysteresis disabled bit 1 C1SYNC: C1 Output Synchronous Mode bit 1 = C1 output is synchronized to rising edge of TMR1 clock (T1CLK) 0 = C1 output is asynchronous bit 0 C2SYNC: C2 Output Synchronous Mode bit 1 = C2 output is synchronized to rising edge of TMR1 clock (T1CLK) 0 = C2 output is asynchronous  2010-2016 Microchip Technology Inc. DS40001412G-page 309

PIC18(L)F2X/4XK22 TABLE 18-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 149 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 309 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH<1:0> 308 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH<1:0> 308 VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 335 VREFCON2 — — — DACR<4:0> 336 VREFCON0 FVREN FVRST FVRS<1:0> — — — — 332 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PMD2 — — — — CTMUMD CMP2MD CMP1MD ADCMD 54 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by the comparator module. DS40001412G-page 310  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 19.0 CHARGE TIME • High precision time measurement MEASUREMENT UNIT (CTMU) • Time delay of external or internal signal asynchronous to system clock The Charge Time Measurement Unit (CTMU) is a • Accurate current source suitable for capacitive flexible analog module that provides accurate measurement differential time measurement between pulse sources, The CTMU works in conjunction with the A/D Converter as well as asynchronous pulse generation. By working to provide up to 28(1) channels for time or charge with other on-chip analog modules, the CTMU can be measurement, depending on the specific device and used to precisely measure time, measure capacitance, the number of A/D channels available. When config- measure relative changes in capacitance or generate ured for time delay, the CTMU is connected to the output pulses with a specific time delay. The CTMU is C12IN1- input of Comparator 2. The level-sensitive ideal for interfacing with capacitive-based sensors. input edge sources can be selected from four sources: The module includes the following key features: two external input pins (CTED1/CTED2) or the ECCP1/ • Up to 28(1) channels available for capacitive or (E)CCP2 Special Event Triggers. time measurement input Figure19-1 provides a block diagram of the CTMU. • On-chip precision current source • Four-edge input trigger sources • Polarity control for each edge source Note1: PIC18(L)F2XK22 devices have up to 17 • Control of edge sequence channels available. • Control of response to edges FIGURE 19-1: CTMU BLOCK DIAGRAM CTMUCONH/CTMUCONL CTMUICON EDGEN EDGSEQEN EDG1SELx ITRIM<5:0> TGEN EDG1POL IRNG<1:0> IDISSEN EDG2SELx EDG1STAT CTTRIG Current Source EDG2POL EDG2STAT CTED1 Edge CTMU Control Control CTED2 Logic Current Logic Control ECCP2 Pulse CTPLS ECCP1 Generator Comparator 2 Output Comparator C1/C2 Input A/D Converter  2010-2016 Microchip Technology Inc. DS40001412G-page 311

PIC18(L)F2X/4XK22 19.1 CTMU Operation 19.1.2 CURRENT SOURCE The CTMU works by using a fixed current source to At the heart of the CTMU is a precision current source, charge a circuit. The type of circuit depends on the type designed to provide a constant reference for of measurement being made. In the case of charge measurements. The level of current is user-selectable measurement, the current is fixed, and the amount of across three ranges, with the ability to trim the output. time the current is applied to the circuit is fixed. The The current range is selected by the IRNG<1:0> bits amount of voltage read by the A/D is then a (CTMUICON<1:0>), with a value of ‘00’ representing measurement of the capacitance of the circuit. In the the lowest range. case of time measurement, the current, as well as the Current trim is provided by the ITRIM<5:0> bits capacitance of the circuit, is fixed. In this case, the (CTMUICON<7:2>). Note that half of the range adjusts voltage read by the A/D is then representative of the the current source positively and the other half reduces amount of time elapsed from the time the current the current source. A value of ‘000000’ is the neutral source starts and stops charging the circuit. position (no change). A value of ‘100000’ is the maxi- If the CTMU is being used as a time delay, both mum negative adjustment, and ‘011111’ is the maxi- capacitance and current source are fixed, as well as the mum positive adjustment. voltage supplied to the comparator circuit. The delay of 19.1.3 EDGE SELECTION AND CONTROL a signal is determined by the amount of time it takes the voltage to charge to the comparator threshold voltage. CTMU measurements are controlled by edge events occurring on the module’s two input channels. Each 19.1.1 THEORY OF OPERATION channel, referred to as Edge 1 and Edge 2, can be The operation of the CTMU is based on the equation configured to receive input pulses from one of the edge for charge: input pins (CTED1 and CTED2) or ECCPx Special Event Triggers. The input channels are level-sensitive, responding to the instantaneous level on the channel dV rather than a transition between levels. The inputs are I = C------- dT selected using the EDG1SEL and EDG2SEL bit pairs (CTMUCONL<3:2 and 6:5>). More simply, the amount of charge measured in In addition to source, each channel can be configured for coulombs in a circuit is defined as current in amperes event polarity using the EDGE2POL and EDGE1POL (I) multiplied by the amount of time in seconds that the bits (CTMUCONL<7,4>). The input channels can also current flows (t). Charge is also defined as the be filtered for an edge event sequence (Edge 1 occur- capacitance in farads (C) multiplied by the voltage of ring before Edge 2) by setting the EDGSEQEN bit the circuit (V). It follows that: (CTMUCONH<2>). 19.1.4 EDGE STATUS It = CV. The CTMUCONL register also contains two Status bits: EDG2STAT and EDG1STAT (CTMUCONL<1:0>). The CTMU module provides a constant, known current Their primary function is to show if an edge response source. The A/D Converter is used to measure (V) in has occurred on the corresponding channel. The the equation, leaving two unknowns: capacitance (C) CTMU automatically sets a particular bit when an edge and time (t). The above equation can be used to response is detected on its channel. The level-sensitive calculate capacitance or time, by either the relationship nature of the input channels also means that the Status using the known fixed capacitance of the circuit: bits become set immediately if the channel’s configura- tion is changed and is the same as the channel’s t = CVI current state. or by: C = ItV using a fixed time that the current source is applied to the circuit. DS40001412G-page 312  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 The module uses the edge Status bits to control the 19.2 CTMU Module Initialization current source output to external analog modules (such as the A/D Converter). Current is only supplied to The following sequence is a general guideline used to external modules when only one (but not both) of the initialize the CTMU module: Status bits is set, and shuts current off when both bits 1. Select the current source range using the IRNG are either set or cleared. This allows the CTMU to bits (CTMUICON<1:0>). measure current only during the interval between 2. Adjust the current source trim using the ITRIM edges. After both Status bits are set, it is necessary to bits (CTMUICON<7:2>). clear them before another measurement is taken. Both 3. Configure the edge input sources for Edge 1 and bits should be cleared simultaneously, if possible, to Edge 2 by setting the EDG1SEL and EDG2SEL avoid re-enabling the CTMU current source. bits (CTMUCONL<3:2 and 6:5>). In addition to being set by the CTMU hardware, the 4. Configure the input polarities for the edge inputs edge Status bits can also be set by software. This is using the EDG1POL and EDG2POL bits also the user’s application to manually enable or (CTMUCONL<4,7>). The default configuration disable the current source. Setting either one (but not is for negative edge polarity (high-to-low both) of the bits enables the current source. Setting or transitions). clearing both bits at once disables the source. 5. Enable edge sequencing using the EDGSEQEN bit (CTMUCONH<2>). By default, edge 19.1.5 INTERRUPTS sequencing is disabled. The CTMU sets its interrupt flag (PIR3<2>) whenever 6. Select the operating mode (Measurement or the current source is enabled, then disabled. An Time Delay) with the TGEN bit. The default interrupt is generated only if the corresponding mode is Time/Capacitance Measurement. interrupt enable bit (PIE3<2>) is also set. If edge 7. Discharge the connected circuit by setting the sequencing is not enabled (i.e., Edge 1 must occur IDISSEN bit (CTMUCONH<1>); after waiting a before Edge 2), it is necessary to monitor the edge sufficient time for the circuit to discharge, clear Status bits and determine which edge occurred last and IDISSEN. caused the interrupt. 8. Disable the module by clearing the CTMUEN bit (CTMUCONH<7>). 9. Enable the module by setting the CTMUEN bit. 10. Clear the Edge Status bits: EDG2STAT and EDG1STAT (CTMUCONL<1:0>). 11. Enable both edge inputs by setting the EDGEN bit (CTMUCONH<3>). Depending on the type of measurement or pulse generation being performed, one or more additional modules may also need to be initialized and configured with the CTMU module: • Edge Source Generation: In addition to the external edge input pins, both Timer1 and the Output Compare/PWM1 module can be used as edge sources for the CTMU. • Capacitance or Time Measurement: The CTMU module uses the A/D Converter to measure the voltage across a capacitor that is connected to one of the analog input channels. • Pulse Generation: When generating system clock independent output pulses, the CTMU module uses Comparator 2 and the associated comparator voltage reference.  2010-2016 Microchip Technology Inc. DS40001412G-page 313

PIC18(L)F2X/4XK22 19.3 Calibrating the CTMU Module FIGURE 19-2: CTMU CURRENT SOURCE CALIBRATION CIRCUIT The CTMU requires calibration for precise measurements of capacitance and time, as well as for accurate time delay. If the application only requires PIC18(L)FXXK22 Device measurement of a relative change in capacitance or CTMU Current Source time, calibration is usually not necessary. An example of this type of application would include a capacitive touch switch, in which the touch circuit has a baseline capacitance, and the added capacitance of the human body changes the overall capacitance of a circuit. A/D Converter If actual capacitance or time measurement is required, two hardware calibrations must take place: the current source needs calibration to set it to a precise current, ANx A/D and the circuit being measured needs calibration to measure and/or nullify all other capacitance other than RCAL MUX that to be measured. 19.3.1 CURRENT SOURCE CALIBRATION A value of 70% of full-scale voltage is chosen to make The current source on the CTMU module is trimable. sure that the A/D Converter was in a range that is well Therefore, for precise measurements, it is possible to above the noise floor. Keep in mind that if an exact cur- measure and adjust this current source by placing a rent is chosen, that is to incorporate the trimming bits high precision resistor, RCAL, onto an unused analog channel. An example circuit is shown in Figure19-2. from CTMUICON, the resistor value of RCAL may need The current source measurement is performed using to be adjusted accordingly. RCAL may also be adjusted the following steps: to allow for available resistor values. RCAL should be of the highest precision available, keeping in mind the 1. Initialize the A/D Converter. amount of precision needed for the circuit that the 2. Initialize the CTMU. CTMU will be used to measure. A recommended 3. Enable the current source by setting EDG1STAT minimum would be 0.1% tolerance. (CTMUCONL<0>). The following examples show one typical method for 4. Issue settling time delay. performing a CTMU current calibration. Example19-1 5. Perform A/D conversion. demonstrates how to initialize the A/D Converter and 6. Calculate the current source current using the CTMU; this routine is typical for applications using I=V/RCAL, where RCAL is a high precision both modules. Example19-2 demonstrates one resistance and V is measured by performing an method for the actual calibration routine. A/D conversion. The CTMU current source may be trimmed with the trim bits in CTMUICON using an iterative process to get an exact desired current. Alternatively, the nominal value without adjustment may be used; it may be stored by the software for use in all subsequent capacitive or time measurements. To calculate the value for RCAL, the nominal current must be chosen, and then the resistance can be calculated. For example, if the A/D Converter reference voltage is 3.3V, use 70% of full scale, or 2.31V as the desired approximate voltage to be read by the A/D Converter. If the range of the CTMU current source is selected to be 0.55 A, the resistor value needed is cal- culated as RCAL=2.31V/0.55A, for a value of 4.2MΩ. Similarly, if the current source is chosen to be 5.5A, RCAL would be 420,000Ω, and 42,000Ω if the current source is set to 55A. DS40001412G-page 314  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 EXAMPLE 19-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.h" /**************************************************************************/ /*Set up CTMU *****************************************************************/ /**************************************************************************/ void setup(void) { //CTMUCONH/1 - CTMU Control registers CTMUCONH = 0x00; //make sure CTMU is disabled CTMUCONL = 0x90; //CTMU continues to run when emulator is stopped,CTMU continues //to run in idle mode,Time Generation mode disabled, Edges are blocked //No edge sequence order, Analog current source not grounded, trigger //output disabled, Edge2 polarity = positive level, Edge2 source = //source 0, Edge1 polarity = positive level, Edge1 source = source 0, //CTMUICON - CTMU Current Control Register CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment /**************************************************************************/ //Set up AD converter; /**************************************************************************/ TRISA=0x04; //set channel 2 as an input // Configure AN2 as an analog channel ANSELAbits.ANSA2=1; TRISAbits.TRISA2=1; // ADCON2 ADCON2bits.ADFM=1; // Results format 1= Right justified ADCON2bits.ACQT=1; // Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD ADCON2bits.ADCS=2; // Clock conversion bits 6= FOSC/64 2=FOSC/32 // ADCON1 ADCON1bits.PVCFG0 =0; // Vref+ = AVdd ADCON1bits.NVCFG1 =0; // Vref- = AVss // ADCON0 ADCON0bits.CHS=2; // Select ADC channel ADCON0bits.ADON=1; // Turn on ADC }  2010-2016 Microchip Technology Inc. DS40001412G-page 315

PIC18(L)F2X/4XK22 EXAMPLE 19-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 //@ 8MHz = 125uS. #define DELAY for(i=0;i<COUNT;i++) #define RCAL .027 //R value is 4200000 (4.2M) //scaled so that result is in //1/100th of uA #define ADSCALE 1023 //for unsigned conversion 10 sig bits #define ADREF 3.3 //Vdd connected to A/D Vr+ int main(void) { int i; int j = 0; //index for loop unsigned int Vread = 0; double VTot = 0; float Vavg=0, Vcal=0, CTMUISrc = 0; //float values stored for calcs //assume CTMU and A/D have been set up correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero CTMUCONLbits.EDG2STAT = 0; for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag VTot += Vread; //Add the reading to the total } Vavg = (float)(VTot/10.000); //Average of 10 readings Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA } DS40001412G-page 316  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 19.3.2 CAPACITANCE CALIBRATION There is a small amount of capacitance from the internal A/D Converter sample capacitor as well as stray capacitance from the circuit board traces and pads that affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by making sure the desired capacitance to be measured has been removed. The measurement is then performed using the following steps: 1. Initialize the A/D Converter and the CTMU. 2. Set EDG1STAT (=1). 3. Wait for a fixed delay of time t. 4. Clear EDG1STAT. 5. Perform an A/D conversion. 6. Calculate the stray and A/D sample capacitances: C = C +C = ItV OFFSET STRAY AD where I is known from the current source measurement step, t is a fixed delay and V is measured by performing an A/D conversion. This measured value is then stored and used for calculations of time measurement or subtracted for capacitance measurement. For calibration, it is expected that the capacitance of CSTRAY+CAD is approximately known. CAD is approximately 4pF. An iterative process may need to be used to adjust the time, t, that the circuit is charged to obtain a reasonable voltage reading from the A/D Converter. The value of t may be determined by setting COFFSET to a theoretical value, then solving for t. For example, if CSTRAY is theoretically calculated to be 11pF, and V is expected to be 70% of VDD, or 2.31V, then t would be: (4 pF + 11 pF) • 2.31V/0.55 A or 63s. See Example19-3 for a typical routine for CTMU capacitance calibration.  2010-2016 Microchip Technology Inc. DS40001412G-page 317

PIC18(L)F2X/4XK22 EXAMPLE 19-3: CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 25 //@ 8MHz INTFRC = 62.5 us. #define ETIME COUNT*2.5 //time in uS #define DELAY for(i=0;i<COUNT;i++) #define ADSCALE 1023 //for unsigned conversion 10 sig bits #define ADREF 3.3 //Vdd connected to A/D Vr+ #define RCAL .027 //R value is 4200000 (4.2M) //scaled so that result is in //1/100th of uA int main(void) { int i; int j = 0; //index for loop unsigned int Vread = 0; float CTMUISrc, CTMUCap, Vavg, VTot, Vcal; //assume CTMU and A/D have been set up correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero CTMUCONLbits.EDG2STAT = 0; for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag VTot += Vread; //Add the reading to the total } Vavg = (float)(VTot/10.000); //Average of 10 readings Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA CTMUCap = (CTMUISrc*ETIME/Vcal)/100; } DS40001412G-page 318  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 19.4 Measuring Capacitance with the 19.4.2 RELATIVE CHARGE CTMU MEASUREMENT An application may not require precise capacitance There are two separate methods of measuring measurements. For example, when detecting a valid capacitance with the CTMU. The first is the absolute press of a capacitance-based switch, detecting a rela- method, in which the actual capacitance value is tive change of capacitance is of interest. In this type of desired. The second is the relative method, in which application, when the switch is open (or not touched), the actual capacitance is not needed, rather an the total capacitance is the capacitance of the combina- indication of a change in capacitance is required. tion of the board traces, the A/D Converter, etc. A larger 19.4.1 ABSOLUTE CAPACITANCE voltage will be measured by the A/D Converter. When MEASUREMENT the switch is closed (or is touched), the total capacitance is larger due to the addition of the For absolute capacitance measurements, both the capacitance of the human body to the above listed current and capacitance calibration steps found in capacitances, and a smaller voltage will be measured Section 19.3 “Calibrating the CTMU Module” by the A/D Converter. should be followed. Capacitance measurements are Detecting capacitance changes is easily accomplished then performed using the following steps: with the CTMU using these steps: 1. Initialize the A/D Converter. 1. Initialize the A/D Converter and the CTMU. 2. Initialize the CTMU. 2. Set EDG1STAT. 3. Set EDG1STAT. 3. Wait for a fixed delay. 4. Wait for a fixed delay, T. 4. Clear EDG1STAT. 5. Clear EDG1STAT. 5. Perform an A/D conversion. 6. Perform an A/D conversion. The voltage measured by performing the A/D 7. Calculate the total capacitance, CTOTAL = (I * T)/V, conversion is an indication of the relative capacitance. where I is known from the current source Note that in this case, no calibration of the current measurement step (see Section 19.3.1 “Current source or circuit capacitance measurement is needed. Source Calibration”), T is a fixed delay and V is See Example19-4 for a sample software routine for a measured by performing an A/D conversion. capacitive touch switch. 8. Subtract the stray and A/D capacitance (COFFSET from Section 19.3.2 “Capacitance Calibration”) from CTOTAL to determine the measured capacitance.  2010-2016 Microchip Technology Inc. DS40001412G-page 319

PIC18(L)F2X/4XK22 EXAMPLE 19-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define COUNT 500 //@ 8MHz = 125uS. #define DELAY for(i=0;i<COUNT;i++) #define OPENSW 1000 //Un-pressed switch value #define TRIP 300 //Difference between pressed //and un-pressed switch #define HYST 65 //amount to change //from pressed to un-pressed #define PRESSED 1 #define UNPRESSED 0 int main(void) { unsigned int Vread; //storage for reading unsigned int switchState; int i; //assume CTMU and A/D have been set up correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; // Enable the CTMU CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero CTMUCONLbits.EDG2STAT = 0; CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D if(Vread < OPENSW - TRIP) { switchState = PRESSED; } else if(Vread > OPENSW - TRIP + HYST) { switchState = UNPRESSED; } } DS40001412G-page 320  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 19.5 Measuring Time with the CTMU It is assumed that the time measured is small enough Module that the capacitance, COFFSET, provides a valid voltage to the A/D Converter. For the smallest time measure- Time can be precisely measured after the ratio (C/I) is ment, always set the A/D Channel Select register measured from the current and capacitance calibration (AD1CHS) to an unused A/D channel; the correspond- step by following these steps: ing pin for which is not connected to any circuit board 1. Initialize the A/D Converter and the CTMU. trace. This minimizes added stray capacitance, keep- ing the total circuit capacitance close to that of the A/D 2. Set EDG1STAT. Converter itself (4-5pF). To measure longer time 3. Set EDG2STAT. intervals, an external capacitor may be connected to an 4. Perform an A/D conversion. A/D channel and this channel selected when making a 5. Calculate the time between edges as T = (C/I) * V, time measurement. where I is calculated in the current calibration step (Section 19.3.1 “Current Source Calibration”), C is calculated in the capacitance calibration step (Section 19.3.2 “Capacitance Calibration”) and V is measured by performing the A/D conversion. FIGURE 19-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC18(L)FXXK22 Device CTMU CTED1 EDG1 Current Source CTED2 EDG2 Output Pulse A/D Converter ANX CAD RPR  2010-2016 Microchip Technology Inc. DS40001412G-page 321

PIC18(L)F2X/4XK22 19.6 Creating a Delay with the CTMU An example use of this feature is for interfacing with Module variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the pulse width output A unique feature on board the CTMU module is its on CTPLS will vary. The CTPLS output pin can be con- ability to generate system clock independent output nected to an input capture pin and the varying pulse pulses based on an external capacitor value. This is width is measured to determine the humidity in the accomplished using the internal comparator voltage application. reference module, Comparator 2 input pin and an Follow these steps to use this feature: external capacitor. The pulse is output onto the CTPLS pin. To enable this mode, set the TGEN bit. 1. Initialize Comparator 2. 2. Initialize the comparator voltage reference. See Figure19-4 for an example circuit. CPULSE is chosen by the user to determine the output pulse width 3. Initialize the CTMU and enable time delay on CTPLS. The pulse width is calculated by generation by setting the TGEN bit. T=(CPULSE/I)*V, where I is known from the current 4. Set EDG1STAT. source measurement step (Section 19.3.1 “Current 5. When CPULSE charges to the value of the voltage Source Calibration”) and V is the internal reference reference trip point, an output pulse is generated voltage (CVREF). on CTPLS. FIGURE 19-4: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC18(L)FXXK22 Device CTMU CTED1 EDG1 CTPLS Current Source Comparator C12IN1- C2 CPULSE CVREF 19.7 Operation During Sleep/Idle 19.7.2 IDLE MODE Modes The behavior of the CTMU in Idle mode is determined by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL 19.7.1 SLEEP MODE AND DEEP SLEEP is cleared, the module will continue to operate in Idle MODES mode. If CTMUSIDL is set, the module’s current source When the device enters any Sleep mode, the CTMU is disabled when the device enters Idle mode. If the module current source is always disabled. If the CTMU module is performing an operation when Idle mode is is performing an operation that depends on the current invoked, in this case, the results will be similar to those source when Sleep mode is invoked, the operation may with Sleep mode. not terminate correctly. Capacitance and time measurements may return erroneous values. 19.8 CTMU Peripheral Module Disable (PMD) When this peripheral is not used, the Peripheral Module Disable bit can be set to disconnect all clock sources to the module, reducing power consumption to an absolute minimum. See Section3.6 “Selective Peripheral Module Control”. DS40001412G-page 322  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 19.9 Effects of a Reset on CTMU 19.10 Registers Upon Reset, all registers of the CTMU are cleared. This There are three control registers for the CTMU: leaves the CTMU module disabled, its current source is • CTMUCONH turned off and all configuration options return to their • CTMUCONL default settings. The module needs to be re-initialized following any Reset. • CTMUICON The CTMUCONH and CTMUCONL registers If the CTMU is in the process of taking a measurement at (Register19-1 and Register19-2) contain control bits the time of Reset, the measurement will be lost. A partial for configuring the CTMU module edge source selec- charge may exist on the circuit that was being measured, tion, edge source polarity selection, edge sequencing, and should be properly discharged before the CTMU makes subsequent attempts to make a measurement. A/D trigger, analog circuit capacitor discharge and enables. The CTMUICON register (Register19-3) has The circuit is discharged by setting and then clearing the IDISSEN bit (CTMUCONH<1>) while the A/D Converter bits for selecting the current source range and current source trim. is connected to the appropriate channel. 19.11 Register Definitions: CTMU Control REGISTER 19-1: CTMUCONH: CTMU CONTROL REGISTER 0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 4 TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation bit 3 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 2 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 1 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 0 CTTRIG: CTMU Special Event Trigger Control Bit 1 = CTMU Special Event Trigger is enabled 0 = CTMU Special Event Trigger is disabled  2010-2016 Microchip Technology Inc. DS40001412G-page 323

PIC18(L)F2X/4XK22 REGISTER 19-2: CTMUCONL: CTMU CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL<1:0> EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = ECCP2 Special Event Trigger bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = ECCP2 Special Event Trigger bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred DS40001412G-page 324  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 19-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM<5:0> IRNG<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current bit 1-0 IRNG<1:0>: Current Source Range Select bits (see Table27-4) 11 = 100  Base current 10 = 10  Base current 01 = Base current level 00 = Current source disabled TABLE 19-1: REGISTERS ASSOCIATED WITH CTMU MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 323 CTMUCONL EDG2POL EDG2SEL<1:0> EDG1POL EDG1SEL<1:0> EDG2STAT EDG1STAT 324 CTMUICON ITRIM<5:0> IRNG<1:0> 325 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD2 — — — — CTMUMD CMP2MD CMP1MD ADCMD 54 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during CTMU operation.  2010-2016 Microchip Technology Inc. DS40001412G-page 325

PIC18(L)F2X/4XK22 20.0 SR LATCH 20.2 Latch Output The module consists of a single SR latch with multiple The SRQEN and SRNQEN bits of the SRCON0 register Set and Reset inputs as well as separate latch outputs. control the Q and Q latch outputs. Both of the SR latch The SR latch module includes the following features: outputs may be directly output to I/O pins at the same time. Control is determined by the state of bits SRQEN • Programmable input selection and SRNQEN in the SRCON0 register. • SR latch output is available internally/externally The applicable TRIS bit of the corresponding port must • Selectable Q and Q output be cleared to enable the port pin output driver. • Firmware Set and Reset The SR latch can be used in a variety of analog 20.3 DIVSRCLK Clock Generation applications, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing The DIVSRCLK clock signal is generated from the applications. peripheral clock which is pre-scaled by a value determined by the SRCLK<2:0> bits. See Figure20-2 20.1 Latch Operation and Table20-1 for additional detail. The latch is a Set-Reset latch that does not depend on a 20.4 Effects of a Reset clock source. Each of the Set and Reset inputs are active-high. The latch can be set or reset by: Upon any device Reset, the SR latch is not initialized, and the SRQ and SRNQ outputs are unknown. The • Software control (SRPS and SRPR bits) user’s firmware is responsible to initialize the latch • Comparator C1 output (sync_C1OUT) output before enabling it to the output pins. • Comparator C2 output (sync_C2OUT) • SRI Pin • Programmable clock (DIVSRCLK) The SRPS and the SRPR bits of the SRCON0 register may be used to set or reset the SR latch, respectively. The latch is Reset-dominant. Therefore, if both Set and Reset inputs are high, the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset operation. The output from Comparator C1 or C2 can be used as the Set or Reset inputs of the SR latch. The output of either Comparator can be synchronized to the Timer1 clock source. See Section18.0 “Comparator Module” and Section12.0 “Timer1/3/5 Module with Gate Control” for more information. An external source on the SRI pin can be used as the Set or Reset inputs of the SR latch. An internal clock source, DIVSRCLK, is available and it can periodically set or reset the SR latch. The SRCLK<2:0> bits in the SRCON0 register are used to select the clock source period. The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to set or reset the SR latch, respectively. DS40001412G-page 326  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 20-1: DIVSRCLK BLOCK DIAGRAM 3 SRCLK<2:0> Programmable SRCLK divider Peripheral 1:4 to 1:512 DIVSRCLK Clock 4-512 cycles ... t0 t0+4 t0+8 t0+12 Tosc SRCLK<2:0> = "001" 1:8 FIGURE 20-2: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRLEN SRPS Pulse SRQEN Gen(2) SRI SRSPE S Q DIVSRCLK SRQ SRSCKE sync_C2OUT(3) SRSC2E sync_C1OUT(3) SR SRSC1E Latch(1) SRPR Pulse Gen(2) SRI SRRPE R Q DIVSRCLK SRNQ SRRCKE SRLEN sync_C2OUT(3) SRNQEN SRRC2E sync_C1OUT(3) SRRC1E Note 1: If R=1 and S=1 simultaneously, Q=0, Q=1 2: Pulse generator causes a pulse width of 2 TOSC clock cycles. 3: Name denotes the connection point at the comparator output.  2010-2016 Microchip Technology Inc. DS40001412G-page 327

PIC18(L)F2X/4XK22 TABLE 20-1: DIVSRCLK FREQUENCY TABLE SRCLK<2:0> Divider FOSC = 20 MHz FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 25.6 s 32 s 64 s 128 s 512 s 110 256 12.8 s 16 s 32 s 64 s 256 s 101 128 6.4 s 8 s 16 s 32 s 128 s 100 64 3.2 s 4 s 8 s 16 s 64 s 011 32 1.6 s 2 s 4 s 8 s 32 s 010 16 0.8 s 1 s 2 s 4 s 16 s 001 8 0.4 s 0.5 s 1 s 2 s 8 s 000 4 0.2 s 0.25 s 0.5 s 1 s 4 s DS40001412G-page 328  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 20.5 Register Definitions: SR Latch Control REGISTER 20-1: SRCON0: SR LATCH CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SRLEN: SR Latch Enable bit(1) 1 = SR latch is enabled 0 = SR latch is disabled bit 6-4 SRCLK<2:0>: SR Latch Clock Divider Bits 000 = Generates a 2 TOSC wide pulse on DIVSRCLK every 4 peripheral clock cycles 001 = Generates a 2 TOSC wide pulse on DIVSRCLK every 8 peripheral clock cycles 010 = Generates a 2 TOSC wide pulse on DIVSRCLK every 16 peripheral clock cycles 011 = Generates a 2 TOSC wide pulse on DIVSRCLK every 32 peripheral clock cycles 100 = Generates a 2 TOSC wide pulse on DIVSRCLK every 64 peripheral clock cycles 101 = Generates a 2 TOSC wide pulse on DIVSRCLK every 128 peripheral clock cycles 110 = Generates a 2 TOSC wide pulse on DIVSRCLK every 256 peripheral clock cycles 111 = Generates a 2 TOSC wide pulse on DIVSRCLK every 512 peripheral clock cycles bit 3 SRQEN: SR Latch Q Output Enable bit 1 = Q is present on the SRQ pin 0 = Q is internal only bit 2 SRNQEN: SR Latch Q Output Enable bit 1 = Q is present on the SRNQ pin 0 = Q is internal only bit 1 SRPS: Pulse Set Input of the SR Latch bit(2) 1 = Pulse set input for two TOSC clock cycles 0 = No effect on set input bit 0 SRPR: Pulse Reset Input of the SR Latch bit(2) 1 = Pulse reset input for two TOSC clock cycles 0 = No effect on Reset input Note 1: Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset inputs of the latch. 2: Set only, always reads back ‘0’.  2010-2016 Microchip Technology Inc. DS40001412G-page 329

PIC18(L)F2X/4XK22 REGISTER 20-2: SRCON1: SR LATCH CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SRI pin status sets SR latch 0 = SRI pin status has no effect on SR latch bit 6 SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR latch is pulsed with DIVSRCLK 0 = Set input of SR latch is not pulsed with DIVSRCLK bit 5 SRSC2E: SR Latch C2 Set Enable bit 1 = C2 Comparator output sets SR latch 0 = C2 Comparator output has no effect on SR latch bit 4 SRSC1E: SR Latch C1 Set Enable bit 1 = C1 Comparator output sets SR latch 0 = C1 Comparator output has no effect on SR latch bit 3 SRRPE: SR Latch Peripheral Reset Enable bit 1 = SRI pin resets SR latch 0 = SRI pin has no effect on SR latch bit 2 SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR latch is pulsed with DIVSRCLK 0 = Reset input of SR latch is not pulsed with DIVSRCLK bit 1 SRRC2E: SR Latch C2 Reset Enable bit 1 = C2 Comparator output resets SR latch 0 = C2 Comparator output has no effect on SR latch bit 0 SRRC1E: SR Latch C1 Reset Enable bit 1 = C1 Comparator output resets SR latch 0 = C1 Comparator output has no effect on SR latch TABLE 20-2: REGISTERS ASSOCIATED WITH THE SR LATCH Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 329 SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 330 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 152 Legend: Shaded bits are not used with this module. DS40001412G-page 330  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 21.0 FIXED VOLTAGE REFERENCE 21.1 Independent Gain Amplifiers (FVR) The output of the FVR supplied to the ADC, Comparators and DAC is routed through an The Fixed Voltage Reference, or FVR, is a stable independent programmable gain amplifier. The voltage reference, independent of VDD, with 1.024V, amplifier can be configured to amplify the 1.024V 2.048V or 4.096V selectable output levels. The output reference voltage by 1x, 2x or 4x, to produce the three of the FVR can be configured to supply a reference possible voltage levels. voltage to the following: The FVRS<1:0> bits of the VREFCON0 register are • ADC input channel used to enable and configure the gain amplifier settings • ADC positive reference for the reference supplied to the DAC and Comparator • Comparator positive input modules. When the ADC module is configured to use • Digital-to-Analog Converter (DAC) the FVR output, (FVR BUF2) the reference is buffered The FVR can be enabled by setting the FVREN bit of through an additional unity gain amplifier. This buffer is the VREFCON0 register. disabled if the ADC is not configured to use the FVR. For specific use of the FVR, refer to the specific module sections: Section17.0 “Analog-to-Digital Converter (ADC) Module”, Section22.0 “Digital-to-Analog Converter (DAC) Module” and Section18.0 “Comparator Module”. 21.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRST bit of the VREFCON0 register will be set. See Table27-3 for the minimum delay requirement. FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM FVR_buf2_enable(1) FVR BUF2 x1 x2 to ADC module x4 FVRS<1:0> 2 FVR BUF1 x1 x2 to Comparators, DAC x4 1.024V + - FVREN Fixed FVRST Voltage Reference Note 1: FVR_buf2_enable = ‘1’ when (ADON = ‘1’)AND [(PVCFG<1:0> = ‘10’) OR ( CHS<4:0> = ‘11111’)]  2010-2016 Microchip Technology Inc. DS40001412G-page 331

PIC18(L)F2X/4XK22 21.3 Register Definitions: FVR Control REGISTER 21-1: VREFCON0: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-1 U-0 U-0 U-0 U-0 FVREN FVRST FVRS<1:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled bit 6 FVRST: Fixed Voltage Reference Ready Flag bit 0 = Fixed Voltage Reference output is not ready or not enabled 1 = Fixed Voltage Reference output is ready for use bit 5-4 FVRS<1:0>: Fixed Voltage Reference Selection bits 00 =Fixed Voltage Reference Peripheral output is off 01 =Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 =Fixed Voltage Reference Peripheral output is 2x (2.048V)(1) 11 = Fixed Voltage Reference Peripheral output is 4x (4.096V)(1) bit 3-2 Reserved: Read as ‘0’. Maintain these bits clear. bit 1-0 Unimplemented: Read as ‘0’. Note1: Fixed Voltage Reference output cannot exceed VDD. TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page VREFCON0 FVREN FVRST FVRS<1:0> — — — — 332 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by the FVR module. DS40001412G-page 332  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 22.0 DIGITAL-TO-ANALOG The negative voltage source is disabled by setting the CONVERTER (DAC) MODULE DACLPS bit in the VREFCON1 register. Clearing the DACLPS bit in the VREFCON1 register disables the The Digital-to-Analog Converter supplies a variable positive voltage source. voltage reference, ratiometric with the input source, with 32 selectable output levels. 22.4 Output Clamped to Positive The input of the DAC can be connected to: Voltage Source • External VREF pins The DAC output voltage can be set to VSRC+ with the • VDD supply voltage least amount of power consumption by performing the • FVR (Fixed Voltage Reference) following: The output of the DAC can be configured to supply a • Clearing the DACEN bit in the VREFCON1 reference voltage to the following: register. • Setting the DACLPS bit in the VREFCON1 • Comparator positive input register. • ADC input channel • Configuring the DACPSS bits to the proper • DACOUT pin positive source. The Digital-to-Analog Converter (DAC) can be enabled • Configuring the DACRx bits to ‘11111’ in the by setting the DACEN bit of the VREFCON1 register. VREFCON2 register. This is also the method used to output the voltage level 22.1 Output Voltage Selection from the FVR to an output pin. See Section22.6 “DAC The DAC has 32 voltage level ranges. The 32 levels Voltage Reference Output” for more information. are set with the DACR<4:0> bits of the VREFCON2 register. 22.5 Output Clamped to Negative Voltage Source The DAC output voltage is determined by the following equations: The DAC output voltage can be set to VSRC- with the least amount of power consumption by performing the EQUATION 22-1: DAC OUTPUT VOLTAGE following: VOUT = VSRC+–VSRC-¥D-----A----C----R2---<5----4---:--0--->--- + VSRC- • Crelgeiasrtienrg. the DACEN bit in the VREFCON1 • Clearing the DACLPS bit in the VREFCON1 VSRC+ = VDD, VREF+ or FVR1 register. • Configuring the DACPSS bits to the proper negative source. VSRC- = VSS or VREF- • Configuring the DACRx bits to ‘00000’ in the VREFCON2 register. 22.2 Ratiometric Output Level This allows the comparator to detect a zero-crossing while not consuming additional current through the DAC The DAC output value is derived using a resistor ladder module. with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage 22.6 DAC Voltage Reference Output of either input source fluctuates, a similar fluctuation will result in the DAC output value. The DAC can be output to the DACOUT pin by setting the DACOE bit of the VREFCON1 register to ‘1’. The value of the individual resistors within the ladder Selecting the DAC reference voltage for output on the can be found in Section27.0 “Electrical DACOUT pin automatically overrides the digital output Specifications”. buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been 22.3 Low-Power Voltage State configured for DAC reference voltage output will always return a ‘0’. In order for the DAC module to consume the least amount of power, one of the two voltage reference input Due to the limited current drive capability, a buffer must sources to the resistor ladder must be disconnected. be used on the DAC voltage reference output for Either the positive voltage source, (VSRC+), or the external connections to DACOUT. Figure22-2 shows negative voltage source, (VSRC-) can be disabled. an example buffering technique.  2010-2016 Microchip Technology Inc. DS40001412G-page 333

PIC18(L)F2X/4XK22 FIGURE 22-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) Reserved 11 FVR BUF1 10 VSRC+ VREF+ 01 DACR<4:0> 5 VDD 00 R 2 R 11111 DACPSS<1:0> 11110 R DACEN DACLPS R R X 32 U Steps 1 M DAC Output o- (to Comparators and 2-t ADC Modules) R 3 R 00001 DACOUT R 00000 DACOE DACNSS VREF- 1 VSRC- VSS 0 FIGURE 22-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC R Module + Voltage DACOUT – Buffered DAC Output Reference Output Impedance DS40001412G-page 334  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 22.7 Operation During Sleep 22.8 Effects of a Reset When the device wakes up from Sleep through an A device Reset affects the following: interrupt or a Watchdog Timer time-out, the contents of • DAC is disabled the VREFCON1 register are not affected. To minimize • DAC output voltage is removed from the current consumption in Sleep mode, the voltage DACOUT pin reference should be disabled. • The DACR<4:0> range select bits are cleared 22.9 Register Definitions: DAC Control REGISTER 22-1: VREFCON1: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 DACLPS: DAC Low-Power Voltage Source Select bit 1 = DAC Positive reference source selected 0 = DAC Negative reference source selected bit 5 DACOE: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin bit 4 Unimplemented: Read as ‘0’ bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits 00 = VDD 01 = VREF+ 10 = FVR BUF1 output 11 = Reserved, do not use bit 1 Unimplemented: Read as ‘0’ bit 0 DACNSS: DAC Negative Source Select bits 1 = VREF- 0 = VSS  2010-2016 Microchip Technology Inc. DS40001412G-page 335

PIC18(L)F2X/4XK22 REGISTER 22-2: VREFCON2: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DACR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR<4:0>: DAC Voltage Output Select bits VOUT = ((VSRC+) - (VSRC-))*(DACR<4:0>/(25)) + VSRC- TABLE 22-1: REGISTERS ASSOCIATED WITH DAC MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page VREFCON0 FVREN FVRST FVRS<1:0> — — — — 332 VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 335 VREFCON2 — — — DACR<4:0> 336 Legend: — = Unimplemented locations, read as ‘0’. Shaded bits are not used by the DAC module. DS40001412G-page 336  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 23.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect Control register (HLVD) (Register23-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned The PIC18(L)F2X/4XK22 devices have a High/Low-Volt- off” by the user under software control, which age Detect module (HLVD). This is a programmable cir- minimizes the current consumption for the device. cuit that sets both a device voltage trip point and the The module’s block diagram is shown in Figure23-1. direction of change from that point. If the device experi- ences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the pro- gram execution branches to the interrupt vector address and the software responds to the interrupt. 23.1 Register - HLVD Control REGISTER 23-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 BGVST: Band Gap Reference Voltages Stable Status Flag bit 1 = Internal band gap voltage references are stable 0 = Internal band gap voltage reference is not stable bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL<3:0>: Voltage Detection Level bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting Note 1: See Table27-5 for specifications.  2010-2016 Microchip Technology Inc. DS40001412G-page 337

PIC18(L)F2X/4XK22 The module is enabled by setting the HLVDEN bit trip point voltage. The “trip point” voltage is the voltage (HLVDCON<4>). Each time the HLVD module is level at which the device detects a high or low-voltage enabled, the circuitry requires some time to stabilize. event, depending on the configuration of the module. The IRVST bit (HLVDCON<5>) is a read-only bit used When the supply voltage is equal to the trip point, the to indicate when the circuit is stable. The module can voltage tapped off of the resistor array is equal to the only generate an interrupt after the circuit is stable and internal reference voltage generated by the voltage IRVST is set. reference module. The comparator then generates an The VDIRMAG bit (HLVDCON<7>) determines the interrupt signal by setting the HLVDIF bit. overall operation of the module. When VDIRMAG is The trip point voltage is software programmable to any of cleared, the module monitors for drops in VDD below a 16 values. The trip point is selected by programming the predetermined set point. When the bit is set, the HLVDL<3:0> bits (HLVDCON<3:0>). module monitors for rises in VDD above the set point. The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an 23.2 Operation external source. This mode is enabled when bits, When the HLVD module is enabled, a comparator uses HLVDL<3:0>, are set to ‘1111’. In this state, the an internally generated reference voltage as the set comparator input is multiplexed from the external input point. The set point is compared with the trip point, pin, HLVDIN. This gives users the flexibility of configur- where each node in the resistor divider represents a ing the High/Low-Voltage Detect interrupt to occur at any voltage in the valid operating range. FIGURE 23-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL<3:0> HLVDCON Register HLVDEN VDIRMAG HLVDIN X Set U M HLVDIF 1 o- 6-t 1 HLVDEN Internal Voltage BOREN Reference 1.024V Typical DS40001412G-page 338  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 23.3 HLVD Setup 23.4 Current Consumption To set up the HLVD module: When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static 1. Select the desired HLVD trip point by writing the current. The total current consumption, when enabled, value to the HLVDL<3:0> bits. is specified in Section27.0 “Electrical 2. Set the VDIRMAG bit to detect high voltage Specifications”. Depending on the application, the (VDIRMAG = 1) or low voltage (VDIRMAG = 0). HLVD module does not need to operate constantly. To 3. Enable the HLVD module by setting the reduce current requirements, the HLVD circuitry may HLVDEN bit. only need to be enabled for short periods where the 4. Clear the HLVD interrupt flag (PIR2<2>), which voltage is checked. After such a check, the module may have been set from a previous interrupt. could be disabled. 5. If interrupts are desired, enable the HLVD interrupt by setting the HLVDIE and GIE/GIEH 23.5 HLVD Start-up Time bits (PIE2<2> and INTCON<7>, respectively). The internal reference voltage of the HLVD module, An interrupt will not be generated until the specified in Section27.0 “Electrical Specifications”, IRVST bit is set. may be used by other internal circuitry, such as the programmable Brown-out Reset. If the HLVD or other circuits using the voltage reference are disabled to Note: Before changing any module settings lower the device’s current consumption, the reference (VDIRMAG, HLVDL<3:0>), first disable the voltage circuit will require time to become stable before module (HLVDEN = 0), make the changes a low or high-voltage condition can be reliably and re-enable the module. This prevents detected. This start-up time, TIRVST, is an interval that the generation of false HLVD events. is independent of device clock speed. The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval (see Figure23-2 or Figure23-3).  2010-2016 Microchip Technology Inc. DS40001412G-page 339

PIC18(L)F2X/4XK22 FIGURE 23-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VDD VHLVD HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal Reference is stable HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists DS40001412G-page 340  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 23-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists 23.6 Applications FIGURE 23-4: TYPICAL LOW-VOLTAGE DETECT APPLICATION In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach VA would indicate a high-voltage detect from, for example, VB 3.3V to 5V (the voltage on USB) and vice versa for a e g detach. This feature could save a design a few extra a t components and an attach signal (input pin). ol V For general battery applications, Figure23-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an ISR, Time TA TB which would allow the application to perform “house- keeping tasks” and a controlled shutdown before the Legend: VA = HLVD trip point device voltage exits the valid operating range at TB. VB = Minimum valid device This would give the application a time window, operating voltage represented by the difference between TA and TB, to safely exit.  2010-2016 Microchip Technology Inc. DS40001412G-page 341

PIC18(L)F2X/4XK22 23.7 Operation During Sleep 23.8 Effects of a Reset When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state. during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off. point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 23-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> 337 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are unused by the HLVD module. DS40001412G-page 342  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 24.0 SPECIAL FEATURES OF THE 24.1 Configuration Bits CPU The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various PIC18(L)F2X/4XK22 devices include several features device configurations. These bits are mapped starting intended to maximize reliability and minimize cost through at program memory location 300000h. elimination of external components. These are: The user will note that address 300000h is beyond the • Oscillator Selection user program memory space. In fact, it belongs to the • Resets: configuration memory space (300000h-3FFFFFh), which - Power-on Reset (POR) can only be accessed using table reads and table writes. - Power-up Timer (PWRT) Programming the Configuration registers is done in a - Oscillator Start-up Timer (OST) manner similar to programming the Flash memory. The - Brown-out Reset (BOR) WR bit in the EECON1 register starts a self-timed write • Interrupts to the Configuration register. In Normal operation • Watchdog Timer (WDT) mode, a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and the • Code Protection data for the Configuration register write. Setting the WR • ID Locations bit starts a long write to the Configuration register. The • In-Circuit Serial Programming™ Configuration registers are written a byte at a time. To The oscillator can be configured for the application write or erase a configuration cell, a TBLWT instruction depending on frequency, power, accuracy and cost. All can write a ‘1’ or a ‘0’ into the cell. For additional details of the options are discussed in detail in Section2.0 on Flash programming, refer to Section6.6 “Writing “Oscillator Module (With Fail-Safe Clock Monitor)”. to Flash Program Memory”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18(L)F2X/4XK22 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. Two- Speed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits.  2010-2016 Microchip Technology Inc. DS40001412G-page 343

PIC18(L)F2X/4XK22 TABLE 24-1: CONFIGURATION BITS AND DEVICE IDs Default/ Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300000h CONFIG1L — — — — — — — — 0000 0000 300001h CONFIG1H IESO FCMEN PRICLKEN PLLCFG FOSC<3:0> 0010 0101 300002h CONFIG2L — — — BORV<1:0> BOREN<1:0> PWRTEN 0001 1111 300003h CONFIG2H — — WDPS<3:0> WDTEN<1:0> 0011 1111 300004h CONFIG3L — — — — — — — — 0000 0000 300005h CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 1011 1111 300006h CONFIG4L DEBUG XINST — — — LVP(1) — STRVEN 1000 0101 300007h CONFIG4H — — — — — — — — 1111 1111 300008h CONFIG5L — — — — CP3(2) CP2(2) CP1 CP0 0000 1111 300009h CONFIG5H CPD CPB — — — — — — 1100 0000 30000Ah CONFIG6L — — — — WRT3(2) WRT2(2) WRT1 WRT0 0000 1111 30000Bh CONFIG6H WRTD WRTB WRTC(3) — — — — — 1110 0000 30000Ch CONFIG7L — — — — EBTR3(2) EBTR2(2) EBTR1 EBTR0 0000 1111 30000Dh CONFIG7H — EBTRB — — — — — — 0100 0000 3FFFFEh DEVID1(4) DEV<2:0> REV<4:0> qqqq qqqq 3FFFFFh DEVID2(4) DEV<10:3> 0101 qqqq Legend: – = unimplemented, q = value depends on condition. Shaded bits are unimplemented, read as '0'. Note 1: Can only be changed when in high voltage programming mode. 2: Available on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices only. 3: In user mode, this bit is read-only and cannot be self-programmed. 4: See Register24-12 and Register24-13 for DEVID values. DEVID registers are read-only and cannot be programmed by the user. DS40001412G-page 344  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 24.2 Register Definitions: Configuration Word REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH R/P-0 R/P-0 R/P-1 R/P-0 R/P-0 R/P-1 R/P-0 R/P-1 IESO FCMEN PRICLKEN PLLCFG FOSC<3:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7 IESO(1): Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN(1): Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5 PRICLKEN: Primary Clock Enable bit 1 = Primary Clock is always enabled 0 = Primary Clock can be disabled by software bit 4 PLLCFG: 4 x PLL Enable bit 1 = 4 x PLL always enabled, Oscillator multiplied by 4 0 = 4 x PLL is under software control, PLLEN (OSCTUNE<6>) bit 3-0 FOSC<3:0>: Oscillator Selection bits 1111 = External RC oscillator, CLKOUT function on RA6 1110 = External RC oscillator, CLKOUT function on RA6 1101 = EC oscillator (low power, <500 kHz) 1100 = EC oscillator, CLKOUT function on OSC2 (low power, <500 kHz) 1011 = EC oscillator (medium power, 500 kHz-16 MHz) 1010 = EC oscillator, CLKOUT function on OSC2 (medium power, 500 kHz-16 MHz) 1001 = Internal oscillator block, CLKOUT function on OSC2 1000 = Internal oscillator block 0111 = External RC oscillator 0110 = External RC oscillator, CLKOUT function on OSC2 0101 = EC oscillator (high power, >16 MHz) 0100 = EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz) 0011= HS oscillator (medium power, 4 MHz-16 MHz) 0010= HS oscillator (high power, >16 MHz) 0001= XT oscillator 0000= LP oscillator Note 1: When FOSC<3:0> is configured for HS, XT, or LP oscillator and FCMEN bit is set, then the IESO bit should also be set to prevent a false failed clock indication and to enable automatic clock switch over from the internal oscillator block to the external oscillator when the OST times out.  2010-2016 Microchip Technology Inc. DS40001412G-page 345

PIC18(L)F2X/4XK22 REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — BORV<1:0>(1) BOREN<1:0>(2) PWRTEN(2) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1) 11 = VBOR set to 1.9V nominal 10 = VBOR set to 2.2V nominal 01 = VBOR set to 2.5V nominal 00 = VBOR set to 2.85V nominal bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits(2) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled Note 1: See Section27.1 “DC Characteristics: Supply Voltage, PIC18(L)F2X/4XK22” for specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. DS40001412G-page 346  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — WDTPS<3:0> WDTEN<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 1-0 WDTEN<1:0>: Watchdog Timer Enable bits 11 = WDT enabled in hardware; SWDTEN bit disabled 10 = WDT controlled by the SWDTEN bit 01 = WDT enabled when device is active, disabled when device is in Sleep; SWDTEN bit disabled 00 = WDT disabled in hardware; SWDTEN bit disabled  2010-2016 Microchip Technology Inc. DS40001412G-page 347

PIC18(L)F2X/4XK22 R EGISTER 24-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6 Unimplemented: Read as ‘0’ bit 5 P2BMX: P2B Input MUX bit 1 = P2B is on RB5(1) P2B is on RD2(2) 0 = P2B is on RC0 bit 4 T3CMX: Timer3 Clock Input MUX bit 1 = T3CKI is on RC0 0 = T3CKI is on RB5 bit 3 HFOFST: HFINTOSC Fast Start-up bit 1 = HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize 0 = The system clock is held off until the HFINTOSC is stable bit 2 CCP3MX: CCP3 MUX bit 1 = CCP3 input/output is multiplexed with RB5 0 = CCP3 input/output is multiplexed with RC6(1) CCP3 input/output is multiplexed with RE0(2) bit 1 PBADEN: PORTB A/D Enable bit 1 = ANSELB<5:0> resets to 1, PORTB<5:0> pins are configured as analog inputs on Reset 0 = ANSELB<5:0> resets to 0, PORTB<4:0> pins are configured as digital I/O on Reset bit 0 CCP2MX: CCP2 MUX bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 Note 1: PIC18(L)F2XK22 devices only. 2: PIC18(L)F4XK22 devices only. DS40001412G-page 348  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 24-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW R/P-1 R/P-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG(2) XINST — — — LVP(1) — STVREN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit(2) 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5-3 Unimplemented: Read as ‘0’ bit 2 LVP: Single-Supply ICSP Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Note 1: Can only be changed by a programmer in high-voltage programming mode. 2: The DEBUG bit is managed automatically by device development tools including debuggers and programmers. For normal device operations, this bit should be maintained as a ‘1’. REGISTER 24-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2(1) CP1 CP0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 not code-protected 0 = Block 3 code-protected bit 2 CP2: Code Protection bit(1) 1 = Block 2 not code-protected 0 = Block 2 code-protected bit 1 CP1: Code Protection bit 1 = Block 1 not code-protected 0 = Block 1 code-protected bit 0 CP0: Code Protection bit 1 = Block 0 not code-protected 0 = Block 0 code-protected Note 1: Available on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices.  2010-2016 Microchip Technology Inc. DS40001412G-page 349

PIC18(L)F2X/4XK22 REGISTER 24-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot Block not code-protected 0 = Boot Block code-protected bit 5-0 Unimplemented: Read as ‘0’ REGISTER 24-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3(1) WRT2(1) WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 not write-protected 0 = Block 3 write-protected bit 2 WRT2: Write Protection bit(1) 1 = Block 2 not write-protected 0 = Block 2 write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 not write-protected 0 = Block 1 write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 not write-protected 0 = Block 0 write-protected Note 1: Available on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices. DS40001412G-page 350  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 REGISTER 24-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot Block not write-protected 0 = Boot Block write-protected bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers not write-protected 0 = Configuration registers write-protected bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode. REGISTER 24-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 not protected from table reads executed in other blocks 0 = Block 3 protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit(1) 1 = Block 2 not protected from table reads executed in other blocks 0 = Block 2 protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 not protected from table reads executed in other blocks 0 = Block 1 protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 not protected from table reads executed in other blocks 0 = Block 0 protected from table reads executed in other blocks Note 1: Available on PIC18(L)FX5K22 and PIC18(L)FX6K22s devices.  2010-2016 Microchip Technology Inc. DS40001412G-page 351

PIC18(L)F2X/4XK22 REGISTER 24-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot Block not protected from table reads executed in other blocks 0 = Boot Block protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ REGISTER 24-12: DEVID1: DEVICE ID REGISTER 1 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-5 DEV<2:0>: Device ID bits These bits, together with DEV<10:3> in DEVID2, determine the device ID. See Table24-2 for complete Device ID list. bit 4-0 REV<4:0>: Revision ID bits These bits indicate the device revision. REGISTER 24-13: DEVID2: DEVICE ID REGISTER 2 R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-0 DEV<10:3>: Device ID bits These bits, together with DEV<2:0> in DEVID1, determine the device ID. See Table24-2 for complete Device ID list. DS40001412G-page 352  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 24-2: DEVICE ID TABLE FOR THE PIC18(L)F2X/4XK22 FAMILY DEV<10:3> DEV<2:0> Part Number 000 PIC18F46K22 001 PIC18LF46K22 0101 0100 010 PIC18F26K22 011 PIC18LF26K22 000 PIC18F45K22 001 PIC18LF45K22 0101 0101 010 PIC18F25K22 011 PIC18LF25K22 000 PIC18F44K22 001 PIC18LF44K22 0101 0110 010 PIC18F24K22 011 PIC18LF24K22 000 PIC18F43K22 001 PIC18LF43K22 0101 0111 010 PIC18F23K22 011 PIC18LF23K22  2010-2016 Microchip Technology Inc. DS40001412G-page 353

PIC18(L)F2X/4XK22 24.3 Watchdog Timer (WDT) For PIC18(L)F2X/4XK22 devices, the WDT is driven by the LFINTOSC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4ms and has the same stability as the LFINTOSC oscillator. The 4ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: a SLEEP or CLRWDT instruction is executed, the IRCF bits of the OSCCON register are changed or a clock failure has occurred. Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits of the OSCCON register clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared. FIGURE 24-1: WDT BLOCK DIAGRAM SWDTEN Enable WDT WDTEN WDT Counter LFINTOSC Source 128 Wake-up from Power Managed Modes Change on IRCF bits Programmable Postscaler Reset WDT CLRWDT Reset 1:1 to 1:32,768 All Device Resets 4 WDTPS<3:0> Sleep DS40001412G-page 354  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 24.3.1 CONTROL REGISTER Register24-14 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to control the WDT when the SWDTEN configuration bits select the software control mode. 24.4 Register Definitions: WDT Control REGISTER 24-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note 1: This bit has no effect if the Configuration bits WDTEN <1,0> are not equal to '10'. TABLE 24-3: REGISTERS ASSOCIATED WITH WATCHDOG TIMER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page RCON IPEN SBOREN — RI TO PD POR BOR 56 WDTCON — — — — — — — SWDTEN 355 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the Watchdog Timer. TABLE 24-4: CONFIGURATION REGISTERS ASSOCIATED WITH WATCHDOG TIMER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page CONFIG2H — — WDPS<3:0> WDTEN<1:0> 347 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the Watchdog Timer.  2010-2016 Microchip Technology Inc. DS40001412G-page 355

PIC18(L)F2X/4XK22 24.5 Program Verification and Each of the blocks has three code protection bits asso- Code Protection ciated with them. They are: • Code-Protect bit (CPn) The overall structure of the code protection on the • Write-Protect bit (WRTn) PIC18 Flash devices differs significantly from other PIC microcontroller devices. • External Block Table Read bit (EBTRn) The user program memory is divided into three or five Figure24-2 shows the program memory organization blocks, depending on the device. One of these is a for 8, 16 and 32-Kbyte devices and the specific code Boot Block of 0.5K or 2K bytes, depending on the protection bit associated with each block. The actual device. The remainder of the memory is divided into locations of the bits are summarized in Table24-5. individual blocks on binary boundaries. FIGURE 24-2: CODE-PROTECTED PROGRAM MEMORY FOR PIC18(L)F2X/4XK22 MEMORY SIZE/DEVICE Block Code Protection 8Kbytes 16Kbytes 32Kbytes 64Kbytes Controlled By: (PIC18(L)FX3K22) (PIC18(L)FX4K22) (PIC18(L)FX5K22) (PIC18(L)FX6K22) Boot Block Boot Block Boot Block Boot Block CPB, WRTB, EBTRB (000h-1FFh) (000h-7FFh) (000h-7FFh) (000h-7FFh) Block 0 Block 0 Block 0 Block 0 CP0, WRT0, EBTR0 (200h-FFFh) (800h-1FFFh) (800h-1FFFh) (800h-3FFFh) Block 1 Block 1 Block 1 Block 1 CP1, WRT1, EBTR1 (1000h-1FFFh) (2000h-3FFFh) (2000h-3FFFh) (4000h-7FFFh) Block 2 Block 2 CP2, WRT2, EBTR2 (4000h-5FFFh) (8000h-BFFFh) Block 3 Block 3 CP3, WRT3, EBTR3 (6000h-7FFFh) (C000h-FFFFh) Unimplemented Unimplemented Read ‘0’s Read ‘0’s (2000h-1FFFFFh) (4000h-1FFFFFh) Unimplemented Unimplemented (Unimplemented Read ‘0’s Read ‘0’s Memory Space) (8000h-1FFFFFh) (10000h-1FFFFFh) TABLE 24-5: CONFIGURATION REGISTERS ASSOCIATED WITH CODE PROTECTION File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3(1) CP2(1) CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3(1) WRT2(1) WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC(2) — — — — — 30000Ch CONFIG7L — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded bits are unimplemented. Note 1: Available on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices only. 2: In user mode, this bit is read-only and cannot be self-programmed. DS40001412G-page 356  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 24.5.1 PROGRAM MEMORY A table read instruction that executes from a location CODE PROTECTION outside of that block is not allowed to read and will result in reading ‘0’s. Figures24-3 through24-5 illustrate table The program memory may be read to or written from write and table read protection. any location using the table read and table write instructions. The device ID may be read with table reads. The Configuration registers may be read and Note: Code protection bits may only be written written with the table read and table write instructions. to a ‘0’ from a ‘1’ state. It is not possible to In Normal execution mode, the CPn bits have no direct write a ‘1’ to a bit in the ‘0’ state. Code pro- effect. CPn bits inhibit external reads and writes. A block tection bits are only set to ‘1’ by a full chip of user memory may be protected from table writes if the erase or block erase function. The full chip WRTn Configuration bit is ‘0’. The EBTRn bits control erase and block erase functions can only table reads. For a block of user memory with the EBTRn be initiated via ICSP™ or an external bit cleared to ‘0’, a table READ instruction that executes programmer. from within that block is allowed to read. FIGURE 24-3: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 01 PC = 001FFEh TBLWT* 001FFFh 002000h WRT1, EBTR1 = 11 003FFFh 004000h PC = 005FFEh TBLWT* WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table writes disabled to Blockn whenever WRTn = 0.  2010-2016 Microchip Technology Inc. DS40001412G-page 357

PIC18(L)F2X/4XK22 FIGURE 24-4: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 001FFFh 002000h PC = 003FFEh TBLRD* WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. FIGURE 24-5: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 PC = 001FFEh TBLRD* 001FFFh 002000h WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. DS40001412G-page 358  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 24.5.2 DATA EEPROM To use the In-Circuit Debugger function of the CODE PROTECTION microcontroller, the design must implement In-Circuit Serial Programming connections to the following pins: The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD • MCLR/VPP/RE3 inhibits external reads and writes of data EEPROM. • VDD WRTD inhibits internal and external writes to data • VSS EEPROM. The CPU can always read data EEPROM • RB7 under normal operation, regardless of the protection bit • RB6 settings. This will interface to the In-Circuit Debugger module 24.5.3 CONFIGURATION REGISTER available from Microchip or one of the third party PROTECTION development tool companies. The Configuration registers can be write-protected. 24.9 Single-Supply ICSP Programming The WRTC bit controls protection of the Configuration registers. In Normal execution mode, the WRTC bit is The LVP Configuration bit enables Single-Supply ICSP readable only. WRTC can only be written via ICSP or Programming (formerly known as Low-Voltage ICSP an external programmer. Programming or LVP). When Single-Supply Program- ming is enabled, the microcontroller can be programmed 24.6 ID Locations without requiring high voltage being applied to the MCLR/VPP/RE3 pin. See “PIC18(L)F2XK22/4XK22 Eight memory locations (200000h-200007h) are Flash Memory Programming” (DS41398) for more designated as ID locations, where the user can store details about low voltage programming. checksum or other code identification numbers. These locations are both readable and writable during normal Note1: High-voltage programming is always execution through the TBLRD and TBLWT instructions available, regardless of the state of the or during program/verify. The ID locations can be read LVP bit, by applying VIHH to the MCLR when the device is code-protected. pin. 2: By default, Single-Supply ICSP is 24.7 In-Circuit Serial Programming enabled in unprogrammed devices (as supplied from Microchip) and erased PIC18(L)F2X/4XK22 devices can be serially devices. programmed while in the end application circuit. This is simply done with two lines for clock and data and three 3: While in Low-Voltage ICSP mode, MCLR other lines for power, ground and the programming is always enabled, regardless of the voltage. This allows customers to manufacture boards MCLRE bit, and the RE3 pin can no with unprogrammed devices and then program the longer be used as a general purpose microcontroller just before shipping the product. This input. also allows the most recent firmware or a custom The LVP bit may be set or cleared only when using firmware to be programmed. standard high-voltage programming (VIHH applied to the MCLR/VPP/RE3 pin). Once LVP has been disabled, 24.8 In-Circuit Debugger only the standard high-voltage programming is When the DEBUG Configuration bit is programmed to available and must be used to program the device. a ‘0’, the In-Circuit Debugger functionality is enabled. Memory that is not code-protected can be erased using This function allows simple debugging functions when either a block erase, or erased row by row, then written used with MPLAB® IDE. When the microcontroller has at any specified VDD. If code-protected memory is to be this feature enabled, some resources are not available erased, a block erase is required. for general use. Table24-6 shows which resources are required by the background debugger. TABLE 24-6: DEBUGGER RESOURCES I/O pins: RB6, RB7  2010-2016 Microchip Technology Inc. DS40001412G-page 359

PIC18(L)F2X/4XK22 25.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: PIC18(L)F2X/4XK22 devices incorporate the standard • A literal value to be loaded into a file register set of 75 PIC18 core instructions, as well as an extended (specified by ‘k’) set of eight new instructions, for the optimization of code that is recursive or that utilizes a software stack. The • The desired FSR register to load the literal value extended set is discussed later in this section. into (specified by ‘f’) • No operand required 25.1 Standard Instruction Set (specified by ‘—’) The control instructions may use some of the following The standard PIC18 instruction set adds many operands: enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from these • A program memory address (specified by ‘n’) PIC® MCU instruction sets. Most instructions are a • The mode of the CALL or RETURN instructions single program memory word (16 bits), but there are (specified by ‘s’) four instructions that require two program memory • The mode of the table read and table write locations. instructions (specified by ‘m’) Each single-word instruction is a 16-bit word divided • No operand required into an opcode, which specifies the instruction type and (specified by ‘—’) one or more operands, which further specify the All instructions are a single word, except for four operation of the instruction. double-word instructions. These instructions were The instruction set is highly orthogonal and is grouped made double-word to contain the required information into four basic categories: in 32 bits. In the second word, the four MSbs are ‘1’s. If this second word is executed as an instruction (by • Byte-oriented operations itself), it will execute as a NOP. • Bit-oriented operations All single-word instructions are executed in a single • Literal operations instruction cycle, unless a conditional test is true or the • Control operations program counter is changed as a result of the instruc- The PIC18 instruction set summary in Table25-2 lists tion. In these cases, the execution takes two instruction byte-oriented, bit-oriented, literal and control cycles, with the additional instruction cycle(s) executed operations. Table25-1 shows the opcode field as a NOP. descriptions. The double-word instructions execute in two instruction Most byte-oriented instructions have three operands: cycles. 1. The file register (specified by ‘f’) One instruction cycle consists of four oscillator periods. 2. The destination of the result (specified by ‘d’) Thus, for an oscillator frequency of 4MHz, the normal 3. The accessed memory (specified by ‘a’) instruction execution time is 1s. If a conditional test is true, or the program counter is changed as a result of The file register designator ‘f’ specifies which file an instruction, the instruction execution time is 2 s. register is to be used by the instruction. The destination Two-word branch instructions (if true) would take 3 s. designator ‘d’ specifies where the result of the opera- Figure25-1 shows the general formats that the tion is to be placed. If ‘d’ is zero, the result is placed in instructions can have. All examples use the convention the WREG register. If ‘d’ is one, the result is placed in ‘nnh’ to represent a hexadecimal number. the file register specified in the instruction. The Instruction Set Summary, shown in Table25-2, All bit-oriented instructions have three operands: lists the standard instructions recognized by the 1. The file register (specified by ‘f’) Microchip Assembler (MPASMTM). 2. The bit in the file register (specified by ‘b’) Section25.1.1 “Standard Instruction Set” provides 3. The accessed memory (specified by ‘a’) a description of each instruction. The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register designator ‘f’ represents the number of the file in which the bit is located. DS40001412G-page 360  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). f 12-bit Register file address (000h to FFFh). This is the source address. s f 12-bit Register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for CALL/BRANCH and RETURN instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for indirect addressing of register files (source). s z 7-bit offset value for indirect addressing of register files (destination). d { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr.  Assigned to. < > Register bit field.  In the set of. italics User defined term (font is Courier).  2010-2016 Microchip Technology Inc. DS40001412G-page 361

PIC18(L)F2X/4XK22 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC DS40001412G-page 362  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and CARRY bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N borrow SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem- ory locations have a valid instruction.  2010-2016 Microchip Technology Inc. DS40001412G-page 363

PIC18(L)F2X/4XK22 TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL k, s Call subroutine 1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO k Go to address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software device Reset 1 0000 0000 1111 1111 All RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem- ory locations have a valid instruction. DS40001412G-page 364  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY  PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem- ory locations have a valid instruction.  2010-2016 Microchip Technology Inc. DS40001412G-page 365

PIC18(L)F2X/4XK22 25.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) + k  W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f)  dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: ADDLW 15h Section25.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. W = 10h After Instruction Words: 1 W = 25h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS40001412G-page 366  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 ADDWFC ADD W and CARRY bit to f ANDLW AND literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0  f  255 Operands: 0  k  255 d [0,1] Operation: (W) .AND. k  W a [0,1] Status Affected: N, Z Operation: (W) + (f) + (C)  dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are AND’ed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the CARRY flag and data mem- Words: 1 ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Decode Read literal Process Write to W If ‘a’ is ‘0’ and the extended instruction ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ANDLW 05Fh mode whenever f 95 (5Fh). See Section25.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = A3h Literal Offset Mode” for details. After Instruction Words: 1 W = 03h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction CARRY bit= 1 REG = 02h W = 4Dh After Instruction CARRY bit= 0 REG = 02h W = 50h  2010-2016 Microchip Technology Inc. DS40001412G-page 367

PIC18(L)F2X/4XK22 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0  f  255 Operands: -128  n  127 d [0,1] Operation: if CARRY bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: (W) .AND. (f)  dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the CARRY bit is ‘1’, then the program Description: The contents of W are AND’ed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’ (default). incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC+2+2n. This instruction is then a GPR bank. 2-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Q Cycle Activity: Section25.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to PC Words: 1 ‘n’ Data Cycles: 1 No No No No operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If CARRY = 1; W = 02h PC = address (HERE + 12) REG = C2h If CARRY = 0; PC = address (HERE + 2) DS40001412G-page 368  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0  f  255 Operands: -128  n  127 0  b  7 Operation: if NEGATIVE bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: 0  f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the NEGATIVE bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank. incremented to fetch the next If ‘a’ is ‘0’ and the extended instruction instruction, the new address will be set is enabled, this instruction operates PC+2+2n. This instruction is then a in Indexed Literal Offset Addressing 2-cycle instruction. mode whenever f 95 (5Fh). See Words: 1 Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1(2) Literal Offset Mode” for details. Q Cycle Activity: Words: 1 If Jump: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC Q Cycle Activity: ‘n’ Data Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No Before Instruction ‘n’ Data operation FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If NEGATIVE = 1; PC = address (Jump) If NEGATIVE = 0; PC = address (HERE + 2)  2010-2016 Microchip Technology Inc. DS40001412G-page 369

PIC18(L)F2X/4XK22 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128  n  127 Operands: -128  n  127 Operation: if CARRY bit is ‘0’ Operation: if NEGATIVE bit is ‘0’ (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the CARRY bit is ‘0’, then the program Description: If the NEGATIVE bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a 2-cycle instruction. 2-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If CARRY = 0; If NEGATIVE = 0; PC = address (Jump) PC = address (Jump) If CARRY = 1; If NEGATIVE = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS40001412G-page 370  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128  n  127 Operands: -128  n  127 Operation: if OVERFLOW bit is ‘0’ Operation: if ZERO bit is ‘0’ (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the OVERFLOW bit is ‘0’, then the Description: If the ZERO bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a 2-cycle instruction. 2-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If OVERFLOW= 0; If ZERO = 0; PC = address (Jump) PC = address (Jump) If OVERFLOW= 1; If ZERO = 1; PC = address (HERE + 2) PC = address (HERE + 2)  2010-2016 Microchip Technology Inc. DS40001412G-page 371

PIC18(L)F2X/4XK22 BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024  n  1023 Operands: 0  f  255 0  b  7 Operation: (PC) + 2 + 2n  PC a [0,1] Status Affected: None Operation: 1  f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incre- mented to fetch the next instruction, the Description: Bit ‘b’ in register ‘f’ is set. new address will be PC+2+2n. This If ‘a’ is ‘0’, the Access Bank is selected. instruction is a 2-cycle instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section25.2.3 “Byte-Oriented and Decode Read literal Process Write to PC Bit-Oriented Instructions in Indexed ‘n’ Data Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah DS40001412G-page 372  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0  f  255 Operands: 0  f  255 0  b  7 0  b < 7 a [0,1] a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a 2-cycle instruction. this a 2-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in set is enabled, this instruction operates Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). mode whenever f 95 (5Fh). See Section25.2.3 “Byte-Oriented and See Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE)  2010-2016 Microchip Technology Inc. DS40001412G-page 373

PIC18(L)F2X/4XK22 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0  f  255 Operands: -128  n  127 0  b < 7 Operation: if OVERFLOW bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: (f<b>)  f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the OVERFLOW bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank. instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC+2+2n. This instruction is then a set is enabled, this instruction operates 2-cycle instruction. in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Section25.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: PORTC = 0110 0101 [65h] Before Instruction PC = address (HERE) After Instruction If OVERFLOW= 1; PC = address (Jump) If OVERFLOW= 0; PC = address (HERE + 2) DS40001412G-page 374  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128  n  127 Operands: 0  k  1048575 s [0,1] Operation: if ZERO bit is ‘1’ (PC) + 2 + 2n  PC Operation: (PC) + 4  TOS, k  PC<20:1>, Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (W)  WS, Description: If the ZERO bit is ‘1’, then the program (Status)  STATUSS, will branch. (BSR)  BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will Encoding: have incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk PC+2+2n. This instruction is then a 19 8 2-cycle instruction. Description: Subroutine call of entire 2-Mbyte memory range. First, return address Words: 1 (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, STATUS and Q Cycle Activity: BSR registers are also pushed into their If Jump: respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs (default). Then, the Decode Read literal Process Write to PC 20-bit value ‘k’ is loaded into PC<20:1>. ‘n’ Data CALL is a 2-cycle instruction. No No No No Words: 2 operation operation operation operation If No Jump: Cycles: 2 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process No Q1 Q2 Q3 Q4 ‘n’ Data operation Decode Read literal PUSH PC to Read literal ‘k’<7:0>, stack ‘k’<19:8>, Example: HERE BZ Jump Write to PC No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction If ZERO = 1; Example: HERE CALL THERE, 1 PC = address (Jump) If ZERO = 0; Before Instruction PC = address (HERE + 2) PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= Status  2010-2016 Microchip Technology Inc. DS40001412G-page 375

PIC18(L)F2X/4XK22 CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0  f  255 Operands: None a [0,1] Operation: 000h  WDT, Operation: 000h  f 000h  WDT postscaler, 1  Z 1  TO, 1  PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the post- If ‘a’ is ‘1’, the BSR is used to select the scaler of the WDT. Status bits, TO and GPR bank. PD, are set. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1 mode whenever f 95 (5Fh). See Q Cycle Activity: Section25.2.3 “Byte-Oriented and Q1 Q2 Q3 Q4 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Decode No Process No operation Data operation Words: 1 Cycles: 1 Example: CLRWDT Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 WDT Counter = ? Decode Read Process Write After Instruction register ‘f’ Data register ‘f’ WDT Counter = 00h WDT Postscaler = 0 TO = 1 Example: CLRF FLAG_REG, 1 PD = 1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h DS40001412G-page 376  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: (f)  dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a 2-cycle GPR bank. instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank. mode whenever f 95 (5Fh). See If ‘a’ is ‘0’ and the extended instruction Section25.2.3 “Byte-Oriented and set is enabled, this instruction operates Bit-Oriented Instructions in Indexed in Indexed Literal Offset Addressing Literal Offset Mode” for details. mode whenever f 95 (5Fh). See Words: 1 Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process Write to Note: 3 cycles if skip and followed register ‘f’ Data destination by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h Q1 Q2 Q3 Q4 W = ECh No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG  W; PC = Address (NEQUAL)  2010-2016 Microchip Technology Inc. DS40001412G-page 377

PIC18(L)F2X/4XK22 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0  f  255 Operands: 0  f  255 a  [0,1] a  [0,1] Operation: (f) –W), Operation: (f) –W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory Description: Compares the contents of data memory location ‘f’ to the contents of the W by location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the , If the contents of ‘f’ are less than the contents of WREG then the fetched contents of W, then the fetched instruction is discarded and a NOP is instruction is discarded and a NOP is executed instead, making this a executed instead, making this a 2-cycle instruction. 2-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Note: 3 cycles if skip and followed Section25.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process No Cycles: 1(2) Note: 3 cycles if skip and followed register ‘f’ Data operation by a 2-word instruction. If skip: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No Decode Read Process No operation operation operation operation register ‘f’ Data operation If skip and followed by 2-word instruction: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; Before Instruction PC = Address (LESS) PC = Address (HERE) If REG  W; W = ? PC = Address (NLESS) After Instruction If REG  W; PC = Address (GREATER) If REG  W; PC = Address (NGREATER) DS40001412G-page 378  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0  f  255 d  [0,1] Operation: If [W<3:0> > 9] or [DC = 1] then a  [0,1] (W<3:0>) + 6  W<3:0>; else Operation: (f) – 1  dest ( W<3:0>)  W<3:0>; Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then Encoding: 0000 01da ffff ffff ( W<7:4>) + 6 + DC  W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the else result is stored in W. If ‘d’ is ‘1’, the (W<7:4>) + DC  W<7:4> result is stored back in register ‘f’ Status Affected: C (default). If ‘a’ is ‘0’, the Access Bank is selected. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the Description: DAW adjusts the 8-bit value in W, result- GPR bank. ing from the earlier addition of two vari- If ‘a’ is ‘0’ and the extended instruction ables (each in packed BCD format) and set is enabled, this instruction operates produces a correct packed BCD result. in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Words: 1 Section25.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write Cycles: 1 register W Data W Q Cycle Activity: Example1: Q1 Q2 Q3 Q4 DAW Decode Read Process Write to Before Instruction register ‘f’ Data destination W = A5h C = 0 DC = 0 Example: DECF CNT, 1, 0 After Instruction Before Instruction W = 05h CNT = 01h Z = 0 C = 1 DC = 0 After Instruction Example 2: CNT = 00h Z = 1 Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0  2010-2016 Microchip Technology Inc. DS40001412G-page 379

PIC18(L)F2X/4XK22 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – 1  dest, Operation: (f) – 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, If the result is not ‘0’, the next which is already fetched, is discarded instruction, which is already fetched, is and a NOP is executed instead, making discarded and a NOP is executed it a 2-cycle instruction. instead, making it a 2-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank. set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing Section25.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See Bit-Oriented Instructions in Indexed Section25.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT - 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT  0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP  0; PC = Address (NZERO) DS40001412G-page 380  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0  k  1048575 Operands: 0  f  255 d  [0,1] Operation: k  PC<20:1> a  [0,1] Status Affected: None Operation: (f) + 1  dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire incremented. If ‘d’ is ‘0’, the result is 2-Mbyte memory range. The 20-bit placed in W. If ‘d’ is ‘1’, the result is value ‘k’ is loaded into PC<20:1>. placed back in register ‘f’ (default). GOTO is always a 2-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 2 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section25.2.3 “Byte-Oriented and Decode Read literal No Read literal Bit-Oriented Instructions in Indexed ‘k’<7:0>, operation ‘k’<19:8>, Literal Offset Mode” for details. Write to PC Words: 1 No No No No operation operation operation operation Cycles: 1 Q Cycle Activity: Example: GOTO THERE Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to PC = Address (THERE) register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1  2010-2016 Microchip Technology Inc. DS40001412G-page 381

PIC18(L)F2X/4XK22 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) + 1  dest, Operation: (f) + 1  dest, skip if result  0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is not ‘0’, the next If the result is ‘0’, the next instruction, instruction, which is already fetched, is which is already fetched, is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a 2-cycle it a 2-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section25.2.3 “Byte-Oriented and Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG  0; PC = Address (ZERO) PC = Address (NZERO) If CNT  0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) DS40001412G-page 382  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) .OR. k  W a  [0,1] Status Affected: N, Z Operation: (W) .OR. (f)  dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is Words: 1 ‘0’, the result is placed in W. If ‘d’ is ‘1’, Cycles: 1 the result is placed back in register ‘f’ Q Cycle Activity: (default). If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to W GPR bank. literal ‘k’ Data If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: IORLW 35h in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Before Instruction Section25.2.3 “Byte-Oriented and W = 9Ah Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = BFh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h  2010-2016 Microchip Technology Inc. DS40001412G-page 383

PIC18(L)F2X/4XK22 LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0  f  2 Operands: 0  f  255 0  k  4095 d  [0,1] a  [0,1] Operation: k  FSRf Operation: f  dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to File Select Register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’ (default). Q Cycle Activity: Location ‘f’ can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read literal Process Write If ‘a’ is ‘1’, the BSR is used to select the ‘k’ MSB Data literal ‘k’ GPR bank. MSB to If ‘a’ is ‘0’ and the extended instruction FSRfH set is enabled, this instruction operates Decode Read literal Process Write literal in Indexed Literal Offset Addressing ‘k’ LSB Data ‘k’ to FSRfL mode whenever f 95 (5Fh). See Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Example: LFSR 2, 3ABh Literal Offset Mode” for details. After Instruction Words: 1 FSR2H = 03h FSR2L = ABh Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write W register ‘f’ Data Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h DS40001412G-page 384  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0  f  4095 Operands: 0  k  255 s 0  f  4095 d Operation: k  BSR Operation: (f )  f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The 8-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffffs Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffffd of BSR<7:4> always remains ‘0’, Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Either source or destination can be W Decode Read Process Write literal (a useful special situation). literal ‘k’ Data ‘k’ to BSR MOVFF is particularly useful for transferring a data memory location to a Example: MOVLB 5 peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h The MOVFF instruction cannot use the After Instruction PCL, TOSU, TOSH or TOSL as the BSR Register = 05h destination register. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h  2010-2016 Microchip Technology Inc. DS40001412G-page 385

PIC18(L)F2X/4XK22 MOVLW Move literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: k  W Operation: (W)  f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The 8-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: MOVLW 5Ah mode whenever f 95 (5Fh). See Section25.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 5Ah Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh DS40001412G-page 386  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 MULLW Multiply literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: (W) x k  PRODH:PRODL Operation: (W) x (f)  PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried 8-bit literal ‘k’. The 16-bit result is out between the contents of W and the placed in the PRODH:PRODL register register file location ‘f’. The 16-bit pair. PRODH contains the high byte. result is stored in the PRODH:PRODL W is unchanged. register pair. PRODH contains the None of the Status flags are affected. high byte. Both W and ‘f’ are Note that neither overflow nor carry is unchanged. possible in this operation. A zero result None of the Status flags are affected. is possible but not detected. Note that neither overflow nor carry is possible in this operation. A zero Words: 1 result is possible but not detected. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is Q Cycle Activity: selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write set is enabled, this instruction literal ‘k’ Data registers operates in Indexed Literal Offset PRODH: Addressing mode whenever PRODL f 95 (5Fh). See Section25.2.3 “Byte-Oriented and Bit-Oriented Example: MULLW 0C4h Instructions in Indexed Literal Offset Mode” for details. Before Instruction Words: 1 W = E2h PRODH = ? Cycles: 1 PRODL = ? Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = E2h PRODH = ADh Decode Read Process Write PRODL = 08h register ‘f’ Data registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h  2010-2016 Microchip Technology Inc. DS40001412G-page 387

PIC18(L)F2X/4XK22 NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0  f  255 Operands: None a  [0,1] Operation: No operation Operation: (f) + 1  f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Decode No No No in Indexed Literal Offset Addressing operation operation operation mode whenever f 95 (5Fh). See Section25.2.3 “Byte-Oriented and Example: Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] DS40001412G-page 388  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC+2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah  2010-2016 Microchip Technology Inc. DS40001412G-page 389

PIC18(L)F2X/4XK22 RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n  PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset by software. address (PC+2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC+2+2n. This instruction is a 2-cycle instruction. Decode Start No No Reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to PC Flags* = Reset Value ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2) DS40001412G-page 390  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 RETFIE Return from Interrupt RETLW Return literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, Operation: k  W, 1  GIE/GIEH or PEIE/GIEL, (TOS)  PC, if s = 1 PCLATU, PCLATH are unchanged (WS)  W, Status Affected: None (STATUSS)  Status, (BSRS)  BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged. Description: W is loaded with the 8-bit literal ‘k’. The Status Affected: GIE/GIEH, PEIE/GIEL. program counter is loaded from the top of the stack (the return address). The Encoding: 0000 0000 0001 000s high address latch (PCLATH) remains Description: Return from interrupt. Stack is popped unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers, WS, Q1 Q2 Q3 Q4 STATUSS and BSRS, are loaded into their corresponding registers, W, Decode Read Process POP PC STATUS and BSR. If ‘s’ = 0, no update literal ‘k’ Data from stack, of these registers occurs (default). Write to W No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS W = WS RETLW kn ; End of table BSR = BSRS Status = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn  2010-2016 Microchip Technology Inc. DS40001412G-page 391

PIC18(L)F2X/4XK22 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s  [0,1] Operands: 0  f  255 d  [0,1] Operation: (TOS)  PC, a  [0,1] if s = 1 (WS)  W, Operation: (f<n>)  dest<n + 1>, (STATUSS)  Status, (f<7>)  C, (BSRS)  BSR, (C)  dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the CARRY popped and the top of the stack (TOS) flag. If ‘d’ is ‘0’, the result is placed in is loaded into the program counter. If W. If ‘d’ is ‘1’, the result is stored back ‘s’= 1, the contents of the shadow in register ‘f’ (default). registers, WS, STATUSS and BSRS, If ‘a’ is ‘0’, the Access Bank is are loaded into their corresponding selected. If ‘a’ is ‘1’, the BSR is used to registers, W, STATUS and BSR. If select the GPR bank. ‘s’ = 0, no update of these registers If ‘a’ is ‘0’ and the extended instruction occurs (default). set is enabled, this instruction operates in Indexed Literal Offset Words: 1 Addressing mode whenever Cycles: 2 f 95 (5Fh). See Section25.2.3 Q Cycle Activity: “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Q1 Q2 Q3 Q4 Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 DS40001412G-page 392  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f<n>)  dest<n + 1>, Operation: (f<n>)  dest<n – 1>, (f<7>)  dest<0> (f<0>)  C, (C)  dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the CARRY stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W. If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘1’, the BSR is used to select the register ‘f’ (default). GPR bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the set is enabled, this instruction operates GPR bank. in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f 95 (5Fh). See set is enabled, this instruction operates Section25.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f 95 (5Fh). See Literal Offset Mode” for details. Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0  2010-2016 Microchip Technology Inc. DS40001412G-page 393

PIC18(L)F2X/4XK22 RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a [0,1] a  [0,1] Operation: FFh  f Operation: (f<n>)  dest<n – 1>, Status Affected: None (f<0>)  dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank. placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected (default), overriding the BSR in Indexed Literal Offset Addressing value. If ‘a’ is ‘1’, then the bank will be mode whenever f 95 (5Fh). See selected as per the BSR value. Section25.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Section25.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG, 1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 DS40001412G-page 394  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 SLEEP Enter Sleep mode SUBFWB Subtract f from W with borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 f 255 d  [0,1] Operation: 00h  WDT, a  [0,1] 0  WDT postscaler, 1  TO, Operation: (W) – (f) – (C) dest 0  PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and CARRY flag Description: The Power-down Status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out Status bit (TO) method). If ‘d’ is ‘0’, the result is stored is set. Watchdog Timer and its posts- in W. If ‘d’ is ‘1’, the result is stored in caler are cleared. register ‘f’ (default). The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is with the oscillator stopped. selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction Q Cycle Activity: operates in Indexed Literal Offset Addressing mode whenever Q1 Q2 Q3 Q4 f 95 (5Fh). See Section25.2.3 Decode No Process Go to “Byte-Oriented and Bit-Oriented operation Data Sleep Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? After Instruction Q1 Q2 Q3 Q4 TO = 1 † Decode Read Process Write to PD = 0 register ‘f’ Data destination Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0  2010-2016 Microchip Technology Inc. DS40001412G-page 395

PIC18(L)F2X/4XK22 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 k 255 Operands: 0 f 255 d  [0,1] Operation: k – (W) W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description W is subtracted from the 8-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the Q Cycle Activity: result is stored back in register ‘f’ (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is Decode Read Process Write to W selected. If ‘a’ is ‘1’, the BSR is used literal ‘k’ Data to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction Before Instruction operates in Indexed Literal Offset W = 01h Addressing mode whenever C = ? f 95 (5Fh). See Section25.2.3 After Instruction W = 01h “Byte-Oriented and Bit-Oriented C = 1 ; result is positive Instructions in Indexed Literal Offset Z = 0 Mode” for details. N = 0 Words: 1 Example 2: SUBLW 02h Cycles: 1 Before Instruction W = 02h Q Cycle Activity: C = ? Q1 Q2 Q3 Q4 After Instruction W = 00h Decode Read Process Write to C = 1 ; result is zero register ‘f’ Data destination Z = 1 N = 0 Example 1: SUBWF REG, 1, 0 Example 3: SUBLW 02h Before Instruction REG = 3 Before Instruction W = 2 W = 03h C = ? C = ? After Instruction After Instruction REG = 1 W = FFh ; (2’s complement) W = 2 C = 0 ; result is negative C = 1 ; result is positive Z = 0 Z = 0 N = 1 N = 0 Example 2: SUBWF REG, 0, 0 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 DS40001412G-page 396  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: (f<3:0>)  dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>)  dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the CARRY flag Encoding: 0011 10da ffff ffff (borrow) from register ‘f’ (2’s comple- Description: The upper and lower nibbles of register ment method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is ‘f’ are exchanged. If ‘d’ is ‘0’, the result stored back in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section25.2.3 “Byte-Oriented and Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1100) After Instruction W = 0Dh (0000 1101) C = 1 REG = 35h Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1110) C = 1 After Instruction REG = F5h (1111 0101) ; [2’s comp] W = 0Eh (0000 1110) C = 0 Z = 0 N = 1 ; result is negative  2010-2016 Microchip Technology Inc. DS40001412G-page 397

PIC18(L)F2X/4XK22 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR))  TABLAT; MEMORY (00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR))  TABLAT; TBLPTR = 00A357h (TBLPTR) + 1  TBLPTR; Example2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR))  TABLAT; Before Instruction (TBLPTR) – 1  TBLPTR; TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY (01A357h) = 12h (TBLPTR) + 1  TBLPTR; MEMORY (01A358h) = 34h (Prog Mem (TBLPTR))  TABLAT; After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write TABLAT) Memory) DS40001412G-page 398  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT)  Holding Register; TBLPTR = 00A356h TBLPTR – No Change; HOLDING REGISTER (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT)  Holding Register; TABLAT = 55h (TBLPTR) + 1  TBLPTR; TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT)  Holding Register; (00A356h) = 55h (TBLPTR) – 1  TBLPTR; Example 2: TBLWT +*; if TBLWT+*, (TBLPTR) + 1  TBLPTR; Before Instruction (TABLAT)  Holding Register; TABLAT = 34h TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the three LSBs of (01389Ah) = FFh TBLPTR to determine which of the eight HOLDING REGISTER holding registers the TABLAT is written to. (01389Bh) = 34h The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section6.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register )  2010-2016 Microchip Technology Inc. DS40001412G-page 399

PIC18(L)F2X/4XK22 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0  f  255 Operands: 0 k 255 a  [0,1] Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a 2-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Decode Read Process Write to W in Indexed Literal Offset Addressing literal ‘k’ Data mode whenever f 95 (5Fh). See Section25.2.3 “Byte-Oriented and Example: XORLW 0AFh Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Before Instruction W = B5h Words: 1 After Instruction Cycles: 1(2) W = 1Ah Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT  00h, PC = Address (NZERO) DS40001412G-page 400  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h  2010-2016 Microchip Technology Inc. DS40001412G-page 401

PIC18(L)F2X/4XK22 25.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table25-3. Detailed In addition to the standard 75 instructions of the PIC18 descriptions are provided in Section25.2.2 instruction set, PIC18(L)F2X/4XK22 devices also “Extended Instruction Set”. The opcode field provide an optional extension to the core CPU descriptions in Table25-1 apply to both the standard functionality. The added features include eight and extended PIC18 instruction sets. additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of Note: The instruction set extension and the the standard PIC18 instructions. Indexed Literal Offset Addressing mode The additional features of the extended instruction set were designed for optimizing applications are disabled by default. To enable them, users must set written in C; the user may likely never use the XINST Configuration bit. these instructions directly in assembler. The syntax for these commands is pro- The instructions in the extended set can all be vided as a reference for users who may be classified as literal operations, which either manipulate reviewing code that has been generated the File Select Registers, or use them for indexed by a compiler. addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation 25.2.1 EXTENDED INSTRUCTION SYNTAX for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. Most of the extended instructions use indexed arguments, using one of the File Select Registers and The extended instructions are specifically implemented some offset to specify a source or destination register. to optimize re-entrant program code (that is, code that When an argument for an instruction serves as part of is recursive or that uses a software stack) written in indexed addressing, it is enclosed in square brackets high-level languages, particularly C. Among other (“[ ]”). This is done to indicate that the argument is used things, they allow users working in high-level as an index or offset. MPASM™ Assembler will flag an languages to perform certain operations on data error if it determines that an index or offset value is not structures more efficiently. These include: bracketed. • dynamic allocation and deallocation of software When the extended instruction set is enabled, brackets stack space when entering and leaving are also used to indicate index arguments in byte- subroutines oriented and bit-oriented instructions. This is in addition • function pointer invocation to other changes in their syntax. For more details, see • software Stack Pointer manipulation Section25.2.3.1 “Extended Instruction Syntax with • manipulation of variables located in a software Standard PIC18 Commands”. stack Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 25-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add literal to FSR2 and return 2 1110 1000 11kk kkkk None CALLW Call subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz PUSHL k Store literal at FSR2, 1 1110 1010 kkkk kkkk None decrement FSR2 SUBFSR f, k Subtract literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract literal from FSR2 and 2 1110 1001 11kk kkkk None return DS40001412G-page 402  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 25.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 + k  FSR2, Operation: FSR(f) + k  FSR(f) (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during Q1 Q2 Q3 Q4 the second cycle. Decode Read Process Write to This may be thought of as a special literal ‘k’ Data FSR case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Example: ADDFSR 2, 23h Words: 1 Before Instruction Cycles: 2 FSR2 = 03FFh After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).  2010-2016 Microchip Technology Inc. DS40001412G-page 403

PIC18(L)F2X/4XK22 CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0  z  127 s 0  f  4095 Operation: (PC + 2)  TOS, d (W)  PCL, Operation: ((FSR2) + z )  f s d (PCLATH)  PCH, Status Affected: None (PCLATU)  PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’ in the first word to the value of s latched into PCH and PCU, FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘f ’ in the second word. Both addresses d new next instruction is fetched. can be anywhere in the 4096-byte data Unlike CALL, there is no option to space (000h to FFFh). update W, Status or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an indirect addressing register, the value returned will be 00h. Q1 Q2 Q3 Q4 Decode Read PUSH PC to No Words: 2 WREG stack operation Cycles: 2 No No No No Q Cycle Activity: operation operation operation operation Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Decode No No Write Before Instruction operation operation register ‘f’ PC = address (HERE) PCLATH = 10h No dummy (dest) PCLATU = 00h read W = 06h After Instruction PC = 001006h Example: MOVSF [05h], REG2 TOS = address (HERE + 2) PCLATH = 10h Before Instruction PCLATU = 00h FSR2 = 80h W = 06h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h DS40001412G-page 404  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0  zs  127 Operands: 0k  255 0  z  127 d Operation: k  (FSR2), Operation: ((FSR2) + zs)  ((FSR2) + zd) FSR2 – 1  FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1111 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. FSR2 Description The contents of the source register are is decremented by 1 after the operation. moved to the destination register. The This instruction allows users to push values addresses of the source and destination onto a software stack. registers are determined by adding the 7-bit literal offsets ‘z ’ or ‘z ’, Words: 1 s d respectively, to the value of FSR2. Both Cycles: 1 registers can be located anywhere in the 4096-byte data memory space Q Cycle Activity: (000h to FFFh). Q1 Q2 Q3 Q4 The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to PCL, TOSU, TOSH or TOSL as the data destination destination register. If the resultant source address points to an indirect addressing register, the Example: PUSHL 08h value returned will be 00h. If the resultant destination address points to Before Instruction an indirect addressing register, the FSR2H:FSR2L = 01ECh Memory (01ECh) = 00h instruction will execute as a NOP. Words: 2 After Instruction FSR2H:FSR2L = 01EBh Cycles: 2 Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h  2010-2016 Microchip Technology Inc. DS40001412G-page 405

PIC18(L)F2X/4XK22 SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 – k  FSR2 Operation: FSR(f) – k  FSRf (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified by contents of the FSR2. A RETURN is then ‘f’. executed by loading the PC with the TOS. Words: 1 The instruction takes two cycles to execute; a NOP is performed during the Cycles: 1 second cycle. Q Cycle Activity: This may be thought of as a special case of Q1 Q2 Q3 Q4 the SUBFSR instruction, where f = 3 (binary Decode Read Process Write to ‘11’); it operates only on FSR2. register ‘f’ Data destination Words: 1 Cycles: 2 Q Cycle Activity: Example: SUBFSR 2, 23h Q1 Q2 Q3 Q4 Before Instruction FSR2 = 03FFh Decode Read Process Write to register ‘f’ Data destination After Instruction FSR2 = 03DCh No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) DS40001412G-page 406  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 25.2.3 BYTE-ORIENTED AND 25.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file register argument, ‘f’, in the standard byte-oriented and bit-oriented commands is replaced with the literal offset Note: Enabling the PIC18 instruction set value, ‘k’. As already noted, this occurs only when ‘f’ is extension may cause legacy applications less than or equal to 5Fh. When an offset value is used, to behave erratically or fail entirely. it must be indicated by square brackets (“[ ]”). As with the extended instructions, the use of brackets indicates In addition to eight new commands in the extended set, to the compiler that the value is to be interpreted as an enabling the extended instruction set also enables index or an offset. Omitting the brackets, or using a Indexed Literal Offset Addressing mode (Section5.7.1 value greater than 5Fh within brackets, will generate an “Indexed Addressing with Literal Offset”). This has error in the MPASM assembler. a significant impact on the way that many commands of If the index argument is properly bracketed for Indexed the standard PIC18 instruction set are interpreted. Literal Offset Addressing, the Access RAM argument is When the extended set is disabled, addresses never specified; it will automatically be assumed to be embedded in opcodes are treated as literal memory ‘0’. This is in contrast to standard operation (extended locations: either as a location in the Access Bank (‘a’ = instruction set disabled) when ‘a’ is set on the basis of 0), or in a GPR bank designated by the BSR (‘a’ = 1). the target address. Declaring the Access RAM bit in When the extended instruction set is enabled and ‘a’ = this mode will also generate an error in the MPASM 0, however, a file register argument of 5Fh or less is assembler. interpreted as an offset from the pointer value in FSR2 The destination argument, ‘d’, functions as before. and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit In the latest versions of the MPASM™ assembler, as an argument – that is, all byte-oriented and bit- language support for the extended instruction set must oriented instructions, or almost half of the core PIC18 be explicitly invoked. This is done with either the instructions – may behave differently when the command line option, /y, or the PE directive in the extended instruction set is enabled. source listing. When the content of FSR2 is 00h, the boundaries of the 25.2.4 CONSIDERATIONS WHEN Access RAM are essentially remapped to their original ENABLING THE EXTENDED values. This may be useful in creating backward INSTRUCTION SET compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it It is important to note that the extensions to the instruc- when moving back and forth between C and assembly tion set may not be beneficial to all users. In particular, routines in order to preserve the Stack Pointer. Users users who are not writing code that uses a software must also keep in mind the syntax requirements of the stack may not benefit from using the extensions to the extended instruction set (see Section25.2.3.1 instruction set. “Extended Instruction Syntax with Standard PIC18 Additionally, the Indexed Literal Offset Addressing Commands”). mode may create issues with legacy applications Although the Indexed Literal Offset Addressing mode written to the PIC18 assembler. This is because can be very useful for dynamic stack and pointer instructions in the legacy code may attempt to address manipulation, it can also be very annoying if a simple registers in the Access Bank below 5Fh. Since these arithmetic operation is carried out on the wrong addresses are interpreted as literal offsets to FSR2 register. Users who are accustomed to the PIC18 when the instruction set extension is enabled, the programming must keep in mind that, when the application may read or write to the wrong data extended instruction set is enabled, register addresses addresses. of 5Fh or less are used for Indexed Literal Offset When porting an application to the PIC18(L)F2X/ Addressing. 4XK22, it is very important to consider the type of code. Representative examples of typical byte-oriented and A large, re-entrant application that is written in ‘C’ and bit-oriented instructions in the Indexed Literal Offset would benefit from efficient compilation will do well Addressing mode are provided on the following page to when using the instruction set extensions. Legacy show how execution is affected. The operand condi- applications that heavily use the Access Bank will most tions shown in the examples are applicable to all likely not benefit from using the extended instruction instructions of these types. set.  2010-2016 Microchip Technology Inc. DS40001412G-page 407

PIC18(L)F2X/4XK22 ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0  k  95 Operands: 0  f  95 d  [0,1] 0  b  7 Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in Cycles: 1 register ‘f’ (default). Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Example: ADDWF [OFST], 0 Contents of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction W = 37h Set Indexed Contents SETF of 0A2Ch = 20h (Indexed Literal Offset mode) Syntax: SETF [k] Operands: 0  k  95 Operation: FFh  ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh DS40001412G-page 408  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 25.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18(L)F2X/4XK22 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is ‘0’, disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: • A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project • A command line option • A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information.  2010-2016 Microchip Technology Inc. DS40001412G-page 409

PIC18(L)F2X/4XK22 26.0 DEVELOPMENT SUPPORT 26.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker DS40001412G-page 410  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 26.2 MPLAB XC Compilers 26.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 26.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 26.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process  2010-2016 Microchip Technology Inc. DS40001412G-page 411

PIC18(L)F2X/4XK22 26.6 MPLAB X SIM Software Simulator 26.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 26.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 26.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 26.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS40001412G-page 412  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 26.11 Demonstration/Development 26.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2010-2016 Microchip Technology Inc. DS40001412G-page 413

PIC18(L)F2X/4XK22 27.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, and MCLR)...................................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS PIC18LF24K22......................................................................................................... -0.3V to +4.5V PIC18(L)F26K22....................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to VSS (Note 2)...........................................................................................0V to +11.0V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin (-40°C to +85°C)............................................................................................... 300mA Maximum current out of VSS pin (+85°C to +125°C)............................................................................................ 125 mA Maximum current into VDD pin (-40°C to +85°C)...................................................................................................200mA Maximum current into VDD pin (+85°C to +125°C) .................................................................................................85 mA Input clamp current, IIK (VI < 0 or VI > VDD)20mA Output clamp current, IOK (VO < 0 or VO > VDD)20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin.....................................................................................................25mA Maximum current sunk byall ports (-40°C to +85°C)........................................................................................... 200mA Maximum current sunk byall ports (+85°C to +125°C).........................................................................................110mA Maximum current sourced by all ports (-40°C to +85°C).......................................................................................185mA Maximum current sourced by all ports (+85°C to +125°C)......................................................................................70mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP/ RE3 pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DS40001412G-page 414  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 27-1: PIC18LF2X/4XK22 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL TEMPERATURE) 5.5V 5.0V e 4.0V g a olt 3.6V V 3.0V 2.7V 2.3V 1.8V 10 16 20 30 40 48 60 64 Frequency (MHz) Note1: Maximum Frequency 20 MHz, 1.8V to 2.7V, -40°C to +85°C 2: Maximum Frequency 64 MHz, 2.7V to 3.6V, -40°C to +85°C FIGURE 27-2: PIC18LF2X/4XK22 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE) 5.5V 5.0V e 4.0V g a olt 3.6V V 3.0V 2.7V 2.3V 1.8V 10 16 20 30 40 48 60 64 Frequency (MHz) Note1: Maximum Frequency 16 MHz, 1.8V to 2.7V, +85°C to +125°C 2: Maximum Frequency 48 MHz, 2.7V to 3.6V, +85°C to +125°C  2010-2016 Microchip Technology Inc. DS40001412G-page 415

PIC18(L)F2X/4XK22 FIGURE 27-3: PIC18F2X/4XK22 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL TEMPERATURE) 5.5V 5.0V e 4.0V g a olt 3.6V V 3.0V 2.7V 2.3V 1.8V 10 16 20 30 40 48 60 64 Frequency (MHz) Note1: Maximum Frequency 20 MHz, 2.3V to 2.7V, -40°C to +85°C 2: Maximum Frequency 64 MHz, 2.7V to 5.5V, -40°C to +85°C FIGURE 27-4: PIC18F2X/4XK22 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE) 5.5V 5.0V e 4.0V g a olt 3.6V V 3.0V 2.7V 2.3V 1.8V 10 16 20 30 40 48 60 64 Frequency (MHz) Note1: Maximum Frequency 16 MHz, 2.3V to 2.7V, +85°C to +125°C 2: Maximum Frequency 48 MHz, 2.7V to 5.5V, +85°C to +125°C DS40001412G-page 416  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 27.1 DC Characteristics: Supply Voltage, PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise PIC18(L)F2X/4XK22 stated) Operating temperature -40°C  TA  +125°C Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage PIC18LF2X/4XK22 1.8 — 3.6 V PIC18F2X/4XK22 2.3 — 5.5 V D002 VDR RAM Data Retention Voltage(1) 1.5 — — V D003 VPOR VDD Start Voltage to ensure internal — — 0.7 V See section on Power-on Reset Power-on Reset signal for details D004 SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See section on Power-on Reset Power-on Reset signal for details D005 VBOR Brown-out Reset Voltage BORV<1:0> = 11(2) 1.75 1.9 2.05 V BORV<1:0> = 10 2.05 2.2 2.35 V BORV<1:0> = 01 2.35 2.5 2.65 V BORV<1:0> = 00(3) 2.65 2.85 3.05 V Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: On PIC18(L)F2X/4XK22 devices with BOR enabled, operation is supported until a BOR occurs. This is valid although VDD may be below the minimum rated supply voltage. 3: With BOR enabled, full-speed operation (FOSC = 64 MHz or 48 MHz) is supported until a BOR occurs. This is valid although VDD may be below the minimum voltage for this frequency.  2010-2016 Microchip Technology Inc. DS40001412G-page 417

PIC18(L)F2X/4XK22 27.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) PIC18LF2X/4XK22 Operating temperature -40°C  TA  +125°C Standard Operating Conditions (unless otherwise stated) PIC18F2X/4XK22 Operating temperature -40°C  TA  +125°C Param Typ Typ Max Max Conditions Device Characteristics Units No. +25°C +60°C +85°C +125°C VDD Notes Power-down Base Current (IPD)(1) D006 Sleep mode 0.01 0.04 2 10 A 1.8V WDT, BOR, FVR and SOSC disabled, all 0.01 0.06 2 10 A 3.0V Peripherals inactive 12 13 25 35 A 2.3V 13 14 30 40 A 3.0V 13 14 35 50 A 5.0V Power-down Module Differential Current (delta IPD) D007 Watchdog Timer 0.3 0.3 2.5 2.5 A 1.8V 0.5 0.5 2.5 2.5 A 3.0V 0.35 0.35 5.0 5.0 A 2.3V 0.5 0.5 5.0 5.0 A 3.0V 0.5 0.5 5.0 5.0 A 5.0V D008 Brown-out Reset(2) 8 8.5 15 16 A 2.0V 9 9.5 15 16 A 3.0V 3.4 3.4 15 16 A 2.3V 3.8 3.8 15 16 A 3.0V 5.2 5.2 15 16 A 5.0V D010 High/Low Voltage Detect(2) 6.5 6.7 15 15 A 2.0V 7 7.5 15 15 A 3.0V 2.1 2.1 15 15 A 2.3V 2.4 2.4 15 15 A 3.0V 3.2 3.2 15 15 A 5.0V D011 Secondary Oscillator 0.5 1 3 10 A 1.8V 0.6 1.1 4 10 A 3.0V 32 kHz on SOSC 0.5 1 3 10 A 2.3V 0.6 1.1 4 10 A 3.0V 0.6 1.1 5 10 A 5.0V Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: On PIC18LF2X/4XK22 the BOR, HLVD and FVR enable internal band gap reference. With more than one of these modules enabled, the current consumption will be less than the sum of the specifications. On PIC18F2X/4XK22, the internal band gap reference is always enabled and its current consumption is included in the Power-down Base Current (IPD). 3: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the FRC turn off as soon as conversion (if any) is complete. DS40001412G-page 418  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 27.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/4XK22 (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LF2X/4XK22 Operating temperature -40°C  TA  +125°C Standard Operating Conditions (unless otherwise stated) PIC18F2X/4XK22 Operating temperature -40°C  TA  +125°C Param Typ Typ Max Max Conditions Device Characteristics Units No. +25°C +60°C +85°C +125°C VDD Notes D015 Comparators 7 7 18 18 A 1.8V 7 7 18 18 A 3.0V LP mode 7 7 18 18 A 2.3V 7 7 18 18 A 3.0V 8 8 20 20 A 5.0V D016 Comparators 38 38 95 95 A 1.8V 40 40 105 105 A 3.0V HP mode 39 39 95 95 A 2.3V 40 40 105 105 A 3.0V 40 40 105 105 A 5.0V D017 DAC 14 14 25 25 A 2.0V 20 20 35 35 A 3.0V 15 15 30 30 A 2.3V 20 20 35 35 A 3.0V 32 32 60 60 A 5.0V D018 FVR(2) 15 16 25 25 A 1.8V 15 16 25 25 A 3.0V 28 28 45 45 A 2.3V 31 31 55 55 A 3.0V 66 66 100 100 A 5.0V D013 A/D Converter(3) 185 185 370 370 A 1.8V 210 210 400 400 A 3.0V A/D on, not converting 200 200 380 380 A 2.3V 210 210 400 400 A 3.0V 250 250 450 450 A 5.0V Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: On PIC18LF2X/4XK22 the BOR, HLVD and FVR enable internal band gap reference. With more than one of these modules enabled, the current consumption will be less than the sum of the specifications. On PIC18F2X/4XK22, the internal band gap reference is always enabled and its current consumption is included in the Power-down Base Current (IPD). 3: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the FRC turn off as soon as conversion (if any) is complete.  2010-2016 Microchip Technology Inc. DS40001412G-page 419

PIC18(L)F2X/4XK22 27.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) PIC18LF2X/4XK22 Operating temperature -40°C  TA  +125°C Standard Operating Conditions (unless otherwise stated) PIC18F2X/4XK22 Operating temperature -40°C  TA  +125°C Param Device Characteristics Typ Max Units Conditions No. D020 Supply Current (IDD)(1),(2) 3.6 23 A -40°C VDD = 1.8V FOSC = 31kHz (RC_RUN mode, 3.9 25 A +25°C LFINTOSC 3.9 — A +60°C source) 3.9 28 A +85°C 4.0 30 A 125°C D021 8.1 26 A -40°C VDD = 3.0V 8.4 30 A +25°C 8.6 — A +60°C 8.7 35 A +85°C 10.7 40 A +125°C D022 16 35 A -40°C VDD = 2.3V FOSC = 31kHz (RC_RUN mode, 17 35 A +25°C LFINTOSC 18 35 A +85°C source) 19 50 A +125°C D023 18 50 A -40°C VDD = 3.0V 20 50 A +25°C 21 50 A +85°C 22 60 A +125°C D024 19 55 A -40°C VDD = 5.0V 21 55 A +25°C 22 55 A +85°C 23 70 A +125°C D025 0.14 0.25 mA -40°C to +125°C VDD = 1.8V FOSC = 500kHz (RC_RUN mode, D026 0.17 0.30 mA -40°C to +125°C VDD = 3.0V MFINTOSC source) D027 0.18 0.25 mA -40°C to +125°C VDD = 2.3V FOSC = 500kHz (RC_RUN mode, D028 0.20 0.30 mA -40°C to +125°C VDD = 3.0V MFINTOSC D029 0.25 0.35 mA -40°C to +125°C VDD = 5.0V source) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS40001412G-page 420  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 27.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/4XK22 (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LF2X/4XK22 Operating temperature -40°C  TA  +125°C Standard Operating Conditions (unless otherwise stated) PIC18F2X/4XK22 Operating temperature -40°C  TA  +125°C Param Device Characteristics Typ Max Units Conditions No. D030 0.35 0.50 mA -40°C to +125°C VDD = 1.8V FOSC = 1MHz (RC_RUN mode, D031 0.45 0.65 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D032 0.40 0.60 mA -40°C to +125°C VDD = 2.3V FOSC = 1MHz (RC_RUN mode, D033 0.50 0.65 mA -40°C to +125°C VDD = 3.0V HFINTOSC D034 0.55 0.75 mA -40°C to +125°C VDD = 5.0V source) D035 1.3 2.0 mA -40°C to +125°C VDD = 1.8V FOSC = 16MHz (RC_RUN mode, D036 2.2 3.0 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D037 1.7 2.0 mA -40°C to +125°C VDD = 2.3V FOSC = 16MHz (RC_RUN mode, D038 2.2 3.0 mA -40°C to +125°C VDD = 3.0V HFINTOSC D039 2.5 3.5 mA -40°C to +125°C VDD = 5.0V source) D041 6.2 8.5 mA -40°C to +125°C VDD = 3.0V FOSC = 64MHz (RC_RUN mode, HFINTOSC + PLL source) D043 6.2 8.5 mA -40°C to +125°C VDD = 3.0V FOSC = 64MHz (RC_RUN mode, D044 6.8 9.5 mA -40°C to +125°C VDD = 5.0V HFINTOSC + PLL source) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2010-2016 Microchip Technology Inc. DS40001412G-page 421

PIC18(L)F2X/4XK22 27.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) PIC18LF2X/4XK22 Operating temperature -40°C  TA  +125°C Standard Operating Conditions (unless otherwise stated) PIC18F2X/4XK22 Operating temperature -40°C  TA  +125°C Param Device Characteristics Typ Max Units Conditions No. D045 Supply Current (IDD)(1),(2) 0.5 18 A -40°C VDD = 1.8V FOSC = 31kHz (RC_IDLE mode, 0.6 18 A +25°C LFINTOSC source) 0.7 — A +60°C 0.75 20 A +85°C 2.3 22 A +125°C D046 1.1 20 A -40°C VDD = 3.0V 1.2 20 A +25°C 1.3 — A +60°C 1.4 22 A +85°C 3.2 25 A +125°C D047 17 30 A -40°C VDD = 2.3V FOSC = 31kHz (RC_IDLE mode, 13 30 A +25°C LFINTOSC source) 14 30 A +85°C 15 45 A +125°C D048 19 35 A -40°C VDD = 3.0V 15 35 A +25°C 16 35 A +85°C 17 50 A +125°C D049 21 40 A -40°C VDD = 5.0V 15 40 A +25°C 16 40 A +85°C 18 60 A +125°C D050 0.11 0.20 mA -40°C to +125°C VDD = 1.8V FOSC = 500kHz (RC_IDLE mode, D051 0.12 0.25 mA -40°C to +125°C VDD = 3.0V MFINTOSC source) D052 0.14 0.21 mA -40°C to +125°C VDD = 2.3V FOSC = 500kHz (RC_IDLE mode, D053 0.15 0.25 mA -40°C to +125°C VDD = 3.0V MFINTOSC source) D054 0.20 0.31 mA -40°C to +125°C VDD = 5.0V Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS40001412G-page 422  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 27.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/4XK22 (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LF2X/4XK22 Operating temperature -40°C  TA  +125°C Standard Operating Conditions (unless otherwise stated) PIC18F2X/4XK22 Operating temperature -40°C  TA  +125°C Param Device Characteristics Typ Max Units Conditions No. D055 0.25 0.40 mA -40°C to +125°C VDD = 1.8V FOSC = 1MHz (RC_IDLE mode, D056 0.35 0.50 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D057 0.30 0.45 mA -40°C to +125°C VDD = 2.3V FOSC = 1MHz (RC_IDLE mode, D058 0.40 0.50 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D059 0.45 0.60 mA -40°C to +125°C VDD = 5.0V D060 0.50 0.7 mA -40°C to +125°C VDD = 1.8V FOSC = 16MHz (RC_IDLE mode, D061 0.80 1.1 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D062 0.65 1.0 mA -40°C to +125°C VDD = 2.3V FOSC = 16MHz (RC_IDLE mode, D063 0.80 1.1 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D064 0.95 1.2 mA -40°C to +125°C VDD = 5.0V D066 2.5 3.5 mA -40°C to +125°C VDD = 3.0V FOSC = 64MHz (RC_IDLE mode, HFINTOSC + PLL source) D068 2.5 3.5 mA -40°C to +125°C VDD = 3.0V FOSC = 64MHz (RC_IDLE mode, D069 3.0 4.5 mA -40°C to +125°C VDD = 5.0V HFINTOSC + PLL source) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2010-2016 Microchip Technology Inc. DS40001412G-page 423

PIC18(L)F2X/4XK22 27.5 DC Characteristics: Primary Run Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Device Characteristics Typ Max Units Conditions No. D070 Supply Current (IDD)(1),(2) 0.11 0.20 mA -40°C to +125°C VDD = 1.8V FOSC = 1MHz (PRI_RUN mode, D071 0.17 0.25 mA -40°C to +125°C VDD = 3.0V ECM source) D072 0.15 0.25 mA -40°C to +125°C VDD = 2.3V FOSC = 1MHz (PRI_RUN mode, D073 0.20 0.30 mA -40°C to +125°C VDD = 3.0V ECM source) D074 0.25 0.35 mA -40°C to +125°C VDD = 5.0V D075 1.45 2.0 mA -40°C to +125°C VDD = 1.8V FOSC = 20MHz (PRI_RUN mode, D076 2.60 3.5 mA -40°C to +125°C VDD = 3.0V ECH source) D077 1.95 2.5 mA -40°C to +125°C VDD = 2.3V FOSC = 20MHz (PRI_RUN mode, D078 2.65 3.5 mA -40°C to +125°C VDD = 3.0V ECH source) D079 2.95 4.5 mA -40°C to +125°C VDD = 5.0V D080 7.5 10 mA -40°C to +125°C VDD = 3.0V FOSC = 64MHz (PRI_RUN, ECH oscillator) D081 7.5 10 mA -40°C to +125°C VDD = 3.0V FOSC = 64MHz (PRI_RUN mode, D082 8.5 11.5 mA -40°C to +125°C VDD = 5.0V ECH source) D083 1.0 1.5 mA -40°C to +125°C VDD = 1.8V FOSC = 4MHz 16MHz Internal D084 1.8 3.0 mA -40°C to +125°C VDD = 3.0V (PRI_RUN mode, ECM + PLL source) D085 1.4 2.0 mA -40°C to +125°C VDD = 2.3V FOSC = 4MHz 16MHz Internal D086 1.85 2.5 mA -40°C to +125°C VDD = 3.0V (PRI_RUN mode, D087 2.1 3.0 mA -40°C to +125°C VDD = 5.0V ECM + PLL source) D088 6.35 9.0 mA -40°C to +125°C VDD = 3.0V FOSC = 16MHz 64MHz Internal (PRI_RUN mode, ECH + PLL source) D089 6.35 9.0 mA -40°C to +125°C VDD = 3.0V FOSC = 16MHz 64MHz Internal D090 7.0 10 mA -40°C to +125°C VDD = 5.0V (PRI_RUN mode, ECH + PLL source) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS40001412G-page 424  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 27.6 DC Characteristics: Primary Idle Supply Current, PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) PIC18LF2X/4XK22 Operating temperature -40°C  TA  +125°C Standard Operating Conditions (unless otherwise stated) PIC18F2X/4XK22 Operating temperature -40°C  TA  +125°C Param Device Characteristics Typ Max Units Conditions No. D100 Supply Current (IDD)(1),(2) 0.030 0.050 mA -40°C to +125°C VDD = 1.8V Fosc = 1MHz (PRI_IDLE mode, D101 0.045 0.065 mA -40°C to +125°C VDD = 3.0V ECM source) D102 0.06 0.12 mA -40°C to +125°C VDD = 2.3V Fosc = 1MHz (PRI_IDLE mode, D103 0.08 0.15 mA -40°C to +125°C VDD = 3.0V ECM source) D104 0.13 0.20 mA -40°C to +125°C VDD = 5.0V D105 0.45 0.8 mA -40°C to +125°C VDD = 1.8V Fosc = 20MHz (PRI_IDLE mode, D106 0.70 1.0 mA -40°C to +125°C VDD = 3.0V ECH source) D107 0.55 0.8 mA -40°C to +125°C VDD = 2.3V Fosc = 20MHz (PRI_IDLE mode, D108 0.75 1.0 mA -40°C to +125°C VDD = 3.0V ECH source) D109 0.90 1.2 mA -40°C to +125°C VDD = 5.0V D110 2.25 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 64MHz (PRI_IDLE mode, ECH source) D111 2.25 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 64MHz (PRI_IDLE mode, D112 2.60 3.5 mA -40°C to +125°C VDD = 5.0V ECH source) D113 0.35 0.6 mA -40°C to +125°C VDD = 1.8V Fosc = 4MHz 16MHz Internal D114 0.55 0.8 mA -40°C to +125°C VDD = 3.0V (PRI_IDLE mode, ECM + PLL source) D115 0.45 0.6 mA -40°C to +125°C VDD = 2.3V Fosc = 4MHz 16MHz Internal D116 0.60 0.9 mA -40°C to +125°C VDD = 3.0V (PRI_IDLE mode, D117 0.70 1.0 mA -40°C to +125°C VDD = 5.0V ECM + PLL source) D118 2.2 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 16MHz 64MHz Internal (PRI_IDLE mode, ECH + PLL source) D119 2.2 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 16MHz 64MHz Internal D120 2.5 3.5 mA -40°C to +125°C VDD = 5.0V (PRI_IDLE mode, ECH + PLL source) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2010-2016 Microchip Technology Inc. DS40001412G-page 425

PIC18(L)F2X/4XK22 . 27.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) PIC18LF2X/4XK22 Operating temperature -40°C  TA  +125°C Standard Operating Conditions (unless otherwise stated) PIC18F2X/4XK22 Operating temperature -40°C  TA  +125°C Param Device Characteristics Typ Max Units Conditions No. D130 Supply Current (IDD)(1),(2) 3.5 23 A -40°C VDD = 1.8V Fosc = 32kHz (SEC_RUN mode, 3.7 25 A +25°C SOSC source) 3.8 — A +60°C 4.0 28 A +85°C 5.1 30 A +125°C D131 6.2 26 A -40°C VDD = 3.0V 6.4 30 A +25°C 6.5 — A +60°C 6.8 35 A +85°C 7.8 40 A +125°C D132 15 35 A -40°C VDD = 2.3V Fosc = 32kHz (SEC_RUN mode, 16 35 A +25°C SOSC source) 17 35 A +85°C 19 50 A +125°C D133 18 50 A -40°C VDD = 3.0V 19 50 A +25°C 21 50 A +85°C 22 60 A +125°C D134 19 55 A -40°C VDD = 5.0V 20 55 A +25°C 22 55 A +85°C 23 70 A +125°C Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; SOSCI / SOSCO = complementary external square wave, from rail-to-rail. DS40001412G-page 426  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 27.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) PIC18LF2X/4XK22 Operating temperature -40°C  TA  +125°C Standard Operating Conditions (unless otherwise stated) PIC18F2X/4XK22 Operating temperature -40°C  TA  +125°C Param Device Characteristics Typ Max Units Conditions No. D135 0.9 18 A -40°C VDD = 1.8V Fosc = 32kHz (SEC_IDLE mode, 1.0 18 A +25°C SOSC source) 1.1 — A +60°C 1.3 20 A +85°C 2.3 22 A +125°C D136 1.3 20 A -40°C VDD = 3.0V 1.4 20 A +25°C 1.5 — A +60°C 1.8 22 A +85°C 2.9 25 A +125°C D137 12 30 A -40°C VDD = 2.3V Fosc = 32kHz (SEC_IDLE mode, 13 30 A +25°C SOSC source) 14 30 A +85°C 16 45 A +125°C D138 13 35 A -40°C VDD = 3.0V 14 35 A +25°C 16 35 A +85°C 18 50 A +125°C D139 14 40 A -40°C VDD = 5.0V 15 40 A +25°C 16 40 A +85°C 18 60 A +125°C Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; SOSCI / SOSCO = complementary external square wave, from rail-to-rail.  2010-2016 Microchip Technology Inc. DS40001412G-page 427

PIC18(L)F2X/4XK22 27.8 DC Characteristics: Input/Output Characteristics, PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +125°C Param Symbol Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O PORT: D140 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V D140A — — 0.15VDD V 1.8V  VDD  4.5V D141 with Schmitt Trigger — — 0.2VDD V 2.0V  VDD  5.5V buffer with I2C levels — — 0.3VDD V with SMBus levels — — 0.8 V 2.7V  VDD  5.5V D142 MCLR, OSC1 (RC — — 0.2VDD V mode)(1) D142A OSC1 (HS mode) — — 0.3VDD V VIH Input High Voltage I/O ports: — — D147 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V D147A 0.25VDD + — — V 1.8V  VDD  4.5V 0.8 D148 with Schmitt Trigger 0.8VDD — — V 2.0V  VDD  5.5V buffer with I2C levels 0.7VDD — — V with SMBus levels 2.1 — — V 2.7V  VDD  5.5V D149 MCLR 0.8VDD — — V D150A OSC1 (HS mode) 0.7VDD — — V D150B OSC1 (RC mode)(1) 0.9VDD — — V IIL Input Leakage I/O and VSS VPIN VDD, MCLR(2),(3) Pin at high-impedance D155 I/O ports and MCLR — 0.1 50 nA +25°C(4) — 0.7 100 nA +60°C — 4 200 nA +85°C — 35 1000 nA +125°C IPU Weak Pull-up Current(4) D158 IPURB PORTB weak pull-up 25 85 200 A VDD = 3.3V, VPIN = VSS current 25 130 300 A VDD = 5.0V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. DS40001412G-page 428  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 27.8 DC Characteristics: Input/Output Characteristics, PIC18(L)F2X/4XK22 (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +125°C Param Symbol Characteristic Min Typ† Max Units Conditions No. VOL Output Low Voltage D159 I/O ports IOL = 8 mA, VDD = 5V — — 0.6 V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V VOH Output High Voltage(3) D161 I/O ports IOH = 3.5 mA, VDD = 5V VDD - 0.7 — — V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested.  2010-2016 Microchip Technology Inc. DS40001412G-page 429

PIC18(L)F2X/4XK22 27.9 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. Internal Program Memory Programming Specifications(1) D170 VPP Voltage on MCLR/VPP pin 8 — 9 V (Note 3), (Note 4) D171 IDDP Supply Current during — — 10 mA Programming Data EEPROM Memory D172 ED Byte Endurance 100K — — E/W -40C to +85C D173 VDRW VDD for Read/Write VDDMIN — VDDMAX V Using EECON to read/ write D175 TDEW Erase/Write Cycle Time — 3 4 ms D176 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D177 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +85°C Cycles before Refresh(2) Program Flash Memory D178 EP Cell Endurance 10K — — E/W -40C to +85C (Note 5) D179 VPR VDD for Read VDDMIN — VDDMAX V D181 VIW VDD for Row Erase or Write 2.2 — VDDMAX V PIC18LF24K22 D182 VIW VDDMIN — VDDMAX V PIC18(L)F26K22 D183 TIW Self-timed Write Cycle Time — 2 — ms D184 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP voltage must be placed between the MPLAB ICD 2 and target system when programming or debugging with the MPLAB ICD 2. 5: Self-write and Block Erase. DS40001412G-page 430  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 27.10 Analog Characteristics TABLE 27-1: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. CM01 VIOFF Input Offset Voltage — 3 40 mV High-Power mode VREF = VDD/2 — 4 60 mV Low-Power mode VREF = VDD/2 CM02 VICM Input Common-mode Voltage VSS — VDD V CM04* TRESP Response Time(1) — 200 400 ns High-Power mode — 600 3500 ns Low-Power mode CM05* TMC2OV Comparator Mode Change to — — 10 s Output Valid * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. TABLE 27-2: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions: 2.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. CV01* CLSB Step Size(2) — VDD/32 — V CV02* CACC Absolute Accuracy — — 1/2 LSb VSRC 2.0V CV03* CR Unit Resistor Value (R) — 5k —  CV04* CST Settling Time(1) — — 10 s CV05* VSRC+ DAC Positive Reference VSRC- +2 — VDD V CV06* VSRC- DAC Negative Reference VSS — VSRC+ -2 V CV07* VSRC DAC Reference Range 2 — VDD V (VSRC+ - VSRC-) * These parameters are characterized but not tested. Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. 2: See Section22.0 “Digital-to-Analog Converter (DAC) Module” for more information.  2010-2016 Microchip Technology Inc. DS40001412G-page 431

PIC18(L)F2X/4XK22 TABLE 27-3: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Operating Conditions: -40°C < TA < +125°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. VR01 VROUT VR voltage output to ADC 0.973 1.024 1.085 V 1x output, VDD 2.5V 1.946 2.048 2.171 V 2x output, VDD 2.5V 3.891 4.096 4.342 V 4x output, VDD 4.75V (PIC18F2X/4XK22) VR02 VROUT VR voltage output all other 0.942 1.024 1.096 V 1x output, VDD 2.5V modules 1.884 2.048 2.191 V 2x output, VDD 2.5V 3.768 4.096 4.383 V 4x output, VDD 4.75V (PIC18F2X/4XK22) VR04* TSTABLE Settling Time — 25 100 s 0 to 125°C * These parameters are characterized but not tested. TABLE 27-4: CHARGE TIME MEASUREMENT UNIT (CTMU) SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated) Param Sym Characteristics Min Typ(1) Max Units Comments No. CT01 IOUT1 CTMU Current Source, — 0.55 — A IRNG<1:0>=01 Base Range CT02 IOUT2 CTMU Current Source, — 5.5 — A IRNG<1:0>=10 10X Range CT03 IOUT3 CTMU Current Source, — 55 — A IRNG<1:0>=11 100X Range VDD  3.0V Note 1: Nominal value at center point of current trim range (CTMUICON<7:2>=000000). DS40001412G-page 432  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 27-5: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be VHLVD cleared by software) (HLVDIF set by hardware) HLVDIF TABLE 27-5: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Symbol Characteristic HLVDL<3:0> Min Typ† Max Units Conditions No. HLVD Voltage on VDD 0000 1.69 1.84 1.99 V Transition High-to-Low 0001 1.92 2.07 2.22 V 0010 2.08 2.28 2.48 V 0011 2.24 2.44 2.64 V 0100 2.34 2.54 2.74 V 0101 2.54 2.74 2.94 V 0110 2.62 2.87 3.12 V 0111 2.76 3.01 3.26 V 1000 3.00 3.30 3.60 V 1001 3.18 3.48 3.78 V 1010 3.44 3.69 3.94 V 1011 3.66 3.91 4.16 V 1100 3.90 4.15 4.40 V 1101 4.11 4.41 4.71 V 1110 4.39 4.74 5.09 V 1111 V(HLVDIN pin) v † Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.  2010-2016 Microchip Technology Inc. DS40001412G-page 433

PIC18(L)F2X/4XK22 27.11 AC (Timing) Characteristics 27.11.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS40001412G-page 434  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 27.11.2 TIMING CONDITIONS The temperature and voltages specified in Table27-6 apply to all timing specifications unless otherwise noted. Figure27-6 specifies the load conditions for the timing specifications. TABLE 27-6: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA +125°C AC CHARACTERISTICS Operating voltage VDD range as described in Section27.1 “DC Characteristics: Supply Voltage, PIC18(L)F2X/4XK22” and Section27.9 “Memory Programming Requirements”. FIGURE 27-6: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Legend: Pin RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKOUT and including D and E outputs as ports  2010-2016 Microchip Technology Inc. DS40001412G-page 435

PIC18(L)F2X/4XK22 27.11.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-7: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 27-7: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKIN DC 0.5 MHz EC, ECIO Oscillator mode (low power) Frequency(1) DC 16 MHz EC, ECIO Oscillator mode (medium power) EC, ECIO Oscillator mode (high power) DC 64 MHz Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 5 200 kHz LP Oscillator mode 0.1 4 MHz XT Oscillator mode 4 4 MHz HS Oscillator mode, VDD < 2.7V 4 16 MHz HS Oscillator mode, VDD 2.7V, Medium-Power mode (HSMP) 4 20 MHz HS Oscillator mode, VDD 2.7V, High-Power mode (HSHP) 1 TOSC External CLKIN Period(1) 2.0 — s EC, ECIO Oscillator mode (low power) 62.5 — ns EC, ECIO Oscillator mode (medium power) EC, ECIO Oscillator mode (high power) 15.6 — ns Oscillator Period(1) 250 — ns RC Oscillator mode 5 200 s LP Oscillator mode 0.25 10 s XT Oscillator mode 250 250 ns HS Oscillator mode, VDD < 2.7V 62.5 250 ns HS Oscillator mode, VDD 2.7V, Medium-Power mode (HSMP) 50 250 ns HS Oscillator mode, VDD 2.7V, High-Power mode (HSHP) 2 TCY Instruction Cycle Time(1) 62.5 — ns TCY = 4/FOSC 3 TOSL, External Clock in (OSC1) 2.5 — s LP Oscillator mode TOSH High or Low Time 30 — ns XT Oscillator mode 10 — ns HS Oscillator mode 4 TOSR, External Clock in (OSC1) — 50 ns LP Oscillator mode TOSF Rise or Fall Time — 20 ns XT Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating condi- tions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS40001412G-page 436  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 27-8: PLL CLOCK TIMING SPECIFICATIONS Param. Sym Characteristic Min Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 5 MHz VDD < 2.7V, -40°C to +85°C 4 4 MHz VDD < 2.7V, +85°C to +125°C 4 16 MHz 2.7V  VDD, -40°C to +85°C 4 12 MHz 2.7V  VDD, +85°C to +125°C F11 FSYS On-Chip VCO System Frequency 16 20 MHz VDD < 2.7V, -40°C to +85°C 16 16 MHz VDD < 2.7V, +85°C to +125°C 16 64 MHz 2.7V  VDD, -40°C to +85°C 16 48 MHz 2.7V  VDD, +85°C to +125°C F12 t PLL Start-up Time (Lock Time) — 2 ms rc TABLE 27-9: AC CHARACTERISTICS:INTERNAL OSCILLATORS ACCURACY PIC18(L)F46K22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param. Freq. Characteristics Min Typ† Max Units Conditions No. Tolerance OA1 Internal Calibrated  2% — 16.0 — MHz 0°C TA +60°C, VDD 2.5V HFINTOSC Frequency(1)  3% — 16.0 — MHz +60°C TA +85°C, VDD 2.5V  5% — 16.0 — MHz -40°C TA +125°C OA2 Internal Calibrated  2% — 500 — kHz 0°C TA +60°C, VDD 2.5V MFINTOSC Frequency(1)  3% — 500 — kHz +60°C TA +85°C, VDD 2.5V  5% — 500 — kHz -40°C TA +125°C OA3 Internal Calibrated  20% — 31 — kHz -40°C TA +125°C LFINTOSC Frequency(1) † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.  2010-2016 Microchip Technology Inc. DS40001412G-page 437

PIC18(L)F2X/4XK22 FIGURE 27-8: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure27-6 for load conditions. TABLE 27-10: CLKOUT AND I/O TIMING REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 10 TosH2ckL OSC1  to CLKOUT  — 75 200 ns (Note 1) 11 TosH2ckH OSC1  to CLKOUT  — 75 200 ns (Note 1) 12 TckR CLKOUT Rise Time — 35 100 ns (Note 1) 13 TckF CLKOUT Fall Time — 35 100 ns (Note 1) 14 TckL2ioV CLKOUT  to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TioV2ckH Port In Valid before CLKOUT  0.25 TCY + 25 — — ns (Note 1) 16 TckH2ioI Port In Hold after CLKOUT  0 — — ns (Note 1) 17 TosH2ioV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns 18 TosH2ioI OSC1  (Q2 cycle) to Port Input Invalid 100 — — ns (I/O in hold time) 19 TioV2osH Port Input Valid to OSC1 (I/O in setup time) 0 — — ns 20 TioR Port Output Rise Time — 40 72 ns VDD = 1.8V — 15 32 ns VDD = 3.3V - 5.0V 21 TioF Port Output Fall Time — 28 55 ns VDD = 1.8V — 15 30 ns VDD = 3.3V - 5.0V 22† TINP INTx pin High or Low Time 20 — — ns 23† TRBP RB<7:4> Change KBIx High or Low Time TCY — — ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC. DS40001412G-page 438  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 27-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure27-6 for load conditions. FIGURE 27-10: BROWN-OUT RESET TIMING VDD BVDD 35 VBGAP = 1.2V VIVRST Enable Internal Reference Voltage Internal Reference Voltage Stable 36  2010-2016 Microchip Technology Inc. DS40001412G-page 439

PIC18(L)F2X/4XK22 TABLE 27-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — s 31 TWDT Watchdog Timer Time-out Period 3.5 4.1 4.7 ms 1:1 prescaler (no postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 54.8 64.4 74.1 ms 34 TIOZ I/O High-Impedance from MCLR — 2 — s Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 2001 — — s VDD  BVDD (see D005) 36 TIVRST Internal Reference Voltage Stable — 25 35 s 37 THLVD High/Low-Voltage Detect Pulse 2001 — — s VDD  VHLVD Width 38 TCSD CPU Start-up Time 5 — 10 s 39 TIOBST Time for HF-INTOSC to Stabilize — 0.25 1 ms 40 TIOSC_ST Time for HF-INTOSC to Start — TBD TBD µs Note 1: Minimum pulse width that will consistently trigger a reset or interrupt. Shorter pulses may intermittently trigger a response. FIGURE 27-11: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure27-6 for load conditions. DS40001412G-page 440  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 27-12: TIMER0 AND TIMER1/3/5 EXTERNAL CLOCK REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 Tt0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 Tt1H TxCKI High Synchronous, no prescaler 0.5 TCY + 20 — ns Time Synchronous, 10 — ns with prescaler Asynchronous 30 — ns 46 Tt1L TxCKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns Time Synchronous, 10 — ns with prescaler Asynchronous 30 — ns 47 Tt1P TxCKI Input Synchronous Greater of: — ns N = prescale Period 20ns or value (1, 2, 4, 8) (TCY + 40)/N Asynchronous 60 — ns Ft1 TxCKI Clock Input Frequency Range DC 50 kHz 48 Tcke2tmrI Delay from External TxCKI Clock Edge to Timer 2 TOSC 7 TOSC — Increment FIGURE 27-12: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure27-6 for load conditions.  2010-2016 Microchip Technology Inc. DS40001412G-page 441

PIC18(L)F2X/4XK22 TABLE 27-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param. Symbol Characteristic Min Max Units Conditions No. 50 TccL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With 10 — ns prescaler 51 TccH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With 10 — ns prescaler 52 TccP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TccR CCPx Output Fall Time — 25 ns 54 TccF CCPx Output Fall Time — 25 ns DS40001412G-page 442  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 27-13: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure27-6 for load conditions. FIGURE 27-14: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure27-6 for load conditions.  2010-2016 Microchip Technology Inc. DS40001412G-page 443

PIC18(L)F2X/4XK22 FIGURE 27-15: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure27-6 for load conditions. FIGURE 27-16: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure27-6 for load conditions. DS40001412G-page 444  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 27-14: SPI MODE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS  to SCK  or SCK  Input TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 25 — ns 72 TscL SCK Input Low Time Continuous 30 — ns 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 25 — ns TdiV2scL 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 25 — ns TscL2diL 75 TdoR SDO Data Output Rise Time — 30 ns 76 TdoF SDO Data Output Fall Time — 20 ns 77 TssH2doZ SS to SDO Output High-Impedance 10 50 ns 78 TscR SCK Output Rise Time — 30 ns (Master mode) 79 TscF SCK Output Fall Time (Master mode) — 20 ns 80 TscH2doV, SDO Data Output Valid after SCK Edge — 20 ns SPI Master Mode TscL2doV 60 ns SPI Slave Mode 81 TdoV2scH, SDO Data Output Setup to SCK Edge TCY — ns TdoV2scL 82 TssL2doV SDO Data Output Valid after SS  Edge — 60 ns 83 TscH2ssH, SS  after SCK edge 1.5 TCY + 40 — ns TscL2ssH FIGURE 27-17: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure27-6 for load conditions.  2010-2016 Microchip Technology Inc. DS40001412G-page 445

PIC18(L)F2X/4XK22 TABLE 27-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Start condition Setup Time 400 kHz mode 600 — 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first clock pulse is generated Hold Time 400 kHz mode 600 — 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 27-18: I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure27-6 for load conditions. DS40001412G-page 446  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 27-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 102 TR SDA and SCL Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time Start condition 400 kHz mode 0.6 — s 91 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time clock pulse is generated 400 kHz mode 0.6 — s 106 THD:DA Data Input Hold 100 kHz mode 0 — ns T Time 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup 100 kHz mode 250 — ns (Note 2) Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 109 TAA Output Valid from 100 kHz mode — 3500 ns (Note 1) Clock 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before a new transmission 400 kHz mode 1.3 — s can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT=1000+250=1250ns (according to the standard mode I2C bus specification), before the SCL line is released.  2010-2016 Microchip Technology Inc. DS40001412G-page 447

PIC18(L)F2X/4XK22 FIGURE 27-19: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure27-6 for load conditions. TABLE 27-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Repeated Start Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the first clock pulse is Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins. FIGURE 27-20: MASTER SSP I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure27-6 for load conditions. DS40001412G-page 448  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 27-18: MASTER SSP I2C BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be Rise Time from 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be Fall Time from 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time Repeated Start 400 kHz mode 2(TOSC)(BRG + 1) — ms condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time clock pulse is generated 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free before a new trans- 400 kHz mode 1.3 — ms mission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter 107250ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line, parameter 102 + parameter 107=1000+250=1250ns (for 100 kHz mode), before the SCL line is released.  2010-2016 Microchip Technology Inc. DS40001412G-page 449

PIC18(L)F2X/4XK22 FIGURE 27-21: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 122 Note: Refer to Figure27-6 for load conditions. TABLE 27-19: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid — 40 ns 121 Tckrf Clock Out Rise Time and Fall Time — 20 ns (Master mode) 122 Tdtrf Data Out Rise Time and Fall Time — 20 ns FIGURE 27-22: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TXx/CKx pin 125 RXx/DTx pin 126 Note: Refer to Figure27-6 for load conditions. TABLE 27-20: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TdtV2ckl SYNC RCV (MASTER & SLAVE) Data Setup before CK  (DT setup time) 10 — ns 126 TckL2dtl Data Hold after CK  (DT hold time) 15 — ns DS40001412G-page 450  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 TABLE 27-21: A/D CONVERTER CHARACTERISTICS:PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) PIC18(L)F2X/4XK22 Operating temperature Tested at +25°C Param. Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bits VREF  3.0V A03 EIL Integral Linearity Error — ±0.5 ±1 LSb VREF = 3.0V A04 EDL Differential Linearity Error — ±0.5 ±1 LSb VREF  3.0V A06 EOFF Offset Error — ±0.7 ±2 LSb VREF  3.0V A07 EGN Gain Error — ±0.7 ±2 LSb VREF  3.0V A08 ETOTL Total Error — ±0.8 ±3 LSb VREF  3.0V A20 VREF Reference Voltage Range 2 — VDD V (VREFH – VREFL) A21 VREFH Reference Voltage High VDD/2 — VDD + 0.3 V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD/2 V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 3 k Analog Voltage Source Note: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. FIGURE 27-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLE SAMPLING STOPPED Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (0.5TAD), which also disconnects the holding capacitor from the analog input.  2010-2016 Microchip Technology Inc. DS40001412G-page 451

PIC18(L)F2X/4XK22 TABLE 27-22: A/D CONVERSION REQUIREMENTS PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature Tested at +25°C Param. Symbol Characteristic Min Typ Max Units Conditions No. 130 TAD A/D Clock Period 1 — 25 s -40C to +85C 1 — 4 s +85C to +125C 131 TCNV Conversion Time 11 — 11 TAD (not including acquisition time) (Note 1) 132 TACQ Acquisition Time (Note 2) 1.4 — — s VDD = 3V, Rs = 50 135 TSWC Switching Time from Convert  Sample — — (Note 3) 136 TDIS Discharge Time 1 — 1 TCY Note 1: ADRES register may be read on the following TCY cycle. 2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50 . 3: On the following cycle of the device clock. DS40001412G-page 452  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 28.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g. outside specified power supply range) and therefore, outside the warranted range.  2010-2016 Microchip Technology Inc. DS40001412G-page 453

PIC18(L)F2X/4XK22 FIGURE 28-1: PIC18LF2X/4XK22 BASE IPD 10 Max. 85°C 1 A) (µD 0.1 P Typ. 60°C I Typ. 25°C 0.01 Limited Accuracy 0.001 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD(V) FIGURE 28-2: PIC18F2X/4XK22 BASE IPD 40 35 Max. 85°C 30 A) µ25 (D P ΔI 20 15 Typ. 60°C Typ. 25°C 10 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) DS40001412G-page 454  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-3: PIC18LF2X/4XK22 DELTA IPD WATCHDOG TIMER (WDT) 3.0 2.5 Max. 2.0 A) µ (D 1.5 P ΔI 1.0 0.5 Typ. 0.0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-4: PIC18F2X/4XK22 DELTA IPD WATCHDOG TIMER (WDT) 6 5 Max. 4 A) µ (D 3 P ΔI 2 1 Typical 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 455

PIC18(L)F2X/4XK22 FIGURE 28-5: PIC18LF2X/4XK22 DELTA IPD BROWN-OUT RESET (BOR) 16 15 Max. 85°C 14 13 12 A) µ (D 11 P ΔI 10 9 Typical 8 7 6 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-6: PIC18F2X/4XK22 DELTA IPD BROWN-OUT RESET (BOR) 17 15 Max. 85°C 13 A) 11 µ (D P ΔI 9 7 5 Typical 3 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) DS40001412G-page 456  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-7: PIC18LF2X/4XK22 DELTA IPD HIGH/LOW-VOLTAGE DETECT (HLVD) 20 18 16 Max. 14 A) µ (D 12 P ΔI 10 8 Typical 6 4 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-8: PIC18F2X/4XK22 DELTA IPD HIGH/LOW-VOLTAGE DETECT (HLVD) 16 Max. 14 12 10 A) µ (D 8 P ΔI 6 4 Typical 2 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 457

PIC18(L)F2X/4XK22 FIGURE 28-9: PIC18LF2X/4XK22 DELTA IPD SECONDARY OSCILLATOR 4.5 4.0 Max. 85°C 3.5 3.0 A) 2.5 µ (D P ΔI 2.0 1.5 Typ. 60°C 1.0 Typ. 25°C 0.5 0.0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-10: PIC18F2X/4XK22 DELTA IPD SECONDARY OSCILLATOR 6 5 Max. 85°C 4 A) µ (D 3 P ΔI 2 1 Typical 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) DS40001412G-page 458  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-11: PIC18LF2X/4XK22 DELTA IPD COMPARATOR LOW-POWER MODE 20 18 Max. 16 A) 14 µ (D P ΔI 12 10 8 Typical 6 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-12: PIC18F2X/4XK22 DELTA IPD COMPARATOR LOW-POWER MODE 40 35 30 25 A) µ (D20 Max. P ΔI 15 10 Typical 5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 459

PIC18(L)F2X/4XK22 FIGURE 28-13: PIC18LF2X/4XK22 DELTA IPD COMPARATOR HIGH-POWER MODE 120 Max. 100 80 A) µ (D 60 P ΔI 40 Typ. 20 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-14: PIC18F2X/4XK22 DELTA IPD COMPARATOR HIGH-POWER MODE 120 Max. 100 80 A) µ (D 60 P ΔI 40 Typical 20 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) DS40001412G-page 460  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-15: PIC18LF2X/4XK22 DELTA IPD DAC 50 45 40 Max. 35 A) µ (D 30 P ΔI 25 20 Typical 15 10 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-16: PIC18F2X/4XK22 DELTA IPD DAC 70 60 Max. 50 A) 40 µ (D P ΔI30 Typical 20 10 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 461

PIC18(L)F2X/4XK22 FIGURE 28-17: PIC18LF2X/4XK22 DELTA IPD FVR 30 28 26 Max. 24 22 A) µ (D 20 P ΔI 18 16 Typ. 60°C Typ. 25°C 14 12 10 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-18: PIC18F2X/4XK22 DELTA IPD FVR 120 100 Max. 80 A) Typical µ (D 60 P ΔI 40 20 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) Note1: On the PIC18F2X/4XK22, enabling the FVR results in significantly more Sleep current when the part enters Voltage Regulation mode at VDD ~ 3.2V. DS40001412G-page 462  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-19: PIC18(L)F2X/4XK22 DELTA IDD A/D CONVERTOR1 500 450 Max. 400 350 300 A) (µD250 Typical D ΔI 200 150 100 50 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) Note1: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode, both the ADC and the FRC turn off as soon as conversion (if any) is complete.  2010-2016 Microchip Technology Inc. DS40001412G-page 463

PIC18(L)F2X/4XK22 FIGURE 28-20: PIC18LF2X/4XK22 TYPICAL IDD: RC_RUN LF-INTOSC 31 kHz 14 12 125°C 10 25°C A) 8 -40°C µ (D 85°C D I 6 4 2 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-21: PIC18LF2X/4XK22 MAXIMUM IDD: RC_RUN LF-INTOSC 31 kHz 55 45 125°C 35 A) µ (D D I 85°C 25 25°C -40°C 15 5 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412G-page 464  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-22: PIC18F2X/4XK22 TYPICAL IDD: RC_RUN LF-INTOSC 31 kHz 28 26 24 125°C 22 85°C 25°C A) 20 µ (D -40°C ID 18 16 14 12 10 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-23: PIC18F2X/4XK22 MAXIMUM IDD: RC_RUN LF-INTOSC 31 kHz 85 75 125°C 65 55 -40°C to +85°C A) µ (D 45 D I 35 25 15 5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 465

PIC18(L)F2X/4XK22 FIGURE 28-24: PIC18LF2X/4XK22 IDD: RC_RUN MF-INTOSC 500 kHz 0.40 0.35 Max 0.30 0.25 A) m 0.20 (D D I Typical 0.15 0.10 0.05 0.00 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-25: PIC18F2X/4XK22 IDD: RC_RUN MF-INTOSC 500 kHz 0.4 0.35 Max. 0.3 0.25 Typical A) m (D 0.2 D I 0.15 0.1 0.05 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) DS40001412G-page 466  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-26: PIC18LF2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC 3.50 3.00 2.50 16 MHz A) 2.00 m (D ID 1.50 8 MHz 1.00 4 MHz 2 MHz 0.50 1 MHz 0.00 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-27: PIC18LF2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC 4.5 4.0 3.5 16 MHz 3.0 A) 2.5 m (D D 2.0 I 8 MHz 1.5 4 MHz 1.0 2 MHz 1 MHz 0.5 0.0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 467

PIC18(L)F2X/4XK22 FIGURE 28-28: PIC18F2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC 3 2.5 16 MHz 2 A) m (D1.5 8 MHz D I 1 4 MHz 2 MHz 0.5 1 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-29: PIC18F2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC 4 3.5 16 MHz 3 2.5 A) m (D 2 8 MHz D I 1.5 4 MHZ 1 2 MHz 1 MHz 0.5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) DS40001412G-page 468  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-30: PIC18LF2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC with PLL 9 8 7 64 MHz 6 A) 5 m (D D 4 I 32 MHz 3 16 MHz 2 1 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-31: PIC18LF2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC with PLL 12 10 64 MHz 8 A) m (D 6 D I 32 MHz 4 16 MHz 2 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 469

PIC18(L)F2X/4XK22 FIGURE 28-32: PIC18F2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC with PLL 8 7 64 MHz 6 5 A) m 4 (D 32 MHz D I 3 16 MHz 2 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-33: PIC18F2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC with PLL 12 10 64 MHz 8 A) m 6 (D D I 32 MHz 4 16 MHz 2 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) DS40001412G-page 470  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-34: PIC18LF2X/4XK22 TYPICAL IDD: RC_IDLE LF-INTOSC 31 kHz 4 3.5 125°C 3 2.5 A) µ (D 2 D I 1.5 85°C 25°C 1 -40°C 0.5 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD(V) FIGURE 28-35: PIC18LF2X/4XK22 MAXIMUM IDD: RC_IDLE LF-INTOSC 31 kHz 35 30 125°C 25 20 A) µ (D ID 15 85°C 10 25°C 5 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 471

PIC18(L)F2X/4XK22 FIGURE 28-36: PIC18F2X/4XK22 TYPICAL IDD: RC_IDLE LF-INTOSC 31 kHz 22 21 20 -40°C 19 18 A) (µD 17 ID 125°C 16 15 85°C 25°C 14 13 12 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-37: PIC18F2X/4XK22 MAXIMUM IDD: RC_IDLE LF-INTOSC 31 kHz 70 60 125°C 50 A) (µD 40 -40°C to-4 0+C8 5°C D I 30 20 10 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) DS40001412G-page 472  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-38: PIC18LF2X/4XK22 IDD: RC_IDLE MF-INTOSC 500 kHz 0.3 Max. 0.25 0.2 A) m (D 0.15 D I Typical 0.1 0.05 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-39: PIC18F2X/4XK22 IDD: RC_IDLE MF-INTOSC 500 kHz 0.35 Max. 0.3 0.25 0.2 Typical A) m (D 0.15 D I 0.1 0.05 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 473

PIC18(L)F2X/4XK22 FIGURE 28-40: PIC18LF2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOSC 1.2 1 0.8 16 MHz A) m (D0.6 8 MHz D I 4 MHz 0.4 2 MHz 1 MHz 0.2 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 28-41: PIC18LF2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC 1.6 1.4 1.2 16 MHz 1 A) m 0.8 (D 8 MHz D I 0.6 4 MHz 1 MHz 0.4 0.2 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) DS40001412G-page 474  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-42: PIC18F2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOSC 1 16 MHz 0.9 0.8 A) 0.7 8 MHz m (D D I 0.6 4 MHz 0.5 2 MHz 1 MHz 0.4 0.3 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-43: PIC18F2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC 1.4 1.2 16 MHz 1 8 MHz A) 0.8 m (D 4 MHz ID 0.6 1 MHz 0.4 0.2 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 475

PIC18(L)F2X/4XK22 FIGURE 28-44: PIC18LF2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOSC with PLL 3.5 3 2.5 64 MHz 2 A) m (D 1.5 D I 32 MHz 1 16 MHz 0.5 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-45: PIC18LF2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC with PLL 5 4.5 4 64 MHz 3.5 3 A) m (D 2.5 D I 2 32 MHz 1.5 16 MHz 1 0.5 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412G-page 476  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-46: PIC18F2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOSC with PLL 3 64 MHz 2.5 2 A) m 32 MHz (D 1.5 D I 1 16 MHz 0.5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-47: PIC18F2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC with PLL 5 4.5 64 MHz 4 3.5 3 A) m (D 2.5 D I 2 32 MHz 1.5 16 MHz 1 0.5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 477

PIC18(L)F2X/4XK22 FIGURE 28-48: PIC18LF2X/4XK22 TYPICAL IDD: PRI_RUN EC MEDIUM POWER 3.0 2.5 2.0 16 MHz A) m 1.5 (D 10 MHz D I 1.0 4 MHz 0.5 1 MHz 0.0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-49: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_RUN EC MEDIUM POWER 4.0 3.5 3.0 2.5 16 MHz A) m (D 2.0 D I 10 MHz 1.5 1.0 4 MHz 0.5 1 MHz 0.0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412G-page 478  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-50: PIC18F2X/4XK22 TYPICAL IDD: PRI_RUN EC MEDIUM POWER 2.5 16 MHz 2 1.5 A) 10 MHz m (D D I 1 4 MHz 0.5 1 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-51: PIC18F2X/4XK22 MAXIMUM IDD: PRI_RUN EC MEDIUM POWER 3.5 3 16 MHz 2.5 A) 2 m 10 MHz (D D I 1.5 1 4 MHz 0.5 1 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 479

PIC18(L)F2X/4XK22 FIGURE 28-52: PIC18LF2X/4XK22 TYPICAL IDD: PRI_RUN EC HIGH POWER 12 10 8 64 MHz A) m (D 6 D I 40 MHz 4 20 MHz 16 MHz 2 10 MHz 4 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD(V) FIGURE 28-53: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_RUN EC HIGH POWER 16 14 12 64 MHz 10 A) m 8 (D D I 40 MHz 6 4 20 MHz 16 MHz 2 10 MHz 4 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412G-page 480  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-54: PIC18F2X/4XK22 TYPICAL IDD: PRI_RUN EC HIGH POWER 9 64 MHz 8 7 6 40 MHz A) 5 m (D D 4 I 3 20 MHz 16 MHz 2 10 MHz 1 4 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD(V) FIGURE 28-55: PIC18F2X/4XK22 MAXIMUM IDD: PRI_RUN EC HIGH POWER 14 12 64 MHz 10 A) 8 m (D 40 MHz D I 6 20 MHz 4 16 MHz 10 MHz 2 4 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 481

PIC18(L)F2X/4XK22 FIGURE 28-56: PIC18LF2X/4XK22 TYPICAL IDD: PRI_RUN EC with PLL 10 9 8 7 64 MHz 6 A) m 5 (D D I 4 32 MHz 3 2 16 MHz 1 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-57: PIC18LF2X/4XK22 MAXIMIUM IDD: PRI_RUN EC with PLL 14 12 10 64 MHz A) 8 m (D D I 6 32 MHz 4 16 MHz 2 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412G-page 482  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-58: PIC18F2X/4XK22 TYPICAL IDD: PRI_RUN EC with PLL 8 7 64 MHz 6 5 A) m (D 4 D 32 MHz I 3 2 16 MHz 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-59: PIC18F2X/4XK22 MAXIMUM IDD: PRI_RUN EC with PLL 12 10 64 MHz 8 A) m 6 (D D I 32 MHz 4 16 MHz 2 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 483

PIC18(L)F2X/4XK22 FIGURE 28-60: PIC18LF2X/4XK22 TYPICAL IDD: PRI_IDLE EC MEDIUM POWER 0.9 0.8 0.7 0.6 16 MHz A) 0.5 m (DD 0.4 I 10 MHz 0.3 0.2 4 MHz 0.1 1 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-61: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_IDLE EC MEDIUM POWER 1.2 1 0.8 16 MHz A) m 0.6 (D D I 10 MHz 0.4 0.2 4 MHz 1 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412G-page 484  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-62: PIC18F2X/4XK22 TYPICAL IDD: PRI_IDLE EC MEDIUM POWER 0.8 16 MHz 0.7 0.6 0.5 10 MHz A) m (D 0.4 D I 0.3 4 MHz 0.2 1 MHz 0.1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-63: PIC18F2X/4XK22 MAXIMUM IDD: PRI_IDLE EC MEDIUM POWER 1.2 1 16 MHz 0.8 A) m 0.6 10 MHz (D D I 0.4 4 MHz 0.2 1 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 485

PIC18(L)F2X/4XK22 FIGURE 28-64: PIC18LF2X/4XK22 TYPICAL IDD: PRI_IDLE EC HIGH POWER 3.5 3 2.5 64 MHz A) 2 m (D ID 1.5 40 MHz 1 20 MHz 16 MHz 0.5 10 MHz 4 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD(V) FIGURE 28-65: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_IDLE EC HIGH POWER 5 4.5 4 3.5 64 MHz 3 A) m (D 2.5 D I 2 40 MHz 1.5 1 20 MHz 16 MHz 0.5 10 MHz 4 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412G-page 486  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-66: PIC18F2X/4XK22 TYPICAL IDD: PRI_IDLE EC HIGH POWER 3 64 MHz 2.5 2 A) 40 MHz m 1.5 (D D I 1 20 MHz 16 MHz 0.5 10 MHz 4 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD(V) FIGURE 28-67: PIC18F2X/4XK22 MAXIMUM IDD: PRI_IDLE EC HIGH POWER 4 3.5 64 MHz 3 2.5 A) m 40 MHz (D 2 D I 1.5 20 MHz 1 16 MHz 10 MHz 0.5 4 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 487

PIC18(L)F2X/4XK22 FIGURE 28-68: PIC18LF2X/4XK22 TYPICAL IDD: PRI_IDLE EC with PLL 3.5 3 2.5 64 MHz A) 2 m (D D 1.5 I 32 MHz 1 0.5 16 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-69: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_IDLE EC with PLL 4.5 4 3.5 64 MHz 3 A) 2.5 m (D D 2 I 1.5 32 MHz 1 16 MHz 0.5 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412G-page 488  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-70: PIC18F2X/4XK22 TYPICAL IDD: PRI_IDLE EC with PLL 3 2.5 64 MHz 2 A) m 1.5 (D D I 32 MHz 1 16 MHz 0.5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-71: PIC18F2X/4XK22 MAXIMUM IDD: PRI_IDLE EC with PLL 4 3.5 64 MHz 3 2.5 A) m 2 (D D I 32 MHz 1.5 1 16 MHz 0.5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 489

PIC18(L)F2X/4XK22 FIGURE 28-72: PIC18LF2X/4XK22 TYPICAL IDD: SEC_RUN 32.768 kHz 9 8 125°C 7 85°C 60°C 25°C A) -40°C µ 6 (D D I 5 4 3 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-73: PIC18LF2X/4XK22 MAXIMUM IDD: SEC_RUN 32.768 kHz 50 45 40 85°C 35 25°C A) 30 µ (D -40°C D 25 I 20 15 10 5 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412G-page 490  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-74: PIC18F2X/4XK22 TYPICAL IDD: SEC_RUN 32.768 kHz 22 21 85°C 20 25°C 19 A) -40°C µ 18 (D D I 17 16 15 14 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-75: PIC18F2X/4XK22 MAXIMUM IDD: SEC_RUN 32.768 kHz 85 75 125°C 65 55 -40°C to +85°C A) µ (D 45 D I 35 25 15 5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 491

PIC18(L)F2X/4XK22 FIGURE 28-76: PIC18LF2X/4XK22 TYPICAL IDD: SEC_IDLE 32.768 kHz 2.3 2.1 1.9 85°C 1.7 60°C A) 1.5 25°C µ (D -40°C D 1.3 I 1.1 0.9 0.7 0.5 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-77: PIC18LF2X/4XK22 MAXIMUM IDD: SEC_IDLE 32.768 kHz 25 20 85°C 25°C 15 A) µ (D -40°C D I 10 5 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) DS40001412G-page 492  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-78: PIC18F2X/4XK22 TYPICAL IDD: SEC_IDLE 32.768 kHz 18 17 16 85°C 15 A) 25°C (µD 14 D I -40°C 13 12 11 10 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-79: PIC18F2X/4XK22 MAXIMUM IDD: SEC_IDLE 32.768 kHz 63 125°C 58 53 48 A) µ (D 43 D I -40°C to +85°C 38 33 28 23 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 493

PIC18(L)F2X/4XK22 FIGURE 28-80: PIC18(L)F2X/4XK22 TTL BUFFER INPUT LOW VOLTAGE 1.5 1.3 25°C 1.1 -40°C 0.9 ) V (L 125°C 85°C VI 0.7 Max. 0.5 0.3 0.1 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 5.4 VDD (V) FIGURE 28-81: PIC18(L)F2X/4XK22 SCHMITT TRIGGER BUFFER INPUT LOW VOLTAGE 2.0 1.8 1.6 25°C -40°C 1.4 1.2 ) 85°C V V (IL 1.0 125°C Max. 0.8 0.6 0.4 0.2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VDD (V) DS40001412G-page 494  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-82: PIC18(L)F2X/4XK22 TTL BUFFER INPUT HIGH VOLTAGE 2.1 1.9 Min. 1.7 1.5 V) 1.3 -40°C (H 25°C VI 85°C 1.1 125°C 0.9 0.7 0.5 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 5.4 VDD (V) FIGURE 28-83: PIC18(L)F2X/4XK22 SCHMITT TRIGGER BUFFER INPUT HIGH VOLTAGE 4.5 4.0 3.5 Min. ) 3.0 V (H VI 2.5 2.0 25°C -40°C 1.5 85°C 125°C 1.0 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 5.4 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 495

PIC18(L)F2X/4XK22 FIGURE 28-84: PIC18(L)F2X/4XK22 PIN INPUT LEAKAGE 1.00E-05 1.00E-06 Max. 1.00E-07 A) ( e g a k a 1.00E-08 e L t Typical u p n I 1.00E-09 1.00E-10 1.00E-11 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 Temperature (°C) DS40001412G-page 496  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-85: PIC18(L)F2X/4XK22 OUTPUT LOW VOLTAGE 1.6 1.4 1.2 1 Max. 2V Typ. 2V Typ. 3V Max. 3V ) 0.8 V (L VO Max. 5V Typ. 5V 0.6 0.4 0.2 0 0 5 10 15 20 25 30 IOL (mA) FIGURE 28-86: PIC18(L)F2X/4XK22 OUTPUT HIGH VOLTAGE 5 4 Typ. 5V 3 V) (H Min. 5V O V 2 Min. 3V Typ. 3V 1 Min. 2V Typ. 2V 0 0 5 10 15 20 25 IOH (mA)  2010-2016 Microchip Technology Inc. DS40001412G-page 497

PIC18(L)F2X/4XK22 FIGURE 28-87: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE, NORMAL-POWER MODE; VDD=5.5V 60 50 40 V) m et ( 6 sigma s 30 Off s. b A 20 10 Typical 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VREF(V) FIGURE 28-88: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE, NORMAL-POWER MODE; VDD=3.0V 45 40 35 30 V) m 6 sigma et ( 25 s Off s. 20 b A 15 10 Typical 5 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF (V) DS40001412G-page 498  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-89: PIC18LF2X/4XK22 COMPARATOR OFFSET VOLTAGE, NORMAL-POWER MODE; VDD=1.8V 35 30 25 6 sigma ) V m 20 t ( e s f f O s. 15 b A 10 5 Typical 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VREF (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 499

PIC18(L)F2X/4XK22 FIGURE 28-90: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE, LOW-POWER MODE; VDD=5.5V 90 80 70 60 V) m 50 et ( s Off 40 6 sigma s. b A 30 20 Typical 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VREF(V) FIGURE 28-91: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE, LOW-POWER MODE; VDD=3.0V 80 70 60 50 V) m et ( 40 s 6 sigma Off bs. 30 A 20 10 Typical 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF(V) DS40001412G-page 500  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-92: PIC18LF2X/4XK22 COMPARATOR OFFSET VOLTAGE, LOW-POWER MODE; VDD=1.8V 60 50 40 6 sigma ) V m t ( se 30 f f O s. b A 20 10 Typical 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VREF(V)  2010-2016 Microchip Technology Inc. DS40001412G-page 501

PIC18(L)F2X/4XK22 FIGURE 28-93: PIC18(L)F2X/4XK22 TYPICAL DAC ABS. ERROR VDD = 2.5V, 3.0V, & 5.5V 1.7 1.6 1.5 1.4 1.3 1.2 EF R Sb) 1.1 m Vmit (L 1.0 muLi rror 0.9 Mini E e 0.8 t u ol 0.7 s b 0.6 A Max LSb Limit 0.5 0.4 2.5V 0.3 3.0V 0.2 0.1 5.5V 0.0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VREF (V) DS40001412G-page 502  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-94: PIC18(L)F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 1X OUTPUT 1.035 1.030 1.025 5.5V V) 1 ( 2.5V x 1.020 R V F 1.015 1.010 1.005 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 28-95: PIC18(L)F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 1X OUTPUT 1.10 Max. 1.08 1.06 V) 1.04 - 1 ( 40°C x R 25°C V 1.02 F 85°C 125°C 1.00 0.98 Min. 0.96 2.5 3 3.5 4 4.5 5 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 503

PIC18(L)F2X/4XK22 FIGURE 28-96: PIC18(L)F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 2X OUTPUT 2.065 2.055 5.5V 2.045 V) 2 ( 2.5V x R V F 2.035 2.025 2.015 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 28-97: PIC18(L)F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 2X OUTPUT 2.20 Max. 2.15 2.10 V) x2 ( 2.05 25°C -40°C R V 85°C F 125°C 2.00 1.95 Min. 1.90 2.5 3 3.5 4 4.5 5 5.5 VDD (V) DS40001412G-page 504  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-98: PIC18F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 4X OUTPUT 4.13 4.11 5.5V 4.09 V) 4 ( 4.5V x R V F 4.07 4.05 4.03 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 28-99: PIC18F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 4X OUTPUT 4.40 4.35 Max. 4.30 4.25 4.20 V) 4.15 - 4 ( 40°C x R 4.10 25°C V F 85°C 4.05 125°C 4.00 3.95 3.90 Min. 3.85 4.5 4.7 4.9 5.1 5.3 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 505

PIC18(L)F2X/4XK22 FIGURE 28-100: PIC18(L)F2X/4XK22 HF-INTOSC FREQUENCY vs. TEMPERATURE at 16 MHZ MIN / MAX: ± 2%, T = 0°C to +70°C +2% / -3%, T = +70°C to +85°C ± 5%, T = -40°C to 0°C and +85°C to +125°C 16.80 16.64 16.48 16.32 Max. 16.16 ) z H M16.00 q ( e r15.84 F Typical 15.68 Min. 15.52 15.36 15.20 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temp (°C) DS40001412G-page 506  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 FIGURE 28-101: PIC18LF2X/4XK22 TYPICAL LF-INTOSC FREQUENCY vs. VDD Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C 32.5 32.0 25°C 31.5 -40°C 85°C ) 31.0 z H k ( y nc 30.5 125°C e u q e Fr 30.0 29.5 29.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 28-102: PIC18F2X/4XK22 TYPICAL LF-INTOSC FREQUENCY vs. VDD Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C 32.5 32.0 31.5 25°C ) 31.0 -40°C z H k ( y c 30.5 n e u q 85°C e r 30.0 F 29.5 125°C 29.0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001412G-page 507

PIC18(L)F2X/4XK22 FIGURE 28-103: PIC18LF2X/4XK22 TYPICAL LF-INTOSC FREQUENCY vs. TEMPERATURE Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C 32.5 1.8V 32.0 31.5 3V z) 31.0 H 3.6V k ( y nc 30.5 e u q e Fr 30.0 29.5 29.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 28-104: PIC18F2X/4XK22 TYPICAL LF-INTOSC FREQUENCY vs. TEMPERATURE Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C 32.5 32.0 2.5V 31.5 3.0V ) 5.5V Hz 31.0 k ( y c n 30.5 e u q e r F 30.0 29.5 29.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) DS40001412G-page 508  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC18F25K22 -E/SP e3 0810017 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX PIC18F25K22 XXXXXXXXXXXXXXXXXXXX -E/SO e3 XXXXXXXXXXXXXXXXXXXX 0810017 YYWWNNN 28-Lead SSOP (5.30 mm) Example PIC18F25K22 -E/SS e3 0810017 Legend: XX...X Customer-specific information or Microchip part number Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2016 Microchip Technology Inc. DS40001412G-page 509

PIC18(L)F2X/4XK22 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 XXXXXXXX 18F25K22 XXXXXXXX -E/ML e3 YYWWNNN 0610017 28-Lead UQFN (4x4x0.5 mm) Example PIC18 PIN 1 PIN 1 F23K22 E/MV e3 810017 40-Lead PDIP (600 mil) Example XXXXXXXXXXXXXXXXXX PIC18F45K22 XXXXXXXXXXXXXXXXXX -E/P e3 XXXXXXXXXXXXXXXXXX 0810017 YYWWNNN Legend: XX...X Customer-specific information or Microchip part number Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS40001412G-page 510  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Package Marking Information (Continued) 40-Lead UQFN (5x5x0.5 mm) Example PIN 1 PIN 1 PIC18F 45K22 -I/MV e3 0810017 44-Lead QFN (8x8x0.9 mm) Example PIN 1 PIN 1 XXXXXXXXXXX 1845K22 XXXXXXXXXXX -E/ML e3 XXXXXXXXXXX 0810017 YYWWNNN 44-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX 18F45K22 -E/PT e3 XXXXXXXXXX 0810017 XXXXXXXXXX YYWWNNN Legend: XX...X Customer-specific information or Microchip part number Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2016 Microchip Technology Inc. DS40001412G-page 511

PIC18(L)F2X/4XK22 29.2 Package Details The following sections give the technical details of the packages. (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:14)(cid:15)(cid:10)(cid:16)(cid:17)(cid:8)(cid:18)(cid:19)(cid:13)(cid:20)(cid:10)(cid:21)(cid:22)(cid:8)(cid:17)(cid:10)(cid:23)(cid:14)(cid:5)(cid:6)(cid:13)(cid:14)(cid:7)(cid:10)(cid:24)(cid:11)(cid:16)(cid:25)(cid:10)(cid:26)(cid:10)(cid:27)(cid:28)(cid:28)(cid:10)(cid:29)(cid:13)(cid:17)(cid:10)(cid:30)(cid:31)(cid:9)(cid:15)(cid:10) (cid:11)(cid:16)(cid:21)(cid:23)(cid:16)! "(cid:31)(cid:19)(cid:7)# 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) "(cid:31)(cid:19)(cid:7)(cid:18)# (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1 DS40001412G-page 512  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2016 Microchip Technology Inc. DS40001412G-page 513

PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001412G-page 514  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2016 Microchip Technology Inc. DS40001412G-page 515

PIC18(L)F2X/4XK22 (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:16)(cid:17)(cid:8)(cid:18)(cid:19)(cid:13)(cid:20)(cid:10)(cid:11)$%(cid:13)(cid:14)(cid:12)(cid:10)(cid:11)(cid:29)(cid:8)(cid:17)(cid:17)(cid:10)&(cid:22)(cid:19)(cid:17)(cid:13)(cid:14)(cid:7)(cid:10)(cid:24)(cid:11)(cid:11)(cid:25)(cid:10)(cid:26)(cid:10)’((cid:27)(cid:28)(cid:10)(cid:29)(cid:29)(cid:10)(cid:30)(cid:31)(cid:9)(cid:15)(cid:10) (cid:11)(cid:11)&(cid:16)! "(cid:31)(cid:19)(cid:7)# 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:30)(cid:4)(cid:20)(cid:3)(cid:4) (cid:30)(cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< "(cid:31)(cid:19)(cid:7)(cid:18)# (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)-1 DS40001412G-page 516  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2016 Microchip Technology Inc. DS40001412G-page 517

PIC18(L)F2X/4XK22 DS40001412G-page 518  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22  2010-2016 Microchip Technology Inc. DS40001412G-page 519

PIC18(L)F2X/4XK22 (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:16)(cid:17)(cid:8)(cid:18)(cid:19)(cid:13)(cid:20)(cid:10))(cid:22)(cid:8)(cid:9)(cid:10)*(cid:17)(cid:8)(cid:19)+(cid:10)"(cid:31)(cid:10)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:16)(cid:8)(cid:20)(cid:12)(cid:8),(cid:7)(cid:10)(cid:24)-(cid:6)(cid:25)(cid:10)(cid:26)(cid:10)./.(cid:10)(cid:29)(cid:29)(cid:10)(cid:30)(cid:31)(cid:9)(cid:15)(cid:10) )*"! 0(cid:13)(cid:19)$(cid:10)(cid:28)(’’(cid:10)(cid:29)(cid:29)(cid:10)1(cid:31)(cid:14)(cid:19)(cid:8)(cid:20)(cid:19)(cid:10)(cid:6)(cid:7)(cid:14),(cid:19)$ "(cid:31)(cid:19)(cid:7)# 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS40001412G-page 520  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2016 Microchip Technology Inc. DS40001412G-page 521

PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001412G-page 522  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22  2010-2016 Microchip Technology Inc. DS40001412G-page 523

PIC18(L)F2X/4XK22 2(cid:28)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:16)(cid:17)(cid:8)(cid:18)(cid:19)(cid:13)(cid:20)(cid:10)(cid:21)(cid:22)(cid:8)(cid:17)(cid:10)(cid:23)(cid:14)(cid:5)(cid:6)(cid:13)(cid:14)(cid:7)(cid:10)(cid:24)(cid:16)(cid:25)(cid:10)(cid:26)(cid:10).(cid:28)(cid:28)(cid:10)(cid:29)(cid:13)(cid:17)(cid:10)(cid:30)(cid:31)(cid:9)(cid:15)(cid:10) (cid:16)(cid:21)(cid:23)(cid:16)! "(cid:31)(cid:19)(cid:7)# 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c b1 A1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:29) = (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:29)(cid:24)(cid:4) = (cid:20)?(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:23)<(cid:29) = (cid:20)(cid:29)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)(cid:24)<(cid:4) = (cid:3)(cid:20)(cid:4)(cid:24)(cid:29) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) = (cid:20)(cid:3)(cid:4)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< = (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)-(cid:4) = (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) = (cid:20)(cid:4)(cid:3)- : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:5)(cid:4)(cid:4) "(cid:31)(cid:19)(cid:7)(cid:18)# (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)?1 DS40001412G-page 524  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2016 Microchip Technology Inc. DS40001412G-page 525

PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001412G-page 526  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2016 Microchip Technology Inc. DS40001412G-page 527

PIC18(L)F2X/4XK22 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X 0.20 C TOP VIEW A1 0.10 C C SEATING A PLANE 44X A3 0.08 C SIDE VIEW L 0.10 C A B D2 0.10 C A B E2 K 2 1 NOTE 1 N 44X b e 0.07 C A B 0.05 C BOTTOM VIEW Microchip Technology Drawing C04-103D Sheet 1 of 2 DS40001412G-page 528  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 44 Pitch e 0.65 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Terminal Thickness A3 0.20 REF Overall Width E 8.00 BSC Exposed Pad Width E2 6.25 6.45 6.60 Overall Length D 8.00 BSC Exposed Pad Length D2 6.25 6.45 6.60 Terminal Width b 0.20 0.30 0.35 Terminal Length L 0.30 0.40 0.50 Terminal-to-Exposed-Pad K 0.20 - - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-103D Sheet 2 of 2  2010-2016 Microchip Technology Inc. DS40001412G-page 529

PIC18(L)F2X/4XK22 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV 44 G2 1 2 ØV EV C2 Y2 G1 Y1 E SILK SCREEN X1 RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.65 BSC Optional Center Pad Width X2 6.60 Optional Center Pad Length Y2 6.60 Contact Pad Spacing C1 8.00 Contact Pad Spacing C2 8.00 Contact Pad Width (X44) X1 0.35 Contact Pad Length (X44) Y1 0.85 Contact Pad to Contact Pad (X40) G1 0.30 Contact Pad to Center Pad (X44) G2 0.28 Thermal Via Diameter V 0.33 Thermal Via Pitch EV 1.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing No. C04-2103C DS40001412G-page 530  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A D1 B NOTE 2 (DATUM A) (DATUM B) E1 E A A NOTE 1 2X N 0.20 H A B 2X 1 2 3 0.20 H A B TOP VIEW 4X 11 TIPS 0.20 C A B A A2 C SEATING PLANE 0.10 C A1 SIDE VIEW 1 2 3 N NOTE 1 44 X b 0.20 C A B e BOTTOM VIEW Microchip Technology Drawing C04-076C Sheet 1 of 2  2010-2016 Microchip Technology Inc. DS40001412G-page 531

PIC18(L)F2X/4XK22 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging H c θ L (L1) SECTION A-A Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 44 Lead Pitch e 0.80 BSC Overall Height A - - 1.20 Standoff A1 0.05 - 0.15 Molded Package Thickness A2 0.95 1.00 1.05 Overall Width E 12.00 BSC Molded Package Width E1 10.00 BSC Overall Length D 12.00 BSC Molded Package Length D1 10.00 BSC Lead Width b 0.30 0.37 0.45 Lead Thickness c 0.09 - 0.20 Lead Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle θ 0° 3.5° 7° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Exact shape of each corner is optional. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076C Sheet 2 of 2 DS40001412G-page 532  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2016 Microchip Technology Inc. DS40001412G-page 533

PIC18(L)F2X/4XK22 APPENDIX A: REVISION HISTORY Revision A (February 2010) Initial release of this document. Revision B (April 2010) Updated Figures 2-4, 12-1 and 18-2; Updated Registers 2-2, 10-4, 10-5, 10-7, 17-2, 24-1 and 24-5; Updated Sections 10.3.2, 18.8.4, Synchronizing Comparator Output to Timer1; Updated Sections 27.2, 27-3, 27-4, 27-5, 27-6, 27-7 and 27-9; Updated Tables 27-2, 27-3, 27-4 and 27-7; Other minor corrections. Revision C (July 2010) Added 40-pin UQFN diagram; Updated Table 2 and Table 1-3 to add 40-UQFN column; Updated Table 1-1 to add “40-pin UQFN”; Updated Figure 27-1; Added Figure 27-2; Updated Table 27-6; Added 40-Lead UQFN Package Marking Information and Details; Updated Packaging Information section; Updated Table B-1 to add “40-pin UQFN”; Updated Product Identification System section; Other minor corrections. Revision D (November 2010) Updated the data sheet to new format; Revised Tables 1-2, 1-3, 5-2, 10-1, 10-5, 10-6, 10-8, 10-9, 10-11, 10- 14, 14-13 and Register 14-5; Updated the Electrical Characteristics section. Revision E (January 2012) Updated Section 2.5.2, EC Mode; Updated Table 3-2; Removed Table 3-3; Updated Section 14.4.8; Removed CM2CON Register; Updated the Electrical Characteristics section; Updated the Packaging Information section; Updated the Char. Data section; Other minor corrections. Revision F (May 2012) Minor corrections; release of Final data sheet. Revision G (August 2016) Minor corrections to Tables 1-2, 17-1, 27-11, 27-14, 27- 22, Section 2.6.1, Example 7-3, Registers 9-4, 9-5, 9-11, 14-5, Figures 10-1, 17-3, 17-4, 27-23; Updated Packaging Information Section. DS40001412G-page 534  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in TableB-1. TABLE B-1: DEVICE DIFFERENCES PIC18F23K22 PIC18F24K22 Features(1) PIC18LF23K2 PIC18LF24K2 PIC18F25K22 PIC18F26K22 PIC18F43K22 PIC18F44K22 PIC18F45K22 PIC18F46K22 PIC18LF25K22 PIC18LF26K22 PIC18LF43K22 PIC18LF44K22 PIC18LF45K22 PIC18LF46K22 2 2 Program Memory 8192 16384 32768 65536 8192 16384 32768 65536 (Bytes) SRAM (Bytes) 512 768 1536 3896 512 768 1536 3896 EEPROM (Bytes) 256 256 256 1024 256 256 256 1024 Interrupt Sources 26 26 33 33 26 26 33 33 I/O Ports Ports A, B, Ports A, B, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, C, (E) C, (E) (E) (E) D, E D, E D, E D, E Capture/Compare/PWM 2 2 2 2 2 2 2 2 Modules (CCP) Enhanced CCP 1 1 1 1 2 2 2 2 Modules (ECCP) Full Bridge ECCP Module 2 2 2 2 1 1 1 1 Half Bridge 10-bit Analog-to-Digital 17 input 17 input 17 input 17 input 28 input 28 input 28 input 28 input Module channels channels channels channels channels channels channels channels Packages 28-pin PDIP 28-pin PDIP 28-pin PDIP 28-pin PDIP 40-pin PDIP 40-pin PDIP 40-pin PDIP 40-pin PDIP 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin SOIC 40-pin UQFN 40-pin UQFN 40-pin UQFN 40-pin UQFN 28-pin 28-pin 28-pin SSOP 28-pin SSOP 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP SSOP SSOP 28-pin QFN 28-pin QFN 44-pin QFN 44-pin QFN 44-pin QFN 44-pin QFN 28-pin QFN 28-pin QFN 28-pin 28-pin UQFN UQFN Note1: PIC18FXXK22: operating voltage, 2.3V-5.5V. PIC18LFXXK22: operating voltage, 1.8V-3.6V.  2010-2016 Microchip Technology Inc. DS40001412G-page 535

PIC18FXXXX THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Product Support – Data sheets and errata, • Technical Support application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or Field Application Engineer (FAE) for software support. Local sales offices are also available to help customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, online discussion groups, Microchip consultant Technical support is available through the website program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. DS40001412G-page 536  2010-2016 Microchip Technology Inc.

PIC18(L)F2X/4XK22 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](2) - X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC18(L)F45K22-E/P 301 = Extended temp., Option Range PDIP package, QTP pattern #301. b) PIC18F46K22-I/SO = Industrial temp., SOIC package. c) PIC18F46K22-E/P = Extended temp., PDIP Device: PIC18F23K22, PIC18LF23K22 package. PIC18F24K22, PIC18LF24K22 PIC18F25K22, PIC18LF25K22 d) PIC18F46K22T-I/ML = Tape and reel, Industrial PIC18F26K22, PIC18LF26K22 temp., QFN package. PIC18F43K22, PIC18LF43K22 PIC18F44K22, PIC18LF44K22 PIC18F45K22, PIC18LF45K22 PIC18F46K22, PIC18LF46K22 Tape and Reel Blank = standard packaging (tube or tray) Option: T = Tape and Reel(1), (2) Note1: Tape and Reel option is available for ML, Temperature E = -40C to +125C (Extended) MV, PT, SO and SS packages with industrial Range: I = -40C to +85C (Industrial) Temperature Range only. 2: Tape and Reel identifier only appears in catalog part number description. This Package: ML = QFN identifier is used for ordering purposes and MV = UQFN is not printed on the device package. P = PDIP PT = TQFP (Thin Quad Flatpack) SO = SOIC SP = Skinny Plastic DIP SS = SSOP Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise)  2010-2016 Microchip Technology Inc. DS40001412G-page 537

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, and may be superseded by updates. It is your responsibility to dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, ensure that your application meets with your specifications. KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MICROCHIP MAKES NO REPRESENTATIONS OR MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, WARRANTIES OF ANY KIND WHETHER EXPRESS OR RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O IMPLIED, WRITTEN OR ORAL, STATUTORY OR are registered trademarks of Microchip Technology OTHERWISE, RELATED TO THE INFORMATION, Incorporated in the U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR ClockWorks, The Embedded Control Solutions Company, FITNESS FOR PURPOSE. Microchip disclaims all liability ETHERSYNCH, Hyper Speed Control, HyperLight Load, arising from this information and its use. Use of Microchip IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are devices in life support and/or safety applications is entirely at registered trademarks of Microchip Technology Incorporated the buyer’s risk, and the buyer agrees to defend, indemnify and in the U.S.A. hold harmless Microchip from any and all damages, claims, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, suits, or expenses resulting from such use. No licenses are BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, conveyed, implicitly or otherwise, under any Microchip dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, intellectual property rights unless otherwise stated. EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of Tempe, Arizona; Gresham, Oregon and design centers in California Microchip Technology Inc. in other countries. and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademark of Microchip Technology devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. QUALITY MANAGEMENT SYSTEM © 2010-2016, Microchip Technology Incorporated, Printed in CERTIFIED BY DNV the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0907-6 == ISO/TS 16949 == DS40001412G-page 538  2010-2016 Microchip Technology Inc.

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