PIC18F2455/2550/4455/4550 Data Sheet 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology © 2009 Microchip Technology Inc. DS39632E

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of Microchip MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries. WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard, arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39632E-page ii © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology Universal Serial Bus Features: Peripheral Highlights: • USB V2.0 Compliant • High-Current Sink/Source: 25mA/25mA • Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s) • Three External Interrupts • Supports Control, Interrupt, Isochronous and Bulk • Four Timer modules (Timer0 to Timer3) Transfers • Up to 2 Capture/Compare/PWM (CCP) modules: • Supports up to 32 Endpoints (16 bidirectional) - Capture is 16-bit, max. resolution 5.2ns (TCY/16) • 1 Kbyte Dual Access RAM for USB - Compare is 16-bit, max. resolution 83.3ns (TCY) • On-Chip USB Transceiver with On-Chip Voltage - PWM output: PWM resolution is 1 to 10-bit Regulator • Enhanced Capture/Compare/PWM (ECCP) module: • Interface for Off-Chip USB Transceiver - Multiple output modes • Streaming Parallel Port (SPP) for USB streaming - Selectable polarity transfers (40/44-pin devices only) - Programmable dead time - Auto-shutdown and auto-restart Power-Managed Modes: • Enhanced USART module: • Run: CPU on, Peripherals on - LIN bus support • Idle: CPU off, Peripherals on • Master Synchronous Serial Port (MSSP) module • Sleep: CPU off, Peripherals off Supporting 3-Wire SPI (all 4 modes) and I2C™ • Idle mode Currents Down to 5.8 μA Typical Master and Slave modes • Sleep mode Currents Down to 0.1 μA Typical • 10-Bit, Up to 13-Channel Analog-to-Digital Converter • Timer1 Oscillator: 1.1 μA Typical, 32 kHz, 2V (A/D) module with Programmable Acquisition Time • Watchdog Timer: 2.1 μA Typical • Dual Analog Comparators with Input Multiplexing • Two-Speed Oscillator Start-up Special Microcontroller Features: Flexible Oscillator Structure: • C Compiler Optimized Architecture with Optional • Four Crystal modes, including High-Precision PLL Extended Instruction Set for USB • 100,000 Erase/Write Cycle Enhanced Flash • Two External Clock modes, Up to 48 MHz Program Memory Typical • Internal Oscillator Block: • 1,000,000 Erase/Write Cycle Data EEPROM - 8 user-selectable frequencies, from 31kHz Memory Typical to 8MHz • Flash/Data EEPROM Retention: > 40 Years - User-tunable to compensate for frequency drift • Self-Programmable under Software Control • Secondary Oscillator using Timer1 @ 32 kHz • Priority Levels for Interrupts • Dual Oscillator Options allow Microcontroller and • 8 x 8 Single-Cycle Hardware Multiplier USB module to Run at Different Clock Speeds • Extended Watchdog Timer (WDT): • Fail-Safe Clock Monitor: - Programmable period from 41ms to 131s - Allows for safe shutdown if any clock stops • Programmable Code Protection • Single-Supply 5V In-Circuit Serial Programming™ (ICSP™) via Two Pins • In-Circuit Debug (ICD) via Two Pins • Optional Dedicated ICD/ICSP Port (44-pin, TQFP package only) • Wide Operating Voltage Range (2.0V to 5.5V) Program Memory Data Memory MSSP T ors Device (Fblyatsehs) #I nSsintrgulec-tWionosrd (SbRytAeMs) E(EbPyRteOs)M I/O A1/D0- B(ciht ) CC(PPW/EMCC)P SPP SPI MI2aCs™ter EUSAR omparat 8T/i1m6-eBrsit C PIC18F2455 24K 12288 2048 256 24 10 2/0 No Y Y 1 2 1/3 PIC18F2550 32K 16384 2048 256 24 10 2/0 No Y Y 1 2 1/3 PIC18F4455 24K 12288 2048 256 35 13 1/1 Yes Y Y 1 2 1/3 PIC18F4550 32K 16384 2048 256 35 13 1/1 Yes Y Y 1 2 1/3 © 2009 Microchip Technology Inc. DS39632E-page 1

PIC18F2455/2550/4455/4550 Pin Diagrams 28-Pin PDIP, SOIC MCLR/VPP/RE3 1 28 RB7/KBI3/PGD RA0/AN0 2 27 RB6/KBI2/PGC RA1/AN1 3 26 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 25 RB4/AN11/KBI0 RA3/AN3/VREF+ 5 50 24 RB3/AN9/CCP2(1)/VPO 55 RA4/T0CKI/C1OUT/RCV 6 45 23 RB2/AN8/INT2/VMO 22 RA5/AN4/SS/HLVDIN/C2OUT 7 FF 22 RB1/AN10/INT1/SCK/SCL 88 VSS 8 11 21 RB0/AN12/INT0/FLT0/SDI/SDA OSC1/CLKI 9 CC 20 VDD OSC2/CLKO/RA6 10 PIPI 19 VSS RC0/T1OSO/T13CKI 11 18 RC7/RX/DT/SDO RC1/T1OSI/CCP2(1)/UOE 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/D+/VP VUSB 14 15 RC4/D-/VM 40-Pin PDIP MCLR/VPP/RE3 1 40 RB7/KBI3/PGD RA0/AN0 2 39 RB6/KBI2/PGC RA1/AN1 3 38 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 37 RB4/AN11/KBI0/CSSPP RA3/AN3/VREF+ 5 36 RB3/AN9/CCP2(1)/VPO RA4/T0CKI/C1OUT/RCV 6 35 RB2/AN8/INT2/VMO RA5/AN4/SS/HLVDIN/C2OUT 7 34 RB1/AN10/INT1/SCK/SCL RE0/AN5/CK1SPP 8 50 33 RB0/AN12/INT0/FLT0/SDI/SDA RE1/AN6/CK2SPP 9 4555 32 VDD RE2/AN7/OESPP 10 F4F4 31 VSS VDD 11 88 30 RD7/SPP7/P1D 11 VSS 12 CC 29 RD6/SPP6/P1C OSC1/CLKI 13 PIPI 28 RD5/SPP5/P1B OSC2/CLKO/RA6 14 27 RD4/SPP4 RC0/T1OSO/T13CKI 15 26 RC7/RX/DT/SDO RC1/T1OSI/CCP2(1)/UOE 16 25 RC6/TX/CK RC2/CCP1/P1A 17 24 RC5/D+/VP VUSB 18 23 RC4/D-/VM RD0/SPP0 19 22 RD3/SPP3 RD1/SPP1 20 21 RD2/SPP2 Note1: RB3 is the alternate pin for CCP2 multiplexing. DS39632E-page 2 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 Pin Diagrams (Continued) E O U 1)/ (2 44-Pin TQFP TX/CKD+/VPD-/VMSPP3SPP2SPP1SPP0 CCP1/P1AT1OSI/CCP(2)CPORTS C6/C5/C4/D3/D2/D1/D0/USBC2/C1/C/I RRRRRRRVRRN 43210987654 RC7/RX/DT/SDO 1 4444433333333 NC/ICRST(2)/ICVPP(2) RD4/SPP4 2 32 RC0/T1OSO/T13CKI RD5/SPP5/P1B 3 31 OSC2/CLKO/RA6 RD6/SPP6/P1C 4 30 OSC1/CLKI RD7/SPP7/P1D 5 PIC18F4455 29 VSS VSS 6 PIC18F4550 28 VDD VDD 7 27 RE2/AN7/OESPP RB0/AN12/INT0/FLT0/SDI/SDA 8 26 RE1/AN6/CK2SPP RB1/AN10/INT1/SCK/SCL 9 25 RE0/AN5/CK1SPP RB2/AN8/INT2/VMO 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB3/AN9/CCP2(1)/VPO 11 23 RA4/T0CKI/C1OUT/RCV 23456789012 11111111222 (2)(2)NC/ICCK/ICPGC(2)(2)NC/ICDT/ICPGDRB4/AN11/KBI0/CSSPPRB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGDMCLR/V/RE3PPRA0/AN0RA1/AN1RA2/AN2/V-/CVREFREFRA3/AN3/V+REF OE A(1)P2/U13CKI 1CT 44-Pin QFN TX/CKD+/VPD-/VMSPP3SPP2SPP1SPP0 CCP1/PT1OSI/CT1OSO/ C6/C5/C4/D3/D2/D1/D0/USBC2/C1/C0/ RRRRRRRVRRR 4443424140393837363534 RC7/RX/DT/SDO 1 33 OSC2/CLKO/RA6 RD4/SPP4 2 32 OSC1/CLKI RD5/SPP5/P1B 3 31 VSS RD6/SPP6/P1C 4 30 VSS RD7/SPP7/P1D 5 PIC18F4455 29 VDD VSS 6 PIC18F4550 28 VDD VDD 7 27 RE2/AN7/OESPP VDD 8 26 RE1/AN6/CK2SPP RB0/AN12/INT0/FLT0/SDI/SDA 9 25 RE0/AN5/CK1SPP RB1/AN10/INT1/SCK/SCL 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB2/AN8/INT2/VMO 11 23 RA4/T0CKI/C1OUT/RCV 23456789012 11111111222 OCPMCD301F+ (1)RB3/AN9/CCP2/VPNRB4/AN11/KBI0/CSSPRB5/KBI1/PGRB6/KBI2/PGRB7/KBI3/PGMCLR/V/REPPRA0/ANRA1/ANRA2/AN2/V-/CVREFRERA3/AN3/VREF Note1: RB3 is the alternate pin for CCP2 multiplexing. 2: Special ICPORT features available in select circumstances. See Section25.9 “Special ICPORT Features (44-Pin TQFP Package Only)” for more information. © 2009 Microchip Technology Inc. DS39632E-page 3

PIC18F2455/2550/4455/4550 Table of Contents 1.0 Device Overview..........................................................................................................................................................................7 2.0 Oscillator Configurations............................................................................................................................................................23 3.0 Power-Managed Modes.............................................................................................................................................................35 4.0 Reset..........................................................................................................................................................................................45 5.0 Memory Organization.................................................................................................................................................................59 6.0 Flash Program Memory..............................................................................................................................................................81 7.0 Data EEPROM Memory.............................................................................................................................................................91 8.0 8 x 8 Hardware Multiplier............................................................................................................................................................97 9.0 Interrupts....................................................................................................................................................................................99 10.0 I/O Ports...................................................................................................................................................................................113 11.0 Timer0 Module.........................................................................................................................................................................127 12.0 Timer1 Module.........................................................................................................................................................................131 13.0 Timer2 Module.........................................................................................................................................................................137 14.0 Timer3 Module.........................................................................................................................................................................139 15.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................143 16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................151 17.0 Universal Serial Bus (USB)......................................................................................................................................................165 18.0 Streaming Parallel Port............................................................................................................................................................191 19.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................197 20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................243 21.0 10-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................265 22.0 Comparator Module..................................................................................................................................................................275 23.0 Comparator Voltage Reference Module...................................................................................................................................281 24.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................285 25.0 Special Features of the CPU....................................................................................................................................................291 26.0 Instruction Set Summary..........................................................................................................................................................313 27.0 Development Support...............................................................................................................................................................363 28.0 Electrical Characteristics..........................................................................................................................................................367 29.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................407 30.0 Packaging Information..............................................................................................................................................................409 Appendix A: Revision History.............................................................................................................................................................419 Appendix B: Device Differences.........................................................................................................................................................419 Appendix C: Conversion Considerations...........................................................................................................................................420 Appendix D: Migration From Baseline to Enhanced Devices.............................................................................................................420 Appendix E: Migration From Mid-Range to Enhanced Devices.........................................................................................................421 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................421 Index..................................................................................................................................................................................................423 The Microchip Web Site.....................................................................................................................................................................433 Customer Change Notification Service..............................................................................................................................................433 Customer Support..............................................................................................................................................................................433 Reader Response..............................................................................................................................................................................434 PIC18F2455/2550/4455/4550 Product Identification System............................................................................................................435 DS39632E-page 4 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. DS39632E-page 5

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 6 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 1.0 DEVICE OVERVIEW 1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES This document contains device-specific information for the following devices: All of the devices in the PIC18F2455/2550/4455/4550 family offer twelve different oscillator options, allowing • PIC18F2455 • PIC18LF2455 users a wide range of choices in developing application • PIC18F2550 • PIC18LF2550 hardware. These include: • PIC18F4455 • PIC18LF4455 • Four Crystal modes using crystals or ceramic resonators. • PIC18F4550 • PIC18LF4550 • Four External Clock modes, offering the option of This family of devices offers the advantages of all using two pins (oscillator input and a divide-by-4 PIC18 microcontrollers – namely, high computational clock output) or one pin (oscillator input, with the performance at an economical price – with the addition second pin reassigned as general I/O). of high-endurance, Enhanced Flash program • An internal oscillator block which provides an memory. In addition to these features, the 8MHz clock (±2% accuracy) and an INTRC PIC18F2455/2550/4455/4550 family introduces design source (approximately 31kHz, stable over enhancements that make these microcontrollers a log- ical choice for many high-performance, power sensitive temperature and VDD), as well as a range of 6 user-selectable clock frequencies, between applications. 125kHz to 4MHz, for a total of 8 clock frequencies. This option frees an oscillator pin for 1.1 New Core Features use as an additional general purpose I/O. 1.1.1 nanoWatt TECHNOLOGY • A Phase Lock Loop (PLL) frequency multiplier, available to both the High-Speed Crystal and All of the devices in the PIC18F2455/2550/4455/4550 External Oscillator modes, which allows a wide family incorporate a range of features that can signifi- range of clock speeds from 4MHz to 48MHz. cantly reduce power consumption during operation. • Asynchronous dual clock operation, allowing the Key items include: USB module to run from a high-frequency • Alternate Run Modes: By clocking the controller oscillator while the rest of the microcontroller is from the Timer1 source or the internal oscillator clocked from an internal low-power oscillator. block, power consumption during code execution Besides its availability as a clock source, the internal can be reduced by as much as 90%. oscillator block provides a stable reference source that • Multiple Idle Modes: The controller can also run gives the family additional features for robust with its CPU core disabled but the peripherals still operation: active. In these states, power consumption can be • Fail-Safe Clock Monitor: This option constantly reduced even further, to as little as 4%, of normal monitors the main clock source against a operation requirements. reference signal provided by the internal • On-the-Fly Mode Switching: The oscillator. If a clock failure occurs, the controller is power-managed modes are invoked by user code switched to the internal oscillator block, allowing during operation, allowing the user to incorporate for continued low-speed operation or a safe power-saving ideas into their application’s application shutdown. software design. • Two-Speed Start-up: This option allows the • Low Consumption in Key Modules: The power internal oscillator to serve as the clock source requirements for both Timer1 and the Watchdog from Power-on Reset, or wake-up from Sleep Timer are minimized. See Section28.0 mode, until the primary clock source is available. “Electrical Characteristics” for values. 1.1.2 UNIVERSAL SERIAL BUS (USB) Devices in the PIC18F2455/2550/4455/4550 family incorporate a fully featured Universal Serial Bus communications module that is compliant with the USB Specification Revision 2.0. The module supports both low-speed and full-speed communication for all sup- ported data transfer types. It also incorporates its own on-chip transceiver and 3.3V regulator and supports the use of external transceivers and voltage regulators. © 2009 Microchip Technology Inc. DS39632E-page 7

PIC18F2455/2550/4455/4550 1.2 Other Special Features 1.3 Details on Individual Family Members • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are Devices in the PIC18F2455/2550/4455/4550 family are rated to last for many thousands of erase/write available in 28-pin and 40/44-pin packages. Block cycles – up to 100,000 for program memory and diagrams for the two groups are shown in Figure1-1 1,000,000 for EEPROM. Data retention without and Figure1-2. refresh is conservatively estimated to be greater The devices are differentiated from each other in six than 40 years. ways: • Self-Programmability: These devices can write to their own program memory spaces under internal 1. Flash program memory (24Kbytes for software control. By using a bootloader routine, PIC18FX455 devices, 32Kbytes for located in the protected Boot Block at the top of PIC18FX550 devices). program memory, it becomes possible to create an 2. A/D channels (10 for 28-pin devices, 13 for application that can update itself in the field. 40/44-pin devices). • Extended Instruction Set: The 3. I/O ports (3 bidirectional ports and 1 input only PIC18F2455/2550/4455/4550 family introduces port on 28-pin devices, 5 bidirectional ports on an optional extension to the PIC18 instruction set, 40/44-pin devices). which adds 8 new instructions and an Indexed 4. CCP and Enhanced CCP implementation Literal Offset Addressing mode. This extension, (28-pin devices have two standard CCP enabled as a device configuration option, has modules, 40/44-pin devices have one standard been specifically designed to optimize re-entrant CCP module and one ECCP module). application code originally developed in high-level 5. Streaming Parallel Port (present only on languages such as C. 40/44-pin devices). • Enhanced CCP Module: In PWM mode, this All other features for devices in this family are identical. module provides 1, 2 or 4 modulated outputs for These are summarized in Table1-1. controlling half-bridge and full-bridge drivers. Other features include auto-shutdown for The pinouts for all devices are listed in Table1-2 and disabling PWM outputs on interrupt or other select Table1-3. conditions, and auto-restart to reactivate outputs Like all Microchip PIC18 devices, members of the once the condition has cleared. PIC18F2455/2550/4455/4550 family are available as • Enhanced Addressable USART: This serial both standard and low-voltage devices. Standard communication module is capable of standard devices with Enhanced Flash memory, designated with RS-232 operation and provides support for the LIN an “F” in the part number (such as PIC18F2550), bus protocol. The TX/CK and RX/DT signals can accommodate an operating VDD range of 4.2V to 5.5V. be inverted, eliminating the need for inverting Low-voltage parts, designated by “LF” (such as buffers. Other enhancements include Automatic PIC18LF2550), function over an extended VDD range Baud Rate Detection and a 16-bit Baud Rate of 2.0V to 5.5V. Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated, without waiting for a sampling period and thus, reducing code overhead. • Dedicated ICD/ICSP Port: These devices introduce the use of debugger and programming pins that are not multiplexed with other micro- controller features. Offered as an option in select packages, this feature allows users to develop I/O intensive applications while retaining the ability to program and debug in the circuit. DS39632E-page 8 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 1-1: DEVICE FEATURES Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550 Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz Program Memory (Bytes) 24576 32768 24576 32768 Program Memory (Instructions) 12288 16384 12288 16384 Data Memory (Bytes) 2048 2048 2048 2048 Data EEPROM Memory (Bytes) 256 256 256 256 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Timers 4 4 4 4 Capture/Compare/PWM Modules 2 2 1 1 Enhanced Capture/ 0 0 1 1 Compare/PWM Modules Serial Communications MSSP, MSSP, MSSP, MSSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART Universal Serial Bus (USB) 1 1 1 1 Module Streaming Parallel Port (SPP) No No Yes Yes 10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Comparators 2 2 2 2 Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), WDT WDT WDT WDT Programmable Low-Voltage Yes Yes Yes Yes Detect Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set Instruction Set Instruction Set Instruction Set enabled enabled enabled enabled Packages 28-Pin PDIP 28-Pin PDIP 40-Pin PDIP 40-Pin PDIP 28-Pin SOIC 28-Pin SOIC 44-Pin QFN 44-Pin QFN 44-Pin TQFP 44-Pin TQFP © 2009 Microchip Technology Inc. DS39632E-page 9

PIC18F2455/2550/4455/4550 FIGURE 1-1: PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch RA0/AN0 inc/dec logic 8 8 RA1/AN1 Data Memory RA2/AN2/VREF-/CVREF 21 PCLAT U PCLATH (2Kbytes) RRAA43//TA0NC3K/VI/RCE1FO+UT/RCV 20 Address Latch RA5/AN4/SS/HLVDIN/C2OUT PCU PCH PCL OSC2/CLKO/RA6 Program Counter 12 Data Address<12> 31 Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (24/32Kbytes) FSR1 Data Latch FSR2 12 PORTB RB0/AN12/INT0/FLT0/SDI/SDA inc/dec RB1/AN10/INT1/SCK/SCL 8 Table Latch logic RB2/AN8/INT2/VMO RB3/AN9/CCP2(3)/VPO RB4/AN11/KBI0 ROM Latch Address RB5/KBI1/PGM Instruction Bus <16> Decode RB6/KBI2/PGC RB7/KBI3/PGD IR 8 Instruction State Machine Decode & Control Signals Control PRODH PRODL PORTC 8 x 8 Multiply RC0/T1OSO/T13CKI 3 8 RC1/T1OSI/CCP2(3)/UOE OSC1(2) Internal Power-up RC2/CCP1 OsBcloillcaktor Timer BITOP8 W8 8 RC4/D-/VM OSC2(2) Oscillator RC5/D+/VP INTRC Start-up Timer RC6/TX/CK T1OSI Oscillator Power-on 8 8 RC7/RX/DT/SDO Reset 8 MHz ALU<8> T1OSO Oscillator Watchdog Timer 8 MCLR(1) Single-Supply BrRowesne-otut Programming In-Circuit Fail-Safe VDD,VSS Debugger Clock Monitor PORTE USB Voltage Band Gap VUSB Regulator Reference MCLR/VPP/RE3(1) BOR Data HLVD EEPROM Timer0 Timer1 Timer2 Timer3 ADC Comparator CCP1 CCP2 MSSP EUSART USB 10-Bit Note1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section2.0 “Oscillator Configurations” for additional information. 3: RB3 is the alternate pin for CCP2 multiplexing. DS39632E-page 10 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 1-2: PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA RA0/AN0 inc/dec logic 8 8 Data Latch RA1/AN1 RA2/AN2/VREF-/CVREF Data Memory RA3/AN3/VREF+ 21 PCLAT U PCLATH (2Kbytes) RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT 20 Address Latch PCU PCH PCL OSC2/CLKO/RA6 Program Counter 12 Data Address<12> PORTB 31 Level Stack RB0/AN12/INT0/FLT0/SDI/SDA Address Latch 4 12 4 RB1/AN10/INT1/SCK/SCL BSR Access Program Memory STKPTR FSR0 Bank RB2/AN8/INT2/VMO (24/32Kbytes) FSR1 RB3/AN9/CCP2(4)/VPO Data Latch FSR2 12 RB4/AN11/KBI0/CSSPP RB5/KBI1/PGM RB6/KBI2/PGC inc/dec 8 logic RB7/KBI3/PGD Table Latch Address PORTC ROM Latch Instruction Bus <16> Decode RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(4)/UOE RC2/CCP1/P1A IR RC4/D-/VM RC5/D+/VP 8 RC6/TX/CK Instruction State Machine RC7/RX/DT/SDO Decode & Control Signals Control PRODH PRODL PORTD 8 x 8 Multiply VDD, VSS 3 8 Internal OSC1(2) OsBcloillcaktor PoTwimere-rup BITO8P W8 8 RRDD05//SSPPPP05:/RP1DB4/SPP4 OSC2(2) Oscillator RD6/SPP6/P1C INTRC Start-up Timer RD7/SPP7/P1D T1OSI Oscillator 8 8 Power-on T1OSO O8s cMillHatzor Reset ALU<8> Watchdog 8 ICPGC(3) Single-Supply Timer ICPGD(3) Programming BrRowesne-otut PORTE In-Circuit RE0/AN5/CK1SPP ICPORTS(3) Debugger Fail-Safe RE1/AN6/CK2SPP ICRST(3) Clock Monitor RBeafnedr eGnacpe MREC2L/RA/NV7P/PO/REES3P(P1) MCLR(1) USB Voltage Regulator VUSB BOR Data HLVD EEPROM Timer0 Timer1 Timer2 Timer3 Comparator ECCP1 CCP2 MSSP EUSART ADC USB 10-Bit Note1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section2.0 “Oscillator Configurations” for additional information. 3: These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section25.9 “Special ICPORT Features (44-Pin TQFP Package Only)” for additional information. 4: RB3 is the alternate pin for CCP2 multiplexing. © 2009 Microchip Technology Inc. DS39632E-page 11

PIC18F2455/2550/4455/4550 TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type PDIP, SOIC MCLR/VPP/RE3 1 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI 9 Oscillator crystal or external clock input. OSC1 I Analog Oscillator crystal input or external clock source input. CLKI I Analog External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.) OSC2/CLKO/RA6 10 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. DS39632E-page 12 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP, SOIC PORTA is a bidirectional I/O port. RA0/AN0 2 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 3 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF-/CVREF 4 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Analog comparator reference output. RA3/AN3/VREF+ 5 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI/C1OUT/RCV 6 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RCV I TTL External USB transceiver RCV input. RA5/AN4/SS/ 7 HLVDIN/C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output. RA6 — — — See the OSC2/CLKO/RA6 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. © 2009 Microchip Technology Inc. DS39632E-page 13

PIC18F2455/2550/4455/4550 TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP, SOIC PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0/FLT0/ 21 SDI/SDA RB0 I/O TTL Digital I/O. AN12 I Analog Analog input 12. INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input (CCP1 module). SDI I ST SPI data in. SDA I/O ST I2C™ data I/O. RB1/AN10/INT1/SCK/ 22 SCL RB1 I/O TTL Digital I/O. AN10 I Analog Analog input 10. INT1 I ST External interrupt 1. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C mode. RB2/AN8/INT2/VMO 23 RB2 I/O TTL Digital I/O. AN8 I Analog Analog input 8. INT2 I ST External interrupt 2. VMO O — External USB transceiver VMO output. RB3/AN9/CCP2/VPO 24 RB3 I/O TTL Digital I/O. AN9 I Analog Analog input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. VPO O — External USB transceiver VPO output. RB4/AN11/KBI0 25 RB4 I/O TTL Digital I/O. AN11 I Analog Analog input 11. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1/PGM 26 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 27 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD 28 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. DS39632E-page 14 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP, SOIC PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 11 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2/UOE 12 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. UOE O — External USB transceiver OE output. RC2/CCP1 13 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. RC4/D-/VM 15 RC4 I TTL Digital input. D- I/O — USB differential minus line (input/output). VM I TTL External USB transceiver VM input. RC5/D+/VP 16 RC5 I TTL Digital input. D+ I/O — USB differential plus line (input/output). VP O TTL External USB transceiver VP input. RC6/TX/CK 17 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see RX/DT). RC7/RX/DT/SDO 18 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see TX/CK). SDO O — SPI data out. RE3 — — — See MCLR/VPP/RE3 pin. VUSB 14 P — Internal USB 3.3V voltage regulator output, positive supply for internal USB transceiver. VSS 8, 19 P — Ground reference for logic and I/O pins. VDD 20 P — Positive supply for logic and I/O pins. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. © 2009 Microchip Technology Inc. DS39632E-page 15

PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP MCLR/VPP/RE3 1 18 18 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI 13 32 30 Oscillator crystal or external clock input. OSC1 I Analog Oscillator crystal input or external clock source input. CLKI I Analog External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.) OSC2/CLKO/RA6 14 33 31 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. DS39632E-page 16 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTA is a bidirectional I/O port. RA0/AN0 2 19 19 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 3 20 20 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF-/ 4 21 21 CVREF RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Analog comparator reference output. RA3/AN3/VREF+ 5 22 22 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI/C1OUT/ 6 23 23 RCV RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RCV I TTL External USB transceiver RCV input. RA5/AN4/SS/ 7 24 24 HLVDIN/C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output. RA6 — — — — — See the OSC2/CLKO/RA6 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. DS39632E-page 17

PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0/ 33 9 8 FLT0/SDI/SDA RB0 I/O TTL Digital I/O. AN12 I Analog Analog input 12. INT0 I ST External interrupt 0. FLT0 I ST Enhanced PWM Fault input (ECCP1 module). SDI I ST SPI data in. SDA I/O ST I2C™ data I/O. RB1/AN10/INT1/SCK/ 34 10 9 SCL RB1 I/O TTL Digital I/O. AN10 I Analog Analog input 10. INT1 I ST External interrupt 1. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C mode. RB2/AN8/INT2/VMO 35 11 10 RB2 I/O TTL Digital I/O. AN8 I Analog Analog input 8. INT2 I ST External interrupt 2. VMO O — External USB transceiver VMO output. RB3/AN9/CCP2/VPO 36 12 11 RB3 I/O TTL Digital I/O. AN9 I Analog Analog input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. VPO O — External USB transceiver VPO output. RB4/AN11/KBI0/CSSPP 37 14 14 RB4 I/O TTL Digital I/O. AN11 I Analog Analog input 11. KBI0 I TTL Interrupt-on-change pin. CSSPP O — SPP chip select control output. RB5/KBI1/PGM 38 15 15 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 39 16 16 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD 40 17 17 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. DS39632E-page 18 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 15 34 32 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2/ 16 35 35 UOE RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. UOE O — External USB transceiver OE output. RC2/CCP1/P1A 17 36 36 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O TTL Enhanced CCP1 PWM output, channel A. RC4/D-/VM 23 42 42 RC4 I TTL Digital input. D- I/O — USB differential minus line (input/output). VM I TTL External USB transceiver VM input. RC5/D+/VP 24 43 43 RC5 I TTL Digital input. D+ I/O — USB differential plus line (input/output). VP I TTL External USB transceiver VP input. RC6/TX/CK 25 44 44 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see RX/DT). RC7/RX/DT/SDO 26 1 1 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see TX/CK). SDO O — SPI data out. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. DS39632E-page 19

PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTD is a bidirectional I/O port or a Streaming Parallel Port (SPP). These pins have TTL input buffers when the SPP module is enabled. RD0/SPP0 19 38 38 RD0 I/O ST Digital I/O. SPP0 I/O TTL Streaming Parallel Port data. RD1/SPP1 20 39 39 RD1 I/O ST Digital I/O. SPP1 I/O TTL Streaming Parallel Port data. RD2/SPP2 21 40 40 RD2 I/O ST Digital I/O. SPP2 I/O TTL Streaming Parallel Port data. RD3/SPP3 22 41 41 RD3 I/O ST Digital I/O. SPP3 I/O TTL Streaming Parallel Port data. RD4/SPP4 27 2 2 RD4 I/O ST Digital I/O. SPP4 I/O TTL Streaming Parallel Port data. RD5/SPP5/P1B 28 3 3 RD5 I/O ST Digital I/O. SPP5 I/O TTL Streaming Parallel Port data. P1B O — Enhanced CCP1 PWM output, channel B. RD6/SPP6/P1C 29 4 4 RD6 I/O ST Digital I/O. SPP6 I/O TTL Streaming Parallel Port data. P1C O — Enhanced CCP1 PWM output, channel C. RD7/SPP7/P1D 30 5 5 RD7 I/O ST Digital I/O. SPP7 I/O TTL Streaming Parallel Port data. P1D O — Enhanced CCP1 PWM output, channel D. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. DS39632E-page 20 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTE is a bidirectional I/O port. RE0/AN5/CK1SPP 8 25 25 RE0 I/O ST Digital I/O. AN5 I Analog Analog input 5. CK1SPP O — SPP clock 1 output. RE1/AN6/CK2SPP 9 26 26 RE1 I/O ST Digital I/O. AN6 I Analog Analog input 6. CK2SPP O — SPP clock 2 output. RE2/AN7/OESPP 10 27 27 RE2 I/O ST Digital I/O. AN7 I Analog Analog input 7. OESPP O — SPP output enable output. RE3 — — — — — See MCLR/VPP/RE3 pin. VSS 12, 31 6, 30, 6, 29 P — Ground reference for logic and I/O pins. 31 VDD 11, 32 7, 8, 7, 28 P — Positive supply for logic and I/O pins. 28, 29 VUSB 18 37 37 P — Internal USB 3.3V voltage regulator output, positive supply for the USB transceiver. NC/ICCK/ICPGC(3) — — 12 No Connect or dedicated ICD/ICSP™ port clock. ICCK I/O ST In-Circuit Debugger clock. ICPGC I/O ST ICSP programming clock. NC/ICDT/ICPGD(3) — — 13 No Connect or dedicated ICD/ICSP port clock. ICDT I/O ST In-Circuit Debugger data. ICPGD I/O ST ICSP programming data. NC/ICRST/ICVPP(3) — — 33 No Connect or dedicated ICD/ICSP port Reset. ICRST I — Master Clear (Reset) input. ICVPP P — Programming voltage input. NC/ICPORTS(3) — — 34 P — No Connect or 28-pin device emulation. ICPORTS Enable 28-pin device emulation when connected to VSS. NC — 13 — — — No Connect. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. DS39632E-page 21

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 22 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 2.0 OSCILLATOR 2.2 Oscillator Types CONFIGURATIONS PIC18F2455/2550/4455/4550 devices can be operated in twelve distinct oscillator modes. In contrast with pre- 2.1 Overview vious PIC18 enhanced microcontrollers, four of these modes involve the use of two oscillator types at once. Devices in the PIC18F2455/2550/4455/4550 family Users can program the FOSC3:FOSC0 Configuration incorporate a different oscillator and microcontroller bits to select one of these modes: clock system than previous PIC18F devices. The addi- 1. XT Crystal/Resonator tion of the USB module, with its unique requirements for a stable clock source, make it necessary to provide 2. HS High-Speed Crystal/Resonator a separate clock source that is compliant with both 3. HSPLL High-Speed Crystal/Resonator USB low-speed and full-speed specifications. with PLL Enabled To accommodate these requirements, PIC18F2455/ 4. EC External Clock with FOSC/4 Output 2550/4455/4550 devices include a new clock branch to 5. ECIO External Clock with I/O on RA6 provide a 48MHz clock for full-speed USB operation. 6. ECPLL External Clock with PLL Enabled Since it is driven from the primary clock source, an and FOSC/4 Output on RA6 additional system of prescalers and postscalers has 7. ECPIO External Clock with PLL Enabled, been added to accommodate a wide range of oscillator I/O on RA6 frequencies. An overview of the oscillator structure is shown in Figure2-1. 8. INTHS Internal Oscillator used as Microcontroller Clock Source, HS Other oscillator features used in PIC18 enhanced Oscillator used as USB Clock Source microcontrollers, such as the internal oscillator block 9. INTIO Internal Oscillator used as and clock switching, remain the same. They are Microcontroller Clock Source, EC discussed later in this chapter. Oscillator used as USB Clock Source, 2.1.1 OSCILLATOR CONTROL Digital I/O on RA6 10. INTCKOInternal Oscillator used as The operation of the oscillator in PIC18F2455/2550/ Microcontroller Clock Source, EC 4455/4550 devices is controlled through two Configu- Oscillator used as USB Clock Source, ration registers and two control registers. Configuration registers, CONFIG1L and CONFIG1H, select the FOSC/4 Output on RA6 oscillator mode and USB prescaler/postscaler options. 2.2.1 OSCILLATOR MODES AND As Configuration bits, these are set when the device is USB OPERATION programmed and left in that configuration until the device is reprogrammed. Because of the unique requirements of the USB module, The OSCCON register (Register2-2) selects the Active a different approach to clock operation is necessary. In Clock mode; it is primarily used in controlling clock previous PIC® devices, all core and peripheral clocks switching in power-managed modes. Its use is were driven by a single oscillator source; the usual discussed in Section2.4.1 “Oscillator Control sources were primary, secondary or the internal oscilla- Register”. tor. With PIC18F2455/2550/4455/4550 devices, the pri- mary oscillator becomes part of the USB module and The OSCTUNE register (Register2-1) is used to trim cannot be associated to any other clock source. Thus, the INTRC frequency source, as well as select the the USB module must be clocked from the primary clock low-frequency clock source that drives several special source; however, the microcontroller core and other features. Its use is described in Section2.2.5.2 peripherals can be separately clocked from the “OSCTUNE Register”. secondary or internal oscillators as before. Because of the timing requirements imposed by USB, an internal clock of either 6MHz or 48MHz is required while the USB module is enabled. Fortunately, the microcontroller and other peripherals are not required to run at this clock speed when using the primary oscillator. There are numerous options to achieve the USB module clock requirement and still provide flexibil- ity for clocking the rest of the device from the primary oscillator source. These are detailed in Section2.3 “Oscillator Settings for USB”. © 2009 Microchip Technology Inc. DS39632E-page 23

PIC18F2455/2550/4455/4550 FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM PIC18F2455/2550/4455/4550 PLLDIV USB Clock Source ÷ 12 111 ÷ 10 110 USBDIV ÷ 6 er 101 (4 MHz Input Only) Primary Oscillator al ÷ 5 0 OSC2 Presc ÷ 4 100101MUX 96P MLLHz ÷ 2 1 Sleep L ÷ 3 L 010 P OSC1 ÷ 2 001 FSEN ÷ 1 000 HSPLL, ECPLL, 1 USB XTPLL, ECPIO Peripheral CPUDIV er ÷ 6 11 ÷ 4 0 CPUDIV scal ÷ 4 10 XT, HS, EC, ECIO ator Postscaler ÷÷÷÷ 1234 110101 PLL Post ÷÷ 23 0010 01 Primary CPU cill 00 Clock IDLEN Os FOSC3:FOSC0 Secondary Oscillator X Peripherals T1OSO U T1OSC M T1OSCEN Enable T1OSI Oscillator OSCCON<6:4> Internal Oscillator 8 MHz 111 4 MHz OInsBctleiolrlcnaktaolr caler 2 MHz 111001 CColonctrkol SI8No MTuRrHcCze (IN8 TMOHSzC) OSC Posts 5205100 M kkHHHzzz 100011010MUX FOSC3:FOS C0 OSCCON< 1:0> Source INT 125 kHz 001 Clock Source Option 31 kHz (INTRC) 1 31 kHz 000 for Other Modules 0 OSCTUNE<7> WDT, PWRT, FSCM and Two-Speed Start-up DS39632E-page 24 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 2.2.2 CRYSTAL OSCILLATOR/CERAMIC TABLE 2-1: CAPACITOR SELECTION FOR RESONATORS CERAMIC RESONATORS In HS, HSPLL, XT and XTPLL Oscillator modes, a Typical Capacitor Values Used: crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure2-2 Mode Freq OSC1 OSC2 shows the pin connections. XT 4.0 MHz 33 pF 33 pF The oscillator design requires the use of a parallel cut HS 8.0 MHz 27 pF 27 pF crystal. 16.0 MHz 22 pF 22 pF Note: Use of a series cut crystal may give a fre- Capacitor values are for design guidance only. quency out of the crystal manufacturer’s These capacitors were tested with the resonators specifications. listed below for basic start-up and operation. These values are not optimized. FIGURE 2-2: CRYSTAL/CERAMIC Different capacitor values may be required to produce RESONATOR OPERATION acceptable oscillator operation. The user should test (XT, HS OR HSPLL the performance of the oscillator over the expected CONFIGURATION) VDD and temperature range for the application. C1(1) OSC1 See the notes following Table2-2 for additional information. To Internal Resonators Used: XTAL (3) Logic RF 4.0 MHz Sleep 8.0 MHz RS(2) C2(1) OSC2 PIC18FXXXX 16.0 MHz When using ceramic resonators with frequencies Note 1: See Table2-1 and Table2-2 for initial values of above 3.5MHz, HS mode is recommended over XT C1 and C2. mode. HS mode may be used at any VDD for which 2: A series resistor (RS) may be required for AT the controller is rated. If HS is selected, the gain of the strip cut crystals. oscillator may overdrive the resonator. Therefore, a 3: RF varies with the oscillator mode chosen. series resistor should be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of RS is 330Ω. © 2009 Microchip Technology Inc. DS39632E-page 25

PIC18F2455/2550/4455/4550 TABLE 2-2: CAPACITOR SELECTION FOR FIGURE 2-3: EXTERNAL CLOCK INPUT CRYSTAL OSCILLATOR OPERATION (HS OSC CONFIGURATION) Typical Capacitor Values Crystal Tested: Osc Type Freq Clock from OSC1 C1 C2 Ext. System PIC18FXXXX XT 4 MHz 27 pF 27 pF (HS Mode) Open OSC2 HS 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 2.2.3 EXTERNAL CLOCK INPUT 20 MHz 15 pF 15 pF Capacitor values are for design guidance only. The EC, ECIO, ECPLL and ECPIO Oscillator modes require an external clock source to be connected to the These capacitors were tested with the crystals listed OSC1 pin. There is no oscillator start-up time required below for basic start-up and operation. These values after a Power-on Reset or after an exit from Sleep are not optimized. mode. Different capacitor values may be required to produce In the EC and ECPLL Oscillator modes, the oscillator acceptable oscillator operation. The user should test frequency divided by 4 is available on the OSC2 pin. the performance of the oscillator over the expected This signal may be used for test purposes or to VDD and temperature range for the application. synchronize other logic. Figure2-4 shows the pin See the notes following this table for additional connections for the EC Oscillator mode. information. Crystals Used: FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION 4 MHz (EC AND ECPLL 8 MHz CONFIGURATION) 20 MHz Clock from OSC1/CLKI Note1: Higher capacitance increases the stability Ext. System PIC18FXXXX of oscillator but also increases the FOSC/4 OSC2/CLKO start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any The ECIO and ECPIO Oscillator modes function like the voltage, it may be necessary to use the EC and ECPLL modes, except that the OSC2 pin HS mode or switch to a crystal oscillator. becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure2-5 shows 3: Since each resonator/crystal has its own the pin connections for the ECIO Oscillator mode. characteristics, the user should consult the resonator/crystal manufacturer for FIGURE 2-5: EXTERNAL CLOCK appropriate values of external INPUT OPERATION components. (ECIO AND ECPIO 4: Rs may be required to avoid overdriving CONFIGURATION) crystals with low drive level specification. 5: Always verify oscillator performance over the VDD and temperature range that is Clock from OSC1/CLKI expected for the application. Ext. System PIC18FXXXX An internal postscaler allows users to select a clock RA6 I/O (OSC2) frequency other than that of the crystal or resonator. Frequency division is determined by the CPUDIV Configuration bits. Users may select a clock frequency The internal postscaler for reducing clock frequency in of the oscillator frequency, or 1/2, 1/3 or 1/4 of the XT and HS modes is also available in EC and ECIO frequency. modes. An external clock may also be used when the micro- controller is in HS Oscillator mode. In this case, the OSC2/CLKO pin is left open (Figure2-3). DS39632E-page 26 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 2.2.4 PLL FREQUENCY MULTIPLIER 2.2.5 INTERNAL OSCILLATOR BLOCK PIC18F2455/2550/4255/4550 devices include a Phase The PIC18F2455/2550/4455/4550 devices include an Locked Loop (PLL) circuit. This is provided specifically internal oscillator block which generates two different for USB applications with lower speed oscillators and clock signals; either can be used as the microcontroller’s can also be used as a microcontroller clock source. clock source. If the USB peripheral is not used, the internal oscillator may eliminate the need for external The PLL is enabled in HSPLL, XTPLL, ECPLL and oscillator circuits on the OSC1 and/or OSC2 pins. ECPIO Oscillator modes. It is designed to produce a fixed 96MHz reference clock from a fixed 4MHz input. The main output (INTOSC) is an 8MHz clock source The output can then be divided and used for both the which can be used to directly drive the device clock. It USB and the microcontroller core clock. Because the also drives the INTOSC postscaler which can provide a PLL has a fixed frequency input and output, there are range of clock frequencies from 31kHz to 4MHz. The eight prescaling options to match the oscillator input INTOSC output is enabled when a clock frequency frequency to the PLL. from 125kHz to 8MHz is selected. There is also a separate postscaler option for deriving The other clock source is the internal RC oscillator the microcontroller clock from the PLL. This allows the (INTRC) which provides a nominal 31kHz output. USB peripheral and microcontroller to use the same INTRC is enabled if it is selected as the device clock oscillator input and still operate at different clock source; it is also enabled automatically when any of the speeds. In contrast to the postscaler for XT, HS and EC following are enabled: modes, the available options are 1/2, 1/3, 1/4 and 1/6 • Power-up Timer of the PLL output. • Fail-Safe Clock Monitor The HSPLL, ECPLL and ECPIO modes make use of • Watchdog Timer the HS mode oscillator for frequencies up to 48MHz. • Two-Speed Start-up The prescaler divides the oscillator input by up to 12 to produce the 4MHz drive for the PLL. The XTPLL mode These features are discussed in greater detail in can only use an input frequency of 4MHz which drives Section25.0 “Special Features of the CPU”. the PLL directly. The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring FIGURE 2-6: PLL BLOCK DIAGRAM the IRCF bits of the OSCCON register (page33). (HS MODE) 2.2.5.1 Internal Oscillator Modes HS/EC/ECIO/XT Oscillator Enable When the internal oscillator is used as the micro- PLL Enable (from CONFIG1H Register) controller clock source, one of the other oscillator modes (External Clock or External Crystal/Resonator) must be used as the USB clock source. The choice of OSC2 Phase the USB clock source is determined by the particular Oscillator FIN Comparator internal oscillator mode. OSC1 Preasncdaler FOUT There are four distinct modes available: 1. INTHS mode: The USB clock is provided by the Loop oscillator in HS mode. Filter 2. INTXT mode: The USB clock is provided by the oscillator in XT mode. 3. INTCKO mode: The USB clock is provided by an ÷24 VCO SYSCLK external clock input on OSC1/CLKI; the OSC2/ X U CLKO pin outputs FOSC/4. M 4. INTIO mode: The USB clock is provided by an external clock input on OSC1/CLKI; the OSC2/ CLKO pin functions as a digital I/O (RA6). Of these four modes, only INTIO mode frees up an additional pin (OSC2/CLKO/RA6) for port I/O use. © 2009 Microchip Technology Inc. DS39632E-page 27

PIC18F2455/2550/4455/4550 2.2.5.2 OSCTUNE Register 2.2.5.3 Internal Oscillator Output Frequency and Drift The internal oscillator’s output has been calibrated at the factory but can be adjusted in the user’s applica- The internal oscillator block is calibrated at the factory tion. This is done by writing to the OSCTUNE register to produce an INTOSC output frequency of 8.0MHz. (Register2-1). The tuning sensitivity is constant However, this frequency may drift as VDD or tempera- throughout the tuning range. ture changes, which can affect the controller operation in a variety of ways. The INTOSC clock will stabilize within 1ms. Code exe- cution continues during this shift. There is no indication The low-frequency INTRC oscillator operates indepen- that the shift has occurred. dently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily The OSCTUNE register also contains the INTSRC bit. reflected by changes in INTRC and vice versa. The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31kHz frequency option is selected. This is covered in greater detail in Section2.4.1 “Oscillator Control Register”. REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC — — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock derived from 8MHz INTOSC source (divide-by-256 enabled) 0 = 31kHz device clock derived directly from INTRC internal oscillator bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 TUN4:TUN0: Frequency Tuning bits 01111 = Maximum frequency • • • • 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 • • • • 10000 = Minimum frequency DS39632E-page 28 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 2.2.5.4 Compensating for INTOSC Drift Finally, a CCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an It is possible to adjust the INTOSC frequency by external event with a known period (i.e., AC power modifying the value in the OSCTUNE register. This has frequency). The time of the first event is captured in the no effect on the INTRC clock source frequency. CCPRxH:CCPRxL registers and is recorded for use Tuning the INTOSC source requires knowing when to later. When the second event causes a capture, the make the adjustment, in which direction it should be time of the first event is subtracted from the time of the made and in some cases, how large a change is second event. Since the period of the external event is needed. When using the EUSART, for example, an known, the time difference between events can be adjustment may be required when it begins to generate calculated. framing errors or receives data with errors while in If the measured time is much greater than the calcu- Asynchronous mode. Framing errors indicate that the lated time, the internal oscillator block is running too device clock frequency is too high; to adjust for this, fast; to compensate, decrement the OSCTUNE register. decrement the value in OSCTUNE to reduce the clock If the measured time is much less than the calculated frequency. On the other hand, errors in data may sug- time, the internal oscillator block is running too slow; to gest that the clock speed is too low; to compensate, compensate, increment the OSCTUNE register. increment OSCTUNE to increase the clock frequency. It is also possible to verify device clock speed against a reference clock. Two timers may be used: one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. © 2009 Microchip Technology Inc. DS39632E-page 29

PIC18F2455/2550/4455/4550 2.3 Oscillator Settings for USB active and the controller clock source is one of the primary oscillator modes (XT, HS or EC, with or without When these devices are used for USB connectivity, the PLL). they must have either a 6MHz or 48MHz clock for This restriction does not apply if the microcontroller USB operation, depending on whether Low-Speed or clock source is the secondary oscillator or internal Full-Speed mode is being used. This may require some oscillator block. forethought in selecting an oscillator frequency and programming the device. 2.3.2 RUNNING DIFFERENT USB AND The full range of possible oscillator configurations MICROCONTROLLER CLOCKS compatible with USB operation is shown in Table2-3. The USB module, in either mode, can run asynchro- 2.3.1 LOW-SPEED OPERATION nously with respect to the microcontroller core and other peripherals. This means that applications can use The USB clock for Low-Speed mode is derived from the the primary oscillator for the USB clock while the micro- primary oscillator chain and not directly from the PLL. It controller runs from a separate clock source at a lower is divided by 4 to produce the actual 6MHz clock. speed. If it is necessary to run the entire application Because of this, the microcontroller can only use a from only one clock source, full-speed operation clock frequency of 24MHz when the USB module is provides a greater selection of microcontroller clock frequencies. TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION Input Oscillator PLL Division Clock Mode MCU Clock Division Microcontroller Frequency (PLLDIV2:PLLDIV0) (FOSC3:FOSC0) (CPUDIV1:CPUDIV0) Clock Frequency 48MHz N/A(1) EC, ECIO None (00) 48MHz ÷2 (01) 24MHz ÷3 (10) 16MHz ÷4 (11) 12MHz 48MHz ÷12 (111) EC, ECIO None (00) 48MHz ÷2 (01) 24MHz ÷3 (10) 16MHz ÷4 (11) 12MHz ECPLL, ECPIO ÷2 (00) 48MHz ÷3 (01) 32MHz ÷4 (10) 24MHz ÷6 (11) 16MHz 40MHz ÷10 (110) EC, ECIO None (00) 40MHz ÷2 (01) 20MHz ÷3 (10) 13.33MHz ÷4 (11) 10MHz ECPLL, ECPIO ÷2 (00) 48MHz ÷3 (01) 32MHz ÷4 (10) 24MHz ÷6 (11) 16MHz 24MHz ÷6 (101) HS, EC, ECIO None (00) 24MHz ÷2 (01) 12MHz ÷3 (10) 8MHz ÷4 (11) 6MHz HSPLL, ECPLL, ECPIO ÷2 (00) 48MHz ÷3 (01) 32MHz ÷4 (10) 24MHz ÷6 (11) 16MHz Legend: All clock frequencies, except 24MHz, are exclusively associated with full-speed USB operation (USB clock of 48MHz). Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24MHz, USB clock of 6MHz). Note 1: Only valid when the USBDIV Configuration bit is cleared. DS39632E-page 30 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED) Input Oscillator PLL Division Clock Mode MCU Clock Division Microcontroller Frequency (PLLDIV2:PLLDIV0) (FOSC3:FOSC0) (CPUDIV1:CPUDIV0) Clock Frequency 20MHz ÷5 (100) HS, EC, ECIO None (00) 20MHz ÷2 (01) 10MHz ÷3 (10) 6.67MHz ÷4 (11) 5MHz HSPLL, ECPLL, ECPIO ÷2 (00) 48MHz ÷3 (01) 32MHz ÷4 (10) 24MHz ÷6 (11) 16MHz 16MHz ÷4 (011) HS, EC, ECIO None (00) 16MHz ÷2 (01) 8MHz ÷3 (10) 5.33MHz ÷4 (11) 4MHz HSPLL, ECPLL, ECPIO ÷2 (00) 48MHz ÷3 (01) 32MHz ÷4 (10) 24MHz ÷6 (11) 16MHz 12MHz ÷3 (010) HS, EC, ECIO None (00) 12MHz ÷2 (01) 6MHz ÷3 (10) 4MHz ÷4 (11) 3MHz HSPLL, ECPLL, ECPIO ÷2 (00) 48MHz ÷3 (01) 32MHz ÷4 (10) 24MHz ÷6 (11) 16MHz 8MHz ÷2 (001) HS, EC, ECIO None (00) 8MHz ÷2 (01) 4MHz ÷3 (10) 2.67MHz ÷4 (11) 2MHz HSPLL, ECPLL, ECPIO ÷2 (00) 48MHz ÷3 (01) 32MHz ÷4 (10) 24MHz ÷6 (11) 16MHz 4MHz ÷1 (000) XT, HS, EC, ECIO None (00) 4MHz ÷2 (01) 2MHz ÷3 (10) 1.33MHz ÷4 (11) 1MHz HSPLL, ECPLL, XTPLL, ÷2 (00) 48MHz ECPIO ÷3 (01) 32MHz ÷4 (10) 24MHz ÷6 (11) 16MHz Legend: All clock frequencies, except 24MHz, are exclusively associated with full-speed USB operation (USB clock of 48MHz). Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24MHz, USB clock of 6MHz). Note 1: Only valid when the USBDIV Configuration bit is cleared. © 2009 Microchip Technology Inc. DS39632E-page 31

PIC18F2455/2550/4455/4550 2.4 Clock Sources and Oscillator The Internal Oscillator Frequency Select bits, Switching IRCF2:IRCF0, select the frequency output of the internal oscillator block to drive the device clock. The choices are Like previous PIC18 enhanced devices, the the INTRC source, the INTOSC source (8MHz) or one PIC18F2455/2550/4455/4550 family includes a feature of the frequencies derived from the INTOSC postscaler that allows the device clock source to be switched from (31kHz to 4MHz). If the internal oscillator block is the main oscillator to an alternate, low-frequency clock supplying the device clock, changing the states of these source. These devices offer two alternate clock bits will have an immediate change on the internal oscil- sources. When an alternate clock source is enabled, lator’s output. On device Resets, the default output the various power-managed operating modes are frequency of the internal oscillator block is set at 1MHz. available. When an output frequency of 31kHz is selected Essentially, there are three clock sources for these (IRCF2:IRCF0 = 000), users may choose which inter- devices: nal oscillator acts as the source. This is done with the • Primary oscillators INTSRC bit in the OSCTUNE register (OSCTUNE<7>). Setting this bit selects INTOSC as a 31.25kHz clock • Secondary oscillators source by enabling the divide-by-256 output of the • Internal oscillator block INTOSC postscaler. Clearing INTSRC selects INTRC The primary oscillators include the External Crystal (nominally 31kHz) as the clock source. and Resonator modes, the External Clock modes and This option allows users to select the tunable and more the internal oscillator block. The particular mode is precise INTOSC as a clock source, while maintaining defined by the FOSC3:FOSC0 Configuration bits. The power savings with a very low clock speed. Regardless details of these modes are covered earlier in this of the setting of INTSRC, INTRC always remains the chapter. clock source for features such as the Watchdog Timer The secondary oscillators are those external sources and the Fail-Safe Clock Monitor. not connected to the OSC1 or OSC2 pins. These The OSTS, IOFS and T1RUN bits indicate which clock sources may continue to operate even after the source is currently providing the device clock. The OSTS controller is placed in a power-managed mode. bit indicates that the Oscillator Start-up Timer (OST) has PIC18F2455/2550/4455/4550 devices offer the Timer1 timed out and the primary clock is providing the device oscillator as a secondary oscillator. This oscillator, in all clock in primary clock modes. The IOFS bit indicates power-managed modes, is often the time base for when the internal oscillator block has stabilized and is functions such as a Real-Time Clock (RTC). Most providing the device clock in RC Clock modes. The often, a 32.768kHz watch crystal is connected T1RUN bit (T1CON<6>) indicates when the Timer1 oscil- between the RC0/T1OSO/T13CKI and RC1/T1OSI/ lator is providing the device clock in secondary clock UOE pins. Like the XT and HS Oscillator mode circuits, modes. In power-managed modes, only one of these loading capacitors are also connected from each pin to three bits will be set at any time. If none of these bits are ground. The Timer1 oscillator is discussed in greater set, the INTRC is providing the clock or the internal detail in Section12.3 “Timer1 Oscillator”. oscillator block has just started and is not yet stable. In addition to being a primary clock source, the internal The IDLEN bit determines if the device goes into Sleep oscillator block is available as a power-managed mode, or one of the Idle modes, when the SLEEP mode clock source. The INTRC source is also used as instruction is executed. the clock source for several special features, such as The use of the flag and control bits in the OSCCON the WDT and Fail-Safe Clock Monitor. register is discussed in more detail in Section3.0 “Power-Managed Modes”. 2.4.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register2-2) controls several Note 1: The Timer1 oscillator must be enabled to aspects of the device clock’s operation, both in select the secondary clock source. The full-power operation and in power-managed modes. Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control regis- The System Clock Select bits, SCS1:SCS0, select the ter (T1CON<3>). If the Timer1 oscillator is clock source. The available clock sources are the not enabled, then any attempt to select a primary clock (defined by the FOSC3:FOSC0 Configu- secondary clock source will be ignored. ration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock source changes 2: It is recommended that the Timer1 immediately after one or more of the bits is written to, oscillator be operating and stable prior to following a brief clock transition interval. The SCS bits switching to it as the clock source; other- are cleared on all forms of Reset. wise, a very long delay may occur while the Timer1 oscillator starts. DS39632E-page 32 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 2.4.2 OSCILLATOR TRANSITIONS sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula PIC18F2455/2550/4455/4550 devices contain circuitry assumes that the new clock source is stable. to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs Clock transitions are discussed in greater detail in during the clock switch. The length of this pause is the Section3.1.2 “Entering Power-Managed Modes”. REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8MHz (INTOSC drives clock directly) 110 = 4MHz 101 = 2MHz 100 = 1MHz(3) 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31kHz (from either INTOSC/256 or INTRC directly)(2) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable bit 1-0 SCS1:SCS0: System Clock Select bits 1x = Internal oscillator 01 = Timer1 oscillator 00 = Primary oscillator Note 1: Depends on the state of the IESO Configuration bit. 2: Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. © 2009 Microchip Technology Inc. DS39632E-page 33

PIC18F2455/2550/4455/4550 2.5 Effects of Power-Managed Modes command over the USB. Once the module has sus- on the Various Clock Sources pended operation and shifted to a low-power state, the microcontroller may be safely put into Sleep mode. When PRI_IDLE mode is selected, the designated Enabling any on-chip feature that will operate during primary oscillator continues to run without interruption. Sleep will increase the current consumed during Sleep. For all other power-managed modes, the oscillator The INTRC is required to support WDT operation. The using the OSC1 pin is disabled. Unless the USB Timer1 oscillator may be operating to support a module is enabled, the OSC1 pin (and OSC2 pin if Real-Time Clock. Other features may be operating that used by the oscillator) will stop oscillating. do not require a device clock source (i.e., MSSP slave, In secondary clock modes (SEC_RUN and PSP, INTx pins and others). Peripherals that may add SEC_IDLE), the Timer1 oscillator is operating and significant current consumption are listed in providing the device clock. The Timer1 oscillator may Section28.2 “DC Characteristics: Power-Down and also run in all power-managed modes if required to Supply Current”. clock Timer1 or Timer3. In internal oscillator modes (RC_RUN and RC_IDLE), 2.6 Power-up Delays the internal oscillator block provides the device clock Power-up delays are controlled by two timers so that no source. The 31kHz INTRC output can be used directly external Reset circuitry is required for most applications. to provide the clock and may be enabled to support The delays ensure that the device is kept in Reset until various special features regardless of the the device power supply is stable under normal circum- power-managed mode (see Section25.2 “Watchdog stances and the primary clock is operating and stable. Timer (WDT)”, Section25.3 “Two-Speed Start-up” For additional information on power-up delays, see and Section25.4 “Fail-Safe Clock Monitor” for more Section4.5 “Device Reset Timers”. information on WDT, Fail-Safe Clock Monitor and Two-Speed Start-up). The INTOSC output at 8MHz The first timer is the Power-up Timer (PWRT), which may be used directly to clock the device or may be provides a fixed delay on power-up (parameter 33, divided down by the postscaler. The INTOSC output is Table28-12). It is enabled by clearing (= 0) the disabled if the clock is provided directly from the INTRC PWRTEN Configuration bit. output. The second timer is the Oscillator Start-up Timer Regardless of the Run or Idle mode selected, the USB (OST), intended to keep the chip in Reset until the clock source will continue to operate. If the device is crystal oscillator is stable (XT and HS modes). The operating from a crystal or resonator-based oscillator, OST does this by counting 1024 oscillator cycles that oscillator will continue to clock the USB module. before allowing the oscillator to clock the device. The core and all other modules will switch to the new When the HSPLL Oscillator mode is selected, the clock source. device is kept in Reset for an additional 2ms following If the Sleep mode is selected, all clock sources are the HS mode OST delay, so the PLL can lock to the stopped. Since all the transistor switching currents incoming clock frequency. have been stopped, Sleep mode achieves the lowest There is a delay of interval, TCSD (parameter 38, current consumption of the device (only leakage Table28-12), following POR, while the controller currents). becomes ready to execute instructions. This delay runs Sleep mode should never be invoked while the USB concurrently with any other delays. This may be the module is operating and connected. The only exception only delay that occurs when any of the EC or internal is when the device has been issued a “Suspend” oscillator modes are used as the primary clock source. TABLE 2-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin INTCKO Floating, pulled by external clock At logic low (clock/4 output) INTIO Floating, pulled by external clock Configured as PORTA, bit 6 ECIO, ECPIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) XT and HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table4-2 in Section4.0 “Reset” for time-outs due to Sleep and MCLR Reset. DS39632E-page 34 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 3.0 POWER-MANAGED MODES 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three PIC18F2455/2550/4455/4550 devices offer a total of clock sources for power-managed modes. They are: seven operating modes for more efficient power management. These modes provide a variety of • The primary clock, as defined by the options for selective power conservation in applications FOSC3:FOSC0 Configuration bits where resources may be limited (i.e., battery-powered • The secondary clock (the Timer1 oscillator) devices). • The internal oscillator block (for RC modes) There are three categories of power-managed modes: 3.1.2 ENTERING POWER-MANAGED • Run modes MODES • Idle modes Switching from one power-managed mode to another • Sleep mode begins by loading the OSCCON register. The These categories define which portions of the device SCS1:SCS0 bits select the clock source and determine are clocked and sometimes, what speed. The Run and which Run or Idle mode is to be used. Changing these Idle modes may use any of the three available clock bits causes an immediate switch to the new clock sources (primary, secondary or internal oscillator source, assuming that it is running. The switch may block); the Sleep mode does not use a clock source. also be subject to clock transition delays. These are The power-managed modes include several discussed in Section3.1.3 “Clock Transitions and power-saving features offered on previous PIC® Status Indicators” and subsequent sections. devices. One is the clock switching feature, offered in Entry to the power-managed Idle or Sleep modes is other PIC18 devices, allowing the controller to use the triggered by the execution of a SLEEP instruction. The Timer1 oscillator in place of the primary oscillator. Also actual mode that results depends on the status of the included is the Sleep mode, offered by all PIC devices, IDLEN bit. where all device clocks are stopped. Depending on the current mode and the mode being switched to, a change to a power-managed mode does 3.1 Selecting Power-Managed Modes not always require setting all of these bits. Many Selecting a power-managed mode requires two transitions may be done by changing the oscillator decisions: if the CPU is to be clocked or not and the select bits, or changing the IDLEN bit, prior to issuing a selection of a clock source. The IDLEN bit SLEEP instruction. If the IDLEN bit is already (OSCCON<7>) controls CPU clocking, while the configured correctly, it may only be necessary to SCS1:SCS0 bits (OSCCON<1:0>) select the clock perform a SLEEP instruction to switch to the desired source. The individual modes, bit settings, clock sources mode. and affected modules are summarized in Table3-1. TABLE 3-1: POWER-MANAGED MODES OSCCON<7,1:0> Module Clocking Mode Available Clock and Oscillator Source IDLEN(1) SCS1:SCS0 CPU Peripherals Sleep 0 N/A Off Off None – all clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary – all oscillator modes. This is the normal full-power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 oscillator RC_RUN N/A 1x Clocked Clocked Internal oscillator block(2) PRI_IDLE 1 00 Off Clocked Primary – all oscillator modes SEC_IDLE 1 01 Off Clocked Secondary – Timer1 oscillator RC_IDLE 1 1x Off Clocked Internal oscillator block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2009 Microchip Technology Inc. DS39632E-page 35

PIC18F2455/2550/4455/4550 3.1.3 CLOCK TRANSITIONS AND generating a stable 8MHz output. Entering another STATUS INDICATORS power-managed RC mode at the same frequency would clear the OSTS bit. The length of the transition between clock sources is the sum of two cycles of the old clock source and three Note1: Caution should be used when modifying a to four cycles of the new clock source. This formula single IRCF bit. If VDD is less than 3V, it is assumes that the new clock source is stable. possible to select a higher clock speed Three bits indicate the current clock source and its than is supported by the low VDD. Improper device operation may result if status. They are: the VDD/FOSC specifications are violated. • OSTS (OSCCON<3>) 2: Executing a SLEEP instruction does not • IOFS (OSCCON<2>) necessarily place the device into Sleep • T1RUN (T1CON<6>) mode. It acts as the trigger to place the In general, only one of these bits will be set while in a controller into either the Sleep mode, or given power-managed mode. When the OSTS bit is one of the Idle modes, depending on the set, the primary clock is providing the device clock. setting of the IDLEN bit. When the IOFS bit is set, the INTOSC output is provid- 3.1.4 MULTIPLE SLEEP COMMANDS ing a stable, 8MHz clock source to a divider that actually drives the device clock. When the T1RUN bit is The power-managed mode that is invoked with the set, the Timer1 oscillator is providing the clock. If none SLEEP instruction is determined by the setting of the of these bits are set, then either the INTRC clock IDLEN bit at the time the instruction is executed. If source is clocking the device, or the INTOSC source is another SLEEP instruction is executed, the device will not yet stable. enter the power-managed mode specified by IDLEN at If the internal oscillator block is configured as the that time. If IDLEN has changed, the device will enter primary clock source by the FOSC3:FOSC0 Con- the new power-managed mode specified by the new figuration bits, then both the OSTS and IOFS bits may setting. be set when in PRI_RUN or PRI_IDLE modes. This Upon resuming normal operation after waking from indicates that the primary clock (INTOSC output) is Sleep or Idle, the internal state machines require at least one TCY delay before another SLEEP instruction can be executed. If two back to back SLEEP instruc- tions will be executed, the process shown in Example3-1 should be used. EXAMPLE 3-1: EXECUTING BACK TO BACK SLEEP INSTRUCTIONS SLEEP NOP ;Wait at least 1 Tcy before executing another sleep instruction SLEEP 3.2 Run Modes 3.2.2 SEC_RUN MODE In the Run modes, clocks to both the core and The SEC_RUN mode is the compatible mode to the peripherals are active. The difference between these “clock switching” feature offered in other PIC18 modes is the clock source. devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the 3.2.1 PRI_RUN MODE option of lower power consumption while still using a high-accuracy clock source. The PRI_RUN mode is the normal, full-power execu- tion mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section25.3 “Two-Speed Start-up” for details). In this mode, the OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section2.4.1 “Oscillator Control Register”). DS39632E-page 36 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 SEC_RUN mode is entered by setting the SCS1:SCS0 On transitions from SEC_RUN mode to PRI_RUN, the bits to ‘01’. The device clock source is switched to the peripherals and CPU continue to be clocked from the Timer1 oscillator (see Figure3-1), the primary Timer1 oscillator while the primary clock is started. oscillator is shut down, the T1RUN bit (T1CON<6>) is When the primary clock becomes ready, a clock switch set and the OSTS bit is cleared. back to the primary clock occurs (see Figure3-2). When the clock switch is complete, the T1RUN bit is Note: The Timer1 oscillator should already be cleared, the OSTS bit is set and the primary clock is running prior to entering SEC_RUN mode. providing the clock. The IDLEN and SCS bits are not If the T1OSCEN bit is not set when the affected by the wake-up; the Timer1 oscillator SCS1:SCS0 bits are set to ‘01’, entry to continues to run. SEC_RUN mode will not occur. If the Timer1 oscillator is enabled but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI 1 2 3 n-1 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock(2) Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS1:SCS0 bits Changed OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. © 2009 Microchip Technology Inc. DS39632E-page 37

PIC18F2455/2550/4455/4550 3.2.3 RC_RUN MODE If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will In RC_RUN mode, the CPU and peripherals are remain clear; there will be no indication of the current clocked from the internal oscillator block using the clock source. The INTRC source is providing the INTOSC multiplexer; the primary clock is shut down. device clocks. When using the INTRC source, this mode provides the best power conservation of all the Run modes while still If the IRCF bits are changed from all clear (thus, executing code. It works well for user applications enabling the INTOSC output), or if INTSRC is set, the which are not highly timing sensitive or do not require IOFS bit becomes set after the INTOSC output high-speed clocks at all times. becomes stable. Clocks to the device continue while the INTOSC source stabilizes after an interval of If the primary clock source is the internal oscillator TIOBST. block (either INTRC or INTOSC), there are no distin- guishable differences between the PRI_RUN and If the IRCF bits were previously at a non-zero value or RC_RUN modes during execution. However, a clock if INTSRC was set before setting SCS1 and the switch delay will occur during entry to and exit from INTOSC source was already stable, the IOFS bit will RC_RUN mode. Therefore, if the primary clock source remain set. is the internal oscillator block, the use of RC_RUN On transitions from RC_RUN mode to PRI_RUN mode, mode is not recommended. the device continues to be clocked from the INTOSC This mode is entered by setting SCS1 to ‘1’. Although multiplexer while the primary clock is started. When the it is ignored, it is recommended that SCS0 also be primary clock becomes ready, a clock switch to the cleared; this is to maintain software compatibility with primary clock occurs (see Figure3-4). When the clock future devices. When the clock source is switched to switch is complete, the IOFS bit is cleared, the OSTS the INTOSC multiplexer (see Figure3-3), the primary bit is set and the primary clock is providing the device oscillator is shut down and the OSTS bit is cleared. The clock. The IDLEN and SCS bits are not affected by the IRCF bits may be modified at any time to immediately switch. The INTRC source will continue to run if either change the clock speed. the WDT or the Fail-Safe Clock Monitor is enabled. Note: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. DS39632E-page 38 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC 1 2 3 n-1 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock(2) Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS1:SCS0 bits Changed OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. © 2009 Microchip Technology Inc. DS39632E-page 39

PIC18F2455/2550/4455/4550 3.3 Sleep Mode 3.4 Idle Modes The power-managed Sleep mode in the The Idle modes allow the controller’s CPU to be PIC18F2455/2550/4455/4550 devices is identical to selectively shut down while the peripherals continue to the legacy Sleep mode offered in all other PIC devices. operate. Selecting a particular Idle mode allows users It is entered by clearing the IDLEN bit (the default state to further manage power consumption. on device Reset) and executing the SLEEP instruction. If the IDLEN bit is set to ‘1’ when a SLEEP instruction is This shuts down the selected oscillator (Figure3-5). All executed, the peripherals will be clocked from the clock clock source status bits are cleared. source selected using the SCS1:SCS0 bits; however, the Entering the Sleep mode from any other mode does not CPU will not be clocked. The clock source status bits are require a clock switch. This is because no clocks are not affected. Setting IDLEN and executing a SLEEP needed once the controller has entered Sleep. If the instruction provides a quick method of switching from a WDT is selected, the INTRC source will continue to given Run mode to its corresponding Idle mode. operate. If the Timer1 oscillator is enabled, it will also If the WDT is selected, the INTRC source will continue continue to run. to operate. If the Timer1 oscillator is enabled, it will also When a wake event occurs in Sleep mode (by interrupt, continue to run. Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only until the clock source selected by the SCS1:SCS0 bits exits from any of the Idle modes are by interrupt, WDT becomes ready (see Figure3-6), or it will be clocked time-out or a Reset. When a wake event occurs, CPU from the internal oscillator block if either the Two-Speed execution is delayed by an interval of TCSD Start-up or the Fail-Safe Clock Monitor are enabled (parameter38, Table28-12) while it becomes ready to (see Section25.0 “Special Features of the CPU”). In execute code. When the CPU begins executing code, either case, the OSTS bit is set when the primary clock it resumes with the same clock source for the current is providing the device clocks. The IDLEN and SCS bits Idle mode. For example, when waking from RC_IDLE are not affected by the wake-up. mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits. FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS39632E-page 40 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 3.4.1 PRI_IDLE MODE 3.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes in that it does not disable the primary device peripherals continue to be clocked from the Timer1 clock. For timing sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by set- the fastest resumption of device operation, with its ting the IDLEN bit and executing a SLEEP instruction. If more accurate primary clock source, since the clock the device is in another Run mode, set IDLEN first, then source does not have to “warm up” or transition from set SCS1:SCS0 to ‘01’ and execute SLEEP. When the another oscillator. clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared PRI_IDLE mode is entered from PRI_RUN mode by and the T1RUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then clear the SCS bits and execute SLEEP. be clocked from the Timer1 oscillator. After an interval Although the CPU is disabled, the peripherals continue of TCSD following the wake event, the CPU begins exe- to be clocked from the primary clock source specified cuting code being clocked by the Timer1 oscillator. The by the FOSC3:FOSC0 Configuration bits. The OSTS IDLEN and SCS bits are not affected by the wake-up; bit remains set (see Figure3-7). the Timer1 oscillator continues to run (see Figure3-8). When a wake event occurs, the CPU is clocked from the Note: The Timer1 oscillator should already be primary clock source. A delay of interval TCSD is running prior to entering SEC_IDLE mode. required between the wake event and when code If the T1OSCEN bit is not set when the execution starts. This is required to allow the CPU to SLEEP instruction is executed, the SLEEP become ready to execute instructions. After the instruction will be ignored and entry to wake-up, the OSTS bit remains set. The IDLEN and SEC_IDLE mode will not occur. If the SCS bits are not affected by the wake-up (see Timer1 oscillator is enabled but not yet Figure3-8). running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event © 2009 Microchip Technology Inc. DS39632E-page 41

PIC18F2455/2550/4455/4550 3.4.3 RC_IDLE MODE On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the In RC_IDLE mode, the CPU is disabled but the periph- GIE/GIEH bit (INTCON<7>) is set. Otherwise, code erals continue to be clocked from the internal oscillator execution continues or resumes without branching block using the INTOSC multiplexer. This mode allows (see Section9.0 “Interrupts”). for controllable power conservation during Idle periods. A fixed delay of interval TCSD following the wake event From RC_RUN, this mode is entered by setting the is required when leaving Sleep and Idle modes. This IDLEN bit and executing a SLEEP instruction. If the delay is required for the CPU to prepare for execution. device is in another Run mode, first set IDLEN, then set Instruction execution resumes on the first clock cycle the SCS1 bit and execute SLEEP. Although its value is following this delay. ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future 3.5.2 EXIT BY WDT TIME-OUT devices. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF A WDT time-out will cause different actions depending bits before executing the SLEEP instruction. When the on which power-managed mode the device is in when clock source is switched to the INTOSC multiplexer, the the time-out occurs. primary oscillator is shut down and the OSTS bit is If the device is not executing code (all Idle modes and cleared. Sleep mode), the time-out will result in an exit from the If the IRCF bits are set to any non-zero value, or the power-managed mode (see Section3.2 “Run INTSRC bit is set, the INTOSC output is enabled. The Modes” and Section3.3 “Sleep Mode”). If the device IOFS bit becomes set after the INTOSC output is executing code (all Run modes), the time-out will becomes stable, after an interval of TIOBST result in a WDT Reset (see Section25.2 “Watchdog (parameter39, Table28-12). Clocks to the peripherals Timer (WDT)”). continue while the INTOSC source stabilizes. If the The WDT timer and postscaler are cleared by execut- IRCF bits were previously at a non-zero value, or ing a SLEEP or CLRWDT instruction, the loss of a INTSRC was set before the SLEEP instruction was currently selected clock source (if the Fail-Safe Clock executed and the INTOSC source was already stable, Monitor is enabled) and modifying the IRCF bits in the the IOFS bit will remain set. If the IRCF bits and OSCCON register if the internal oscillator block is the INTSRC are all clear, the INTOSC output will not be device clock source. enabled, the IOFS bit will remain clear and there will be no indication of the current clock source. 3.5.3 EXIT BY RESET When a wake event occurs, the peripherals continue to Normally, the device is held in Reset by the Oscillator be clocked from the INTOSC multiplexer. After a delay Start-up Timer (OST) until the primary clock becomes of TCSD following the wake event, the CPU begins ready. At that time, the OSTS bit is set and the device executing code being clocked by the INTOSC multi- begins executing code. If the internal oscillator block is plexer. The IDLEN and SCS bits are not affected by the the new clock source, the IOFS bit is set instead. wake-up. The INTRC source will continue to run if The exit delay time from Reset to the start of code either the WDT or the Fail-Safe Clock Monitor is execution depends on both the clock sources before enabled. and after the wake-up and the type of oscillator if the new clock source is the primary clock. Exit delays are 3.5 Exiting Idle and Sleep Modes summarized in Table3-2. An exit from Sleep mode or any of the Idle modes is Code execution can begin before the primary clock triggered by an interrupt, a Reset or a WDT time-out. becomes ready. If either the Two-Speed Start-up (see This section discusses the triggers that cause exits Section25.3 “Two-Speed Start-up”) or Fail-Safe from power-managed modes. The clocking subsystem Clock Monitor (see Section25.4 “Fail-Safe Clock actions are discussed in each of the power-managed Monitor”) is enabled, the device may begin execution modes (see Section3.2 “Run Modes”, Section3.3 as soon as the Reset source has cleared. Execution is “Sleep Mode” and Section3.4 “Idle Modes”). clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the 3.5.1 EXIT BY INTERRUPT internal oscillator block until either the primary clock Any of the available interrupt sources can cause the becomes ready or a power-managed mode is entered device to exit from an Idle mode or Sleep mode to a before the primary clock becomes ready; the primary Run mode. To enable this functionality, an interrupt clock is then shut down. source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. DS39632E-page 42 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 3.5.4 EXIT WITHOUT AN OSCILLATOR In these instances, the primary clock source either START-UP DELAY does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not Certain exits from power-managed modes do not require an oscillator start-up delay (EC and any internal invoke the OST at all. There are two cases: oscillator modes). However, a fixed delay of interval • PRI_IDLE mode, where the primary clock source TCSD following the wake event is still required when is not stopped; and leaving Sleep and Idle modes to allow the CPU to • the primary clock source is not any of the XT or prepare for execution. Instruction execution resumes HS modes. on the first clock cycle following this delay. TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Microcontroller Clock Source Clock Ready Status Exit Delay Bit (OSCCON) Before Wake-up After Wake-up XT, HS Primary Device Clock XTPLL, HSPLL OSTS None (PRI_IDLE mode) EC INTOSC(3) IOFS XT, HS TOST(4) T1OSC or INTRC(1) XTPLL, HSPLL TOST + trc(4) OSTS EC TCSD(2) INTOSC(3) TIOBST(5) IOFS XT, HS TOST(4) INTOSC(3) XTPLL, HSPLL TOST + trc(4) OSTS EC TCSD(2) INTOSC(3) None IOFS XT, HS TOST(4) None XTPLL, HSPLL TOST + trc(4) OSTS (Sleep mode) EC TCSD(2) INTOSC(3) TIOBST(5) IOFS Note 1: In this instance, refers specifically to the 31kHz INTRC clock source. 2: TCSD (parameter 38, Table28-12) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section3.4 “Idle Modes”). 3: Includes both the INTOSC 8MHz source and postscaler derived frequencies. 4: TOST is the Oscillator Start-up Timer period (parameter 32, Table28-12). trc is the PLL lock time-out (parameter F12, Table28-9); it is also designated as TPLL. 5: Execution continues during TIOBST (parameter 39, Table28-12), the INTOSC stabilization period. © 2009 Microchip Technology Inc. DS39632E-page 43

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 44 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 4.0 RESET A simplified block diagram of the on-chip Reset circuit is shown in Figure4-1. The PIC18F2455/2550/4455/4550 devices differentiate between various kinds of Reset: 4.1 RCON Register a) Power-on Reset (POR) Device Reset events are tracked through the RCON b) MCLR Reset during normal operation register (Register4-1). The lower five bits of the regis- c) MCLR Reset during power-managed modes ter indicate that a specific Reset event has occurred. In d) Watchdog Timer (WDT) Reset (during most cases, these bits can only be cleared by the event execution) and must be set by the application after the event. The e) Programmable Brown-out Reset (BOR) state of these flag bits, taken together, can be read to f) RESET Instruction indicate the type of Reset that just occurred. This is described in more detail in Section4.6 “Reset State g) Stack Full Reset of Registers”. h) Stack Underflow Reset The RCON register also has control bits for setting This section discusses Resets generated by MCLR, interrupt priority (IPEN) and software control of the POR and BOR and covers the operation of the various BOR (SBOREN). Interrupt priority is discussed in start-up timers. Stack Reset events are covered in Section9.0 “Interrupts”. BOR is covered in Section5.1.2.4 “Stack Full and Underflow Resets”. Section4.4 “Brown-out Reset (BOR)”. WDT Resets are covered in Section25.2 “Watchdog Timer (WDT)”. FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset BOREN S OST/PWRT OST 1024 Cycles Chip_Reset 10-Bit Ripple Counter R Q OSC1 32 μs PWRT 65.5 ms INTRC(1) 11-Bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is the low-frequency INTRC source from the internal oscillator block. 2: See Table4-2 for time-out situations. © 2009 Microchip Technology Inc. DS39632E-page 45

PIC18F2455/2550/4455/4550 REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN1:BOREN0 = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section4.6 “Reset State of Registers” for additional information. Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after POR). DS39632E-page 46 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 4.2 Master Clear Reset (MCLR) FIGURE 4-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering an SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small VDD VDD pulses. The MCLR pin is not driven low by any internal Resets, D R including the WDT. R1 MCLR In PIC18F2455/2550/4455/4550 devices, the MCLR input can be disabled with the MCLRE Configuration C PIC18FXXXX bit. When MCLR is disabled, the pin becomes a digital input. See Section10.5 “PORTE, TRISE and LATE Registers” for more information. Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. 4.3 Power-on Reset (POR) The diode D helps discharge the capacitor A Power-on Reset pulse is generated on-chip quickly when VDD powers down. whenever VDD rises above a certain threshold. This 2: R < 40kΩ is recommended to make sure that the voltage drop across R does not violate allows the device to start in the initialized state when the device’s electrical specification. VDD is adequate for operation. 3: R1 ≥ 1 kΩ will limit any current flowing into To take advantage of the POR circuitry, tie the MCLR pin MCLR from external capacitor C, in the event through a resistor (1kΩ to 10kΩ) to VDD. This will of MCLR/VPP pin breakdown, due to Electro- eliminate external RC components usually needed to static Discharge (ESD) or Electrical create a Power-on Reset delay. A minimum rise rate for Overstress (EOS). VDD is specified (parameter D004, Section28.1 “DC Characteristics”). For a slow rise time, see Figure4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2009 Microchip Technology Inc. DS39632E-page 47

PIC18F2455/2550/4455/4550 4.4 Brown-out Reset (BOR) Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its PIC18F2455/2550/4455/4550 devices implement a environment without having to reprogram the device to BOR circuit that provides the user with a number of change BOR configuration. It also allows the user to configuration and power-saving options. The BOR tailor device power consumption in software by elimi- is controlled by the BORV1:BORV0 and nating the incremental current that the BOR consumes. BOREN1:BOREN0 Configuration bits. There are a total While the BOR current is typically very small, it may of four BOR configurations which are summarized in have some impact in low-power applications. Table4-1. Note: Even when BOR is under software control, The BOR threshold is set by the BORV1:BORV0 bits. If the BOR Reset voltage level is still set by BOR is enabled (any values of BOREN1:BOREN0 the BORV1:BORV0 Configuration bits. It except ‘00’), any drop of VDD below VBOR (parameter cannot be changed in software. D005, Section 28.1 “DC Characteristics”) for greater than TBOR (parameter 35, Table28-12) will 4.4.2 DETECTING BOR reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will When BOR is enabled, the BOR bit always resets to ‘0’ remain in Brown-out Reset until VDD rises above VBOR. on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading If the Power-up Timer is enabled, it will be invoked after the state of BOR alone. A more reliable method is to VDD rises above VBOR; it then will keep the chip in simultaneously check the state of both POR and BOR. Reset for an additional time delay, TPWRT This assumes that the POR bit is reset to ‘1’ in software (parameter33, Table28-12). If VDD drops below VBOR immediately after any POR event. IF BOR is ‘0’ while while the Power-up Timer is running, the chip will go POR is ‘1’, it can be reliably assumed that a BOR event back into a Brown-out Reset and the Power-up Timer has occurred. will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. 4.4.3 DISABLING BOR IN SLEEP MODE BOR and the Power-on Timer (PWRT) are When BOREN1:BOREN0 = 10, the BOR remains independently configured. Enabling BOR Reset does under hardware control and operates as previously not automatically enable the PWRT. described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the 4.4.1 SOFTWARE ENABLED BOR device returns to any other operating mode, BOR is When BOREN1:BOREN0 = 01, the BOR can be automatically re-enabled. enabled or disabled by the user in software. This is This mode allows for applications to recover from done with the control bit, SBOREN (RCON<6>). brown-out situations, while actively executing code, Setting SBOREN enables the BOR to function as when the device requires BOR protection the most. At previously described. Clearing SBOREN disables the the same time, it saves additional power in Sleep mode BOR entirely. The SBOREN bit operates only in this by eliminating the small incremental BOR current. mode; otherwise, it is read as ‘0’. TABLE 4-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN BOR Operation BOREN1 BOREN0 (RCON<6>) 0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR enabled in software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. DS39632E-page 48 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 4.5 Device Reset Timers 4.5.3 PLL LOCK TIME-OUT PIC18F2455/2550/4455/4550 devices incorporate With the PLL enabled in its PLL mode, the time-out three separate on-chip timers that help regulate the sequence following a Power-on Reset is slightly differ- Power-on Reset process. Their main function is to ent from other oscillator modes. A separate timer is ensure that the device clock is stable before code is used to provide a fixed time-out that is sufficient for the executed. These timers are: PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the • Power-up Timer (PWRT) oscillator start-up time-out. • Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: 4.5.1 POWER-UP TIMER (PWRT) 1. After the POR condition has cleared, PWRT The Power-up Timer (PWRT) of the PIC18F2455/2550/ time-out is invoked (if enabled). 4455/4550 devices is an 11-bit counter which uses the 2. Then, the OST is activated. INTRC source as the clock input. This yields an approximate time interval of 2048x32μs=65.6ms. The total time-out will vary based on oscillator configu- While the PWRT is counting, the device is held in ration and the status of the PWRT. Figure4-3, Reset. Figure4-4, Figure4-5, Figure4-6 and Figure4-7 all depict time-out sequences on power-up, with the The power-up time delay depends on the INTRC clock Power-up Timer enabled and the device operating in and will vary from chip to chip due to temperature and HS Oscillator mode. Figures4-3 through4-6 also apply process variation. See DC parameter 33 (Table28-12) to devices operating in XT mode. For devices in RC for details. mode and with the PWRT disabled, on the other hand, The PWRT is enabled by clearing the PWRTEN there will be no time-out at all. Configuration bit. Since the time-outs occur from the POR pulse, if MCLR 4.5.2 OSCILLATOR START-UP is kept low long enough, all time-outs will expire. Bring- ing MCLR high will begin execution immediately TIMER (OST) (Figure4-5). This is useful for testing purposes or to The Oscillator Start-up Timer (OST) provides a synchronize more than one PIC18FXXXX device 1024oscillator cycle (from OSC1 input) delay after the operating in parallel. PWRT delay is over (parameter 33, Table28-12). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, HS and HSPLL modes and only on Power-on Reset or on exit from most power-managed modes. TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Exit from Configuration Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HS, XT 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC HSPLL, XTPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) EC, ECIO 66 ms(1) — — ECPLL, ECPIO 66 ms(1) + 2 ms(2) 2 ms(2) 2 ms(2) INTIO, INTCKO 66 ms(1) — — INTHS, INTXT 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. © 2009 Microchip Technology Inc. DS39632E-page 49

PIC18F2455/2550/4455/4550 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39632E-page 50 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the Power-up Timer. © 2009 Microchip Technology Inc. DS39632E-page 51

PIC18F2455/2550/4455/4550 4.6 Reset State of Registers Table4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Most registers are unaffected by a Reset. Their status Power-on and Brown-out Resets, Master Clear and is unknown on POR and unchanged by all other WDT Resets and WDT wake-ups. Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations as indicated in Table4-3. These bits are used in software to determine the nature of the Reset. TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 0 0 0 0 RESET instruction 0000h 0 u u u u u u Brown-out Reset 0000h 1 1 1 u 0 u u MCLR Reset during power-managed Run 0000h u 1 u u u u u modes MCLR Reset during power-managed Idle 0000h u 1 0 u u u u modes and Sleep mode WDT time-out during full power or 0000h u 0 u u u u u power-managed Run modes MCLR Reset during full-power execution 0000h u u u u u u u Stack Full Reset (STVREN = 1) 0000h u u u u u 1 u Stack Underflow Reset (STVREN = 1) 0000h u u u u u u 1 Stack Underflow Error (not an actual Reset, 0000h u u u u u u 1 STVREN = 0) WDT time-out during power-managed Idle or PC + 2 u 0 0 u u u u Sleep modes Interrupt exit from power-managed modes PC + 2(1) u u 0 u u u u Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled (BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’. DS39632E-page 52 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets TOSU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---0 uuuu(1) TOSH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(1) TOSL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(1) STKPTR 2455 2550 4455 4550 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu PCLATH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu PCL 2455 2550 4455 4550 0000 0000 0000 0000 PC + 2(3) TBLPTRU 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu TBLPTRH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TABLAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu PRODH 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 2455 2550 4455 4550 0000 000x 0000 000u uuuu uuuu(2) INTCON2 2455 2550 4455 4550 1111 -1-1 1111 -1-1 uuuu -u-u(2) INTCON3 2455 2550 4455 4550 11-0 0-00 11-0 0-00 uu-u u-uu(2) INDF0 2455 2550 4455 4550 N/A N/A N/A POSTINC0 2455 2550 4455 4550 N/A N/A N/A POSTDEC0 2455 2550 4455 4550 N/A N/A N/A PREINC0 2455 2550 4455 4550 N/A N/A N/A PLUSW0 2455 2550 4455 4550 N/A N/A N/A FSR0H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu FSR0L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu WREG 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 2455 2550 4455 4550 N/A N/A N/A POSTINC1 2455 2550 4455 4550 N/A N/A N/A POSTDEC1 2455 2550 4455 4550 N/A N/A N/A PREINC1 2455 2550 4455 4550 N/A N/A N/A PLUSW1 2455 2550 4455 4550 N/A N/A N/A FSR1H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu FSR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 4: See Table4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. DS39632E-page 53

PIC18F2455/2550/4455/4550 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets INDF2 2455 2550 4455 4550 N/A N/A N/A POSTINC2 2455 2550 4455 4550 N/A N/A N/A POSTDEC2 2455 2550 4455 4550 N/A N/A N/A PREINC2 2455 2550 4455 4550 N/A N/A N/A PLUSW2 2455 2550 4455 4550 N/A N/A N/A FSR2H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu FSR2L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 2455 2550 4455 4550 ---x xxxx ---u uuuu ---u uuuu TMR0H 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TMR0L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu OSCCON 2455 2550 4455 4550 0100 q000 0100 00q0 uuuu uuqu HLVDCON 2455 2550 4455 4550 0-00 0101 0-00 0101 u-uu uuuu WDTCON 2455 2550 4455 4550 ---- ---0 ---- ---0 ---- ---u RCON(4) 2455 2550 4455 4550 0q-1 11q0 0q-q qquu uq-u qquu TMR1H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 2455 2550 4455 4550 0000 0000 u0uu uuuu uuuu uuuu TMR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu PR2 2455 2550 4455 4550 1111 1111 1111 1111 1111 1111 T2CON 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu SSPBUF 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu SSPSTAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu SSPCON1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu SSPCON2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu ADRESH 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu ADCON1 2455 2550 4455 4550 --00 0qqq --00 0qqq --uu uuuu ADCON2 2455 2550 4455 4550 0-00 0000 0-00 0000 u-uu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 4: See Table4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. DS39632E-page 54 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets CCPR1H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu CCPR2H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu BAUDCON 2455 2550 4455 4550 0100 0-00 0100 0-00 uuuu u-uu ECCP1DEL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu ECCP1AS 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu CVRCON 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu CMCON 2455 2550 4455 4550 0000 0111 0000 0111 uuuu uuuu TMR3H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 2455 2550 4455 4550 0000 0000 uuuu uuuu uuuu uuuu SPBRGH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu SPBRG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu RCREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TXREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TXSTA 2455 2550 4455 4550 0000 0010 0000 0010 uuuu uuuu RCSTA 2455 2550 4455 4550 0000 000x 0000 000x uuuu uuuu EEADR 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu EEDATA 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu EECON2 2455 2550 4455 4550 0000 0000 0000 0000 0000 0000 EECON1 2455 2550 4455 4550 xx-0 x000 uu-0 u000 uu-0 u000 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 4: See Table4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. DS39632E-page 55

PIC18F2455/2550/4455/4550 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets IPR2 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu PIR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(2) PIE2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu IPR1 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu 2455 2550 4455 4550 -111 1111 -111 1111 -uuu uuuu PIR1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(2) 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu PIE1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu OSCTUNE 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu TRISE 2455 2550 4455 4550 ---- -111 ---- -111 ---- -uuu TRISD 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu TRISC 2455 2550 4455 4550 11-- -111 11-- -111 uu-- -uuu TRISB 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu TRISA(5) 2455 2550 4455 4550 -111 1111(5) -111 1111(5) -uuu uuuu(5) LATE 2455 2550 4455 4550 ---- -xxx ---- -uuu ---- -uuu LATD 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu LATC 2455 2550 4455 4550 xx-- -xxx uu-- -uuu uu-- -uuu LATB 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 2455 2550 4455 4550 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5) PORTE 2455 2550 4455 4550 0--- x000 0--- x000 u--- uuuu PORTD 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 2455 2550 4455 4550 xxxx -xxx uuuu -uuu uuuu -uuu PORTB 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5) 2455 2550 4455 4550 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 4: See Table4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. DS39632E-page 56 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets UEP15 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP14 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP13 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP12 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP11 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP10 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP9 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP8 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP7 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP6 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP5 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP4 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP3 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP2 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP1 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UEP0 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu UCFG 2455 2550 4455 4550 00-0 0000 00-0 0000 uu-u uuuu UADDR 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu UCON 2455 2550 4455 4550 -0x0 000- -0x0 000- -uuu uuu- USTAT 2455 2550 4455 4550 -xxx xxx- -xxx xxx- -uuu uuu- UEIE 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu UEIR 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu UIE 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu UIR 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu UFRMH 2455 2550 4455 4550 ---- -xxx ---- -xxx ---- -uuu UFRML 2455 2550 4455 4550 xxxx xxxx xxxx xxxx uuuu uuuu SPPCON 2455 2550 4455 4550 ---- --00 ---- --00 ---- --uu SPPEPS 2455 2550 4455 4550 00-0 0000 00-0 0000 uu-u uuuu SPPCFG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu SPPDATA 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 4: See Table4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. DS39632E-page 57

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 58 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 5.0 MEMORY ORGANIZATION 5.1 Program Memory Organization There are three types of memory in PIC18 enhanced PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address will return all ‘0’s (a • Data EEPROM NOP instruction). As Harvard architecture devices, the data and program The PIC18F2455 and PIC18F4455 each have 24Kbytes memories use separate busses; this allows for con- of Flash memory and can store up to 12,288 single-word current access of the two memory spaces. The data instructions. The PIC18F2550 and PIC18F4550 each EEPROM, for practical purposes, can be regarded as have 32Kbytes of Flash memory and can store up to a peripheral device, since it is addressed and accessed 16,384 single-word instructions. through a set of control registers. PIC18 devices have two interrupt vectors. The Reset Additional detailed information on the operation of the vector address is at 0000h and the interrupt vector Flash program memory is provided in Section6.0 addresses are at 0008h and 0018h. “Flash Program Memory”. Data EEPROM is The program memory maps for PIC18FX455 and discussed separately in Section7.0 “Data EEPROM PIC18FX550 devices are shown in Figure5-1. Memory”. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK 24 Kbyte Devices 32 Kbyte Device PC<20:0> PC<20:0> CALL, RCALL, RETURN, 21 CALL, RCALL, RETURN, 21 RETFIE, RETLW, CALLW, RETFIE, RETLW, CALLW, ADDULNK, SUBULNK ADDULNK, SUBULNK Stack Level 1 Stack Level 1 ••• ••• Stack Level 31 Stack Level 31 Reset Vector 0000h Reset Vector 0000h High-Priority Interrupt Vector 0008h High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector 0018h Low-Priority Interrupt Vector 0018h On-Chip Program Memory On-Chip Program Memory 5FFFh 6000h ce 7FFFh ce a a Sp 8000h Sp y y or or m m e e M M er er Us Us Read ‘0’ Read ‘0’ 1FFFFFh 1FFFFFh 200000h 200000h © 2009 Microchip Technology Inc. DS39632E-page 59

PIC18F2455/2550/4455/4550 5.1.1 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and is contained in three separate 8-bit registers. The the stack is readable and writable through the low byte, known as the PCL register, is both readable Top-of-Stack Special Function Registers. Data can also and writable. The high byte, or PCH register, contains be pushed to, or popped from the stack, using these the PC<15:8> bits; it is not directly readable or writable. registers. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack. register contains the PC<20:16> bits; it is also not The Stack Pointer is first incremented and the location directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the register are performed through the PCLATU register. contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred a pop from the stack. The contents of the location to the program counter by any operation that writes pointed to by the STKPTR are transferred to the PC PCL. Similarly, the upper two bytes of the program and then the Stack Pointer is decremented. counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all offsets to the PC (see Section5.1.4.1 “Computed Resets. There is no RAM associated with the location GOTO”). corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is The PC addresses bytes in the program memory. To full, has overflowed or has underflowed. prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to 5.1.2.1 Top-of-Stack Access a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. Only the top of the return address stack (TOS) is readable and writable. A set of three registers, The CALL, RCALL and GOTO program branch TOSU:TOSH:TOSL, hold the contents of the stack loca- instructions write to the program counter directly. For tion pointed to by the STKPTR register (Figure5-2). This these instructions, the contents of PCLATH and allows users to implement a software stack if necessary. PCLATU are not transferred to the program counter. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL 5.1.2 RETURN ADDRESS STACK registers. These values can be placed on a user-defined The return address stack allows any combination of up software stack. At return time, the software can return to 31 program calls and interrupts to occur. The PC is these values to TOSU:TOSH:TOSL and do a return. pushed onto the stack when a CALL or RCALL instruc- The user must disable the global interrupt enable bits tion is executed or an interrupt is Acknowledged. The while accessing the stack to prevent inadvertent stack PC value is pulled off the stack on a RETURN, RETLW or corruption. a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack<20:0> 11111 11110 Top-of-Stack Registers Stack Pointer 11101 TOSU TOSH TOSL STKPTR<4:0> 00h 1Ah 34h 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 DS39632E-page 60 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 5.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The STKPTR register (Register5-1) contains the Stack to the PC and sets the STKUNF bit, while the Stack Pointer value, the STKFUL (Stack Full) status bit and Pointer remains at zero. The STKUNF bit will remain the STKUNF (Stack Underflow) status bit. The value of set until cleared by software or until a POR occurs. the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System (RTOS) for return stack maintenance. not the same as a Reset, as the contents of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a 5.1.2.3 PUSH and POP Instructions POR. Since the Top-of-Stack is readable and writable, the The action that takes place when the stack becomes ability to push values onto the stack and pull values off full depends on the state of the STVREN (Stack the stack, without disturbing normal program execu- Overflow Reset Enable) Configuration bit. (Refer to tion, is a desirable feature. The PIC18 instruction set Section25.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control. (default), the 31st push will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data onto the stack, set the STKFUL bit and reset the or a return address on the stack. device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto Pointer will be set to zero. the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st push and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by decre- Any additional pushes will not overwrite the 31st push menting the Stack Pointer. The previous value pushed and the STKPTR will remain at 31. onto the stack then becomes the TOS value. REGISTER 5-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. © 2009 Microchip Technology Inc. DS39632E-page 61

PIC18F2455/2550/4455/4550 5.1.2.4 Stack Full and Underflow Resets 5.1.4 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in There may be programming situations that require the Configuration Register 4L. When STVREN is set, a full creation of data structures, or look-up tables, in or underflow condition will set the appropriate STKFUL program memory. For PIC18 devices, look-up tables or STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit but not cause • Table Reads a device Reset. The STKFUL or STKUNF bits are cleared by user software or a Power-on Reset. 5.1.4.1 Computed GOTO 5.1.3 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in A Fast Register Stack is provided for the STATUS, Example5-2. WREG and BSR registers to provide a “fast return” option for interrupts. Each stack is only one level deep A look-up table can be formed with an ADDWF PCL and is neither readable nor writable. It is loaded with the instruction and a group of RETLW nn instructions. The current value of the corresponding register when the W register is loaded with an offset into the table before processor vectors for an interrupt. All interrupt sources executing a call to that table. The first instruction of the will push values into the stack registers. The values in called routine is the ADDWF PCL instruction. The next the registers are then loaded back into their associated instruction executed will be one of the RETLW nn registers if the RETFIE, FAST instruction is used to instructions that returns the value ‘nn’ to the calling return from the interrupt. function. If both low and high-priority interrupts are enabled, the The offset value (in WREG) specifies the number of stack registers cannot be used reliably to return from bytes that the program counter should advance and low-priority interrupts. If a high-priority interrupt occurs should be multiples of 2 (LSb = 0). while servicing a low-priority interrupt, the stack In this method, only one data byte may be stored in register values stored by the low-priority interrupt will each instruction location and room on the return be overwritten. In these cases, users must save the key address stack is required. registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 5-2: COMPUTED GOTO USING Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE interrupts are used, the Fast Register Stack can be MOVF OFFSET, W used to restore the STATUS, WREG and BSR registers CALL TABLE at the end of a subroutine call. To use the Fast Register ORG nn00h Stack for a subroutine call, a CALL label, FAST TABLE ADDWF PCL instruction must be executed to save the STATUS, RETLW nnh WREG and BSR registers to the Fast Register Stack. A RETLW nnh RETURN, FAST instruction is then executed to restore RETLW nnh these registers from the Fast Register Stack. . . Example5-1 shows a source code example that uses . the Fast Register Stack during a subroutine call and return. 5.1.4.2 Table Reads and Table Writes EXAMPLE 5-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per ;STACK program word by using table reads and writes. The • Table Pointer (TBLPTR) register specifies the byte • address and the Table Latch (TABLAT) register contains the data that is read from or written to program SUB1 • memory. Data is transferred to or from program • memory one byte at a time. RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK Table read and table write operations are discussed further in Section6.1 “Table Reads and Table Writes”. DS39632E-page 62 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 5.2 PIC18 Instruction Cycle 5.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 5.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are pipe- The microcontroller clock input, whether from an lined in such a manner that a fetch takes one instruction internal or external source, is internally divided by four cycle, while the decode and execute takes another to generate four non-overlapping quadrature clocks instruction cycle. However, due to the pipelining, each (Q1, Q2, Q3 and Q4). Internally, the program counter is instruction effectively executes in one cycle. If an incremented on every Q1; the instruction is fetched instruction causes the program counter to change (e.g., from the program memory and latched into the Instruc- GOTO), then two cycles are required to complete the tion Register (IR) during Q4. The instruction is decoded instruction (Example5-3). and executed during the following Q1 through Q4. The A fetch cycle begins with the Program Counter (PC) clocks and instruction execution flow are shown in incrementing in Q1. Figure5-3. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 5-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Q3 Phase Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. DS39632E-page 63

PIC18F2455/2550/4455/4550 5.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruc- tion. Since instructions are always stored on word The program memory is addressed in bytes. Instruc- boundaries, the data contained in the instruction is a tions are stored as two bytes or four bytes in program word address. The word address is written to PC<20:1>, memory. The Least Significant Byte of an instruction which accesses the desired byte address in program word is always stored in a program memory location memory. Instruction #2 in Figure5-4 shows how the with an even address (LSb = 0). To maintain alignment instruction, GOTO 0006h, is encoded in the program with instruction boundaries, the PC increments in steps memory. Program branch instructions, which encode a of 2 and the LSb will always read ‘0’ (see Section5.1.1 relative address offset, operate in the same manner. The “Program Counter”). offset value stored in a branch instruction represents the Figure5-4 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section26.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0 ↓ Program Memory 000000h Byte Locations → 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 5.2.4 TWO-WORD INSTRUCTIONS used by the instruction sequence. If the first word is skipped for some reason and the second word is The standard PIC18 instruction set has four two-word executed by itself, a NOP is executed instead. This is instructions: CALL, MOVFF, GOTO and LSFR. In all necessary for cases when the two-word instruction is cases, the second word of the instructions always has preceded by a conditional instruction that changes the ‘1111’ as its four Most Significant bits; the other 12 bits PC. Example5-4 shows how this works. are literal data, usually a data memory address. The use of ‘1111’ in the 4 MSbs of an instruction Note: See Section5.5 “Program Memory and specifies a special form of NOP. If the instruction is the Extended Instruction Set” for information on two-word instruction in the executed in proper sequence, immediately after the first word, the data in the second word is accessed and extended instruction set. EXAMPLE 5-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code DS39632E-page 64 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 5.3 Data Memory Organization 5.3.2 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section5.6 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit 12-bit address, allowing up to 4096 bytes of data low-order address and a 4-bit Bank Pointer. memory. The memory space is divided into as many as Most instructions in the PIC18 instruction set make use 16 banks that contain 256 bytes each. of the Bank Pointer, known as the Bank Select Register PIC18F2455/2550/4455/4550 devices implement eight (BSR). This SFR holds the 4 Most Significant bits of a complete banks, for a total of 2048 bytes. Figure5-5 location’s address; the instruction itself includes the shows the data memory organization for the devices. eightLeast Significant bits. Only the four lower bits of The data memory contains Special Function Registers the BSR are implemented (BSR3:BSR0). The upper (SFRs) and General Purpose Registers (GPRs). The four bits are unused; they will always read ‘0’ and can- SFRs are used for control and status of the controller not be written to. The BSR can be loaded directly by and peripheral functions, while GPRs are used for data using the MOVLB instruction. storage and scratchpad operations in the user’s The value of the BSR indicates the bank in data application. Any read of an unimplemented location will memory. The eight bits in the instruction show the loca- read as ‘0’s. tion in the bank and can be thought of as an offset from The instruction set and architecture allow operations the bank’s lower boundary. The relationship between across all banks. The entire data memory may be the BSR’s value and the bank division in data memory accessed by Direct, Indirect or Indexed Addressing is shown in Figure5-6. modes. Addressing modes are discussed later in this Since up to sixteen registers may share the same subsection. low-order address, the user must always be careful to To ensure that commonly used registers (SFRs and ensure that the proper bank is selected before perform- select GPRs) can be accessed in a single cycle, PIC18 ing a data read or write. For example, writing what devices implement an Access Bank. This is a 256-byte should be program data to an 8-bit address of F9h, memory space that provides fast access to SFRs and while the BSR is 0Fh, will end up resetting the program the lower portion of GPR Bank 0 without using the counter. BSR. Section5.3.3 “Access Bank” provides a While any bank can be selected, only those banks that detailed description of the Access RAM. are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while 5.3.1 USB RAM reads from unimplemented banks will return ‘0’s. Even Banks 4 through 7 of the data memory are actually so, the STATUS register will still be affected as if the mapped to special dual port RAM. When the USB operation was successful. The data memory map in module is disabled, the GPRs in these banks are used Figure5-5 indicates which banks are implemented. like any other GPR in the data memory space. In the core PIC18 instruction set, only the MOVFF When the USB module is enabled, the memory in these instruction fully specifies the 12-bit address of the banks is allocated as buffer RAM for USB operation. source and target registers. This instruction ignores the This area is shared between the microcontroller core BSR completely when it executes. All other instructions and the USB Serial Interface Engine (SIE) and is used include only the low-order address as an operand and to transfer data directly between the two. must use either the BSR or the Access Bank to locate their target registers. It is theoretically possible to use the areas of USB RAM that are not allocated as USB buffers for normal scratchpad memory or other variable storage. In prac- tice, the dynamic nature of buffer allocation makes this risky at best. Additionally, Bank 4 is used for USB buffer management when the module is enabled and should not be used for any other purposes during that time. Additional information on USB RAM and buffer operation is provided in Section17.0 “Universal Serial Bus (USB)”. © 2009 Microchip Technology Inc. DS39632E-page 65

PIC18F2455/2550/4455/4550 FIGURE 5-5: DATA MEMORY MAP When a = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. = 0000 00h Access RAM 05Fh Bank 0 060h The first 96 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The remaining 160 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When a = 1: = 0011 00h 300h The BSR specifies the bank Bank 3 GPR used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 GPR(1) FFh 4FFh = 0101 00h 500h Bank 5 GPR(1) FFh 5FFh = 0110 00h 600h Bank 6 GPR(1) Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 GPR(1) Access RAM Low 5Fh FFh 7FFh Access RAM High 60h 00h 800h (SFRs) FFh = 1000 Bank 8 Unused to Read as 00h = 1110 Bank 14 FFh EFFh 00h Unused F00h = 1111 F5Fh Bank 15 SFR F60h FFh FFFh Note 1: These banks also serve as RAM buffer for USB operation. See Section5.3.1 “USB RAM” for more information. DS39632E-page 66 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) Data Memory From Opcode(2) 7 0 000h 00h 7 0 0 0 0 0 0 0 1 1 Bank 0 FFh 1 1 1 1 1 1 1 1 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 5.3.3 ACCESS BANK however, the instruction is forced to use the Access Bank address map; the current value of the BSR is While the use of the BSR, with an embedded 8-bit ignored entirely. address, allows users to address the entire range of data memory, it also means that the user must always Using this “forced” addressing allows the instruction to ensure that the correct bank is selected. Otherwise, operate on a data address in a single cycle without data may be read from or written to the wrong location. updating the BSR first. For 8-bit addresses of 60h and This can be disastrous if a GPR is the intended target above, this means that users can evaluate and operate of an operation but an SFR is written to instead. on SFRs more efficiently. The Access RAM below 60h Verifying and/or changing the BSR for each read or is a good place for data values that the user might need write to data memory can become very inefficient. to access rapidly, such as immediate computational results or common program variables. Access RAM To streamline access for the most commonly used data also allows for faster and more code efficient context memory locations, the data memory is configured with saving and switching of variables. an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The mapping of the Access Bank is slightly different The Access Bank consists of the first 96 bytes of when the extended instruction set is enabled (XINST memory (00h-5Fh) in Bank 0 and the last 160 bytes of Configuration bit = 1). This is discussed in more detail memory (60h-FFh) in Block 15. The lower half is known in Section5.6.3 “Mapping the Access Bank in as the “Access RAM” and is composed of GPRs. The Indexed Literal Offset Mode”. upper half is where the device’s SFRs are mapped. 5.3.4 GENERAL PURPOSE These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion REGISTER FILE by an 8-bit address (Figure5-5). PIC18 devices may have banked memory in the GPR The Access Bank is used by core PIC18 instructions area. This is data RAM which is available for use by all that include the Access RAM bit (the ‘a’ parameter in instructions. GPRs start at the bottom of Bank 0 the instruction). When ‘a’ is equal to ‘1’, the instruction (address 000h) and grow upwards towards the bottom uses the BSR and the 8-bit address included in the of the SFR area. GPRs are not initialized by a opcode for the data memory address. When ‘a’ is ‘0’, Power-on Reset and are unchanged on all other Resets. © 2009 Microchip Technology Inc. DS39632E-page 67

PIC18F2455/2550/4455/4550 5.3.5 SPECIAL FUNCTION REGISTERS peripheral functions. The Reset and interrupt registers are described in their respective chapters, while the The Special Function Registers (SFRs) are registers ALU’s STATUS register is described later in this used by the CPU and peripheral modules for controlling section. Registers related to the operation of a the desired operation of the device. These registers are peripheral feature are described in the chapter for that implemented as static RAM in the data memory space. peripheral. SFRs start at the top of data memory and extend down- ward to occupy the top segment of Bank 15, from F60h The SFRs are typically distributed among the to FFFh. A list of these registers is given in Table5-1 peripherals whose functions they control. Unused SFR and Table5-2. locations are unimplemented and read as ‘0’s. The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the TABLE 5-1: SPECIAL FUNCTION REGISTER MAP Address Name Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 F7Fh UEP15 FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 F7Eh UEP14 FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 F7Dh UEP13 FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2) F7Ch UEP12 FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE F7Bh UEP11 FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —(2) F7Ah UEP10 FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2) F79h UEP9 FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2) F78h UEP8 FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL F97h —(2) F77h UEP7 FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE(3) F76h UEP6 FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3) F75h UEP5 FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h UEP4 FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h UEP3 FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA F72h UEP2 FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —(2) F71h UEP1 FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2) F70h UEP0 FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2) F6Fh UCFG FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh —(2) F6Eh UADDR FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3) F6Dh UCON FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3) F6Ch USTAT FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC F6Bh UEIE FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB F6Ah UEIR FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA F69h UIE FE8h WREG FC8h SSPADD FA8h EEDATA F88h —(2) F68h UIR FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2(1) F87h —(2) F67h UFRMH FE6h POSTINC1(1) FC6h SSPCON1 FA6h EECON1 F86h —(2) F66h UFRML FE5h POSTDEC1(1) FC5h SSPCON2 FA5h —(2) F85h —(2) F65h SPPCON(3) FE4h PREINC1(1) FC4h ADRESH FA4h —(2) F84h PORTE F64h SPPEPS(3) FE3h PLUSW1(1) FC3h ADRESL FA3h —(2) F83h PORTD(3) F63h SPPCFG(3) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SPPDATA(3) FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h —(2) FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h —(2) Note 1: Not a physical register. 2: Unimplemented registers are read as ‘0’. 3: These registers are implemented only on 40/44-pin devices. DS39632E-page 68 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 5-2: REGISTER FILE SUMMARY Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 53, 60 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 53, 60 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 53, 60 STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 53, 61 PCLATU — — — Holding Register for PC<20:16> ---0 0000 53, 60 PCLATH Holding Register for PC<15:8> 0000 0000 53, 60 PCL PC Low Byte (PC<7:0>) 0000 0000 53, 60 TBLPTRU — — bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 53, 84 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 53, 84 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 53, 84 TABLAT Program Memory Table Latch 0000 0000 53, 84 PRODH Product Register High Byte xxxx xxxx 53, 97 PRODL Product Register Low Byte xxxx xxxx 53, 97 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 53, 101 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 53, 102 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 53, 103 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 53, 75 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 53, 76 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 53, 76 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 53, 76 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – N/A 53, 76 value of FSR0 offset by W FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 53, 75 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 53, 75 WREG Working Register xxxx xxxx 53 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 53, 75 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 53, 76 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 53, 76 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 53, 76 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – N/A 53, 76 value of FSR1 offset by W FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 53, 75 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 53, 75 BSR — — — — Bank Select Register ---- 0000 54, 65 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 54, 75 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 54, 76 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 54, 76 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 54, 76 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – N/A 54, 76 value of FSR2 offset by W FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 54, 75 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 54, 75 STATUS — — — N OV Z DC C ---x xxxx 54, 73 TMR0H Timer0 Register High Byte 0000 0000 54, 129 TMR0L Timer0 Register Low Byte xxxx xxxx 54, 129 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 54, 127 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits. 2: The SBOREN bit is only available when BOREN<1:0>=01; otherwise, the bit reads as ‘0’. 3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. 5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3>=0). 7: I2C™ Slave mode only. © 2009 Microchip Technology Inc. DS39632E-page 69

PIC18F2455/2550/4455/4550 TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 54, 33 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 54, 285 WDTCON — — — — — — — SWDTEN --- ---0 54, 304 RCON IPEN SBOREN(2) — RI TO PD POR BOR 0q-1 11q0 54, 46 TMR1H Timer1 Register High Byte xxxx xxxx 54, 136 TMR1L Timer1 Register Low Byte xxxx xxxx 54, 136 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 54, 131 TMR2 Timer2 Register 0000 0000 54, 138 PR2 Timer2 Period Register 1111 1111 54, 138 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 54, 137 SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 54, 198, 207 SSPADD MSSP Address Register in I2C™ Slave mode. MSSP Baud Rate Reload Register in I2C™ Master mode. 0000 0000 54, 207 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 54, 198, 208 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 54, 199, 209 SSPCON2 GCEN ACKSTAT ACKDT/ ACKEN/ RCEN/ PEN/ RSEN/ SEN 0000 0000 54, 210 ADMSK5(7) ADMSK4(7) ADMSK3(7) ADMSK2(7) ADMSK1(7) ADRESH A/D Result Register High Byte xxxx xxxx 54, 274 ADRESL A/D Result Register Low Byte xxxx xxxx 54, 274 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 54, 265 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 54, 266 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 54, 267 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 55, 144 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 55, 144 CCP1CON P1M1(3) P1M0(3) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 55, 143, 151 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 55, 144 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 55, 144 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 55, 143 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 55, 246 ECCP1DEL PRSEN PDC6(3) PDC5(3) PDC4(3) PDC3(3) PDC2(3) PDC1(3) PDC0(3) 0000 0000 55, 160 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(3) PSSBD0(3) 0000 0000 55, 161 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 55, 281 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 55, 275 TMR3H Timer3 Register High Byte xxxx xxxx 55, 141 TMR3L Timer3 Register Low Byte xxxx xxxx 55, 141 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 55, 139 SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 55, 247 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 55, 247 RCREG EUSART Receive Register 0000 0000 55, 256 TXREG EUSART Transmit Register 0000 0000 55, 253 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 55, 244 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 55, 245 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits. 2: The SBOREN bit is only available when BOREN<1:0>=01; otherwise, the bit reads as ‘0’. 3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. 5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3>=0). 7: I2C™ Slave mode only. DS39632E-page 70 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page EEADR EEPROM Address Register 0000 0000 55, 91 EEDATA EEPROM Data Register 0000 0000 55, 91 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 55, 82 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 55, 83 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 1111 1111 56, 109 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 0000 0000 56, 105 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 0000 0000 56, 107 IPR1 SPPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 56, 108 PIR1 SPPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 56, 104 PIE1 SPPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 56, 106 OSCTUNE INTSRC — — TUN4 TUN3 TUN2 TUN1 TUN0 0--0 0000 56, 28 TRISE(3) — — — — — TRISE2 TRISE1 TRISE0 ---- -111 56, 126 TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 56, 124 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 11-- -111 56, 121 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 56, 118 TRISA — TRISA6(4) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 56, 115 LATE(3) — — — — — LATE2 LATE1 LATE0 ---- -xxx 56, 126 LATD(3) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 56, 124 LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 xx-- -xxx 56, 121 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 56, 118 LATA — LATA6(4) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 -xxx xxxx 56, 115 PORTE RDPU(3) — — — RE3(5) RE2(3) RE1(3) RE0(3) 0--- x000 56, 125 PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 56, 124 PORTC RC7 RC6 RC5(6) RC4(6) — RC2 RC1 RC0 xxxx -xxx 56, 121 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 56, 118 PORTA — RA6(4) RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 56, 115 UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits. 2: The SBOREN bit is only available when BOREN<1:0>=01; otherwise, the bit reads as ‘0’. 3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. 5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3>=0). 7: I2C™ Slave mode only. © 2009 Microchip Technology Inc. DS39632E-page 71

PIC18F2455/2550/4455/4550 TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000 57, 168 UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 57, 173 UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 57, 166 USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 57, 171 UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 57, 185 UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 57, 184 UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 57, 183 UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 57, 181 UFRMH — — — — — FRM10 FRM9 FRM8 ---- -xxx 57, 173 UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 57, 173 SPPCON(3) — — — — — — SPPOWN SPPEN ---- --00 57, 191 SPPEPS(3) RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 00-0 0000 57, 195 SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 0000 0000 57, 192 SPPDATA(3) DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0000 0000 57, 196 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits. 2: The SBOREN bit is only available when BOREN<1:0>=01; otherwise, the bit reads as ‘0’. 3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. 5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3>=0). 7: I2C™ Slave mode only. DS39632E-page 72 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 5.3.6 STATUS REGISTER It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS The STATUS register, shown in Register5-2, contains register because these instructions do not affect the Z, the arithmetic status of the ALU. As with any other SFR, C, DC, OV or N bits in the STATUS register. it can be the operand for any instruction. For other instructions that do not affect Status bits, see If the STATUS register is the destination for an instruc- the instruction set summaries in Table26-2 and tion that affects the Z, DC, C, OV or N bits, the results Table26-3. of the instruction are not written; instead, the STATUS register is updated according to the instruction Note: The C and DC bits operate as the Borrow performed. Therefore, the result of an instruction with and Digit Borrow bits, respectively, in the STATUS register as its destination may be different subtraction. than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). REGISTER 5-2: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. 2: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. DS39632E-page 73

PIC18F2455/2550/4455/4550 5.4 Data Addressing Modes Purpose Register File”) or a location in the Access Bank (Section5.3.3 “Access Bank”) as the data Note: The execution of some instructions in the source for the instruction. core PIC18 instruction set are changed The Access RAM bit ‘a’ determines how the address is when the PIC18 extended instruction interpreted. When ‘a’ is ‘1’, the contents of the BSR setis enabled. See Section5.6 “Data (Section5.3.2 “Bank Select Register (BSR)”) are Memory and the Extended Instruction used with the address to determine the complete 12-bit Set” for more information. address of the register. When ‘a’ is ‘0’, the address is While the program memory can be addressed in only interpreted as being a register in the Access Bank. one way – through the program counter – information Addressing that uses the Access RAM is sometimes in the data memory space can be addressed in several also known as Direct Forced Addressing mode. ways. For most instructions, the addressing mode is A few instructions, such as MOVFF, include the entire fixed. Other instructions may use up to three modes, 12-bit address (either source or destination) in their depending on which operands are used and whether or opcodes. In these cases, the BSR is ignored entirely. not the extended instruction set is enabled. The destination of the operation’s results is determined The addressing modes are: by the destination bit ‘d’. When ‘d’ is ‘1’, the results are • Inherent stored back in the source register, overwriting its origi- nal contents. When ‘d’ is ‘0’, the results are stored in • Literal the W register. Instructions without the ‘d’ argument • Direct have a destination that is implicit in the instruction; their • Indirect destination is either the target register being operated An additional addressing mode, Indexed Literal Offset, on or the W register. is available when the extended instruction set is 5.4.3 INDIRECT ADDRESSING enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section5.6.1 “Indexed Indirect Addressing allows the user to access a location Addressing with Literal Offset”. in data memory without giving a fixed address in the instruction. This is done by using File Select Registers 5.4.1 INHERENT AND LITERAL (FSRs) as pointers to the locations to be read or written ADDRESSING to. Since the FSRs are themselves located in RAM as Many PIC18 control instructions do not need any Special Function Registers, they can also be directly argument at all; they either perform an operation that manipulated under program control. This makes FSRs globally affects the device or they operate implicitly on very useful in implementing data structures, such as one register. This addressing mode is known as tables and arrays in data memory. Inherent Addressing. Examples include SLEEP, RESET The registers for Indirect Addressing are also and DAW. implemented with Indirect File Operands (INDFs) that Other instructions work in a similar way but require an permit automatic manipulation of the pointer value with additional explicit argument in the opcode. This is auto-incrementing, auto-decrementing or offsetting known as Literal Addressing mode because they with another value. This allows for efficient code, using require some literal value as an argument. Examples loops, such as the example of clearing an entire RAM include ADDLW and MOVLW, which respectively, add or bank in Example5-5. move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit EXAMPLE 5-5: HOW TO CLEAR RAM program memory address. (BANK 1) USING INDIRECT ADDRESSING 5.4.2 DIRECT ADDRESSING LFSR FSR0, 100h ; Direct Addressing mode specifies all or part of the NEXT CLRF POSTINC0 ; Clear INDF source and/or destination address of the operation ; register then within the opcode itself. The options are specified by ; inc pointer the arguments accompanying the instruction. BTFSS FSR0H, 1 ; All done with ; Bank1? In the core PIC18 instruction set, bit-oriented and BRA NEXT ; NO, clear next byte-oriented instructions use some version of Direct CONTINUE ; YES, continue Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section5.3.4 “General DS39632E-page 74 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 5.4.3.1 FSR Registers and the mapped in the SFR space but are not physically imple- INDF Operand mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. At the core of Indirect Addressing are three sets of A read from INDF1, for example, reads the data at the registers: FSR0, FSR1 and FSR2. Each represents a address indicated by FSR1H:FSR1L. Instructions that pair of 8-bit registers: FSRnH and FSRnL. The four use the INDF registers as operands actually use the upper bits of the FSRnH register are not used, so each contents of their corresponding FSR as a pointer to the FSR pair holds a 12-bit value. This represents a value instruction’s target. The INDF operand is just a that can address the entire range of the data memory convenient way of using the pointer. in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current Indirect Addressing is accomplished with a set of contents of the BSR and the Access RAM bit have no Indirect File Operands, INDF0 through INDF2. These effect on determining the target address. can be thought of as “virtual” registers; they are FIGURE 5-7: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 indirect addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... x x x x 1 1 1 0 1 1 0 0 1 1 0 0 Bank 3 through Bank 13 ...to determine the data memory location to be used in that operation. E00h In this case, the FSR1 pair contains ECCh. This means the contents of BBaannkk 1144 location ECCh will be added to that F00h of the W register and stored back in Bank 15 ECCh. FFFh Data Memory © 2009 Microchip Technology Inc. DS39632E-page 75

PIC18F2455/2550/4455/4550 5.4.3.2 FSR Registers and POSTINC, 5.4.3.3 Operations by FSRs on FSRs POSTDEC, PREINC and PLUSW Indirect Addressing operations that target other FSRs In addition to the INDF operand, each FSR register pair or virtual registers represent special cases. For exam- also has four additional indirect operands. Like INDF, ple, using an FSR to point to one of the virtual registers these are “virtual” registers that cannot be indirectly will not result in successful operations. As a specific read or written to. Accessing these registers actually case, assume that FSR0H:FSR0L contains FE7h, the accesses the associated FSR register pair, but also address of INDF1. Attempts to read the value of INDF1, performs a specific action on it stored value. They are: using INDF0 as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as the operand, will • POSTDEC: accesses the FSR value, then result in a NOP. automatically decrements it by ‘1’ afterwards • POSTINC: accesses the FSR value, then On the other hand, using the virtual registers to write to automatically increments it by ‘1’ afterwards an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any • PREINC: increments the FSR value by ‘1’, then incrementing or decrementing. Thus, writing to INDF2 uses it in the operation or POSTDEC2 will write the same value to the • PLUSW: adds the signed value of the W register FSR2H:FSR2L. (range of -127 to 128) to that of the FSR and uses the new value in the operation. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct In this context, accessing an INDF register uses the operations. Users should proceed cautiously when value in the FSR registers without changing them. Sim- working on these registers, particularly if their code ilarly, accessing a PLUSW register gives the FSR value uses Indirect Addressing. offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual Similarly, operations by Indirect Addressing are gener- registers changes the value of the FSR registers. ally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently Operations on the FSRs with POSTDEC, POSTINC change settings that might affect the operation of the and PREINC affect the entire register pair; that is, device. rollovers of the FSRnL register, from FFh to 00h, carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. DS39632E-page 76 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 5.5 Program Memory and the When using the extended instruction set, this Extended Instruction Set addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0); The operation of program memory is unaffected by the and use of the extended instruction set. • The file address argument is less than or equal Enabling the extended instruction set adds eight to 5Fh. additional two-word commands to the existing Under these conditions, the file address of the instruc- PIC18instruction set: ADDFSR, ADDULNK, CALLW, tion is not interpreted as the lower byte of an address MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These (used with the BSR in Direct Addressing), or as an 8-bit instructions are executed as described in address in the Access Bank. Instead, the value is Section5.2.4 “Two-Word Instructions”. interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of 5.6 Data Memory and the Extended FSR2 are added to obtain the target address of the Instruction Set operation. Enabling the PIC18 extended instruction set (XINST 5.6.2 INSTRUCTIONS AFFECTED BY Configuration bit = 1) significantly changes certain INDEXED LITERAL OFFSET MODE aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the Any of the core PIC18 instructions that can use Direct core PIC18 instructions is different. This is due to the Addressing are potentially affected by the Indexed introduction of a new addressing mode for the data Literal Offset Addressing mode. This includes all memory space. This mode also alters the behavior of byte-oriented and bit-oriented instructions, or almost Indirect Addressing using FSR2 and its associated one-half of the standard PIC18 instruction set. Instruc- operands. tions that only use Inherent or Literal Addressing modes are unaffected. What does not change is just as important. The size of the data memory space is unchanged, as well as its Additionally, byte-oriented and bit-oriented instructions linear addressing. The SFR map remains the same. are not affected if they do not use the Access Bank Core PIC18 instructions can still operate in both Direct (Access RAM bit is ‘1’) or include a file address of 60h and Indirect Addressing mode; inherent and literal or above. Instructions meeting these criteria will instructions do not change at all. Indirect Addressing continue to execute as before. A comparison of the with FSR0 and FSR1 also remains unchanged. different possible addressing modes when the extended instruction set is enabled in shown in 5.6.1 INDEXED ADDRESSING WITH Figure5-8. LITERAL OFFSET Those who desire to use byte-oriented or bit-oriented Enabling the PIC18 extended instruction set changes instructions in the Indexed Literal Offset mode should the behavior of Indirect Addressing using the FSR2 note the changes to assembler syntax for this mode. register pair and its associated file operands. Under the This is described in more detail in Section26.2.1 proper conditions, instructions that use the Access “Extended Instruction Syntax”. Bank – that is, most bit-oriented and byte-oriented instructions – can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. © 2009 Microchip Technology Inc. DS39632E-page 77

PIC18F2455/2550/4455/4550 FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When a = 0 and f ≥ 60h: The instruction executes in 060h Direct Forced mode. ‘f’ is inter- 080h Bank 0 preted as a location in the 100h Access RAM between 060h 00h and 0FFh. This is the same as Bank 1 60h the SFRs or locations F60h to through 0FFh (Bank 15) of data Bank 14 Valid range for ‘f’ memory. FFh Locations below 60h are not F00h Access RAM Bank 15 available in this addressing F60h mode. SFRs FFFh Data Memory When a = 0 and f ≤ 5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 080h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to obtain the address of the target Bank 1 through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F60h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When a = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 080h Direct mode (also known as Direct Long mode). ‘f’ is inter- 100h preted as a location in one of the 16 banks of the data 001001da ffffffff Bank 1 memory space. The bank is through designated by the Bank Select Bank 14 Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F60h SFRs FFFh Data Memory DS39632E-page 78 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 5.6.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue The use of Indexed Literal Offset Addressing mode to use Direct Addressing as before. Any indirect or effectively changes how the lower portion of Access indexed operation that explicitly uses any of the indirect RAM (00h to 5Fh) is mapped. Rather than containing file operands (including FSR2) will continue to operate just the contents of the bottom half of Bank 0, this mode as standard Indirect Addressing. Any instruction that maps the contents from Bank 0 and a user-defined uses the Access Bank, but includes a register address “window” that can be located anywhere in the data of greater than 05Fh, will use Direct Addressing and memory space. The value of FSR2 establishes the the normal Access Bank map. lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 5.6.4 BSR IN INDEXED LITERAL plus 95 (5Fh). Addresses in the Access RAM above OFFSET MODE 5Fh are mapped as previously described (see Section5.3.3 “Access Bank”). An example of Access Although the Access Bank is remapped when the Bank remapping in this addressing mode is shown in extended instruction set is enabled, the operation of the Figure5-9. BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. FIGURE 5-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: ADDWF f, d, a 000h FSR2H:FSR2L = 120h Bank 0 Locations in the region from the FSR2 Pointer 100h (120h) to the pointer plus 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Access RAM (000h-05Fh). 200h Bank 1 “Window” 5Fh Special Function Registers 60h at F60h through FFFh are mapped to 60h through Bank 2 FFh as usual. through SFRs Bank 0 addresses below Bank 14 5Fh are not available in FFh this mode. They can still Access Bank be addressed by using the F00h BSR. Bank 15 F60h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. DS39632E-page 79

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 80 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable, during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte • Table Read (TBLRD) at a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 32 bytes at a time. Program memory is The program memory space is 16 bits wide, while the erased in blocks of 64 bytes at a time. A Bulk Erase data RAM space is 8 bits wide. Table reads and table operation may not be issued from user code. writes move data between these two memory spaces Writing or erasing program memory will cease through an 8-bit register (TABLAT). instruction fetches until the operation is complete. The Table read operations retrieve data from program program memory cannot be accessed during the write memory and place it into the data RAM space. or erase, therefore, code cannot execute. An internal Figure6-1 shows the operation of a table read with programming timer terminates program memory writes program memory and data RAM. and erases. Table write operations store data from the data memory A value written to program memory does not need to be space into holding registers in program memory. The a valid instruction. Executing a program memory procedure to write the contents of the holding registers location that forms an invalid instruction results in a into program memory is detailed in Section6.5 “Writing NOP. to Flash Program Memory”. Figure6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. DS39632E-page 81

PIC18F2455/2550/4455/4550 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in Section6.5 “Writing to Flash Program Memory”. 6.2 Control Registers The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase Several control registers are used in conjunction with operation is initiated on the next WR command. When the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled. • EECON1 register The WREN bit, when set, will allow a write operation. • EECON2 register On power-up, the WREN bit is clear. The WRERR bit is • TABLAT register set in hardware when the WREN bit is set and cleared • TBLPTR registers when the internal programming timer expires and the write operation is complete. 6.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is The EECON1 register (Register6-1) is the control read as ‘1’. This can indicate that a write register for memory accesses. The EECON2 register is operation was prematurely terminated by not a physical register; it is used exclusively in the a Reset or a write operation was memory write and erase sequences. Reading attempted improperly. EECON2 will read all ‘0’s. The WR control bit initiates write operations. The bit The EEPGD control bit determines if the access will be cannot be cleared, only set, in software; it is cleared in a program or data EEPROM memory access. When hardware at the completion of the write operation. clear, any subsequent operations will operate on the Note: The EEIF interrupt flag bit (PIR2<4>) is set data EEPROM memory. When set, any subsequent when the write is complete. It must be operations will operate on the program memory. cleared in software. The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section25.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD. DS39632E-page 82 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 6-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. DS39632E-page 83

PIC18F2455/2550/4455/4550 6.2.2 TABLE LATCH REGISTER (TABLAT) 6.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the SFR space. The Table Latch register is used to Flash program memory. hold 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the TBLPTR memory and data RAM. determine which byte is read from program memory into TABLAT. 6.2.3 TABLE POINTER REGISTER (TBLPTR) When a TBLWT is executed, the five LSbs of the Table Pointer register (TBLPTR<4:0>) determine which of The Table Pointer (TBLPTR) register addresses a byte the 32 program memory holding registers is written to. within the program memory. The TBLPTR is comprised When the timed write to program memory begins (via of three SFR registers: Table Pointer Upper Byte, Table the WR bit), the 16 MSbs of the TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<21:6>) determine which program memory (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- block of 32 bytes is written to. For more detail, see ters join to form a 22-bit wide pointer. The low-order Section6.5 “Writing to Flash Program Memory”. 21bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to When an erase of program memory is executed, the the Device ID, the user ID and the Configuration bits. 16MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least The Table Pointer, TBLPTR, is used by the TBLRD and Significant bits (TBLPTR<5:0>) are ignored. TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table opera- Figure6-3 describes the relevant boundaries of the tion. These operations are shown in Table6-1. These TBLPTR based on Flash program memory operations. operations on the TBLPTR only affect the low-order 21bits. TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 TABLE ERASE TBLPTR<21:6> TABLE WRITE – TBLPTR<21:5> TABLE READ – TBLPTR<21:0> DS39632E-page 84 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 6.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure6-4 shows the interface between the internal program memory and the TABLAT. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVF WORD_ODD © 2009 Microchip Technology Inc. DS39632E-page 85

PIC18F2455/2550/4455/4550 6.4 Erasing Flash Program Memory 6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through The sequence of events for erasing a block of internal ICSP control, can larger blocks of program memory be program memory is: Bulk Erased. Word Erase in the Flash array is not 1. Load Table Pointer register with address of row supported. being erased. When initiating an erase sequence from the micro- 2. Set the EECON1 register for the erase operation: controller itself, a block of 64 bytes of program memory • set EEPGD bit to point to program memory; is erased. The Most Significant 16 bits of the • clear the CFGS bit to access program memory; TBLPTR<21:6> point to the block being erased. • set WREN bit to enable writes; TBLPTR<5:0> are ignored. • set FREE bit to enable the erase. The EECON1 register commands the erase operation. 3. Disable interrupts. The EEPGD bit must be set to point to the Flash 4. Write 55h to EECON2. program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase 5. Write 0AAh to EECON2. operation. 6. Set the WR bit. This will begin the Row Erase cycle. For protection, the write initiate sequence for EECON2 must be used. 7. The CPU will stall for duration of the erase (about 2ms using internal timer). A long write is necessary for erasing the internal Flash. 8. Re-enable interrupts. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS39632E-page 86 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 6.5 Writing to Flash Program Memory The long write is necessary for programming the internal Flash. Instruction execution is halted while in a The minimum programming block is 16 words or long write cycle. The long write will be terminated by 32bytes. Word or byte programming is not supported. the internal programming timer. Table writes are used internally to load the holding The EEPROM on-chip timer controls the write time. registers needed to program the Flash memory. There The write/erase voltages are generated by an on-chip are 32 holding registers used by the table writes for charge pump, rated to operate over the voltage range programming. of the device. Since the Table Latch (TABLAT) is only a single byte, the Note: The default value of the holding registers on TBLWT instruction may need to be executed 32times for device Resets and after write operations is each programming operation. All of the table write oper- FFh. A write of FFh to a holding register ations will essentially be short writes because only the does not modify that byte. This means that holding registers are written. At the end of updating the individual bytes of program memory may be 32 holding registers, the EECON1 register must be modified, provided that the change does not written to in order to start the programming operation attempt to change any bit from a ‘0’ to a ‘1’. with a long write. When modifying individual bytes, it is not necessary to load all 32 holding registers before executing a write operation. FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxx00 TBLPTR = xxxx01 TBLPTR = xxxx02 TBLPTR = xxxx1F Holding Register Holding Register Holding Register Holding Register Program Memory 6.5.1 FLASH PROGRAM MEMORY WRITE 8. Disable interrupts. SEQUENCE 9. Write 55h to EECON2. The sequence of events for programming an internal 10. Write 0AAh to EECON2. program memory location should be: 11. Set the WR bit. This will begin the write cycle. 1. Read 64 bytes into RAM. 12. The CPU will stall for duration of the write (about 2ms using internal timer). 2. Update data values in RAM as necessary. 13. Re-enable interrupts. 3. Load Table Pointer register with address being erased. 14. Repeat steps 6 through 14 once more to write 64 bytes. 4. Execute the Row Erase procedure. 15. Verify the memory (table read). 5. Load Table Pointer register with address of first byte being written. This procedure will require about 8ms to update one 6. Write 32 bytes into the holding registers with row of 64 bytes of memory. An example of the required auto-increment. code is given in Example6-3. 7. Set the EECON1 register for the write operation: Note: Before setting the WR bit, the Table • set EEPGD bit to point to program memory; Pointer address needs to be within the • clear the CFGS bit to access program memory; intended address range of the 32 bytes in the holding register. • set WREN to enable byte writes. © 2009 Microchip Technology Inc. DS39632E-page 87

PIC18F2455/2550/4455/4550 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64’ ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW D’2’ MOVWF COUNTER1 WRITE_BUFFER_BACK MOVLW D’32’ ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS MOVF POSTINC0, W ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_WORD_TO_HREGS DS39632E-page 88 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) DECFSZ COUNTER1 BRA WRITE_BUFFER_BACK BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory 6.5.2 WRITE VERIFY 6.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the To protect against spurious writes to Flash program memory should be verified against the original value. memory, the write initiate sequence must also be This should be used in applications where excessive followed. See Section25.0 “Special Features of the writes can stress bits near the specification limit. CPU” for more detail. 6.5.3 UNEXPECTED TERMINATION OF 6.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section25.5 “Program Verification and Code location just programmed should be verified and repro- Protection” for details on code protection of Flash grammed if needed. If the write operation is interrupted program memory. by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TBLPTRU — — bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 53 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 53 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 53 TABLAT Program Memory Table Latch 53 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 EECON2 EEPROM Control Register 2 (not a physical register) 55 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 55 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits. © 2009 Microchip Technology Inc. DS39632E-page 89

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PIC18F2455/2550/4455/4550 7.0 DATA EEPROM MEMORY Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data The data EEPROM is a nonvolatile memory array, EEPROM memory. When set, subsequent operations separate from the data RAM and program memory, that access Configuration registers. When CFGS is clear, is used for long-term storage of program data. It is not the EEPGD bit selects either Flash program or data directly mapped in either the register file or program EEPROM memory. memory space, but is indirectly addressed through the The WREN bit, when set, will allow a write operation. Special Function Registers (SFRs). The EEPROM is On power-up, the WREN bit is clear. The WRERR bit is readable and writable during normal operation over the set in hardware when the WREN bit is set and cleared entire VDD range. when the internal programming timer expires and the Four SFRs are used to read and write to the data write operation is complete. EEPROM as well as the program memory. They are: Note: During normal operation, the WRERR is • EECON1 read as ‘1’. This can indicate that a write • EECON2 operation was prematurely terminated by • EEDATA a Reset or a write operation was • EEADR attempted improperly. The data EEPROM allows byte read and write. When The WR control bit initiates write operations. The bit interfacing to the data memory block, EEDATA holds cannot be cleared, only set, in software; it is cleared in the 8-bit data for read/write and the EEADR register hardware at the completion of the write operation. holds the address of the EEPROM location being Note: The EEIF interrupt flag bit (PIR2<4>) is set accessed. when the write is complete. It must be The EEPROM data memory is rated for high erase/write cleared in software. cycle endurance. A byte write automatically erases the Control bits, RD and WR, start read and erase/write location and writes the new data (erase-before-write). operations, respectively. These bits are set by firmware The write time is controlled by an on-chip timer; it will and cleared by hardware at the completion of the vary with voltage and temperature as well as from chip operation. to chip. Please refer to parameter D122 (Table28-1 in Section28.0 “Electrical Characteristics”) for exact The RD bit cannot be set when accessing program limits. memory (EEPGD = 1). Program memory is read using table read instructions. See Section6.1 “Table Reads 7.1 EECON1 and EECON2 Registers and Table Writes” regarding table reads. Access to the data EEPROM is controlled by two The EECON2 register is not a physical register. It is registers: EECON1 and EECON2. These are the same used exclusively in the memory write and erase registers which control access to the program memory sequences. Reading EECON2 will read all ‘0’s. and are used in a similar manner for the data EEPROM. The EECON1 register (Register7-1) is the control register for data and program memory access. Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. © 2009 Microchip Technology Inc. DS39632E-page 91

PIC18F2455/2550/4455/4550 REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39632E-page 92 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 7.2 Reading the Data EEPROM Additionally, the WREN bit in EECON1 must be set to Memory enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- To read a data memory location, the user must write the cution (i.e., runaway programs). The WREN bit should address to the EEADR register, clear the EEPGD be kept clear at all times except when updating the control bit (EECON1<7>) and then set control bit, RD EEPROM. The WREN bit is not cleared byhardware. (EECON1<0>). The data is available on the very next After a write sequence has been initiated, EECON1, instruction cycle; therefore, the EEDATA register can EEADR and EEDATA cannot be modified. The WR bit be read by the next instruction. EEDATA will hold this will be inhibited from being set unless the WREN bit is value until another read operation or until it is written to set. The WREN bit must be set on a previous instruc- by the user (during a write operation). tion. Both WR and WREN cannot be set with the same The basic process is shown in Example7-1. instruction. At the completion of the write cycle, the WR bit is 7.3 Writing to the Data EEPROM cleared in hardware and the EEPROM Interrupt Flag bit Memory (EEIF) is set. The user may either enable this interrupt, or poll this bit. EEIF must be cleared by software. To write an EEPROM data location, the address must first be written to the EEADR register and the data 7.4 Write Verify written to the EEDATA register. The sequence in Example7-2 must be followed to initiate the write cycle. Depending on the application, good programming The write will not begin if this sequence is not exactly practice may dictate that the value written to the followed (write 55h to EECON2, write 0AAh to memory should be verified against the original value. EECON2, then set WR bit) for each byte. It is strongly This should be used in applications where excessive recommended that interrupts be disabled during this writes can stress bits near the specification limit. codesegment. EXAMPLE 7-1: DATA EEPROM READ MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Lower bits of Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA EXAMPLE 7-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Lower bits of Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable Interrupts ; User code execution BCF EECON1, WREN ; Disable writes on write complete (EEIF set) © 2009 Microchip Technology Inc. DS39632E-page 93

PIC18F2455/2550/4455/4550 7.5 Operation During Code-Protect 7.7 Using the Data EEPROM Data EEPROM memory has its own code-protect bits in The data EEPROM is a high-endurance, byte- Configuration Words. External read and write addressable array that has been optimized for the operations are disabled if code protection is enabled. storage of frequently changing information (e.g., program variables or other data that are updated The microcontroller itself can both read and write to the often). Frequently changing values will typically be internal data EEPROM regardless of the state of the updated more often than specification D124 or D124A. code-protect Configuration bit. Refer to Section25.0 If this is not the case, an array refresh must be “Special Features of the CPU” for additional performed. For this reason, variables that change information. infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. 7.6 Protection Against Spurious Write A simple data EEPROM refresh routine is shown in There are conditions when the device may not want to Example7-3. write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have Note: If data EEPROM is only used to store constants and/or data that changes rarely, been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM are blocked an array refresh is likely not required. See during the Power-up Timer period (TPWRT, specification D124 or D124A. parameter33, Table28-12). The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE CLRF EEADR ; Start at address 0 BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes Loop ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA LOOP ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts DS39632E-page 94 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 EEADR EEPROM Address Register 55 EEDATA EEPROM Data Register 55 EECON2 EEPROM Control Register 2 (not a physical register) 55 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 55 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. DS39632E-page 95

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 96 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 8.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 8-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 8.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY register. ROUTINE Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the MOVF ARG1, W MULWF ARG2 ; ARG1 * ARG2 -> advantages of higher computational throughput and ; PRODH:PRODL reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit allows the PIC18 devices to be used in many applica- SUBWF PRODH, F ; PRODH = PRODH tions previously reserved for digital signal processors. ; - ARG1 A comparison of various hardware and software MOVF ARG2, W multiply operations, along with the savings in memory BTFSC ARG1, SB ; Test Sign Bit and execution time, is shown in Table8-1. SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 8.2 Operation Example8-1 shows the instruction sequence for an 8x8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example8-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 μs Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 μs 6 μs Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs 16 x 16 unsigned Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs 16 x 16 signed Hardware multiply 35 40 4.0 μs 16.0 μs 40 μs © 2009 Microchip Technology Inc. DS39632E-page 97

PIC18F2455/2550/4455/4550 Example8-3 shows the sequence to do a 16 x 16 EQUATION 8-2: 16 x 16 SIGNED unsigned multiplication. Equation8-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + EQUATION 8-1: 16 x 16 UNSIGNED (ARG1H • ARG2L • 28) + MULTIPLICATION (ARG1L • ARG2H • 28) + ALGORITHM (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L (-1 • ARG1H<7> • ARG2H:ARG2L • 216) = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + EXAMPLE 8-4: 16 x 16 SIGNED (ARG1L • ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 8-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L,W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example8-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation8-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers ; (RES3:RES0). To account for the sign bits of the SIGN_ARG1 arguments, the MSb for each argument pair is tested BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? and the appropriate subtractions are done. BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS39632E-page 98 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 9.0 INTERRUPTS When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the The PIC18F2455/2550/4455/4550 devices have IPEN bit is cleared, this is the GIE bit. If interrupt priority multiple interrupt sources and an interrupt priority feature levels are used, this will be either the GIEH or GIEL bit. that allows each interrupt source to be assigned a high- High-priority interrupt sources can interrupt a low- priority level or a low-priority level. The high-priority priority interrupt. Low-priority interrupts are not interrupt vector is at 000008h and the low-priority processed while high-priority interrupts are in progress. interrupt vector is at 000018h. High-priority interrupt The return address is pushed onto the stack and the events will interrupt any low-priority interrupts that may PC is loaded with the interrupt vector address be in progress. (000008h or 000018h). Once in the Interrupt Service There are ten registers which are used to control Routine, the source(s) of the interrupt can be deter- interrupt operation. These registers are: mined by polling the interrupt flag bits. The interrupt • RCON flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. • INTCON • INTCON2 The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL • INTCON3 if priority levels are used) which re-enables interrupts. • PIR1, PIR2 For external interrupt events, such as the INTx pins or • PIE1, PIE2 the PORTB input change interrupt, the interrupt latency • IPR1, IPR2 will be three to four instruction cycles. The exact It is recommended that the Microchip header files latency is the same for one or two-cycle instructions. supplied with MPLAB® IDE be used for the symbolic bit Individual interrupt flag bits are set regardless of the names in these registers. This allows the assembler/ status of their corresponding enable bit or the GIE bit. compiler to automatically take care of the placement of Note: Do not use the MOVFF instruction to modify these bits within the specified register. any of the interrupt control registers while Each interrupt source has three bits to control its any interrupt is enabled. Doing so may operation. The functions of these bits are: cause erratic microcontroller behavior. • Flag bit to indicate that an interrupt event occurred 9.1 USB Interrupts • Enable bit that allows program execution to Unlike other peripherals, the USB module is capable of branch to the interrupt vector address when the generating a wide range of interrupts for many types of flag bit is set events. These include several types of normal commu- • Priority bit to select high priority or low priority nication and status events and several module level The interrupt priority feature is enabled by setting the error events. IPEN bit (RCON<7>). When interrupt priority is To handle these events, the USB module is equipped enabled, there are two bits which enable interrupts with its own interrupt logic. The logic functions in a globally. Setting the GIEH bit (INTCON<7>) enables all manner similar to the microcontroller level interrupt fun- interrupts that have the priority bit set (high priority). nel, with each interrupt source having separate flag and Setting the GIEL bit (INTCON<6>) enables all enable bits. All events are funneled to a single device interrupts that have the priority bit cleared (low priority). level interrupt, USBIF (PIR2<5>). Unlike the device When the interrupt flag, enable bit and appropriate level interrupt logic, the individual USB interrupt events global interrupt enable bit are set, the interrupt will cannot be individually assigned their own priority. This vector immediately to address 000008h or 000018h, is determined at the device level interrupt funnel for all depending on the priority bit setting. Individual inter- USB events by the USBIP bit. rupts can be disabled through their corresponding For additional details on USB interrupt logic, refer to enable bits. Section17.5 “USB Interrupts”. When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC® mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. © 2009 Microchip Technology Inc. DS39632E-page 99

PIC18F2455/2550/4455/4550 FIGURE 9-1: INTERRUPT LOGIC Wake-up if in Sleep Mode TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Interrupt to CPU INT1IF Vector to Location INT1IE Peripheral Interrupt Flag bit INT1IP 0008h Peripheral Interrupt Enable bit INT2IF Peripheral Interrupt Priority bit INT2IE INT2IP TMR1IF GIE/GIEH TMR1IE TMR1IP IPEN From USB USBIF IPEN Interrupt Logic USBIE PEIE/GIEL USBIP IPEN Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Interrupt to CPU TMR0IF Vector to Location TMR0IE 0018h TMR1IF TMR0IP TMR1IE TMR1IP RBIF RBIE FInrtoemrru UpSt BLo gic UUSSBBIIEF RBIP PEIE/GIEL USBIP GIE/GIEH INT1IF Additional Peripheral Interrupts INT1IE INT1IP INT2IF INT2IE INT2IP DS39632E-page 100 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 9.2 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers which contain various enable, priority and flag interrupt enable bit. User software should bits. ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts (if GIE/GIEH = 1) 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction cycle, will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. DS39632E-page 101

PIC18F2455/2550/4455/4550 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39632E-page 102 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. DS39632E-page 103

PIC18F2455/2550/4455/4550 9.3 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the Global peripheral interrupts. Due to the number of peripheral Interrupt Enable bit, GIE (INTCON<7>). interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1 and PIR2). 2: User software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPPIF: Streaming Parallel Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear. DS39632E-page 104 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5 USBIF: USB Interrupt Flag bit 1 = USB has requested an interrupt (must be cleared in software) 0 = No USB interrupt request bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision has occurred (must be cleared in software) 0 = No bus collision occurred bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A high/low-voltage condition occurred (must be cleared in software) 0 = No high/low-voltage event has occurred bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 or TMR3 register capture occurred (must be cleared in software) 0 = No TMR1 or TMR3 register capture occurred Compare mode: 1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. DS39632E-page 105

PIC18F2455/2550/4455/4550 9.4 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPPIE: Streaming Parallel Port Read/Write Interrupt Enable bit(1) 1 = Enables the SPP read/write interrupt 0 = Disables the SPP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear. DS39632E-page 106 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 USBIE: USB Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. DS39632E-page 107

PIC18F2455/2550/4455/4550 9.5 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPPIP: Streaming Parallel Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear. DS39632E-page 108 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 USBIP: USB Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. DS39632E-page 109

PIC18F2455/2550/4455/4550 9.6 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 9-10: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) For details of bit operation, see Register4-1. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register4-1. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register4-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register4-1. bit 1 POR: Power-on Reset Status bit(2) For details of bit operation, see Register4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register4-1. Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. See Register4-1 for additional information. 2: The actual Reset value of POR is determined by the type of device Reset. See Register4-1 for additional information. DS39632E-page 110 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 9.7 INTx Pin Interrupts 9.8 TMR0 Interrupt External interrupts on the RB0/AN12/INT0/FLT0/SDI/ In 8-bit mode (which is the default), an overflow in the SDA, RB1/AN10/INT1/SCK/SCL and RB2/AN8/INT2/ TMR0 register (FFh→00h) will set flag bit, TMR0IF. In VMO pins are edge-triggered. If the corresponding 16-bit mode, an overflow in the TMR0H:TMR0L regis- INTEDGx bit in the INTCON2 register is set (= 1), the ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt interrupt is triggered by a rising edge; if the bit is clear, can be enabled/disabled by setting/clearing enable bit, the trigger is on the falling edge. When a valid edge TMR0IE (INTCON<5>). Interrupt priority for Timer0 is appears on the RBx/INTx pin, the corresponding flag determined by the value contained in the interrupt bit, INTxIF, is set. This interrupt can be disabled by priority bit, TMR0IP (INTCON2<2>). See Section11.0 clearing the corresponding enable bit, INTxIE. Flag bit, “Timer0 Module” for further details on the Timer0 INTxIF, must be cleared in software in the Interrupt module. Service Routine before re-enabling the interrupt. 9.9 PORTB Interrupt-on-Change All external interrupts (INT0, INT1 and INT2) can wake- up the processor from the power-managed modes if bit, An input change on PORTB<7:4> sets flag bit, RBIF INTxIE, was set prior to going into the power-managed (INTCON<0>). The interrupt can be enabled/disabled modes. If the Global Interrupt Enable bit, GIE, is set, the by setting/clearing enable bit, RBIE (INTCON<3>). processor will branch to the interrupt vector following Interrupt priority for PORTB interrupt-on-change is wake-up. determined by the value contained in the interrupt Interrupt priority for INT1 and INT2 is determined by priority bit, RBIP (INTCON2<0>). the value contained in the interrupt priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). 9.10 Context Saving During Interrupts There is no priority bit associated with INT0. It is always a high-priority interrupt source. During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack. If a fast return from interrupt is not used (see Section5.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS © 2009 Microchip Technology Inc. DS39632E-page 111

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 112 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 10.0 I/O PORTS Reading the PORTA register reads the status of the pins; writing to it will write to the port latch. Depending on the device selected and features The Data Latch register (LATA) is also memory enabled, there are up to five ports available. Some pins mapped. Read-modify-write operations on the LATA of the I/O ports are multiplexed with an alternate register read and write the latched output value for function from the peripheral features on the device. In PORTA. general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA6 pin Each port has three registers for its operation. These is multiplexed with the main oscillator pin; it is enabled registers are: as an oscillator or I/O pin by the selection of the main • TRIS register (data direction register) oscillator in Configuration Register 1H (see • PORT register (reads the levels on the pins of the Section25.1 “Configuration Bits” for details). When device) not used as a port pin, RA6 and its associated TRIS • LAT register (output latch) and LAT bits are read as ‘0’. The Data Latch register (LATA) is useful for read- RA4 is also multiplexed with the USB module; it serves modify-write operations on the value driven by the I/O as a receiver input from an external USB transceiver. pins. For details on configuration of the USB module, see Section17.2 “USB Status and Control”. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure10-1. Several PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the comparator FIGURE 10-1: GENERIC I/O PORT voltage reference output. The operation of pins RA5 and RA3:RA0 as A/D converter inputs is selected by OPERATION clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). RD LAT Note: On a Power-on Reset, RA5 and RA3:RA0 Data are configured as analog inputs and read Bus D Q as ‘0’. RA4 is configured as a digital input. WR LAT I/O pin(1) All other PORTA pins have TTL input levels and full orPORT CK CMOS output drivers. Data Latch The TRISA register controls the direction of the RA D Q pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are WR TRIS CK maintained set when using them as analog inputs. TRIS Latch Input Buffer EXAMPLE 10-1: INITIALIZING PORTA RD TRIS CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches Q D CLRF LATA ; Alternate method ; to clear output ENEN ; data latches MOVLW 0Fh ; Configure A/D RD PORT MOVWF ADCON1 ; for digital inputs MOVLW 07h ; Configure comparators Note1: I/O pins have diode protection to VDD and VSS. MOVWF CMCON ; for digital input MOVLW 0CFh ; Value used to ; initialize data 10.1 PORTA, TRISA and LATA Registers ; direction MOVWF TRISA ; Set RA<3:0> as inputs PORTA is an 8-bit wide, bidirectional port. The corre- ; RA<5:4> as outputs sponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2009 Microchip Technology Inc. DS39632E-page 113

PIC18F2455/2550/4455/4550 TABLE 10-1: PORTA I/O SUMMARY TRIS Pin Function I/O I/O Type Description Setting RA0/AN0 RA0 0 OUT DIG LATA<0> data output; not affected by analog input. 1 IN TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 IN ANA A/D Input Channel 0 and Comparator C1- input. Default configuration on POR; does not affect digital output. RA1/AN1 RA1 0 OUT DIG LATA<1> data output; not affected by analog input. 1 IN TTL PORTA<1> data input; reads ‘0’ on POR. AN1 1 IN ANA A/D Input Channel 1 and Comparator C2- input. Default configuration on POR; does not affect digital output. RA2/AN2/ RA2 0 OUT DIG LATA<2> data output; not affected by analog input. Disabled when VREF-/CVREF CVREF output enabled. 1 IN TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. AN2 1 IN ANA A/D Input Channel 2 and Comparator C2+ input. Default configuration on POR; not affected by analog output. VREF- 1 IN ANA A/D and comparator voltage reference low input. CVREF x OUT ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RA3/AN3/ RA3 0 OUT DIG LATA<3> data output; not affected by analog input. VREF+ 1 IN TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 IN ANA A/D Input Channel 3 and Comparator C1+ input. Default configuration on POR. VREF+ 1 IN ANA A/D and comparator voltage reference high input. RA4/T0CKI/ RA4 0 OUT DIG LATA<4> data output; not affected by analog input. C1OUT/RCV 1 IN ST PORTA<4> data input; disabled when analog input enabled. T0CKI 1 IN ST Timer0 clock input. C1OUT 0 OUT DIG Comparator 1 output; takes priority over port data. RCV x IN TTL External USB transceiver RCV input. RA5/AN4/SS/ RA5 0 OUT DIG LATA<5> data output; not affected by analog input. HLVDIN/C2OUT 1 IN TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 IN ANA A/D Input Channel 4. Default configuration on POR. SS 1 IN TTL Slave select input for MSSP module. HLVDIN 1 IN ANA High/Low-Voltage Detect external trip point input. C2OUT 0 OUT DIG Comparator 2 output; takes priority over port data. OSC2/CLKO/ OSC2 x OUT ANA Main oscillator feedback output connection (all XT and HS modes). RA6 CLKO x OUT DIG System cycle clock output (FOSC/4); available in EC, ECPLL and INTCKO modes. RA6 0 OUT DIG LATA<6> data output. Available only in ECIO, ECPIO and INTIO modes; otherwise, reads as ‘0’. 1 IN TTL PORTA<6> data input. Available only in ECIO, ECPIO and INTIO modes; otherwise, reads as ‘0’. Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) DS39632E-page 114 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTA — RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 56 LATA — LATA6(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 56 TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 55 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 55 UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2009 Microchip Technology Inc. DS39632E-page 115

PIC18F2455/2550/4455/4550 10.2 PORTB, TRISB and LATB A mismatch condition will continue to set flag bit, RBIF. Registers Reading PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared after a one TCY delay. PORTB is an 8-bit wide, bidirectional port. The corre- The interrupt-on-change feature is recommended for sponding Data Direction register is TRISB. Setting a wake-up on key depression operation and operations TRISB bit (= 1) will make the corresponding PORTB where PORTB is only used for the interrupt-on-change pin an input (i.e., put the corresponding output driver in feature. Polling of PORTB is not recommended while a high-impedance mode). Clearing a TRISB bit (= 0) using the interrupt-on-change feature. will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Pins, RB2 and RB3, are multiplexed with the USB peripheral and serve as the differential signal outputs The Data Latch register (LATB) is also memory for an external USB transceiver (TRIS configuration). mapped. Read-modify-write operations on the LATB Refer to Section17.2.2.2 “External Transceiver” for register read and write the latched output value for additional information on configuring the USB module PORTB. for operation with an external transceiver. Each of the PORTB pins has a weak internal pull-up. A RB4 is multiplexed with CSSPP, the chip select single control bit can turn on all the pull-ups. This is function for the Streaming Parallel Port (SPP) – TRIS performed by clearing bit, RBPU (INTCON2<7>). The setting. Details of its operation are discussed in weak pull-up is automatically turned off when the port Section18.0 “Streaming Parallel Port”. pin is configured as an output. The pull-ups are disabled on a Power-on Reset. EXAMPLE 10-2: INITIALIZING PORTB Note: On a Power-on Reset, RB4:RB0 are CLRF PORTB ; Initialize PORTB by configured as analog inputs by default and ; clearing output read as ‘0’; RB7:RB5 are configured as ; data latches digital inputs. CLRF LATB ; Alternate method ; to clear output By programming the Configuration bit, ; data latches PBADEN (CONFIG3H<1>), RB4:RB0 will MOVLW 0Eh ; Set RB<4:0> as alternatively be configured as digital inputs MOVWF ADCON1 ; digital I/O pins on POR. ; (required if config bit ; PBADEN is set) Four of the PORTB pins (RB7:RB4) have an interrupt- MOVLW 0CFh ; Value used to on-change feature. Only pins configured as inputs can ; initialize data cause this interrupt to occur. Any RB7:RB4 pin ; direction configured as an output is excluded from the interrupt- MOVWF TRISB ; Set RB<3:0> as inputs on-change comparison. The pins are compared with ; RB<5:4> as outputs the old value latched on the last read of PORTB. The ; RB<7:6> as inputs “mismatch” outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). The interrupt-on-change can be used to wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). This will end the mismatch condition. b) Wait one TCY delay (for example, execute one NOP instruction). c) Clear flag bit, RBIF DS39632E-page 116 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 10-3: PORTB I/O SUMMARY TRIS Pin Function I/O I/O Type Description Setting RB0/AN12/ RB0 0 OUT DIG LATB<0> data output; not affected by analog input. INT0/FLT0/ 1 IN TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. SDI/SDA Disabled when analog input enabled.(1) AN12 1 IN ANA A/D Input Channel 12.(1) INT0 1 IN ST External Interrupt 0 input. FLT0 1 IN ST Enhanced PWM Fault input (ECCP1 module); enabled in software. SDI 1 IN ST SPI data input (MSSP module). SDA 1 OUT DIG I2C™ data output (MSSP module); takes priority over port data. 1 IN I2C/SMB I2C data input (MSSP module); input type depends on module setting. RB1/AN10/ RB1 0 OUT DIG LATB<1> data output; not affected by analog input. INT1/SCK/ 1 IN TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. SCL Disabled when analog input enabled.(1) AN10 1 IN ANA A/D Input Channel 10.(1) INT1 1 IN ST External Interrupt 1 input. SCK 0 OUT DIG SPI clock output (MSSP module); takes priority over port data. 1 IN ST SPI clock input (MSSP module). SCL 0 OUT DIG I2C clock output (MSSP module); takes priority over port data. 1 IN I2C/SMB I2C clock input (MSSP module); input type depends on module setting. RB2/AN8/ RB2 0 OUT DIG LATB<2> data output; not affected by analog input. INT2/VMO 1 IN TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) AN8 1 IN ANA A/D input channel 8.(1) INT2 1 IN ST External Interrupt 2 input. VMO 0 OUT DIG External USB transceiver VMO data output. RB3/AN9/ RB3 0 OUT DIG LATB<3> data output; not affected by analog input. CCP2/VPO 1 IN TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) AN9 1 IN ANA A/D Input Channel 9.(1) CCP2(2) 0 OUT DIG CCP2 compare and PWM output. 1 IN ST CCP2 capture input. VPO 0 OUT DIG External USB transceiver VPO data output. RB4/AN11/ RB4 0 OUT DIG LATB<4> data output; not affected by analog input. KBI0/CSSPP 1 IN TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) AN11 1 IN ANA A/D Input Channel 11.(1) KBI0 1 IN TTL Interrupt-on-pin change. CSSPP(4) 0 OUT DIG SPP chip select control output. RB5/KBI1/ RB5 0 OUT DIG LATB<5> data output. PGM 1 IN TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 IN TTL Interrupt-on-pin change. PGM x IN ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP Configuration bit; all other pin functions disabled. Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, I2C/SMB = I2C/SMBus input buffer, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1. 3: All other pin functions are disabled when ICSP™ or ICD operation is enabled. 4: 40/44-pin devices only. © 2009 Microchip Technology Inc. DS39632E-page 117

PIC18F2455/2550/4455/4550 TABLE 10-3: PORTB I/O SUMMARY (CONTINUED) TRIS Pin Function I/O I/O Type Description Setting RB6/KBI2/ RB6 0 OUT DIG LATB<6> data output. PGC 1 IN TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 IN TTL Interrupt-on-pin change. PGC x IN ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(3) RB7/KBI3/ RB7 0 OUT DIG LATB<7> data output. PGD 1 IN TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 IN TTL Interrupt-on-pin change. PGD x OUT DIG Serial execution data output for ICSP and ICD operation.(3) x IN ST Serial execution data input for ICSP and ICD operation.(3) Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, I2C/SMB = I2C/SMBus input buffer, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1. 3: All other pin functions are disabled when ICSP™ or ICD operation is enabled. 4: 40/44-pin devices only. TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 56 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 56 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 53 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 53 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54 SPPCON(1) — — — — — — SPPOWN SPPEN 57 SPPCFG(1) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 57 UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. Note 1: These registers are unimplemented on 28-pin devices. DS39632E-page 118 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 10.3 PORTC, TRISC and LATC When enabling peripheral functions on PORTC pins Registers other than RC4 and RC5, care should be taken in defin- ing the TRIS bits. Some peripherals override the TRIS PORTC is a 7-bit wide, bidirectional port. The corre- bit to make a pin an output, while other peripherals sponding Data Direction register is TRISC. Setting a override the TRIS bit to make a pin an input. The user TRISC bit (= 1) will make the corresponding PORTC should refer to the corresponding peripheral section for pin an input (i.e., put the corresponding output driver in the correct TRIS bit settings. a high-impedance mode). Clearing a TRISC bit (= 0) Note: On a Power-on Reset, these pins, except will make the corresponding PORTC pin an output (i.e., RC4 and RC5, are configured as digital put the contents of the output latch on the selected pin). inputs. To use pins RC4 and RC5 as The RC3 pin is not implemented in these devices. digital inputs, the USB module must be The Data Latch register (LATC) is also memory disabled (UCON<3> = 0) and the on-chip mapped. Read-modify-write operations on the LATC USB transceiver must be disabled register read and write the latched output value for (UCFG<3> = 1). PORTC. The contents of the TRISC register are affected by PORTC is primarily multiplexed with serial communica- peripheral overrides. Reading TRISC always returns tion modules, including the EUSART, MSSP module the current contents, even though a peripheral device and the USB module (Table10-5). Except for RC4 and may be overriding one or more of the pins. RC5, PORTC uses Schmitt Trigger input buffers. Pins RC4 and RC5 are multiplexed with the USB EXAMPLE 10-3: INITIALIZING PORTC module. Depending on the configuration of the module, CLRF PORTC ; Initialize PORTC by they can serve as the differential data lines for the on- ; clearing output chip USB transceiver, or the data inputs from an ; data latches external USB transceiver. Both RC4 and RC5 have CLRF LATC ; Alternate method TTL input buffers instead of the Schmitt Trigger buffers ; to clear output on the other pins. ; data latches MOVLW 07h ; Value used to Unlike other PORTC pins, RC4 and RC5 do not have ; initialize data TRISC bits associated with them. As digital ports, they ; direction can only function as digital inputs. When configured for MOVWF TRISC ; RC<5:0> as outputs USB operation, the data direction is determined by the ; RC<7:6> as inputs configuration and status of the USB module at a given time. If an external transceiver is used, RC4 and RC5 always function as inputs from the transceiver. If the on-chip transceiver is used, the data direction is determined by the operation being performed by the module at that time. When the external transceiver is enabled, RC2 also serves as the output enable control to the transceiver. Additional information on configuring USB options is provided in Section17.2.2.2 “External Transceiver”. © 2009 Microchip Technology Inc. DS39632E-page 119

PIC18F2455/2550/4455/4550 TABLE 10-5: PORTC I/O SUMMARY TRIS Pin Function I/O I/O Type Description Setting RC0/T1OSO/ RC0 0 OUT DIG LATC<0> data output. T13CKI 1 IN ST PORTC<0> data input. T1OSO x OUT ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T13CKI 1 IN ST Timer1/Timer3 counter input. RC1/T1OSI/ RC1 0 OUT DIG LATC<1> data output. CCP2/UOE 1 IN ST PORTC<1> data input. T1OSI x IN ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. CCP2(1) 0 OUT DIG CCP2 compare and PWM output; takes priority over port data. 1 IN ST CCP2 capture input. UOE 0 OUT DIG External USB transceiver OE output. RC2/CCP1/ RC2 0 OUT DIG LATC<2> data output. P1A 1 IN ST PORTC<2> data input. CCP1 0 OUT DIG ECCP1 compare and PWM output; takes priority over port data. 1 IN ST ECCP1 capture input. P1A(3) 0 OUT DIG ECCP1 Enhanced PWM output, Channel A; takes priority over port data. May be configured for tri-state during Enhanced PWM shutdown events. RC4/D-/VM RC4 —(2) IN TTL PORTC<4> data input; disabled when USB module or on-chip transceiver are enabled. D- —(2) OUT XCVR USB bus differential minus line output (internal transceiver). —(2) IN XCVR USB bus differential minus line input (internal transceiver). VM —(2) IN TTL External USB transceiver VM input. RC5/D+/VP RC5 —(2) IN TTL PORTC<5> data input; disabled when USB module or on-chip transceiver are enabled. D+ —(2) OUT XCVR USB bus differential plus line output (internal transceiver). —(2) IN XCVR USB bus differential plus line input (internal transceiver). VP —(2) IN TTL External USB transceiver VP input. RC6/TX/CK RC6 0 OUT DIG LATC<6> data output. 1 IN ST PORTC<6> data input. TX 0 OUT DIG Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as output. CK 0 OUT DIG Synchronous serial clock output (EUSART module); takes priority over port data. 1 IN ST Synchronous serial clock input (EUSART module). Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, XCVR = USB transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Default pin assignment. Alternate pin assignment is RB3 (when CCP2MX = 0). 2: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is determined by the USB configuration. 3: 40/44-pin devices only. DS39632E-page 120 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 10-5: PORTC I/O SUMMARY (CONTINUED) TRIS Pin Function I/O I/O Type Description Setting RC7/RX/DT/ RC7 0 OUT DIG LATC<7> data output. SDO 1 IN ST PORTC<7> data input. RX 1 IN ST Asynchronous serial receive data input (EUSART module). DT 1 OUT DIG Synchronous serial data output (EUSART module); takes priority over SPI and port data. 1 IN ST Synchronous serial data input (EUSART module). User must configure as an input. SDO 0 OUT DIG SPI data output (MSSP module); takes priority over port data. Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, XCVR = USB transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Default pin assignment. Alternate pin assignment is RB3 (when CCP2MX = 0). 2: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is determined by the USB configuration. 3: 40/44-pin devices only. TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTC RC7 RC6 RC5(1) RC4(1) — RC2 RC1 RC0 56 LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 56 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56 UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC. Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3>=0). © 2009 Microchip Technology Inc. DS39632E-page 121

PIC18F2455/2550/4455/4550 10.4 PORTD, TRISD and LATD PORTD can also be configured as an 8-bit wide Registers Streaming Parallel Port (SPP). In this mode, the input buffers are TTL. For additional information on con- Note: PORTD is only available on 40/44-pin figuration and uses of the SPP, see Section18.0 devices. “Streaming Parallel Port”. PORTD is an 8-bit wide, bidirectional port. The corre- Note: When the Enhanced PWM mode is used sponding Data Direction register is TRISD. Setting a with either dual or quad outputs, the MSSP TRISD bit (= 1) will make the corresponding PORTD functions of PORTD are automatically pin an input (i.e., put the corresponding output driver in disabled. a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., EXAMPLE 10-4: INITIALIZING PORTD put the contents of the output latch on the selected pin). CLRF PORTD ; Initialize PORTD by The Data Latch register (LATD) is also memory ; clearing output mapped. Read-modify-write operations on the LATD ; data latches register read and write the latched output value for CLRF LATD ; Alternate method ; to clear output PORTD. ; data latches All pins on PORTD are implemented with Schmitt MOVLW 0CFh ; Value used to Trigger input buffers. Each pin is individually ; initialize data configurable as an input or output. ; direction MOVWF TRISD ; Set RD<3:0> as inputs Each of the PORTD pins has a weak internal pull-up. A ; RD<5:4> as outputs single control bit, RDPU (PORTE<7>), can turn on all ; RD<7:6> as inputs the pull-ups. This is performed by setting RDPU. The weak pull-up is automatically turned off when the port pin is configured as a digital output or as one of the other multiplexed peripherals. The pull-ups are disabled on a Power-on Reset. The PORTE register is shown in Section10.5 “PORTE, TRISE and LATE Registers”. Three of the PORTD pins are multiplexed with outputs, P1B, P1C and P1D, of the Enhanced CCP module. The operation of these additional PWM output pins is covered in greater detail in Section16.0 “Enhanced Capture/Compare/PWM (ECCP) Module”. Note: On a Power-on Reset, these pins are configured as digital inputs. DS39632E-page 122 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 10-7: PORTD I/O SUMMARY TRIS Pin Function I/O I/O Type Description Setting RD0/SPP0 RD0 0 OUT DIG LATD<0> data output. 1 IN ST PORTD<0> data input. SPP0 1 OUT DIG SPP<0> output data; takes priority over port data. 1 IN TTL SPP<0> input data. RD1/SPP1 RD1 0 OUT DIG LATD<1> data output. 1 IN ST PORTD<1> data input. SPP1 1 OUT DIG SPP<1> output data; takes priority over port data. 1 IN TTL SPP<1> input data. RD2/SPP2 RD2 0 OUT DIG LATD<2> data output. 1 IN ST PORTD<2> data input. SPP2 1 OUT DIG SPP<2> output data; takes priority over port data. 1 IN TTL SPP<2> input data. RD3/SPP3 RD3 0 OUT DIG LATD<3> data output. 1 IN ST PORTD<3> data input. SPP3 1 OUT DIG SPP<3> output data; takes priority over port data. 1 IN TTL SPP<3> input data. RD4/SPP4 RD4 0 OUT DIG LATD<4> data output. 1 IN ST PORTD<4> data input. SPP4 1 OUT DIG SPP<4> output data; takes priority over port data. 1 IN TTL SPP<4> input data. RD5/SPP5/P1B RD5 0 OUT DIG LATD<5> data output 1 IN ST PORTD<5> data input SPP5 1 OUT DIG SPP<5> output data; takes priority over port data. 1 IN TTL SPP<5> input data. P1B 0 OUT DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and SPP data.(1) RD6/SPP6/P1C RD6 0 OUT DIG LATD<6> data output. 1 IN ST PORTD<6> data input. SPP6 1 OUT DIG SPP<6> output data; takes priority over port data. 1 IN TTL SPP<6> input data. P1C 0 OUT DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and SPP data.(1) RD7/SPP7/P1D RD7 0 OUT DIG LATD<7> data output. 1 IN ST PORTD<7> data input. SPP7 1 OUT DIG SPP<7> output data; takes priority over port data. 1 IN TTL SPP<7> input data. P1D 0 OUT DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and SPP data.(1) Legend: OUT = Output, IN = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input Note 1: May be configured for tri-state during Enhanced PWM shutdown events. © 2009 Microchip Technology Inc. DS39632E-page 123

PIC18F2455/2550/4455/4550 TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 56 LATD(3) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 56 TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56 PORTE RDPU(3) — — — RE3(1,2) RE2(3) RE1(3) RE0(3) 56 CCP1CON P1M1(3) P1M0(3) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 55 SPPCON(3) — — — — — — SPPOWN SPPEN 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). 3: These registers and/or bits are unimplemented on 28-pin devices. DS39632E-page 124 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 10.5 PORTE, TRISE and LATE The fourth pin of PORTE (MCLR/VPP/RE3) is an input Registers only pin. Its operation is controlled by the MCLRE Config- uration bit. When selected as a port pin (MCLRE=0), it Depending on the particular PIC18F2455/2550/4455/ functions as a digital input only pin; as such, it does not 4550 device selected, PORTE is implemented in two have TRIS or LAT bits associated with its operation. different ways. Otherwise, it functions as the device’s Master Clear input. In either configuration, RE3 also functions as the For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/AN5/CK1SPP, RE1/AN6/CK2SPP programming voltage input during programming. and RE2/AN7/OESPP) are individually configurable as Note: On a Power-on Reset, RE3 is enabled as inputs or outputs. These pins have Schmitt Trigger a digital input only if Master Clear input buffers. When selected as an analog input, these functionality is disabled. pins will read as ‘0’s. The corresponding Data Direction register is TRISE. EXAMPLE 10-5: INITIALIZING PORTE Setting a TRISE bit (= 1) will make the corresponding CLRF PORTE ; Initialize PORTE by PORTE pin an input (i.e., put the corresponding output ; clearing output driver in a high-impedance mode). Clearing a TRISE bit ; data latches (= 0) will make the corresponding PORTE pin an output CLRF LATE ; Alternate method (i.e., put the contents of the output latch on the selected ; to clear output pin). ; data latches MOVLW 0Ah ; Configure A/D In addition to port data, the PORTE register MOVWF ADCON1 ; for digital inputs (Register10-1) also contains the RDPU control bit MOVLW 03h ; Value used to (PORTE<7>); this enables or disables the weak ; initialize data pull-ups on PORTD. ; direction MOVLW 07h ; Turn off TRISE controls the direction of the RE pins, even when MOVWF CMCON ; comparators they are being used as analog inputs. The user must MOVWF TRISC ; Set RE<0> as inputs make sure to keep the pins configured as inputs when ; RE<1> as outputs using them as analog inputs. ; RE<2> as inputs Note: On a Power-on Reset, RE2:RE0 are 10.5.1 PORTE IN 28-PIN DEVICES configured as analog inputs. For 28-pin devices, PORTE is only available when Mas- The Data Latch register (LATE) is also memory ter Clear functionality is disabled (MCLRE=0). In these mapped. Read-modify-write operations on the LATE cases, PORTE is a single bit, input only port comprised register read and write the latched output value for of RE3 only. The pin operates as previously described. PORTE. REGISTER 10-1: PORTE REGISTER R/W-0 U-0 U-0 U-0 R/W-x R/W-0 R/W-0 R/W-0 RDPU(3) — — — RE3(1,2) RE2(3) RE1(3) RE0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RDPU: PORTD Pull-up Enable bit 1 = PORTD pull-ups are enabled by individual port latch values 0 = All PORTD pull-ups are disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3-0 RE3:RE0: PORTE Data Input bits(1,2,3) Note 1: implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise, read as ‘0’. 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). 3: Unimplemented in 28-pin devices; read as ‘0’. © 2009 Microchip Technology Inc. DS39632E-page 125

PIC18F2455/2550/4455/4550 TABLE 10-9: PORTE I/O SUMMARY TRIS Pin Function I/O I/O Type Description Setting RE0/AN5/ RE0 0 OUT DIG LATE<0> data output; not affected by analog input. CK1SPP 1 IN ST PORTE<0> data input; disabled when analog input enabled. AN5 1 IN ANA A/D Input Channel 5; default configuration on POR. CK1SPP 0 OUT DIG SPP clock 1 output (SPP enabled). RE1/AN6/ RE1 0 OUT DIG LATE<1> data output; not affected by analog input. CK2SPP 1 IN ST PORTE<1> data input; disabled when analog input enabled. AN6 1 IN ANA A/D Input Channel 6; default configuration on POR. CK2SPP 0 OUT DIG SPP clock 2 output (SPP enabled). RE2/AN7/ RE2 0 OUT DIG LATE<2> data output; not affected by analog input. OESPP 1 IN ST PORTE<2> data input; disabled when analog input enabled. AN7 1 IN ANA A/D Input Channel 7; default configuration on POR. OESPP 0 OUT DIG SPP enable output (SPP enabled). MCLR/VPP/ MCLR —(1) IN ST External Master Clear input; enabled when MCLRE Configuration bit RE3 is set. VPP — (1) IN ANA High-voltage detection, used for ICSP™ mode entry detection. Always available regardless of pin mode. RE3 — (1) IN ST PORTE<3> data input; enabled when MCLRE Configuration bit is clear. Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input Note 1: RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode. TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTE RDPU(3) — — — RE3(1,2) RE2(3) RE1(3) RE0(3) 56 LATE(3) — — — — — LATE2 LATE1 LATE0 56 TRISE(3) — — — — — TRISE2 TRISE1 TRISE0 56 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 55 SPPCON(3) — — — — — — SPPOWN SPPEN 57 SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). 3: These registers or bits are unimplemented on 28-pin devices. DS39632E-page 126 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 11.0 TIMER0 MODULE The T0CON register (Register11-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or coun- A simplified block diagram of the Timer0 module in 8-bit ter in both 8-bit or 16-bit modes mode is shown in Figure11-1. Figure11-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt on overflow REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. DS39632E-page 127

PIC18F2455/2550/4455/4550 11.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter; the timer/counter. mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode, the module increments 11.2 Timer0 Reads and Writes in on every clock by default unless a different prescaler 16-Bit Mode value is selected (see Section11.3 “Prescaler”). If the TMR0 register is written to, the increment is TMR0H is not the actual high byte of Timer0 in 16-bit inhibited for the following two instruction cycles. The mode. It is actually a buffered version of the real high user can work around this by writing an adjusted value byte of Timer0 which is not directly readable nor to the TMR0 register. writable (refer to Figure11-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of The Counter mode is selected by setting the T0CS bit TMR0L. This provides the ability to read all 16 bits of (= 1). In Counter mode, Timer0 increments either on Timer0 without having to verify that the read of the high every rising or falling edge of pin RA4/T0CKI/C1OUT/ and low byte were valid, due to a rollover between RCV. The incrementing edge is determined by the successive reads of the high and low byte. Timer0 Source Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on Similarly, a write to the high byte of Timer0 must also the external clock input are discussed below. take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a An external clock source can be used to drive Timer0; write occurs to TMR0L. This allows all 16 bits of Timer0 however, it must meet certain requirements to ensure to be updated at once. that the external clock can be synchronized with the FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) 8 T0CS 3 T0PS2:T0PS0 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L HTigMh RB0yte TMR0IF T0CKI pin Programmable 0 Clocks 8 on Overflow Prescaler T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS2:T0PS0 Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. DS39632E-page 128 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 11.3 Prescaler 11.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software its value is set by the PSA and T0PS2:T0PS0 bits control and can be changed “on-the-fly” during program (T0CON<3:0>) which determine the prescaler execution. assignment and prescale ratio. 11.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0 from 1:2 through 1:256, in power-of-2 increments, are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before re- TMR0, BSF TMR0,etc.) clear the prescaler count. enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TMR0L Timer0 Register Low Byte 54 TMR0H Timer0 Register High Byte 54 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 53 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 54 TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56 Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. © 2009 Microchip Technology Inc. DS39632E-page 129

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 130 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 12.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is shown in Figure12-1. A block diagram of the module’s The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure12-2. features: The module incorporates its own low-power oscillator • Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1 counter oscillator can also be used as a low-power clock source • Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation. and TMR1L) Timer1 can also be used to provide Real-Time Clock • Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal device clock or Timer1 oscillator internal options addition of external components and code overhead. • Interrupt on overflow Timer1 is controlled through the T1CON Control • Module Reset on CCP Special Event Trigger register (Register12-1). It also contains the Timer1 • Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 =Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from RC0/T1OSO/T13CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. DS39632E-page 131

PIC18F2455/2550/4455/4550 12.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled. • Timer When Timer1 is enabled, the RC1/T1OSI/UOE and • Synchronous Counter RC0/T1OSO/T13CKI pins become inputs. This means • Asynchronous Counter the values of TRISC<1:0> are ignored and the pins are read as ‘0’. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator On/Off 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 On/Off T1CKPS1:T1CKPS0 T1SYNC TMR1ON Clear TMR1 TMR1L HTigMh RB1yte STMetR 1IF (CCP Special Event Trigger) on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 T1CKPS1:T1CKPS0 On/Off T1SYNC TMR1ON Clear TMR1 TMR1L HTigMh RB1yte STMetR 1IF (CCP Special Event Trigger) on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39632E-page 132 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 12.2 Timer1 16-Bit Read/Write Mode TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(2,3,4) Timer1 can be configured for 16-bit reads and writes (see Figure12-2). When the RD16 control bit Osc Type Freq C1 C2 (T1CON<7>) is set, the address for TMR1H is mapped LP 32kHz 27pF(1) 27pF(1) to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Note1: Microchip suggests these values as a Timer1 into the Timer1 high byte buffer. This provides starting point in validating the oscillator the user with the ability to accurately read all 16 bits of circuit. Timer1 without having to determine whether a read of 2: Higher capacitance increases the stability the high byte, followed by a read of the low byte, has of the oscillator but also increases the become invalid due to a rollover between reads. start-up time. A write to the high byte of Timer1 must also take place 3: Since each resonator/crystal has its own through the TMR1H Buffer register. The Timer1 high characteristics, the user should consult byte is updated with the contents of TMR1H when a the resonator/crystal manufacturer for write occurs to TMR1L. This allows a user to write all appropriate values of external 16 bits to both the high and low bytes of Timer1 at once. components. The high byte of Timer1 is not directly readable or 4: Capacitor values are for design guidance writable in this mode. All reads and writes must take only. place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. 12.3.1 USING TIMER1 AS A CLOCK The prescaler is only cleared on writes to TMR1L. SOURCE The Timer1 oscillator is also available as a clock source 12.3 Timer1 Oscillator in power-managed modes. By setting the clock select An on-chip crystal oscillator circuit is incorporated bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device between pins T1OSI (input) and T1OSO (amplifier switches to SEC_RUN mode. Both the CPU and output). It is enabled by setting the Timer1 Oscillator peripherals are clocked from the Timer1 oscillator. If the Enable bit, T1OSCEN (T1CON<3>). The oscillator is a IDLEN bit (OSCCON<7>) is cleared and a SLEEP low-power circuit rated for 32kHz crystals. It will instruction is executed, the device enters SEC_IDLE continue to run during all power-managed modes. The mode. Additional details are available in Section3.0 circuit for a typical LP oscillator is shown in Figure12-3. “Power-Managed Modes”. Table12-1 shows the capacitor selection for the Timer1 Whenever the Timer1 oscillator is providing the clock oscillator. source, the Timer1 system clock status flag, T1RUN The user must provide a software time delay to ensure (T1CON<6>), is set. This can be used to determine the proper start-up of the Timer1 oscillator. controller’s current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe FIGURE 12-3: EXTERNAL Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock, polling COMPONENTS FOR THE the T1RUN bit will indicate whether the clock is being TIMER1 LP OSCILLATOR provided by the Timer1 oscillator or another source. C1 PIC18FXXXX 27 pF 12.3.2 LOW-POWER TIMER1 OPTION T1OSI The Timer1 oscillator can operate at two distinct levels of power consumption based on device configuration. XTAL When the LPT1OSC Configuration bit is set, the Timer1 32.768 kHz oscillator operates in a low-power mode. When LPT1OSC is not set, Timer1 operates at a higher power T1OSO level. Power consumption for a particular mode is rela- C2 tively constant, regardless of the device’s operating 27 pF mode. The default Timer1 configuration is the higher Note: See the notes with Table12-1 for additional power mode. information about capacitor selection. As the low-power Timer1 mode tends to be more sensitive to interference, high noise environments may cause some oscillator instability. The low-power option is, therefore, best suited for low noise applications where power conservation is an important design consideration. © 2009 Microchip Technology Inc. DS39632E-page 133

PIC18F2455/2550/4455/4550 12.3.3 TIMER1 OSCILLATOR LAYOUT 12.5 Resetting Timer1 Using the CCP CONSIDERATIONS Special Event Trigger The Timer1 oscillator circuit draws very little power If either of the CCP modules is configured in Compare during operation. Due to the low-power nature of the mode to generate a Special Event Trigger oscillator, it may also be sensitive to rapidly changing (CCP1M3:CCP1M0 or CCP2M3:CCP2M0=1011), signals in close proximity. this signal will reset Timer1. The trigger from CCP2 will The oscillator circuit, shown in Figure12-3, should be also start an A/D conversion if the A/D module is located as close as possible to the microcontroller. enabled (see Section15.3.4 “Special Event Trigger” There should be no circuits passing within the oscillator for more information). circuit boundaries other than VSS or VDD. The module must be configured as either a timer or a If a high-speed circuit must be located near the oscilla- synchronous counter to take advantage of this feature. tor (such as the CCP1 pin in Output Compare or PWM When used this way, the CCPRH:CCPRL register pair mode, or the primary oscillator using the OSC2 pin), a effectively becomes a period register for Timer1. grounded guard ring around the oscillator circuit, as If Timer1 is running in Asynchronous Counter mode, shown in Figure12-4, may be helpful when used on a this Reset operation may not work. single-sided PCB or in addition to a ground plane. In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take FIGURE 12-4: OSCILLATOR CIRCUIT precedence. WITH GROUNDED GUARD RING Note: The Special Event Triggers from the CCP2 module will not set the TMR1IF interrupt VDD flag bit (PIR1<0>). VSS 12.6 Using Timer1 as a Real-Time Clock OSC1 Adding an external LP oscillator to Timer1 (such as the OSC2 one described in Section12.3 “Timer1 Oscillator”) gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time RC0 base and several lines of application code to calculate the time. When operating in Sleep mode and using a RC1 battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. RC2 The application code routine, RTCisr, shown in Note: Not drawn to scale. Example12-1, demonstrates a simple method to increment a counter at one-second intervals using an 12.4 Timer1 Interrupt Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls The TMR1 register pair (TMR1H:TMR1L) increments the routine, which increments the seconds counter by from 0000h to FFFFh and rolls over to 0000h. The one. Additional counters for minutes and hours are Timer1 interrupt, if enabled, is generated on overflow incremented as the previous counter overflows. which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled Since the register pair is 16 bits wide, counting up to by setting or clearing the Timer1 Interrupt Enable bit, overflow the register directly from a 32.768kHz clock TMR1IE (PIE1<0>). would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to pre- load it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1) as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. DS39632E-page 134 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 12.7 Considerations in Asynchronous following a later Timer1 increment. This can be done Counter Mode by monitoring TMR1L within the interrupt routine until it increments, and then updating the TMR1H:TMR1L reg- Following a Timer1 interrupt and an update to the ister pair while the clock is low, or one-half of the period TMR1 registers, the Timer1 module uses a falling edge of the clock source. Assuming that Timer1 is being on its clock source to trigger the next register update on used as a Real-Time Clock, the clock source is a the rising edge. If the update is completed after the 32.768kHz crystal oscillator; in this case, one-half clock input has fallen, the next rising edge will not be period of the clock is 15.25μs. counted. The Real-Time Clock application code in Example12-1 If the application can reliably update TMR1 before the shows a typical ISR for Timer1, as well as the optional timer input goes low, no additional action is needed. code required if the update cannot be done reliably Otherwise, an adjusted update can be performed within the required interval. EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr ; Insert the next 4 lines of code when TMR1 ; can not be reliably updated before clock pulse goes low BTFSC TMR1L,0 ; wait for TMR1L to become clear BRA $-2 ; (may already be clear) BTFSS TMR1L,0 ; wait for TMR1L to become set BRA $-2 ; TMR1 has just incremented ; If TMR1 update can be completed before clock pulse goes low ; Start ISR here BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done CLRF hours ; Reset hours RETURN ; Done © 2009 Microchip Technology Inc. DS39632E-page 135

PIC18F2455/2550/4455/4550 TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 TMR1L Timer1 Register Low Byte 54 TMR1H TImer1 Register High Byte 54 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. DS39632E-page 136 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 13.0 TIMER2 MODULE 13.1 Timer2 Operation The Timer2 module timer incorporates the following In normal operation, TMR2 is incremented from 00h on features: each clock (FOSC/4). A 2-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by- • 8-bit Timer and Period registers (TMR2 and PR2, 16 prescale options. These are selected by the prescaler respectively) control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The • Readable and writable (both registers) value of TMR2 is compared to that of the Period register, • Software programmable prescaler (1:1, 1:4 and PR2, on each clock cycle. When the two values match, 1:16) the comparator generates a match signal as the timer • Software programmable postscaler (1:1 through output. This signal also resets the value of TMR2 to 00h 1:16) on the next cycle and drives the output counter/post- • Interrupt on TMR2 to PR2 match scaler (see Section13.2 “Timer2 Interrupt”). • Optional use as the shift clock for the MSSP The TMR2 and PR2 registers are both directly readable module and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. The module is controlled through the T2CON register Both the prescaler and postscaler counters are cleared (Register13-1) which enables or disables the timer and on the following events: configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), • a write to the TMR2 register to minimize power consumption. • a write to the T2CON register A simplified block diagram of the module is shown in • any device Reset (Power-on Reset, MCLR Reset, Figure13-1. Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 © 2009 Microchip Technology Inc. DS39632E-page 137

PIC18F2455/2550/4455/4550 13.2 Timer2 Interrupt 13.3 TMR2 Output Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2 to PR2 match) pro- the CCP modules, where it is used as a time base for vides the input for the 4-bit output counter/postscaler. operations in PWM mode. This counter generates the TMR2 match interrupt flag Timer2 can be optionally used as the shift clock source which is latched in TMR2IF (PIR1<1>). The interrupt is for the MSSP module operating in SPI mode. enabled by setting the TMR2 Match Interrupt Enable Additional information is provided in Section19.0 bit, TMR2IE (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>). FIGURE 13-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS3:T2OUTPS0 Set TMR2IF Postscaler 2 T2CKPS1:T2CKPS0 TMR2 Output (to PWM or MSSP) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 TMR2 Timer2 Register 54 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 54 PR2 Timer2 Period Register 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. DS39632E-page 138 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 14.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure14-1. A block diagram of the module’s The Timer3 module timer/counter incorporates these operation in Read/Write mode is shown in Figure14-2. features: The Timer3 module is controlled through the T3CON • Software selectable operation as a 16-bit timer or register (Register14-1). It also selects the clock source counter options for the CCP modules (see Section15.1.1 • Readable and writable 8-bit registers (TMR3H “CCP Modules and Timer Resources” for more and TMR3L) information). • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt on overflow • Module Reset on CCP Special Event Trigger REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 1x = Timer3 is the capture/compare clock source for both CCP modules 01 = Timer3 is the capture/compare clock source for CCP2; Timer1 is the capture/compare clock source for CCP1 00 = Timer1 is the capture/compare clock source for both CCP modules bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. DS39632E-page 139

PIC18F2455/2550/4455/4550 14.1 Timer3 Operation cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input Timer3 can operate in one of three modes: or the Timer1 oscillator, if enabled. • Timer As with Timer1, the RC1/T1OSI/UOE and RC0/ • Synchronous Counter T1OSO/T13CKI pins become inputs when the Timer1 • Asynchronous Counter oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 14-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 On/Off T3CKPS1:T3CKPS0 T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set CCP1/CCP2 Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 T3CKPS1:T3CKPS0 On/Off T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set CCP1/CCP2 Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39632E-page 140 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 14.2 Timer3 16-Bit Read/Write Mode 14.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes The TMR3 register pair (TMR3H:TMR3L) increments (see Figure14-2). When the RD16 control bit from 0000h to FFFFh and overflows to 0000h. The (T3CON<7>) is set, the address for TMR3H is mapped Timer3 interrupt, if enabled, is generated on overflow to a buffer register for the high byte of Timer3. A read and is latched in interrupt flag bit, TMR3IF (PIR2<1>). from TMR3L will load the contents of the high byte of This interrupt can be enabled or disabled by setting or Timer3 into the Timer3 high byte buffer. This provides clearing the Timer3 Interrupt Enable bit, TMR3IE the user with the ability to accurately read all 16 bits of (PIE2<1>). Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has 14.5 Resetting Timer3 Using the CCP become invalid due to a rollover between reads. Special Event Trigger A write to the high byte of Timer3 must also take place If the CCP2 module is configured to generate a through the TMR3H Buffer register. The Timer3 high Special Event Trigger in Compare mode byte is updated with the contents of TMR3H when a (CCP2M3:CCP2M0=1011), this signal will reset write occurs to TMR3L. This allows a user to write all Timer3. It will also start an A/D conversion if the A/D 16 bits to both the high and low bytes of Timer3 at once. module is enabled (see Section15.3.4 “Special The high byte of Timer3 is not directly readable or Event Trigger” for more information.). writable in this mode. All reads and writes must take The module must be configured as either a timer or place through the Timer3 High Byte Buffer register. synchronous counter to take advantage of this feature. Writes to TMR3H do not clear the Timer3 prescaler. When used this way, the CCPR2H:CCPR2L register The prescaler is only cleared on writes to TMR3L. pair effectively becomes a period register for Timer3. If Timer3 is running in Asynchronous Counter mode, 14.3 Using the Timer1 Oscillator as the the Reset operation may not work. Timer3 Clock Source In the event that a write to Timer3 coincides with a The Timer1 internal oscillator may be used as the clock Special Event Trigger from a CCP module, the write will source for Timer3. The Timer1 oscillator is enabled by take precedence. setting the T1OSCEN (T1CON<3>) bit. To use it as the Note: The Special Event Triggers from the CCP2 Timer3 clock source, the TMR3CS bit must also be set. module will not set the TMR3IF interrupt As previously noted, this also configures Timer3 to flag bit (PIR2<1>). increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section12.0 “Timer1 Module”. TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56 TMR3L Timer3 Register Low Byte 55 TMR3H Timer3 Register High Byte 55 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. DS39632E-page 141

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 142 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 15.0 CAPTURE/COMPARE/PWM The Capture and Compare operations described in this (CCP) MODULES chapter apply to all standard and Enhanced CCP modules. PIC18F2455/2550/4455/4550 devices all have two Note: Throughout this section and Section16.0 CCP (Capture/Compare/PWM) modules. Each module “Enhanced Capture/Compare/PWM (ECCP) contains a 16-bit register, which can operate as a 16-bit Module”, references to the register and bit Capture register, a 16-bit Compare register or a PWM names for CCP modules are referred to gener- Master/Slave Duty Cycle register. ically by the use of ‘x’ or ‘y’ in place of the In 28-pin devices, the two standard CCP modules (CCP1 specific module number. Thus, “CCPxCON” and CCP2) operate as described in this chapter. In might refer to the control register for CCP1, 40/44-pin devices, CCP1 is implemented as an CCP2 or ECCP1. “CCPxCON” is used Enhanced CCP module, with standard Capture and throughout these sections to refer to the Compare modes and Enhanced PWM modes. The module control register regardless of whether ECCP implementation is discussed in Section16.0 the CCP module is a standard or Enhanced “Enhanced Capture/Compare/PWM (ECCP) Module”. implementation. REGISTER 15-1: CCPxCON: STANDARD CCPx CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 —(1) —(1) DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’(1) bit 5-4 DCxB1:DCxB0: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. bit 3-0 CCPxM3:CCPxM0: CCPx Module Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode: toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match (CCPxIF bit is set) 11xx = PWM mode Note 1: These bits are not implemented on 28-pin devices and are read as ‘0’. © 2009 Microchip Technology Inc. DS39632E-page 143

PIC18F2455/2550/4455/4550 15.1 CCP Module Configuration The assignment of a particular timer to a module is determined by the Timer to CCP enable bits in the Each Capture/Compare/PWM module is associated T3CON register (Register14-1). Both modules may be with a control register (generically, CCPxCON) and a active at any given time and may share the same timer data register (CCPRx). The data register, in turn, is resource if they are configured to operate in the same comprised of two 8-bit registers: CCPRxL (low byte) mode (Capture/Compare or PWM) at the same time. The and CCPRxH (high byte). All registers are both interactions between the two modules are summarized in readable and writable. Figure15-2. In Timer1 in Asynchronous Counter mode, the capture operation will not work. 15.1.1 CCP MODULES AND TIMER RESOURCES 15.1.2 CCP2 PIN ASSIGNMENT The CCP modules utilize Timers 1, 2 or 3, depending The pin assignment for CCP2 (capture input, compare on the mode selected. Timer1 and Timer3 are available and PWM output) can change, based on device config- to modules in Capture or Compare modes, while uration. The CCP2MX Configuration bit determines Timer2 is available for modules in PWM mode. which pin CCP2 is multiplexed to. By default, it is assigned to RC1 (CCP2MX = 1). If the Configuration bit TABLE 15-1: CCP MODE – TIMER is cleared, CCP2 is multiplexed with RB3. RESOURCE Changing the pin assignment of CCP2 does not CCP/ECCP Mode Timer Resource automatically change any requirements for configuring the port pin. Users must always verify that the appropri- Capture Timer1 or Timer3 ate TRIS register is configured correctly for CCP2 Compare Timer1 or Timer3 operation, regardless of where it is located. PWM Timer2 TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES CCP1 Mode CCP2 Mode Interaction Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different for each CCP. Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Automatic A/D conversions on trigger event can also be done. Operation of CCP1 could be affected if it is using the same timer as a time base. Compare Capture CCP1 be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Operation of CCP2 could be affected if it is using the same timer as a time base. Compare Compare Either module can be configured for the Special Event Trigger to reset the time base. Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if both modules are using the same time base. Capture PWM(1) None Compare PWM(1) None PWM(1) Capture None PWM(1) Compare None PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). Note 1: Includes standard and Enhanced PWM operation. DS39632E-page 144 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 15.2 Capture Mode 15.2.3 SOFTWARE INTERRUPT In Capture mode, the CCPRxH:CCPRxL register pair When the Capture mode is changed, a false capture captures the 16-bit value of the TMR1 or TMR3 interrupt may be generated. The user should keep the registers when an event occurs on the corresponding CCPxIE interrupt enable bit clear to avoid false CCPx pin. An event is defined as one of the following: interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. • every falling edge • every rising edge 15.2.4 CCP PRESCALER • every 4th rising edge There are four prescaler settings in Capture mode. • every 16th rising edge They are specified as part of the operating mode The event is selected by the mode select bits, selected by the mode select bits (CCPxM3:CCPxM0). Whenever the CCP module is turned off or Capture CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture mode is disabled, the prescaler counter is cleared. This is made, the interrupt request flag bit, CCPxIF, is set; it means that any Reset will clear the prescaler counter. must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old Switching from one capture prescaler to another may captured value is overwritten by the new captured value. generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from 15.2.1 CCP PIN CONFIGURATION a non-zero prescaler. Example15-1 shows the In Capture mode, the appropriate CCPx pin should be recommended method for switching between capture configured as an input by setting the corresponding prescalers. This example also clears the prescaler TRIS direction bit. counter and will not generate the “false” interrupt. Note: If RB3/CCP2 or RC1/CCP2 is configured EXAMPLE 15-1: CHANGING BETWEEN as an output, a write to the port can cause CAPTURE PRESCALERS a capture condition. (CCP2 SHOWN) 15.2.2 TIMER1/TIMER3 MODE SELECTION CLRF CCP2CON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load WREG with the The timers that are to be used with the capture feature ; new prescaler mode (Timer1 and/or Timer3) must be running in Timer mode or ; value and CCP ON Synchronized Counter mode. In Asynchronous Counter MOVWF CCP2CON ; Load CCP2CON with mode, the capture operation will not work. The timer to be ; this value used with each CCP module is selected in the T3CON register (see Section15.1.1 “CCP Modules and Timer Resources”). FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP1IF T3CCP2 TMR3 Enable CCP1 pin Prescaler and CCPR1H CCPR1L ÷ 1, 4, 16 Edge Detect TMR1 T3CCP2 Enable 4 TMR1H TMR1L CCP1CON<3:0> Set CCP2IF 4 Q1:Q4 4 CCP2CON<3:0> T3CCP1 TMR3H TMR3L T3CCP2 TMR3 Enable CCP2 pin Prescaler and CCPR2H CCPR2L ÷ 1, 4, 16 Edge Detect TMR1 Enable T3CCP2 TMR1H TMR1L T3CCP1 © 2009 Microchip Technology Inc. DS39632E-page 145

PIC18F2455/2550/4455/4550 15.3 Compare Mode 15.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is Timer1 and/or Timer3 must be running in Timer mode, constantly compared against either the TMR1 or TMR3 or Synchronized Counter mode, if the CCP module is register pair value. When a match occurs, the CCPx pin using the compare feature. In Asynchronous Counter can be: mode, the compare operation may not work. • driven high 15.3.3 SOFTWARE INTERRUPT MODE • driven low When the Generate Software Interrupt mode is chosen • toggled (high-to-low or low-to-high) (CCPxM3:CCPxM0 = 1010), the corresponding CCPx • remain unchanged (that is, reflects the state of the pin is not affected. Only a CCP interrupt is generated, I/O latch) if enabled, and the CCPxIE bit is set. The action on the pin is based on the value of the mode 15.3.4 SPECIAL EVENT TRIGGER select bits (CCPxM3:CCPxM0). At the same time, the interrupt flag bit, CCPxIF, is set. Both CCP modules are equipped with a Special Event Trigger. This is an internal hardware signal generated 15.3.1 CCP PIN CONFIGURATION in Compare mode to trigger actions by other modules. The user must configure the CCPx pin as an output by The Special Event Trigger is enabled by selecting clearing the appropriate TRIS bit. the Compare Special Event Trigger mode (CCPxM3:CCPxM0 = 1011). Note: Clearing the CCP2CON register will force For either CCP module, the Special Event Trigger resets the RB3 or RC1 compare output latch the Timer register pair for whichever timer resource is (depending on device configuration) to the currently assigned as the module’s time base. This default low level. This is not the PORTB or allows the CCPRx registers to serve as a programmable PORTC I/O data latch. Period register for either timer. The Special Event Trigger for CCP2 can also start an A/D conversion. In order to do this, the A/D converter must already be enabled. FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger Set CCP1IF (Timer1/Timer3 Reset) CCPR1H CCPR1L CCP1 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCP1CON<3:0> TMR1H TMR1L 0 0 1 TMR3H TMR3L 1 Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) T3CCP1 T3CCP2 Set CCP2IF CCP2 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCPR2H CCPR2L CCP2CON<3:0> DS39632E-page 146 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 RCON IPEN SBOREN(1) — RI TO PD POR BOR 54 PIR1 SPPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56 TMR1L Timer1 Register Low Byte 54 TMR1H Timer1 Register High Byte 54 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54 TMR3H Timer3 Register High Byte 55 TMR3L Timer3 Register Low Byte 55 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 55 CCPR1L Capture/Compare/PWM Register 1 Low Byte 55 CCPR1H Capture/Compare/PWM Register 1 High Byte 55 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 55 CCPR2L Capture/Compare/PWM Register 2 Low Byte 55 CCPR2H Capture/Compare/PWM Register 2 High Byte 55 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: The SBOREN bit is only available when BOREN<1:0>=01; otherwise, the bit reads as ‘0’. 2: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2009 Microchip Technology Inc. DS39632E-page 147

PIC18F2455/2550/4455/4550 15.4 PWM Mode 15.4.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCPx pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the the CCP2 pin is multiplexed with a PORTB or PORTC following formula: data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. EQUATION 15-1: Note: Clearing the CCP2CON register will force PWM Period = [(PR2) + 1] • 4 • TOSC • the RB3 or RC1 output latch (depending (TMR2 Prescale Value) on device configuration) to the default low level. This is not the PORTB or PORTC PWM frequency is defined as 1/[PWM period]. I/O data latch. When TMR2 is equal to PR2, the following three events Figure15-3 shows a simplified block diagram of the occur on the next increment cycle: CCP module in PWM mode. • TMR2 is cleared For a step-by-step procedure on how to set up the CCP • The CCPx pin is set (exception: if PWM duty module for PWM operation, see Section15.4.4 cycle=0%, the CCPx pin will not be set) “Setup for PWM Operation”. • The PWM duty cycle is latched from CCPRxL into CCPRxH FIGURE 15-3: SIMPLIFIED PWM BLOCK Note: The Timer2 postscalers (see Section13.0 DIAGRAM “Timer2 Module”) are not used in the CCPxCON<5:4> determination of the PWM frequency. The Duty Cycle Registers postscaler could be used to have a servo CCPRxL update rate at a different frequency than the PWM output. 15.4.2 PWM DUTY CYCLE CCPRxH (Slave) The PWM duty cycle is specified by writing to the Comparator R Q CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available. The CCPRxL contains CCPx Output the eight MSbs and the CCPxCON<5:4> bits contain TMR2 (Note 1) the two LSbs. This 10-bit value is represented by S CCPRxL:CCPxCON<5:4>. The following equation is Corresponding used to calculate the PWM duty cycle in time: Comparator TRIS bit Clear Timer, CCPx pin and EQUATION 15-2: latch D.C. PR2 PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) • Note1: The 8-bit TMR2 value is concatenated with the 2-bit TOSC • (TMR2 Prescale Value) internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. CCPRxL and CCPxCON<5:4> can be written to at any A PWM output (Figure15-4) has a time base (period) time, but the duty cycle value is not latched into and a time that the output stays high (duty cycle). The CCPRxH until after a match between PR2 and TMR2 frequency of the PWM is the inverse of the period occurs (i.e., the period is complete). In PWM mode, (1/period). CCPRxH is a read-only register. FIGURE 15-4: PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 DS39632E-page 148 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 The CCPRxH register and a 2-bit internal latch are EQUATION 15-3: used to double-buffer the PWM duty cycle. This ⎛FOSC⎞ double-buffering is essential for glitchless PWM log⎝F----P---W-----M---⎠ operation. PWM Resolution (max) = -----------------------------bits log(2) When the CCPRxH and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCPx pin is cleared. Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be The maximum PWM resolution (bits) for a given PWM cleared. frequency is given by the equation: TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 15.4.3 PWM AUTO-SHUTDOWN 15.4.4 SETUP FOR PWM OPERATION (CCP1 ONLY) The following steps should be taken when configuring The PWM auto-shutdown features of the Enhanced CCP the CCPx module for PWM operation: module are also available to CCP1 in 28-pin devices. The 1. Set the PWM period by writing to the PR2 operation of this feature is discussed in detail in register. Section16.4.7 “Enhanced PWM Auto-Shutdown”. 2. Set the PWM duty cycle by writing to the Auto-shutdown features are not available for CCP2. CCPRxL register and CCPxCON<5:4> bits. 3. Make the CCPx pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. 5. Configure the CCPx module for PWM operation. © 2009 Microchip Technology Inc. DS39632E-page 149

PIC18F2455/2550/4455/4550 TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 RCON IPEN SBOREN(1) — RI TO PD POR BOR 54 PIR1 SPPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56 TMR2 Timer2 Register 54 PR2 Timer2 Period Register 54 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 54 CCPR1L Capture/Compare/PWM Register 1 Low Byte 55 CCPR1H Capture/Compare/PWM Register 1 High Byte 55 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 55 CCPR2L Capture/Compare/PWM Register 2 Low Byte 55 CCPR2H Capture/Compare/PWM Register 2 High Byte 55 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 55 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 55 ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: The SBOREN bit is only available when BOREN<1:0>=01; otherwise, the bit reads as ‘0’. 2: These bits are unimplemented on 28-pin devices; always maintain these bits clear. DS39632E-page 150 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 16.0 ENHANCED automatic shutdown and restart. The Enhanced CAPTURE/COMPARE/PWM features are discussed in detail in Section16.4 “Enhanced PWM Mode”. Capture, Compare and (ECCP) MODULE single output PWM functions of the ECCP module are the same as described for the standard CCP module. Note: The ECCP module is implemented only in 40/44-pin devices. The control register for the Enhanced CCP module is shown in Register16-1. It differs from the CCPxCON In 28-pin devices, CCP1 is implemented as a standard registers in 28-pin devices in that the two Most Signifi- CCP module with Enhanced PWM capabilities. These cant bits are implemented to control PWM functionality. include the provision for 2 or 4 output channels, user-selectable polarity, dead-band control and REGISTER 16-1: CCP1CON: ECCP CONTROL REGISTER (40/44-PIN DEVICES) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bits If CCP1M3:CCP1M2 = 00, 01, 10: xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins If CCP1M3:CCP1M2 = 11: 00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B1:DC1B0: PWM Duty Cycle Bit 1 and Bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits 0000 =Capture/Compare/PWM off (resets ECCP module) 0001 =Reserved 0010 =Compare mode, toggle output on match 0011 =Capture mode 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF) 1001 =Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF) 1010 =Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state 1011 =Compare mode, trigger special event (CCP1 resets TMR1 or TMR3, sets CCP1IF bit) 1100 =PWM mode: P1A, P1C active-high; P1B, P1D active-high 1101 =PWM mode: P1A, P1C active-high; P1B, P1D active-low 1110 =PWM mode: P1A, P1C active-low; P1B, P1D active-high 1111 =PWM mode: P1A, P1C active-low; P1B, P1D active-low © 2009 Microchip Technology Inc. DS39632E-page 151

PIC18F2455/2550/4455/4550 In addition to the expanded range of modes available 16.2 Capture and Compare Modes through the CCP1CON register, the ECCP module has two additional registers associated with Enhanced Except for the operation of the Special Event Trigger PWM operation and auto-shutdown features. They are: discussed below, the Capture and Compare modes of the ECCP module are identical in operation to that of • ECCP1DEL (PWM Dead-Band Delay) CCP. These are discussed in detail in Section15.2 • ECCP1AS (ECCP Auto-Shutdown Control) “Capture Mode” and Section15.3 “Compare Mode”. 16.1 ECCP Outputs and Configuration 16.2.1 SPECIAL EVENT TRIGGER The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. The Special Event Trigger output of ECCP resets the These outputs, designated P1A through P1D, are TMR1 or TMR3 register pair, depending on which timer multiplexed with I/O pins on PORTC and PORTD. The resource is currently selected. This allows the outputs that are active depend on the CCP operating CCPR1H:CCPR1L registers to effectively be a 16-bit mode selected. The pin assignments are summarized programmable period register for Timer1 or Timer3. in Table16-1. 16.3 Standard PWM Mode To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the When configured in Single Output mode, the ECCP P1M1:P1M0 and CCP1M3:CCP1M0 bits. The module functions identically to the standard CCP appropriate TRISC and TRISD direction bits for the port module in PWM mode as described in Section15.4 pins must also be set as outputs. “PWM Mode”. This is also sometimes referred to as “Compatible CCP” mode, as in Table16-1. 16.1.1 ECCP MODULES AND TIMER RESOURCES Note: When setting up single output PWM operations, users are free to use either of Like the standard CCP modules, the ECCP module can the processes described in Section15.4.4 utilize Timers 1, 2 or 3, depending on the mode “Setup for PWM Operation” or selected. Timer1 and Timer3 are available for modules Section16.4.9 “Setup for PWM Opera- in Capture or Compare modes, while Timer2 is tion”. The latter is more generic but will available for modules in PWM mode. Interactions work for either single or multi-output PWM. between the standard and Enhanced CCP modules are identical to those described for standard CCP modules. Additional details on timer resources are provided in Section15.1.1 “CCP Modules and Timer Resources”. TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES CCP1CON ECCP Mode RC2 RD5 RD6 RD7 Configuration All PIC18F4455/4550 devices: Compatible CCP 00xx 11xx CCP1 RD5/SPP5 RD6/SPP6 RD7/SPP7 Dual PWM 10xx 11xx P1A P1B RD6/SPP6 RD7/SPP7 Quad PWM x1xx 11xx P1A P1B P1C P1D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode. DS39632E-page 152 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 16.4 Enhanced PWM Mode 16.4.1 PWM PERIOD The Enhanced PWM mode provides additional PWM The PWM period is specified by writing to the PR2 output options for a broader range of control applica- register. The PWM period can be calculated using the tions. The module is a backward compatible version of following equation: the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to EQUATION 16-1: select the polarity of the signal (either active-high or PWM Period = [(PR2) + 1] • 4 • TOSC • active-low). The module’s output mode and polarity are (TMR2 Prescale Value) configured by setting the P1M1:P1M0 and CCP1M3:CCP1M0 bits of the CCP1CON register. PWM frequency is defined as 1/[PWM period]. When Figure16-1 shows a simplified block diagram of PWM TMR2 is equal to PR2, the following three events occur operation. All control registers are double-buffered and on the next increment cycle: are loaded at the beginning of a new PWM cycle (the • TMR2 is cleared period boundary when Timer2 resets) in order to • The CCP1 pin is set (if PWM duty cycle=0%, the prevent glitches on any of the outputs. The exception is CCP1 pin will not be set) the PWM Dead-Band Delay register, ECCP1DEL, • The PWM duty cycle is copied from CCPR1L into which is loaded at either the duty cycle boundary or the CCPR1H boundary period (whichever comes first). Because of the buffering, the module waits until the assigned timer Note: The Timer2 postscaler (see Section13.0 resets instead of starting immediately. This means that “Timer2 Module”) is not used in the Enhanced PWM waveforms do not exactly match the determination of the PWM frequency. The standard PWM waveforms, but are instead offset by postscaler could be used to have a servo one full instruction cycle (4 TOSC). update rate at a different frequency than As before, the user must manually configure the the PWM output. appropriate TRIS bits for output. FIGURE 16-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> P1M1:P1M0 CCP1M3:CCP1M0 Duty Cycle Registers 2 4 CCPR1L CCP1/P1A CCP1/P1A TRISD<4> CCPR1H (Slave) P1B P1B Output TRISD<5> Comparator R Q Controller P1C P1C TMR2 (Note 1) S TRISD<6> P1D P1D Comparator Clear Timer, TRISD<7> set CCP1 pin and latch D.C. PR2 ECCP1DEL Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. DS39632E-page 153

PIC18F2455/2550/4455/4550 16.4.2 PWM DUTY CYCLE EQUATION 16-3: The PWM duty cycle is specified by writing to the log(FOSC) CCPR1L register and to the CCP1CON<5:4> bits. Up FPWM to 10-bit resolution is available. The CCPR1L contains PWM Resolution (max) = bits log(2) the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation. Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be EQUATION 16-2: cleared. PWM Duty Cycle = (CCPR1L:CCP1CON<5:4> • 16.4.3 PWM OUTPUT CONFIGURATIONS TOSC • (TMR2 Prescale Value) The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into • Single Output CCPR1H until a match between PR2 and TMR2 occurs • Half-Bridge Output (i.e., the period is complete). In PWM mode, CCPR1H • Full-Bridge Output, Forward mode is a read-only register. • Full-Bridge Output, Reverse mode The CCPR1H register and a 2-bit internal latch are The Single Output mode is the standard PWM mode used to double-buffer the PWM duty cycle. This discussed in Section16.4 “Enhanced PWM Mode”. double-buffering is essential for glitchless PWM opera- The Half-Bridge and Full-Bridge Output modes are tion. When the CCPR1H and 2-bit latch match TMR2, covered in detail in the sections that follow. concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The The general relationship of the outputs in all maximum PWM resolution (bits) for a given PWM configurations is summarized in Figure16-2 and frequency is given by the following equation. Figure16-3. TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 DS39632E-page 154 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 Duty PR2 + 1 CCP1CON SIGNAL Cycle <7:6> Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 Duty PR2 + 1 CCP1CON SIGNAL Cycle <7:6> Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section16.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. DS39632E-page 155

PIC18F2455/2550/4455/4550 16.4.4 HALF-BRIDGE MODE FIGURE 16-4: HALF-BRIDGE PWM OUTPUT In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output sig- Period Period nal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin Duty Cycle (Figure16-4). This mode can be used for half-bridge P1A(2) applications, as shown in Figure16-5, or for full-bridge td applications where four power switches are being td modulated with two PWM signals. P1B(2) In Half-Bridge Output mode, the programmable dead-band delay can be used to prevent shoot-through (1) (1) (1) current in half-bridge power devices. The value of bits PDC6:PDC0 sets the number of instruction cycles td = Dead-Band Delay before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains Note 1: At this time, the TMR2 register is equal to the inactive during the entire cycle. See Section16.4.6 PR2 register. “Programmable Dead-Band Delay” for more details 2: Output signals are shown as active-high. of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTD<5> data latches, the TRISC<2> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs. FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) PIC18FX455/X550 FET Driver + P1A V - Load FET Driver + P1B V - V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18FX455/X550 FET FET Driver Driver P1A Load FET FET Driver Driver P1B V- DS39632E-page 156 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 16.4.5 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTD<5>, PORTD<6> and In Full-Bridge Output mode, four pins are used as PORTD<7> data latches. The TRISC<2>, TRISD<5>, outputs; however, only two outputs are active at a time. TRISD<6> and TRISD<7> bits must be cleared to In the Forward mode, pin P1A is continuously active make the P1A, P1B, P1C and P1D pins outputs. and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure16-6. FIGURE 16-6: FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. DS39632E-page 157

PIC18F2455/2550/4455/4550 FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18FX455/X550 FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D 16.4.5.1 Direction Change in Full-Bridge Mode Figure16-9 shows an example where the PWM direc- tion changes from forward to reverse at a near 100% In the Full-Bridge Output mode, the P1M1 bit in the duty cycle. At time t1, the outputs, P1A and P1D, CCP1CON register allows the user to control the become inactive, while output P1C becomes active. In forward/reverse direction. When the application firm- this example, since the turn-off time of the power ware changes this direction control bit, the module will devices is longer than the turn-on time, a shoot-through assume the new direction on the next PWM cycle. current may flow through power devices, QC and QD, Just before the end of the current PWM period, the (see Figure16-7) for the duration of ‘t’. The same modulated outputs (P1B and P1D) are placed in their phenomenon will occur to power devices, QA and QB, inactive state, while the unmodulated outputs (P1A and for PWM direction change from reverse to forward. P1C) are switched to drive in the opposite direction. If changing PWM direction at high duty cycle is required This occurs in a time interval of (4 TOSC * (Timer2 for an application, one of the following requirements Prescale Value) before the next PWM period begins. must be met: The Timer2 prescaler will be either 1, 4 or 16, depending on the value of the T2CKPS1:T2CKPS0 bits 1. Reduce PWM for a PWM period before (T2CON<1:0>). During the interval from the switch of changing directions. the unmodulated outputs to the beginning of the next 2. Use switch drivers that can drive the switches off period, the modulated outputs (P1B and P1D) remain faster than they can drive them on. inactive. This relationship is shown in Figure16-8. Other options to prevent shoot-through current may Note that in the Full-Bridge Output mode, the ECCP exist. module does not provide any dead-band delay. In gen- eral, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. DS39632E-page 158 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 16-8: PWM DIRECTION CHANGE Period(1) Period SIGNAL P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 16-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A(1) P1B(1) DC P1C(1) P1D(1) DC t (2) ON External Switch C(1) t (3) OFF External Switch D(1) t = t – t (2, 3) OFF ON Potential Shoot-Through Current(1) Note 1: All signals are shown as active-high. 2: t is the turn-on delay of power switch QC and its driver. ON 3: t is the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. DS39632E-page 159

PIC18F2455/2550/4455/4550 16.4.6 PROGRAMMABLE DEAD-BAND A shutdown event can be caused by either of the DELAY comparator modules, a low level on the RB0/AN12/INT0/FLT0/SDI/SDA pin, or any combination Note: Programmable dead-band delay is not of these three sources. The comparators may be used to implemented in 28-pin devices with monitor a voltage input proportional to a current being standard CCP modules. monitored in the bridge circuit. If the voltage exceeds a In half-bridge applications where all power switches are threshold, the comparator switches state and triggers a modulated at the PWM frequency at all times, the power shutdown. Alternatively, a digital signal on the INT0 pin switches normally require more time to turn off than to can also trigger a shutdown. The auto-shutdown feature turn on. If both the upper and lower power switches are can be disabled by not selecting any auto-shutdown switched at the same time (one turned on and the other sources. The auto-shutdown sources to be used are turned off), both switches may be on for a short period of selected using the ECCPAS2:ECCPAS0 bits (bits<6:4> time until one switch completely turns off. During this of the ECCP1AS register). brief interval, a very high current (shoot-through current) When a shutdown occurs, the output pins are may flow through both power switches, shorting the asynchronously placed in their shutdown states, bridge supply. To avoid this potentially destructive specified by the PSSAC1:PSSAC0 and shoot-through current from flowing during switching, PSSBD1:PSSBD0 bits (ECCP1AS3:ECCP1AS0). Each turning on either of the power switches is normally pin pair (P1A/P1C and P1B/P1D) may be set to drive delayed to allow the other switch to completely turn off. high, drive low or be tri-stated (not driving). The In the Half-Bridge Output mode, a digitally program- ECCPASE bit (ECCP1AS<7>) is also set to hold the mable dead-band delay is available to avoid Enhanced PWM outputs in their shutdown states. shoot-through current from destroying the bridge The ECCPASE bit is set by hardware when a shutdown power switches. The delay occurs at the signal transi- event occurs. If automatic restarts are not enabled, the tion from the non-active state to the active state. See ECCPASE bit is cleared by firmware when the cause of Figure16-4 for illustration. Bits PDC6:PDC0 of the the shutdown clears. If automatic restarts are enabled, ECCP1DEL register (Register16-2) set the delay the ECCPASE bit is automatically cleared when the period in terms of microcontroller instruction cycles cause of the auto-shutdown has cleared. (TCY or 4 TOSC). These bits are not available on 28-pin If the ECCPASE bit is set when a PWM period begins, devices, as the standard CCP module does not support the PWM outputs remain in their shutdown state for that half-bridge operation. entire PWM period. When the ECCPASE bit is cleared, 16.4.7 ENHANCED PWM AUTO-SHUTDOWN the PWM outputs will return to normal operation at the beginning of the next PWM period. When ECCP is programmed for any of the Enhanced PWM modes, the active output pins may be configured Note: Writing to the ECCPASE bit is disabled for auto-shutdown. Auto-shutdown immediately places while a shutdown condition is active. the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs. REGISTER 16-2: ECCP1DEL: PWM DEAD-BAND DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC6:PDC0: PWM Delay Count bits(1) Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. Note 1: Reserved on 28-pin devices; maintain these bits clear. DS39632E-page 160 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS2:ECCPAS0: ECCP Auto-Shutdown Source Select bits 111 = FLT0 or Comparator 1 or Comparator 2 110 = FLT0 or Comparator 2 101 = FLT0 or Comparator 1 100 = FLT0 011 = Either Comparator 1 or 2 010 = Comparator 2 output 001 = Comparator 1 output 000 = Auto-shutdown is disabled bit 3-2 PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits 1x = Pins A and C tri-state (40/44-pin devices) 01 = Drive Pins A and C to ‘1’ 00 = Drive Pins A and C to ‘0’ bit 1-0 PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits(1) 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ 00 = Drive Pins B and D to ‘0’ Note 1: Reserved on 28-pin devices; maintain these bits clear. © 2009 Microchip Technology Inc. DS39632E-page 161

PIC18F2455/2550/4455/4550 16.4.7.1 Auto-Shutdown and Auto-Restart 16.4.8 START-UP CONSIDERATIONS The auto-shutdown feature can be configured to allow When the ECCP module is used in the PWM mode, the automatic restarts of the module following a shutdown application hardware must use the proper external pull-up event. This is enabled by setting the PRSEN bit of the and/or pull-down resistors on the PWM output pins. When ECCP1DEL register (ECCP1DEL<7>). the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits In Shutdown mode with PRSEN = 1 (Figure16-10), the must keep the power switch devices in the OFF state until ECCPASE bit will remain set for as long as the cause the microcontroller drives the I/O pins with the proper of the shutdown continues. When the shutdown condi- signal levels or activates the PWM output(s). tion clears, the ECCP1ASE bit is cleared. If PRSEN =0 (Figure16-11), once a shutdown condition occurs, the The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow ECCPASE bit will remain set until it is cleared by the user to choose whether the PWM output signals are firmware. Once ECCPASE is cleared, the Enhanced active-high or active-low for each pair of PWM output PWM will resume at the beginning of the next PWM pins (P1A/P1C and P1B/P1D). The PWM output period. polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configura- Note: Writing to the ECCPASE bit is disabled tion while the PWM pins are configured as outputs is while a shutdown condition is active. not recommended, since it may result in damage to the Independent of the PRSEN bit setting, if the application circuits. auto-shutdown source is one of the comparators, the The P1A, P1B, P1C and P1D output latches may not be shutdown condition is a level. The ECCPASE bit in the proper states when the PWM module is initialized. cannot be cleared as long as the cause of the shutdown Enabling the PWM pins for output at the same time as persists. the ECCP module may cause damage to the applica- The Auto-Shutdown mode can be forced by writing a ‘1’ tion circuit. The ECCP module must be enabled in the to the ECCPASE bit. proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The com- pletion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. FIGURE 16-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED) PWM Period PWM Period PWM Period PWM Activity Dead Time Dead Time Dead Time Duty Cycle Duty Cycle Duty Cycle ShutdownEvent ECCPASE bit FIGURE 16-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED) PWM Period PWM Period PWM Period PWM Activity Dead Time Dead Time Dead Time Duty Cycle Duty Cycle Duty Cycle ShutdownEvent ECCPASE bit ECCPASE Cleared by Firmware DS39632E-page 162 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 16.4.9 SETUP FOR PWM OPERATION 16.4.10 OPERATION IN POWER-MANAGED MODES The following steps should be taken when configuring the ECCP module for PWM operation: In Sleep mode, all clock sources are disabled. Timer2 1. Configure the PWM pins, P1A and P1B (and will not increment and the state of the module will not P1C and P1D, if used), as inputs by setting the change. If the ECCP pin is driving a value, it will continue corresponding TRIS bits. to drive that value. When the device wakes up, it will 2. Set the PWM period by loading the PR2 register. continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from INTOSC and 3. If auto-shutdown is required, do the following: the postscaler may not be stable immediately. • Disable auto-shutdown (ECCPASE = 0) In PRI_IDLE mode, the primary clock will continue to • Configure source (FLT0, Comparator 1 or clock the ECCP module without change. In all other Comparator 2) power-managed modes, the selected power-managed • Wait for non-shutdown condition mode clock will clock Timer2. Other power-managed 4. Configure the ECCP module for the desired mode clocks will most likely be different than the PWM mode and configuration by loading the primary clock frequency. CCP1CON register with the appropriate values: • Select one of the available output 16.4.10.1 Operation with Fail-Safe configurations and direction with the Clock Monitor P1M1:P1M0 bits. If the Fail-Safe Clock Monitor is enabled, a clock failure • Select the polarities of the PWM output will force the device into the power-managed RC_RUN signals with the CCP1M3:CCP1M0 bits. mode and the OSCFIF bit (PIR2<7>) will be set. The 5. Set the PWM duty cycle by loading the CCPR1L ECCP will then be clocked from the internal oscillator register and CCP1CON<5:4> bits. clock source, which may have a different clock 6. For Half-Bridge Output mode, set the frequency than the primary clock. dead-band delay by loading ECCP1DEL<6:0> See the previous section for additional details. with the appropriate value. 7. If auto-shutdown operation is required, load the 16.4.11 EFFECTS OF A RESET ECCP1AS register: Both Power-on Reset and subsequent Resets will force • Select the auto-shutdown sources using the all ports to Input mode and the CCP registers to their ECCPAS2:ECCPAS0 bits. Reset states. • Select the shutdown states of the PWM This forces the Enhanced CCP module to reset to a output pins using the PSSAC1:PSSAC0 and state compatible with the standard CCP module. PSSBD1:PSSBD0 bits. • Set the ECCPASE bit (ECCP1AS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. 8. If auto-restart operation is required, set the PRSEN bit (ECCP1DEL<7>). 9. Configure and start TMR2: • Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). • Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). • Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 10. Enable PWM outputs after a new PWM cycle has started: • Wait until TMRx overflows (TMRxIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2009 Microchip Technology Inc. DS39632E-page 163

PIC18F2455/2550/4455/4550 TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP MODULE AND TIMER1 TO TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 RCON IPEN SBOREN(1) — RI TO PD POR BOR 54 IPR1 SPPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 PIR1 SPPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56 TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56 TMR1L Timer1 Register Low Byte 54 TMR1H Timer1 Register High Byte 54 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54 TMR2 Timer2 Module Register 54 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 54 PR2 Timer2 Period Register 54 TMR3L Timer3 Register Low Byte 55 TMR3H Timer3 Register High Byte 55 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 55 CCPR1L Capture/Compare/PWM Register 1 (LSB) 55 CCPR1H Capture/Compare/PWM Register 1 (MSB) 55 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 55 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 55 ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: The SBOREN bit is only available when BOREN<1:0>=01; otherwise, the bit reads as ‘0’. 2: These bits or registers are unimplemented in 28-pin devices; always maintain these bits clear. DS39632E-page 164 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 17.0 UNIVERSAL SERIAL BUS The SIE can be interfaced directly to the USB, utilizing (USB) the internal transceiver, or it can be connected through an external transceiver. An internal 3.3V regulator is This section describes the details of the USB also available to power the internal transceiver in 5V peripheral. Because of the very specific nature of the applications. module, knowledge of USB is expected. Some Some special hardware features have been included to high-level USB information is provided in improve performance. Dual port memory in the Section17.10 “Overview of USB” only for application device’s data memory space (USB RAM) has been design reference. Designers are encouraged to refer to supplied to share direct memory access between the the official specification published by the USB Imple- microcontroller core and the SIE. Buffer descriptors are menters Forum (USB-IF) for the latest information. also provided, allowing users to freely program end- USB specification Revision 2.0 is the most current point memory usage within the USB RAM space. A specification at the time of publication of this document. Streaming Parallel Port has been provided to support the uninterrupted transfer of large volumes of data, 17.1 Overview of the USB Peripheral such as isochronous data, to external memory buffers. The PIC18FX455/X550 device family contains a Figure17-1 presents a general overview of the USB full-speed and low-speed compatible USB Serial Inter- peripheral and its features. face Engine (SIE) that allows fast communication between any USB host and the PIC® microcontroller. FIGURE 17-1: USB PERIPHERAL AND OPTIONS PIC18FX455/X550 Family 3.3V Regulator External 3.3V VUSB Supply(3) VREGEN EN Optional P External Pull-ups(2) FSEN P UPUEN Internal Pull-ups (Full (Low UTRDIS Speed) Speed) Transceiver USB Bus USB Clock from the FS D+ Oscillator Module UOE D- UOE(1) TrEaxntsecreniavler USB Control and VM(1) USB Bus Configuration VP(1) RCV(1) USB VMO(1) SIE VPO(1) SPP7:SPP0 1Kbyte CK1SPP USB RAM CK2SPP CSSPP OESPP Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1). 2: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used. 3: Do not enable the internal regulator when using an external 3.3V supply. © 2009 Microchip Technology Inc. DS39632E-page 165

PIC18F2455/2550/4455/4550 17.2 USB Status and Control In addition, the USB Control register contains a status bit, SE0 (UCON<5>), which is used to indicate the occur- The operation of the USB module is configured and rence of a single-ended zero on the bus. When the USB managed through three control registers. In addition, a module is enabled, this bit should be monitored to deter- total of 22 registers are used to manage the actual USB mine whether the differential data lines have come out of transactions. The registers are: a single-ended zero condition. This helps to differentiate • USB Control register (UCON) the initial power-up state from the USB Reset signal. • USB Configuration register (UCFG) The overall operation of the USB module is controlled by • USB Transfer Status register (USTAT) the USBEN bit (UCON<3>). Setting this bit activates the • USB Device Address register (UADDR) module and resets all of the PPBI bits in the Buffer • Frame Number registers (UFRMH:UFRML) Descriptor Table to ‘0’. This bit also activates the on-chip • Endpoint Enable registers 0 through 15 (UEPn) voltage regulator (if the VREGEN Configuration bit is set) and connects internal pull-up resistors, if they are 17.2.1 USB CONTROL REGISTER (UCON) enabled. Thus, this bit can be used as a soft attach/detach to the USB. Although all status and control The USB Control register (Register17-1) contains bits bits are ignored when this bit is clear, the module needs needed to control the module behavior during transfers. to be fully preconfigured prior to setting this bit. The register contains bits that control the following: Note: When disabling the USB module, make • Main USB Peripheral Enable sure the SUSPND bit (UCON<1>) is clear • Ping-Pong Buffer Pointer Reset prior to clearing the USBEN bit. Clearing • Control of the Suspend mode the USBEN bit when the module is in the • Packet Transfer Disable suspended state may prevent the module from fully powering down. REGISTER 17-1: UCON: USB CONTROL REGISTER U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0 — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks 0 = Ping-Pong Buffer Pointers not being reset bit 5 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero active on the USB bus 0 = No single-ended zero detected bit 4 PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing disabled, automatically set when a SETUP token is received 0 = SIE token and packet processing enabled bit 3 USBEN: USB Module Enable bit 1 = USB module and supporting circuitry enabled (device attached) 0 = USB module and supporting circuitry disabled (device detached) bit 2 RESUME: Resume Signaling Enable bit 1 = Resume signaling activated 0 = Resume signaling disabled bit 1 SUSPND: Suspend USB bit 1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive 0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate bit 0 Unimplemented: Read as ‘0’ DS39632E-page 166 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 The PPBRST bit (UCON<6>) controls the Reset status The UCFG register also contains two bits which aid in when Double-Buffering mode (ping-pong buffering) is module testing, debugging and USB certifications. used. When the PPBRST bit is set, all Ping-Pong Buf- These bits control output enable state monitoring and fer Pointers are set to the Even buffers. PPBRST has eye pattern generation. to be cleared by firmware. This bit is ignored in buffer- Note: The USB speed, transceiver and pull-up ing modes not using ping-pong buffering. should only be configured during the mod- The PKTDIS bit (UCON<4>) is a flag indicating that the ule setup phase. It is not recommended to SIE has disabled packet transmission and reception. switch these settings while the module is This bit is set by the SIE when a SETUP token is enabled. received to allow setup processing. This bit cannot be set by the microcontroller, only cleared; clearing it 17.2.2.1 Internal Transceiver allows the SIE to continue transmission and/or The USB peripheral has a built-in, USB 2.0, full-speed reception. Any pending events within the Buffer and low-speed compliant transceiver, internally con- Descriptor Table will still be available, indicated within nected to the SIE. This feature is useful for low-cost the USTAT register’s FIFO buffer. single chip applications. The UTRDIS bit (UCFG<3>) The RESUME bit (UCON<2>) allows the peripheral to controls the transceiver; it is enabled by default perform a remote wake-up by executing Resume (UTRDIS = 0). The FSEN bit (UCFG<2>) controls the signaling. To generate a valid remote wake-up, transceiver speed; setting the bit enables full-speed firmware must set RESUME for 10ms and then clear operation. the bit. For more information on Resume signaling, see The on-chip USB pull-up resistors are controlled by the Sections7.1.7.5, 11.4.4 and 11.9 in the USB 2.0 UPUEN bit (UCFG<4>). They can only be selected specification. when the on-chip transceiver is enabled. The SUSPND bit (UCON<1>) places the module and The USB specification requires 3.3V operation for supporting circuitry (i.e., voltage regulator) in a communications; however, the rest of the chip may be low-power mode. The input clock to the SIE is also running at a higher voltage. Thus, the transceiver is disabled. This bit should be set by the software in response to an IDLEIF interrupt. It should be reset by supplied power from a separate source, VUSB. the microcontroller firmware after an ACTVIF interrupt 17.2.2.2 External Transceiver is observed. When this bit is active, the device remains attached to the bus but the transceiver outputs remain This module provides support for use with an off-chip Idle. The voltage on the VUSB pin may vary depending transceiver. The off-chip transceiver is intended for on the value of this bit. Setting this bit before a IDLEIF applications where physical conditions dictate the request will result in unpredictable bus behavior. location of the transceiver to be away from the SIE. External transceiver operation is enabled by setting the Note: While in Suspend mode, a typical bus UTRDIS bit. powered USB device is limited to 2.5 mA of current. Care should be taken to assure FIGURE 17-2: TYPICAL EXTERNAL minimum current draw when the device TRANSCEIVER WITH enters Suspend mode. ISOLATION 17.2.2 USB CONFIGURATION REGISTER PIC® VDDIsolated 3.3V Derived (UCFG) Microcontroller fromUSB from USB Prior to communicating over USB, the module’s VDD VUSB associated internal and/or external hardware must be 1.5 kΩ configured. Most of the configuration is performed with VM Isolation Transceiver VP the UCFG register (Register17-2). The separate USB RCV D+ voltage regulator (see Section17.2.2.8 “Internal VMO D- Regulator”) is controlled through the Configuration VPO registers. UOE The UFCG register contains most of the bits that Note: The above setting shows a simplified schematic control the system level behavior of the USB module. for a full-speed configuration using an external These include: transceiver with isolation. • Bus Speed (full speed versus low speed) • On-Chip Pull-up Resistor Enable • On-Chip Transceiver Enable • Ping-Pong Buffer Usage © 2009 Microchip Technology Inc. DS39632E-page 167

PIC18F2455/2550/4455/4550 REGISTER 17-2: UCFG: USB CONFIGURATION REGISTER R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UTEYE UOEMON(1) — UPUEN(2,3) UTRDIS(2) FSEN(2) PPB1 PPB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled bit 6 UOEMON: USB OE Monitor Enable bit(1) 1 = UOE signal active; it indicates intervals during which the D+/D- lines are driving 0 = UOE signal inactive bit 5 Unimplemented: Read as ‘0’ bit 4 UPUEN: USB On-Chip Pull-up Enable bit(2,3) 1 = On-chip pull-up enabled (pull-up on D+ with FSEN=1 or D- with FSEN=0) 0 = On-chip pull-up disabled bit 3 UTRDIS: On-Chip Transceiver Disable bit(2) 1 = On-chip transceiver disabled; digital transceiver interface enabled 0 = On-chip transceiver active bit 2 FSEN: Full-Speed Enable bit(2) 1 = Full-speed device: controls transceiver edge rates; requires input clock at 48MHz 0 = Low-speed device: controls transceiver edge rates; requires input clock at 6MHz bit 1-0 PPB1:PPB0: Ping-Pong Buffers Configuration bits 11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15 10 = Even/Odd ping-pong buffers enabled for all endpoints 01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0 00 = Even/Odd ping-pong buffers disabled Note 1: If UTRDIS is set, the UOE signal will be active independent of the UOEMON bit setting. 2: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These values must be preconfigured prior to enabling the module. 3: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored. There are 6 signals from the module to communicate The VPO and VMO signals are outputs from the SIE to with and control an external transceiver: the external transceiver. The RCV signal is the output from the external transceiver to the SIE; it represents • VM: Input from the single-ended D- line the differential signals from the serial bus translated • VP: Input from the single-ended D+ line into a single pulse train. The VM and VP signals are • RCV: Input from the differential receiver used to report conditions on the serial bus to the SIE • VMO: Output to the differential line driver that can’t be captured with the RCV signal. The • VPO: Output to the differential line driver combinations of states of these signals and their • UOE: Output enable interpretation are listed in Table17-1 and Table17-2. DS39632E-page 168 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 17-1: DIFFERENTIAL OUTPUTS TO 17.2.2.5 Ping-Pong Buffer Configuration TRANSCEIVER The usage of ping-pong buffers is configured using the VPO VMO Bus State PPB1:PPB0 bits. Refer to Section17.4.4 “Ping-Pong Buffering” for a complete explanation of the ping-pong 0 0 Single-Ended Zero buffers. 0 1 Differential ‘0’ 17.2.2.6 USB Output Enable Monitor 1 0 Differential ‘1’ The USB OE monitor provides indication as to whether 1 1 Illegal Condition the SIE is listening to the bus or actively driving the bus. This is enabled by default when using an external TABLE 17-2: SINGLE-ENDED INPUTS transceiver or when UCFG<6>=1. FROM TRANSCEIVER The USB OE monitoring is useful for initial system VP VM Bus State debugging, as well as scope triggering during eye pattern generation tests. 0 0 Single-Ended Zero 0 1 Low Speed 17.2.2.7 Eye Pattern Test Enable 1 0 High Speed An automatic eye pattern test can be generated by the module when the UCFG<7> bit is set. The eye pattern 1 1 Error output will be observable based on module settings, The UOE signal toggles the state of the external trans- meaning that the user is first responsible for configuring ceiver. This line is pulled low by the device to enable the SIE clock settings, pull-up resistor and Transceiver the transmission of data from the SIE to an external mode. In addition, the module has to be enabled. device. Once UTEYE is set, the module emulates a switch from a receive to transmit state and will start transmitting a 17.2.2.3 Internal Pull-up Resistors J-K-J-K bit sequence (K-J-K-J for full speed). The The PIC18FX455/X550 devices have built-in pull-up sequence will be repeated indefinitely while the Eye resistors designed to meet the requirements for Pattern Test mode is enabled. low-speed and full-speed USB. The UPUEN bit Note that this bit should never be set while the module (UCFG<4>) enables the internal pull-ups. Figure17-1 is connected to an actual USB system. This test mode shows the pull-ups and their control. is intended for board verification to aid with USB certi- fication tests. It is intended to show a system developer 17.2.2.4 External Pull-up Resistors the noise integrity of the USB signals which can be External pull-up may also be used if the internal resis- affected by board traces, impedance mismatches and tors are not used. The VUSB pin may be used to pull up proximity to other system components. It does not D+ or D-. The pull-up resistor must be 1.5kΩ (±5%) as properly test the transition from a receive to a transmit required by the USB specifications. Figure17-3 shows state. Although the eye pattern is not meant to replace an example. the more complex USB certification test, it should aid during first order system debugging. FIGURE 17-3: EXTERNAL CIRCUITRY PIC® Host Microcontroller Controller/HUB VUSB 1.5 kΩ D+ D- Note: The above setting shows a typical connection for a full-speed configuration using an on-chip regulator and an external pull-up resistor. © 2009 Microchip Technology Inc. DS39632E-page 169

PIC18F2455/2550/4455/4550 17.2.2.8 Internal Regulator SIE processes additional endpoints (Figure17-4). When the SIE completes using a buffer for reading or The PIC18FX455/X550 devices have a built-in 3.3V reg- writing data, it updates the USTAT register. If another ulator to provide power to the internal transceiver and USB transfer is performed before a transaction provide a source for the internal/external pull-ups. An complete interrupt is serviced, the SIE will store the external 220nF (±20%) capacitor is required for stability. status of the next transfer into the status FIFO. Note: The drive from VUSB is sufficient to only Clearing the transfer complete flag bit, TRNIF, causes drive an external pull-up in addition to the the SIE to advance the FIFO. If the next data in the internal transceiver. FIFO holding register is valid, the SIE will reassert the The regulator can be enabled or disabled through the interrupt within 5TCY of clearing TRNIF. If no additional VREGEN Configuration bit. When enabled, the voltage data is present, TRNIF will remain clear; USTAT data is visible on pin VUSB whenever the USBEN bit is also will no longer be reliable. set. When the regulator is disabled (VREGEN = 0), a 3.3V source must be provided through the VUSB pin for Note: If an endpoint request is received while the the internal transceiver. USTAT FIFO is full, the SIE will automatically issue a NAK back to the Note1: Do not enable the internal regulator if an host. external regulator is connected to VUSB. 2: VDD must be equal to or greater than FIGURE 17-4: USTAT FIFO VUSB at all times, even with the regulator disabled. USTAT from SIE 17.2.3 USB STATUS REGISTER (USTAT) The USB Status register reports the transaction status within the SIE. When the SIE issues a USB transfer complete interrupt, USTAT should be read to determine 4-byte FIFO ClearingTRNIF for USTAT AdvancesFIFO the status of the transfer. USTAT contains the transfer endpoint number, direction and Ping-Pong Buffer Pointer value (if used). Data Bus Note: The data in the USB Status register is valid only when the TRNIF interrupt flag is asserted. The USTAT register is actually a read window into a four-byte status FIFO, maintained by the SIE. It allows the microcontroller to process one transfer while the DS39632E-page 170 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 17-3: USTAT: USB STATUS REGISTER U-0 R-x R-x R-x R-x R-x R-x U-0 — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits (represents the number of the BDT updated by the last USB transfer) 1111 = Endpoint 15 1110 = Endpoint 14 .... 0001 = Endpoint 1 0000 = Endpoint 0 bit 2 DIR: Last BD Direction Indicator bit 1 = The last transaction was an IN token 0 = The last transaction was an OUT or SETUP token bit 1 PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the Odd BD bank 0 = The last transaction was to the Even BD bank bit 0 Unimplemented: Read as ‘0’ Note 1: This bit is only valid for endpoints with available Even and Odd BD registers. © 2009 Microchip Technology Inc. DS39632E-page 171

PIC18F2455/2550/4455/4550 17.2.4 USB ENDPOINT CONTROL transactions. For Endpoint 0, this bit should always be cleared since the USB specifications identify Each of the 16 possible bidirectional endpoints has its Endpoint0 as the default control endpoint. own independent control register, UEPn (where ‘n’ rep- resents the endpoint number). Each register has an The EPOUTEN bit (UEPn<2>) is used to enable or dis- identical complement of control bits. The prototype is able USB OUT transactions from the host. Setting this shown in Register17-4. bit enables OUT transactions. Similarly, the EPINEN bit (UEPn<1>) enables or disables USB IN transactions The EPHSHK bit (UEPn<4>) controls handshaking for from the host. the endpoint; setting this bit enables USB handshaking. Typically, this bit is always set except when using The EPSTALL bit (UEPn<0>) is used to indicate a isochronous endpoints. STALL condition for the endpoint. If a STALL is issued on a particular endpoint, the EPSTALL bit for that end- The EPCONDIS bit (UEPn<3>) is used to enable or point pair will be set by the SIE. This bit remains set disable USB control operations (SETUP) through the until it is cleared through firmware, or until the SIE is endpoint. Clearing this bit enables SETUP transac- reset. tions. Note that the corresponding EPINEN and EPOUTEN bits must be set to enable IN and OUT REGISTER 17-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake enabled 0 = Endpoint handshake disabled (typically used for isochronous endpoints) bit 3 EPCONDIS: Bidirectional Endpoint Control bit If EPOUTEN = 1 and EPINEN = 1: 1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed 0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed bit 2 EPOUTEN: Endpoint Output Enable bit 1 = Endpoint n output enabled 0 = Endpoint n output disabled bit 1 EPINEN: Endpoint Input Enable bit 1 = Endpoint n input enabled 0 = Endpoint n input disabled bit 0 EPSTALL: Endpoint Stall Indicator bit 1 = Endpoint n has issued one or more STALL packets 0 = Endpoint n has not issued any STALL packets DS39632E-page 172 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 17.2.5 USB ADDRESS REGISTER FIGURE 17-5: IMPLEMENTATION OF (UADDR) USB RAM IN DATA MEMORY SPACE The USB Address register contains the unique USB address that the peripheral will decode when active. UADDR is reset to 00h when a USB Reset is received, 000h indicated by URSTIF, or when a Reset is received from the microcontroller. The USB address must be written Banks 0 User Data by the microcontroller during the USB setup phase to 3 (enumeration) as part of the Microchip USB firmware support. 3FFh Buffer Descriptors, 400h 17.2.6 USB FRAME NUMBER REGISTERS (UFRMH:UFRML) USB Data or User Data 4FFh 500h The Frame Number registers contain the 11-bit frame number. The low-order byte is contained in UFRML, Banks 4 USB Data or while the three high-order bits are contained in to 7 User Data UFRMH. The register pair is updated with the current (USB RAM) frame number whenever a SOF token is received. For the microcontroller, these registers are read-only. The Frame Number register is primarily used for 7FFh isochronous transfers. 800h 17.3 USB RAM USB data moves between the microcontroller core and the SIE through a memory space known as the USB RAM. This is a special dual port memory that is Banks 8 Unused mapped into the normal data memory space in Banks4 to 14 through 7 (400h to 7FFh) for a total of 1Kbyte (Figure17-5). Bank 4 (400h through 4FFh) is used specifically for endpoint buffer control, while Banks 5 through 7 are available for USB data. Depending on the type of buffering being used, all but 8 bytes of Bank 4 may also F00h be available for use as USB buffer space. Bank15 F60h SFRs Although USB RAM is available to the microcontroller FFFh as data memory, the sections that are being accessed by the SIE should not be accessed by the microcontroller. A semaphore mechanism is used to determine the access to a particular buffer at any given time. This is discussed in Section17.4.1.1 “Buffer Ownership”. © 2009 Microchip Technology Inc. DS39632E-page 173

PIC18F2455/2550/4455/4550 17.4 Buffer Descriptors and the Buffer FIGURE 17-6: EXAMPLE OF A BUFFER Descriptor Table DESCRIPTOR Address Registers Contents The registers in Bank 4 are used specifically for end- point buffer control in a structure known as the Buffer 400h BD0STAT (xxh) Descriptor Table (BDT). This provides a flexible method Buffer 401h BD0CNT 40h Size of Block for users to construct and control endpoint buffers of Descriptor 402h BD0ADRL 00h various lengths and configuration. Starting 403h BD0ADRH 05h Address The BDT is composed of Buffer Descriptors (BD) which are used to define and control the actual buffers in the 500h USB RAM space. Each BD, in turn, consists of four reg- isters, where n represents one of the 64 possible BDs (range of 0 to 63): Buffer USB Data • BDnSTAT: BD Status register • BDnCNT: BD Byte Count register 53Fh • BDnADRL: BD Address Low register Note: Memory regions not to scale. • BDnADRH: BD Address High register BDs always occur as a four-byte block in the sequence, Unlike other control registers, the bit configuration for BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address the BDnSTAT register is context sensitive. There are of BDnSTAT is always an offset of (4n – 1) (in hexa- two distinct configurations, depending on whether the decimal) from 400h, with n being the buffer descriptor microcontroller or the USB module is modifying the BD number. and buffer at a particular time. Only three bit definitions Depending on the buffering configuration used are shared between the two. (Section17.4.4 “Ping-Pong Buffering”), there are up 17.4.1.1 Buffer Ownership to 32, 33 or 64 sets of buffer descriptors. At a minimum, the BDT must be at least 8 bytes long. This is because Because the buffers and their BDs are shared between the USB specification mandates that every device must the CPU and the USB module, a simple semaphore have Endpoint 0 with both input and output for initial mechanism is used to distinguish which is allowed to setup. Depending on the endpoint and buffering update the BD and associated buffers in memory. configuration, the BDT can be as long as 256 bytes. This is done by using the UOWN bit (BDnSTAT<7>) as Although they can be thought of as Special Function a semaphore to distinguish which is allowed to update Registers, the Buffer Descriptor Status and Address the BD and associated buffers in memory. UOWN is the registers are not hardware mapped, as conventional only bit that is shared between the two configurations microcontroller SFRs in Bank 15 are. If the endpoint cor- of BDnSTAT. responding to a particular BD is not enabled, its registers When UOWN is clear, the BD entry is “owned” by the are not used. Instead of appearing as unimplemented microcontroller core. When the UOWN bit is set, the BD addresses, however, they appear as available RAM. entry and the buffer memory are “owned” by the USB Only when an endpoint is enabled by setting the peripheral. The core should not modify the BD or its UEPn<1> bit does the memory at those addresses corresponding data buffer during this time. Note that become functional as BD registers. As with any address the microcontroller core can still read BDnSTAT while in the data memory space, the BD registers have an the SIE owns the buffer and vice versa. indeterminate value on any device Reset. The buffer descriptors have a different meaning based An example of a BD for a 64-byte buffer, starting at on the source of the register update. Prior to placing 500h, is shown in Figure17-6. A particular set of BD ownership with the USB peripheral, the user can con- registers is only valid if the corresponding endpoint has figure the basic operation of the peripheral through the been enabled using the UEPn register. All BD registers BDnSTAT bits. During this time, the byte count and buf- are available in USB RAM. The BD for each endpoint fer location registers can also be set. should be set up prior to enabling the endpoint. When UOWN is set, the user can no longer depend on 17.4.1 BD STATUS AND CONFIGURATION the values that were written to the BDs. From this point, the SIE updates the BDs as necessary, overwriting the Buffer descriptors not only define the size of an end- original BD values. The BDnSTAT register is updated point buffer, but also determine its configuration and by the SIE with the token PID and the transfer count, control. Most of the configuration is done with the BD BDnCNT, is updated. Status register, BDnSTAT. Each BD has its own unique and correspondingly numbered BDnSTAT register. DS39632E-page 174 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 The BDnSTAT byte of the BDT should always be the the SIE. When enabled, it checks the data packet’s par- last byte updated when preparing to arm an endpoint. ity against the value of DTS (BDnSTAT<6>). If a packet The SIE will clear the UOWN bit when a transaction arrives with an incorrect synchronization, the data will has completed. The only exception to this is when KEN essentially be ignored. It will not be written to the USB is enabled and/or BSTALL is enabled. RAM and the USB transfer complete interrupt flag will not be set. The SIE will send an ACK token back to the No hardware mechanism exists to block access when host to Acknowledge receipt, however. The effects of the UOWN bit is set. Thus, unexpected behavior can the DTSEN bit on the SIE are summarized in occur if the microcontroller attempts to modify memory Table17-3. when the SIE owns it. Similarly, reading such memory may produce inaccurate data until the USB peripheral The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides returns ownership to the microcontroller. support for control transfers, usually one-time stalls on Endpoint 0. It also provides support for the 17.4.1.2 BDnSTAT Register (CPU Mode) SET_FEATURE/CLEAR_FEATURE commands speci- When UOWN = 0, the microcontroller core owns the fied in Chapter 9 of the USB specification; typically, BD. At this point, the other seven bits of the register continuous STALLs to any endpoint other than the take on control functions. default control endpoint. The Keep Enable bit, KEN (BDnSTAT<5>), determines The BSTALL bit enables buffer stalls. Setting BSTALL if a BD stays enabled. If the bit is set, once the UOWN causes the SIE to return a STALL token to the host if a bit is set, it will remain owned by the SIE independent received token would use the BD in that location. The of the endpoint activity. This prevents the USTAT FIFO EPSTALL bit in the corresponding UEPn control regis- from being updated, as well as the transaction ter is set and a STALL interrupt is generated when a complete interrupt from being set for the endpoint. This STALL is issued to the host. The UOWN bit remains set feature should only be enabled when the Streaming and the BDs are not changed unless a SETUP token is Parallel Port is selected as the data I/O channel instead received. In this case, the STALL condition is cleared of USB RAM. and the ownership of the BD is returned to the microcontroller core. The Address Increment Disable bit, INCDIS (BDnSTAT<4>), controls the SIE’s automatic address The BD9:BD8 bits (BDnSTAT<1:0>) store the two most significant digits of the SIE byte count; the lower 8 digits increment function. Setting INCDIS disables the are stored in the corresponding BDnCNT register. See auto-increment of the buffer address by the SIE for Section17.4.2 “BD Byte Count” for more each byte transmitted or received. This feature should information. only be enabled when using the Streaming Parallel Port, where each data byte is processed to or from the same memory location. The Data Toggle Sync Enable bit, DTSEN (BDnSTAT<3>), controls data toggle parity checking. Setting DTSEN enables data toggle synchronization by TABLE 17-3: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION BDnSTAT Settings Device Response after Receiving Packet OUT Packet from Host DTSEN DTS Handshake UOWN TRNIF BDnSTAT and USTAT Status DATA0 1 0 ACK 0 1 Updated DATA1 1 0 ACK 1 0 Not Updated DATA1 1 1 ACK 0 1 Updated DATA0 1 1 ACK 1 0 Not Updated Either 0 x ACK 0 1 Updated Either, with error x x NAK 1 0 Not Updated Legend: x = don’t care © 2009 Microchip Technology Inc. DS39632E-page 175

PIC18F2455/2550/4455/4550 REGISTER 17-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x UOWN(1) DTS(2) KEN INCDIS DTSEN BSTALL BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit(1) 0 = The microcontroller core owns the BD and its corresponding buffer bit 6 DTS: Data Toggle Synchronization bit(2) 1 = Data 1 packet 0 = Data 0 packet bit 5 KEN: BD Keep Enable bit 1 = USB will keep the BD indefinitely once UOWN is set (required for SPP endpoint configuration) 0 = USB will hand back the BD once a token has been processed bit 4 INCDIS: Address Increment Disable bit 1 = Address increment disabled (required for SPP endpoint configuration) 0 = Address increment enabled bit 3 DTSEN: Data Toggle Synchronization Enable bit 1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored except for a SETUP transaction, which is accepted even if the data toggle bits do not match 0 = No data toggle synchronization is performed bit 2 BSTALL: Buffer Stall Enable bit 1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the given location (UOWN bit remains set, BD value is unchanged) 0 = Buffer stall disabled bit 1-0 BC9:BC8: Byte Count 9 and 8 bits The byte count bits represent the number of bytes that will be transmitted for an IN token or received during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023. Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module. 2: This bit is ignored unless DTSEN=1. DS39632E-page 176 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 17.4.1.3 BDnSTAT Register (SIE Mode) The 10-bit byte count is distributed over two registers. The lower 8 bits of the count reside in the BDnCNT When the BD and its buffer are owned by the SIE, most register. The upper two bits reside in BDnSTAT<1:0>. of the bits in BDnSTAT take on a different meaning. The This represents a valid byte range of 0 to 1023. configuration is shown in Register17-6. Once UOWN is set, any data or control settings previously written 17.4.3 BD ADDRESS VALIDATION there by the user will be overwritten with data from the SIE. The BD Address register pair contains the starting RAM address location for the corresponding endpoint buffer. The BDnSTAT register is updated by the SIE with the For an endpoint starting location to be valid, it must fall token Packet Identifier (PID) which is stored in in the range of the USB RAM, 400h to 7FFh. No BDnSTAT<5:3>. The transfer count in the correspond- mechanism is available in hardware to validate the BD ing BDnCNT register is updated. Values that overflow address. the 8-bit register carry over to the two most significant digits of the count, stored in BDnSTAT<1:0>. If the value of the BD address does not point to an address in the USB RAM, or if it points to an address 17.4.2 BD BYTE COUNT within another endpoint’s buffer, data is likely to be lost or overwritten. Similarly, overlapping a receive buffer The byte count represents the total number of bytes (OUT endpoint) with a BD location in use can yield that will be transmitted during an IN transfer. After an IN unexpected results. When developing USB transfer, the SIE will return the number of bytes sent to applications, the user may want to consider the the host. inclusion of software-based address validation in their For an OUT transfer, the byte count represents the code. maximum number of bytes that can be received and stored in USB RAM. After an OUT transfer, the SIE will return the actual number of bytes received. If the number of bytes received exceeds the corresponding byte count, the data packet will be rejected and a NAK handshake will be generated. When this happens, the byte count will not be updated. REGISTER 17-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE MICROCONTROLLER) R/W-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x UOWN — PID3 PID2 PID1 PID0 BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit 1 = The SIE owns the BD and its corresponding buffer bit 6 Reserved: Not written by the SIE bit 5-2 PID3:PID0: Packet Identifier bits The received token PID value of the last transfer (IN, OUT or SETUP transactions only). bit 1-0 BC9:BC8: Byte Count 9 and 8 bits These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer and the actual number of bytes transmitted on an IN transfer. © 2009 Microchip Technology Inc. DS39632E-page 177

PIC18F2455/2550/4455/4550 17.4.4 PING-PONG BUFFERING the completion of a transaction (UOWN cleared by the SIE), the pointer is toggled to the Odd BD. After the An endpoint is defined to have a ping-pong buffer when completion of the next transaction, the pointer is it has two sets of BD entries: one set for an Even toggled back to the Even BD and so on. transfer and one set for an Odd transfer. This allows the CPU to process one BD while the SIE is processing the The Even/Odd status of the last transaction is stored in other BD. Double-buffering BDs in this way allows for the PPBI bit of the USTAT register. The user can reset maximum throughput to/from the USB. all Ping-Pong Pointers to Even using the PPBRST bit. The USB module supports four modes of operation: Figure17-7 shows the four different modes of operation and how USB RAM is filled with the BDs. • No ping-pong support • Ping-pong buffer support for OUT Endpoint 0 only BDs have a fixed relationship to a particular endpoint, depending on the buffering configuration. The mapping • Ping-pong buffer support for all endpoints of BDs to endpoints is detailed in Table17-4. This • Ping-pong buffer support for all other Endpoints relationship also means that gaps may occur in the except Endpoint 0 BDT if endpoints are not enabled contiguously. This The ping-pong buffer settings are configured using the theoretically means that the BDs for disabled endpoints PPB1:PPB0 bits in the UCFG register. could be used as buffer space. In practice, users should avoid using such spaces in the BDT unless a The USB module keeps track of the Ping-Pong Pointer method of validating BD addresses is implemented. individually for each endpoint. All pointers are initially reset to the Even BD when the module is enabled. After FIGURE 17-7: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES PPB1:PPB0=00 PPB1:PPB0=01 PPB1:PPB0=10 PPB1:PPB0=11 No Ping-Pong Ping-Pong Buffer Ping-Pong Buffers Ping-Pong Buffers Buffers on EP0 OUT on all EPs on all other EPs except EP0 400h 400h 400h 400h EP0 OUT EP0 OUT Even EP0 OUT Even EP0 OUT Descriptor Descriptor Descriptor Descriptor EP0 IN EP0 OUT Odd EP0 OUT Odd EP0 IN Descriptor Descriptor Descriptor Descriptor EP1 OUT EP0 IN Even EP1 OUT Even Descriptor EP0 IN Descriptor Descriptor Descriptor EP1 IN EP0 IN Odd EP1 OUT Odd Descriptor EP1 OUT Descriptor Descriptor Descriptor EP1 OUT Even EP1 IN Even EP1 IN Descriptor Descriptor Descriptor EP1 OUT Odd EP1 IN Odd EP15 IN Descriptor Descriptor Descriptor 47Fh EP1 IN Even EP15 IN Descriptor 483h Descriptor EP1 IN Odd Descriptor Available as Available Data RAM as EP15 IN Odd Data RAM Descriptor 4F7h Available as Data RAM EP15 IN Odd Descriptor 4FFh 4FFh 4FFh 4FFh Maximum Memory Maximum Memory Maximum Memory Maximum Memory Used: 128 bytes Used: 132 bytes Used: 256 bytes Used: 248 bytes Maximum BDs: Maximum BDs: Maximum BDs: Maximum BDs: 32 (BD0 to BD31) 33 (BD0 to BD32) 64 (BD0 to BD63) 62 (BD0 to BD61) Note: Memory area not shown to scale. DS39632E-page 178 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 17-4: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Mode 3 Mode 0 Mode 1 Mode 2 Endpoint (Ping-Pong on all other EPs, (No Ping-Pong) (Ping-Pong on EP0 OUT) (Ping-Pong on all EPs) except EP0) Out In Out In Out In Out In 0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1 1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O) 2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O) 3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O) 4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O) 5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O) 6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O) 7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O) 8 16 17 17 18 32 (E), 33 (O) 34 (E), 35 (O) 30 (E), 31 (O) 32 (E), 33 (O) 9 18 19 19 20 36 (E), 37 (O) 38 (E), 39 (O) 34 (E), 35 (O) 36 (E), 37 (O) 10 20 21 21 22 40 (E), 41 (O) 42 (E), 43 (O) 38 (E), 39 (O) 40 (E), 41 (O) 11 22 23 23 24 44 (E), 45 (O) 46 (E), 47 (O) 42 (E), 43 (O) 44 (E), 45 (O) 12 24 25 25 26 48 (E), 49 (O) 50 (E), 51 (O) 46 (E), 47 (O) 48 (E), 49 (O) 13 26 27 27 28 52 (E), 53 (O) 54 (E), 55 (O) 50 (E), 51 (O) 52 (E), 53 (O) 14 28 29 29 30 56 (E), 57 (O) 58 (E), 59 (O) 54 (E), 55 (O) 56 (E), 57 (O) 15 30 31 31 32 60 (E), 61 (O) 62 (E), 63 (O) 58 (E), 59 (O) 60 (E), 61 (O) Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer TABLE 17-5: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BDnSTAT(1) UOWN DTS(4) PID3(2) PID2(2) PID1(2) PID0(2) BC9 BC8 KEN(3) INCDIS(3) DTSEN(3) BSTALL(3) BDnCNT(1) Byte Count BDnADRL(1) Buffer Address Low BDnADRH(1) Buffer Address High Note 1: For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx). 2: Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values written for KEN, INCDIS, DTSEN and BSTALL are no longer valid. 3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the BDnSTAT register are used to configure the KEN, INCDIS, DTSEN and BSTALL settings. 4: This bit is ignored unless DTSEN = 1. © 2009 Microchip Technology Inc. DS39632E-page 179

PIC18F2455/2550/4455/4550 17.5 USB Interrupts Figure17-8 shows the interrupt logic for the USB module. There are two layers of interrupt registers in The USB module can generate multiple interrupt con- the USB module. The top level consists of overall USB ditions. To accommodate all of these interrupt sources, status interrupts; these are enabled and flagged in the the module is provided with its own interrupt logic UIE and UIR registers, respectively. The second level structure, similar to that of the microcontroller. USB consists of USB error conditions, which are enabled interrupts are enabled with one set of control registers and flagged in the UEIR and UEIE registers. An and trapped with a separate set of flag registers. All interrupt condition in any of these triggers a USB Error sources are funneled into a single USB interrupt Interrupt Flag (UERRIF) in the top level. request, USBIF (PIR2<5>), in the microcontroller’s Interrupts may be used to trap routine events in a USB interrupt logic. transaction. Figure17-9 shows some common events within a USB frame and their corresponding interrupts. FIGURE 17-8: USB INTERRUPT LOGIC FUNNEL Second Level USB Interrupts Top Level USB Interrupts (USB Error Conditions) (USB Status Interrupts) UEIR (Flag) and UEIE (Enable) Registers UIR (Flag) and UIE (Enable) Registers SOFIF SOFIE BTSEF BTSEE TRNIF USBIF TRNIE BTOEF BTOEE IDLEIF DFN8EF IDLEIE DFN8EE UERRIF CRC16EF UERRIE CRC16EE STALLIF CRC5EF STALLIE CRC5EE PIDEF PIDEE ACTVIF ACTVIE URSTIF URSTIE FIGURE 17-9: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS From Host From Host To Host SETUPToken Data ACK Set TRNIF From Host To Host From Host USB Reset IN Token Data ACK Set TRNIF URSTIF From Host From Host To Host Start-Of-Frame OUT Token Empty Data ACK Set TRNIF SOFIF Transaction Transaction Complete RESET SOF SETUP DATA STATUS SOF Differential Data Control Transfer(1) 1ms Frame Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames. DS39632E-page 180 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 17.5.1 USB INTERRUPT STATUS When the USB module is in the Low-Power Suspend REGISTER (UIR) mode (UCON<1> = 1), the SIE does not get clocked. When in this state, the SIE cannot process packets, The USB Interrupt Status register (Register17-7) con- and therefore, cannot detect new interrupt conditions tains the flag bits for each of the USB status interrupt other than the Activity Detect Interrupt, ACTVIF. The sources. Each of these sources has a corresponding ACTVIF bit is typically used by USB firmware to detect interrupt enable bit in the UIE register. All of the USB when the microcontroller should bring the USB module status flags are ORed together to generate the USBIF out of the Low-Power Suspend mode (UCON<1> = 0). interrupt flag for the microcontroller’s interrupt funnel. Once an interrupt bit has been set by the SIE, it must be cleared by software by writing a ‘0’. The flag bits can also be set in software which can aid in firmware debugging. REGISTER 17-7: UIR: USB INTERRUPT STATUS REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 — SOFIF STALLIF IDLEIF(1) TRNIF(2) ACTVIF(3) UERRIF(4) URSTIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token received by the SIE 0 = No Start-Of-Frame token received by the SIE bit 5 STALLIF: A STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the SIE 0 = A STALL handshake has not been sent bit 4 IDLEIF: Idle Detect Interrupt bit(1) 1 = Idle condition detected (constant Idle state of 3ms or more) 0 = No Idle condition detected bit 3 TRNIF: Transaction Complete Interrupt bit(2) 1 = Processing of pending transaction is complete; read USTAT register for endpoint information 0 = Processing of pending transaction is not complete or no transaction is pending bit 2 ACTVIF: Bus Activity Detect Interrupt bit(3) 1 = Activity on the D+/D- lines was detected 0 = No activity detected on the D+/D- lines bit 1 UERRIF: USB Error Condition Interrupt bit(4) 1 = An unmasked error condition has occurred 0 = No unmasked error condition has occurred. bit 0 URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset occurred; 00h is loaded into UADDR register 0 = No USB Reset has occurred Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode. 2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens). 3: This bit is typically unmasked only following the detection of a UIDLE interrupt event. 4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and cannot be set or cleared by the user. © 2009 Microchip Technology Inc. DS39632E-page 181

PIC18F2455/2550/4455/4550 17.5.1.1 Bus Activity Detect Interrupt Bit immediately operational while waiting for the 96 MHz (ACTVIF) PLL to lock. The application code should clear the ACTVIF flag as shown in Example17-1. The ACTVIF bit cannot be cleared immediately after the USB module wakes up from Suspend or while the Note: Only one ACTVIF interrupt is generated USB module is suspended. A few clock cycles are when resuming from the USB bus Idle required to synchronize the internal hardware state condition. If user firmware clears the machine before the ACTVIF bit can be cleared by ACTVIF bit, the bit will not immediately firmware. Clearing the ACTVIF bit before the internal become set again, even when there is hardware is synchronized may not have an effect on continuous bus traffic. Bus traffic must the value of ACTVIF. Additionally, if the USB module cease long enough to generate another uses the clock from the 96 MHz PLL source, then after IDLEIF condition before another ACTVIF clearing the SUSPND bit, the USB module may not be interrupt can be generated. EXAMPLE 17-1: CLEARING ACTVIF BIT (UIR<2>) Assembly: BCF UCON, SUSPND Loop: BCF UIR, ACTVIF BTFSC UIR, ACTVIF BRA Loop Done: C: UCONbits.SUSPND = 0; while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; } DS39632E-page 182 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 17.5.2 USB INTERRUPT ENABLE The values in this register only affect the propagation REGISTER (UIE) of an interrupt condition to the microcontroller’s inter- rupt logic. The flag bits are still set by their interrupt The USB Interrupt Enable register (Register17-8) conditions, allowing them to be polled and serviced contains the enable bits for the USB status interrupt without actually generating an interrupt. sources. Setting any of these bits will enable the respective interrupt source in the UIR register. REGISTER 17-8: UIE: USB INTERRUPT ENABLE REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOFIE: Start-Of-Frame Token Interrupt Enable bit 1 = Start-Of-Frame token interrupt enabled 0 = Start-Of-Frame token interrupt disabled bit 5 STALLIE: STALL Handshake Interrupt Enable bit 1 = STALL interrupt enabled 0 = STALL interrupt disabled bit 4 IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle detect interrupt enabled 0 = Idle detect interrupt disabled bit 3 TRNIE: Transaction Complete Interrupt Enable bit 1 = Transaction interrupt enabled 0 = Transaction interrupt disabled bit 2 ACTVIE: Bus Activity Detect Interrupt Enable bit 1 = Bus activity detect interrupt enabled 0 = Bus activity detect interrupt disabled bit 1 UERRIE: USB Error Interrupt Enable bit 1 = USB error interrupt enabled 0 = USB error interrupt disabled bit 0 URSTIE: USB Reset Interrupt Enable bit 1 = USB Reset interrupt enabled 0 = USB Reset interrupt disabled © 2009 Microchip Technology Inc. DS39632E-page 183

PIC18F2455/2550/4455/4550 17.5.3 USB ERROR INTERRUPT STATUS Each error bit is set as soon as the error condition is REGISTER (UEIR) detected. Thus, the interrupt will typically not correspond with the end of a token being processed. The USB Error Interrupt Status register (Register17-9) contains the flag bits for each of the error sources Once an interrupt bit has been set by the SIE, it must within the USB peripheral. Each of these sources is be cleared by software by writing a ‘0’. controlled by a corresponding interrupt enable bit in the UEIE register. All of the USB error flags are ORed together to generate the USB Error Interrupt Flag (UERRIF) at the top level of the interrupt logic. REGISTER 17-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BTSEF: Bit Stuff Error Flag bit 1 = A bit stuff error has been detected 0 = No bit stuff error bit 6-5 Unimplemented: Read as ‘0’ bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed) 0 = No bus turnaround time-out bit 3 DFN8EF: Data Field Size Error Flag bit 1 = The data field was not an integral number of bytes 0 = The data field was an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = The CRC16 failed 0 = The CRC16 passed bit 1 CRC5EF: CRC5 Host Error Flag bit 1 = The token packet was rejected due to a CRC5 error 0 = The token packet was accepted bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed DS39632E-page 184 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 17.5.4 USB ERROR INTERRUPT ENABLE As with the UIE register, the enable bits only affect the REGISTER (UEIE) propagation of an interrupt condition to the micro- controller’s interrupt logic. The flag bits are still set by The USB Error Interrupt Enable register their interrupt conditions, allowing them to be polled (Register17-10) contains the enable bits for each of and serviced without actually generating an interrupt. the USB error interrupt sources. Setting any of these bits will enable the respective error interrupt source in the UEIR register to propagate into the UERR bit at the top level of the interrupt logic. REGISTER 17-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Bit stuff error interrupt enabled 0 = Bit stuff error interrupt disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Bus turnaround time-out error interrupt enabled 0 = Bus turnaround time-out error interrupt disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Data field size error interrupt enabled 0 = Data field size error interrupt disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16 failure interrupt enabled 0 = CRC16 failure interrupt disabled bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = CRC5 host error interrupt enabled 0 = CRC5 host error interrupt disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = PID check failure interrupt enabled 0 = PID check failure interrupt disabled © 2009 Microchip Technology Inc. DS39632E-page 185

PIC18F2455/2550/4455/4550 17.6 USB Power Modes The application should never source any current onto the 5V VBUS pin of the USB cable. Many USB applications will likely have several different sets of power requirements and configuration. The FIGURE 17-11: SELF-POWER ONLY most common power modes encountered are Bus Power Only, Self-Power Only and Dual Power with Attach Sense Self-Power Dominance. The most common cases are VBUS I/O pin presented here. ~5V 100kΩ VSELF VDD 17.6.1 BUS POWER ONLY ~5V In Bus Power Only mode, all power for the application is drawn from the USB (Figure17-10). This is 100kΩ VUSB effectively the simplest power method for the device. VSS In order to meet the inrush current requirements of the USB 2.0 specifications, the total effective capacitance appearing across VBUS and ground must be no more than 10μF. If not, some kind of inrush limiting is required. For more details, see Section 7.2.4 of the 17.6.3 DUAL POWER WITH SELF-POWER USB 2.0 specification. DOMINANCE According to the USB 2.0 specification, all USB devices Some applications may require a dual power option. must also support a Low-Power Suspend mode. In the This allows the application to use internal power pri- USB Suspend mode, devices must consume no more marily, but switch to power from the USB when no inter- than 2.5mA from the 5V VBUS line of the USB cable. nal power is available. Figure17-12 shows a simple The host signals the USB device to enter the Suspend Dual Power with Self-Power Dominance example, mode by stopping all USB traffic to that device for more which automatically switches between Self-Power Only than 3ms. This condition will cause the IDLEIF bit in and USB Bus Power Only modes. the UIR register to become set. Dual power devices also must meet all of the special During the USB Suspend mode, the D+ or D- pull-up requirements for inrush current and Suspend mode resistor must remain active, which will consume some current and must not enable the USB module until of the allowed suspend current: 2.5 mA budget. VBUS is driven high. For descriptions of those require- ments, see Section17.6.1 “Bus Power Only” and FIGURE 17-10: BUS POWER ONLY Section17.6.2 “Self-Power Only”. Additionally, dual power devices must never source current onto the 5V VBUS pin of the USB cable. V~B5UVS VDD FIGURE 17-12: DUAL POWER EXAMPLE VUSB 100kΩ Attach Sense I/O pin VSS VBUS VDD ~5V 100kΩ VUSB 17.6.2 SELF-POWER ONLY In Self-Power Only mode, the USB application provides VSELF VSS ~5V its own power, with very little power being pulled from the USB. Figure17-11 shows an example. Note that an attach indication is added to indicate when the USB has been connected and the host is actively powering VBUS. In order to meet compliance specifications, the USB Note: Users should keep in mind the limits for module (and the D+ or D- pull-up resistor) should not devices drawing power from the USB. be enabled until the host actively drives VBUS high. One According to USB specification 2.0, this of the I/O pins may be used for this purpose. cannot exceed 100mA per low-power device or 500mA per high-power device. DS39632E-page 186 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 17.7 Streaming Parallel Port Refer to Section18.0 “Streaming Parallel Port” for more information about the SPP. The Streaming Parallel Port (SPP) is an alternate route option for data besides USB RAM. Using the SPP, an Note1: If an endpoint is configured to use the endpoint can be configured to send data to or receive SPP, the SPP module must also be data directly from external hardware. configured to use the USB module. Otherwise, unexpected operation may This methodology presents design possibilities where occur. the microcontroller acts as a data manager, allowing the SPP to pass large blocks of data without the micro- 2: In addition, if an endpoint is configured to controller actually processing it. An application use the SPP, the data transfer type of that example might include a data acquisition system, endpoint must be isochronous only. where data is streamed from an external FIFO through USB to the host computer. In this case, endpoint control is managed by the microcontroller and raw data 17.8 Oscillator movement is processed externally. The SPP is enabled as a USB endpoint port through The USB module has specific clock requirements. For the associated endpoint buffer descriptor. The endpoint full-speed operation, the clock source must be 48MHz. must be enabled as follows: Even so, the microcontroller core and other peripherals are not required to run at that clock speed or even from 1. Set BDnADRL:BDnADRH to point to FFFFh. the same clock source. Available clocking options are 2. Set the KEN bit (BDnSTAT<5>) to let SIE keep described in detail in Section2.3 “Oscillator Settings control of the buffer. for USB”. 3. Set the INCDIS bit (BDnSTAT<4>) to disable automatic address increment. TABLE 17-6: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1) Details on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module. Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table17-5. © 2009 Microchip Technology Inc. DS39632E-page 187

PIC18F2455/2550/4455/4550 Details on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 page PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56 UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 57 UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 57 USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — 57 UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 57 UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 57 UFRMH — — — — — FRM10 FRM9 FRM8 57 UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 57 UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 57 UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 57 UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 57 UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module. Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table17-5. DS39632E-page 188 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 17.10 Overview of USB 17.10.3 TRANSFERS This section presents some of the basic USB concepts There are four transfer types defined in the USB and useful information necessary to design a USB specification. device. Although much information is provided in this • Isochronous: This type provides a transfer section, there is a plethora of information provided method for large amounts of data (up to within the USB specifications and class specifications. 1023bytes) with timely delivery ensured; Thus, the reader is encouraged to refer to the USB however, the data integrity is not ensured. This is specifications for more information (www.usb.org). If good for streaming applications where small data you are very familiar with the details of USB, then this loss is not critical, such as audio. section serves as a basic, high-level refresher of USB. • Bulk: This type of transfer method allows for large amounts of data to be transferred with ensured 17.10.1 LAYERED FRAMEWORK data integrity; however, the delivery timeliness is USB device functionality is structured into a layered not ensured. framework graphically shown in Figure17-13. Each • Interrupt: This type of transfer provides for level is associated with a functional level within the ensured timely delivery for small blocks of data, device. The highest layer, other than the device, is the plus data integrity is ensured. configuration. A device may have multiple configura- • Control: This type provides for device setup tions. For example, a particular device may have control. multiple power requirements based on Self-Power Only or Bus Power Only modes. While full-speed devices support all transfer types, low-speed devices are limited to interrupt and control For each configuration, there may be multiple transfers only. interfaces. Each interface could support a particular mode of that configuration. 17.10.4 POWER Below the interface is the endpoint(s). Data is directly Power is available from the Universal Serial Bus. The moved at this level. There can be as many as USB specification defines the bus power requirements. 16bidirectional endpoints. Endpoint 0 is always a Devices may either be self-powered or bus powered. control endpoint and by default, when the device is on Self-powered devices draw power from an external the bus, Endpoint 0 must be available to configure the source, while bus powered devices use power supplied device. from the bus. 17.10.2 FRAMES Information communicated on the bus is grouped into 1ms time slots, referred to as frames. Each frame can contain many transactions to various devices and endpoints. Figure17-9 shows an example of a transaction within a frame. FIGURE 17-13: USB LAYERS Device To other Configurations (if any) Configuration To other Interfaces (if any) Interface Interface Endpoint Endpoint Endpoint Endpoint Endpoint © 2009 Microchip Technology Inc. DS39632E-page 189

PIC18F2455/2550/4455/4550 The USB specification limits the power taken from the 17.10.6.2 Configuration Descriptor bus. Each device is ensured 100mA at approximately The configuration descriptor provides information on 5V (one unit load). Additional power may be requested, the power requirements of the device and how many up to a maximum of 500mA. Note that power above different interfaces are supported when in this configu- one unit load is a request and the host or hub is not ration. There may be more than one configuration for a obligated to provide the extra current. Thus, a device device (i.e., low-power and high-power configurations). capable of consuming more than one unit load must be able to maintain a low-power configuration of a one unit 17.10.6.3 Interface Descriptor load or less, if necessary. The interface descriptor details the number of end- The USB specification also defines a Suspend mode. points used in this interface, as well as the class of the In this situation, current must be limited to 2.5 mA, interface. There may be more than one interface for a averaged over 1 second. A device must enter a configuration. Suspend state after 3ms of inactivity (i.e., no SOF tokens for 3ms). A device entering Suspend mode 17.10.6.4 Endpoint Descriptor must drop current consumption within 10ms after The endpoint descriptor identifies the transfer type Suspend. Likewise, when signaling a wake-up, the (Section17.10.3 “Transfers”) and direction, as well device must signal a wake-up within 10ms of drawing as some other specifics for the endpoint. There may be current above the Suspend limit. many endpoints in a device and endpoints may be 17.10.5 ENUMERATION shared in different configurations. When the device is initially attached to the bus, the host 17.10.6.5 String Descriptor enters an enumeration process in an attempt to identify Many of the previous descriptors reference one or the device. Essentially, the host interrogates the device, more string descriptors. String descriptors provide gathering information such as power consumption, data human readable information about the layer rates and sizes, protocol and other descriptive (Section17.10.1 “Layered Framework”) they information; descriptors contain this information. A describe. Often these strings show up in the host to typical enumeration process would be as follows: help the user identify the device. String descriptors are 1. USB Reset: Reset the device. Thus, the device generally optional to save memory and are encoded in is not configured and does not have an address a unicode format. (address 0). 2. Get Device Descriptor: The host requests a 17.10.7 BUS SPEED small portion of the device descriptor. Each USB device must indicate its bus presence and 3. USB Reset: Reset the device again. speed to the host. This is accomplished through a 4. Set Address: The host assigns an address to the 1.5kΩ resistor which is connected to the bus at the device. time of the attachment event. 5. Get Device Descriptor: The host retrieves the Depending on the speed of the device, the resistor device descriptor, gathering info such as either pulls up the D+ or D- line to 3.3V. For a manufacturer, type of device, maximum control low-speed device, the pull-up resistor is connected to packet size. the D- line. For a full-speed device, the pull-up resistor 6. Get configuration descriptors. is connected to the D+ line. 7. Get any other descriptors. 17.10.8 CLASS SPECIFICATIONS AND 8. Set a configuration. DRIVERS The exact enumeration process depends on the host. USB specifications include class specifications which 17.10.6 DESCRIPTORS operating system vendors optionally support. Examples of classes include Audio, Mass Storage, There are eight different standard descriptor types of Communications and Human Interface (HID). In most which five are most important for this device. cases, a driver is required at the host side to ‘talk’ to the USB device. In custom applications, a driver may need 17.10.6.1 Device Descriptor to be developed. Fortunately, drivers are available for The device descriptor provides general information, most common host systems for the most common such as manufacturer, product number, serial number, classes of devices. Thus, these drivers can be reused. the class of the device and the number of configurations. There is only one device descriptor. DS39632E-page 190 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 18.0 STREAMING PARALLEL PORT In addition, the SPP can provide time multiplexed addressing information along with the data by using the Note: The Streaming Parallel Port is only second strobe output. Thus, the USB endpoint number available on 40/44-pin devices. can be written in conjunction with the data for that endpoint. PIC18F4455/4550 USB devices provide a Streaming Parallel Port as a high-speed interface for moving data 18.1 SPP Configuration to and from an external system. This parallel port operates as a master port, complete with chip select The operation of the SPP is controlled by two registers: and clock outputs to control the movement of data to SPPCON and SPPCFG. The SPPCON register slave devices. Data can be channelled either directly to (Register18-1) controls the overall operation of the the USB SIE or to the microprocessor core. Figure18-1 parallel port and determines if it operates under USB or shows a block view of the SPP data path. microcontroller control. The SPPCFG register (Register18-2) controls timing configuration and pin FIGURE 18-1: SPP DATA PATH outputs. PIC18F4455/4550 18.1.1 ENABLING THE SPP To enable the SPP, set the SPPEN bit (SPPCON<0>). In addition, the TRIS bits for the corresponding SPP USB CK1SPP pins must be properly configured. At a minimum: SIE CK2SPP • Bits TRISD<7:0> must be set (= 1) SPP OESPP Logic • Bits TRISE<2:1> must be cleared (= 0) CSSPP If CK1SPP is to be used: CPU SPP<7:0> • Bit TRISE<0> must be cleared (= 0) If CSPP is to be used: • Bit TRISB<4> must be cleared (= 0) REGISTER 18-1: SPPCON: SPP CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SPPOWN SPPEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 SPPOWN: SPP Ownership bit 1 = USB peripheral controls the SPP 0 = Microcontroller directly controls the SPP bit 0 SPPEN: SPP Enable bit 1 = SPP is enabled 0 = SPP is disabled © 2009 Microchip Technology Inc. DS39632E-page 191

PIC18F2455/2550/4455/4550 REGISTER 18-2: SPPCFG: SPP CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CLKCFG1:CLKCFG0: SPP Clock Configuration bits 1x = CLK1 toggles on read or write of an Odd endpoint address; CLK2 toggles on read or write of an Even endpoint address 01 = CLK1 toggles on write; CLK2 toggles on read 00 = CLK1 toggles only on endpoint address write; CLK2 toggles on data read or write bit 5 CSEN: SPP Chip Select Pin Enable bit 1 = RB4 pin is controlled by the SPP module and functions as SPP CS output 0 = RB4 functions as a digital I/O port bit 4 CLK1EN: SPP CLK1 Pin Enable bit 1 = RE0 pin is controlled by the SPP module and functions as SPP CLK1 output 0 = RE0 functions as a digital I/O port bit 3-0 WS3:WS0: SPP Wait States bits 1111 = 30 additional wait states 1110 = 28 additional wait states • • • • 0001 = 2 additional wait states 0000 = 0 additional wait states 18.1.2 CLOCKING DATA 18.1.3 WAIT STATES The SPP has four control outputs: The SPP is designed with the capability of adding wait states to read and write operations. This allows access • Two separate clock outputs (CK1SPP and to parallel devices that require extra time for access. CK2SPP) • Output enable (OESPP) Wait state clocking is based on the data source clock. If the SPP is configured to operate as a USB endpoint, • Chip select (CSSPP) then wait states are based on the USB clock. Likewise, Together, they allow for several different configurations if the SPP is configured to operate from the micro- for controlling the flow of data to slave devices. When controller, then wait states are based on the instruction all control outputs are used, the three main options are: rate (FOSC/4). • CLK1 clocks endpoint address information while The WS3:WS0 bits set the wait states used by the SPP, CLK2 clocks data with a range of no wait states to 30 wait states, in multi- • CLK1 clocks write operations while CLK2 clocks ples of two. The wait states are added symmetrically to reads all transactions, with one-half added following each of the • CLK1 clocks Odd address data while CLK2 clocks two clock cycles normally required for the transaction. Even address data Figure18-3 and Figure18-4 show signalling examples with 4 wait states added to each transaction. Additional control options are derived by disabling the CK1SPP and CSSPP outputs. These are enabled or 18.1.4 SPP PULL-UPS disabled with the CLK1EN and CSEN bits, respectively, located in Register18-2. The SPP data lines (SPP<7:0>) are equipped with internal pull-ups for applications that may leave the port in a high-impedance condition. The pull-ups are enabled using the control bit, RDPU (PORTE<7>). DS39632E-page 192 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 18-2: TIMING FOR MICROCONTROLLER WRITE ADDRESS, WRITE DATA AND READ DATA (NO WAIT STATES) FOSC/4 OESPP CSSPP CK1SPP CK2SPP SPP<7:0> ADDR DATA DATA Write Address Write Data Read Data MOVWF SPPEPS MOVWF SPPDATA MOVF SPPDATA, W FIGURE 18-3: TIMING FOR USB WRITE ADDRESS AND DATA (4 WAIT STATES) USB Clock OESPP CSSPP CK1SPP CK2SPP SPP<7:0> Write Address Write Data 2 Wait States 2 Wait States 2 Wait States 2 Wait States FIGURE 18-4: TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES) USB Clock OESPP CSSPP CK1SPP CK2SPP SPP<7:0> Write Address Read Data 2 Wait States 2 Wait States 2 Wait States 2 Wait States © 2009 Microchip Technology Inc. DS39632E-page 193

PIC18F2455/2550/4455/4550 18.2 Setup for USB Control 18.3.1 SPP INTERRUPTS When the SPP is configured for USB operation, data When owned by the microcontroller core, control can can be clocked directly to and from the USB peripheral generate an interrupt to notify the application when without intervention of the microcontroller; thus, no each read and write operation is completed. The process time is required. Data is clocked into or out interrupt flag bit is SPPIF (PIR1<7>) and is enabled by from the SPP with endpoint (address) information first, the SPPIE bit (PIE1<7>). Like all other microcontroller followed by one or more bytes of data, as shown in level interrupts, it can be set to a low or high priority. Figure18-5. This is ideal for applications that require This is done with the SPPIP bit (IPR1<7>). isochronous, large volume data movement. 18.3.2 WRITING TO THE SPP The following steps are required to set up the SPP for Once configured, writing to the SPP is performed by USB control: writing to the SPPEPS and SPPDATA registers. If the 1. Configure the SPP as desired, including wait SPP is configured to clock out endpoint address infor- states and clocks. mation with the data, writing to the SPPEPS register 2. Set the SPPOWN bit for USB ownership. initiates the address write cycle. Otherwise, the write is 3. Set the buffer descriptor starting address started by writing the data to the SPPDATA register. (BDnADRL:BDnADRH) to FFFFh. The SPPBUSY bit indicates the status of the address 4. Set the KEN bit (BDnSTAT<5>) so the buffer and the data write cycles. descriptor is kept indefinitely by the SIE. The following is an example write sequence: 5. Set the INCDIS bit (BDnSTAT<4>) to disable 1. Write the 4-bit address to the SPPEPS register. automatic buffer address increment. The SPP automatically starts writing the 6. Set the SPPEN bit to enable the module. address. If address write is not used, then skip to step 3. Note: If a USB endpoint is configured to use the 2. Monitor the SPPBUSY bit to determine when the SPP, the data transfer type of that address has been sent. The duration depends endpoint must be isochronous only. on the wait states. 3. Write the data to the SPPDATA register. The 18.3 Setup for Microcontroller Control SPP automatically starts writing the data. The SPP can also act as a parallel port for the 4. Monitor the SPPBUSY bit to determine when the microcontroller. In this mode, the SPPEPS register data has been sent. The duration depends on (Register18-3) provides status and address write the wait states. control. Data is written to and read from the SPPDATA 5. Go back to steps 1 or 3 to write a new address register. When the SPP is owned by the or data. microcontroller, the SPP clock is driven by the Note: The SPPBUSY bit should be polled to instruction clock (FOSC/4). make certain that successive writes to the The following steps are required to set up the SPP for SPPEPS or SPPDATA registers do not microcontroller operation: overrun the wait time due to the wait state 1. Configure the SPP as desired, including wait setting. states and clocks. 2. Clear the SPPOWN bit. 3. Set SPPEN to enable the module. FIGURE 18-5: TRANSFER OF DATA BETWEEN USB SIE AND SPP Write USB endpoint number to SPP Write outbound USB data to SPP or read inbound USB data from SPP Endpoint Byte 0 Byte 1 Byte 2 Byte 3 Byte n Address DS39632E-page 194 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 18.3.3 READING FROM THE SPP 3. Read the data from the SPPDATA register; the data from the previous read operation is Reading from the SPP involves reading the SPPDATA returned. The SPP automatically starts the read register. Reading the register the first time initiates the cycle for the next read. read operation. When the read is finished, indicated by the SPPBUSY bit, the SPPDATA will be loaded with the 4. Monitor the SPPBUSY bit to determine when the current data. data has been read. The duration depends on the wait states. The following is an example read sequence: 5. Go back to step 3 to read the current byte from 1. Write the 4-bit address to the SPPEPS register. the SPP and start the next read cycle. The SPP automatically starts writing the address. If address write is not used then skip to step 3. 2. Monitor the SPPBUSY bit to determine when the address has been sent. The duration depends on the wait states. REGISTER 18-3: SPPEPS: SPP ENDPOINT ADDRESS AND STATUS REGISTER R-0 R-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RDSPP: SPP Read Status bit (Valid when SPPCON<SPPOWN> = 1, USB) 1 = The last transaction was a read from the SPP 0 = The last transaction was not a read from the SPP bit 6 WRSPP: SPP Write Status bit (Valid when SPPCON<SPPOWN> = 1, USB) 1 = The last transaction was a write to the SPP 0 = The last transaction was not a write to the SPP bit 5 Unimplemented: Read as ‘0’ bit 4 SPPBUSY: SPP Handshaking Override bit 1 = The SPP is busy 0 = The SPP is ready to accept another read or write request bit 3-0 ADDR3:ADDR0: SPP Endpoint Address bits 1111 = Endpoint Address 15 • • • • 0001 0000 = Endpoint Address 0 © 2009 Microchip Technology Inc. DS39632E-page 195

PIC18F2455/2550/4455/4550 TABLE 18-1: REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page SPPCON(3) — — — — — — SPPOWN SPPEN 57 SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 57 SPPEPS(3) RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 57 SPPDATA(3) DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 57 PIR1 SPPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 PORTE RDPU(3) — — — RE3(1,2) RE2(3) RE1(3) RE0(3) 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). 3: These registers and/or bits are unimplemented on 28-pin devices. DS39632E-page 196 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.0 MASTER SYNCHRONOUS 19.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four modes of the SPI are supported. To accomplish 19.1 Master SSP (MSSP) Module communication, typically three pins are used: Overview • Serial Data Out (SDO) – RC7/RX/DT/SDO • Serial Data In (SDI) – RB0/AN12/INT0/FLT0/SDI/SDA The Master Synchronous Serial Port (MSSP) module is • Serial Clock (SCK) – RB1/AN10/INT1/SCK/SCL a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral Additionally, a fourth pin may be used when in a Slave devices may be serial EEPROMs, shift registers, mode of operation: display drivers, A/D converters, etc. The MSSP module • Slave Select (SS) – RA5/AN4/SS/HLVDIN/C2OUT can operate in one of two modes: Figure19-1 shows the block diagram of the MSSP • Serial Peripheral Interface (SPI) module when operating in SPI mode. • Inter-Integrated Circuit (I2C™) - Full Master mode FIGURE 19-1: MSSP BLOCK DIAGRAM - Slave mode (with general address call) (SPIMODE) The I2C interface supports the following modes in Internal hardware: Data Bus • Master mode Read Write • Multi-Master mode • Slave mode SSPBUF reg 19.2 Control Registers The MSSP module has three associated control regis- SSPSR reg ters. These include a status register (SSPSTAT) and SDI bit0 Shift two control registers (SSPCON1 and SSPCON2). The Clock use of these registers and their individual Configuration bits differ significantly depending on whether the MSSP SDO module is operated in SPI or I2C mode. Additional details are provided under the individual SS Control sections. Enable SS Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE 2 4 (T M R 2 O u tp u )t 2 Edge Select SCK Prescaler TOSC 4, 16, 64 Data to TX/RX in SSPSR TRIS bit Note: Only those pin functions relevant to SPI operation are shown here. © 2009 Microchip Technology Inc. DS39632E-page 197

PIC18F2455/2550/4455/4550 19.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes The MSSP module has four registers for SPI mode are written to or read from. operation. These are: In receive operations, SSPSR and SSPBUF together • MSSP Control Register 1 (SSPCON1) create a double-buffered receiver. When SSPSR • MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF • Serial Receive/Transmit Buffer Register and the SSPIF interrupt is set. (SSPBUF) During transmission, the SSPBUF is not double- • MSSP Shift Register (SSPSR) – Not directly buffered. A write to SSPBUF will write to both SSPBUF accessible and SSPSR. SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower six bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 19-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE(1) D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Note 1: Polarity of clock state is set by the CKP bit (SSPCON1<4>). DS39632E-page 198 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 19-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over- flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins(2) bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin(3) 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled(3) 0011 = SPI Master mode, clock = TMR2 output/2(3,4) 0010 = SPI Master mode, clock = FOSC/64(3) 0001 = SPI Master mode, clock = FOSC/16(3) 0000 = SPI Master mode, clock = FOSC/4(3) Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only. 4: PR2 = 0x00 is not supported when running the SPI module in TMR2 Output/2 mode. © 2009 Microchip Technology Inc. DS39632E-page 199

PIC18F2455/2550/4455/4550 19.3.2 OPERATION the WCOL bit so that it can be determined if the follow- ing write(s) to the SSPBUF register completed When initializing the SPI, several options need to be successfully. specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). Note: When the application software is expect- These control bits allow the following to be specified: ing to receive valid data, the SSPBUF • Master mode (SCK is the clock output) should be read before the next byte of data to transfer is written to the SSPBUF. • Slave mode (SCK is the clock input) Application software should follow this • Clock Polarity (Idle state of SCK) process even when the current contents of • Data Input Sample Phase (middle or end of data SSPBUF are not important. output time) The Buffer Full bit, BF (SSPSTAT<0>), indicates when • Clock Edge (output data on rising/falling edge of SSPBUF has been loaded with the received data SCK) (transmission is complete). When the SSPBUF is read, • Clock Rate (Master mode only) the BF bit is cleared. This data may be irrelevant if the • Slave Select mode (Slave mode only) SPI is only a transmitter. Generally, the MSSP interrupt The MSSP module consists of a transmit/receive shift is used to determine when the transmission/reception register (SSPSR) and a buffer register (SSPBUF). The has completed. If the interrupt method is not going to SSPSR shifts the data in and out of the device, MSb be used, then software polling can be done to ensure first. The SSPBUF holds the data that was written to the that a write collision does not occur. Example19-1 SSPSR until the received data is ready. Once the eight shows the loading of the SSPBUF (SSPSR) for data bits of data have been received, that byte is moved to transmission. the SSPBUF register. Then, the Buffer Full detect bit, The SSPSR is not directly readable or writable and can BF (SSPSTAT<0>) and the interrupt flag bit, SSPIF, are only be accessed by addressing the SSPBUF register. set. This double-buffering of the received data Additionally, the MSSP Status register (SSPSTAT) (SSPBUF) allows the next byte to start reception before indicates the various status conditions. reading the data that was just received. Any write to the Note: The SSPBUF register cannot be used with SSPBUF register during transmission/reception of data read-modify-write instructions, such as will be ignored and the Write Collision detect bit, WCOL BCF, BTFSC and COMF. (SSPCON1<7>), will be set. User software must clear EXAMPLE 19-1: LOADING THE SSPBUF (SSPSR) REGISTER TransmitSPI: BCF PIR1, SSPIF ;Make sure interrupt flag is clear (may have been set from previous transmission). MOVF SSPBUF, W ;Perform read, even if the data in SSPBUF is not important MOVWF RXDATA ;Save previously received byte in user RAM, if the data is meaningful MOVF TXDATA, W ;WREG = Contents of TXDATA (user data to send) MOVWF SSPBUF ;Load data to send into transmit buffer WaitComplete: ;Loop until data has finished transmitting BTFSS PIR1, SSPIF ;Interrupt flag set when transmit is complete BRA WaitComplete DS39632E-page 200 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.3.3 ENABLING SPI I/O Any serial port function that is not desired may be overridden by programming the corresponding data To enable the serial port, MSSP Enable bit, SSPEN direction (TRIS) register to the opposite value. Input (SSPCON1<5>), must be set. To reset or reconfigure functions which will not be used do not need to be SPI mode, clear the SSPEN bit, reinitialize the SSPCON configured as digital inputs. registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For 19.3.4 TYPICAL CONNECTION the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) Figure19-2 shows a typical connection between two appropriately programmed as follows: microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. • SDI must have TRISB<0> bit set (configure as Data is shifted out of both shift registers on their digital in ADCON1) programmed clock edge and latched on the opposite • SDO must have TRISC<7> bit cleared edge of the clock. Both processors should be pro- • SCK (Master mode) must have TRISB<1> bit grammed to the same Clock Polarity (CKP), then both cleared controllers would send and receive data at the same • SCK (Slave mode) must have TRISB<1> bit set time. Whether the data is meaningful (or dummy data) (configure as digital in ADCON1) depends on the application software. This leads to • SS must have TRISA<5> bit set (configure as three scenarios for data transmission: digital in ADCON1) • Master sends data – Slave sends dummy data • Master sends data – Slave sends data • Master sends dummy data – Slave sends data FIGURE 19-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2 © 2009 Microchip Technology Inc. DS39632E-page 201

PIC18F2455/2550/4455/4550 19.3.5 MASTER MODE • FOSC/4 (or TCY) The master can initiate the data transfer at any time • FOSC/16 (or 4 • TCY) because it controls the SCK. The master determines • FOSC/64 (or 16 • TCY) when the slave (Processor 2, Figure19-2) is to • Timer2 output/2 broadcast data by the software protocol. This allows a maximum data rate (at 48MHz) of In Master mode, the data is transmitted/received as 12.00Mbps. soon as the SSPBUF register is written to. If the SPI is When used in Timer2 Output/2 mode, the bit rate can only going to receive, the SDO output could be dis- be configured using the PR2 Period register and the abled (programmed as an input). The SSPSR register Timer2 prescaler. However, writing to SSPBUF does will continue to shift in the signal present on the SDI pin not clear the current TMR2 value in hardware. Depend- at the programmed clock rate. As each byte is ing upon the current value of TMR2 when the user firm- received, it will be loaded into the SSPBUF register as ware writes to SSPBUF, this can result in an if a normal received byte (interrupts and status bits unpredictable MSb bit width, unless the procedure of appropriately set). This could be useful in receiver Example19-2 is used. applications as a “Line Activity Monitor” mode. Figure19-3 shows the waveforms for Master mode. The clock polarity is selected by appropriately When the CKE bit is set, the SDO data is valid before programming the CKP bit (SSPCON1<4>). This, then, there is a clock edge on SCK. The change of the input would give waveforms for SPI communication as sample is shown based on the state of the SMP bit. The shown in Figure19-3, Figure19-5 and Figure19-6, time when the SSPBUF is loaded with the received where the MSB is transmitted first. In Master mode, the data is shown. SPI clock rate (bit rate) is user-programmable to be one of the following: EXAMPLE 19-2: LOADING SSPBUF WITH THE TIMER2/2 CLOCK MODE TransmitSPI: BCF PIR1, SSPIF ;Make sure interrupt flag is clear (may have been set from previous transmission) MOVF SSPBUF, W ;Perform read, even if the data in SSPBUF is not important MOVWF RXDATA ;Save previously received byte in user RAM, if the data is meaningful BCF T2CON, TMR2ON ;Turn off timer when loading SSPBUF CLRF TMR2 ;Set timer to a known state MOVF TXDATA, W ;WREG = Contents of TXDATA (user data to send) MOVWF SSPBUF ;Load data to send into transmit buffer BSF T2CON, TMR2ON ;Start timer to begin transmission WaitComplete: ;Loop until data has finished transmitting BTFSS PIR1, SSPIF ;Interrupt flag set when transmit is complete BRA WaitComplete DS39632E-page 202 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 19-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2↓ SSPBUF © 2009 Microchip Technology Inc. DS39632E-page 203

PIC18F2455/2550/4455/4550 19.3.6 SLAVE MODE transmitted byte and becomes a floating output. Exter- nal pull-up/pull-down resistors may be desirable In Slave mode, the data is transmitted and received as depending on the application. the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Note 1: When the SPI module is in Slave mode While in Slave mode, the external clock is supplied by with SS pin control enabled the external clock source on the SCK pin. This external (SSPCON1<3:0> = 0100), the SPI module clock must meet the minimum high and low times as will reset if the SS pin is set to VDD. specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE While in Sleep mode, the slave can transmit/receive set, then the SS pin control must be data. When a byte is received, the device can be con- enabled. figured to wake-up from Sleep. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to 19.3.7 SLAVE SELECT a high level or clearing the SSPEN bit. SYNCHRONIZATION To emulate two-wire communication, the SDO pin can The SS pin allows a Synchronous Slave mode. The be connected to the SDI pin. When the SPI needs to SPI must be in Slave mode with the SS pin control operate as a receiver, the SDO pin can be configured enabled (SSPCON1<3:0> = 04h). When the SS pin is as an input. This disables transmissions from the SDO. low, transmission and reception are enabled and the The SDI can always be left as an input (SDI function) SDO pin is driven. When the SS pin goes high, the since it cannot create a bus conflict. SDO pin is no longer driven, even if in the middle of a FIGURE 19-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2↓ SSPBUF DS39632E-page 204 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF FIGURE 19-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF © 2009 Microchip Technology Inc. DS39632E-page 205

PIC18F2455/2550/4455/4550 19.3.8 OPERATION IN POWER-MANAGED 19.3.9 EFFECTS OF A RESET MODES A Reset disables the MSSP module and terminates the In SPI Master mode, module clocks may be operating current transfer. at a different speed than when in Full-Power mode; in 19.3.10 BUS MODE COMPATIBILITY the case of the Sleep mode, all clocks are halted. Table19-1 shows the compatibility between the In most Idle modes, a clock is provided to the peripher- standard SPI modes and the states of the CKP and als. That clock should be from the primary clock CKE control bits. source, the secondary clock (Timer1 oscillator) or the INTOSC source. See Section2.4 “Clock Sources TABLE 19-1: SPI BUS MODES and Oscillator Switching” for additional information. In most cases, the speed that the master clocks SPI Standard SPI Mode Control Bits State data is not important; however, this should be Terminology CKP CKE evaluated for each system. If MSSP interrupts are enabled, they can wake the con- 0, 0 0 1 troller from Sleep mode or one of the Idle modes when 0, 1 0 0 the master completes sending data. If an exit from 1, 0 1 1 Sleep or Idle mode is not desired, MSSP interrupts 1, 1 1 0 should be disabled. There is also an SMP bit which controls when the data If the Sleep mode is selected, all module clocks are is sampled. halted and the transmission/reception will remain in that state until the devices wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/ Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 TRISA — TRISA6(2) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56 SSPBUF MSSP Receive Buffer/Transmit Register 54 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 54 SSPSTAT SMP CKE D/A P S R/W UA BF 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear. 2: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. DS39632E-page 206 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.4 I2C Mode 19.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call These are: support) and provides interrupts on Start and Stop bits • MSSP Control Register 1 (SSPCON1) in hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPCON2) function). The MSSP module implements the standard • MSSP Status Register (SSPSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPBUF) Two pins are used for data transfer: • MSSP Shift Register (SSPSR) – Not directly • Serial clock (SCL) – RB1/AN10/INT1/SCK/SCL accessible • Serial data (SDA) – RB0/AN12/INT0/FLT0/SDI/SDA • MSSP Address Register (SSPADD) The user must configure these pins as inputs by setting SSPCON1, SSPCON2 and SSPSTAT are the control the associated TRIS bits. and status registers in I2C mode operation. The SSPCON1 and SSPCON2 registers are readable and FIGURE 19-7: MSSP BLOCK DIAGRAM writable. The lower six bits of the SSPSTAT are read-only. (I2C™ MODE) The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or Internal out. SSPBUF is the buffer register to which data bytes Data Bus are written to or read from. Read Write SSPADD register holds the slave device address when the MSSP is configured in I2C Slave mode. When the SSPBUF reg SCL MSSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload Shift value. Clock In receive operations, SSPSR and SSPBUF together SSPSR reg create a double-buffered receiver. When SSPSR SDA MSb LSb receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. Match Detect Addr Match During transmission, the SSPBUF is not double- Address Mask buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPADD reg Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT reg) Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. © 2009 Microchip Technology Inc. DS39632E-page 207

PIC18F2455/2550/4455/4550 REGISTER 19-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPBUF is full 0 = SSPBUF is empty In Receive mode: 1 = SSPBUF is full (does not include the ACK and Stop bits) 0 = SSPBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. DS39632E-page 208 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 19-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins(1) 0 = Disables serial port and configures these pins as I/O port pins(1) bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled(2) 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled(2) 1011 = I2C Firmware Controlled Master mode (slave Idle)(2) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))(2,3) 0111 = I2C Slave mode, 10-bit address(2) 0110 = I2C Slave mode, 7-bit address(2) Note 1: When enabled, the SDA and SCL pins must be properly configured as input or output. 2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. 3: Guideline only; exact baud rate slightly dependent upon circuit conditions, but the highest clock rate should not exceed this formula. SSPADD values of ‘0’ and ‘1’ are not supported. © 2009 Microchip Technology Inc. DS39632E-page 209

PIC18F2455/2550/4455/4550 REGISTER 19-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) Unused in Master mode. bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit(2) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit(2) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit(2) 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). DS39632E-page 210 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 19-6: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit Unused in Slave mode. bit 5-2 ADMSK5:ADMSK2: Slave Address Mask Select bits 1 = Masking of corresponding bits of SSPADD enabled 0 = Masking of corresponding bits of SSPADD disabled bit 1 ADMSK1: Slave Address Mask Select bit In 7-Bit Addressing mode: 1 = Masking of SPADD<1> only enabled 0 = Masking of SPADD<1> only disabled In 10-Bit Addressing mode: 1 = Masking of SSPADD<1:0> enabled 0 = Masking of SSPADD<1:0> disabled bit 0 SEN: Stretch Enable bit(1) 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). © 2009 Microchip Technology Inc. DS39632E-page 211

PIC18F2455/2550/4455/4550 19.4.2 OPERATION 19.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPCON1<5>). a Start condition to occur. Following the Start condition, The SSPCON1 register allows control of the I2C the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the operation. Four mode selection bits (SSPCON1<3:0>) allow one of the following I2C modes to be selected: clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The • I2C Master mode, clock address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) with Start and 1. The SSPSR register value is loaded into the Stop bit interrupts enabled SSPBUF register. • I2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is 4. The MSSP Interrupt Flag bit, SSPIF, is set (and Idle interrupt is generated, if enabled) on the falling Selection of any I2C mode with the SSPEN bit set edge of the ninth SCL pulse. forces the SCL and SDA pins to be open-drain, In 10-Bit Addressing mode, two address bytes need to provided these pins are programmed as inputs by be received by the slave. The five Most Significant bits setting the appropriate TRISC or TRISD bits. To ensure (MSbs) of the first address byte specify if this is a 10-bit proper operation of the module, pull-up resistors must address. Bit R/W (SSPSTAT<2>) must specify a be provided externally to the SCL and SDA pins. write so the slave device will receive the second address byte. For a 10-bit address, the first byte 19.4.3 SLAVE MODE would equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ In Slave mode, the SCL and SDA pins must be are the two MSbs of the address. The sequence of configured as inputs (TRISC<4:3> set). The MSSP events for 10-bit addressing is as follows, with steps module will override the input state with the output data 7 through 9 for the slave-transmitter: when required (slave-transmitter). 1. Receive first (high) byte of address (bits SSPIF, The I2C Slave mode hardware will always generate an BF and UA (SSPSTAT<1>) are set on address interrupt on an address match. Address masking will match). allow the hardware to generate an interrupt for more 2. Update the SSPADD register with second (low) than one address (up to 31 in 7-bit addressing and up byte of address (clears bit, UA, and releases the to 63 in 10-bit addressing). Through the mode select SCL line). bits, the user can also choose to interrupt on Start and 3. Read the SSPBUF register (clears bit, BF) and Stop bits. clear flag bit, SSPIF. When an address is matched, or the data transfer after 4. Receive second (low) byte of address (bits, an address match is received, the hardware auto- SSPIF, BF and UA, are set). matically will generate the Acknowledge (ACK) pulse 5. Update the SSPADD register with the first (high) and load the SSPBUF register with the received value byte of address. If match releases SCL line, this currently in the SSPSR register. will clear bit, UA. Any combination of the following conditions will cause 6. Read the SSPBUF register (clears bit, BF) and the MSSP module not to give this ACK pulse: clear flag bit, SSPIF. • The Buffer Full bit, BF (SSPSTAT<0>), was set 7. Receive Repeated Start condition. before the transfer was received. 8. Receive first (high) byte of address (bits, SSPIF • The overflow bit, SSPOV (SSPCON1<6>), was and BF, are set). set before the transfer was received. 9. Read the SSPBUF register (clears bit, BF) and In this case, the SSPSR register value is not loaded clear flag bit, SSPIF. into the SSPBUF, but bit, SSPIF, is set. The BF bit is cleared by reading the SSPBUF register, while bit, SSPOV, is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. DS39632E-page 212 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.4.3.2 Address Masking In 10-Bit Address mode, bits ADMSK<5:2> mask the corresponding address bits in the SSPADD register. In Masking an address bit causes that bit to become a addition, ADMSK1 simultaneously masks the two LSbs “don’t care”. When one address bit is masked, two of the address (SSPADD<1:0>). For any ADMSK bits addresses will be Acknowledged and cause an that are active (ADMSK<n>=1), the corresponding interrupt. It is possible to mask more than one address address bit is ignored (SSPADD<n>=x). Also note bit at a time, which makes it possible to Acknowledge that although in 10-Bit Addressing mode, the upper up to 31 addresses in 7-bit mode and up to address bits reuse part of the SSPADD register bits, the 63addresses in 10-bit mode (see Example19-3). address mask bits do not interact with those bits. They The I2C Slave behaves the same way whether address only affect the lower address bits. masking is used or not. However, when address masking is used, the I2C slave can Acknowledge Note1: ADMSK1 masks the two Least Significant multiple addresses and cause interrupts. When this bits of the address. occurs, it is necessary to determine which address 2: The two Most Significant bits of the caused the interrupt by checking SSPBUF. address are not affected by address In 7-Bit Address mode, address mask bits masking. ADMSK<5:1> (SSPCON2<5:1>) mask the corre- sponding address bits in the SSPADD register. For any ADMSK bits that are set (ADMSK<n>=1), the corresponding address bit is ignored (SSPADD<n>=x). For the module to issue an address Acknowledge, it is sufficient to match only on addresses that do not have an active address mask. EXAMPLE 19-3: ADDRESS MASKING EXAMPLES 7-bit addressing: SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’) ADMSK<5:1> = 00111 Addresses Acknowledged : A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh 10-bit addressing: SSPADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since they are not affected by masking) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh © 2009 Microchip Technology Inc. DS39632E-page 213

PIC18F2455/2550/4455/4550 19.4.3.3 Reception 19.4.3.4 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPSTAT register is set. The received address is the SSPBUF register and the SDA line is held low loaded into the SSPBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin RB1/AN10/INT1/SCK/ SCL is held low regardless of SEN (see Section19.4.4 When the address byte overflow condition exists, then “Clock Stretching” for more detail). By stretching the the no Acknowledge (ACK) pulse is given. An overflow clock, the master will be unable to assert another clock condition is defined as either bit, BF (SSPSTAT<0>), is pulse until the slave is done preparing the transmit set, or bit, SSPOV (SSPCON1<6>), is set. data. The transmit data must be loaded into the An MSSP interrupt is generated for each data transfer SSPBUF register which also loads the SSPSR register. byte. The Interrupt Flag bit, SSPIF, must be cleared in Then the RB1/AN10/INT1/SCK/SCL pin should be software. The SSPSTAT register is used to determine enabled by setting bit, CKP (SSPCON1<4>). The eight the status of the byte. data bits are shifted out on the falling edge of the SCL If SEN is enabled (SSPCON2<0> = 1), RB1/AN10/ input. This ensures that the SDA signal is valid during INT1/SCK/SCL will be held low (clock stretch) following the SCL high time (Figure19-10). each data transfer. The clock must be released by The ACK pulse from the master-receiver is latched on setting bit, CKP (SSPCON1<4>). See Section19.4.4 the rising edge of the ninth SCL input pulse. If the SDA “Clock Stretching” for more detail. line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT regis- ter) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, the RB1/AN10/INT1/SCK/SCL pin must be enabled by setting bit CKP (SSPCON1<4>). An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. DS39632E-page 214 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 2 FIGURE 19-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e Receiving D6D5D4 234 Cleared in softwarSSPBUF is read 7 D 1 K 9 = 0 AC W 8 R/ A1 7 A2 6 = )0 ddress A3 5 n SEN A e Receiving A5A4 34 eset to ‘’ wh0 ot r A6 2 s n e SDAA7 SCL1S (PIR1<3>) SSPIF BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) CKP(CKP do © 2009 Microchip Technology Inc. DS39632E-page 215

PIC18F2455/2550/4455/4550 2 FIGURE 19-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 pt. u D1 7 nterr n i D2 6 e a s u Data D3 5 e d ca Receiving D5D4 34 ared in softwarPBUF is read owledged an D6 2 CleSS Ackn e D7 1 ’).0 X will b K 9 a ‘ X. R/W = 0 AC 8 a ‘’ or 1 5.X.A3. Receiving Address SDAA7A6A5XA3XX SCL1234567S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) CKP(CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can be either x 2:In this example, an address equal to A7.A6.A DS39632E-page 216 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 2 FIGURE 19-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S ACK 9 PIF I S D0 8 m S o Data D1 7 Fr Transmitting D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software KP is set in software C D7 1 R ACK 9 PIF IS S S D0 8 m o Fr D1 7 a g Dat D2 6 ware Transmittin D6D5D4D3 2345 Cleared in software SSPBUF is written in soft CKP is set in software D7 1 PIF S SCL held lowwhile CPUresponds to S K C A 9 1 = W 8 R/ 1 A 7 2 ess A 6 Addr A3 5 g eivin A4 4 ec R A5 3 A6A7 12 Data in sampled >) 0>) 3 < < T 1 A R T DA CL S SPIF (PI F (SSPS KP S S S B C © 2009 Microchip Technology Inc. DS39632E-page 217

PIC18F2455/2550/4455/4550 FIGURE 19-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. 0 D 8 1 D 7 e Byte 3D2 6 softwar a D 5 n eceive Dat D5D4 34 Cleared i R 6 D 2 7 D 1 K AC 9 0 D 8 untilD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPADD is updated with highbyte of address d low SPAD D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACK11110A9A8A7A6A5A4A3A2A1 1234567891234567 R1<3>) Cleared in softwareCleared in software TAT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag SPCON1<6>) TAT<1>) UA is set indicating thatCleared by hardwarethe SSPADD needs to bewhen SSPADD is updatedupdatedwith low byte of address UA is set indicating thatSSPADD needs to beupdated (CKP does not reset to ‘’ when SEN = )00 SDA SCLS (PISSPIF BF (SSPS SSPOV (S UA (SSPS KP C DS39632E-page 218 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 19-12: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 Clock is held low untilClock is held low untilupdate of SSPADD has update of SSPADD has taken placetaken place Receive First Byte of AddressReceive Second Byte of AddressReceive Data ByteR/W = 0 ACKACKDA11110A9A8A7A6A5XA3A2XXD7D6D5D4D3D1D2 CL1234567891234567891234576S SPIF (PIR1<3>) Cleared in softwareCleared in softwareCleared in software F (SSPSTAT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag SPOV (SSPCON1<6>) A (SSPSTAT<1>) UA is set indicating thatCleared by hardware whenCleared by hardwarethe SSPADD needs to beSSPADD is updated with highwhen SSPADD is updatedupdatedbyte of addresswith low byte of address UA is set indicating thatSSPADD needs to beupdated KP(CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can be either a ‘’ or a ‘’).x10 2:In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt. 3:Note that the Most Significant bits of the address are not affected by the bit masking. S S S B S U C © 2009 Microchip Technology Inc. DS39632E-page 219

PIC18F2455/2550/4455/4550 2 FIGURE 19-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCL low w Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressR/W = Transmitting Data Byte1 0ACKD11111A8A9D6D5D4D3D2D7ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPBUFWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPADD has taken place W = Receive Second Byte of Address0 A6A5A4A3A2A1A0A7ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address UA is set indicating thatSSPADD needs to beupdated e First Byte of AddressR/ 110A9A8 345678 SSPBUF is written withcontents of SSPSR UA is set indicating thatthe SSPADD needs to beupdated Receiv SDA11 SCL12S (PIR1<3>) SSPIF BF (SSPSTAT<0>) UA (SSPSTAT<1>) CKP (SSPCON1<4>) DS39632E-page 220 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.4.4 CLOCK STRETCHING 19.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. 7-Bit Slave Transmit mode implements clock stretch- The SEN bit (SSPCON2<0>) allows clock stretching to ing by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line 19.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPBUF before the master device can In 7-Bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure19-10). ninth clock at the end of the ACK sequence if the BF Note1: If the user loads the contents of SSPBUF, bit is set, the CKP bit in the SSPCON1 register is setting the BF bit before the falling edge of automatically cleared, forcing the SCL output to be the ninth clock, the CKP bit will not be held low. The CKP bit being cleared to ‘0’ will assert cleared and clock stretching will not occur. the SCL line low. The CKP bit must be set in the user’s 2: The CKP bit can be set in software ISR before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR regardless of the state of the BF bit. and read the contents of the SSPBUF before the 19.4.4.4 Clock Stretching for 10-Bit Slave master device can initiate another receive sequence. Transmit Mode This will prevent buffer overruns from occurring (see Figure19-15). In 10-Bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by Note1: If the user reads the contents of the the state of the UA bit, just as it is in 10-Bit Slave SSPBUF before the falling edge of the Receive mode. The first two addresses are followed ninth clock, thus clearing the BF bit, the by a third address sequence which contains the high- CKP bit will not be cleared and clock order bits of the 10-bit address and the R/W bit set to stretching will not occur. ‘1’. After the third address sequence is performed, the 2: The CKP bit can be set in software UA bit is not set, the module is now configured in regardless of the state of the BF bit. The Transmit mode and clock stretching is controlled by user should be careful to clear the BF bit the BF flag as in 7-Bit Slave Transmit mode (see in the ISR before the next receive Figure19-13). sequence in order to prevent an overflow condition. 19.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. © 2009 Microchip Technology Inc. DS39632E-page 221

PIC18F2455/2550/4455/4550 19.4.4.5 Clock Synchronization and already asserted the SCL line. The SCL output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This When the CKP bit is cleared, the SCL output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, clearing the CKP bit will not assert the minimum high time requirement for SCL (see SCL output low until the SCL output is already Figure19-14). sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 19-14: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX – 1 SCL Master device CKP asserts clock Master device deasserts clock Write SSPCON1 DS39632E-page 222 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 2 FIGURE 19-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 Data D3 5 g eivin D4 4 c e R D5 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the ninth clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause Buffer Full (BF) bit is clear prior to falling edge of ninth clock Receiving Data D6D5D4D3D7 12345 Cleared in software SPBUF is read If BF is clearedprior to the fallingedge of the ninth clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 s s e ddr A3 5 A g eivin A4 4 ec R A5 3 A6 2 >) 6 A7 1 1< >) 0>) ON DA CLS (PIR1<3SPIF F (SSPSTAT< SPOV (SSPC KP S S S B S C © 2009 Microchip Technology Inc. DS39632E-page 223

PIC18F2455/2550/4455/4550 FIGURE 19-16: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) w ent. Clock is not held lobecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not s D 8 1 D 7 e Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D2D7D6D5D4D3D1D0D2 123457896123456 Cleared in softwareCleared in softwar Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPADD register beforethe falling edge of the ninth clock will haveno effect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of AddressW = 0 A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address after falling edgeof ninth clock UA is set indicating thatSSPADD needs to beupdated Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. Receive First Byte of AddressR/ 11110A9A8 12345678 1<3>) Cleared in software AT<0>) SSPBUF is written withcontents of SSPSR PCON1<6>) AT<1>) UA is set indicating thatthe SSPADD needs to beupdated R T S T SDA SCLS SSPIF (PI BF (SSPS SSPOV (S UA (SSPS KP C DS39632E-page 224 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the The addressing procedure for the I2C bus is such that SSPIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the the master. The exception is the general call address interrupt can be checked by reading the contents of the which can address all devices. When this address is SSPBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device specific or a general call address. Acknowledge. In 10-bit mode, the SSPADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second The general call address is recognized when the Gen- half of the address is not necessary, the UA bit will not eral Call Enable (GCEN) bit is enabled (SSPCON2<7> be set and the slave will begin receiving data after the set). Following a Start bit detect, 8 bits are shifted into Acknowledge (Figure19-17). the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 19-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’ © 2009 Microchip Technology Inc. DS39632E-page 225

PIC18F2455/2550/4455/4550 19.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPCON1 and by setting the of events. For instance, the user is not SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and are manipulated by the MSSP hardware if the TRIS bits immediately write the SSPBUF register to are set. initiate transmission before the Start condition is complete. In this case, the Master mode operation is supported by interrupt SSPBUF will not be written to and the generation on the detection of the Start and Stop WCOL bit will be set, indicating that a write conditions. The Stop (P) and Start (S) bits are cleared to the SSPBUF did not occur. from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is The following events will cause the MSSP Interrupt set or the bus is Idle, with both the S and P bits clear. Flag bit, SSPIF, to be set (and MSSP interrupt, if In Firmware Controlled Master mode, user code enabled): conducts all I2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options: • Acknowledge transmit 1. Assert a Start condition on SDA and SCL. • Repeated Start 2. Assert a Repeated Start condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. 2 FIGURE 19-18: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM3:SSPM0 Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock ct e SSPSR Detce) MSb LSb L ur e Oo abl WCk s SCL Receive En StAarcGtk beninot,ew Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCL In Write Collision Detect Set/Reset S, P, WCOL (SSPSTAT, SSPCON1); Clock Arbitration set SSPIF, BCLIF; Bus Collision State Counter for reset ACKSTAT, PEN (SSPCON2) End of XMIT/RCV DS39632E-page 226 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDA, while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all eight first byte transmitted contains the slave address of the bits are transmitted. receiving device (seven bits) and the Read/Write (R/W) 5. The MSSP module shifts in the ACK bit from the bit. In this case, the R/W bit will be logic ‘0’. Serial data slave device and writes its value into the is transmitted eight bits at a time. After each byte is SSPCON2 register (SSPCON2<6>). transmitted, an Acknowledge bit is received. Start and 6. The MSSP module generates an interrupt at the Stop conditions are output to indicate the beginning end of the ninth clock cycle by setting the SSPIF and the end of a serial transfer. bit. In Master Receive mode, the first byte transmitted con- 7. The user loads the SSPBUF with eight bits of tains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDA pin until all eight bits logic ‘1’ Thus, the first byte transmitted is a 7-bit slave are transmitted. address followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDA, while SCL outputs the slave device and writes its value into the serial clock. Serial data is received eight bits at a time. SSPCON2 register (SSPCON2<6>). After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the 10. The MSSP module generates an interrupt at the beginning and end of transmission. end of the ninth clock cycle by setting the SSPIF bit. The Baud Rate Generator used for the SPI mode 11. The user generates a Stop condition by setting operation is used to set the SCL clock frequency for either 100kHz, 400kHz or 1MHz I2C operation. See the Stop Enable bit, PEN (SSPCON2<2>). Section19.4.7 “Baud Rate” for more detail. 12. Interrupt is generated once the Stop condition is complete. © 2009 Microchip Technology Inc. DS39632E-page 227

PIC18F2455/2550/4455/4550 19.4.7 BAUD RATE Table19-3 demonstrates clock rates based on In I2C Master mode, the Baud Rate Generator (BRG) instruction cycles and the BRG value loaded into SSPADD. SSPADD values of less than 2 are not reload value is placed in the lower seven bits of the supported. Due to the need to support I2C clock SSPADD register (Figure19-19). When a write occurs stretching capability, I2C baud rates are partially to SSPBUF, the Baud Rate Generator will automatically dependent upon system parameters, such as line begin counting. The BRG counts down to ‘0’ and stops capacitance and pull-up strength. The parameters until another reload has taken place. The BRG count is provided in Table19-3 are guidelines, and the actual decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is baud rate may be slightly slower than that predicted in the table. The baud rate formula shown in the bit reloaded automatically. description of Register19-4 sets the maximum baud Once the given operation is complete (i.e., transmis- rate that can occur for a given SSPADD value. sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. FIGURE 19-19: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 Reload Reload SCL Control CLKO BRG Down Counter FOSC/4 TABLE 19-3: I2C™ CLOCK RATE W/BRG FSCL FCY FCY * 2 BRG Value (2 Rollovers of BRG) 10 MHz 20 MHz 18h 400 kHz(1) 10 MHz 20 MHz 1Fh 312.5 kHz 10 MHz 20 MHz 63h 100 kHz 4 MHz 8 MHz 09h 400 kHz(1) 4 MHz 8 MHz 0Ch 308 kHz 4 MHz 8 MHz 27h 100 kHz 1 MHz 2 MHz 02h 333 kHz(1) 1 MHz 2 MHz 09h 100 kHz Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. DS39632E-page 228 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCL high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCL pin (SCL allowed to float high). event that the clock is held low by an external device When the SCL pin is allowed to float high, the Baud (Figure19-20). Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 19-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload © 2009 Microchip Technology Inc. DS39632E-page 229

PIC18F2455/2550/4455/4550 19.4.8 I2C MASTER MODE START Note: If, at the beginning of the Start condition, CONDITION TIMING the SDA and SCL pins are already sam- To initiate a Start condition, the user sets the Start pled low, or if during the Start condition, the Enable bit, SEN (SSPCON2<0>). If the SDA and SCL SCL line is sampled low before the SDA pins are sampled high, the Baud Rate Generator is line is driven low, a bus collision occurs, reloaded with the contents of SSPADD<6:0> and starts the Bus Collision Interrupt Flag, BCLIF, is its count. If SCL and SDA are both sampled high when set, the Start condition is aborted and the the Baud Rate Generator times out (TBRG), the SDA I2C module is reset into its Idle state. pin is driven low. The action of the SDA being driven 19.4.8.1 WCOL Status Flag low while SCL is high is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the If the user writes the SSPBUF when a Start sequence Baud Rate Generator is reloaded with the contents of is in progress, the WCOL bit is set and the contents of SSPADD<6:0> and resumes its count. When the Baud the buffer are unchanged (the write doesn’t occur). Rate Generator times out (TBRG), the SEN bit Note: Because queueing of events is not (SSPCON2<0>) will be automatically cleared by allowed, writing to the lower five bits of hardware, the Baud Rate Generator is suspended, SSPCON2 is disabled until the Start leaving the SDA line held low and the Start condition is condition is complete. complete. FIGURE 19-21: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st bit 2nd bit SDA TBRG SCL TBRG S DS39632E-page 230 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDA is sampled low when SCL goes the SCL pin is asserted low. When the SCL pin is sam- from low-to-high. pled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The • SCL goes low before SDA is SDA pin is released (brought high) for one Baud Rate asserted low. This may indicate that Generator count (TBRG). When the Baud Rate Genera- another master is attempting to tor times out, if SDA is sampled high, the SCL pin will transmit a data ‘1’. be deasserted (brought high). When SCL is sampled Immediately following the SSPIF bit getting set, the user high, the Baud Rate Generator is reloaded with the may write the SSPBUF with the 7-bit address in 7-bit contents of SSPADD<6:0> and begins counting. SDA mode or the default first address in 10-bit mode. After the and SCL must be sampled high for one TBRG. This first eight bits are transmitted and an ACK is received, action is then followed by assertion of the SDA pin the user may then transmit an additional eight bits of (SDA = 0) for one TBRG while SCL is high. Following address (10-bit mode) or eight bits of data (7-bit mode). this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will not be 19.4.9.1 WCOL Status Flag reloaded, leaving the SDA pin held low. As soon as a If the user writes the SSPBUF when a Repeated Start Start condition is detected on the SDA and SCL pins, sequence is in progress, the WCOL bit is set and the the S bit (SSPSTAT<3>) will be set. The SSPIF bit will contents of the buffer are unchanged (the write doesn’t not be set until the Baud Rate Generator has timed out. occur). Note: Because queueing of events is not allowed, writing of the lower five bits of SSPCON2 is disabled until the Repeated Start condition is complete. FIGURE 19-22: REPEATED START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. SDA = 1, At completion of Start bit, SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change). and sets SSPIF TBRG TBRG TBRG SDA 1st bit Falling edge of ninth clock, Write to SSPBUF occurs here end of Xmit TBRG SCL TBRG Sr = Repeated Start © 2009 Microchip Technology Inc. DS39632E-page 231

PIC18F2455/2550/4455/4550 19.4.10 I2C MASTER MODE The user should verify that the WCOL is clear after TRANSMISSION each write to SSPBUF to ensure the transfer is correct. In all cases, WCOL must be cleared in software. Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address is accomplished by simply 19.4.10.3 ACKSTAT Status Flag writing a value to the SSPBUF register. This action will In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is set the Buffer Full flag bit, BF, and allow the Baud Rate cleared when the slave has sent an Acknowledge Generator to begin counting and start the next (ACK=0) and is set when the slave does not Acknowl- transmission. Each bit of address/data will be shifted edge (ACK = 1). A slave sends an Acknowledge when out onto the SDA pin after the falling edge of SCL is it has recognized its address (including a general call), asserted (see data hold time specification or when the slave has properly received its data. parameter106). SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid 19.4.11 I2C MASTER MODE RECEPTION before SCL is released high (see data setup time spec- ification parameter 107). When the SCL pin is released Master mode reception is enabled by programming the high, it is held that way for TBRG. The data on the SDA Receive Enable bit, RCEN (SSPCON2<3>). pin must remain stable for that duration and some hold Note: The MSSP module must be in an Idle state time after the next falling edge of SCL. After the eighth before the RCEN bit is set or the RCEN bit bit is shifted out (the falling edge of the eighth clock), will be disregarded. the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to The Baud Rate Generator begins counting and on each respond with an ACK bit during the ninth bit time if an rollover, the state of the SCL pin changes (high-to-low/ address match occurred, or if data was received low-to-high) and data is shifted into the SSPSR. After properly. The status of ACK is written into the ACKDT the falling edge of the eighth clock, the receive enable bit on the falling edge of the ninth clock. If the master flag is automatically cleared, the contents of the receives an Acknowledge, the Acknowledge Status bit, SSPSR are loaded into the SSPBUF, the BF flag bit is ACKSTAT, is cleared. If not, the bit is set. After the ninth set, the SSPIF flag bit is set and the Baud Rate Gener- clock, the SSPIF bit is set and the master clock (Baud ator is suspended from counting, holding SCL low. The Rate Generator) is suspended until the next data byte MSSP is now in Idle state awaiting the next command. is loaded into the SSPBUF, leaving SCL low and SDA When the buffer is read by the CPU, the BF flag bit is unchanged (Figure19-23). automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the After the write to the SSPBUF, each bit of the address Acknowledge Sequence Enable bit, ACKEN will be shifted out on the falling edge of SCL until all (SSPCON2<4>). seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will 19.4.11.1 BF Status Flag deassert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth In receive operation, the BF bit is set when an address clock, the master will sample the SDA pin to see if the or data byte is loaded into SSPBUF from SSPSR. It is address was recognized by a slave. The status of the cleared when the SSPBUF register is read. ACK bit is loaded into the ACKSTAT status bit 19.4.11.2 SSPOV Status Flag (SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the In receive operation, the SSPOV bit is set when eight BF flag is cleared and the Baud Rate Generator is bits are received into the SSPSR and the BF flag bit is turned off until another write to the SSPBUF takes already set from a previous reception. place, holding SCL low and allowing SDA to float. 19.4.11.3 WCOL Status Flag 19.4.10.1 BF Status Flag If the user writes the SSPBUF when a receive is In Transmit mode, the BF bit (SSPSTAT<0>) is set already in progress (i.e., SSPSR is still shifting in a data when the CPU writes to SSPBUF and is cleared when byte), the WCOL bit is set and the contents of the buffer all eight bits are shifted out. are unchanged (the write doesn’t occur). 19.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur) after 2TCY after the SSPBUF write. If SSPBUF is rewritten within 2TCY, the WCOL bit is set and SSPBUF is updated. This may result in a corrupted transfer. DS39632E-page 232 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 19-23: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A > slave, clear ACKSTAT bit SSPCON2<6 Transmitting Data or Second Halfof 10-Bit Address D6D5D4D3D2D1D0 2345678 Cleared in software service routinefrom MSSP interrupt SSPBUF is written in software From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to CK re W = 0 A W 9 ware R/ A1 ss and R/ 78 d by hard ave A2 ddre 6 eare PCON2<0> SEN = ,1dition begins SEN = 0 Transmit Address to Sl A6A5A4A3A7 SSPBUF written with 7-bit astart transmit 12345 Cleared in software SSPBUF written After Start condition, SEN cl Sn Write SStart co S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W © 2009 Microchip Technology Inc. DS39632E-page 233

PIC18F2455/2550/4455/4550 FIGURE 19-24: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) ence, = 1ere Bus masterterminatestransfer P Set SSPIF interruptat end of Acknowledgesequence Set P bit (SSPSTAT<4>)and SSPIF Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequACK from master,er configured as a receiverSDA = ACKDT = SDA = ACKDT = 10ogramming SSPCON2<3> (RCEN = )1PEN bit RCEN = , startRCEN cleared1RCEN clearedwritten hnext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK ACK is not sent 987561234912345678 Set SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptSet SSPIF interruptat end of receiveat end of Acknowledgesequence Cleared in softwareCleared in softwareCleared in softwareCleared insoftware Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Mastby pr ACK from Slave R/W = 1A1ACK 978 Write to SSPCON2<0> (SEN = ),1begin Start Condition SEN = 0Write to SSPBUF occurs here,start XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 361245SCLS SSPIF Cleared in softwareSDA = , SCL = 01while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN DS39632E-page 234 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.4.12 ACKNOWLEDGE SEQUENCE 19.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Enable bit, PEN Acknowledge Sequence Enable bit, ACKEN (SSPCON2<2>). At the end of a receive/transmit, the (SSPCON2<4>). When this bit is set, the SCL pin is SCL line is held low after the falling edge of the ninth pulled low and the contents of the Acknowledge data bit clock. When the PEN bit is set, the master will assert are presented on the SDA pin. If the user wishes to gen- the SDA line low. When the SDA line is sampled low, erate an Acknowledge, then the ACKDT bit should be the Baud Rate Generator is reloaded and counts down cleared. If not, the user should set the ACKDT bit before to 0. When the Baud Rate Generator times out, the starting an Acknowledge sequence. The Baud Rate SCL pin will be brought high and one TBRG (Baud Rate Generator then counts for one rollover period (TBRG) Generator rollover count) later, the SDA pin will be and the SCL pin is deasserted (pulled high). When the deasserted. When the SDA pin is sampled high while SCL pin is sampled high (clock arbitration), the Baud SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG Rate Generator counts for TBRG. The SCL pin is then later, the PEN bit is cleared and the SSPIF bit is set pulled low. Following this, the ACKEN bit is automatically (Figure19-26). cleared, the Baud Rate Generator is turned off and the 19.4.13.1 WCOL Status Flag MSSP module then goes into an inactive state (Figure19-25). If the user writes the SSPBUF when a Stop sequence is in progress, then the WCOL bit is set and the 19.4.12.1 WCOL Status Flag contents of the buffer are unchanged (the write doesn’t If the user writes the SSPBUF when an Acknowledge occur). sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 19-25: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in Set SSPIF at the Cleared in software end of receive software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 19-26: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by ninth clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. © 2009 Microchip Technology Inc. DS39632E-page 235

PIC18F2455/2550/4455/4550 19.4.14 SLEEP OPERATION 19.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 19.4.15 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0, 19.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF, and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure19-27). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit (SSPSTAT<4>) is set, or the SSPBUF can be written to. When the user services the bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine, and if the I2C bus is busy, enabling the MSSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge monitored for arbitration to see if the signal level is the condition was in progress when the bus collision expected output level. This check is performed in occurred, the condition is aborted, the SDA and SCL hardware with the result placed in the BCLIF bit. lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user ser- The states where arbitration can be lost are: vices the bus collision Interrupt Service Routine, and if • Address Transfer the I2C bus is free, the user can resume communication • Data Transfer by asserting a Start condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF bit will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determi- nation of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 19-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data doesn’t match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master SDA SCL Set Bus Collision Interrupt Flag (BCLIF) BCLIF DS39632E-page 236 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.4.17.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure19-30). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure19-28). counts down to 0. If the SCL pin is sampled as ‘0’, b) SCL is sampled low before SDA is asserted low during this time a bus collision does not occur. At the (Figure19-29). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a factor pins are monitored. during a Start condition is that no two bus masters can assert a Start condition at the If the SDA pin is already low, or the SCL pin is already exact same time. Therefore, one master low, then all of the following occur: will always assert SDA before the other. • the Start condition is aborted, This condition does not cause a bus • the BCLIF flag is set and collision because the two masters must be • the MSSP module is reset to its inactive state allowed to arbitrate the first address (Figure19-28). following the Start condition. If the address The Start condition begins with the SDA and SCL pins is the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded from SSPADD<6:0> Start or Stop conditions. and counts down to ‘0’. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 19-28: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 MSSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software © 2009 Microchip Technology Inc. DS39632E-page 237

PIC18F2455/2550/4455/4550 FIGURE 19-29: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 19-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF in software DS39632E-page 238 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 19.4.17.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, see Figure19-31). If SDA is sampled high, the BRG is During a Repeated Start condition, a bus collision reloaded and begins counting. If SDA goes from high-to- occurs if: low before the BRG times out, no bus collision occurs a) A low level is sampled on SDA when SCL goes because no two masters can assert SDA at exactly the from low level to high level. same time. b) SCL goes low before SDA is asserted low, If SCL goes from high-to-low before the BRG times out indicating that another master is attempting to and SDA has not already been asserted, a bus collision transmit a data ‘1’. occurs. In this case, another master is attempting to When the user deasserts SDA and the pin is allowed to transmit a data ‘1’ during the Repeated Start condition float high, the BRG is loaded with SSPADD<6:0> and (see Figure19-32). counts down to ‘0’. The SCL pin is then deasserted and If, at the end of the BRG time-out, both SCL and SDA when sampled high, the SDA pin is sampled. are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 19-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S ‘0’ SSPIF ‘0’ FIGURE 19-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S ‘0’ SSPIF © 2009 Microchip Technology Inc. DS39632E-page 239

PIC18F2455/2550/4455/4550 19.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<6:0> a) After the SDA pin has been deasserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’. (Figure19-33). If the SCL pin is low before SDA goes high. sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure19-34). FIGURE 19-33: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 19-34: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’ DS39632E-page 240 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 19-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56 SSPBUF MSSP Receive Buffer/Transmit Register 54 SSPADD MSSP Address Register in I2C Slave mode. 54 MSSP Baud Rate Reload Register in I2C Master mode. TMR2 Timer2 Register 54 PR2 Timer2 Period Register 54 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 54 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 54 SSPSTAT SMP CKE D/A P S R/W UA BF 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in I2C™ mode. Note 1: These registers or bits are not implemented in 28-pin devices. © 2009 Microchip Technology Inc. DS39632E-page 241

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 242 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 20.0 ENHANCED UNIVERSAL The pins of the Enhanced USART are multiplexed SYNCHRONOUS with PORTC. In order to configure RC6/TX/CK and RC7/RX/DT/SDO as an EUSART: ASYNCHRONOUS RECEIVER • SPEN bit (RCSTA<7>) must be set (= 1) TRANSMITTER (EUSART) • TRISC<7> bit must be set (= 1) The Enhanced Universal Synchronous Asynchronous • TRISC<6> bit must be set (= 1) Receiver Transmitter (EUSART) module is one of the Note: The EUSART control will automatically two serial I/O modules. (Generically, the USART is also reconfigure the pin from input to output as known as a Serial Communications Interface or SCI.) needed. The EUSART can be configured as a full-duplex asynchronous system that can communicate with The operation of the Enhanced USART module is peripheral devices, such as CRT terminals and controlled through three registers: personal computers. It can also be configured as a half- • Transmit Status and Control (TXSTA) duplex synchronous system that can communicate • Receive Status and Control (RCSTA) with peripheral devices, such as A/D or D/A integrated • Baud Rate Control (BAUDCON) circuits, serial EEPROMs, etc. These are detailed on the following pages in The Enhanced USART module implements additional Register20-1, Register20-2 and Register20-3, features, including automatic baud rate detection and respectively. calibration, automatic wake-up on Sync Break recep- tion and 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network bus (LIN bus) systems. The EUSART can be configured in the following modes: • Asynchronous (full-duplex) with: - Auto-wake-up on Break signal - Auto-baud calibration - 12-bit Break character transmission • Synchronous – Master (half-duplex) with selectable clock polarity • Synchronous – Slave (half-duplex) with selectable clock polarity © 2009 Microchip Technology Inc. DS39632E-page 243

PIC18F2455/2550/4455/4550 REGISTER 20-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous Slave mode. DS39632E-page 244 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 20-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2009 Microchip Technology Inc. DS39632E-page 245

PIC18F2455/2550/4455/4550 REGISTER 20-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 RXDTP: Received Data Polarity Select bit Asynchronous mode: 1 = RX data is inverted 0 = RX data received is not inverted Synchronous modes: 1 = Received Data (DT) is inverted. Idle state is a low level. 0 = No inversion of Data (DT). Idle state is a high level. bit 4 TXCKP: Clock and Data Polarity Select bit Asynchronous mode: 1 = TX data is inverted 0 = TX data is not inverted Synchronous modes: 1 = Clock (CK) is inverted. Idle state is a high level. 0 = No inversion of Clock (CK). Idle state is a low level. bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39632E-page 246 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 20.1 Baud Rate Generator (BRG) to use the high baud rate (BRGH = 1), or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud The BRG is a dedicated 8-bit, or 16-bit, generator that rate for a fast oscillator frequency. supports both the Asynchronous and Synchronous Writing a new value to the SPBRGH:SPBRG registers modes of the EUSART. By default, the BRG operates causes the BRG timer to be reset (or cleared). This in 8-bit mode. Setting the BRG16 bit (BAUDCON<3>) ensures the BRG does not wait for a timer overflow selects 16-bit mode. before outputting the new baud rate. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits, 20.1.1 OPERATION IN POWER-MANAGED BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>), also MODES control the baud rate. In Synchronous mode, BRGH is The device clock is used to generate the desired baud ignored. Table20-1 shows the formula for computation rate. When one of the power-managed modes is of the baud rate for different EUSART modes which entered, the new clock source may be operating at a only apply in Master mode (internally generated clock). different frequency. This may require an adjustment to Given the desired baud rate and FOSC, the nearest the value in the SPBRG register pair. integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table20-1. From this, 20.1.2 SAMPLING the error in baud rate can be determined. An example The data on the RX pin is sampled three times by a calculation is shown in Example20-1. Typical baud majority detect circuit to determine if a high or a low rates and error values for the various Asynchronous level is present at the RX pin. modes are shown in Table20-2. It may be advantageous TABLE 20-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair © 2009 Microchip Technology Inc. DS39632E-page 247

PIC18F2455/2550/4455/4550 EXAMPLE 20-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 20-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55 SPBRGH EUSART Baud Rate Generator Register High Byte 55 SPBRG EUSART Baud Rate Generator Register Low Byte 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39632E-page 248 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — © 2009 Microchip Technology Inc. DS39632E-page 249

PIC18F2455/2550/4455/4550 TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — DS39632E-page 250 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 20.1.3 AUTO-BAUD RATE DETECT Note1: If the WUE bit is set with the ABDEN bit, The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on detection and calibration of baud rate. This feature is the byte following the Break character. active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the bit is clear. incoming character baud rate is within the The automatic baud rate measurement sequence range of the selected BRG clock source. (Figure20-1) begins whenever a Start bit is received Some combinations of oscillator frequency and the ABDEN bit is set. The calculation is and EUSART baud rates are not possible self-averaging. due to bit error rates. Overall system timing and communication baud rates In the Auto-Baud Rate Detect (ABD) mode, the clock to must be taken into consideration when the BRG is reversed. Rather than the BRG clocking the using the Auto-Baud Rate Detection incoming RX signal, the RX signal is timing the BRG. In feature. ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. TABLE 20-4: BRG COUNTER CLOCK RATES Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate BRG16 BRGH BRG Counter Clock Detect must receive a byte with the value, 55h (ASCII “U”, which is also the LIN bus Sync character), in order 0 0 FOSC/512 to calculate the proper bit rate. The measurement is 0 1 FOSC/128 taken over both a low and a high bit time in order to min- 1 0 FOSC/128 imize any effects caused by asymmetry of the incoming 1 1 FOSC/32 signal. After a Start bit, the SPBRG begins counting up, Note: During the ABD sequence, SPBRG and using the preselected clock source on the first rising SPBRGH are both used as a 16-bit counter, edge of RX. After eight bits on the RX pin, or the fifth independent of the BRG16 setting. rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG register pair. Once the 5th edge is seen (this should correspond to the 20.1.3.1 ABD and EUSART Transmission Stop bit), the ABDEN bit is automatically cleared. Since the BRG clock is reversed during ABD acquisi- If a rollover of the BRG occurs (an overflow from FFFFh tion, the EUSART transmitter cannot be used during to 0000h), the event is trapped by the ABDOVF status ABD. This means that whenever the ABDEN bit is set, bit (BAUDCON<7>). It is set in hardware by BRG TXREG cannot be written to. Users should also ensure rollovers and can be set or cleared by the user in that ABDEN does not become set during a transmit software. ABD mode remains active after rollover sequence. Failing to do this may result in unpredictable events and the ABDEN bit remains set (Figure20-2). EUSART operation. While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGH register. Refer to Table20-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. © 2009 Microchip Technology Inc. DS39632E-page 251

PIC18F2455/2550/4455/4550 FIGURE 20-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto-Cleared ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE=0. FIGURE 20-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RX pin Start bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h DS39632E-page 252 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 20.2 EUSART Asynchronous Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty The Asynchronous mode of operation is selected by and the TXIF flag bit (PIR1<4>) is set. This interrupt can clearing the SYNC bit (TXSTA<4>). In this mode, the be enabled or disabled by setting or clearing the interrupt EUSART uses standard Non-Return-to-Zero (NRZ) enable bit, TXIE (PIE1<4>). TXIF will be set regardless of format (one Start bit, eight or nine data bits and one the state of TXIE; it cannot be cleared in software. TXIF Stop bit). The most common data format is 8 bits. An is also not cleared immediately upon loading TXREG, but on-chip dedicated 8-bit/16-bit Baud Rate Generator becomes valid in the second instruction cycle following can be used to derive standard baud rate frequencies the load instruction. Polling TXIF immediately following a from the oscillator. load of TXREG will return invalid results. The EUSART transmits and receives the LSb first. The While TXIF indicates the status of the TXREG register, EUSART’s transmitter and receiver are functionally another bit, TRMT (TXSTA<1>), shows the status of independent but use the same data format and baud the TSR register. TRMT is a read-only bit which is set rate. The Baud Rate Generator produces a clock, either when the TSR register is empty. No interrupt logic is x16 or x64 of the bit shift rate depending on the BRGH tied to this bit so the user has to poll this bit in order to and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity determine if the TSR register is empty. is not supported by the hardware but can be implemented in software and stored as the 9th data bit. The TXCKP bit (BAUDCON<4>) allows the TX signal to be inverted (polarity reversed). Devices that buffer The TXCKP (BAUDCON<4>) and RXDTP signals from TTL to RS-232 levels also invert the signal (BAUDCON<5>) bits allow the TX and RX signals to be (when TTL = 1, RS-232 = negative). Inverting the polar- inverted (polarity reversed). Devices that buffer signals ity of the TX pin data by setting the TXCKP bit allows for between TTL and RS-232 levels also invert the signal. use of circuits that provide buffering without inverting the Setting the TXCKP and RXDTP bits allows for the use of signal. circuits that provide buffering without inverting the signal. When operating in Asynchronous mode, the EUSART Note1: The TSR register is not mapped in data module consists of the following important elements: memory so it is not available to the user. • Baud Rate Generator 2: Flag bit, TXIF, is set when enable bit, • Sampling Circuit TXEN, is set. • Asynchronous Transmitter To set up an Asynchronous Transmission: • Asynchronous Receiver 1. Initialize the SPBRGH:SPBRG registers for the • Auto-Wake-up on Break signal appropriate baud rate. Set or clear the BRGH • 12-Bit Break Character Transmit and BRG16 bits, as required, to achieve the desired baud rate. • Auto-Baud Rate Detection 2. Enable the asynchronous serial port by clearing • Pin State Polarity bit, SYNC, and setting bit, SPEN. 20.2.1 EUSART ASYNCHRONOUS 3. If the signal from the TX pin is to be inverted, set TRANSMITTER the TXCKP bit. 4. If interrupts are desired, set enable bit, TXIE. The EUSART transmitter block diagram is shown in 5. If 9-bit transmission is desired, set transmit bit, Figure20-3. The heart of the transmitter is the Transmit TX9. Can be used as address/data bit. (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, 6. Enable the transmission by setting bit, TXEN, TXREG. The TXREG register is loaded with data in which will also set bit, TXIF. software. The TSR register is not loaded until the Stop 7. If 9-bit transmission is selected, the ninth bit bit has been transmitted from the previous load. As should be loaded in bit, TX9D. soon as the Stop bit is transmitted, the TSR is loaded 8. Load data to the TXREG register (starts with new data from the TXREG register (if available). transmission). 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. © 2009 Microchip Technology Inc. DS39632E-page 253

PIC18F2455/2550/4455/4550 FIGURE 20-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXCKP TXIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR Register TX pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGH SPBRG TX9 Baud Rate Generator TX9D FIGURE 20-4: ASYNCHRONOUS TRANSMISSION, TXCKP = 0 (TX NOT INVERTED) Write to TXREG Word 1 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 20-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK), TXCKP = 0 (TX NOT INVERTED) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. DS39632E-page 254 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 TXREG EUSART Transmit Register 55 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55 SPBRGH EUSART Baud Rate Generator Register High Byte 55 SPBRG EUSART Baud Rate Generator Register Low Byte 55 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: Reserved in 28-pin devices; always maintain these bits clear. © 2009 Microchip Technology Inc. DS39632E-page 255

PIC18F2455/2550/4455/4550 20.2.2 EUSART ASYNCHRONOUS 20.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure20-6. This mode would typically be used in RS-485 systems. The data is received on the RX pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGH:SPBRG registers for the whereas the main receive serial shifter operates at the appropriate baud rate. Set or clear the BRGH bit rate or at FOSC. This mode would typically be used and BRG16 bits, as required, to achieve the in RS-232 systems. desired baud rate. The RXDTP bit (BAUDCON<5>) allows the RX signal to 2. Enable the asynchronous serial port by clearing be inverted (polarity reversed). Devices that buffer the SYNC bit and setting the SPEN bit. signals from RS-232 to TTL levels also perform an inver- 3. If the signal at the RX pin is to be inverted, set sion of the signal (when RS-232 = positive, TTL = 0). the RXDTP bit. If the signal from the TX pin is to Inverting the polarity of the RX pin data by setting the be inverted, set the TXCKP bit. RXDTP bit allows for the use of circuits that provide 4. If interrupts are required, set the RCEN bit and buffering without inverting the signal. select the desired priority level with the RCIP bit. To set up an Asynchronous Reception: 5. Set the RX9 bit to enable 9-bit reception. 1. Initialize the SPBRGH:SPBRG registers for the 6. Set the ADDEN bit to enable address detect. appropriate baud rate. Set or clear the BRGH 7. Enable reception by setting the CREN bit. and BRG16 bits, as required, to achieve the 8. The RCIF bit will be set when reception is desired baud rate. complete. The interrupt will be Acknowledged if 2. Enable the asynchronous serial port by clearing the RCIE and GIE bits are set. bit, SYNC, and setting bit, SPEN. 9. Read the RCSTA register to determine if any 3. If the signal at the RX pin is to be inverted, set error occurred during reception, as well as read the RXDTP bit. bit 9 of data (if applicable). 4. If interrupts are desired, set enable bit, RCIE. 10. Read RCREG to determine if the device is being 5. If 9-bit reception is desired, set bit, RX9. addressed. 6. Enable the reception by setting bit, CREN. 11. If any error occurred, clear the CREN bit. 7. Flag bit, RCIF, will be set when reception is 12. If the device has been addressed, clear the complete and an interrupt will be generated if ADDEN bit to allow all received data into the enable bit, RCIE, was set. receive buffer and interrupt the CPU. 8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing enable bit, CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. DS39632E-page 256 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 20-6: EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH SPBRG ÷ o6r4 MSb RSR Register LSb ÷ 16 or Stop (8) 7 • • • 1 0 Start Baud Rate Generator ÷ 4 RX9 Pin Buffer Data and Control Recovery RX RX9D RCREG Register FIFO RXDTP SPEN 8 Interrupt RCIF Data Bus RCIE FIGURE 20-7: ASYNCHRONOUS RECEPTION, RXDTP = 0 (RX NOT INVERTED) RX (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set. TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 RCREG EUSART Receive Register 55 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55 SPBRGH EUSART Baud Rate Generator Register High Byte 55 SPBRG EUSART Baud Rate Generator Register Low Byte 55 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: Reserved in 28-pin devices; always maintain these bits clear. © 2009 Microchip Technology Inc. DS39632E-page 257

PIC18F2455/2550/4455/4550 20.2.4 AUTO-WAKE-UP ON SYNC Character and cause data or framing errors. To work BREAK CHARACTER properly, therefore, the initial character in the trans- mission must be all ‘0’s. This can be 00h (8 bits) for During Sleep mode, all clocks to the EUSART are standard RS-232 devices or 000h (12 bits) for LIN bus. suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be per- Oscillator start-up time must also be considered, formed. The auto-wake-up feature allows the controller especially in applications using oscillators with longer to wake-up due to activity on the RX/DT line while the start-up intervals (i.e., XT or HS mode). The Sync EUSART is operating in Asynchronous mode. Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval The auto-wake-up feature is enabled by setting the to allow enough time for the selected oscillator to start WUE bit (BAUDCON<1>). Once set, the typical receive and provide proper initialization of the EUSART. sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event 20.2.4.2 Special Considerations Using independent of the CPU mode. A wake-up event the WUE Bit consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a The timing of WUE and RCIF events may cause some Wake-up Signal character for the LIN protocol.) confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the Following a wake-up event, the module generates an EUSART in an Idle mode. The wake-up event causes a RCIF interrupt. The interrupt is generated synchro- receive interrupt by setting the RCIF bit. The WUE bit is nously to the Q clocks in normal operating modes cleared after this when a rising edge is seen on RX/DT. (Figure20-8) and asynchronously, if the device is in The interrupt condition is then cleared by reading the Sleep mode (Figure20-9). The interrupt condition is RCREG register. Ordinarily, the data in RCREG will be cleared by reading the RCREG register. dummy data and should be discarded. The WUE bit is automatically cleared once a low-to- The fact that the WUE bit has been cleared (or is still high transition is observed on the RX line following the set) and the RCIF flag is set should not be used as an wake-up event. At this point, the EUSART module is in indicator of the integrity of the data in RCREG. Users Idle mode and returns to normal operation. This signals should consider implementing a parallel method in to the user that the Sync Break event is over. firmware to verify received data integrity. 20.2.4.1 Special Considerations Using To assure that no actual data is lost, check the RCIDL Auto-Wake-up bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may Since auto-wake-up functions by sensing rising edge then be set just prior to entering the Sleep mode. transitions on RX/DT, information with any state changes before the Stop bit may signal a false End-Of- FIGURE 20-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RX/DT Line RCIF Cleared due to user read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 20-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RX/DT Line Note 1 RCIF Cleared due to user read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. DS39632E-page 258 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 20.2.5 BREAK CHARACTER SEQUENCE 1. Configure the EUSART for the desired mode. The EUSART module has the capability of sending the 2. Set the TXEN and SENDB bits to set up the special Break character sequences that are required by Break character. the LIN bus standard. The Break character transmit 3. Load the TXREG with a dummy character to consists of a Start bit, followed by twelve ‘0’ bits and a initiate transmission (the value is ignored). Stop bit. The Frame Break character is sent whenever 4. Write ‘55h’ to TXREG to load the Sync character the SENDB and TXEN bits (TXSTA<3> and into the transmit FIFO buffer. TXSTA<5>) are set while the Transmit Shift Register is 5. After the Break has been sent, the SENDB bit is loaded with data. Note that the value of data written to reset by hardware. The Sync character now TXREG will be ignored and all ‘0’s will be transmitted. transmits in the preconfigured mode. The SENDB bit is automatically reset by hardware after When the TXREG becomes empty, as indicated by the the corresponding Stop bit is sent. This allows the user TXIF, the next data byte can be written to TXREG. to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync 20.2.6 RECEIVING A BREAK CHARACTER character in the LIN specification). The Enhanced USART module can receive a Break Note that the data value written to the TXREG for the character in two ways. Break character is ignored. The write simply serves the The first method forces configuration of the baud rate purpose of initiating the proper sequence. at a frequency of 9/13 the typical speed. This allows for The TRMT bit indicates when the transmit operation is the Stop bit transition to be at the correct sampling active or Idle, just as it does during normal transmis- location (13 bits for Break versus Start bit and 8 data sion. See Figure20-10 for the timing of the Break bits for typical data). character sequence. The second method uses the auto-wake-up feature 20.2.5.1 Break and Sync Transmit Sequence described in Section20.2.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the The following sequence will send a message frame EUSART will sample the next two transitions on RX/DT, header made up of a Break, followed by an Auto-Baud cause an RCIF interrupt and receive the next data byte Sync byte. This sequence is typical of a LIN bus followed by another interrupt. master. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed. FIGURE 20-10: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag) © 2009 Microchip Technology Inc. DS39632E-page 259

PIC18F2455/2550/4455/4550 20.3 EUSART Synchronous Once the TXREG register transfers the data to the TSR Master Mode register (occurs in one TCY), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be The Synchronous Master mode is entered by setting enabled or disabled by setting or clearing the interrupt the CSRC bit (TXSTA<7>). In this mode, the data is enable bit, TXIE (PIE1<4>). TXIF is set regardless of transmitted in a half-duplex manner (i.e., transmission the state of enable bit, TXIE; it cannot be cleared in and reception do not occur at the same time). When software. It will reset only when new data is loaded into transmitting data, the reception is inhibited and vice the TXREG register. versa. Synchronous mode is entered by setting bit, While flag bit, TXIF, indicates the status of the TXREG SYNC (TXSTA<4>). In addition, enable bit, SPEN register, another bit, TRMT (TXSTA<1>), shows the (RCSTA<7>), is set in order to configure the TX and RX status of the TSR register. TRMT is a read-only bit which pins to CK (clock) and DT (data) lines, respectively. is set when the TSR is empty. No interrupt logic is tied to The Master mode indicates that the processor this bit so the user has to poll this bit in order to deter- transmits the master clock on the CK line. mine if the TSR register is empty. The TSR is not Clock polarity (CK) is selected with the TXCKP bit mapped in data memory so it is not available to the user. (BAUDCON<4>). Setting TXCKP sets the Idle state on To set up a Synchronous Master Transmission: CK as high, while clearing the bit sets the Idle state as 1. Initialize the SPBRGH:SPBRG registers for the low. Data polarity (DT) is selected with the RXDTP bit appropriate baud rate. Set or clear the BRG16 (BAUDCON<5>). Setting RXDTP sets the Idle state on bit, as required, to achieve the desired baud rate. DT as high, while clearing the bit sets the Idle state as 2. Enable the synchronous master serial port by low. DT is sampled when CK returns to its idle state. setting bits, SYNC, SPEN and CSRC. This option is provided to support Microwire devices with this module. 3. If interrupts are desired, set enable bit, TXIE. 4. If 9-bit transmission is desired, set bit, TX9. 20.3.1 EUSART SYNCHRONOUS MASTER 5. Enable the transmission by setting bit, TXEN. TRANSMISSION 6. If 9-bit transmission is selected, the ninth bit The EUSART transmitter block diagram is shown in should be loaded in bit, TX9D. Figure20-3. The heart of the transmitter is the Transmit 7. Start transmission by loading data to the TXREG (Serial) Shift Register (TSR). The Shift register obtains register. its data from the Read/Write Transmit Buffer register, 8. If using interrupts, ensure that the GIE and PEIE TXREG. The TXREG register is loaded with data in bits in the INTCON register (INTCON<7:6>) are software. The TSR register is not loaded until the last set. bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). FIGURE 20-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT/ SDO pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX/CK pin (TXCKP = 0) RC6/TX/CK pin (TXCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. DS39632E-page 260 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT/SDO pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 TXREG EUSART Transmit Register 55 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55 SPBRGH EUSART Baud Rate Generator Register High Byte 55 SPBRG EUSART Baud Rate Generator Register Low Byte 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: Reserved in 28-pin devices; always maintain these bits clear. © 2009 Microchip Technology Inc. DS39632E-page 261

PIC18F2455/2550/4455/4550 20.3.2 EUSART SYNCHRONOUS 4. If the signal from the CK pin is to be inverted, set MASTER RECEPTION the TXCKP bit. If the signal from the DT pin is to be inverted, set the RXDTP bit. Once Synchronous mode is selected, reception is 5. If interrupts are desired, set enable bit, RCIE. enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive 6. If 9-bit reception is desired, set bit, RX9. Enable bit, CREN (RCSTA<4>). Data is sampled on the 7. If a single reception is required, set bit, SREN. RX pin on the falling edge of the clock. For continuous reception, set bit, CREN. If enable bit, SREN, is set, only a single word is 8. Interrupt flag bit, RCIF, will be set when reception received. If enable bit, CREN, is set, the reception is is complete and an interrupt will be generated if continuous until CREN is cleared. If both bits are set, the enable bit, RCIE, was set. then CREN takes precedence. 9. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred To set up a Synchronous Master Reception: during reception. 1. Initialize the SPBRGH:SPBRG registers for the 10. Read the 8-bit received data by reading the appropriate baud rate. Set or clear the BRG16 RCREG register. bit, as required, to achieve the desired baud rate. 11. If any error occurred, clear the error by clearing 2. Enable the synchronous master serial port by bit, CREN. setting bits, SYNC, SPEN and CSRC. 12. If using interrupts, ensure that the GIE and PEIE bits 3. Ensure bits, CREN and SREN, are clear. in the INTCON register (INTCON<7:6>) are set. FIGURE 20-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT/SDO pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX/CK pin (TXCKP = 0) RC6/TX/CK pin (TXCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 RCREG EUSART Receive Register 55 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55 SPBRGH EUSART Baud Rate Generator Register High Byte 55 SPBRG EUSART Baud Rate Generator Register Low Byte 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: Reserved in 28-pin devices; always maintain these bits clear. DS39632E-page 262 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 20.4 EUSART Synchronous To set up a Synchronous Slave Transmission: Slave Mode 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, Synchronous Slave mode is entered by clearing bit, CSRC. CSRC (TXSTA<7>). This mode differs from the 2. Clear bits, CREN and SREN. Synchronous Master mode in that the shift clock is sup- plied externally at the CK pin (instead of being supplied 3. If interrupts are desired, set enable bit, TXIE. internally in Master mode). This allows the device to 4. If the signal from the CK pin is to be inverted, set transfer or receive data while in any power-managed the TXCKP bit. If the signal from the DT pin is to mode. be inverted, set the RXDTP bit. 5. If 9-bit transmission is desired, set bit, TX9. 20.4.1 EUSART SYNCHRONOUS 6. Enable the transmission by setting enable bit, SLAVE TRANSMISSION TXEN. The operation of the Synchronous Master and Slave 7. If 9-bit transmission is selected, the ninth bit modes is identical, except in the case of the Sleep should be loaded in bit, TX9D. mode. 8. Start transmission by loading data to the TXREG If two words are written to the TXREG and then the register. SLEEP instruction is executed, the following will occur: 9. If using interrupts, ensure that the GIE and PEIE a) The first word will immediately transfer to the bits in the INTCON register (INTCON<7:6>) are TSR register and transmit. set. b) The second word will remain in the TXREG register. c) Flag bit, TXIF, will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit, TXIF, will now be set. e) If enable bit, TXIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 TXREG EUSART Transmit Register 55 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55 SPBRGH EUSART Baud Rate Generator Register High Byte 55 SPBRG EUSART Baud Rate Generator Register Low Byte 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Note 1: Reserved in 28-pin devices; always maintain these bits clear. © 2009 Microchip Technology Inc. DS39632E-page 263

PIC18F2455/2550/4455/4550 20.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical, except in the case of Sleep, or any CSRC. Idle mode and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCIE. Slave mode. 3. If the signal from the CK pin is to be inverted, set If receive is enabled by setting the CREN bit prior to the TXCKP bit. If the signal from the DT pin is to entering Sleep or any Idle mode, then a word may be be inverted, set the RXDTP bit. received while in this low-power mode. Once the word 4. If 9-bit reception is desired, set bit, RX9. is received, the RSR register will transfer the data to the 5. To enable reception, set enable bit, CREN. RCREG register. If the RCIE enable bit is set, the 6. Flag bit, RCIF, will be set when reception is interrupt generated will wake the chip from the low- complete. An interrupt will be generated if power mode. If the global interrupt is enabled, the enable bit, RCIE, was set. program will branch to the interrupt vector. 7. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55 RCREG EUSART Receive Register 55 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55 SPBRGH EUSART Baud Rate Generator Register High Byte 55 SPBRG EUSART Baud Rate Generator Register Low Byte 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: Reserved in 28-pin devices; always maintain these bits clear. DS39632E-page 264 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 21.0 10-BIT ANALOG-TO-DIGITAL The ADCON0 register, shown in Register21-1, CONVERTER (A/D) MODULE controls the operation of the A/D module. The ADCON1 register, shown in Register21-2, configures The Analog-to-Digital (A/D) converter module has the functions of the port pins. The ADCON2 register, 10inputs for the 28-pin devices and 13 for the shown in Register21-3, configures the A/D clock 40/44-pin devices. This module allows conversion of an source, programmed acquisition time and justification. analog input signal to a corresponding 10-bit digital number. The module has five registers: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12) 1101 = Unimplemented(2) 1110 = Unimplemented(2) 1111 = Unimplemented(2) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Note 1: These channels are not implemented on 28-pin devices. 2: Performing a conversion on unimplemented channels will return a floating input measurement. © 2009 Microchip Technology Inc. DS39632E-page 265

PIC18F2455/2550/4455/4550 REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = VSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = VDD bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits: PCFG3: 12 11 10 9 8 (2)7 (2)6 (2)5 4 3 2 1 0 N N N N N N N N N N N N N PCFG0 A A A A A A A A A A A A A 0000(1) A A A A A A A A A A A A A 0001 A A A A A A A A A A A A A 0010 A A A A A A A A A A A A A 0011 D A A A A A A A A A A A A 0100 D D A A A A A A A A A A A 0101 D D D A A A A A A A A A A 0110 D D D D A A A A A A A A A 0111(1) D D D D D A A A A A A A A 1000 D D D D D D A A A A A A A 1001 D D D D D D D A A A A A A 1010 D D D D D D D D A A A A A 1011 D D D D D D D D D A A A A 1100 D D D D D D D D D D A A A 1101 D D D D D D D D D D D A A 1110 D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D A = Analog input D = Digital I/O Note 1: The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When PBADEN= 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111. 2: AN5 through AN7 are available only on 40/44-pin devices. DS39632E-page 266 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 21-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. © 2009 Microchip Technology Inc. DS39632E-page 267

PIC18F2455/2550/4455/4550 The analog reference voltage is software selectable to A device Reset forces all registers to their Reset state. either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any (VDD and VSS) or the voltage level on the conversion in progress is aborted. RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins. Each port pin associated with the A/D converter can be The A/D converter has a unique feature of being able configured as an analog input or as a digital I/O. The to operate while the device is in Sleep mode. To ADRESH and ADRESL registers contain the result of operate in Sleep, the A/D conversion clock must be the A/D conversion. When the A/D conversion is com- derived from the A/D’s internal RC oscillator. plete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is The output of the sample and hold is the input into the cleared and A/D Interrupt Flag bit, ADIF, is set. The converter, which generates the result via successive block diagram of the A/D module is shown in approximation. Figure21-1. FIGURE 21-1: A/D BLOCK DIAGRAM CHS3:CHS0 1100 AN12 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7(1) 0110 AN6(1) 0101 AN5(1) 0100 AN4 VAIN 10-Bit (Input Voltage) 0011 AN3 Converter A/D 0010 AN2 0001 VCFG1:VCFG0 AN1 VDD(2) 0000 AN0 X0 VREF+ X1 Reference Voltage 1X VREF- 0X VSS(2) Note 1: Channels AN5 through AN7 are not available on 28-pin devices. 2: I/O pins have diode protection to VDD and VSS. DS39632E-page 268 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 The value in the ADRESH:ADRESL registers is 5. Wait for A/D conversion to complete, by either: unknown following POR and BOR Resets and is not • Polling for the GO/DONE bit to be cleared affected by any other Reset. OR After the A/D module has been configured as desired, • Waiting for the A/D interrupt the selected channel must be acquired before the con- 6. Read A/D Result registers (ADRESH:ADRESL); version is started. The analog input channels must have their corresponding TRIS bits selected as an clear bit ADIF, if required. input. To determine acquisition time, see Section21.1 7. For next conversion, go to step 1 or step 2, as “A/D Acquisition Requirements”. After this acquisi- required. The A/D conversion time per bit is tion time has elapsed, the A/D conversion can be defined as TAD. A minimum wait of 3 TAD is started. An acquisition time can be programmed to required before the next acquisition starts. occur between setting the GO/DONE bit and the actual start of the conversion. FIGURE 21-2: A/D TRANSFER FUNCTION The following steps should be followed to perform an A/D conversion: 3FFh 1. Configure the A/D module: 3FEh • Configure analog pins, voltage reference and digital I/O (ADCON1) ut p • Select A/D input channel (ADCON0) Out e • Select A/D acquisition time (ADCON2) d o C003h • Select A/D conversion clock (ADCON2) al • Turn on A/D module (ADCON0) Digit 002h 2. Configure A/D interrupt (if desired): • Clear ADIF bit 001h • Set ADIE bit • Set GIE bit 000h B B B B B B B B B B 3. Wait the required acquisition time (if required). S S S S S S S S S S L L L L L L L L L L 5 1 5 2 5 3 2 5 3 5 4. S•taSret tc GonOv/eDrsOioNnE: bit (ADCON0 register) 0. 1. 2. 102 1022. 102 1023. Analog Input Voltage FIGURE 21-3: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC ≤ 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage 6V ILEAKAGE = Leakage Current at the pin due to 5V various junctions VDD 4V 3V RIC = Interconnect Resistance 2V SS = Sampling Switch CHOLD = Sample/hold Capacitance (from DAC) 1 2 3 4 RSS = Sampling Switch Resistance SamplingSwitch(kΩ) © 2009 Microchip Technology Inc. DS39632E-page 269

PIC18F2455/2550/4455/4550 21.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation21-1 may be used. This equation assumes For the A/D converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is shown in Figure21-3. The Example21-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time TACQ. This calculation is based on the following application system required to charge the capacitor CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 25 pF at the analog input (due to pin leakage current). The Rs = 2.5 kΩ maximum recommended impedance for analog Conversion Error ≤ 1/2 LSb sources is 2.5 kΩ. After the analog input channel is VDD = 5V → RSS = 2 kΩ selected (changed), the channel must be sampled for Temperature = 85°C (system max.) at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 21-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 21-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 μs TCOFF = (Temp – 25°C)(0.02 μs/°C) (85°C – 25°C)(0.02 μs/°C) 1.2 μs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 μs. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) μs -(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs 1.05 μs TACQ = 0.2 μs + 1.05 μs + 1.2 μs 2.45 μs DS39632E-page 270 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 21.2 Selecting and Configuring 21.3 Selecting the A/D Conversion Acquisition Time Clock The ADCON2 register allows the user to select an The A/D conversion time per bit is defined as TAD. The acquisition time that occurs each time the GO/DONE A/D conversion requires 11 TAD per 10-bit conversion. bit is set. It also gives users the option to use an The source of the A/D conversion clock is software automatically determined acquisition time. selectable. There are seven possible options for TAD: Acquisition time may be set with the ACQT2:ACQT0 • 2 TOSC bits (ADCON2<5:3>) which provide a range of 2 to • 4 TOSC 20TAD. When the GO/DONE bit is set, the A/D module • 8 TOSC continues to sample the input for the selected acquisi- • 16 TOSC tion time, then automatically begins a conversion. Since the acquisition time is programmed, there may • 32 TOSC be no need to wait for an acquisition time between • 64 TOSC selecting a channel and setting the GO/DONE bit. • Internal RC Oscillator Manual acquisition is selected when For correct A/D conversions, the A/D conversion clock ACQT2:ACQT0=000. When the GO/DONE bit is set, (TAD) must be as short as possible but greater than the sampling is stopped and a conversion begins. The user minimum TAD (see parameter 130 in Table28-29 for is responsible for ensuring the required acquisition time more information). has passed between selecting the desired input Table21-1 shows the resultant TAD times derived from channel and setting the GO/DONE bit. This option is the device operating frequencies and the A/D clock also the default Reset state of the ACQT2:ACQT0 bits source selected. and is compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. TABLE 21-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Assumes TAD Min. = 0.8µs Operation ADCS2:ADCS0 Maximum FOSC 2 TOSC 000 2.50 MHz 4 TOSC 100 5.00 MHz 8 TOSC 001 10.00 MHz 16 TOSC 101 20.00 MHz 32 TOSC 010 40.00 MHz 64 TOSC 110 48.00 MHz RC(2) x11 1.00 MHz(1) Note 1: The RC source has a typical TAD time of 2.5µs. 2: For device frequencies above 1MHz, the device must be in Sleep for the entire conversion or a FOSC divider should be used instead. Otherwise, the A/D accuracy may be out of specification. © 2009 Microchip Technology Inc. DS39632E-page 271

PIC18F2455/2550/4455/4550 21.4 Operation in Power-Managed 21.5 Configuring Analog Port Pins Modes The ADCON1, TRISA, TRISB and TRISE registers all The selection of the automatic acquisition time and A/D configure the A/D port pins. The port pins needed as conversion clock is determined in part by the clock analog inputs must have their corresponding TRIS bits source and frequency while in a power-managed set (input). If the TRIS bit is cleared (output), the digital mode. output level (VOH or VOL) will be converted. If the A/D is expected to operate while the device is in The A/D operation is independent of the state of the a power-managed mode, the ACQT2:ACQT0 and CHS3:CHS0 bits and the TRIS bits. ADCS2:ADCS0 bits in ADCON2 should be updated in Note1: When reading the PORT register, all pins accordance with the clock source to be used in that configured as analog input channels will mode. After entering the mode, an A/D acquisition or read as cleared (a low level). Pins config- conversion may be started. Once started, the device ured as digital inputs will convert as should continue to be clocked by the same clock analog inputs. Analog levels on a digitally source until the conversion has been completed. configured input will be accurately If desired, the device may be placed into the converted. corresponding Idle mode during the conversion. If the 2: Analog levels on any pin defined as a device clock frequency is less than 1MHz, the A/D RC digital input may cause the digital input clock source should be selected. buffer to consume current out of the Operation in the Sleep mode requires the A/D FRC device’s specification limits. clock to be selected. If bits ACQT2:ACQT0 are set to 3: The PBADEN bit in Configuration ‘000’ and a conversion is started, the conversion will be Register 3H configures PORTB pins to delayed one instruction cycle to allow execution of the reset as analog or digital pins by control- SLEEP instruction and entry to Sleep mode. The IDLEN ling how the PCFG0 bits in ADCON1 are bit (OSCCON<7>) must have already been cleared reset. prior to starting the conversion. DS39632E-page 272 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 21.6 A/D Conversions After the A/D conversion is completed or aborted, a 2TCY wait is required before the next acquisition can be Figure21-4 shows the operation of the A/D converter started. After this wait, acquisition on the selected after the GO/DONE bit has been set and the channel is automatically started. ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Note: The GO/DONE bit should NOT be set in Sleep mode before the conversion begins. the same instruction that turns on the A/D. Code should wait at least 2µs after Figure21-5 shows the operation of the A/D converter enabling the A/D before beginning an after the GO/DONE bit has been set, the acquisition and conversion cycle. ACQT2:ACQT0 bits are set to ‘010’ and selecting a 4TAD acquisition time before the conversion starts. 21.7 Discharge Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register The discharge phase is used to initialize the value of pair will NOT be updated with the partially completed the capacitor array. The array is discharged before A/D conversion sample. This means the every sample. This feature helps to optimize the ADRESH:ADRESL registers will continue to contain unity-gain amplifier as the circuit always needs to the value of the last completed conversion (or the last charge the capacitor array, rather than value written to the ADRESH:ADRESL registers). charge/discharge based on previous measurement values. FIGURE 21-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 TAD1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Discharge (Typically 200ns) Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 21-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQ Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 TAD1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Discharge Conversion starts Time (Typically (Holding capacitor is disconnected) 200ns) Set GO/DONE bit (Holding capacitor continues On the following cycle: acquiring input) ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. © 2009 Microchip Technology Inc. DS39632E-page 273

PIC18F2455/2550/4455/4550 21.8 Use of the CCP2 Trigger software overhead (moving ADRESH:ADRESL to the desired location). The appropriate analog input chan- An A/D conversion can be started by the Special Event nel must be selected and the minimum acquisition Trigger of the CCP2 module. This requires that the period is either timed by the user, or an appropriate CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- TACQ time selected before the Special Event Trigger grammed as ‘1011’ and that the A/D module is enabled sets the GO/DONE bit (starts a conversion). (ADON bit is set). When the trigger occurs, the If the A/D module is not enabled (ADON is cleared), the GO/DONE bit will be set, starting the A/D acquisition Special Event Trigger will be ignored by the A/D module and conversion and the Timer1 (or Timer3) counter will but will still reset the Timer1 (or Timer3) counter. be reset to zero. Timer1 (or Timer3) is reset to automat- ically repeat the A/D acquisition period with minimal TABLE 21-2: REGISTERS ASSOCIATED WITH A/D OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 SPPIF(4) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56 PIE1 SPPIE(4) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56 IPR1 SPPIP(4) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56 ADRESH A/D Result Register High Byte 54 ADRESL A/D Result Register Low Byte 54 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 54 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 54 PORTA — RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 56 TRISA — TRISA6(2) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 56 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 56 PORTE RDPU(4) — — — RE3(1,3) RE2(4) RE1(4) RE0(4) 56 TRISE(4) — — — — — TRISE2 TRISE1 TRISE0 56 LATE(4) — — — — — LATE2 LATE1 LATE0 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’. 4: These registers and/or bits are not implemented on 28-pin devices. DS39632E-page 274 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 22.0 COMPARATOR MODULE The CMCON register (Register22-1) selects the comparator input and output configuration. Block The analog comparator module contains two compara- diagrams of the various comparator configurations are tors that can be configured in a variety of ways. The shown in Figure22-1. inputs can be selected from the analog inputs multiplexed with pins RA0 through RA5, as well as the on-chip volt- age reference (see Section23.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register. REGISTER 22-1: CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RA3/AN3/VREF+ C2 VIN- connects to RA2/AN2/VREF-/CVREF 0 = C1 VIN- connects to RA0/AN0 C2 VIN- connects to RA1/AN1 bit 2-0 CM2:CM0: Comparator Mode bits Figure22-1 shows the Comparator modes and the CM2:CM0 bit settings. © 2009 Microchip Technology Inc. DS39632E-page 275

PIC18F2455/2550/4455/4550 22.1 Comparator Configuration mode is changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Section28.0 “Electrical Characteristics”. tors, shown in Figure22-1. Bits, CM2:CM0 of the CMCON register, are used to select these modes. The Note: Comparator interrupts should be disabled TRISA register controls the data direction of the during a Comparator mode change. comparator pins for each mode. If the Comparator Otherwise, a false interrupt may occur. FIGURE 22-1: COMPARATOR I/O OPERATING MODES Comparators Reset Comparators Off (POR Default Value) CM2:CM0 = 000 CM2:CM0 = 111 RA0/AN0 A VIN- RA0/AN0 D VIN- RA3/AN3/ A VIN+ C1 Off (Read as ‘0’) RA3/AN3/ D VIN+ C1 Off (Read as ‘0’) VREF+ VREF+ RA1/AN1 A VIN- RA1/AN1 D VIN- RA2/AN2/ A VIN+ C2 Off (Read as ‘0’) RA2/AN2/ D VIN+ C2 Off (Read as ‘0’) VREF-/CVREF VREF-/CVREF Two Independent Comparators Two Independent Comparators with Outputs CM2:CM0 = 010 CM2:CM0 = 011 RA0/AN0 A VIN- RA0/AN0 A VIN- RA3/AN3/ A VIN+ C1 C1OUT RA3/AN3/ A VIN+ C1 C1OUT VREF+ VREF+ RA4/T0CKI/C1OUT*/RCV RA1/AN1 A VIN- RA2/AN2/ A VIN+ C2 C2OUT RA1/AN1 A VIN- VREF-/CVREF RA2/AN2/ A VIN+ C2 C2OUT VREF-/CVREF RA5/AN4/SS/HLVDIN/C2OUT* Two Common Reference Comparators Two Common Reference Comparators with Outputs CM2:CM0 = 100 CM2:CM0 = 101 RA0/AN0 A VIN- RA0/AN0 A VIN- RA3/AN3/ A VIN+ C1 C1OUT RA3/AN3/ A VIN+ C1 C1OUT VREF+ VREF+ RA4/T0CKI/C1OUT*/ RCV RA1/AN1 A VIN- RA2/AN2/ D VIN+ C2 C2OUT RA1/AN1 A VIN- VREF-/CVREF RA2/AN2/ D VIN+ C2 C2OUT VREF-/CVREF RA5/AN4/SS/HLVDIN/C2OUT* One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM2:CM0 = 001 CM2:CM0 = 110 RA0/AN0 A VIN- RA0/AN0 A CIS = 0 VIN- RVRAE3F/A+N3/ A VIN+ C1 C1OUT RVRAE3F/A+N3/ A CIS = 1 VIN+ C1 C1OUT RA4/T0CKI/C1OUT*/RCV RA1/AN1 A CIS = 0 VIN- RA1/AN1 D VIN- RVRAE2F/A-/CNV2/REFA CIS = 1 VIN+ C2 C2OUT RA2/AN2/ D VIN+ C2 Off (Read as ‘0’) CVREF VREF-/CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs. DS39632E-page 276 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 22.2 Comparator Operation 22.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure22-2, along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference from the the digital output. When the analog input at VIN+ is less comparator voltage reference module. This module is than the analog input VIN-, the output of the comparator described in more detail in Section23.0 “Comparator is a digital low level. When the analog input at VIN+ is Voltage Reference Module”. greater than the analog input VIN-, the output of the The internal reference is only available in the mode comparator is a digital high level. The shaded areas of where four inputs are multiplexed to two comparators the output of the comparator in Figure22-2 represent (CM2:CM0=110). In this mode, the internal voltage the uncertainty, due to input offsets and response time. reference is applied to the VIN+ pin of both comparators. 22.3 Comparator Reference 22.4 Comparator Response Time Depending on the comparator operating mode, either an external or internal voltage reference may be used. Response time is the minimum time, after selecting a The analog signal present at VIN- is compared to the new reference voltage or input source, before the signal at VIN+ and the digital output of the comparator comparator output has a valid level. If the internal ref- is adjusted accordingly (Figure22-2). erence is changed, the maximum delay of the internal voltage reference must be considered when using the FIGURE 22-2: SINGLE COMPARATOR comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section28.0 “Electrical Characteristics”). VIN+ + 22.5 Comparator Outputs Output VIN- – The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RA4 and RA5 I/O pins. When enabled, multiplexors in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the VIN- comparator. The uncertainty of each of the comparators is related to the input offset voltage and VIN+ the response time given in the specifications. Figure22-3 shows the comparator output block diagram. Output The TRISA bits will still function as an output enable/ disable for the RA4 and RA5 pins while in this mode. The polarity of the comparator outputs can be changed 22.3.1 EXTERNAL REFERENCE SIGNAL using the C2INV and C1INV bits (CMCON<5:4>). When external voltage references are used, the Note1: When reading the PORT register, all pins comparator module can be configured to have the com- configured as analog inputs will read as a parators operate from the same or different reference ‘0’. Pins configured as digital inputs will sources. However, threshold detector applications may convert an analog input according to the require the same reference. The reference signal must Schmitt Trigger input specification. be between VSS and VDD and can be applied to either 2: Analog levels on any pin defined as a pin of the comparator(s). digital input may cause the input buffer to consume more current than is specified. © 2009 Microchip Technology Inc. DS39632E-page 277

PIC18F2455/2550/4455/4550 FIGURE 22-3: COMPARATOR OUTPUT BLOCK DIAGRAM X E L + Port Pins P TI To CxOUT UL - pin M D Q Bus CxINV Data Read CMCON EN D Q Set CMIF bit EN CL From Other Reset Comparator 22.6 Comparator Interrupts 22.7 Comparator Operation During Sleep The comparator interrupt flag is set whenever there is a change in the output value of either comparator. When a comparator is active and the device is placed Software will need to maintain information about the in Sleep mode, the comparator remains active and the status of the output bits, as read from CMCON<7:6>, to interrupt is functional if enabled. This interrupt will determine the actual change that occurred. The CMIF wake-up the device from Sleep mode, when enabled. bit (PIR2<6>) is the Comparator Interrupt Flag. The Each operational comparator will consume additional CMIF bit must be reset by clearing it. Since it is also current, as shown in the comparator specifications. To possible to write a ‘1’ to this register, a simulated minimize power consumption while in Sleep mode, turn interrupt may be initiated. off the comparators (CM2:CM0=111) before entering Both the CMIE bit (PIE2<6>) and the PEIE bit (INT- Sleep. If the device wakes up from Sleep, the contents CON<6>) must be set to enable the interrupt. In addi- of the CMCON register are not affected. tion, the GIE bit (INTCON<7>) must also be set. If any 22.8 Effects of a Reset of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt A device Reset forces the CMCON register to its Reset condition occurs. state, causing the comparator modules to be turned off Note: If a change in the CMCON register (CM2:CM0=111). However, the input pins (RA0 (C1OUT or C2OUT) should occur when a through RA3) are configured as analog inputs by read operation is being executed (start of default on device Reset. The I/O configuration for these the Q2 cycle), then the CMIF (PIR2<6>) pins is determined by the setting of the PCFG3:PCFG0 interrupt flag may not get set. bits (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at Reset The user, in the Interrupt Service Routine, can clear the time. interrupt in the following manner: a) Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. DS39632E-page 278 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 22.9 Analog Input Connection range by more than 0.6V in either direction, one of the Considerations diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10kΩ is A simplified circuit for an analog input is shown in recommended for the analog sources. Any external Figure22-4. Since the analog pins are connected to a component connected to an analog input pin, such as digital output, they have reverse biased diodes to VDD a capacitor or a Zener diode, should have very little and VSS. The analog input, therefore, must be between leakage current. VSS and VDD. If the input voltage deviates from this FIGURE 22-4: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L5E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 55 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 55 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56 PORTA — RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 56 LATA — LATA6(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 56 TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: PORTA<6> and its direction and latch bits are individually configured as port pins based on various oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. DS39632E-page 279

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PIC18F2455/2550/4455/4550 23.0 COMPARATOR VOLTAGE used is selected by the CVRR bit (CVRCON<5>). The REFERENCE MODULE primary difference between the ranges is the size of the steps selected by the CVREF Selection bits The comparator voltage reference is a 16-tap resistor (CVR3:CVR0), with one range offering finer resolution. ladder network that provides a selectable reference The equations used to calculate the output of the voltage. Although its primary purpose is to provide a comparator voltage reference are as follows: reference for the analog comparators, it may also be If CVRR = 1: used independently of them. CVREF = ((CVR3:CVR0)/24) x CVRSRC A block diagram of the module is shown in Figure23-1. If CVRR = 0: The resistor ladder is segmented to provide two ranges CVREF = (CVRSRC/4) + (((CVR3:CVR0)/32) x of CVREF values and has a power-down function to CVRSRC) conserve power when the reference is not being used. The comparator reference supply voltage can come The module’s supply reference can be provided from either device VDD/VSS or an external voltage reference. from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit 23.1 Configuring the Comparator (CVRCON<4>). Voltage Reference The settling time of the comparator voltage reference The voltage reference module is controlled through the must be considered when changing the CVREF CVRCON register (Register23-1). The comparator output (see Table28-3 in Section28.0 “Electrical voltage reference provides two ranges of output Characteristics”). voltage, each with 16 distinct levels. The range to be REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin 0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = VDD – VSS bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15) When CVRR = 1: CVREF = ((CVR3:CVR0)/24) • (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC) Note 1: CVROE overrides the TRISA<2> bit setting. © 2009 Microchip Technology Inc. DS39632E-page 281

PIC18F2455/2550/4455/4550 FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ VDD CVRSS = 0 8R CVR3:CVR0 R CVREN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 23.2 Voltage Reference Accuracy/Error 23.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit, CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RA2 pin by clearing (Figure23-1) keep CVREF from approaching the refer- bit, CVROE (CVRCON<6>) and selects the high-voltage ence source rails. The voltage reference is derived range by clearing bit, CVRR (CVRCON<5>). The CVR from the reference source; therefore, the CVREF output value select bits are also cleared. changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be 23.5 Connection Considerations found in Section28.0 “Electrical Characteristics”. The voltage reference module operates independently 23.3 Operation During Sleep of the comparator module. The output of the reference generator may be connected to the RA2 pin if the When the device wakes up from Sleep through an TRISA<2> bit and the CVROE bit are both set. interrupt or a Watchdog Timer time-out, the contents of Enabling the voltage reference output onto RA2 when the CVRCON register are not affected. To minimize it is configured as a digital input will increase current current consumption in Sleep mode, the voltage consumption. Connecting RA2 as a digital output with reference should be disabled. CVRSS enabled will also increase current consumption. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure23-2 shows an example buffering technique. DS39632E-page 282 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 23-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXXX CVREF R(1) Module + Voltage RA2 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<5> and CVRCON<3:0>. TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 55 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 55 TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56 Legend: Shaded cells are not used with the comparator voltage reference. Note 1: PORTA<6> and its direction and latch bits are individually configured as port pins based on various oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. DS39632E-page 283

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 284 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 24.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect Control register (HLVD) (Register24-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned PIC18F2455/2550/4455/4550 devices have a off” by the user under software control which minimizes High/Low-Voltage Detect module (HLVD). This is a pro- the current consumption for the device. grammable circuit that allows the user to specify both a The block diagram for the HLVD module is shown in device voltage trip point and the direction of change Figure24-1. from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. REGISTER 24-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0) 0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0) bit 6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL3:HLVDL0: Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting Note 1: See Table28-6 in Section28.0 “Electrical Characteristics” for specifications. © 2009 Microchip Technology Inc. DS39632E-page 285

PIC18F2455/2550/4455/4550 The module is enabled by setting the HLVDEN bit. event, depending on the configuration of the module. Each time that the HLVD module is enabled, the When the supply voltage is equal to the trip point, the circuitry requires some time to stabilize. The IRVST bit voltage tapped off of the resistor array is equal to the is a read-only bit and is used to indicate when the circuit internal reference voltage generated by the voltage is stable. The module can only generate an interrupt reference module. The comparator then generates an after the circuit is stable and IRVST is set. interrupt signal by setting the HLVDIF bit. The VDIRMAG bit determines the overall operation of The trip point voltage is software programmable to any the module. When VDIRMAG is cleared, the module one of 16 values. The trip point is selected by monitors for drops in VDD below a predetermined set programming the HLVDL3:HLVDL0 bits point. When the bit is set, the module monitors for rises (HLVDCON<3:0>). in VDD above the set point. The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an 24.1 Operation external source. This mode is enabled when bits, HLVDL3:HLVDL0, are set to ‘1111’. In this state, the When the HLVD module is enabled, a comparator uses comparator input is multiplexed from the external input an internally generated reference voltage as the set pin, HLVDIN. This gives users flexibility because it point. The set point is compared with the trip point, allows them to configure the High/Low-Voltage Detect where each node in the resistor divider represents a interrupt to occur at any voltage in the valid operating trip point voltage. The “trip point” voltage is the voltage range. level at which the device detects a high or low-voltage FIGURE 24-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL3:HLVDL0 HLVDCON Register HLVDEN VDIRMAG HLVDIN X Set U M HLVDIF 1 o- 6-t 1 HLVDEN Internal Voltage Reference BOREN 1.2V Typical DS39632E-page 286 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 24.2 HLVD Setup Depending on the application, the HLVD module does not need to be operating constantly. To decrease the The following steps are needed to set up the HLVD current requirements, the HLVD circuitry may only module: need to be enabled for short periods where the voltage 1. Disable the module by clearing the HLVDEN bit is checked. After doing the check, the HLVD module (HLVDCON<4>). may be disabled. 2. Write the value to the HLVDL3:HLVDL0 bits that selects the desired HLVD trip point. 24.4 HLVD Start-up Time 3. Set the VDIRMAG bit to detect high voltage The internal reference voltage of the HLVD module, (VDIRMAG = 1) or low voltage (VDIRMAG = 0). specified in electrical specification parameter D420 (see 4. Enable the HLVD module by setting the Table28-6 in Section28.0 “Electrical Characteris- HLVDEN bit. tics”), may be used by other internal circuitry, such as 5. Clear the HLVD Interrupt Flag, HLVDIF the Programmable Brown-out Reset. If the HLVD or (PIR2<2>), which may have been set from a other circuits using the voltage reference are disabled to previous interrupt. lower the device’s current consumption, the reference 6. Enable the HLVD interrupt, if interrupts are voltage circuit will require time to become stable before desired, by setting the HLVDIE and GIE/GIEH a low or high-voltage condition can be reliably detected. bits (PIE2<2> and INTCON<7>). An interrupt This start-up time, TIRVST, is an interval that is indepen- will not be generated until the IRVST bit is set. dent of device clock speed. It is specified in electrical specification parameter36 (Table28-12). 24.3 Current Consumption The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For When the module is enabled, the HLVD comparator this reason, brief excursions beyond the set point may and voltage divider are enabled and will consume static not be detected during this interval. Refer to current. The total current consumption, when enabled, Figure24-2 or Figure24-3. is specified in electrical specification parameter D022 (Section 28.2 “DC Characteristics”). FIGURE 24-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VDD VHLVD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists © 2009 Microchip Technology Inc. DS39632E-page 287

PIC18F2455/2550/4455/4550 FIGURE 24-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists 24.5 Applications FIGURE 24-4: TYPICAL HIGH/LOW-VOLTAGE In many applications, the ability to detect a drop below DETECT APPLICATION or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a high-voltage detect from, for example, VA 3.3V to 5V (the voltage on USB) and vice versa for a VB detach. This feature could save a design a few extra e components and an attach signal (input pin). ag For general battery applications, Figure24-4 shows a Volt possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an ISR, which would allow the application to perform “house- Time TA TB keeping tasks” and perform a controlled shutdown before the device voltage exits the valid operating Legend: VA = HLVD trip point range at TB. The HLVD, thus, would give the applica- VB = Minimum valid device tion a time window, represented by the difference operating voltage between TA and TB, to safely exit. DS39632E-page 288 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 24.6 Operation During Sleep 24.7 Effects of a Reset When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state. during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off. point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 24-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 54 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. © 2009 Microchip Technology Inc. DS39632E-page 289

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 290 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 25.0 SPECIAL FEATURES OF THE In addition to their Power-up and Oscillator Start-up Tim- CPU ers provided for Resets, PIC18F2455/2550/4455/4550 devices have a Watchdog Timer, which is either PIC18F2455/2550/4455/4550 devices include several permanently enabled via the Configuration bits or features intended to maximize reliability and minimize software controlled (if configured as disabled). cost through elimination of external components. The inclusion of an internal RC oscillator also provides These are: the additional benefits of a Fail-Safe Clock Monitor • Oscillator Selection (FSCM) and Two-Speed Start-up. FSCM provides for • Resets: background monitoring of the peripheral clock and automatic switchover in the event of its failure. - Power-on Reset (POR) Two-Speed Start-up enables code to be executed - Power-up Timer (PWRT) almost immediately on start-up, while the primary clock - Oscillator Start-up Timer (OST) source completes its start-up delays. - Brown-out Reset (BOR) All of these features are enabled and configured by • Interrupts setting the appropriate Configuration register bits. • Watchdog Timer (WDT) • Fail-Safe Clock Monitor • Two-Speed Start-up • Code Protection • ID Locations • In-Circuit Serial Programming The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section2.0 “Oscillator Configurations”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. © 2009 Microchip Technology Inc. DS39632E-page 291

PIC18F2455/2550/4455/4550 25.1 Configuration Bits Programming the Configuration registers is done in a manner similar to programming the Flash memory. The The Configuration bits can be programmed (read as WR bit in the EECON1 register starts a self-timed write ‘0’) or left unprogrammed (read as ‘1’) to select various to the Configuration register. In normal operation mode, device configurations. These bits are mapped starting a TBLWT instruction, with the TBLPTR pointing to the at program memory location 300000h. Configuration register, sets up the address and the The user will note that address 300000h is beyond the data for the Configuration register write. Setting the WR user program memory space. In fact, it belongs to the bit starts a long write to the Configuration register. The configuration memory space (300000h-3FFFFFh), Configuration registers are written a byte at a time. To which can only be accessed using table reads and write or erase a configuration cell, a TBLWT instruction table writes. can write a ‘1’ or a ‘0’ into the cell. For additional details on Flash programming, refer to Section6.5 “Writing to Flash Program Memory”. TABLE 25-1: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300000h CONFIG1L — — USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0 --00 0000 300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0101 300002h CONFIG2L — — VREGEN BORV1 BORV0 BOREN1 BOREN0 PWRTEN --01 1111 300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111 300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN CCP2MX 1--- -011 300006h CONFIG4L DEBUG XINST ICPRT(3) — — LVP — STVREN 100- -1-1 300008h CONFIG5L — — — — CP3(1) CP2 CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L — — — — WRT3(1) WRT2 WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — EBTR3(1) EBTR2 EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(2) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0001 0010(2) Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set. 2: See Register25-13 and Register25-14 for DEVID values. DEVID registers are read-only and cannot be programmed by the user. 3: Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices. DS39632E-page 292 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 25-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) U-0 U-0 R/P-0 R/P-0 R/P-0 R/P-0 R/P-0 R/P-0 — — USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-6 Unimplemented: Read as ‘0’ bit 5 USBDIV: USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) 1 = USB clock source comes from the 96MHz PLL divided by 2 0 = USB clock source comes directly from the primary oscillator block with no postscale bit 4-3 CPUDIV1:CPUDIV0: System Clock Postscaler Selection bits For XT, HS, EC and ECIO Oscillator modes: 11 = Primary oscillator divided by 4 to derive system clock 10 = Primary oscillator divided by 3 to derive system clock 01 = Primary oscillator divided by 2 to derive system clock 00 = Primary oscillator used directly for system clock (no postscaler) For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes: 11 = 96MHz PLL divided by 6 to derive system clock 10 = 96MHz PLL divided by 4 to derive system clock 01 = 96MHz PLL divided by 3 to derive system clock 00 = 96MHz PLL divided by 2 to derive system clock bit 2-0 PLLDIV2:PLLDIV0: PLL Prescaler Selection bits 111 = Divide by 12 (48MHz oscillator input) 110 = Divide by 10 (40MHz oscillator input) 101 = Divide by 6 (24MHz oscillator input) 100 = Divide by 5 (20MHz oscillator input) 011 = Divide by 4 (16MHz oscillator input) 010 = Divide by 3 (12MHz oscillator input) 001 = Divide by 2 (8MHz oscillator input) 000 = No prescale (4MHz oscillator input drives PLL directly) © 2009 Microchip Technology Inc. DS39632E-page 293

PIC18F2455/2550/4455/4550 REGISTER 25-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-0 R/P-1 IESO FCMEN — — FOSC3(1) FOSC2(1) FOSC1(1) FOSC0(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 FOSC3:FOSC0: Oscillator Selection bits(1) 111x = HS oscillator, PLL enabled (HSPLL) 110x = HS oscillator (HS) 1011 = Internal oscillator, HS oscillator used by USB (INTHS) 1010 = Internal oscillator, XT used by USB (INTXT) 1001 = Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO) 1000 = Internal oscillator, port function on RA6, EC used by USB (INTIO) 0111 = EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL) 0110 = EC oscillator, PLL enabled, port function on RA6 (ECPIO) 0101 = EC oscillator, CLKO function on RA6 (EC) 0100 = EC oscillator, port function on RA6 (ECIO) 001x = XT oscillator, PLL enabled (XTPLL) 000x = XT oscillator (XT) Note 1: The microcontroller and USB module both use the selected oscillator as their clock source in XT, HS and EC modes. The USB module uses the indicated XT, HS or EC oscillator as its clock source whenever the microcontroller uses the internal oscillator. DS39632E-page 294 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 25-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — VREGEN BORV1(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-6 Unimplemented: Read as ‘0’ bit 5 VREGEN: USB Internal Voltage Regulator Enable bit 1 = USB voltage regulator enabled 0 = USB voltage regulator disabled bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits(1) 11 = Minimum setting . . . 00 = Maximum setting bit 2-1 BOREN1:BOREN0: Brown-out Reset Enable bits(2) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled Note 1: See Section28.0 “Electrical Characteristics” for the specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. © 2009 Microchip Technology Inc. DS39632E-page 295

PIC18F2455/2550/4455/4550 REGISTER 25-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) DS39632E-page 296 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 25-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 R/P-1 MCLRE — — — — LPT1OSC PBADEN CCP2MX bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled, RE3 input pin disabled 0 = RE3 input pin enabled, MCLR pin disabled bit 6-3 Unimplemented: Read as ‘0’ bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation bit 1 PBADEN: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.) 1 = PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset bit 0 CCP2MX: CCP2 MUX bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 © 2009 Microchip Technology Inc. DS39632E-page 297

PIC18F2455/2550/4455/4550 REGISTER 25-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 R/P-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG XINST ICPRT(1) — — LVP — STVREN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5 ICPRT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit(1) 1 = ICPORT enabled 0 = ICPORT disabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 LVP: Single-Supply ICSP™ Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Note 1: Available only in the 44-pin TQFP packages. Always leave this bit clear in all other devices. DS39632E-page 298 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 25-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2 CP1 CP0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 (006000-007FFFh) is not code-protected 0 = Block 3 (006000-007FFFh) is code-protected bit 2 CP2: Code Protection bit 1 = Block 2 (004000-005FFFh) is not code-protected 0 = Block 2 (004000-005FFFh) is code-protected bit 1 CP1: Code Protection bit 1 = Block 1 (002000-003FFFh) is not code-protected 0 = Block 1 (002000-003FFFh) is code-protected bit 0 CP0: Code Protection bit 1 = Block 0 (000800-001FFFh) is not code-protected 0 = Block 0 (000800-001FFFh) is code-protected Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set. REGISTER 25-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot block (000000-0007FFh) is not code-protected 0 = Boot block (000000-0007FFh) is code-protected bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS39632E-page 299

PIC18F2455/2550/4455/4550 REGISTER 25-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3(1) WRT2 WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 (006000-007FFFh) is not write-protected 0 = Block 3 (006000-007FFFh) is write-protected bit 2 WRT2: Write Protection bit 1 = Block 2 (004000-005FFFh) is not write-protected 0 = Block 2 (004000-005FFFh) is write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 (002000-003FFFh) is not write-protected 0 = Block 1 (002000-003FFFh) is write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 (000800-001FFFh) or (001000-001FFFh) is not write-protected 0 = Block 0 (000800-001FFFh) or (001000-001FFFh) is write-protected Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set. REGISTER 25-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot block (000000-0007FFh) is not write-protected 0 = Boot block (000000-0007FFh) is write-protected bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers (300000-3000FFh) are not write-protected 0 = Configuration registers (300000-3000FFh) are write-protected bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode. DS39632E-page 300 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 REGISTER 25-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3(1) EBTR2 EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks 0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit 1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks 0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks 0 = Block 1 (002000-003FFFh) is protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks 0 = Block 0 (000800-001FFFh) is protected from table reads executed in other blocks Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set. REGISTER 25-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot block (000000-0007FFh) is not protected from table reads executed in other blocks 0 = Boot block (000000-0007FFh) is protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS39632E-page 301

PIC18F2455/2550/4455/4550 REGISTER 25-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2455/2550/4455/4550 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 DEV2:DEV0: Device ID bits For a complete listing, see Register 25-14. bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. REGISTER 25-14: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2455/2550/4455/4550 DEVICES R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-0 DEV10:DEV3: Device ID bits DEV10:DEV3 DEV2:DEV0 Device (DEVID2<7:0>) (DEVID1<7:5>) 0001 0010 011 PIC18F2455 0010 1010 011 PIC18F2458 0001 0010 010 PIC18F2550 0010 1010 010 PIC18F2553 0001 0010 001 PIC18F4455 0010 1010 001 PIC18F4458 0001 0010 000 PIC18F4550 0010 1010 000 PIC18F4553 DS39632E-page 302 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 25.2 Watchdog Timer (WDT) Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts For PIC18F2455/2550/4455/4550 devices, the WDT is when executed. driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal 2: Changing the setting of the IRCF bits WDT period is 4ms and has the same stability as the (OSCCON<6:4>) clears the WDT and INTRC oscillator. postscaler counts. The 4ms period of the WDT is multiplied by a 16-bit 3: When a CLRWDT instruction is executed, postscaler. Any output of the WDT postscaler is the postscaler count will be cleared. selected by a multiplexer, controlled by bits in Configu- ration Register 2H. Available periods range from 4ms 25.2.1 CONTROL REGISTER to 131.072seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events Register25-15 shows the WDTCON register. This is a occur: a SLEEP or CLRWDT instruction is executed, the readable and writable register which contains a control IRCF bits (OSCCON<6:4>) are changed or a clock bit that allows software to override the WDT enable failure has occurred. Configuration bit, but only if the Configuration bit has disabled the WDT. . FIGURE 25-1: WDT BLOCK DIAGRAM SWDTEN Enable WDT INTRC Control WDTEN WDT Counter INTRC Source ÷128 Wake-up from Power-Managed Modes Change on IRCF bits Programmable Postscaler Reset WDT CLRWDT Reset 1:1 to 1:32,768 All Device Resets WDT 4 WDTPS<3:0> SLEEP © 2009 Microchip Technology Inc. DS39632E-page 303

PIC18F2455/2550/4455/4550 REGISTER 25-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled. TABLE 25-2: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page RCON IPEN SBOREN(1) — RI TO PD POR BOR 54 WDTCON — — — — — — — SWDTEN 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer. Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’. DS39632E-page 304 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 25.3 Two-Speed Start-up Reset. For wake-ups from Sleep, the INTOSC or post- scaler clock sources can be selected by setting The Two-Speed Start-up feature helps to minimize the IRCF2:IRCF0 prior to entering Sleep mode. latency period, from oscillator start-up to code execu- In all other power-managed modes, Two-Speed Start-up tion, by allowing the microcontroller to use the INTRC is not used. The device will be clocked by the currently oscillator as a clock source until the primary clock selected clock source until the primary clock source source is available. It is enabled by setting the IESO becomes available. The setting of the IESO bit is Configuration bit. ignored. Two-Speed Start-up should be enabled only if the primary oscillator mode is XT, HS, XTPLL or HSPLL 25.3.1 SPECIAL CONSIDERATIONS FOR (Crystal-Based modes). Other sources do not require USING TWO-SPEED START-UP an OST start-up delay; for these, Two-Speed Start-up While using the INTRC oscillator in Two-Speed Start-up, should be disabled. the device still obeys the normal command sequences When enabled, Resets and wake-ups from Sleep mode for entering power-managed modes, including serial cause the device to configure itself to run from the inter- SLEEP instructions (refer to Section3.1.4 “Multiple nal oscillator block as the clock source, following the Sleep Commands”). In practice, this means that user time-out of the Power-up Timer after a Power-on Reset code can change the SCS1:SCS0 bit settings or issue is enabled. This allows almost immediate code SLEEP instructions before the OST times out. This would execution while the primary oscillator starts and the allow an application to briefly wake-up, perform routine OST is running. Once the OST times out, the device “housekeeping” tasks and return to Sleep before the automatically switches to PRI_RUN mode. device starts to operate from the primary oscillator. Because the OSCCON register is cleared on Reset User code can also check if the primary clock source is events, the INTOSC (or postscaler) clock source is not currently providing the device clocking by checking the initially available after a Reset event; the INTRC clock status of the OSTS bit (OSCCON<3>). If the bit is set, is used directly at its base frequency. To use a higher the primary oscillator is providing the clock. Otherwise, clock speed on wake-up, the INTOSC or postscaler the internal oscillator block is providing the clock during clock sources can be selected to provide a higher clock wake-up from Reset or Sleep mode. speed by setting bits, IRCF2:IRCF0, immediately after FIGURE 25-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake from Interrupt Event OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. © 2009 Microchip Technology Inc. DS39632E-page 305

PIC18F2455/2550/4455/4550 25.4 Fail-Safe Clock Monitor To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide The Fail-Safe Clock Monitor (FSCM) allows the a higher clock speed by setting bits IRCF2:IRCF0 microcontroller to continue operation in the event of an immediately after Reset. For wake-ups from Sleep, the external oscillator failure by automatically switching the INTOSC or postscaler clock sources can be selected device clock to the internal oscillator block. The FSCM by setting IRCF2:IRCF0 prior to entering Sleep mode. function is enabled by setting the FCMEN Configuration The FSCM will detect failures of the primary or second- bit. ary clock sources only. If the internal oscillator block When FSCM is enabled, the INTRC oscillator runs at fails, no failure would be detected, nor would any action all times to monitor clocks to peripherals and provide a be possible. backup clock in the event of a clock failure. Clock monitoring (shown in Figure25-3) is accomplished by 25.4.1 FSCM AND THE WATCHDOG TIMER creating a sample clock signal, which is the INTRC out- Both the FSCM and the WDT are clocked by the put divided by 64. This allows ample time between INTRC oscillator. Since the WDT operates with a FSCM sample clocks for a peripheral clock edge to separate divider and counter, disabling the WDT has occur. The peripheral device clock and the sample no effect on the operation of the INTRC oscillator when clock are presented as inputs to the Clock Monitor latch the FSCM is enabled. (CM). The CM is set on the falling edge of the device clock source, but cleared on the rising edge of the As already noted, the clock source is switched to the sample clock. INTOSC clock when a clock failure is detected. Depending on the frequency selected by the FIGURE 25-3: FSCM BLOCK DIAGRAM IRCF2:IRCF0 bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled Clock Monitor with a small prescale value, a decrease in clock speed Latch (CM) (edge-triggered) allows a WDT time-out to occur and a subsequent Peripheral device Reset. For this reason, Fail-Safe Clock Monitor S Q Clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. INTRC ÷ 64 C Q Source 25.4.2 EXITING FAIL-SAFE OPERATION (32 μs) 488 Hz The fail-safe condition is terminated by either a device (2.048 ms) Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock source Clock specified in Configuration Register 1H (with any Failure start-up delays that are required for the oscillator mode, Detected such as OST or PLL timer). The INTOSC multiplexer provides the device clock until the primary clock source Clock failure is tested for on the falling edge of the becomes ready (similar to a Two-Speed Start-up). The sample clock. If a sample clock falling edge occurs clock source is then switched to the primary clock while CM is still set, a clock failure has been detected (indicated by the OSTS bit in the OSCCON register (Figure25-4). This causes the following: becoming set). The Fail-Safe Clock Monitor then • the FSCM generates an oscillator fail interrupt by resumes monitoring the peripheral clock. setting bit, OSCFIF (PIR2<7>); The primary clock source may never become ready • the device clock source is switched to the internal during start-up. In this case, operation is clocked by the oscillator block (OSCCON is not updated to show INTOSC multiplexer. The OSCCON register will remain the current clock source – this is the fail-safe in its Reset state until a power-managed mode is condition); and entered. • the WDT is reset. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shut- down. See Section3.1.4 “Multiple Sleep Commands” and Section25.3.1 “Special Considerations for Using Two-Speed Start-up” for more details. DS39632E-page 306 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 25-4: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 25.4.3 FSCM INTERRUPTS IN 25.4.4 POR OR WAKE-UP FROM SLEEP POWER-MANAGED MODES The FSCM is designed to detect oscillator failure at any By entering a power-managed mode, the clock point after the device has exited Power-on Reset multiplexer selects the clock source selected by the (POR) or low-power Sleep mode. When the primary OSCCON register. Fail-Safe Clock Monitoring of the device clock is either EC or INTRC, monitoring can power-managed clock source resumes in the begin immediately following these events. power-managed mode. For oscillator modes involving a crystal or resonator If an oscillator failure occurs during power-managed (HS, HSPLL or XT), the situation is somewhat different. operation, the subsequent events depend on whether Since the oscillator may require a start-up time con- or not the oscillator failure interrupt is enabled. If siderably longer than the FCSM sample clock time, a enabled (OSCFIF=1), code execution will be clocked false clock failure may be detected. To prevent this, the by the INTOSC multiplexer. An automatic transition internal oscillator block is automatically configured as back to the failed clock source will not occur. the device clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This If the interrupt is disabled, subsequent interrupts while is identical to Two-Speed Start-up mode. Once the in Idle mode will cause the CPU to begin executing primary clock is stable, the INTRC returns to its role as instructions while being clocked by the INTOSC the FSCM source. source. Note: The same logic that prevents false oscilla- tor failure interrupts on POR or wake from Sleep will also prevent the detection of the oscillator’s failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section25.3.1 “Special Considerations for Using Two-Speed Start-up”, it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power-managed mode is selected, the primary clock is disabled. © 2009 Microchip Technology Inc. DS39632E-page 307

PIC18F2455/2550/4455/4550 25.5 Program Verification and Each of the five blocks has three code protection bits Code Protection associated with them. They are: • Code-Protect bit (CPn) The overall structure of the code protection on the • Write-Protect bit (WRTn) PIC18 Flash devices differs significantly from other PIC® devices. • External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. Figure25-5 shows the program memory organization One of these is a boot block of 2 Kbytes. The remainder for 24 and 32-Kbyte devices and the specific code of the memory is divided into four blocks on binary protection bit associated with each block. The actual boundaries. locations of the bits are summarized in Table25-3. FIGURE 25-5: CODE-PROTECTED PROGRAM MEMORY MEMORY SIZE/DEVICE Block Code Protection Address Controlled By: 24Kbytes 32Kbytes Range 000000h Boot Block Boot Block CPB, WRTB, EBTRB 0007FFh 000800h Block 0 Block 0 CP0, WRT0, EBTR0 001FFFh 002000h Block 1 Block 1 CP1, WRT1, EBTR1 003FFFh 004000h Block 2 Block 2 CP2, WRT2, EBTR2 005FFFh 006000h Unimplemented Block 3 CP3, WRT3, EBTR3 Read ‘0’s 007FFFh 008000h Unimplemented Unimplemented Read ‘0’s Read ‘0’s (Unimplemented Memory Space) 1FFFFFh TABLE 25-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3(1) CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3(1) WRT2 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3(1) EBTR2 EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set. DS39632E-page 308 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 25.5.1 PROGRAM MEMORY A table read instruction that executes from a location CODE PROTECTION outside of that block is not allowed to read and will result in reading ‘0’s. Figures25-6through25-8 The program memory may be read to or written from illustrate table write and table read protection. any location using the table read and table write instructions. The device ID may be read with table Note: Code protection bits may only be written to reads. The Configuration registers may be read and a ‘0’ from a ‘1’ state. It is not possible to written with the table read and table write instructions. write a ‘1’ to a bit in the ‘0’ state. Code protection bits are only set to ‘1’ by a full In normal execution mode, the CPx bits have no direct Chip Erase or Block Erase function. The effect. CPx bits inhibit external reads and writes. A full Chip Erase and Block Erase functions block of user memory may be protected from table can only be initiated via ICSP operation or writes if the WRTx Configuration bit is ‘0’. The EBTRx an external programmer. bits control table reads. For a block of user memory with the EBTRx bit set to ‘0’, a table read instruction that executes from within that block is allowed to read. FIGURE 25-6: TABLE WRITE (WRTx) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 01 PC = 001FFEh TBLWT* 001FFFh 002000h WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 PC = 005FFEh TBLWT* 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table writes disabled to Blockn whenever WRTx = 0. © 2009 Microchip Technology Inc. DS39632E-page 309

PIC18F2455/2550/4455/4550 FIGURE 25-7: EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 001FFFh 002000h WRT1, EBTR1 = 11 PC = 003FFEh TBLRD* 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0. TABLAT register returns a value of ‘0’. FIGURE 25-8: EXTERNAL BLOCK TABLE READ (EBTRx) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh TBLPTR = 0008FFh 000800h WRT0, EBTR0 = 10 PC = 001FFEh TBLRD* 001FFFh 002000h WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: Table reads permitted within Blockn, even when EBTRBx = 0. TABLAT register returns the value of the data at the location TBLPTR. DS39632E-page 310 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 25.5.2 DATA EEPROM To use the In-Circuit Debugger function of the micro- CODE PROTECTION controller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP/RE3, VDD, The entire data EEPROM is protected from external VSS, RB7 and RB6. This will interface to the In-Circuit reads and writes by two bits: CPD and WRTD. CPD Debugger module available from Microchip or one of inhibits external reads and writes of data EEPROM. the third party development tool companies. WRTD inhibits internal and external writes to data EEPROM. The CPU can continue to read and write 25.9 Special ICPORT Features data EEPROM regardless of the protection bit settings. (44-Pin TQFP Package Only) 25.5.3 CONFIGURATION REGISTER Under specific circumstances, the No Connect (NC) PROTECTION pins of devices in 44-pin TQFP packages can provide The Configuration registers can be write-protected. additional functionality. These features are controlled The WRTC bit controls protection of the Configuration by device Configuration bits and are available only in registers. In normal execution mode, the WRTC bit is this package type and pin count. readable only. WRTC can only be written via ICSP operation or an external programmer. 25.9.1 DEDICATED ICD/ICSP PORT The 44-pin TQFP devices can use NC pins to provide 25.6 ID Locations an alternate port for In-Circuit Debugging (ICD) and In-Circuit Serial Programming (ICSP). These pins are Eight memory locations (200000h-200007h) are collectively known as the dedicated ICSP/ICD port, designated as ID locations, where the user can store since they are not shared with any other function of the checksum or other code identification numbers. These device. locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions When implemented, the dedicated port activates three or during program/verify. The ID locations can be read NC pins to provide an alternate device Reset, data and when the device is code-protected. clock ports. None of these ports overlap with standard I/O pins, making the I/O pins available to the user’s 25.7 In-Circuit Serial Programming application. The dedicated ICSP/ICD port is enabled by setting the PIC18F2455/2550/4455/4550 microcontrollers can be ICPRT Configuration bit. The port functions the same serially programmed while in the end application circuit. way as the legacy ICSP/ICD port on RB6/RB7. This is simply done with two lines for clock and data Table25-5 identifies the functionally equivalent pins for and three other lines for power, ground and the ICSP and ICD purposes. programming voltage. This allows customers to manu- facture boards with unprogrammed devices and then TABLE 25-5: EQUIVALENT PINS FOR program the microcontroller just before shipping the LEGACY AND DEDICATED product. This also allows the most recent firmware or a ICD/ICSP™ PORTS custom firmware to be programmed. Pin Name 25.8 In-Circuit Debugger Pin Pin Function Legacy Dedicated Type When the DEBUG Configuration bit is programmed to Port Port a ‘0’, the In-Circuit Debugger functionality is enabled. MCLR/VPP/ NC/ICRST/ P Device Reset and This function allows simple debugging functions when RE3 ICVPP Programming used with MPLAB® IDE. When the microcontroller has Enable this feature enabled, some resources are not available RB6/KBI2/ NC/ICCK/ I Serial Clock for general use. Table25-4 shows which resources are PGC ICPGC required by the background debugger. RB7/KBI3/ NC/ICDT/ I/O Serial Data PGD ICPGD TABLE 25-4: DEBUGGER RESOURCES Legend: I = Input, O = Output, P = Power I/O pins: RB6, RB7 Stack: 2 levels Program Memory: 512 bytes Data Memory: 10 bytes © 2009 Microchip Technology Inc. DS39632E-page 311

PIC18F2455/2550/4455/4550 Even when the dedicated port is enabled, the ICSP Note 1: High-Voltage Programming is always functions remain available through the legacy port. available, regardless of the state of the When VIHH is seen on the MCLR/VPP/RE3 pin, the LVP bit, by applying VIHH to the MCLR pin. state of the ICRST/ICVPP pin is ignored. 2: While in Low-Voltage ICSP Programming Note1: The ICPRT Configuration bit can only be mode, the RB5 pin can no longer be used programmed through the default ICSP as a general purpose I/O pin and should port (MCLR/RB6/RB7). be held low during normal operation. 2: The ICPRT Configuration bit must be 3: When using Low-Voltage ICSP Program- maintained clear for all 28-pin and 40-pin ming (LVP) and the pull-ups on PORTB devices; otherwise, unexpected operation are enabled, bit 5 in the TRISB register may occur. must be cleared to disable the pull-up on RB5 and ensure the proper operation of 25.9.2 28-PIN EMULATION the device. Devices in 44-pin TQFP packages also have the ability 4: If the device Master Clear is disabled, to change their configuration under external control for verify that either of the following is done to debugging purposes. This allows the device to behave ensure proper entry into ICSP mode: as if it were a 28-pin device. a) disable Low-Voltage Programming This 28-pin Configuration mode is controlled through a (CONFIG4L<2> = 0); or single pin, NC/ICPORTS. Connecting this pin to VSS b) make certain that RB5/KBI1/PGM forces the device to function as a 28-pin device. is held low during entry into ICSP. Features normally associated with the 40/44-pin devices are disabled along with their corresponding If Single-Supply ICSP Programming mode will not be control registers and bits. This includes PORTD and used, the LVP bit can be cleared. RB5/KBI1/PGM then PORTE, the SPP and the Enhanced PWM functionality becomes available as the digital I/O pin, RB5. The LVP of CCP1. On the other hand, connecting the pin to VDD bit may be set or cleared only when using standard forces the device to function in its default configuration. high-voltage programming (VIHH applied to the The configuration option is only available when back- MCLR/VPP/RE3 pin). Once LVP has been disabled, ground debugging and the dedicated ICD/ICSP port only the standard high-voltage programming is are both enabled (DEBUG Configuration bit is clear available and must be used to program the device. and ICPRT Configuration bit is set). When disabled, Memory that is not code-protected can be erased using NC/ICPORTS is a No Connect pin. either a Block Erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be 25.10 Single-Supply ICSP Programming erased, a Block Erase is required. If a Block Erase is to be performed when using Low-Voltage Programming, The LVP Configuration bit enables Single-Supply ICSP the device must be supplied with VDD of 4.5V to 5.5V. Programming (formerly known as Low-Voltage ICSP Programming or LVP). When Single-Supply Program- ming is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. While programming using Single-Supply Program- ming, VDD is applied to the MCLR/VPP/RE3 pin as in normal execution mode. To enter Programming mode, VDD is applied to the PGM pin. DS39632E-page 312 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 26.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: PIC18F2455/2550/4455/4550 devices incorporate the • A literal value to be loaded into a file register standard set of 75 PIC18 core instructions, as well as (specified by ‘k’) an extended set of eight new instructions for the optimization of code that is recursive or that utilizes a • The desired FSR register to load the literal value software stack. The extended set is discussed later in into (specified by ‘f’) this section. • No operand required (specified by ‘—’) 26.1 Standard Instruction Set The control instructions may use some of the following operands: The standard PIC18 instruction set adds many enhancements to the previous PIC MCU instruction • A program memory address (specified by ‘n’) sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions PIC MCU instruction sets. Most instructions are a (specified by ‘s’) single program memory word (16 bits) but there are • The mode of the table read and table write four instructions that require two program memory instructions (specified by ‘m’) locations. • No operand required Each single-word instruction is a 16-bit word divided (specified by ‘—’) into an opcode, which specifies the instruction type and All instructions are a single word, except for four one or more operands, which further specify the double-word instructions. These instructions were operation of the instruction. made double-word to contain the required information The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If into four basic categories: this second word is executed as an instruction (by itself), it will execute as a NOP. • Byte-oriented operations • Bit-oriented operations All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the • Literal operations program counter is changed as a result of the instruc- • Control operations tion. In these cases, the execution takes two instruction The PIC18 instruction set summary in Table26-2 lists cycles with the additional instruction cycle(s) executed byte-oriented, bit-oriented, literal and control as a NOP. operations. Table26-1 shows the opcode field The double-word instructions execute in two instruction descriptions. cycles. Most byte-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. 1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4MHz, the normal 2. The destination of the result (specified by ‘d’) instruction execution time is 1μs. If a conditional test is 3. The accessed memory (specified by ‘a’) true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 μs. The file register designator ‘f’ specifies which file Two-word branch instructions (if true) would take 3 μs. register is to be used by the instruction. The destination Figure26-1 shows the general formats that the instruc- designator ‘d’ specifies where the result of the opera- tions can have. All examples use the convention ‘nnh’ tion is to be placed. If ‘d’ is zero, the result is placed in to represent a hexadecimal number. the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction. The instruction set summary, shown in Table26-2, lists the standard instructions recognized by the Microchip All bit-oriented instructions have three operands: MPASMTM Assembler. 1. The file register (specified by ‘f’) Section26.1.1 “Standard Instruction Set” provides 2. The bit in the file register (specified by ‘b’) a description of each instruction. 3. The accessed memory (specified by ‘a’) The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register designator ‘f’ represents the number of the file in which the bit is located. © 2009 Microchip Technology Inc. DS39632E-page 313

PIC18F2455/2550/4455/4550 TABLE 26-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). f 12-bit register file address (000h to FFFh). This is the source address. s f 12-bit register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-Down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a program memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for indirect addressing of register files (source). s z 7-bit offset value for indirect addressing of register files (destination). d { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr. → Assigned to. < > Register bit field. ∈ In the set of. italics User-defined term (font is Courier New). DS39632E-page 314 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC © 2009 Microchip Technology Inc. DS39632E-page 315

PIC18F2455/2550/4455/4550 TABLE 26-2: PIC18FXXXX INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination)2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39632E-page 316 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. © 2009 Microchip Technology Inc. DS39632E-page 317

PIC18F2455/2550/4455/4550 TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move Literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39632E-page 318 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 26.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) + k → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f) → dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: ADDLW 15h Section26.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = 10h Literal Offset Mode” for details. After Instruction Words: 1 W = 25h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). © 2009 Microchip Technology Inc. DS39632E-page 319

PIC18F2455/2550/4455/4550 ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .AND. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) + (f) + (C) → dest Encoding: 0000 1011 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read literal Process Write to W GPR bank (default). ‘k’ Data If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ANDLW 05Fh mode whenever f ≤ 95 (5Fh). See Before Instruction Section26.2.3 “Byte-Oriented and W = A3h Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = 03h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS39632E-page 320 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 d ∈ [0,1] Operation: if Carry bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (W) .AND. (f) → dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ‘1’, then the program Description: The contents of W are ANDed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’ (default). incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC+2+2n. This instruction is then a GPR bank (default). two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section26.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to PC Words: 1 ‘n’ Data Cycles: 1 No No No No operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Decode Read literal Process No ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction W = 17h Before Instruction REG = C2h PC = address (HERE) After Instruction After Instruction W = 02h If Carry = 1; REG = C2h PC = address (HERE + 12) If Carry = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39632E-page 321

PIC18F2455/2550/4455/4550 BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b ≤ 7 Operation: if Negative bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: 0 → f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank (default). incremented to fetch the next If ‘a’ is ‘0’ and the extended instruction instruction, the new address will be set is enabled, this instruction operates PC+2+2n. This instruction is then a in Indexed Literal Offset Addressing two-cycle instruction. mode whenever f ≤ 95 (5Fh). See Words: 1 Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1(2) Literal Offset Mode” for details. Q Cycle Activity: Words: 1 If Jump: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC Q Cycle Activity: ‘n’ Data Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No Before Instruction ‘n’ Data operation FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS39632E-page 322 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39632E-page 323

PIC18F2455/2550/4455/4550 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS39632E-page 324 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 Operation: (PC) + 2 + 2n → PC a ∈ [0,1] Status Affected: None Operation: 1 → f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected. PC+2+2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the two-cycle instruction. GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates Cycles: 2 in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Q1 Q2 Q3 Q4 Bit-Oriented Instructions in Indexed Decode Read literal Process Write to PC Literal Offset Mode” for details. ‘n’ Data Words: 1 No No No No operation operation operation operation Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Example: HERE BRA Jump Decode Read Process Write Before Instruction register ‘f’ Data register ‘f’ PC = address (HERE) After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah © 2009 Microchip Technology Inc. DS39632E-page 325

PIC18F2455/2550/4455/4550 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 0 ≤ b < 7 a ∈ [0,1] a ∈ [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in set is enabled, this instruction operates Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39632E-page 326 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b < 7 Operation: if Overflow bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (f<b>) → f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank (default). instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC+2+2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: PORTC = 0110 0101 [65h] Before Instruction PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39632E-page 327

PIC18F2455/2550/4455/4550 BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: if Zero bit is ‘1’, (PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS, k → PC<20:1>; Status Affected: None if s = 1, Encoding: 1110 0000 nnnn nnnn (W) → WS, Description: If the Zero bit is ‘1’, then the program (STATUS) → STATUSS, will branch. (BSR) → BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will have Encoding: incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk PC+2+2n. This instruction is then a 19 8 two-cycle instruction. Description: Subroutine call of entire 2-Mbyte memory range. First, return address Words: 1 (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, STATUS and Q Cycle Activity: BSR If Jump: registers are also pushed into their respective shadow registers, WS, Q1 Q2 Q3 Q4 STATUSS and BSRS. If ‘s’ = 0, no Decode Read literal Process Write to PC update occurs (default). Then, the ‘n’ Data 20-bit value ‘k’ is loaded into PC<20:1>. No No No No CALL is a two-cycle instruction. operation operation operation operation Words: 2 If No Jump: Cycles: 2 Q1 Q2 Q3 Q4 Decode Read literal Process No Q Cycle Activity: ‘n’ Data operation Q1 Q2 Q3 Q4 Decode Read literal Push PC to Read literal Example: HERE BZ Jump ‘k’<7:0>, stack ‘k’<19:8>, Write to PC Before Instruction No No No No PC = address (HERE) operation operation operation operation After Instruction If Zero = 1; PC = address (Jump) Example: HERE CALL THERE,1 If Zero = 0; PC = address (HERE + 2) Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS = STATUS DS39632E-page 328 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: 000h → WDT, Operation: 000h → f, 000h → WDT postscaler, 1 → Z 1 → TO, 1 → PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the If ‘a’ is ‘1’, the BSR is used to select the postscaler of the WDT. Status bits, TO GPR bank (default). and PD, are set. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1 mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section26.2.3 “Byte-Oriented and Q1 Q2 Q3 Q4 Bit-Oriented Instructions in Indexed Decode No Process No Literal Offset Mode” for details. operation Data operation Words: 1 Cycles: 1 Example: CLRWDT Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 WDT Counter = ? Decode Read Process Write After Instruction register ‘f’ Data register ‘f’ WDT Counter = 00h WDT Postscaler = 0 TO = 1 Example: CLRF FLAG_REG,1 PD = 1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h © 2009 Microchip Technology Inc. DS39632E-page 329

PIC18F2455/2550/4455/4550 COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: (f) → dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank (default). instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank (default). mode whenever f ≤ 95 (5Fh). See If ‘a’ is ‘0’ and the extended instruction Section26.2.3 “Byte-Oriented and set is enabled, this instruction operates Bit-Oriented Instructions in Indexed in Indexed Literal Offset Addressing Literal Offset Mode” for details. mode whenever f ≤ 95 (5Fh). See Words: 1 Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process Write to Note: 3 cycles if skip and followed register ‘f’ Data destination by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h Q1 Q2 Q3 Q4 W = ECh No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL) DS39632E-page 330 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), Operation: (f) – (W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of the W by Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the If the contents of ‘f’ are less than the contents of WREG, then the fetched contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Note: 3 cycles if skip and followed Section26.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process No Cycles: 1(2) register ‘f’ Data operation Note: 3 cycles if skip and followed by a 2-word instruction. If skip: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No Decode Read Process No operation operation operation operation register ‘f’ Data operation If skip and followed by 2-word instruction: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction Example: HERE CPFSGT REG, 0 PC = Address (HERE) W = ? NGREATER : After Instruction GREATER : If REG < W; Before Instruction PC = Address (LESS) PC = Address (HERE) If REG ≥ W; W = ? PC = Address (NLESS) After Instruction If REG > W; PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER) © 2009 Microchip Technology Inc. DS39632E-page 331

PIC18F2455/2550/4455/4550 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: If [W<3:0> > 9] or [DC = 1] then, a ∈ [0,1] (W<3:0>) + 6 → W<3:0>; else, Operation: (f) – 1 → dest (W<3:0>) → W<3:0>; Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then, Encoding: 0000 01da ffff ffff (W<7:4>) + 6 + DC → W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the else, result is stored in W. If ‘d’ is ‘1’, the (W<7:4>) + DC → W<7:4> result is stored back in register ‘f’ Status Affected: C (default). If ‘a’ is ‘0’, the Access Bank is selected. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the Description: DAW adjusts the eight-bit value in W, GPR bank (default). resulting from the earlier addition of two If ‘a’ is ‘0’ and the extended instruction variables (each in packed BCD format) set is enabled, this instruction operates and produces a correct packed BCD in Indexed Literal Offset Addressing result. mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Words: 1 Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write Q Cycle Activity: register W Data W Q1 Q2 Q3 Q4 Example 1: DAW Decode Read Process Write to register ‘f’ Data destination Before Instruction W = A5h C = 0 Example: DECF CNT, 1, 0 DC = 0 Before Instruction After Instruction CNT = 01h W = 05h Z = 0 C = 1 After Instruction DC = 0 CNT = 00h Example 2: Z = 1 Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS39632E-page 332 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, Operation: (f) – 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, If the result is not ‘0’, the next which is already fetched, is discarded instruction, which is already fetched, is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank (default). set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing Section26.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Bit-Oriented Instructions in Indexed Section26.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT ≠ 0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP ≠ 0; PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39632E-page 333

PIC18F2455/2550/4455/4550 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0 ≤ k ≤ 1048575 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k → PC<20:1> a ∈ [0,1] Status Affected: None Operation: (f) + 1 → dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within the entire incremented. If ‘d’ is ‘0’, the result is 2-Mbyte memory range. The 20-bit placed in W. If ‘d’ is ‘1’, the result is value ‘k’ is loaded into PC<20:1>. GOTO placed back in register ‘f’ (default). is always a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Words: 2 GPR bank (default). Cycles: 2 If ‘a’ is ‘0’ and the extended instruction Q Cycle Activity: set is enabled, this instruction operates in Indexed Literal Offset Addressing Q1 Q2 Q3 Q4 mode whenever f ≤ 95 (5Fh). See Decode Read literal No Read literal Section26.2.3 “Byte-Oriented and ‘k’<7:0>, operation ‘k’<19:8>, Bit-Oriented Instructions in Indexed Write to PC Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Example: GOTO THERE Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 PC = Address (THERE) Decode Read Process Write to register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS39632E-page 334 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, Operation: (f) + 1 → dest, skip if result ≠ 0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’. (default) If the result is not ‘0’, the next If the result is ‘0’, the next instruction, instruction, which is already fetched, is which is already fetched, is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG ≠ 0; PC = Address (ZERO) PC = Address (NZERO) If CNT ≠ 0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) © 2009 Microchip Technology Inc. DS39632E-page 335

PIC18F2455/2550/4455/4550 IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) .OR. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) .OR. (f) → dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: IORLW 35h mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = 9Ah Literal Offset Mode” for details. After Instruction W = BFh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS39632E-page 336 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0 ≤ f ≤ 2 Operands: 0 ≤ f ≤ 255 0 ≤ k ≤ 4095 d ∈ [0,1] a ∈ [0,1] Operation: k → FSRf Operation: f → dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to File Select Register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’ (default). Q Cycle Activity: Location ‘f’ can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read literal Process Write If ‘a’ is ‘1’, the BSR is used to select the ‘k’ MSB Data literal ‘k’ MSB GPR bank (default). to FSRfH If ‘a’ is ‘0’ and the extended instruction Decode Read literal Process Write literal ‘k’ set is enabled, this instruction operates ‘k’ LSB Data to FSRfL in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: LFSR 2, 3ABh Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. FSR2H = 03h FSR2L = ABh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write W register ‘f’ Data Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h © 2009 Microchip Technology Inc. DS39632E-page 337

PIC18F2455/2550/4455/4550 MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0 ≤ f ≤ 4095 Operands: 0 ≤ k ≤ 255 s 0 ≤ f ≤ 4095 d Operation: k → BSR Operation: (f ) → f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffff s Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffff d of BSR<7:4> always remains ‘0’ Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Decode Read Process Write literal Either source or destination can be W literal ‘k’ Data ‘k’ to BSR (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a Example: MOVLB 5 peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h The MOVFF instruction cannot use the After Instruction PCL, TOSU, TOSH or TOSL as the BSR Register = 05h destination register. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS39632E-page 338 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: k → W Operation: (W) → f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: MOVLW 5Ah mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 5Ah Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh © 2009 Microchip Technology Inc. DS39632E-page 339

PIC18F2455/2550/4455/4550 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x k → PRODH:PRODL Operation: (W) x (f) → PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried 8-bit literal ‘k’. The 16-bit result is out between the contents of W and the placed in PRODH:PRODL register pair. register file location ‘f’. The 16-bit PRODH contains the high byte. result is stored in the PRODH:PRODL W is unchanged. register pair. PRODH contains the None of the Status flags are affected. high byte. Both W and ‘f’ are Note that neither Overflow nor Carry is unchanged. possible in this operation. A zero result None of the Status flags are affected. is possible but not detected. Note that neither Overflow nor Carry is possible in this operation. A Zero Words: 1 result is possible but not detected. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is Q Cycle Activity: selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write set is enabled, this instruction literal ‘k’ Data registers operates in Indexed Literal Offset PRODH: Addressing mode whenever PRODL f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Example: MULLW 0C4h Instructions in Indexed Literal Offset Mode” for details. Before Instruction W = E2h Words: 1 PRODH = ? Cycles: 1 PRODL = ? After Instruction Q Cycle Activity: W = E2h Q1 Q2 Q3 Q4 PRODH = ADh PRODL = 08h Decode Read Process Write register ‘f’ Data registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS39632E-page 340 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: No operation Operation: (f) + 1 → f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Example: Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] © 2009 Microchip Technology Inc. DS39632E-page 341

PIC18F2455/2550/4455/4550 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Push PC + 2 No No Decode No Pop TOS No onto return operation operation operation value operation stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS39632E-page 342 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n → PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC + 2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC+2+2n. This instruction is a Decode Start No No two-cycle instruction. Reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Flags* = Reset Value Decode Read literal Process Write to PC ‘n’ Data Push PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2) © 2009 Microchip Technology Inc. DS39632E-page 343

PIC18F2455/2550/4455/4550 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, Operation: k → W, 1 → GIE/GIEH or PEIE/GIEL; (TOS) → PC, if s = 1, PCLATU, PCLATH are unchanged (WS) → W, Status Affected: None (STATUSS) → STATUS, (BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers WS, Q1 Q2 Q3 Q4 STATUSS and BSRS are loaded into Decode Read Process Pop PC from their corresponding registers, W, literal ‘k’ Data stack, Write STATUS and BSR. If ‘s’ = 0, no update to W of these registers occurs (default). No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No Pop PC from CALL TABLE ; W contains table operation operation stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS RETLW kn ; End of table W = WS BSR = BSRS STATUS = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn DS39632E-page 344 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (TOS) → PC; a ∈ [0,1] if s = 1, (WS) → W, Operation: (f<n>) → dest<n + 1>, (STATUSS) → STATUS, (f<7>) → C, (BSRS) → BSR, (C) → dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry popped and the top of the stack (TOS) flag. If ‘d’ is ‘0’, the result is placed in is loaded into the program counter. If W. If ‘d’ is ‘1’, the result is stored back ‘s’= 1, the contents of the shadow in register ‘f’ (default). registers WS, STATUSS and BSRS are If ‘a’ is ‘0’, the Access Bank is loaded into their corresponding selected. If ‘a’ is ‘1’, the BSR is used to registers, W, STATUS and BSR. If select the GPR bank (default). ‘s’ = 0, no update of these registers If ‘a’ is ‘0’ and the extended instruction occurs (default). set is enabled, this instruction operates in Indexed Literal Offset Words: 1 Addressing mode whenever Cycles: 2 f ≤ 95 (5Fh). See Section26.2.3 Q Cycle Activity: “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Q1 Q2 Q3 Q4 Mode” for details. Decode No Process Pop PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 © 2009 Microchip Technology Inc. DS39632E-page 345

PIC18F2455/2550/4455/4550 RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n + 1>, Operation: (f<n>) → dest<n – 1>, (f<7>) → dest<0> (f<0>) → C, (C) → dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W. If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘1’, the BSR is used to select the register ‘f’ (default). GPR bank (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the set is enabled, this instruction operates GPR bank (default). in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f ≤ 95 (5Fh). See set is enabled, this instruction operates Section26.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f ≤ 95 (5Fh). See Literal Offset Mode” for details. Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39632E-page 346 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: FFh → f Operation: (f<n>) → dest<n – 1>, Status Affected: None (f<0>) → dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank (default). placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f ≤ 95 (5Fh). See per the BSR value (default). Section26.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 © 2009 Microchip Technology Inc. DS39632E-page 347

PIC18F2455/2550/4455/4550 SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: 00h → WDT, a ∈ [0,1] 0 → WDT postscaler, 1 → TO, Operation: (W) – (f) – (C) → dest 0 → PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored is set. Watchdog Timer and its in W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’ (default). The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is with the oscillator stopped. selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction Q Cycle Activity: operates in Indexed Literal Offset Addressing mode whenever Q1 Q2 Q3 Q4 f ≤ 95 (5Fh). See Section26.2.3 Decode No Process Go to “Byte-Oriented and Bit-Oriented operation Data Sleep Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? Q1 Q2 Q3 Q4 After Instruction TO = 1 † Decode Read Process Write to PD = 0 register ‘f’ Data destination Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39632E-page 348 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k – (W) → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) → dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the Q Cycle Activity: result is stored back in register ‘f’ (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is Decode Read Process Write to W selected. If ‘a’ is ‘1’, the BSR is used literal ‘k’ Data to select the GPR bank (default). Example 1: SUBLW 02h If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction Before Instruction operates in Indexed Literal Offset W = 01h C = ? Addressing mode whenever After Instruction f ≤ 95 (5Fh). See Section26.2.3 W = 01h “Byte-Oriented and Bit-Oriented C = 1 ; result is positive Instructions in Indexed Literal Offset Z = 0 Mode” for details. N = 0 Words: 1 Example 2: SUBLW 02h Cycles: 1 Before Instruction W = 02h Q Cycle Activity: C = ? Q1 Q2 Q3 Q4 After Instruction W = 00h Decode Read Process Write to C = 1 ; result is zero register ‘f’ Data destination Z = 1 N = 0 Example 1: SUBWF REG, 1, 0 Example 3: SUBLW 02h Before Instruction REG = 3 Before Instruction W = 2 W = 03h C = ? C = ? After Instruction After Instruction REG = 1 W = FFh ; (2’s complement) W = 2 C = 0 ; result is negative C = 1 ; result is positive Z = 0 Z = 0 N = 1 N = 0 Example 2: SUBWF REG, 0, 0 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 © 2009 Microchip Technology Inc. DS39632E-page 349

PIC18F2455/2550/4455/4550 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>) → dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored Description: The upper and lower nibbles of register in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is If ‘a’ is ‘0’, the Access Bank is selected. placed in register ‘f’ (default). If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) C = 1 REG = 35h Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39632E-page 350 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR)) → TABLAT, MEMORY (00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR)) → TABLAT, TBLPTR = 00A357h (TBLPTR) + 1 → TBLPTR; Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, Before Instruction (TBLPTR) – 1 → TBLPTR; TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY (01A357h) = 12h (TBLPTR) + 1 → TBLPTR, MEMORY (01A358h) = 34h (Prog Mem (TBLPTR)) → TABLAT After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write Memory) TABLAT) © 2009 Microchip Technology Inc. DS39632E-page 351

PIC18F2455/2550/4455/4550 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT) → Holding Register, TBLPTR = 00A356h HOLDING REGISTER TBLPTR – No Change; (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT) → Holding Register, TABLAT = 55h (TBLPTR) + 1 → TBLPTR; TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT) → Holding Register, (00A356h) = 55h (TBLPTR) – 1 → TBLPTR; Example 2: TBLWT +*; if TBLWT+*, Before Instruction (TBLPTR) + 1 → TBLPTR; TABLAT = 34h (TABLAT) → Holding Register TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of TBLPTR (01389Ah) = FFh to determine which of the HOLDING REGISTER 8 holding registers the TABLAT is written to. (01389Bh) = 34h The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section6.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operation operationoperation operation (Read (Write to TABLAT) Holding Register) DS39632E-page 352 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 a ∈ [0,1] Operation: (W) .XOR. k → W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, making this a two-cycle instruction. Words: 1 If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Q1 Q2 Q3 Q4 set is enabled, this instruction operates Decode Read Process Write to W in Indexed Literal Offset Addressing literal ‘k’ Data mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Example: XORLW 0AFh Literal Offset Mode” for details. Before Instruction Words: 1 W = B5h After Instruction Cycles: 1(2) W = 1Ah Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT ≠ 00h, PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39632E-page 353

PIC18F2455/2550/4455/4550 XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS39632E-page 354 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 26.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table26-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section26.2.2 “Extended Instruction instruction set, PIC18F2455/2550/4455/4550 devices Set”. The opcode field descriptions in Table26-1 also provide an optional extension to the core CPU (page314) apply to both the standard and extended functionality. The added features include eight addi- PIC18 instruction sets. tional instructions that augment Indirect and Indexed Addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing mode for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction set these instructions directly in assembler. are disabled by default. To enable them, users must set The syntax for these commands is pro- the XINST Configuration bit. vided as a reference for users who may be The instructions in the extended set can all be reviewing code that has been generated classified as literal operations, which either manipulate by a compiler. the File Select Registers, or use them for Indexed Addressing. Two of the instructions, ADDFSR and 26.2.1 EXTENDED INSTRUCTION SYNTAX SUBFSR, each have an additional special instantiation Most of the extended instructions use indexed for using FSR2. These versions (ADDULNK and arguments, using one of the File Select Registers and SUBULNK) allow for automatic return after execution. some offset to specify a source or destination register. The extended instructions are specifically implemented When an argument for an instruction serves as part of to optimize re-entrant program code (that is, code that Indexed Addressing, it is enclosed in square brackets is recursive or that uses a software stack) written in (“[ ]”). This is done to indicate that the argument is used high-level languages, particularly C. Among other as an index or offset. The MPASM™ Assembler will things, they allow users working in high-level flag an error if it determines that an index or offset value languages to perform certain operations on data is not bracketed. structures more efficiently. These include: When the extended instruction set is enabled, brackets • Dynamic allocation and deallocation of software are also used to indicate index arguments in byte- stack space when entering and leaving oriented and bit-oriented instructions. This is in addition subroutines to other changes in their syntax. For more details, see • Function Pointer invocation Section26.2.3.1 “Extended Instruction Syntax with Standard PIC18 Commands”. • Software Stack Pointer manipulation • Manipulation of variables located in a software Note: In the past, square brackets have been stack used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 26-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None Decrement FSR2 SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None Return © 2009 Microchip Technology Inc. DS39632E-page 355

PIC18F2455/2550/4455/4550 26.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2, Operation: FSR(f) + k → FSR(f) (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during Q1 Q2 Q3 Q4 the second cycle. Decode Read Process Write to This may be thought of as a special literal ‘k’ Data FSR case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Example: ADDFSR 2, 23h Words: 1 Before Instruction Cycles: 2 FSR2 = 03FFh Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 FSR2 = 0422h Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s). DS39632E-page 356 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0 ≤ z ≤ 127 s 0 ≤ f ≤ 4095 Operation: (PC + 2) → TOS, d (W) → PCL, Operation: ((FSR2) + z ) → f s d (PCLATH) → PCH, Status Affected: None (PCLATU) → PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffff d Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’ in the first word to the value of s latched into PCH and PCU, FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘fd’ in the second word. Both addresses new next instruction is fetched. can be anywhere in the 4096-byte data Unlike CALL, there is no option to space (000h to FFFh). update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an indirect addressing register, the value returned will be 00h. Q1 Q2 Q3 Q4 Decode Read Push PC to No Words: 2 WREG stack operation Cycles: 2 No No No No Q Cycle Activity: operation operation operation operation Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Decode No No Write Before Instruction operation operation register ‘f’ PC = address (HERE) PCLATH = 10h No dummy (dest) PCLATU = 00h read W = 06h After Instruction PC = 001006h Example: MOVSF [05h], REG2 TOS = address (HERE + 2) PCLATH = 10h Before Instruction PCLATU = 00h FSR2 = 80h W = 06h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h © 2009 Microchip Technology Inc. DS39632E-page 357

PIC18F2455/2550/4455/4550 MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255 0 ≤ z ≤ 127 d Operation: k → (FSR2), Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1→ FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1110 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. FSR2 Description The contents of the source register are is decremented by ‘1’ after the operation. moved to the destination register. The This instruction allows users to push values addresses of the source and destination onto a software stack. registers are determined by adding the 7-bit literal offsets ‘z ’ or ‘z ’, Words: 1 s d respectively, to the value of FSR2. Both Cycles: 1 registers can be located anywhere in the 4096-byte data memory space Q Cycle Activity: (000h to FFFh). Q1 Q2 Q3 Q4 The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to PCL, TOSU, TOSH or TOSL as the data destination destination register. If the resultant source address points to an indirect addressing register, the Example: PUSHL 08h value returned will be 00h. If the Before Instruction resultant destination address points to FSR2H:FSR2L = 01ECh an indirect addressing register, the Memory (01ECh) = 00h instruction will execute as a NOP. Words: 2 After Instruction FSR2H:FSR2L = 01EBh Cycles: 2 Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS39632E-page 358 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2, Operation: FSRf – k → FSRf (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified by contents of the FSR2. A RETURN is then ‘f’. executed by loading the PC with the TOS. Words: 1 The instruction takes two cycles to execute; a NOP is performed during the Cycles: 1 second cycle. Q Cycle Activity: This may be thought of as a special case of Q1 Q2 Q3 Q4 the SUBFSR instruction, where f = 3 (binary Decode Read Process Write to ‘11’); it operates only on FSR2. register ‘f’ Data destination Words: 1 Cycles: 2 Q Cycle Activity: Example: SUBFSR 2, 23h Q1 Q2 Q3 Q4 Before Instruction FSR2 = 03FFh Decode Read Process Write to register ‘f’ Data destination After Instruction FSR2 = 03DCh No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) © 2009 Microchip Technology Inc. DS39632E-page 359

PIC18F2455/2550/4455/4550 26.2.3 BYTE-ORIENTED AND 26.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file Note: Enabling the PIC18 instruction set register argument, ‘f’, in the standard byte-oriented and extension may cause legacy applications bit-oriented commands is replaced with the literal offset to behave erratically or fail entirely. value, ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing mode (Section5.6.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within brackets, will generate an the standard PIC18 instruction set are interpreted. error in the MPASM Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing mode, the Access RAM either as a location in the Access Bank (‘a’ = 0) or in a argument is never specified; it will automatically be GPR bank designated by the BSR (‘a’ = 1). When the assumed to be ‘0’. This is in contrast to standard extended instruction set is enabled and ‘a’ = 0, operation (extended instruction set disabled) when ‘a’ however, a file register argument of 5Fh or less is is set on the basis of the target address. Declaring the interpreted as an offset from the pointer value in FSR2 Access RAM bit in this mode will also generate an error and not as a literal address. For practical purposes, this in the MPASM Assembler. means that all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bit- The destination argument, ‘d’, functions as before. oriented instructions, or almost half of the core PIC18 In the latest versions of the MPASM assembler, instructions – may behave differently when the language support for the extended instruction set must extended instruction set is enabled. be explicitly invoked. This is done with either the When the content of FSR2 is 00h, the boundaries of the command line option, /y, or the PE directive in the Access RAM are essentially remapped to their original source listing. values. This may be useful in creating backward 26.2.4 CONSIDERATIONS WHEN compatible code. If this technique is used, it may be ENABLING THE EXTENDED necessary to save the value of FSR2 and restore it INSTRUCTION SET when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users It is important to note that the extensions to the instruc- must also keep in mind the syntax requirements of the tion set may not be beneficial to all users. In particular, extended instruction set (see Section26.2.3.1 users who are not writing code that uses a software “Extended Instruction Syntax with Standard PIC18 stack may not benefit from using the extensions to the Commands”). instruction set. Although the Indexed Literal Offset Addressing mode Additionally, the Indexed Literal Offset Addressing can be very useful for dynamic stack and pointer mode may create issues with legacy applications manipulation, it can also be very annoying if a simple written to the PIC18 assembler. This is because arithmetic operation is carried out on the wrong instructions in the legacy code may attempt to address register. Users who are accustomed to the PIC18 registers in the Access Bank below 5Fh. Since these programming must keep in mind that, when the addresses are interpreted as literal offsets to FSR2 extended instruction set is enabled, register addresses when the instruction set extension is enabled, the of 5Fh or less are used for Indexed Literal Offset application may read or write to the wrong data Addressing. addresses. Representative examples of typical byte-oriented and When porting an application to the PIC18F2455/2550/ bit-oriented instructions in the Indexed Literal Offset 4455/4550, it is very important to consider the type of Addressing mode are provided on the following page to code. A large, re-entrant application that is written in ‘C’ show how execution is affected. The operand and would benefit from efficient compilation will do well conditions shown in the examples are applicable to all when using the instruction set extensions. Legacy instructions of these types. applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39632E-page 360 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 Operands: 0 ≤ f ≤ 95 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in Cycles: 1 register ‘f’ (default). Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Example: ADDWF [OFST],0 Contents of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction W = 37h Contents Set Indexed of 0A2Ch = 20h SETF (Indexed Literal Offset mode) Syntax: SETF [k] Operands: 0 ≤ k ≤ 95 Operation: FFh → ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh © 2009 Microchip Technology Inc. DS39632E-page 361

PIC18F2455/2550/4455/4550 26.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set of the PIC18F2455/2550/4455/4550 family of • A menu option, or dialog box within the devices. This includes the MPLAB C18 C compiler, environment, that allows the user to configure the MPASM Assembly language and MPLAB Integrated language tool and its settings for the project Development Environment (IDE). • A command line option When selecting a target device for software • A directive in the source code development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for These options vary between different compilers, the XINST Configuration bit is ‘0’, disabling the assemblers and development environments. Users are extended instruction set and Indexed Literal Offset encouraged to review the documentation accompany- Addressing mode. For proper execution of applications ing their development systems for the appropriate developed to take advantage of the extended information. instruction set, XINST must be set during programming. DS39632E-page 362 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 27.0 DEVELOPMENT SUPPORT 27.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- • Integrated Development Environment controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software operating system-based application that contains: • Assemblers/Compilers/Linkers • A single graphical interface to all debugging tools - MPASMTM Assembler - Simulator - MPLAB C18 and MPLAB C30 C Compilers - Programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) • Simulators • A full-featured editor with color-coded context - MPLAB SIM Software Simulator • A multiple project manager • Emulators • Customizable data windows with direct edit of contents - MPLAB ICE 2000 In-Circuit Emulator • High-level source code debugging - MPLAB REAL ICE™ In-Circuit Emulator • Visual device initializer for easy register • In-Circuit Debugger initialization - MPLAB ICD 2 • Mouse over variable inspection • Device Programmers • Drag and drop variables from source to watch - PICSTART® Plus Development Programmer windows - MPLAB PM3 Device Programmer • Extensive on-line help - PICkit™ 2 Development Programmer • Integration of select third party tools, such as • Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR Boards and Evaluation Kits C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2009 Microchip Technology Inc. DS39632E-page 363

PIC18F2455/2550/4455/4550 27.2 MPASM Assembler 27.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: • Support for the entire dsPIC30F instruction set • Integration into MPLAB IDE projects • Support for fixed-point and floating-point data • User-defined macros to streamline • Command line interface assembly code • Rich directive set • Conditional assembly for multi-purpose source files • Flexible macro language • Directives that allow complete control over the • MPLAB IDE compatibility assembly process 27.6 MPLAB SIM Software Simulator 27.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulat- ing the PIC MCUs and dsPIC® DSCs on an instruction The MPLAB C18 and MPLAB C30 Code Development level. On any given instruction, the data areas can be Systems are complete ANSI C compilers for examined or modified and stimuli can be applied from Microchip’s PIC18 and PIC24 families of microcon- a comprehensive stimulus controller. Registers can be trollers and the dsPIC30 and dsPIC33 family of digital logged to files for further run-time analysis. The trace signal controllers. These compilers provide powerful buffer and logic analyzer display extend the power of integration capabilities, superior code optimization and the simulator to record and track program execution, ease of use not found with other compilers. actions on I/O, most peripherals and internal registers. For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and debugger. MPLAB C30 CCompilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator 27.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside MPLIB Object Librarian of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS39632E-page 364 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 27.7 MPLAB ICE 2000 27.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes microcontrollers. Software control of the MPLAB ICE the in-circuit debugging capability built into theFlash 2000 In-Circuit Emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers cost- editing, building, downloading and source debugging effective, in-circuit Flash debugging from the graphical from a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step- ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB ICE 2000 In-Circuit Emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 27.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for simple, unified application. maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various 27.8 MPLAB REAL ICE In-Circuit package types. The ICSP™ cable assembly is included Emulator System as a standard item. In Stand-Alone mode, the MPLAB MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set Microchip Flash DSC and MCU devices. It debugs and code protection in this mode. The MPLAB PM3 programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable. with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large included with each kit. memory devices and incorporates an SD/MMC card for file storage and secure data applications. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, Low- Voltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2009 Microchip Technology Inc. DS39632E-page 365

PIC18F2455/2550/4455/4550 27.11 PICSTART Plus Development 27.13 Demonstration, Development and Programmer Evaluation Boards The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func- Integrated Development Environment software makes tional systems. Most boards include prototyping areas for using the programmer simple and efficient. The adding custom circuitry and provide application firmware PICSTART Plus Development Programmer supports and source code for examination and modification. most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs, Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232 PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional The PICSTART Plus Development Programmer is CE EEPROM memory. compliant. The demonstration and development boards can be used in teaching environments, for prototyping custom 27.12 PICkit 2 Development Programmer circuits and for learning about various microcontroller The PICkit™ 2 Development Programmer is a low-cost applications. programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ demon- an easy-to-use interface for programming many of stration/development board series of circuits, Microchip Microchip’s baseline, mid-range and PIC18F families of has a line of evaluation kits and demonstration software Flash memory microcontrollers. The PICkit 2 Starter Kit for analog filter design, KEELOQ® security ICs, CAN, includes a prototyping development board, twelve IrDA®, PowerSmart battery management, SEEVAL® sequential lessons, software and HI-TECH’s PICC™ evaluation system, Sigma-Delta ADC, flow rate Lite C compiler, and is designed to help get up to speed sensing, plus many more. quickly using PIC® microcontrollers. The kit provides Check the Microchip web page (www.microchip.com) everything needed to program, evaluate and develop for the complete list of demonstration, development applications using Microchip’s powerful, mid-range and evaluation kits. Flash memory family of microcontrollers. DS39632E-page 366 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 28.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias...............................................................................................................-40°C to +85°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) (Note 3).....................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk by all ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/ RE3 pin, rather than pulling this pin directly to VSS. 3: When the internal USB regulator is enabled or VUSB is powered externally, RC4 and RC5 are limited to -0.3V to (VUSB + 0.3V) with respect to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS39632E-page 367

PIC18F2455/2550/4455/4550 FIGURE 28-1: PIC18F2455/2550/4455/4550 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 48 MHz Frequency FIGURE 28-2: PIC18LF2455/2550/4455/4550 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL LOW VOLTAGE) 6.0V 5.5V 5.0V 4.5V 4.2V 4.0V e g 3.5V a lt 3.0V o V 2.5V 2.0V 4 MHz 40 MHz 48 MHz Frequency Note1: VDDAPPMIN is the minimum voltage of the PIC® device in the application. 2: For 2.0 < VDD < 4.2 V, FMAX = (16.36MHz/V) (VDDAPPMIN - 2.0V) + 4MHz 3: For VDD ≥ 4.2 V, FMAX = 48MHz. DS39632E-page 368 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 28.1 DC Characteristics: Supply Voltage PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage 2.0(2) — 5.5 V EC, HS, XT and Internal Oscillator modes 3.0(2) — 5.5 V HSPLL, XTPLL, ECPIO and ECPLL Oscillator modes D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See Section4.3 “Power-on Reset (POR)” to Ensure Internal Power-on for details Reset Signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section4.3 “Power-on Reset (POR)” to Ensure Internal Power-on for details Reset Signal D005 VBOR Brown-out Reset Voltage BORV1:BORV0 = 11 2.00 2.05 2.16 V BORV1:BORV0 = 10 2.65 2.79 2.93 V BORV1:BORV0 = 01 4.11 4.33 4.55 V BORV1:BORV0 = 00 4.36 4.59 4.82 V Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: The stated minimums apply for the PIC18LF products in this device family. PIC18F products in this device family are rated for 4.2V minimum in all oscillator modes. © 2009 Microchip Technology Inc. DS39632E-page 369

PIC18F2455/2550/4455/4550 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) PIC18LFX455/X550 0.1 0.95 μA -40°C VDD = 2.0V 0.1 1.0 μA +25°C (Sleep mode) 0.2 5 μA +85°C PIC18LFX455/X550 0.1 1.4 μA -40°C VDD = 3.0V 0.1 2 μA +25°C (Sleep mode) 0.3 8 μA +85°C All devices 0.1 1.9 μA -40°C VDD = 5.0V 0.1 2.0 μA +25°C (Sleep mode) 0.4 15 μA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39632E-page 370 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) (Continued) PIC18LF2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LFX455/X550 15 32 μA -40°C 15 30 μA +25°C VDD = 2.0V 15 29 μA +85°C PIC18LFX455/X550 40 63 μA -40°C FOSC = 31kHz 35 60 μA +25°C VDD = 3.0V (RC_RUN mode, 30 57 μA +85°C INTRC source) All devices 105 168 μA -40°C 90 160 μA +25°C VDD = 5.0V 80 152 μA +85°C PIC18LFX455/X550 0.33 1 mA -40°C 0.33 1 mA +25°C VDD = 2.0V 0.33 1 mA +85°C PIC18LFX455/X550 0.6 1.3 mA -40°C FOSC = 1MHz 0.6 1.2 mA +25°C VDD = 3.0V (RC_RUN mode, 0.6 1.1 mA +85°C INTOSC source) All devices 1.1 2.3 mA -40°C 1.1 2.2 mA +25°C VDD = 5.0V 1.0 2.1 mA +85°C PIC18LFX455/X550 0.8 2.1 mA -40°C 0.8 2.0 mA +25°C VDD = 2.0V 0.8 1.9 mA +85°C PIC18LFX455/X550 1.3 3.0 mA -40°C FOSC = 4MHz 1.3 3.0 mA +25°C VDD = 3.0V (RC_RUN mode, 1.3 3.0 mA +85°C INTOSC source) All devices 2.5 5.3 mA -40°C 2.5 5.0 mA +25°C VDD = 5.0V 2.5 4.8 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2009 Microchip Technology Inc. DS39632E-page 371

PIC18F2455/2550/4455/4550 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) (Continued) PIC18LF2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LFX455/X550 2.9 8 μA -40°C 3.1 8 μA +25°C VDD = 2.0V 3.6 11 μA +85°C PIC18LFX455/X550 4.5 11 μA -40°C FOSC = 31kHz 4.8 11 μA +25°C VDD = 3.0V (RC_IDLE mode, 5.8 15 μA +85°C INTRC source) All devices 9.2 16 μA -40°C 9.8 16 μA +25°C VDD = 5.0V 11.4 36 μA +85°C PIC18LFX455/X550 165 350 μA -40°C 175 350 μA +25°C VDD = 2.0V 190 350 μA +85°C PIC18LFX455/X550 250 500 μA -40°C FOSC = 1MHz 270 500 μA +25°C VDD = 3.0V (RC_IDLE mode, 290 500 μA +85°C INTOSC source) All devices 0.50 1 mA -40°C 0.52 1 mA +25°C VDD = 5.0V 0.55 1 mA +85°C PIC18LFX455/X550 340 500 μA -40°C 350 500 μA +25°C VDD = 2.0V 360 500 μA +85°C PIC18LFX455/X550 520 900 μA -40°C FOSC = 4MHz 540 900 μA +25°C VDD = 3.0V (RC_IDLE mode, 580 900 μA +85°C INTOSC source) All devices 1.0 1.6 mA -40°C 1.1 1.5 mA +25°C VDD = 5.0V 1.1 1.4 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39632E-page 372 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) (Continued) PIC18LF2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LFX455/X550 250 500 μA -40°C 250 500 μA +25°C VDD = 2.0V 250 500 μA +85°C PIC18LFX455/X550 550 650 μA -40°C FOSC = 1MHZ 480 650 μA +25°C VDD = 3.0V (PRI_RUN, EC oscillator) 460 650 μA +85°C All devices 1.2 1.6 mA -40°C 1.1 1.5 mA +25°C VDD = 5.0V 1.0 1.4 mA +85°C PIC18LFX455/X550 0.74 2.0 mA -40°C 0.74 2.0 mA +25°C VDD = 2.0V 0.74 2.0 mA +85°C PIC18LFX455/X550 1.3 3.0 mA -40°C FOSC = 4MHz 1.3 3.0 mA +25°C VDD = 3.0V (PRI_RUN, EC oscillator) 1.3 3.0 mA +85°C All devices 2.7 6.0 mA -40°C 2.6 6.0 mA +25°C VDD = 5.0V 2.5 6.0 mA +85°C All devices 15 35 mA -40°C 16 35 mA +25°C VDD = 4.2V 16 35 mA +85°C FOSC = 40MHZ (PRI_RUN, All devices 21 40 mA -40°C EC oscillator) 21 40 mA +25°C VDD = 5.0V 21 40 mA +85°C All devices 20 40 mA -40°C 20 40 mA +25°C VDD = 4.2V 20 40 mA +85°C FOSC = 48MHZ (PRI_RUN, All devices 25 50 mA -40°C EC oscillator) 25 50 mA +25°C VDD = 5.0V 25 50 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2009 Microchip Technology Inc. DS39632E-page 373

PIC18F2455/2550/4455/4550 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) (Continued) PIC18LF2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LFX455/X550 65 130 μA -40°C 65 120 μA +25°C VDD = 2.0V 70 115 μA +85°C PIC18LFX455/X550 120 270 μA -40°C FOSC = 1MHz 120 250 μA +25°C VDD = 3.0V (PRI_IDLE mode, 130 240 μA +85°C EC oscillator) All devices 230 480 μA -40°C 240 450 μA +25°C VDD = 5.0V 250 430 μA +85°C PIC18LFX455/X550 255 475 μA -40°C 260 450 μA +25°C VDD = 2.0V 270 430 μA +85°C PIC18LFX455/X550 420 900 μA -40°C FOSC = 4MHz 430 850 μA +25°C VDD = 3.0V (PRI_IDLE mode, 450 810 μA +85°C EC oscillator) All devices 0.9 1.5 mA -40°C 0.9 1.4 mA +25°C VDD = 5.0V 0.9 1.3 mA +85°C All devices 6.0 16 mA -40°C 6.2 16 mA +25°C VDD = 4.2V 6.6 16 mA +85°C FOSC = 40MHz (PRI_IDLE mode, All devices 8.1 18 mA -40°C EC oscillator) 8.3 18 mA +25°C VDD = 5.0V 9.0 18 mA +85°C All devices 8.0 18 mA -40°C 8.1 18 mA +25°C VDD = 4.2V 8.2 18 mA +85°C FOSC = 48MHz (PRI_IDLE mode, All devices 9.8 21 mA -40°C EC oscillator) 10.0 21 mA +25°C VDD = 5.0V 10.5 21 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39632E-page 374 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) (Continued) PIC18LF2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LFX455/X550 14 40 μA -40°C 15 40 μA +25°C VDD = 2.0V 16 40 μA +85°C PIC18LFX455/X550 40 74 μA -40°C FOSC = 32kHz(3) 35 70 μA +25°C VDD = 3.0V (SEC_RUN mode, 31 67 μA +85°C Timer1 as clock) All devices 99 150 μA -40°C 81 150 μA +25°C VDD = 5.0V 75 150 μA +85°C PIC18LFX455/X550 2.5 12 μA -40°C 3.7 12 μA +25°C VDD = 2.0V 4.5 12 μA +85°C PIC18LFX455/X550 5.0 15 μA -40°C FOSC = 32kHz(3) 5.4 15 μA +25°C VDD = 3.0V (SEC_IDLE mode, 6.3 15 μA +85°C Timer1 as clock) All devices 8.5 25 μA -40°C 9.0 25 μA +25°C VDD = 5.0V 10.5 36 μA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2009 Microchip Technology Inc. DS39632E-page 375

PIC18F2455/2550/4455/4550 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) (Continued) PIC18LF2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Device Typ Max Units Conditions No. Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD) D022 ΔIWDT Watchdog Timer 1.3 3.8 μA -40°C 1.4 3.8 μA +25°C VDD = 2.0V 2.0 3.8 μA +85°C 1.9 4.6 μA -40°C 2.0 4.6 μA +25°C VDD = 3.0V 2.8 4.6 μA +85°C 4.0 10 μA -40°C 5.5 10 μA +25°C VDD = 5.0V 5.6 10 μA +85°C D022A ΔIBOR Brown-out Reset(4) 35 40 μA -40°C to +85°C VDD = 3.0V 40 45 μA -40°C to +85°C VDD = 5.0V Sleep mode, 0.1 2 μA -40°C to +85°C BOREN1:BOREN0 = 10 D022B ΔILVD High/Low-Voltage 22 38 μA -40°C to +85°C VDD = 2.0V Detect(4) 25 40 μA -40°C to +85°C VDD = 3.0V 29 45 μA -40°C to +85°C VDD = 5.0V D025 ΔIOSCB Timer1 Oscillator 2.1 4.5 μA -40°C 1.8 4.5 μA +25°C VDD = 2.0V 32kHz on Timer1(3) 2.1 4.5 μA +85°C 2.2 6.0 μA -40°C 2.6 6.0 μA +25°C VDD = 3.0V 32kHz on Timer1(3) 2.9 6.0 μA +85°C 3.0 8.0 μA -40°C 3.2 8.0 μA +25°C VDD = 5.0V 32kHz on Timer1(3) 3.4 8.0 μA +85°C D026 ΔIAD A/D Converter 1.0 2.0 μA -40°C to +85°C VDD = 2.0V 1.0 2.0 μA -40°C to +85°C VDD = 3.0V A/D on, not converting 1.0 2.0 μA -40°C to +85°C VDD = 5.0V Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39632E-page 376 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) (Continued) PIC18LF2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Device Typ Max Units Conditions No. USB and Related Module Differential Currents (ΔIUSBx, ΔIPLL, ΔIUREG) ΔIUSBx USB Module 8 14.5 mA +25°C VDD = 3.0V with On-Chip Transceiver 12.4 20 mA +25°C VDD = 5.0V ΔIPLL 96MHz PLL 1.2 3.0 mA +25°C VDD = 3.0V (Oscillator Module) 1.2 4.8 mA +25°C VDD = 5.0V ΔIUREG USB Internal Voltage 80 125 μA +25°C VDD = 5.0V USB Idle, SUSPND Regulator (UCON<1>=1) Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2009 Microchip Technology Inc. DS39632E-page 377

PIC18F2455/2550/4455/4550 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) (Continued) PIC18LF2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Device Typ Max Units Conditions No. ITUSB Total USB Run Currents (ITUSB)(2) Primary Run with USB 29 75 mA -40°C VDD = 5.0V EC+PLL 4 MHz input, Module, PLL and USB 29 65 mA +25°C VDD = 5.0V 48 MHz PRI_RUN, Voltage Regulator USB module enabled in 29 65 mA +85°C VDD = 5.0V Full-Speed mode, USB VREG enabled, no bus traffic Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39632E-page 378 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 28.3 DC Characteristics: PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage I/O Ports (except RC4/RC5 in USB mode): D030 with TTL Buffer VSS 0.15 VDD V VDD < 4.5V D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger Buffer VSS 0.2 VDD V RB0 and RB1 VSS 0.3 VDD V When in I2C™ mode D032 MCLR VSS 0.2 VDD V D032A OSC1 and T1OSI VSS 0.3 VDD V XT, HS, HSPLL modes(1) D033 OSC1 VSS 0.2 VDD V EC mode(1) VIH Input High Voltage I/O Ports (except RC4/RC5 in USB mode): D040 with TTL Buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V D041 with Schmitt Trigger Buffer 0.8 VDD VDD V RB0 and RB1 0.7 VDD VDD V When in I2C mode D042 MCLR 0.8 VDD VDD V D042A OSC1 and T1OSI 0.7 VDD VDD V XT, HS, HSPLL modes(1) D043 OSC1 0.8 VDD VDD V EC mode(1) IIL Input Leakage Current(2) D060 I/O Ports, except D+ and D- — ±200 nA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR — ±1 μA Vss ≤ VPIN ≤ VDD D063 OSC1 — ±1 μA Vss ≤ VPIN ≤ VDD IPU Weak Pull-up Current D070 IPURB PORTB Weak Pull-up Current 50 400 μA VDD = 5V, VPIN = VSS D071 IPURD PORTD Weak Pull-up Current 50 400 μA VDD = 5V, VPIN = VSS Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2: Negative current is defined as current sourced by the pin. 3: Parameter is characterized but not tested. © 2009 Microchip Technology Inc. DS39632E-page 379

PIC18F2455/2550/4455/4550 28.3 DC Characteristics: PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O Ports (except RC4/RC5 in — 0.6 V IOL = 8.5 mA, VDD = 4.5V, USB mode) -40°C to +85°C D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (EC, ECIO modes) -40°C to +85°C VOH Output High Voltage(3) D090 I/O Ports (except RC4/RC5 in VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, USB mode) -40°C to +85°C D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, (EC, ECIO, ECPIO modes) -40°C to +85°C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 Pin — 15 pF In XT and HS modes when external clock is used to drive OSC1 D101 CIO All I/O Pins and OSC2 — 50 pF To meet the AC Timing (in RC mode) Specifications D102 CB SCL, SDA — 400 pF I2C™ Specification Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2: Negative current is defined as current sourced by the pin. 3: Parameter is characterized but not tested. DS39632E-page 380 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC Characteristics Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym Characteristic Min Typ† Max Units Conditions No. Internal Program Memory Programming Specifications(1) D110 VIHH Voltage on MCLR/VPP/RE3 pin 9.00 — 13.25 V (Note 3) D113 IDDP Supply Current during — — 10 mA Programming Data EEPROM Memory D120 ED Byte Endurance 100K 1M — E/W -40°C to +85°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +85°C Cycles before Refresh(2) Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Bulk Erase 3.2(4) — 5.5 V Using ICSP™ port only D132A VIW VDD for All Erase/Write VMIN — 5.5 V Using ICSP port or Operations (except bulk erase) self-erase/write D133A TIW Self-Timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section7.7 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if Single-Supply Programming is disabled. 4: Minimum voltage is 3.2V for PIC18LF devices in the family. Minimum voltage is 4.2V for PIC18F devices in the family. © 2009 Microchip Technology Inc. DS39632E-page 381

PIC18F2455/2550/4455/4550 TABLE 28-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB 300 TRESP Response Time(1) — 150 400 ns PIC18FXXXX 300A — 150 600 ns PIC18LFXXXX, VDD = 2.0V 301 TMC2OV Comparator Mode Change to — — 10 μs Output Valid Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 28-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — 1/4 1 LSb Low Range (CVRR = 1) — — 1/2 LSb High Range (CVRR = 0) D312 VRUR Unit Resistor Value (R) — 2k — Ω 310 TSET Settling Time(1) — — 10 μs Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. DS39632E-page 382 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 28-4: USB MODULE SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated). Param Sym Characteristic Min Typ Max Units Comments No. D313 VUSB USB Voltage 3.0 — 3.6 V Voltage on pin must be in this range for proper USB operation D314 IIL Input Leakage on D+ and D- — — ±1 μA VSS ≤ VPIN ≤ VDD; pins pin at high-impedance D315 VILUSB Input Low Voltage for USB — — 0.8 V For VUSB range Buffer D316 VIHUSB Input High Voltage for USB 2.0 — — V For VUSB range Buffer D317 VCRS Crossover Voltage 1.3 2.0 V Voltage range for D+ and D- crossover to occur D318 VDIFS Differential Input Sensitivity — — 0.2 V The difference between D+ and D- must exceed this value while VCM is met D319 VCM Differential Common Mode 0.8 — 2.5 V Range D320 ZOUT Driver Output Impedance 28 — 44 Ω D321 VOL Voltage Output Low 0.0 — 0.3 V 1.5kΩ load connected to 3.6V D322 VOH Voltage Output High 2.8 — 3.6 V 15kΩ load connected to ground TABLE 28-5: USB INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated). Param Sym Characteristics Min Typ Max Units Comments No. D323 VUSBANA Regulator Output Voltage 3.0 — 3.6 V VDD > 4.0V(1) D324 CUSB External Filter Capacitor 0.22 0.47 12(2) μF Ceramic or other low-ESR Value (VUSB to VSS) capacitor recommended Note 1: If device VDD is less than 4.0V, the internal USB voltage regulator should be disabled and an external 3.0-3.6V supply should be provided on VUSB if the USB module is used. 2: This is a recommended maximum for start-up time and in-rush considerations. When the USB regulator is disabled, there is no maximum. © 2009 Microchip Technology Inc. DS39632E-page 383

PIC18F2455/2550/4455/4550 FIGURE 28-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 28-6: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Typ Max Units Conditions No. D420 HLVD Voltage on VDD HLVDL<3:0> = 0000 2.06 2.17 2.28 V Transition High-to-Low HLVDL<3:0> = 0001 2.12 2.23 2.34 V HLVDL<3:0> = 0010 2.24 2.36 2.48 V HLVDL<3:0> = 0011 2.32 2.44 2.56 V HLVDL<3:0> = 0100 2.47 2.60 2.73 V HLVDL<3:0> = 0101 2.65 2.79 2.93 V HLVDL<3:0> = 0110 2.74 2.89 3.04 V HLVDL<3:0> = 0111 2.96 3.12 3.28 V HLVDL<3:0> = 1000 3.22 3.39 3.56 V HLVDL<3:0> = 1001 3.37 3.55 3.73 V HLVDL<3:0> = 1010 3.52 3.71 3.90 V HLVDL<3:0> = 1011 3.70 3.90 4.10 V HLVDL<3:0> = 1100 3.90 4.11 4.32 V HLVDL<3:0> = 1101 4.11 4.33 4.55 V HLVDL<3:0> = 1110 4.36 4.59 4.82 V HLVDL<3:0> = 1111 1.14 1.20 1.26 V Voltage at HLVDIN input pin compared to Internal Voltage Reference DS39632E-page 384 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 28.4 AC (Timing) Characteristics 28.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp ad SPP address write mc MCLR cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR da SPP data write sc SCK di SDI ss SS do SDO t0 T0CKI dt Data in t1 T13CKI io I/O port wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-Impedance) V Valid L Low Z High-Impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition © 2009 Microchip Technology Inc. DS39632E-page 385

PIC18F2455/2550/4455/4550 28.4.2 TIMING CONDITIONS Note: Because of space limitations, the generic The temperature and voltages specified in Table28-7 terms “PIC18FXXXX” and “PIC18LFXXXX” apply to all timing specifications unless otherwise are used throughout this section to refer to noted. Figure28-4 specifies the load conditions for the the PIC18F2455/2550/4455/4550 and timing specifications. PIC18LF2455/2550/4455/4550 families of devices specifically and only those devices. TABLE 28-7: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section28.1 and Section28.3. LF parts operate for industrial temperatures only. FIGURE 28-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports DS39632E-page 386 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 28-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 28-8: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 48 MHz EC, ECIO Oscillator mode Oscillator Frequency(1) 0.2 1 MHz XT, XTPLL Oscillator mode 4 25(2) MHz HS Oscillator mode 4 24(2) MHz HSPLL Oscillator mode 1 TOSC External CLKI Period(1) 20.8 DC ns EC, ECIO Oscillator mode Oscillator Period(1) 1000 5000 ns XT Oscillator mode 40 250 ns HS Oscillator mode 40 250 ns HSPLL Oscillator mode 2 TCY Instruction Cycle Time(1) 83.3 DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) 30 — ns XT Oscillator mode TosH High or Low Time 10 — ns HS Oscillator mode 4 TosR, External Clock in (OSC1) — 20 ns XT Oscillator mode TosF Rise or Fall Time — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 2: When VDD >= 3.3V, the maximum crystal or resonator frequency is 25 MHz (or 24 MHz with PLL prescaler). When 2.0V < VDD < 3.3V, the maximum crystal frequency = (16.36 MHz/V)(VDD – 2.0V) + 4 MHz. © 2009 Microchip Technology Inc. DS39632E-page 387

PIC18F2455/2550/4455/4550 TABLE 28-9: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 5.5V) Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 48 MHz With PLL prescaler F11 FSYS On-Chip VCO System Frequency — 96 — MHz F12 t PLL Start-up Time (Lock Time) — — 2 ms rc F13 ΔCLK CLKO Stability (Jitter) -0.25 — +0.25 % † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 28-10: AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F2455/2550/4455/4550 (INDUSTRIAL) PIC18LF2455/2550/4455/4550 (INDUSTRIAL) PIC18LF2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2455/2550/4455/4550 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Min Typ Max Units Conditions No. INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) F14 PIC18LF2455/2550/4455/4550 -2 +/-1 2 % +25°C VDD = 2.7-3.3V F15 -5 — 5 % -10°C to +85°C VDD = 2.7-3.3V F16 -10 +/-1 10 % -40°C to +85°C VDD = 2.7-3.3V F17 PIC18F2455/2550/4455/4550 -2 +/-1 2 % +25°C VDD = 4.5-5.5V F18 -5 — 5 % -10°C to +85°C VDD = 4.5-5.5V F19 -10 +/-1 10 % -40°C to +85°C VDD = 4.5-5.5V INTRC Accuracy @ Freq = 31 kHz(2) F20 PIC18LF2455/2550/4455/4550 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V F21 PIC18F2455/2550/4455/4550 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V Legend: Shading of rows is to assist in readability of the table. Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift. 2: INTRC frequency after calibration. 3: Change of INTRC frequency as VDD changes. DS39632E-page 388 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 28-6: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure28-4 for load conditions. TABLE 28-11: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TosH2ckL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1) 11 TosH2ckH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1) 12 TckR CLKO Rise Time — 35 100 ns (Note 1) 13 TckF CLKO Fall Time — 35 100 ns (Note 1) 14 TckL2ioV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TioV2ckH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1) 16 TckH2ioI Port In Hold after CLKO ↑ 0 — — ns (Note 1) 17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TosH2ioI OSC1 ↑ (Q2 cycle) to PIC18FXXXX 100 — — ns 18A Port Input Invalid PIC18LFXXXX 200 — — ns VDD = 2.0V (I/O in hold time) 19 TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup 0 — — ns time) 20 TioR Port Output Rise Time PIC18FXXXX — 10 25 ns 20A PIC18LFXXXX — — 60 ns VDD = 2.0V 21 TioF Port Output Fall Time PIC18FXXXX — 10 25 ns 21A PIC18LFXXXX — — 60 ns VDD = 2.0V 22† TINP INTx pin High or Low Time TCY — — ns 23† TRBP RB7:RB4 Change INTx High or Low Time TCY — — ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. © 2009 Microchip Technology Inc. DS39632E-page 389

PIC18F2455/2550/4455/4550 FIGURE 28-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure28-4 for load conditions. FIGURE 28-8: BROWN-OUT RESET TIMING VDD BVDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period 3.5 4.1 4.8 ms (no postscaler) 32 TOST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 57.0 65.5 77.1 ms 34 TIOZ I/O High-Impedance from MCLR — 2 — μs Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — μs VDD ≤ BVDD (see D005) 36 TIRVST Time for Internal Reference — 20 50 μs Voltage to become Stable 37 TLVD Low-Voltage Detect Pulse Width 200 — — μs VDD ≤ VLVD 38 TCSD CPU Start-up Time 5 — 10 μs 39 TIOBST Time for INTOSC to Stabilize — 1 — ms DS39632E-page 390 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 28-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure28-4 for load conditions. TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 Tt0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 Tt1H T13CKI High Synchronous, no prescaler 0.5 TCY + 20 — ns Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 46 Tt1L T13CKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 47 Tt1P T13CKI Input Synchronous Greater of: — ns N = prescale Period 20ns or value (1, 2, 4, 8) (TCY + 40)/N Asynchronous 60 — ns Ft1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 Tcke2tmrI Delay from External T13CKI Clock Edge to Timer 2 TOSC 7 TOSC — Increment © 2009 Microchip Technology Inc. DS39632E-page 391

PIC18F2455/2550/4455/4550 FIGURE 28-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure28-4 for load conditions. TABLE 28-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TccL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With PIC18FXXXX 10 — ns prescaler PIC18LFXXXX 20 — ns VDD = 2.0V 51 TccH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With PIC18FXXXX 10 — ns prescaler PIC18LFXXXX 20 — ns VDD = 2.0V 52 TccP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TccR CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 54 TccF CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V DS39632E-page 392 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 28-11: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure28-4 for load conditions. TABLE 28-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input 3 TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 20 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2) of Byte 2 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 35 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 78 TscR SCK Output Rise Time PIC18FXXXX — 25 ns (Master mode) PIC18LFXXXX — 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after PIC18FXXXX — 50 ns TscL2doV SCK Edge PIC18LFXXXX — 100 ns VDD = 2.0V Note 1: Requires the use of Parameter 73A. 2: Only if Parameter 71A and 72A are used. © 2009 Microchip Technology Inc. DS39632E-page 393

PIC18F2455/2550/4455/4550 FIGURE 28-12: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure28-4 for load conditions. TABLE 28-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 20 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2) of Byte 2 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 35 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 78 TscR SCK Output Rise Time PIC18FXXXX — 25 ns (Master mode) PIC18LFXXXX — 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after PIC18FXXXX — 50 ns TscL2doV SCK Edge PIC18LFXXXX — 100 ns VDD = 2.0V 81 TdoV2scH, SDO Data Output Setup to SCK Edge TCY — ns TdoV2scL Note 1: Requires the use of Parameter 73A. 2: Only if Parameter 71A and 72A are used. DS39632E-page 394 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 28-13: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure28-4 for load conditions. TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input 3 TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns (Slave mode) 72A Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 20 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 35 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 77 TssH2doZ SS ↑ to SDO Output High-Impedance 10 50 ns 78 TscR SCK Output Rise Time (Master mode) PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns TscL2doV PIC18LFXXXX — 100 ns VDD = 2.0V 83 TscH2ssH, SS ↑ after SCK edge 1.5 TCY + 40 — ns TscL2ssH Note 1: Requires the use of Parameter 73A. 2: Only if Parameter 71A and 72A are used. © 2009 Microchip Technology Inc. DS39632E-page 395

PIC18F2455/2550/4455/4550 FIGURE 28-14: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure28-4 for load conditions. TABLE 28-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input 3 TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 35 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 77 TssH2doZ SS ↑ to SDO Output High-Impedance 10 50 ns 78 TscR SCK Output Rise Time PIC18FXXXX — 25 ns (Master mode) PIC18LFXXXX — 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after SCK PIC18FXXXX — 50 ns TscL2doV Edge PIC18LFXXXX — 100 ns VDD = 2.0V 82 TssL2doV SDO Data Output Valid after SS ↓ PIC18FXXXX — 50 ns Edge PIC18LFXXXX — 100 ns VDD = 2.0V 83 TscH2ssH, SS ↑ after SCK Edge 1.5 TCY + 40 — ns TscL2ssH Note 1: Requires the use of Parameter 73A. 2: Only if Parameter 71A and 72A are used. DS39632E-page 396 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 28-15: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure28-4 for load conditions. TABLE 28-19: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 28-16: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure28-4 for load conditions. © 2009 Microchip Technology Inc. DS39632E-page 397

PIC18F2455/2550/4455/4550 TABLE 28-20: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs PIC18FXXXX must operate at a minimum of 10 MHz MSSP Module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs PIC18FXXXX must operate at a minimum of 10 MHz MSSP Module 1.5 TCY — 102 TR SDA and SCL Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition 100 kHz mode 4.7 — μs Only relevant for Repeated Setup Time 400 kHz mode 0.6 — μs Start condition 91 THD:STA Start Condition 100 kHz mode 4.0 — μs After this period, the first Hold Time 400 kHz mode 0.6 — μs clock pulse is generated 106 THD:DAT Data Input Hold 100 kHz mode 0 — ns Time 400 kHz mode 0 0.9 μs 107 TSU:DAT Data Input Setup 100 kHz mode 250 — ns (Note 2) Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 4.7 — μs Setup Time 400 kHz mode 0.6 — μs 109 TAA Output Valid from 100 kHz mode — 3500 ns (Note 1) Clock 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free before a new transmission 400 kHz mode 1.3 — μs can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system but the requirement, TSU:DAT≥250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS39632E-page 398 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 28-17: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure28-4 for load conditions. TABLE 28-21: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. FIGURE 28-18: MASTER SSP I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure28-4 for load conditions. © 2009 Microchip Technology Inc. DS39632E-page 399

PIC18F2455/2550/4455/4550 TABLE 28-22: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free before a new transmission 400 kHz mode 1.3 — ms can start D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system but parameter #107≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter #102 + parameter #107=1000+250=1250ns (for 100 kHz mode), before the SCL line is released. DS39632E-page 400 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 28-19: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT/SDO pin 120 122 Note: Refer to Figure28-4 for load conditions. TABLE 28-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid PIC18FXXXX — 40 ns PIC18LFXXXX — 100 ns VDD = 2.0V 121 Tckrf Clock Out Rise Time and Fall Time PIC18FXXXX — 20 ns (Master mode) PIC18LFXXXX — 50 ns VDD = 2.0V 122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V FIGURE 28-20: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT/SDO pin 126 Note: Refer to Figure28-4 for load conditions. TABLE 28-24: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Hold before CK ↓ (DT hold time) 10 — ns 126 TCKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns © 2009 Microchip Technology Inc. DS39632E-page 401

PIC18F2455/2550/4455/4550 FIGURE 28-21: USB SIGNAL TIMING USB Data Differential Lines 90% VCRS 10% TLR, TFR TLF, TFF TABLE 28-25: USB LOW-SPEED TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. T01 TLR Transition Rise Time 75 — 300 ns CL = 200 to 600pF T02 TLF Transition Fall Time 75 — 300 ns CL = 200 to 600pF T03 TLRFM Rise/Fall Time Matching 80 — 125 % TABLE 28-26: USB FULL-SPEED REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. T04 TFR Transition Rise Time 4 — 20 ns CL = 50pF T05 TFF Transition Fall Time 4 — 20 ns CL = 50pF T06 TFRFM Rise/Fall Time Matching 90 — 111.1 % DS39632E-page 402 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 FIGURE 28-22: STREAMING PARALLEL PORT TIMING (PIC18F4455/4550) OESPP CSSPP ToeF2adR ToeF2daR SPP<7:0> Write Address Write Data ToeF2adV ToeR2adI ToeF2daV ToeR2adI Note: Refer to Figure28-4 for load conditions. TABLE 28-27: STREAMING PARALLEL PORT REQUIREMENTS (PIC18F4455/4550) Param. Symbol Characteristic Min Max Units Conditions No. T07 ToeF2adR OESPP Falling Edge to CSSPP Rising Edge, 0 5 ns Address Out T08 ToeF2adV OESPP Falling Edge to Address Out Valid 0 5 ns T09 ToeR2adI OESPP Rising Edge to Address Out Invalid 0 5 ns T10 ToeF2daR OESPP Falling Edge to CSSPP Rising Edge, 0 5 ns Data Out T11 ToeF2daV OESPP Falling Edge to Address Out Valid 0 5 ns T12 ToeR2daI OESPP Rising Edge to Data Out Invalid 0 5 ns © 2009 Microchip Technology Inc. DS39632E-page 403

PIC18F2455/2550/4455/4550 TABLE 28-28: A/D CONVERTER CHARACTERISTICS: PIC18F2455/2550/4455/4550 (INDUSTRIAL) PIC18LF2455/2550/4455/4550 (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSB ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSB ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±2.0 LSB ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±1 LSB ΔVREF ≥ 3.0V A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range 1.8 — VDD – VSS V VDD < 3.0V (VREFH – VREFL) 3.0 — VDD – VSS V VDD ≥ 3.0V A21 VREFH Reference Voltage High Vss + — VDD V ΔVREF A22 VREFL Reference Voltage Low VSS — VDD - ΔVREF V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 2.5 kΩ Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 μA During VAIN acquisition. — — 150 μA During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source. FIGURE 28-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 3 2 1 0 ADRES OLD_DATA NEW_DATA TCY(1) ADIF GO DONE SAMPLE SAMPLING STOPPED TDIS Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. DS39632E-page 404 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TABLE 28-29: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period PIC18FXXXX 0.8 25.0(1) μs TOSC based, VREF ≥ 3.0V PIC18LFXXXX 1.4 25.0(1) μs VDD = 2.0V, TOSC based, VREF full range PIC18FXXXX — 1 μs A/D RC mode PIC18LFXXXX — 3 μs VDD = 2.0V, A/D RC mode 131 TCNV Conversion Time 11 12 TAD (not including acquisition time)(2) 132 TACQ Acquisition Time(3) 1.4 — μs -40°C to +85°C 135 TSWC Switching Time from Convert → Sample — (Note 4) 137 TDIS Discharge Time 0.2 — μs Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VSS to VDD). The source impedance (RS) on the input channels is 50Ω. 4: On the following cycle of the device clock. © 2009 Microchip Technology Inc. DS39632E-page 405

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 406 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 29.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time. © 2009 Microchip Technology Inc. DS39632E-page 407

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 408 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example XXXXXXXXXXXXXXXXX PIC18F2455-I/SPe3 XXXXXXXXXXXXXXXXX 0810017 YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC18F2550-E/SOe3 XXXXXXXXXXXXXXXXXXXX 0810017 XXXXXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX PIC18F4455-I/Pe3 XXXXXXXXXXXXXXXXXX 0810017 XXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS39632E-page 409

PIC18F2455/2550/4455/4550 Package Marking Information (Continued) 44-Lead TQFP Example XXXXXXXXXX PIC18F4550 XXXXXXXXXX -I/PTe3 XXXXXXXXXX 0810017 YYWWNNN 44-Lead QFN Example XXXXXXXXXX PIC18F4550 XXXXXXXXXX -I/MLe3 XXXXXXXXXX 0810017 YYWWNNN DS39632E-page 410 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 30.2 Package Details The following sections give the technical details of the packages. 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(cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1 © 2009 Microchip Technology Inc. DS39632E-page 411

PIC18F2455/2550/4455/4550 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)#(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)#(cid:24)(cid:9)(cid:25)(cid:9)$(cid:12)(cid:8)(cid:6)%(cid:9)&’((cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)#(cid:22)) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 3 e b h α h φ c A A2 L A1 L1 β 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)?(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:3)(cid:20)(cid:4)(cid:29) = = (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2)+ (cid:25)(cid:30) (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)-(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:4)(cid:20)-(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:5)(cid:20)(cid:29)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:5)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), ,(cid:11)(cid:28)’%(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)(cid:29) = (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) = (cid:30)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:23)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:30)< = (cid:4)(cid:20)-- 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:30) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:29)B = (cid:30)(cid:29)B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:29)B = (cid:30)(cid:29)B !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:3)1 DS39632E-page 412 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 *(cid:27)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)+(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c b1 A1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:29) = (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:29)(cid:24)(cid:4) = (cid:20)?(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:23)<(cid:29) = (cid:20)(cid:29)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)(cid:24)<(cid:4) = (cid:3)(cid:20)(cid:4)(cid:24)(cid:29) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) = (cid:20)(cid:3)(cid:4)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< = (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)-(cid:4) = (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) = (cid:20)(cid:4)(cid:3)- : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:5)(cid:4)(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)?1 © 2009 Microchip Technology Inc. DS39632E-page 413

PIC18F2455/2550/4455/4550 **(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9),-(cid:12)(cid:13)(cid:9).(cid:21)(cid:7)(cid:8)(cid:9)/(cid:16)(cid:7)(cid:18)0(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15),(cid:24)(cid:9)(cid:25)(cid:9)1(cid:27)21(cid:27)21(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)%(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31),./(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)9(cid:14)(cid:28)#! 7 (cid:23)(cid:23) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)<(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:24)(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B -(cid:20)(cid:29)B (cid:5)B : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:5) (cid:4)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:30)(cid:30)B (cid:30)(cid:3)B (cid:30)-B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:30)(cid:30)B (cid:30)(cid:3)B (cid:30)-B !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ,(cid:11)(cid:28)’%(cid:14)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:8)(cid:10)(cid:9)(cid:15)(cid:14)(cid:9)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:2)(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)C(cid:2)!(cid:7)D(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:30)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)?1 DS39632E-page 414 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 **(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9),-(cid:12)(cid:13)(cid:9).(cid:21)(cid:7)(cid:8)(cid:9)/(cid:16)(cid:7)(cid:18)0(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15),(cid:24)(cid:9)(cid:25)(cid:9)1(cid:27)21(cid:27)21(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)%(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31),./(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2009 Microchip Technology Inc. DS39632E-page 415

PIC18F2455/2550/4455/4550 **(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9).(cid:21)(cid:7)(cid:8)(cid:9)/(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)3(cid:6)(cid:9)(cid:23)4(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)(cid:3)2(cid:3)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)./! !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE1 N L K TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:23) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:29) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-< ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:29)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# E (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)-1 DS39632E-page 416 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 **(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9).(cid:21)(cid:7)(cid:8)(cid:9)/(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)3(cid:6)(cid:9)(cid:23)4(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)(cid:3)2(cid:3)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)./! !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2009 Microchip Technology Inc. DS39632E-page 417

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 418 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 APPENDIX A: REVISION HISTORY Revision D (January 2007) This revision includes updates to the packaging Revision A (May 2004) diagrams. Original data sheet for PIC18F2455/2550/4455/4550 Revision E (August 2008) devices. This revision includes minor corrections to the data Revision B (October 2004) sheet text. In Section30.2 “Package Details”, added This revision includes updates to the Electrical Specifi- land pattern drawings for both 44-pin packages. cations in Section28.0 “Electrical Characteristics” and includes minor corrections to the data sheet text. APPENDIX B: DEVICE DIFFERENCES Revision C (February 2006) This revision includes updates to Section19.0 “Master The differences between the devices listed in this data Synchronous Serial Port (MSSP) Module”, sheet are shown in TableB-1. Section20.0 “Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)” and the Electrical Specifications in Section28.0 “Electrical Characteristics” and includes minor corrections to the data sheet text. TABLE B-1: DEVICE DIFFERENCES Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550 Program Memory (Bytes) 24576 32768 24576 32768 Program Memory (Instructions) 12288 16384 12288 16384 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Capture/Compare/PWM Modules 2 2 1 1 Enhanced Capture/Compare/ 0 0 1 1 PWM Modules Parallel Communications (SPP) No No Yes Yes 10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Packages 28-Pin PDIP 28-Pin PDIP 40-Pin PDIP 40-Pin PDIP 28-Pin SOIC 28-Pin SOIC 44-Pin TQFP 44-Pin TQFP 44-Pin QFN 44-Pin QFN © 2009 Microchip Technology Inc. DS39632E-page 419

PIC18F2455/2550/4455/4550 APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM CONSIDERATIONS BASELINE TO ENHANCED DEVICES This appendix discusses the considerations for converting from previous versions of a device to the This section discusses how to migrate from a Baseline ones listed in this data sheet. Typically, these changes device (i.e., PIC16C5X) to an Enhanced MCU device are due to the differences in the process technology (i.e., PIC18FXXX). used. An example of this type of conversion is from a The following are the list of modifications over the PIC16C74A to a PIC16C74B. PIC16C5X microcontroller family: Not Applicable Not Currently Available DS39632E-page 420 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 APPENDIX E: MIGRATION FROM APPENDIX F: MIGRATION FROM MID-RANGE TO HIGH-END TO ENHANCED DEVICES ENHANCED DEVICES A detailed discussion of the differences between the A detailed discussion of the migration pathway and mid-range MCU devices (i.e., PIC16CXXX) and the differences between the high-end MCU devices (i.e., enhanced devices (i.e., PIC18FXXX) is provided in PIC17CXXX) and the enhanced devices (i.e., AN716, “Migrating Designs from PIC16C74A/74B to PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18C442”. The changes discussed, while device PIC18CXXX Migration”. This Application Note is specific, are generally applicable to all mid-range to available as Literature Number DS00726. enhanced device migrations. This Application Note is available as Literature Number DS00716. © 2009 Microchip Technology Inc. DS39632E-page 421

PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 422 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 INDEX Block Diagrams A/D ...........................................................................268 A Analog Input Model ..................................................269 Baud Rate Generator ..............................................228 A/D ...................................................................................265 Capture Mode Operation .........................................145 Acquisition Requirements ........................................270 Comparator Analog Input Model ..............................279 ADCON0 Register ....................................................265 Comparator I/O Operating Modes ...........................276 ADCON1 Register ....................................................265 Comparator Output ..................................................278 ADCON2 Register ....................................................265 Comparator Voltage Reference ...............................282 ADRESH Register ............................................265, 268 Comparator Voltage Reference ADRESL Register ....................................................265 Output Buffer Example ....................................283 Analog Port Pins, Configuring ..................................272 Compare Mode Operation .......................................146 Associated Registers ...............................................274 Device Clock ..............................................................24 Configuring the Module ............................................269 Enhanced PWM .......................................................153 Conversion Clock (TAD) ...........................................271 EUSART Receive ....................................................257 Conversion Requirements .......................................405 EUSART Transmit ...................................................254 Conversion Status (GO/DONE Bit) ..........................268 External Power-on Reset Circuit Conversions .............................................................273 Converter Characteristics ........................................404 (Slow VDD Power-up) ........................................47 Fail-Safe Clock Monitor ...........................................306 Converter Interrupt, Configuring ..............................269 Generic I/O Port .......................................................113 Discharge .................................................................273 High/Low-Voltage Detect with External Input ..........286 Operation in Power-Managed Modes ......................272 Interrupt Logic ..........................................................100 Selecting and Configuring Acquisition Time ............271 MSSP (I2C Master Mode) ........................................226 Special Event Trigger (CCP2) ..................................274 MSSP (I2C Mode) ....................................................207 Special Event Trigger (ECCP) .................................152 MSSP (SPI Mode) ...................................................197 Use of the CCP2 Trigger ..........................................274 On-Chip Reset Circuit ................................................45 Absolute Maximum Ratings .............................................367 PIC18F2455/2550 .....................................................10 AC (Timing) Characteristics .............................................385 PIC18F4455/4550 .....................................................11 Load Conditions for Device Timing PLL (HS Mode) ..........................................................27 Specifications ...................................................386 PWM Operation (Simplified) ....................................148 Parameter Symbology .............................................385 Reads from Flash Program Memory .........................85 Temperature and Voltage Specifications .................386 Single Comparator ...................................................277 Timing Conditions ....................................................386 SPP Data Path ........................................................191 AC Characteristics Table Read Operation ...............................................81 Internal RC Accuracy ...............................................388 Table Write Operation ...............................................82 Access Bank Table Writes to Flash Program Memory ....................87 Mapping with Indexed Literal Offset Mode .................79 Timer0 in 16-Bit Mode .............................................128 ACKSTAT ........................................................................232 Timer0 in 8-Bit Mode ...............................................128 ACKSTAT Status Flag .....................................................232 Timer1 .....................................................................132 ADCON0 Register ............................................................265 Timer1 (16-Bit Read/Write Mode) ............................132 GO/DONE Bit ...........................................................268 Timer2 .....................................................................138 ADCON1 Register ............................................................265 Timer3 .....................................................................140 ADCON2 Register ............................................................265 Timer3 (16-Bit Read/Write Mode) ............................140 ADDFSR ..........................................................................356 USB Interrupt Logic .................................................180 ADDLW ............................................................................319 USB Peripheral and Options ...................................165 ADDULNK ........................................................................356 Watchdog Timer ......................................................303 ADDWF ............................................................................319 BN ....................................................................................322 ADDWFC .........................................................................320 BNC .................................................................................323 ADRESH Register ............................................................265 BNN .................................................................................323 ADRESL Register ....................................................265, 268 BNOV ..............................................................................324 Analog-to-Digital Converter. See A/D. BNZ .................................................................................324 and BSR .............................................................................79 BOR. See Brown-out Reset. ANDLW ............................................................................320 BOV .................................................................................327 ANDWF ............................................................................321 BRA .................................................................................325 Assembler Break Character (12-Bit) Transmit and Receive ..............259 MPASM Assembler ..................................................364 BRG. See Baud Rate Generator. B Brown-out Reset (BOR) .....................................................48 Baud Rate Generator .......................................................228 Detecting ...................................................................48 BC ....................................................................................321 Disabling in Sleep Mode ............................................48 BCF ..................................................................................322 Software Enabled ......................................................48 BF ....................................................................................232 BSF ..................................................................................325 BF Status Flag .................................................................232 BTFSC .............................................................................326 BTFSS .............................................................................326 BTG .................................................................................327 BZ ....................................................................................328 © 2009 Microchip Technology Inc. DS39632E-page 423

PIC18F2455/2550/4455/4550 C Interrupts .................................................................278 Operation .................................................................277 C Compilers Operation During Sleep ...........................................278 MPLAB C18 .............................................................364 Outputs ....................................................................277 MPLAB C30 .............................................................364 Reference ................................................................277 CALL ................................................................................328 External Signal ................................................277 CALLW .............................................................................357 Internal Signal ..................................................277 Capture (CCP Module) .....................................................145 Response Time ........................................................277 CCP Pin Configuration .............................................145 Comparator Specifications ...............................................382 CCPRxH:CCPRxL Registers ...................................145 Comparator Voltage Reference .......................................281 Prescaler ..................................................................145 Accuracy and Error ..................................................282 Software Interrupt ....................................................145 Associated Registers ...............................................283 Timer1/Timer3 Mode Selection ................................145 Configuring ..............................................................281 Capture (ECCP Module) ..................................................152 Connection Considerations ......................................282 Capture/Compare (CCP Module) Effects of a Reset ....................................................282 Associated Registers ...............................................147 Operation During Sleep ...........................................282 Capture/Compare/PWM (CCP) ........................................143 Compare (CCP Module) ..................................................146 Capture Mode. See Capture. CCP Pin Configuration .............................................146 CCP Mode and Timer Resources ............................144 CCPRx Register ......................................................146 CCP2 Pin Assignment .............................................144 Software Interrupt ....................................................146 CCPRxH Register ....................................................144 Special Event Trigger ..............................141, 146, 274 CCPRxL Register .....................................................144 Timer1/Timer3 Mode Selection ................................146 Compare Mode. See Compare. Compare (ECCP Module) ................................................152 Interaction of Two CCP Modules for Special Event Trigger ..............................................152 Timer Resources ..............................................144 Configuration Bits ............................................................292 Module Configuration ...............................................144 Configuration Register Protection ....................................311 Clock Sources ....................................................................32 Context Saving During Interrupts .....................................111 Effects of Power-Managed Modes .............................34 Conversion Considerations ..............................................420 Selecting the 31 kHz Source ......................................32 CPFSEQ ..........................................................................330 Selection Using OSCCON Register ...........................32 CPFSGT ..........................................................................331 CLRF ................................................................................329 CPFSLT ...........................................................................331 CLRWDT ..........................................................................329 Crystal Oscillator/Ceramic Resonator ................................25 Code Examples Customer Change Notification Service ............................433 16 x 16 Signed Multiply Routine ................................98 Customer Notification Service .........................................433 16 x 16 Unsigned Multiply Routine ............................98 Customer Support ............................................................433 8 x 8 Signed Multiply Routine ....................................97 8 x 8 Unsigned Multiply Routine ................................97 D Changing Between Capture Prescalers ...................145 Data Addressing Modes ....................................................74 Computed GOTO Using an Offset Value ...................62 Comparing Addressing Modes with the Data EEPROM Read .................................................93 Extended Instruction Set Enabled .....................78 Data EEPROM Refresh Routine ................................94 Direct .........................................................................74 Data EEPROM Write .................................................93 Indexed Literal Offset ................................................77 Erasing a Flash Program Memory Row .....................86 Indirect .......................................................................74 Executing Back to Back SLEEP Instructions .............36 Inherent and Literal ....................................................74 Fast Register Stack ....................................................62 Data EEPROM How to Clear RAM (Bank 1) Using Code Protection .......................................................311 Indirect Addressing ............................................74 Data EEPROM Memory .....................................................91 Implementing a Real-Time Clock Using Associated Registers .................................................95 a Timer1 Interrupt Service ...............................135 EECON1 and EECON2 Registers .............................91 Initializing PORTA ....................................................113 Operation During Code-Protect .................................94 Initializing PORTB ....................................................116 Protection Against Spurious Write .............................94 Initializing PORTC ....................................................119 Reading .....................................................................93 Initializing PORTD ....................................................122 Using .........................................................................94 Initializing PORTE ....................................................125 Write Verify ................................................................93 Loading the SSPBUF (SSPSR) Register .................200 Writing .......................................................................93 Reading a Flash Program Memory Word ..................85 Data Memory .....................................................................65 Saving STATUS, WREG and BSR Access Bank ..............................................................67 Registers in RAM .............................................111 and the Extended Instruction Set ..............................77 Writing to Flash Program Memory .......................88–89 Bank Select Register (BSR) ......................................65 Code Protection ...............................................................291 General Purpose Registers .......................................67 COMF ...............................................................................330 Map for PIC18F2455/2550/4455/4550 Devices .........66 Comparator ......................................................................275 Special Function Registers ........................................68 Analog Input Connection Considerations .................279 Map ....................................................................68 Associated Registers ...............................................279 USB RAM ..................................................................65 Configuration ............................................................276 DAW ................................................................................332 Effects of a Reset .....................................................278 DS39632E-page 424 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 DC and AC Characteristics Synchronous Master Mode ......................................260 Graphs and Tables ..................................................407 Associated Registers, Receive ........................262 DC Characteristics ...........................................................379 Associated Registers, Transmit .......................261 Power-Down and Supply Current ............................370 Reception ........................................................262 Supply Voltage .........................................................369 Transmission ...................................................260 DCFSNZ ..........................................................................333 Synchronous Slave Mode ........................................263 DECF ...............................................................................332 Associated Registers, Receive ........................264 DECFSZ ...........................................................................333 Associated Registers, Transmit .......................263 Dedicated ICD/ICSP Port .................................................311 Reception ........................................................264 Development Support ......................................................363 Transmission ...................................................263 Device Differences ...........................................................419 Extended Instruction Set .................................................355 Device Overview ..................................................................7 ADDFSR ..................................................................356 Features (table) ............................................................9 ADDULNK ...............................................................356 New Core Features ......................................................7 and Using MPLAB IDE Tools ..................................362 Other Special Features ................................................8 CALLW ....................................................................357 Device Reset Timers ..........................................................49 Considerations for Use ............................................360 Oscillator Start-up Timer (OST) .................................49 MOVSF ....................................................................357 PLL Lock Time-out .....................................................49 MOVSS ....................................................................358 Power-up Timer (PWRT) ...........................................49 PUSHL .....................................................................358 Direct Addressing ...............................................................75 SUBFSR ..................................................................359 SUBULNK ................................................................359 E Syntax ......................................................................355 Effect on Standard PIC MCU Instructions ..................77, 360 External Clock Input ...........................................................26 Electrical Characteristics ..................................................367 F Enhanced Capture/Compare/PWM (ECCP) ....................151 Associated Registers ...............................................164 Fail-Safe Clock Monitor ...........................................291, 306 Capture and Compare Modes ..................................152 Exiting the Operation ...............................................306 Capture Mode. See Capture (ECCP Module). Interrupts in Power-Managed Modes ......................307 Outputs and Configuration .......................................152 POR or Wake-up from Sleep ...................................307 Pin Configurations for ECCP1 .................................152 WDT During Oscillator Failure .................................306 PWM Mode. See PWM (ECCP Module). Fast Register Stack ...........................................................62 Standard PWM Mode ...............................................152 Firmware Instructions ......................................................313 Timer Resources ......................................................152 Flash Program Memory .....................................................81 Enhanced Universal Synchronous Asynchronous Associated Registers .................................................89 Receiver Transmitter (EUSART). See EUSART. Control Registers .......................................................82 Equations EECON1 and EECON2 .....................................82 A/D Acquisition Time ................................................270 TABLAT (Table Latch) Register ........................84 A/D Minimum Charging Time ...................................270 TBLPTR (Table Pointer) Register ......................84 Calculating the Minimum Required A/D Erase Sequence ........................................................86 Acquisition Time ..............................................270 Erasing ......................................................................86 Errata ...................................................................................5 Operation During Code-Protect .................................89 EUSART Protection Against Spurious Writes ...........................89 Asynchronous Mode ................................................253 Reading .....................................................................85 12-Bit Break Transmit and Receive .................259 Table Pointer Associated Registers, Receive ........................257 Boundaries Based on Operation .......................84 Associated Registers, Transmit .......................255 Table Pointer Boundaries ..........................................84 Auto-Wake-up on Sync Break Character .........258 Table Reads and Table Writes ..................................81 Receiver ...........................................................256 Unexpected Termination of Write ..............................89 Setting up 9-Bit Mode with Write Sequence .........................................................87 Address Detect ........................................256 Write Verify ................................................................89 Transmitter .......................................................253 Writing To ..................................................................87 Baud Rate Generator FSCM. See Fail-Safe Clock Monitor. Operation in Power-Managed Modes ..............247 G Baud Rate Generator (BRG) ....................................247 Associated Registers .......................................248 GOTO ..............................................................................334 Auto-Baud Rate Detect ....................................251 H Baud Rate Error, Calculating ...........................248 Baud Rates, Asynchronous Modes .................249 Hardware Multiplier ............................................................97 High Baud Rate Select (BRGH Bit) .................247 Introduction ................................................................97 Sampling ..........................................................247 Operation ...................................................................97 Performance Comparison ..........................................97 © 2009 Microchip Technology Inc. DS39632E-page 425

PIC18F2455/2550/4455/4550 High/Low-Voltage Detect .................................................285 Instruction Cycle ................................................................63 Applications ..............................................................288 Clocking Scheme .......................................................63 Associated Registers ...............................................289 Flow/Pipelining ...........................................................63 Characteristics .........................................................384 Instruction Set ..................................................................313 Current Consumption ...............................................287 ADDLW ....................................................................319 Effects of a Reset .....................................................289 ADDWF ....................................................................319 Operation .................................................................286 ADDWF (Indexed Literal Offset mode) ....................361 During Sleep ....................................................289 ADDWFC .................................................................320 Setup ........................................................................287 ANDLW ....................................................................320 Start-up Time ...........................................................287 ANDWF ....................................................................321 Typical Application ...................................................288 BC ............................................................................321 HLVD. See High/Low-Voltage Detect. .............................285 BCF .........................................................................322 BN ............................................................................322 I BNC .........................................................................323 I/O Ports ...........................................................................113 BNN .........................................................................323 I2C Mode (MSSP) BNOV ......................................................................324 Acknowledge Sequence Timing ...............................235 BNZ .........................................................................324 Associated Registers ...............................................241 BOV .........................................................................327 Baud Rate Generator ...............................................228 BRA .........................................................................325 Bus Collision BSF ..........................................................................325 During a Repeated Start Condition ..................239 BSF (Indexed Literal Offset mode) ..........................361 During a Stop Condition ...................................240 BTFSC .....................................................................326 Clock Arbitration .......................................................229 BTFSS .....................................................................326 Clock Stretching .......................................................221 BTG .........................................................................327 10-Bit Slave Receive Mode (SEN = 1) .............221 BZ ............................................................................328 10-Bit Slave Transmit Mode .............................221 CALL ........................................................................328 7-Bit Slave Receive Mode (SEN = 1) ...............221 CLRF .......................................................................329 7-Bit Slave Transmit Mode ...............................221 CLRWDT .................................................................329 Clock Synchronization and the CKP Bit ...................222 COMF ......................................................................330 Effect of a Reset ......................................................236 CPFSEQ ..................................................................330 General Call Address Support .................................225 CPFSGT ..................................................................331 I2C Clock Rate w/BRG .............................................228 CPFSLT ...................................................................331 Master Mode ............................................................226 DAW ........................................................................332 Operation .........................................................227 DCFSNZ ..................................................................333 Reception .........................................................232 DECF .......................................................................332 Repeated Start Condition Timing .....................231 DECFSZ ..................................................................333 Start Condition Timing .....................................230 General Format ........................................................315 Transmission ....................................................232 GOTO ......................................................................334 Transmit Sequence ..........................................227 INCF ........................................................................334 Multi-Master Communication, Bus Collision INCFSZ ....................................................................335 and Arbitration ..................................................236 INFSNZ ....................................................................335 Multi-Master Mode ...................................................236 IORLW .....................................................................336 Operation .................................................................212 IORWF .....................................................................336 Read/Write Bit Information (R/W Bit) ...............212, 214 LFSR .......................................................................337 Registers ..................................................................207 MOVF ......................................................................337 Serial Clock (RB1/AN10/INT1/SCK/SCL) ................214 MOVFF ....................................................................338 Slave Mode ..............................................................212 MOVLB ....................................................................338 Addressing .......................................................212 MOVLW ...................................................................339 Addressing Masking .........................................213 MOVWF ...................................................................339 Reception .........................................................214 MULLW ....................................................................340 Transmission ....................................................214 MULWF ....................................................................340 Sleep Operation .......................................................236 NEGF .......................................................................341 Stop Condition Timing ..............................................235 NOP .........................................................................341 ID Locations .............................................................291, 311 Opcode Field Descriptions .......................................314 Idle Modes ..........................................................................40 POP .........................................................................342 INCF .................................................................................334 PUSH .......................................................................342 INCFSZ ............................................................................335 RCALL .....................................................................343 In-Circuit Debugger ..........................................................311 RESET .....................................................................343 In-Circuit Serial Programming (ICSP) ......................291, 311 RETFIE ....................................................................344 Indexed Literal Offset Addressing RETLW ....................................................................344 and Standard PIC18 Instructions .............................360 RETURN ..................................................................345 Indexed Literal Offset Mode .................................77, 79, 360 RLCF .......................................................................345 Indirect Addressing ............................................................75 RLNCF .....................................................................346 INFSNZ ............................................................................335 RRCF .......................................................................346 Initialization Conditions for all Registers ......................53–57 RRNCF ....................................................................347 DS39632E-page 426 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 SETF ........................................................................347 MOVLB ............................................................................338 SETF (Indexed Literal Offset mode) ........................361 MOVLW ...........................................................................339 SLEEP .....................................................................348 MOVSF ............................................................................357 Standard Instructions ...............................................313 MOVSS ............................................................................358 SUBFWB ..................................................................348 MOVWF ...........................................................................339 SUBLW ....................................................................349 MPLAB ASM30 Assembler, Linker, Librarian ..................364 SUBWF ....................................................................349 MPLAB ICD 2 In-Circuit Debugger ..................................365 SUBWFB ..................................................................350 MPLAB ICE 2000 High-Performance SWAPF ....................................................................350 Universal In-Circuit Emulator ...................................365 TBLRD .....................................................................351 MPLAB Integrated Development TBLWT .....................................................................352 Environment Software .............................................363 TSTFSZ ...................................................................353 MPLAB PM3 Device Programmer ...................................365 XORLW ....................................................................353 MPLAB REAL ICE In-Circuit Emulator System ...............365 XORWF ....................................................................354 MPLINK Object Linker/MPLIB Object Librarian ...............364 INTCON Register MSSP RBIF Bit ....................................................................116 ACK Pulse .......................................................212, 214 INTCON Registers ...........................................................101 Control Registers (general) .....................................197 Inter-Integrated Circuit. See I2C. I2C Mode. See I2C Mode. Internal Oscillator Block .....................................................27 Module Overview .....................................................197 Adjustment .................................................................28 SPI Master/Slave Connection ..................................201 INTHS, INTXT, INTCKO and INTIO Modes ...............27 SPI Mode. See SPI Mode. OSCTUNE Register ...................................................28 SSPBUF ..................................................................202 Internal RC Oscillator SSPSR ....................................................................202 Use with WDT ..........................................................303 MULLW ............................................................................340 Internet Address ...............................................................433 MULWF ............................................................................340 Interrupt Sources .............................................................291 N A/D Conversion Complete .......................................269 Capture Complete (CCP) .........................................145 NEGF ...............................................................................341 Compare Complete (CCP) .......................................146 NOP .................................................................................341 Interrupt-on-Change (RB7:RB4) ..............................116 O INTx Pin ...................................................................111 PORTB, Interrupt-on-Change ..................................111 Oscillator Configuration .....................................................23 TMR0 .......................................................................111 EC ..............................................................................23 TMR0 Overflow ........................................................129 ECIO ..........................................................................23 TMR1 Overflow ........................................................131 ECPIO .......................................................................23 TMR2 to PR2 Match (PWM) ............................148, 153 ECPLL .......................................................................23 TMR3 Overflow ................................................139, 141 HS ..............................................................................23 Interrupts ............................................................................99 HSPLL .......................................................................23 USB ............................................................................99 INTCKO .....................................................................23 Interrupts, Flag Bits Internal Oscillator Block .............................................27 Interrupt-on-Change (RB7:RB4) INTHS ........................................................................23 Flag (RBIF Bit) .................................................116 INTIO .........................................................................23 INTOSC Frequency Drift ....................................................28 INTXT ........................................................................23 INTOSC, INTRC. See Internal Oscillator Block. Oscillator Modes and USB Operation ........................23 IORLW .............................................................................336 Settings for USB ........................................................30 IORWF .............................................................................336 XT ..............................................................................23 IPR Registers ...................................................................108 XTPLL ........................................................................23 Oscillator Selection ..........................................................291 L Oscillator Start-up Timer (OST) ...................................34, 49 LFSR ................................................................................337 Oscillator Switching ...........................................................32 Low-Voltage ICSP Programming. See Single-Supply Oscillator Transitions .........................................................33 ICSP Programming. Oscillator, Timer1 .....................................................131, 141 Oscillator, Timer3 .............................................................139 M P Master Clear Reset (MCLR) ..............................................47 Master Synchronous Serial Port (MSSP). See MSSP. Packaging Information .....................................................409 Memory Organization .........................................................59 Details ......................................................................411 Data Memory .............................................................65 Marking ....................................................................409 Program Memory .......................................................59 PICSTART Plus Development Programmer ....................366 Memory Programming Requirements ..............................381 PIE Registers ...................................................................106 Microchip Internet Web Site .............................................433 Pin Functions Migration from Baseline to Enhanced Devices ................420 MCLR/VPP/RE3 ...................................................12, 16 Migration from High-End to Enhanced Devices ...............421 NC/ICCK/ICPGC .......................................................21 Migration from Mid-Range to Enhanced Devices ............421 NC/ICDT/ICPGD ........................................................21 MOVF ...............................................................................337 NC/ICPORTS ............................................................21 MOVFF ............................................................................338 NC/ICRST/ICVPP .......................................................21 © 2009 Microchip Technology Inc. DS39632E-page 427

PIC18F2455/2550/4455/4550 OSC1/CLKI ..........................................................12, 16 PORTC OSC2/CLKO/RA6 ................................................12, 16 Associated Registers ...............................................121 RA0/AN0 ..............................................................13, 17 I/O Summary ............................................................120 RA1/AN1 ..............................................................13, 17 LATC Register .........................................................119 RA2/AN2/VREF-/CVREF ........................................13, 17 PORTC Register ......................................................119 RA3/AN3/VREF+ ...................................................13, 17 TRISC Register ........................................................119 RA4/T0CKI/C1OUT/RCV .....................................13, 17 PORTD RA5/AN4/SS/HLVDIN/C2OUT .............................13, 17 Associated Registers ...............................................124 RB0/AN12/INT0/FLT0/SDI/SDA ..........................14, 18 I/O Summary ............................................................123 RB1/AN10/INT1/SCK/SCL ...................................14, 18 LATD Register .........................................................122 RB2/AN8/INT2/VMO ............................................14, 18 PORTD Register ......................................................122 RB3/AN9/CCP2/VPO ...........................................14, 18 TRISD Register ........................................................122 RB4/AN11/KBI0 .........................................................14 PORTE RB4/AN11/KBI0/CSSPP ............................................18 Associated Registers ...............................................126 RB5/KBI1/PGM ....................................................14, 18 I/O Summary ............................................................126 RB6/KBI2/PGC ....................................................14, 18 LATE Register .........................................................125 RB7/KBI3/PGD ....................................................14, 18 PORTE Register ......................................................125 RC0/T1OSO/T13CKI ...........................................15, 19 TRISE Register ........................................................125 RC1/T1OSI/CCP2/UOE .......................................15, 19 Postscaler, WDT RC2/CCP1 .................................................................15 Assignment (PSA Bit) ..............................................129 RC2/CCP1/P1A .........................................................19 Rate Select (T0PS2:T0PS0 Bits) .............................129 RC4/D-/VM ...........................................................15, 19 Power-Managed Modes .....................................................35 RC5/D+/VP ..........................................................15, 19 and Multiple Sleep Commands ..................................36 RC6/TX/CK ..........................................................15, 19 and PWM Operation ................................................163 RC7/RX/DT/SDO .................................................15, 19 Clock Sources ............................................................35 RD0/SPP0 ..................................................................20 Clock Transitions and Status Indicators ....................36 RD1/SPP1 ..................................................................20 Entering .....................................................................35 RD2/SPP2 ..................................................................20 Exiting Idle and Sleep Modes ....................................42 RD3/SPP3 ..................................................................20 by Interrupt ........................................................42 RD4/SPP4 ..................................................................20 by Reset ............................................................42 RD5/SPP5/P1B ..........................................................20 by WDT Time-out ..............................................42 RD6/SPP6/P1C ..........................................................20 Without an Oscillator Start-up Delay .................43 RD7/SPP7/P1D ..........................................................20 Idle .............................................................................40 RE0/AN5/CK1SPP .....................................................21 Idle Modes RE1/AN6/CK2SPP .....................................................21 PRI_IDLE ...........................................................41 RE2/AN7/OESPP .......................................................21 RC_IDLE ...........................................................42 VDD .......................................................................15, 21 SEC_IDLE .........................................................41 VSS .......................................................................15, 21 Run Modes ................................................................36 VUSB .....................................................................15, 21 PRI_RUN ...........................................................36 Pinout I/O Descriptions RC_RUN ............................................................38 PIC18F2455/2550 ......................................................12 SEC_RUN .........................................................36 PIC18F4455/4550 ......................................................16 Selecting ....................................................................35 PIR Registers ...................................................................104 Sleep .........................................................................40 PLL Frequency Multiplier ...................................................27 Summary (table) ........................................................35 HSPLL, XTPLL, ECPLL and ECPIO Power-on Reset (POR) ......................................................47 Oscillator Modes ................................................27 Oscillator Start-up Timer (OST) .................................49 PLL Lock Time-out .............................................................49 Power-up Timer (PWRT) ...........................................49 POP ..................................................................................342 Time-out Sequence ...................................................49 POR. See Power-on Reset. Power-up Delays ...............................................................34 PORTA Power-up Timer (PWRT) .............................................34, 49 Associated Registers ...............................................115 Prescaler I/O Summary ............................................................114 Timer2 .....................................................................154 LATA Register ..........................................................113 Prescaler, Timer0 ............................................................129 PORTA Register ......................................................113 Assignment (PSA Bit) ..............................................129 TRISA Register ........................................................113 Rate Select (T0PS2:T0PS0 Bits) .............................129 PORTB Prescaler, Timer2 ............................................................149 Associated Registers ...............................................118 PRI_IDLE Mode .................................................................41 I/O Summary ............................................................117 PRI_RUN Mode .................................................................36 LATB Register ..........................................................116 Program Counter ...............................................................60 PORTB Register ......................................................116 PCL, PCH and PCU Registers ..................................60 RB1/AN10/INT1/SCK/SCL Pin .................................214 PCLATH and PCLATU Registers ..............................60 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........116 TRISB Register ........................................................116 DS39632E-page 428 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 Program Memory Registers and the Extended Instruction Set ...............................77 ADCON0 (A/D Control 0) .........................................265 Code Protection .......................................................309 ADCON1 (A/D Control 1) .........................................266 Instructions .................................................................64 ADCON2 (A/D Control 2) .........................................267 Two-Word ..........................................................64 BAUDCON (Baud Rate Control) ..............................246 Interrupt Vector ..........................................................59 BDnSTAT (Buffer Descriptor n Status, Look-up Tables ..........................................................62 CPU Mode) ......................................................176 Map and Stack (diagram) ...........................................59 BDnSTAT (Buffer Descriptor n Status, Reset Vector ..............................................................59 SIE Mode) .......................................................177 Program Verification and Code Protection .......................308 CCP1CON (ECCP Control) .....................................151 Associated Registers ...............................................308 CCPxCON (Standard CCPx Control) ......................143 Programming, Device Instructions ...................................313 CMCON (Comparator Control) ................................275 Pulse-Width Modulation. See PWM (CCP Module) CONFIG1H (Configuration 1 High) ..........................294 and PWM (ECCP Module). CONFIG1L (Configuration 1 Low) ...........................293 PUSH ...............................................................................342 CONFIG2H (Configuration 2 High) ..........................296 PUSH and POP Instructions ..............................................61 CONFIG2L (Configuration 2 Low) ...........................295 PUSHL .............................................................................358 CONFIG3H (Configuration 3 High) ..........................297 PWM (CCP Module) CONFIG4L (Configuration 4 Low) ...........................298 Associated Registers ...............................................150 CONFIG5H (Configuration 5 High) ..........................299 Auto-Shutdown (CCP1 Only) ...................................149 CONFIG5L (Configuration 5 Low) ...........................299 Duty Cycle ................................................................148 CONFIG6H (Configuration 6 High) ..........................300 Example Frequencies/Resolutions ..........................149 CONFIG6L (Configuration 6 Low) ...........................300 Period .......................................................................148 CONFIG7H (Configuration 7 High) ..........................301 Setup for PWM Operation ........................................149 CONFIG7L (Configuration 7 Low) ...........................301 TMR2 to PR2 Match ................................................148 CVRCON (Comparator Voltage PWM (ECCP Module) ......................................................153 Reference Control) ..........................................281 CCPR1H:CCPR1L Registers ...................................153 DEVID1 (Device ID 1) ..............................................302 Direction Change in Full-Bridge Output Mode .........158 DEVID2 (Device ID 2) ..............................................302 Duty Cycle ................................................................154 ECCP1AS (Enhanced Capture/Compare/PWM Effects of a Reset .....................................................163 Auto-Shutdown Control) ..................................161 Enhanced PWM Auto-Shutdown .............................160 ECCP1DEL (PWM Dead-Band Delay) ....................160 Enhanced PWM Mode .............................................153 EECON1 (Data EEPROM Control 1) ...................83, 92 Example Frequencies/Resolutions ..........................154 HLVDCON (High/Low-Voltage Detect Control) .......285 Full-Bridge Application Example ..............................158 INTCON (Interrupt Control) .....................................101 Full-Bridge Mode ......................................................157 INTCON2 (Interrupt Control 2) ................................102 Half-Bridge Mode .....................................................156 INTCON3 (Interrupt Control 3) ................................103 Half-Bridge Output Mode IPR1 (Peripheral Interrupt Priority 1) .......................108 Applications Example ......................................156 IPR2 (Peripheral Interrupt Priority 2) .......................109 Operation in Power-Managed Modes ......................163 OSCCON (Oscillator Control) ....................................33 Operation with Fail-Safe Clock Monitor ...................163 OSCTUNE (Oscillator Tuning) ...................................28 Output Configurations ..............................................154 PIE1 (Peripheral Interrupt Enable 1) .......................106 Output Relationships (Active-High) ..........................155 PIE2 (Peripheral Interrupt Enable 2) .......................107 Output Relationships (Active-Low) ...........................155 PIR1 (Peripheral Interrupt Request (Flag) 1) ...........104 Period .......................................................................153 PIR2 (Peripheral Interrupt Request (Flag) 2) ...........105 Programmable Dead-Band Delay ............................160 PORTE ....................................................................125 Setup for PWM Operation ........................................163 RCON (Reset Control) .......................................46, 110 Start-up Considerations ...........................................162 RCSTA (Receive Status and Control) .....................245 TMR2 to PR2 Match ................................................153 SPPCFG (SPP Configuration) .................................192 SPPCON (SPP Control) ..........................................191 Q SPPEPS (SPP Endpoint Address and Status) ........195 Q Clock ....................................................................149, 154 SSPCON1 (MSSP Control 1, I2C Mode) .................209 SSPCON1 (MSSP Control 1, SPI Mode) ................199 R SSPCON2 (MSSP Control 2, RAM. See Data Memory. I2C Master Mode) ............................................210 RC_IDLE Mode ..................................................................42 SSPCON2 (MSSP Control 2, I2C Slave Mode) .......211 RC_RUN Mode ..................................................................38 SSPSTAT (MSSP Status, I2C Mode) ......................208 RCALL .............................................................................343 SSPSTAT (MSSP Status, SPI Mode) ......................198 RCON Register STATUS ....................................................................73 Bit Status During Initialization ....................................52 STKPTR (Stack Pointer) ............................................61 Reader Response ............................................................434 T0CON (Timer0 Control) .........................................127 Register File .......................................................................67 T1CON (Timer1 Control) .........................................131 Register File Summary ................................................69–72 T2CON (Timer2 Control) .........................................137 T3CON (Timer3 Control) .........................................139 © 2009 Microchip Technology Inc. DS39632E-page 429

PIC18F2455/2550/4455/4550 TXSTA (Transmit Status and Control) .....................244 Typical Connection ..................................................201 UCFG (USB Configuration) ......................................168 SPP. See Streaming Parallel Port. ..................................191 UCON (USB Control) ...............................................166 SS ....................................................................................197 UEIE (USB Error Interrupt Enable) ..........................185 SSPOV ............................................................................232 UEIR (USB Error Interrupt Status) ...........................184 SSPOV Status Flag .........................................................232 UEPn (USB Endpoint n Control) ..............................172 SSPSTAT Register UIE (USB Interrupt Enable) ......................................183 R/W Bit ....................................................................214 UIR (USB Interrupt Status) ......................................181 SSPxSTAT Register USTAT (USB Status) ...............................................171 R/W Bit ....................................................................212 WDTCON (Watchdog Timer Control) .......................304 Stack Full/Underflow Resets ..............................................62 RESET .............................................................................343 STATUS Register ..............................................................73 Reset State of Registers ....................................................52 Streaming Parallel Port ....................................................191 Resets ........................................................................45, 291 Associated Registers ...............................................196 Brown-out Reset (BOR) ...........................................291 Clocking Data ..........................................................192 Oscillator Start-up Timer (OST) ...............................291 Configuration ...........................................................191 Power-on Reset (POR) ............................................291 Internal Pull-ups .......................................................192 Power-up Timer (PWRT) .........................................291 Interrupts .................................................................194 RETFIE ............................................................................344 Microcontroller Control Setup ..................................194 RETLW .............................................................................344 Reading from (Microcontroller Mode) ......................195 RETURN ..........................................................................345 Transfer of Data Between USB SIE Return Address Stack ........................................................60 and SPP (diagram) ..........................................194 and Associated Registers ..........................................60 USB Control Setup ..................................................194 Return Stack Pointer (STKPTR) ........................................61 Wait States ..............................................................192 Revision History ...............................................................419 Writing to (Microcontroller Mode) .............................194 RLCF ................................................................................345 SUBFSR ..........................................................................359 RLNCF .............................................................................346 SUBFWB .........................................................................348 RRCF ...............................................................................346 SUBLW ............................................................................349 RRNCF .............................................................................347 SUBULNK ........................................................................359 SUBWF ............................................................................349 S SUBWFB .........................................................................350 SCK ..................................................................................197 SWAPF ............................................................................350 SDI ...................................................................................197 T SDO .................................................................................197 SEC_IDLE Mode ................................................................41 T0CON Register SEC_RUN Mode ................................................................36 PSA Bit ....................................................................129 Serial Clock, SCK .............................................................197 T0CS Bit ..................................................................128 Serial Data In (SDI) ..........................................................197 T0PS2:T0PS0 Bits ...................................................129 Serial Data Out (SDO) .....................................................197 T0SE Bit ..................................................................128 Serial Peripheral Interface. See SPI Mode. Table Pointer Operations (table) ........................................84 SETF ................................................................................347 Table Reads/Table Writes .................................................62 Slave Select (SS) .............................................................197 TBLRD .............................................................................351 SLEEP ..............................................................................348 TBLWT .............................................................................352 Sleep Time-out in Various Situations (table) ................................49 OSC1 and OSC2 Pin States ......................................34 Timer0 ..............................................................................127 Sleep Mode ........................................................................40 16-Bit Mode Timer Reads and Writes ......................128 Software Simulator (MPLAB SIM) ....................................364 Associated Registers ...............................................129 Special Event Trigger. See Compare (CCP Module). Clock Source Edge Select (T0SE Bit) .....................128 Special Event Trigger. See Compare (ECCP Module). Clock Source Select (T0CS Bit) ...............................128 Special Features of the CPU ............................................291 Operation .................................................................128 Special ICPORT Features ................................................311 Overflow Interrupt ....................................................129 SPI Mode (MSSP) Prescaler .................................................................129 Associated Registers ...............................................206 Switching Assignment .....................................129 Bus Mode Compatibility ...........................................206 Prescaler. See Prescaler, Timer0. Effects of a Reset .....................................................206 Timer1 ..............................................................................131 Enabling SPI I/O ......................................................201 16-Bit Read/Write Mode ..........................................133 Master Mode ............................................................202 Associated Registers ...............................................136 Master/Slave Connection .........................................201 Interrupt ...................................................................134 Operation .................................................................200 Operation .................................................................132 Operation in Power-Managed Modes ......................206 Oscillator ..........................................................131, 133 Serial Clock ..............................................................197 Layout Considerations .....................................134 Serial Data In ...........................................................197 Low-Power Option ...........................................133 Serial Data Out ........................................................197 Using Timer1 as a Clock Source .....................133 Slave Mode ..............................................................204 Overflow Interrupt ....................................................131 Slave Select .............................................................197 Resetting, Using a Special Event Slave Select Synchronization ..................................204 Trigger Output (CCP) ......................................134 SPI Clock .................................................................202 Special Event Trigger (ECCP) .................................152 DS39632E-page 430 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 TMR1H Register ......................................................131 Full-Bridge PWM Output ..........................................157 TMR1L Register .......................................................131 Half-Bridge PWM Output .........................................156 Use as a Real-Time Clock .......................................134 High/Low-Voltage Detect Characteristics ................384 Timer2 ..............................................................................137 High-Voltage Detect (VDIRMAG = 1) ......................288 Associated Registers ...............................................138 I2C Bus Data ............................................................397 Interrupt ....................................................................138 I2C Bus Start/Stop Bits ............................................397 Operation .................................................................137 I2C Master Mode (7 or 10-Bit Transmission) ...........233 Output ......................................................................138 I2C Master Mode (7-Bit Reception) .........................234 PR2 Register ....................................................148, 153 I2C Slave Mode (10-Bit Reception, TMR2 to PR2 Match Interrupt ..........................148, 153 SEN = 0, ADMSK 01001) ................................219 Timer3 ..............................................................................139 I2C Slave Mode (10-Bit Reception, SEN = 0) ..........218 16-Bit Read/Write Mode ...........................................141 I2C Slave Mode (10-Bit Reception, SEN = 1) ..........224 Associated Registers ...............................................141 I2C Slave Mode (10-Bit Transmission) ....................220 Operation .................................................................140 I2C Slave Mode (7-bit Reception, Oscillator ..........................................................139, 141 SEN = 0, ADMSK = 01011) .............................216 Overflow Interrupt ............................................139, 141 I2C Slave Mode (7-Bit Reception, SEN = 0) ............215 Special Event Trigger (CCP) ....................................141 I2C Slave Mode (7-Bit Reception, SEN = 1) ............223 TMR3H Register ......................................................139 I2C Slave Mode (7-Bit Transmission) ......................217 TMR3L Register .......................................................139 I2C Slave Mode General Call Address Timing Diagrams Sequence (7 or 10-Bit Address Mode) ............225 A/D Conversion ........................................................404 Low-Voltage Detect (VDIRMAG = 0) .......................287 Acknowledge Sequence ..........................................235 Master SSP I2C Bus Data .......................................399 Asynchronous Reception (TXCKP = 0, Master SSP I2C Bus Start/Stop Bits ........................399 TX Not Inverted) ..............................................257 PWM Auto-Shutdown (PRSEN = 0, Asynchronous Transmission (TXCKP = 0, Auto-Restart Disabled) ....................................162 TX Not Inverted) ..............................................254 PWM Auto-Shutdown (PRSEN = 1, Asynchronous Transmission, Back to Back Auto-Restart Enabled) .....................................162 (TXCKP = 0, TX Not Inverted) .........................254 PWM Direction Change ...........................................159 Automatic Baud Rate Calculation ............................252 PWM Direction Change at Near Auto-Wake-up Bit (WUE) During 100% Duty Cycle .............................................159 Normal Operation ............................................258 PWM Output ............................................................148 Auto-Wake-up Bit (WUE) During Sleep ...................258 Repeated Start Condition ........................................231 Baud Rate Generator with Clock Arbitration ............229 Reset, Watchdog Timer (WDT), Oscillator Start-up BRG Overflow Sequence .........................................252 Timer (OST) and Power-up Timer (PWRT) .....390 BRG Reset Due to SDA Arbitration During Send Break Character Sequence ............................259 Start Condition .................................................238 Slave Synchronization .............................................204 Brown-out Reset (BOR) ...........................................390 Slow Rise Time (MCLR Tied to VDD, Bus Collision During a Repeated Start VDD Rise > TPWRT) ............................................51 Condition (Case 1) ...........................................239 SPI Mode (Master Mode) ........................................203 Bus Collision During a Repeated Start SPI Mode (Slave Mode with CKE = 0) .....................205 Condition (Case 2) ...........................................239 SPI Mode (Slave Mode with CKE = 1) .....................205 Bus Collision During a Start Condition SPP Write Address and Data for USB (SCL = 0) .........................................................238 (4 Wait States) .................................................193 Bus Collision During a Start Condition SPP Write Address and Read Data for (SDA Only) .......................................................237 USB (4 Wait States) ........................................193 Bus Collision During a Stop Condition SPP Write Address, Write and Read (Case 1) ...........................................................240 Data (No Wait States) ......................................193 Bus Collision During a Stop Condition Stop Condition Receive or Transmit Mode ..............235 (Case 2) ...........................................................240 Streaming Parallel Port (PIC18F4455/4550) ...........403 Bus Collision for Transmit and Acknowledge ...........236 Synchronous Reception (Master Mode, SREN) ......262 Capture/Compare/PWM (All CCP Modules) ............392 Synchronous Transmission .....................................260 CLKO and I/O ..........................................................389 Synchronous Transmission (Through TXEN) ..........261 Clock Synchronization .............................................222 Time-out Sequence on POR w/PLL Enabled Clock/Instruction Cycle ..............................................63 (MCLR Tied to VDD) ..........................................51 EUSART Synchronous Receive Time-out Sequence on Power-up (Master/Slave) .................................................401 (MCLR Not Tied to VDD), Case 1 ......................50 EUSART Synchronous Transmission Time-out Sequence on Power-up (Master/Slave) .................................................401 (MCLR Not Tied to VDD), Case 2 ......................50 Example SPI Master Mode (CKE = 0) .....................393 Time-out Sequence on Power-up Example SPI Master Mode (CKE = 1) .....................394 (MCLR Tied to VDD, VDD Rise TPWRT) ..............50 Example SPI Slave Mode (CKE = 0) .......................395 Timer0 and Timer1 External Clock ..........................391 Example SPI Slave Mode (CKE = 1) .......................396 Transition for Entry to Idle Mode ...............................41 External Clock (All Modes Except PLL) ...................387 Transition for Entry to SEC_RUN Mode ....................37 Fail-Safe Clock Monitor ............................................307 Transition for Entry to Sleep Mode ............................40 First Start Bit Timing ................................................230 © 2009 Microchip Technology Inc. DS39632E-page 431

PIC18F2455/2550/4455/4550 Transition for Two-Speed Start-up Buffer Descriptors ....................................................174 (INTOSC to HSPLL) .........................................305 Address Validation ...........................................177 Transition for Wake From Idle to Run Mode ..............41 Assignment in Different Buffering Modes ........179 Transition for Wake from Sleep (HSPLL) ...................40 BDnSTAT Register (CPU Mode) .....................175 Transition From RC_RUN Mode to BDnSTAT Register (SIE Mode) .......................177 PRI_RUN Mode .................................................39 Byte Count .......................................................177 Transition from SEC_RUN Mode to Example ...........................................................174 PRI_RUN Mode (HSPLL) ..................................37 Memory Map ....................................................178 Transition to RC_RUN Mode .....................................39 Ownership .......................................................174 USB Signal ...............................................................402 Ping-Pong Buffering ........................................178 Timing Diagrams and Specifications ................................387 Register Summary ...........................................179 Capture/Compare/PWM Requirements Status and Configuration .................................174 (All CCP Modules) ...........................................392 Class Specifications and Drivers .............................190 CLKO and I/O Requirements ...................................389 Descriptors ...............................................................190 EUSART Synchronous Receive Endpoint Control ......................................................172 Requirements ...................................................401 Enumeration ............................................................190 EUSART Synchronous Transmission External Pull-up Resistors .......................................169 Requirements ...................................................401 External Transceiver ................................................167 Example SPI Mode Requirements Eye Pattern Test Enable ..........................................169 (Master Mode, CKE = 0) ..................................393 Firmware and Drivers ..............................................187 Example SPI Mode Requirements Frame Number Registers ........................................173 (Master Mode, CKE = 1) ..................................394 Frames ....................................................................189 Example SPI Mode Requirements Internal Pull-up Resistors .........................................169 (Slave Mode, CKE = 0) ....................................395 Internal Transceiver .................................................167 Example SPI Mode Requirements Internal Voltage Regulator .......................................170 (Slave Mode, CKE = 1) ....................................396 Interrupts .................................................................180 External Clock Requirements ..................................387 and USB Transactions .....................................180 I2C Bus Data Requirements (Slave Mode) ..............398 Layered Framework .................................................189 I2C Bus Start/Stop Bits Requirements .....................397 Oscillator Requirements ..........................................187 Master SSP I2C Bus Data Requirements ................400 Output Enable Monitor .............................................169 Master SSP I2C Bus Start/Stop Bits Overview ..........................................................165, 189 Requirements ...................................................399 Ping-Pong Buffer Configuration ...............................169 PLL Clock .................................................................388 Power ......................................................................189 Reset, Watchdog Timer, Oscillator Start-up Power Modes ...........................................................186 Timer, Power-up Timer and Bus Power Only ...............................................186 Brown-out Reset Requirements .......................390 Dual Power with Self-Power Dominance .........186 Streaming Parallel Port Requirements Self-Power Only ...............................................186 (PIC18F4455/4550) .........................................403 RAM .........................................................................173 Timer0 and Timer1 External Clock Memory Map ....................................................173 Requirements ...................................................391 Speed ......................................................................190 USB Full-Speed Requirements ................................402 Status and Control ...................................................166 USB Low-Speed Requirements ...............................402 Transfer Types .........................................................189 Top-of-Stack Access ..........................................................60 UFRMH:UFRML Registers ......................................173 TQFP Packages and Special Features ............................311 USB. See Universal Serial Bus. TSTFSZ ............................................................................353 V Two-Speed Start-up .................................................291, 305 Two-Word Instructions Voltage Reference Specifications ....................................382 Example Cases ..........................................................64 W TXSTA Register BRGH Bit .................................................................247 Watchdog Timer (WDT) ...........................................291, 303 Associated Registers ...............................................304 U Control Register .......................................................303 Universal Serial Bus ...........................................................65 During Oscillator Failure ..........................................306 Address Register (UADDR) .....................................173 Programming Considerations ..................................303 and Streaming Parallel Port .....................................187 WCOL ......................................................230, 231, 232, 235 Associated Registers ...............................................187 WCOL Status Flag ...................................230, 231, 232, 235 Buffer Descriptor Table ............................................174 WWW Address ................................................................433 WWW, On-Line Support ......................................................5 X XORLW ............................................................................353 XORWF ...........................................................................354 DS39632E-page 432 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS39632E-page 433

PIC18F2455/2550/4455/4550 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City/State/ZIP/Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F2455/2550/4455/4550 Literature Number: DS39632E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39632E-page 434 © 2009 Microchip Technology Inc.

PIC18F2455/2550/4455/4550 PIC18F2455/2550/4455/4550 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18LF4550-I/P 301 = Industrial temp., PDIP Range package, Extended VDD limits, QTP pattern #301. b) PIC18LF2455-I/SO = Industrial temp., SOIC package, Extended VDD limits. Device PIC18F2455/2550(1), PIC18F4455/4550(1), c) PIC18F4455-I/P = Industrial temp., PDIP PIC18F2455/2550T(2), PIC18F4455/4550T(2); package, normal VDD limits. VDD range 4.2V to 5.5V PIC18LF2455/2550(1), PIC18LF4455/4550(1), PIC18LF2455/2550T(2), PIC18LF4455/4550T(2); VDD range 2.0V to 5.5V Temperature Range I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package PT = TQFP (Thin Quad Flatpack) Note1: F = Standard Voltage Range SO = SOIC SP = Skinny Plastic DIP LF = Wide Voltage Range P = PDIP 2: T = in tape and reel TQFP ML = QFN packages only. Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) © 2009 Microchip Technology Inc. DS39632E-page 435

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18F4455-I/P PIC18F2455T-I/SO PIC18LF4550T-I/PT PIC18F2550T-I/SO PIC18F2455-I/SO PIC18LF4550T- I/ML PIC18F4455T-I/ML PIC18F2455-I/SP PIC18LF4455T-I/PT PIC18LF4550-I/PT PIC18LF4455T-I/ML PIC18LF2550T-I/SO PIC18F4550T-I/ML PIC18F4550T-I/PT PIC18LF2455T-I/SO PIC18LF4550-I/ML PIC18LF2455- I/SO PIC18LF2455-I/SP PIC18F4550-I/PT PIC18F4550-I/ML PIC18F2550-I/SP PIC18F2550-I/SO PIC18LF4455- I/ML PIC18LF4455-I/PT PIC18F4455-I/ML PIC18F4455-I/PT PIC18LF2550-I/SO PIC18LF2550-I/SP PIC18LF4455- I/P PIC18LF4550-I/P PIC18F4455T-I/PT PIC18F4550-I/P