PIC18(L)F2X/45K50 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology Universal Serial Bus Features: • Digital-to-Analog Converter (DAC) module: - Fixed Voltage Reference (FVR) with 1.024V, • USB V2.0 Compliant 2.048V and 4.096V output levels • Crystal-less Full Speed (12 Mb/s) and Low-Speed - 5-bit rail-to-rail resistive DAC with positive Operation (1.5 Mb/s) and negative reference selection • Supports Control, Interrupt, Isochronous and Bulk • High/Low-Voltage Detect module Transfers • Charge Time Measurement Unit (CTMU): • Supports up to 32 Endpoints (16 Bidirectional) - Supports capacitive touch sensing for touch • 1 Kbyte Dual Access RAM for USB screens and capacitive switches • On-Chip USB Transceiver • Enhanced USART module: Flexible Oscillator Structure: - Supports RS-485, RS-232 and LIN/J2602 - Auto-wake-up on Start bit • 3x and 4xPLL Clock Multipliers - Auto-Baud Detect • Two External Clock modes, Up to 48 MHz (12 Extreme Low-Power Management with MIPS) XLP: • Internal 31 kHz Oscillator • Internal Oscillator, 31 kHz to 16 MHz • Sleep mode: 20 nA, typical - Factory calibrated to ± 1% • Watchdog Timer: 300 nA, typical - Self-tune to ± 0.20% max. from USB or • Timer1 Oscillator: 800 nA @ 32 kHz secondary oscillator • Peripheral Module Disable • Secondary Oscillator using Timer1 @ 32 kHz Special Microcontroller Features: • Fail-Safe Clock Monitor: - Allows for safe shutdown if any clock stops • Low-Power, High-Speed CMOS Flash Technology • C Compiler Optimized Architecture for Re-Entrant Peripheral Highlights: Code • Power Management Features: • Up to 33 I/O pins plus 3 Input-Only Pins: - Run: CPU on, peripherals on, SRAM on - High-current Sink/Source 25 mA/25 mA - Idle: CPU off, peripherals on, SRAM on - Three programmable external interrupts - Sleep: CPU off, peripherals off, SRAM on - 11 programmable interrupts-on-change • Priority Levels for Interrupts - Nine programmable weak pull-ups • Self-Programmable under Software Control - Programmable slew rate • 8 x 8 Single-Cycle Hardware Multiplier • SR Latch • Extended Watchdog Timer (WDT): • Enhanced Capture/Compare/PWM (ECCP) - Programmable period from 4 ms to 131s module: • Single-Supply In-Circuit Serial Programming™ - One, two or four PWM outputs (ICSP™) via Two Pins - Selectable polarity • In-Circuit Debug (ICD) with Three Breakpoints via - Programmable dead time Two Pins - Auto-shutdown and auto-restart • Optional dedicated ICD/ICSP Port (44-pin TQFP - Pulse steering control Package Only) • Capture/Compare/PWM (CCP) module • Wide Operating Voltage Range: • Master Synchronous Serial Port (MSSP) module - F devices: 2.3V to 5.5V Supporting 3-Wire SPI (all four modes) and I2C™ - LF devices: 1.8V to 3.6V Master and Slave modes • Flash Program Memory of 10,000 Erase/Write • Two Analog Comparators with Input Multiplexing Cycles Minimum and 20-year Data Retention • 10-Bit Analog-to-Digital (A/D) Converter module: - Up to 25 input channels - Auto-acquisition capability - Conversion available during Sleep  2012-2014 Microchip Technology Inc. DS30000684B-page 1

PIC18(L)F2X/45K50 PIC18(L)F2X/45K50 Family Types Device (PFblyraotseghsr )amSIn iMnstgerlumec-Wtoioroynrsd (SbRyDtAaeMtsa) MEe(EmbDPyoaRtretayOs )M Pins I/O 10-Bit A/DChannels omparators CCP/ECCP BOR/LVD CTMU MSSP EUSART Timers8-bit/16-bit USB 2.0 C PIC18(L)F45K50 32K 16384 2048 256 40/44 36 25-ch 2 1/1 Yes Yes 1 1 2/2 Yes PIC18(L)F25K50 32K 16384 2048 256 28 25 14-ch 2 1/1 Yes Yes 1 1 2/2 Yes PIC18(L)F24K50 16K 8192 2048 256 28 25 14-ch 2 1/1 Yes Yes 1 1 2/2 Yes Pin Diagrams FIGURE 1: 28-PIN SPDIP (300 MIL), SOIC, SSOP MCLR/VPP/RE3 1 28 RB7 RA0 2 27 RB6 RA1 3 26 RB5 RA2 4 0 25 RB4 RA3 5 K5 24 RB3 RA4 6 X 23 RB2 2 RA5 7 F 22 RB1 VSS 8 L) 21 RB0 ( RA7 9 8 20 VDD 1 RA6 10 C 19 VSS RC0 11 PI 18 RC7 RC1 12 17 RC6 RC2 13 16 D+ VUSB3V3 14 15 D- FIGURE 2: 28-PIN QFN 3 E R /P P V R/ A1A0CLB7B6B5B4 RRMRRRR 8765432 2222222 RA2 1 21 RB3 RA3 2 20 RB2 RA4 3 19 RB1 PIC18(L)F2XK50 RA5 4 18 RB0 VSS 5 17 VDD RA7 6 16 VSS RA6 7 15 RC7 891011121314 RC0RC1RC233BVD-D+RC6 S U V Note: For the QFN package, it is recommended that the bottom pad be connected to VSS. DS30000684B-page 2  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 3: 40-PIN PDIP (600 MIL) MCLR/VPP/RE3 1 40 RB7 RA0 2 39 RB6 RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 7 0 34 RB1 RE0 8 K5 33 RB0 RE1 9 5 32 VDD 4 RE2 10 F 31 VSS VDD 11 L) 30 RD7 VSS 12 8( 29 RD6 1 RA7 13 C 28 RD5 RA6 14 PI 27 RD4 RC0 15 26 RC7 RC1 16 25 RC6 RC2 17 24 D+ VUSB3V3 18 23 D- RD0 19 22 RD3 RD1 20 21 RD2 FIGURE 4: 40-PIN UQFN 3 V 3 RC6D+D-RD3RD2RD1RD0VUSBRC2RC1 0987654321 4333333333 RC7 1 30 RC0 RD4 2 29 RA6 RD5 3 28 RA7 RD6 4 27 VSS RD7 5 PIC18(L)F45K50 26 VDD VSS 6 25 RE2 VDD 7 24 RE1 RB0 8 23 RE0 RB1 9 22 RA5 RB2 10 21 RA4 11121314151617181920 3456730123 BBBBBEAAAA RRRRRRRRRR /P P V R/ L C M Note: For the UQFN package, it is recommended that the bottom pad be connected to VSS.  2012-2014 Microchip Technology Inc. DS30000684B-page 3

PIC18(L)F2X/45K50 FIGURE 5: 44-PIN TQFP 3 V 3 RC6D+D-RD3RD2RD1RD0VUSBRC2RC1NC 43210987654 RC7 14444433333333 NC/ICRST(1)/ICVPP(1) RD4 2 32 RC0 RD5 3 31 RA6 RD6 4 30 RA7 RD7 5 29 VSS PIC18(L)F45K50 VSS 6 28 VDD VDD 7 27 RE2 RB0 8 26 RE1 RB1 9 25 RE0 RB2 10 24 RA5 RB3 11 23 RA4 23456789012 11111111222 (1)CPGC(1)CPGDRB4RB5RB6RB7V/RE3PPRA0RA1RA2RA3 (1)K/I(1)T/I /CLR CD M CC C/IC/I NN Note 1: Special ICPORT programming/debug port features available when ICPRT=1 DS30000684B-page 4  2012-2014 Microchip Technology Inc.

 2 0 TABLE 1: PIC18(L)F2X/45K50 PIN SUMMARY 1 2 -2 P 0 O 1 S 4 Microchip Tech I/O n SPDIP/SOIC/S 28-Pin QFN 40-Pin PDIP 40-Pin UQFN 44-Pin TQFP Analog Comparator CTMU SR Latch Reference USB (E)CCP EUSART MSSP Timers Interrupts Pull-up Basic ICD no Pi lo 8- g 2 y In RA0 2 27 2 17 19 AN0 C12IN0- — — — — — — — — — — — — c . RA1 3 28 3 18 20 AN1 C12IN1- CTCMP — — — — — — — — — — — RA2 4 1 4 19 21 AN2 C2IN+ — — VREF- — — — — — — — — — DACOUT RA3 5 2 5 20 22 AN3 C1IN+ — — VREF+ — — — — — — — — — RA4 6 3 6 21 23 — C1OUT — SRQ — — — — — T0CKI — — — — RA5 7 4 7 22 24 AN4 C2OUT SRNQ HLVDIN — — — SS — — — — — RA6 10 7 14 29 31 — — — — — — — — — — — — OSC2 — CLKO RA7 9 6 13 28 30 — — — — — — — — — — — — OSC1 — CLKI RB0 21 18 33 8 8 AN12 — — SRI — — FLT0 — SDI — INT0 Y — — P SDA I RB1 22 19 34 9 9 AN10 C12IN3- — — — — P1C(5) — SCK — INT1 Y — — C SCL 1 RB2 23 20 35 10 10 AN8 — CTED1 — — — P1B(5) — — — INT2 Y — — 8 RB3 24 21 36 11 11 AN9 C12IN2- CTED2 — — — CCP2(1) — SDO — — — — — ( RB4 25 22 37 12 14 AN11 — — — — — P1D(5) — — — IOCB4 Y — — L RB5 26 23 38 13 15 AN13 — — — — — — — — T1G IOCB5 — — — ) F T3CKI(2) 2 RB6 27 24 39 14 16 — — — — — — — — — — IOCB6 Y PGC — X D Note 1: Alternate CCP2 pin location based on Configuration bit. S 3 2: Alternate T3CKI pin location based on Configuration bits. / 0 4 0 3: Pins are enabled when ICPRT =1, otherwise, they are disabled. 00 4: Location on 40/44-Pin parts (PIC18(L)F45K50). Function not on this pin on 28-Pin parts (PIC18(L)F2XK50). 5 6 84 5: Location on 28-Pin parts (PIC18(L)F2XK50). Function not on this pin on 40/44-Pin parts (PIC18(L)F45K50). K B -p 6: Alternate SDO pin location based on Configuration bits. 5 a 7: RE3 can be used for digital input only (no output functionality). g e 0 5

D TABLE 1: PIC18(L)F2X/45K50 PIN SUMMARY (CONTINUED) P S 3 0 P I 0 O C 006 SS 84B-page 6 I/O Pin SPDIP/SOIC/ 28-Pin QFN 40-Pin PDIP 40-Pin UQFN 44-Pin TQFP Analog Comparator CTMU SR Latch Reference USB (E)CCP EUSART MSSP Timers Interrupts Pull-up Basic ICD 18(L)F 8- 2 2 RB7 28 25 40 15 17 — — — — — — — — — — IOCB7 Y PGD — X RC0 11 8 15 30 32 — — — — — — — — — SOSCO IOCC0 — — — / 4 T1CKI T3CKI 5 T3G K RC1 12 9 16 31 35 — — — — — — CCP2 — — SOSCI IOCC1 — — — 5 RC2 13 10 17 32 36 AN14 — CTPLS — — — CCP1 — — — IOCC2 — — — 0 P1A — 14 11 18 33 37 — — — — — VUSB3V3 — — — — — — VDDCORE — — 15 12 23 38 42 — — — — — D- — — — — IOCC4 — — — — 16 13 24 39 43 — — — — — D+ — — — — IOCC5 — — — RC6 17 14 25 40 44 AN18 — — — — — — TX — — IOCC6 — — — CK RC7 18 15 26 1 1 AN19 — — — — — — RX SDO(6) — IOCC7 — — — DT RD0 — — 19 34 38 AN20 — — — — — — — — — — — — — RD1 — — 20 35 39 AN21 — — — — — — — — — — — — — RD2 — — 21 36 40 AN22 — — — — — — — — — — — — —  2 RD3 — — 22 37 41 AN23 — — — — — — — — — — — — — 0 12 RD4 — — 27 2 2 AN24 — — — — — — — — — — — — — -20 RD5 — — 28 3 3 AN25 — — — — — P1B(4) — — — — — — — 1 4 M RD6 — — 29 4 4 AN26 — — — — — P1C(4) — — — — — — — icro RD7 — — 30 5 5 AN27 — — — — — P1D(4) — — — — — — — c h Note 1: Alternate CCP2 pin location based on Configuration bit. ip T 2: Alternate T3CKI pin location based on Configuration bits. ec 3: Pins are enabled when ICPRT =1, otherwise, they are disabled. h n 4: Location on 40/44-Pin parts (PIC18(L)F45K50). Function not on this pin on 28-Pin parts (PIC18(L)F2XK50). o lo 5: Location on 28-Pin parts (PIC18(L)F2XK50). Function not on this pin on 40/44-Pin parts (PIC18(L)F45K50). g y 6: Alternate SDO pin location based on Configuration bits. In 7: RE3 can be used for digital input only (no output functionality). c .

 TABLE 1: PIC18(L)F2X/45K50 PIN SUMMARY (CONTINUED) 2 0 P 12 O -20 SS 14 Microchip T I/O n SPDIP/SOIC/ 28-Pin QFN 40-Pin PDIP 40-Pin UQFN 44-Pin TQFP Analog Comparator CTMU SR Latch Reference USB (E)CCP EUSART MSSP Timers Interrupts Pull-up Basic ICD ec Pi hn 8- o 2 lo g RE0 — — 8 23 25 AN5 — — — — — — — — — — — — — y In RE1 — — 9 24 26 AN6 — — — — — — — — — — — — — c . RE2 — — 10 25 27 AN7 — — — — — — — — — — — — — RE3(7) 1 26 1 16 18 — — — — — — — — — — — Y MCLR — VPP — 20 17 11, 7, 7, — — — — — — — — — — — — VDD — 32 26 28 — 8, 5, 12, 6, 6, — — — — — — — — — — — — VSS — 19 16 31 27 29 — — — – –- 12(3) — — — — — — — — — — — — ICPGC(3) ICCK(3) — — — – –- 13(3) — — — — — — — — — — — — ICPGD(3) ICDT(3) — — — –- –- 33(3) — — — — — — — — — — — — ICVPP(3) ICRST(3) P Note 1: Alternate CCP2 pin location based on Configuration bit. 2: Alternate T3CKI pin location based on Configuration bits. I 3: Pins are enabled when ICPRT =1, otherwise, they are disabled. C 4: Location on 40/44-Pin parts (PIC18(L)F45K50). Function not on this pin on 28-Pin parts (PIC18(L)F2XK50). 1 5: Location on 28-Pin parts (PIC18(L)F2XK50). Function not on this pin on 40/44-Pin parts (PIC18(L)F45K50). 8 6: Alternate SDO pin location based on Configuration bits. 7: RE3 can be used for digital input only (no output functionality). ( L ) F 2 X D S 3 / 0 4 0 00 5 6 84 K B -p 5 a g e 0 7

PIC18(L)F2X/45K50 Table of Contents 1.0 Device Overview....................................................................................................................................................................... 10 2.0 Guidelines for Getting Started with PIC18(L)F2X/45K50 Microcontrollers................................................................................ 23 3.0 Oscillator Module (With Fail-Safe Clock Monitor)...................................................................................................................... 28 4.0 Power-Managed Modes............................................................................................................................................................ 52 5.0 Reset......................................................................................................................................................................................... 63 6.0 Memory Organization................................................................................................................................................................ 73 7.0 Flash Program Memory............................................................................................................................................................. 95 8.0 Data EEPROM Memory.......................................................................................................................................................... 104 9.0 8 x 8 Hardware Multiplier......................................................................................................................................................... 109 10.0 Interrupts.................................................................................................................................................................................. 111 11.0 I/O Ports.................................................................................................................................................................................. 128 12.0 Timer0 Module......................................................................................................................................................................... 153 13.0 Timer1/3 Module with Gate Control......................................................................................................................................... 156 14.0 Timer2 Module......................................................................................................................................................................... 168 15.0 Capture/Compare/PWM Modules............................................................................................................................................ 172 16.0 Master Synchronous Serial Port (MSSP) Module................................................................................................................... 203 17.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART).............................................................. 258 18.0 Analog-to-Digital Converter (ADC) Module............................................................................................................................. 287 19.0 Comparator Module................................................................................................................................................................. 301 20.0 Charge Time Measurement Unit (CTMU)................................................................................................................................ 310 21.0 SR Latch.................................................................................................................................................................................. 325 22.0 Fixed Voltage Reference (FVR)............................................................................................................................................... 330 23.0 Digital-to-Analog Converter (DAC) Module............................................................................................................................. 332 24.0 Universal Serial Bus (USB)..................................................................................................................................................... 336 25.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................ 364 26.0 Special Features of the CPU................................................................................................................................................... 370 27.0 Instruction Set Summary......................................................................................................................................................... 390 28.0 Development Support.............................................................................................................................................................. 440 29.0 Electrical Specifications........................................................................................................................................................... 444 30.0 DC and AC Characteristics Graphs and Charts...................................................................................................................... 485 31.0 Packaging Information............................................................................................................................................................. 486 Appendix A: Revision History............................................................................................................................................................ 503 Appendix B: Device Differences........................................................................................................................................................ 504 The Microchip Web Site.................................................................................................................................................................... 505 Customer Change Notification Service............................................................................................................................................. 505 Customer Support............................................................................................................................................................................. 505 Product Identification System............................................................................................................................................................ 506 DS30000684B-page 8  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2012-2014 Microchip Technology Inc. DS30000684B-page 9

PIC18(L)F2X/45K50 1.0 DEVICE OVERVIEW 1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES This document contains device-specific information for the following devices: All of the devices in the PIC18(L)F2X/45K50 family offer ten different oscillator options, allowing users a • PIC18(L)F45K50 wide range of choices in developing application • PIC18(L)F25K50 hardware. These include: • PIC18(L)F24K50 • Four Crystal modes, using crystals or ceramic resonators This family offers the advantages of all PIC18 microcontrollers – namely, high computational • Six External Clock modes, offering the option of performance at an economical price – with the addition using two pins (oscillator input and a divide-by- of high-endurance, Flash program memory. On top of four clock output) or one pin (oscillator input, with these features, the PIC18(L)F2X/45K50 family the second pin reassigned as general I/O) introduces design enhancements that make these • Two External RC Oscillator modes with the same microcontrollers a logical choice for many pin options as the External Clock modes high-performance, power sensitive applications. • An internal oscillator block which contains a 16MHz HFINTOSC oscillator and a 31kHz 1.1 New Core Features INTRC oscillator, which together provide eight user selectable clock frequencies, from 31kHz to 1.1.1 XLP TECHNOLOGY 16MHz. This option frees the two oscillator pins All of the devices in the PIC18(L)F2X/45K50 family for use as additional general purpose I/O. incorporate a range of features that can significantly • 3x and 4x Phase Lock Loop (PLL) frequency reduce power consumption during operation. Key multipliers, available to both external and internal items include: oscillator modes, which allows clock speeds of up to 48MHz. Used with the internal oscillator, the • Alternate Run Modes: By clocking the controller PLL gives users a complete selection of clock from the Timer1 source or the internal oscillator speeds, from 31kHz to 48MHz – all without using block, power consumption during code execution an external crystal or clock circuit. can be reduced by as much as 90%. • Multiple Idle Modes: The controller can also run Besides its availability as a clock source, the internal with its CPU core disabled but the peripherals still oscillator block provides a stable reference source that active. In these states, power consumption can be gives the family additional features for robust reduced even further, to as little as 4% of normal operation: operation requirements. • Active Clock Tuning: This option allows the • Peripheral Module Disable bits: User code can internal oscillator to automatically tune itself to power down individual peripheral modules during match USB host or external 32.768 kHz Run and Idle modes for further lowering dynamic secondary oscillator clock sources. Full-speed power reduction. USB operation can now meet specification • On-the-fly Mode Switching: The power- requirements without an external crystal, enabling managed modes are invoked by user code during lower-cost designs. operation, allowing the user to incorporate • Fail-Safe Clock Monitor: This option constantly power-saving ideas into their application’s monitors the main clock source against a software design. reference signal provided by the INTRC. If a clock • Low Consumption in Key Modules: The power failure occurs, the controller is switched to the requirements for both Timer1 and the Watchdog internal oscillator block, allowing for continued Timer are minimized. See Section29.0 “Electri- operation or a safe application shutdown. cal Specifications” for values. • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source 1.1.2 UNIVERSAL SERIAL BUS (USB) from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. Devices in the PIC18(L)F2X/45K50 family incorporate a fully-featured USB communications module with a built-in transceiver that is compliant with the USB Specification Revision 2.0. The module supports both low-speed and full-speed communication for all supported data transfer types. The device incorporates its own on-chip transceiver and 3.3V regulator for USB. DS30000684B-page 10  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 1.2 Other Special Features • Charge Time Measurement Unit (CTMU): The CTMU is a flexible analog module that provides • Memory Endurance: The Flash cells for both accurate differential time measurement between program memory and data EEPROM are rated to pulse sources, as well as asynchronous pulse last for many thousands of erase/write cycles – up to generation. Together with other on-chip analog 10K for program memory and 100K for EEPROM. modules, the CTMU can precisely measure time, Data retention without refresh is conservatively measure capacitance or relative changes in estimated to be greater than 40 years. capacitance or generate output pulses that are • Self-Programmability: These devices can write independent of the system clock. to their own program memory spaces under • SR Latch Output: A single SR latch with multiple internal software control. By using a bootloader Set and Reset inputs as well as separate latch routine located in the protected Boot Block at the outputs. top of program memory, it becomes possible to create an application that can update itself in the 1.3 Details on Individual Family field. Members • Extended Instruction Set: The PIC18(L)F2X/ 45K50 family introduces an optional extension to Devices in the PIC18(L)F2X/45K50 family are available the PIC18 instruction set, which adds eight new in 28-pin and 40/44-pin packages. The block diagram instructions and an Indexed Addressing mode. for the device family is shown in Figure1-1. This extension, enabled as a device configuration The devices have the following differences: option, has been specifically designed to optimize 1. Flash program memory re-entrant application code originally developed in 2. A/D channels high-level languages, such as C. 3. I/O ports • Enhanced CCP module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for 4. Input Voltage Range/Power Consumption controlling half-bridge and full-bridge drivers. All other features for devices in this family are identical. Other features include: These are summarized in Table1-1. - Auto-shutdown, for disabling PWM outputs The pinouts for all devices are listed in the pin summary on interrupt or other select conditions table (Table1) and I/O description tables (Table1-2 - Auto-restart, to reactivate outputs once the and Table1-3). condition has cleared - Output steering to selectively enable one or more of four outputs to provide the PWM signal. • Enhanced Addressable EUSART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. • Dedicated ICD/ICSP™ Port: These devices introduce the use of debugger and programming pins that are not multiplexed with other microcontroller features. Offered as an option in the TQFP packaged devices, this feature allows users to develop I/O intensive applications while retaining the ability to program and debug in the circuit.  2012-2014 Microchip Technology Inc. DS30000684B-page 11

PIC18(L)F2X/45K50 TABLE 1-1: DEVICE FEATURES Features PIC18(L)F24K50 PIC18(L)F25K50 PIC18(L)F45K50 Program Memory (Bytes) 16384 32768 32768 Program Memory (Instructions) 8192 16384 16384 Data Memory (Bytes) 2048 2048 2048 Data EEPROM Memory (Bytes) 256 256 256 I/O Ports A, B, C, E(1) A, B, C, E(1) A, B, C, D, E Capture/Compare/PWM Modules 1 1 1 (CCP) Enhanced CCP Modules (ECCP) 1 1 1 10-bit Analog-to-Digital Module 3 internal 3 internal 3 internal (ADC) 14 input 14 input 25 input Packages 28-pin SPDIP 28-pin SPDIP 40-pin PDIP 28-pin SOIC 28-pin SOIC 40-pin UQFN 28-pin SSOP 28-pin SSOP 44-pin TQFP 28-pin QFN 28-pin QFN Interrupt Sources 25 Timers (16-bit) 2 Serial Communications MSSP, EUSART SR Latch Yes Charge Time Measurement Unit Yes Module (CTMU) Programmable Yes High/Low-Voltage Detect (HLVD) Programmable Brown-out Reset Yes (BOR) Resets (and Delays) POR, BOR, LPBOR RESET Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT Instruction Set 75 Instructions; 83 with Extended Instruction Set enabled Operating Frequency DC – 48 MHz Note 1: PORTE contains the single RE3 read-only bit. DS30000684B-page 12  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 1-1: PIC18(L)F2X/45K50 FAMILY BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 8 Data Latch inc/dec logic Data Memory 21 PCLAT U PCLATH 20 Address Latch PORTA PCU PCH PCL RA0:RA7 Program Counter 12 Data Address<12> 31-Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (16/32Kbytes) FSR1 PORTB Data Latch FSR2 12 RB0:RB7 inc/dec 8 logic Table Latch Address ROM Latch Instruction Bus <16> Decode PORTC RC0:RC3 IR RC6:RC7 8 Instruction State machine Decode and control signals Control PRODH PRODL PORTD 8 x 8 Multiply RD0:RD7 3 8 BITOP W 8 8 8 OSC1(2) Internal Power-up Oscillator Timer 8 8 Block PORTE OSC2(2) Oscillator ALU<8> INTRC Start-up Timer RE0:RE2 SOSCI Oscillator Power-on 8 RE3(1) Reset 16 MHz SOSCO Oscillator Watchdog Timer MCLR(1) Single-Supply Brown-out BParencdi sGioanp FVR Programming Reset Reference In-Circuit Fail-Safe Debugger Clock Monitor HBLOVRD EEDPaRtaOM Timer0 TTiimmeerr13 Timer2 CTMU DAC FVR FVR Comparators ECCP1 USB MSSP EUSART SR Latch ADC DAC C1/C2 CCP2 10-bit DAC Note 1: RE3 is only available when MCLR functionality is disabled. 2: OSC1/CLKIN and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section6.0 “Memory Organization” for additional information.  2012-2014 Microchip Technology Inc. DS30000684B-page 13

PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer SPDIP, Pin Name Description Type Type SOIC, QFN SSOP 2 27 RA0/C12IN0-/AN0 RA0 I/O TTL/DIG Digital I/O. C12IN0- I Analog Comparators C1 and C2 inverting input. AN0 I Analog Analog input 0. 3 28 RA1/C12IN1-/AN1 RA1 I/O TTL/DIG Digital I/O. C12IN1- I Analog Comparators C1 and C2 inverting input. AN1 I Analog Analog input 1. 4 1 RA2/C2IN+/AN2/DACOUT/VREF- RA2 I/O TTL/DIG Digital I/O. C2IN+ I Analog Comparator C2 non-inverting input. AN2 I Analog Analog input 2. DACOUT O Analog DAC Reference output. VREF- I Analog A/D reference voltage (low) input. 5 2 RA3/C1IN+/AN3/VREF+ RA3 I/O TTL/DIG Digital I/O. C1IN+ I Analog Comparator C1 non-inverting input. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. 6 3 RA4/C1OUT/SRQ/T0CKI RA4 I/O ST/DIG Digital I/O. C1OUT O DIG Comparator C1 output. SRQ O DIG SR latch Q output. T0CKI I ST Timer0 external clock input. 7 4 RA5/C2OUT/SRNQ/SS/HLVDIN/AN4 RA5 I/O TTL/DIG Digital I/O. C2OUT O DIG Comparator C2 output. SRNQ O DIG SR latch Q output. SS I TTL SPI slave select input (MSSP). HLVDIN I Analog High/Low-Voltage Detect input. AN4 I Analog Analog input 4. 10 7 RA6/CLKO/OSC2 RA6 I/O TTL/DIG Digital I/O. CLKO O DIG Outputs 1/4 the frequency of OSC1 and denotes the instruction cycle rate. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator modes. Legend: TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. DS30000684B-page 14  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer SPDIP, Pin Name Description Type Type SOIC, QFN SSOP 9 6 RA7/CLKI/OSC1 RA7 I/O TTL/DIG Digital I/O. CLKI I CMOS External clock source input. Always associated with pin function OSC1. OSC1 I ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. 21 18 RB0/INT0/FLT0/SRI/SDI/SDA/AN12 RB0 I/O TTL/DIG Digital Output or Input with internal pull-up option. INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input for ECCP auto-shutdown. SRI I ST SR latch input. SDI I ST SPI data in (MSSP). SDA I/O I2C™ I2C data I/O (MSSP). AN12 I Analog Analog input 12. 22 19 RB1/INT1/P1C/SCK/SCL/C12IN3-/AN10 RB1 I/O TTL/DIG Digital Output or Input with internal pull-up option. INT1 I ST External interrupt 1. P1C O DIG Enhanced CCP1 PWM output. SCK I/O ST/DIG Synchronous serial clock input/output for SPI mode (MSSP). SCL I/O I2C Synchronous serial clock input/output for I2C mode (MSSP). C12IN3- I Analog Comparators C1 and C2 inverting input. AN10 I Analog Analog input 10. 23 20 RB2/INT2/CTED1/P1B/AN8 RB2 I/O TTL/DIG Digital Output or Input with internal pull-up option. INT2 I ST External interrupt 2. CTED1 I ST CTMU Edge 1 input. P1B O DIG Enhanced CCP1 PWM output. AN8 I Analog Analog input 8. 24 21 RB3/CTED2/CCP2/SDO/C12IN2-/AN9 RB3 I/O TTL/DIG Digital Output or Input with internal pull-up option. CTED2 I ST CTMU Edge 2 input. CCP2(2) I/O ST/DIG Alternate Capture 2 input/Compare 2 output/PWM 2 output. SDO(1) O DIG SPI data out (MSSP). C12IN2- I Analog Comparators C1 and C2 inverting input. AN9 I Analog Analog input 9. Legend: TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear.  2012-2014 Microchip Technology Inc. DS30000684B-page 15

PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer SPDIP, Pin Name Description Type Type SOIC, QFN SSOP 25 22 RB4/IOCB4/P1D/AN11 RB4 I/O TTL/DIG Digital Output or Input with internal pull-up option. IOCB4 I TTL Interrupt-on-change pin. P1D O DIG Enhanced CCP1 PWM output. AN11 I Analog Analog input 11. 26 23 RB5/IOCB5/T3CKI/T1G/AN13 RB5 I/O TTL/DIG Digital Output or Input with internal pull-up option. IOCB5 I TTL Interrupt-on-change pin. T3CKI(2) I ST Alternate Timer3 clock input. T1G I ST Timer1 external clock gate input. AN13 I Analog Analog input 13. 27 24 RB6/IOCB6/PGC RB6 I/O TTL/DIG Digital Output or Input with internal pull-up option. IOCB6 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. 28 25 RB7/IOCB7/PGD RB7 I/O TTL/DIG Digital Output or Input with internal pull-up option. IOCB7 I TTL Interrupt-on-change pin. PGD I/O ST/DIG In-Circuit Debugger and ICSP™ programming data pin. 11 8 RC0/IOCC0/T3CKI/T3G/T1CKI/SOSCO RC0 I/O ST/DIG Digital I/O. IOCC0 I TTL Interrupt-on-change pin. T3CKI(1) I ST Timer3 clock input. T3G I ST Timer3 external clock gate input. T1CKI I ST Timer1 clock input. SOSCO O — Secondary oscillator output. 12 9 RC1/IOCC1/CCP2/SOSCI RC1 I/O ST/DIG Digital I/O. IOCC1 I TTL Interrupt-on-change pin. CCP2(1) I/O ST/DIG Capture 2 input/Compare 2 output/PWM 2 output. SOSCI I Analog Secondary oscillator input. Legend: TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. DS30000684B-page 16  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer SPDIP, Pin Name Description Type Type SOIC, QFN SSOP 13 10 RC2/CTPLS/P1A/CCP1/IOCC2/AN14 RC2 I/O ST/DIG Digital I/O. CTPLS O DIG CTMU pulse generator output. P1A O DIG Enhanced CCP1 PWM output. CCP1 I/O ST/DIG Capture 1 input/Compare 1 output/PWM 1 output. IOCC2 I TTL Interrupt-on-change pin. AN14 I Analog Analog input 14. 14 11 VUSB3V3 VUSB3V3 P — Internal 3.3V voltage regulator output, positive supply for USB transceiver. 15 12 D-/IOCC4 D- I/O — USB differential minus line input/output. IOCC4 I ST Interrupt-on-change pin. 16 13 D+/IOCC5 D+ I/O — USB differential plus line input/output. IOCC5 I ST Interrupt-on-change pin. 17 14 RC6/IOCC6/TX/CK/AN18 RC6 I/O ST/DIG Digital I/O. IOCC6 I TTL Interrupt-on-change pin. TX O DIG EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). AN18 I Analog Analog input 18. 18 15 RC7/SDO/IOCC7/RX/DT/AN19 RC7 I/O ST/DIG Digital I/O. SDO(2) O DIG Alternate SPI data out pin assignment (MSSP). IOCC7 I TTL Interrupt-on-change pin. RX I ST EUSART asynchronous receive. DT I/O ST/DIG EUSART synchronous data (see related TX/CK). AN19 I Analog Analog input 19. 1 26 RE3/VPP/MCLR RE3 I ST Digital input. VPP P Programming voltage input. MCLR I ST Active-Low Master Clear (device Reset) input. 20 17 VDD P — Positive supply for logic and I/O pins. 8, 19 5, 16 VSS P — Ground reference for logic and I/O pins. Legend: TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear.  2012-2014 Microchip Technology Inc. DS30000684B-page 17

PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type PDIP TQFP UQFN 2 19 17 RA0/C12IN0-/AN0 RA0 I/O TTL/DIG Digital I/O. C12IN0- I Analog Comparators C1 and C2 inverting input. AN0 I Analog Analog input 0. 3 20 18 RA1/C12IN1-/AN1 RA1 I/O TTL/DIG Digital I/O. C12IN1- I Analog Comparators C1 and C2 inverting input. AN1 I Analog Analog input 1. 4 21 19 RA2/C2IN+/AN2/DACOUT/VREF- RA2 I/O TTL/DIG Digital I/O. C2IN+ I Analog Comparator C2 non-inverting input. AN2 I Analog Analog input 2. DACOUT O Analog DAC Reference output. VREF- I Analog A/D reference voltage (low) input. 5 22 20 RA3/C1IN+/AN3/VREF+ RA3 I/O TTL/DIG Digital I/O. C1IN+ I Analog Comparator C1 non-inverting input. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. 6 23 21 RA4/C1OUT/SRQ/T0CKI RA4 I/O ST/DIG Digital I/O. C1OUT O DIG Comparator C1 output. SRQ O TTL SR latch Q output. T0CKI I ST Timer0 external clock input. 7 24 22 RA5/C2OUT/SRNQ/SS/HLVDIN/AN4 RA5 I/O TTL/DIG Digital I/O. C2OUT O DIG Comparator C2 output. SRNQ O DIG SR latch Q output. SS I TTL SPI slave select input (MSSP). HLVDIN I Analog High/Low-Voltage Detect input. AN4 I Analog Analog input 4. 14 31 29 RA6/CLKO/OSC2 RA6 I/O TTL/DIG Digital I/O. CLKO O DIG Outputs 1/4 the frequency of OSC1 and denotes the instruction cycle rate. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. 13 30 28 RA7/CLKI/OSC1 RA7 I/O TTL/DIG Digital I/O. CLKI I CMOS External clock source input. Always associated with pin function OSC1. OSC1 I ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. Legend: TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. 3: Pin is “No Connect”, except on PIC18(L)F45K50 TQFP devices with ICPRT Configuration bit set. DS30000684B-page 18  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP TQFP UQFN 33 8 8 RB0/INT0/FLT0/SDI/SDA/SRI/AN12 RB0 I/O TTL/DIG Digital Output or Input with internal pull-up option. INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input for ECCP auto-shutdown. SDI I ST SPI Data in (MSSP). SDA I/O I2C™ I2C Data I/O (MSSP). SRI I ST SR latch input. AN12 I Analog Analog input 12. 34 9 9 RB1/INT1/P1C/SCK/SCL/C12IN3-/AN10 RB1 I/O TTL/DIG Digital Output or Input with internal pull-up option. INT1 I ST External interrupt 1. P1C O DIG Enhanced CCP1 PWM output. SCK I/O ST/DIG Synchronous serial clock input/output for SPI mode (MSSP). SCL I/O I2C Synchronous serial clock input/output for I2C mode (MSSP). C12IN3- I Analog Comparators C1 and C2 inverting input. AN10 I Analog Analog input 10. 35 10 10 RB2/P1B/INT2/CTED1/AN8 RB2 I/O TTL/DIG Digital Output or Input with internal pull-up option. P1B O DIG Enhanced CCP1 PWM output. INT2 I ST External interrupt 2. CTED1 I ST CTMU Edge 1 input. AN8 I Analog Analog input 8. 36 11 11 RB3/CTED2/SDO/CCP2/C12IN2-/AN9 RB3 I/O TTL/DIG Digital Output or Input with internal pull-up option. CTED2 I ST CTMU Edge 2 input. SDO(1) O DIG SPI Data out (MSSP). CCP2(2) I/O ST Alternate Capture 2 input/Compare 2 output/PWM 2 output. C12IN2- I Analog Comparators C1 and C2 inverting input. AN9 I Analog Analog input 9. 37 14 12 RB4/IOCB4/P1D/AN11 RB4 I/O TTL/DIG Digital Output or Input with internal pull-up option. IOCB4 I TTL Interrupt-on-change pin. P1D O DIG Enhanced CCP1 PWM output. AN11 I Analog Analog input 11. 38 15 13 RB5/IOCB5/T3CKI/T1G/AN13 RB5 I/O TTL/DIG Digital Output or Input with internal pull-up option. IOCB5 I TTL Interrupt-on-change pin. T3CKI(2) I ST Alternate Timer3 clock input. T1G I ST Timer1 external clock gate input. AN13 I Analog Analog input 13. Legend: TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. 3: Pin is “No Connect”, except on PIC18(L)F45K50 TQFP devices with ICPRT Configuration bit set.  2012-2014 Microchip Technology Inc. DS30000684B-page 19

PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP TQFP UQFN 39 16 14 RB6/IOCB6/PGC RB6 I/O TTL/DIG Digital Output or Input with internal pull-up option. IOCB6 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. 40 17 15 RB7/IOCB7/PGD RB7 I/O TTL/DIG Digital Output or Input with internal pull-up option. IOCB7 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. 15 32 30 RC0/IOCC0/T3CKI/T3G/T1CKI/SOSCO RC0 I/O ST/DIG Digital I/O. IOCC0 I TTL Interrupt-on-change pin. T3CKI(1) I ST Timer3 clock input. T3G I ST Timer3 external clock gate input. T1CKI I ST Timer1 clock input. SOSCO O — Secondary oscillator output. 16 35 31 RC1/IOCC1/CCP2/SOSCI RC1 I/O ST/DIG Digital I/O. IOCC1 I TTL Interrupt-on-change pin. CCP2(1) I/O ST/DIG Capture 2 input/Compare 2 output/PWM 2 output. SOSCI I Analog Secondary oscillator input. 17 36 32 RC2/CTPLS/P1A/CCP1/IOCC2/AN14 RC2 I/O ST/DIG Digital I/O. CTPLS O DIG CTMU pulse generator output. P1A O DIG Enhanced CCP1 PWM output. CCP1 I/O ST/DIG Capture 1 input/Compare 1 output/PWM 1 output. IOCC2 I TTL Interrupt-on-change pin. AN14 I Analog Analog input 14. 18 37 33 VUSB3V3 VUSB3V3 P — Internal 3.3V voltage regulator output, positive supply for USB transceiver. 23 42 38 D-/IOCC4 D- I/O — USB differential minus line input/output. IOCC4 I ST Interrupt-on-change pin. 24 43 39 D+/IOCC5 D+ I/O — USB differential plus line input/output. IOCC5 I ST Interrupt-on-change pin. Legend: TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. 3: Pin is “No Connect”, except on PIC18(L)F45K50 TQFP devices with ICPRT Configuration bit set. DS30000684B-page 20  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP TQFP UQFN 25 44 40 RC6/IOCC6/TX/CK/AN18 RC6 I/O ST/DIG Digital I/O. IOCC6 I TTL Interrupt-on-change pin. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). AN18 I Analog Analog input 18. 26 1 1 RC7/RX/DT/SDO/IOCC7/AN19 RC7 I/O ST/DIG Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see related TX/CK). SDO(2) O DIG Alternate SPI data out (MSSP). IOCC7 I TTL Interrupt-on-change pin. AN19 I Analog Analog input 19. 19 38 34 RD0/AN20 RD0 I/O ST/DIG Digital I/O. AN20 I Analog Analog input 20. 20 39 35 RD1/AN21 RD1 I/O ST/DIG Digital I/O. AN21 I Analog Analog input 21. 21 40 36 RD2/AN22 RD2 I/O ST/DIG Digital I/O AN22 I Analog Analog input 22. 22 41 37 RD3/AN23 RD3 I/O ST/DIG Digital I/O. AN23 I Analog Analog input 23. 27 2 2 RD4/AN24 RD4 I/O ST/DIG Digital I/O. AN24 I Analog Analog input 24. 28 3 3 RD5/P1B/AN25 RD5 I/O ST/DIG Digital I/O. P1B O DIG Enhanced CCP1 PWM output. AN25 I Analog Analog input 25. 29 4 4 RD6/P1C/AN26 RD6 I/O ST/DIG Digital I/O. P1C O DIG Enhanced CCP1 PWM output. AN26 I Analog Analog input 26. 30 5 5 RD7/P1D/AN27 RD7 I/O ST/DIG Digital I/O. P1D O DIG Enhanced CCP1 PWM output. AN27 I Analog Analog input 27. Legend: TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. 3: Pin is “No Connect”, except on PIC18(L)F45K50 TQFP devices with ICPRT Configuration bit set.  2012-2014 Microchip Technology Inc. DS30000684B-page 21

PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP TQFP UQFN 8 25 23 RE0/AN5 RE0 I/O ST/DIG Digital I/O. AN5 I Analog Analog input 5. 9 26 24 RE1/AN6 RE1 I/O ST/DIG Digital I/O. AN6 I Analog Analog input 6. 10 27 25 RE2/AN7 RE2 I/O ST Digital I/O. AN7 I Analog Analog input 7. 1 18 16 RE3/VPP/MCLR RE3 I ST Digital input. VPP P Programming voltage input. MCLR I ST Active-low Master Clear (device Reset) input. — 12 — ICCK/ICPGC ICCK I/O ST Dedicated In-Circuit Debugger clock. ICPGC(3) I/O ST Dedicated ICSP™ programming clock. — 13 — ICDT/ICPGD ICDT I/O ST Dedicated In-Circuit Debugger data. ICPGD(3) I/O ST Dedicated ICSP™ programming data. — 33 — ICRST/ICVPP ICRST I ST Dedicated Master Clear Reset input. ICVPP(3) I P Dedicated programming voltage input. 11,32 7, 28 7, 26 VDD P — Positive supply for logic and I/O pins. 12,31 6, 29 6, 27 VSS P — Ground reference for logic and I/O pins. 34 NC Legend: TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Note 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. 3: Pin is “No Connect”, except on PIC18(L)F45K50 TQFP devices with ICPRT Configuration bit set. DS30000684B-page 22  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH MINIMUM CONNECTIONS PIC18(L)F2X/45K50 MICROCONTROLLERS C2(2) VDD 2.1 Basic Connection Requirements R1 DD SS V V Getting started with the PIC18(L)F2X/45K50 family of R2 8-bit microcontrollers requires attention to a minimal MCLR (1) VUSB3V3 set of device pin connections before proceeding with C1 development. C7(2) PIC18F2X/45K50 The following pins must always be connected: • All VDD and VSS pins C6(2) VSS VDD C3(2) (see Section2.2 “Power Supply Pins”) VDD VSS • MCLR pin D S (see Section2.3 “Master Clear (MCLR) Pin”) VD VS • VUSB3V3 pins (see Section2.4 “Voltage Regulator Pins C4(2) (VUSB3V3)”) These pins must also be connected if they are being used in the end application: Key (all values are recommendations): • PGC/PGD pins used for In-Circuit Serial C1 through C6: 0.1 F, 20V ceramic Programming (ICSP) and debugging purposes (see R1: 10 kΩ Section2.5 “ICSP Pins”) R2: 100Ω to 470Ω • OSC1 and OSC2 pins when an external oscillator Note 1: See Section2.4 “Voltage Regulator Pins source is used (VUSB3V3)” for explanation of VUSB3V3 pin (see Section2.6 “External Oscillator Pins”) connections. 2: The example shown is for a PIC18F device Additionally, the following pins may be required: with five VDD/VSS pairs. Other devices may • VREF+/VREF- pins are used when external voltage have more or less pairs; adjust the number reference for analog modules is implemented of decoupling capacitors appropriately. The minimum mandatory connections are shown in Figure2-1.  2012-2014 Microchip Technology Inc. DS30684A-page 23

PIC18(L)F2X/45K50 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: Device Reset, and Device Programming The use of decoupling capacitors on every pair of and Debugging. If programming and debugging are power supply pins, such as VDD and VSS is required. not required in the end application, a direct Consider the following criteria when using decoupling connection to VDD may be all that is required. The capacitors: addition of other components, to help increase the application’s resistance to spurious Resets from • Value and type of capacitor: A 0.1 F (100 nF), voltage sags, may be beneficial. A typical 10-20V capacitor is recommended. The capacitor configuration is shown in Figure2-1. Other circuit should be a low-ESR device, with a resonance designs may be implemented, depending on the frequency in the range of 200MHz and higher. application’s requirements. Ceramic capacitors are recommended. • Placement on the printed circuit board: The During programming and debugging, the resistance and capacitance that can be added to the pin must decoupling capacitors should be placed as close to the pins as possible. It is recommended to be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage place the capacitors on the same side of the board as the device. If space is constricted, the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values capacitor can be placed on another layer on the of R1 and C1 will need to be adjusted based on the PCB using a via; however, ensure that the trace application and PCB requirements. For example, it is length from the pin to the capacitor is no greater recommended that the capacitor, C1, be isolated than 0.25inch (6mm). from the MCLR pin during programming and • Handling high-frequency noise: If the board is debugging operations by using a jumper (Figure2-2). experiencing high-frequency noise (upward of The jumper is replaced for normal run-time tens of MHz), add a second ceramic type operations. capacitor in parallel to the above described decoupling capacitor. The value of the second Any components associated with the MCLR pin capacitor can be in the range of 0.01F to should be placed within 0.25 inch (6mm) of the pin. 0.001F. Place this second capacitor next to each primary decoupling capacitor. In high-speed FIGURE 2-2: EXAMPLE OF MCLR PIN circuit designs, consider implementing a decade CONNECTIONS pair of capacitances as close to the power and ground pins as possible (e.g., 0.1F in parallel VDD with 0.001F). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the JP PIC18F2X/45K50 decoupling capacitors are first in the power chain. Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R1 10k is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10k. Ensure that the On boards with power traces running longer than MCLR pin VIH and VIL specifications are met. sixinches in length, it is suggested to use a tank 2: R2470 will limit any current flowing into capacitor for integrated circuits, including MCLR from the external capacitor, C, in the microcontrollers, to supply a local power source. The event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical value of the tank capacitor should be determined based Overstress (EOS). Ensure that the MCLR pin on the trace resistance that connects the power supply VIH and VIL specifications are met. source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7F to 47F. DS30684A-page 24  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 2.4 Voltage Regulator Pins (VUSB3V3) The X5R and X7R capacitors typically exhibit satisfac- tory temperature stability (ex: ±15% over a wide The on-chip voltage regulator must always be temperature range, but consult the manufacturer’s data connected directly to either a supply voltage or to an sheets for exact specifications). However, Y5V capaci- external capacitor. tors typically have extreme temperature tolerance When the regulator is enabled (F devices), a low-ESR specifications of +22%/-82%. Due to the extreme capacitor is required on the VUSB3V3 pin to stabilize the temperature tolerance, a 10 F nominal rated Y5V type voltage regulator output voltage. The VUSB3V3 pin must capacitor may not deliver enough total capacitance to not be connected to VDD and is recommended to use a meet minimum internal voltage regulator stability and ceramic capacitor connected to ground. Refer to transient response requirements. Therefore, Y5V Section29.0 “Electrical Specifications” for capacitors are not recommended for use with the additional information. internal regulator if the application must operate over a wide temperature range. It is recommended that the trace length not exceed 0.25inch (6mm). Refer to Section29.0 “Electrical In addition to temperature tolerance, the effective Specifications” for additional information. capacitance of large value ceramic capacitors can vary substantially, based on the amount of DC voltage When the regulator is disabled (LF devices), the applied to the capacitor. This effect can be very signifi- VUSB3V3 pin should be externally tied to a voltage cant, but is often overlooked or is not always source maintained at the VDD level. Refer to documented. Section29.0 “Electrical Specifications” for information on VDD and VUSB3V3. A typical DC bias voltage vs. capacitance graph for X7R type and Y5V type capacitors is shown in • LF devices (with the name PIC18LF2X/45K50) Figure2-3. permanently disable the voltage regulator. The VDD level of these devices must comply with FIGURE 2-3: DC BIAS VOLTAGE vs. the “voltage regulator disabled” specification for CAPACITANCE Parameter D001, in Section29.0 “Electrical Specifications”. CHARACTERISTICS • F devices permanently enable the voltage regulator. These devices require an external capacitor on %) 10 e ( 0 the VUSB3V3 pin. Refer to Section29.0 ng-10 16V Capacitor “Electrical Specifications” for additional ha-20 C-30 information. ance --5400 10V Capacitor 2.4.1 CONSIDERATIONS FOR CERAMIC pacit--7600 6.3V Capacitor CAPACITORS Ca-80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 In recent years, large value, low-voltage, surface-mount DC Bias Voltage (VDC) ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small When selecting a ceramic capacitor to be used with the physical size and other properties make ceramic internal voltage regulator, it is suggested to select a capacitors very attractive in many types of applications. high-voltage rating, so that the operating voltage is a Ceramic capacitors are suitable for use with the small percentage of the maximum rated capacitor internal voltage regulator of this microcontroller. voltage. For example, choose a ceramic capacitor However, some care is needed in selecting the rated at 16V for the 3.3V VUSB3V3 voltage. capacitor to ensure that it maintains sufficient capacitance over the intended operating range of the application. Typical low-cost, ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial toler- ance specifications for these types of capacitors are often specified as ±10% to ±20% (X5R and X7R), or -20%/+80% (Y5V). However, the effective capacitance that these capacitors provide in an application circuit will also vary based on additional factors, such as the applied DC bias voltage and the temperature. The total in-circuit tolerance is, therefore, much wider than the initial tolerance specification.  2012-2014 Microchip Technology Inc. DS30684A-page 25

PIC18(L)F2X/45K50 2.5 ICSP Pins 2.6 External Oscillator Pins The PGC and PGD pins are used for In-Circuit Serial Many microcontrollers have options for at least two Programming (ICSP) and debugging purposes. It is oscillators: a high-frequency primary oscillator and a recommended to keep the trace length between the low-frequency secondary oscillator (refer to ICSP connector and the ICSP pins on the device as Section3.0 “Oscillator Module (With Fail-Safe short as possible. If the ICSP connector is expected to Clock Monitor)” for details). experience an ESD event, a series resistor is recom- The oscillator circuit should be placed on the same mended, with the value in the range of a few tens of side of the board as the device. Place the oscillator ohms, not to exceed 100Ω. circuit close to the respective oscillator pins with no Pull-up resistors, series diodes and capacitors on the more than 0.5inch (12mm) between the circuit PGC and PGD pins are not recommended as they will components and the pins. The load capacitors should interfere with the programmer/debugger communica- be placed next to the oscillator itself, on the same side tions to the device. If such discrete components are an of the board. application requirement, they should be removed from Use a grounded copper pour around the oscillator the circuit during programming and debugging. Alter- circuit to isolate it from surrounding circuits. The natively, refer to the AC/DC characteristics and timing grounded copper pour should be routed directly to the requirements information in the respective device MCU ground. Do not run any signal traces or power Flash programming specification for information on traces inside the ground pour. Also, if using a two-sided capacitive loading limits, and pin input voltage high board, avoid any traces on the other side of the board (VIH) and input low (VIL) requirements. where the crystal is placed. For device emulation, ensure that the “Communication Layout suggestions are shown in Figure 2-4. In-line Channel Select” (i.e., PGCx/PGDx pins), programmed packages may be handled with a single-sided layout into the device, matches the physical connections for that completely encompasses the oscillator pins. With the ICSP to the Microchip debugger/emulator tool. fine-pitch packages, it is not always possible to com- For more information on available Microchip pletely surround the pins and components. A suitable development tools connection requirements, refer to solution is to tie the broken guard sections to a mirrored Section28.0 “Development Support”. ground layer. In all cases, the guard trace(s) must be returned to ground. In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” 2.7 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the output to logic low. DS30684A-page 26  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 2-4: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Single-Sided and In-Line Layouts: Copper Pour Primary Oscillator (tied to ground) Crystal DEVICE PINS Primary OSC1 Oscillator C1 ` OSC2 C2 GND ` SOSCO SOSCI Timer1 Oscillator Crystal ` T1 Oscillator: C1 T1 Oscillator: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 Oscillator GND Crystal C1 OSCI DEVICE PINS  2012-2014 Microchip Technology Inc. DS30684A-page 27

PIC18(L)F2X/45K50 3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 3.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. Figure3-1 illustrates a block diagram of the oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of three internal oscillators, with a choice of speeds selectable via software. Additional clock features include: • Selectable system clock source between external or internal sources via software. • Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. • Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources. The primary clock module can be configured to provide one of six clock sources as the primary clock. 1. RC External Resistor/Capacitor 2. LP Low-Power Crystal 3. XT Crystal/Resonator 4. INTOSC Internal Oscillator 5. HS High-Speed Crystal/Resonator 6. EC External Clock The HS and EC oscillator circuits can be optimized for power consumption and oscillator speed using settings in FOSC<3:0>. Additional FOSC<3:0> selections enable RA6 to be used as I/O or CLKO (FOSC/4) for RC, EC and INTOSC Oscillator modes. Primary clock modes are selectable by the FOSC<3:0> bits of the CONFIG1H Configuration register. The primary clock operation is further defined by these Configuration and register bits: 1. PCLKEN (CONFIG1H<5>) 2. PRISD (OSCCON2<2>) 3. CFGPLLEN (CONFIG1L<1>) 4. PLLEN (OSCCON2<4>) 5. IRCF<2:0> (OSCCON<6:4>) 6. INTSRC (OSCCON2<5>) The HFINTOSC and INTRC are factory calibrated high and low-frequency oscillators, respectively, which are used as the internal clock sources. DS30000684B-page 28  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 3-1: SIMPLIFIED OSCILLATOR SYSTEM BLOCK DIAGRAM Secondary Oscillator(1) SOSCO SOesccoilnladtaorry SOSCOUT LoEwv-ePnot wSewr itMchode (SCS<1:0>) (SOSC) SOSCI 2 Primary Clock Module Secondary Oscillator PCLKPERNISD PLL_Selec t( 3) CPUDIV 01 IDLE EN FOSC<3:0>(4) CPU OOSSCC12 OP(sOcriiSmllaCat)royr(2) Primary OINsTcOillaStCor 10 43xxP oLrL 10 PLL Postscaler  1236 11001010 PCrilmocakry 00 Clock Switch MUX Peripheral s4 RA6 CLKO Enabled Modes INTOSC 1x Internal Oscillator IRCF<2:0> INTSRC FSEN 3 3 1 USB Module HF-16 MHZ Clock H(F1I6N MTOHSz)C HHHHFFFF----2184 MMMMHHHHZZZZ Interna  84 10 0 NNeeeeddss 468 M MHHz zf ofor rL FSS INTOSC HF-500 kHZ l O CDiirvcidueit HHFF--3215.02 5k HkZHZ scillato INTOSC LS48MHZ r M U X (3) INTRC LF-31.25 kHz (31.25 kHz) Note 1: Details in Figure3-3. 2: Details in Figure3-2. 3: Details in Table3-1. 4: The Primary Oscillator MUX uses the INTOSC branch when FOSC<3:0> = 100x.  2012-2014 Microchip Technology Inc. DS30000684B-page 29

PIC18(L)F2X/45K50 3.2 Oscillator Control 3.2.3 LOW-FREQUENCY SELECTION The OSCCON, OSCCON2 and OSCTUNE registers When a nominal output frequency of 31.25kHz is (Register3-1 to Register3-3) control several aspects selected (IRCF<2:0> = 000), users may choose of the device clock’s operation, both in full-power which internal oscillator acts as the source. This is operation and in power-managed modes. done with the INTSRC bit of the OSCCON2<5> register. See Figure3-2 and Register3-1 for specific • Main System Clock Selection (SCS) 31.25kHz selection. This option allows users to • Primary Oscillator Circuit Shutdown (PRISD) select a 31.25kHz clock (based on HFINTOSC) that • Secondary Oscillator Enable (SOSCGO) can be tuned using the TUN<6:0> bits in the • Primary Clock Frequency multiplier (PLLEN) OSCTUNE register, while maintaining power savings with a very low clock speed. INTRC always remains • Internal Frequency selection bits (IRCF, INTSRC) the clock source for features such as the Watchdog • Clock Status bits (OSTS, HFIOFS, LFIOFS, Timer and the Fail-Safe Clock Monitor, regardless of SOSCRUN, PLLRDY) the setting of the INTSRC bit. • Power management selection (IDLEN) This option allows users to select the tunable and more 3.2.1 MAIN SYSTEM CLOCK SELECTION precise HFINTOSC as a clock source, while maintaining power savings with a very low clock speed. The System Clock Select bits, SCS<1:0>, select the main clock source. The available clock sources are: 3.2.4 POWER MANAGEMENT • Primary clock defined by the FOSC<3:0> bits of The IDLEN bit of the OSCCON register determines CONFIG1H. The primary clock can be the primary whether the device goes into Sleep mode or one of the oscillator, an external clock, or the internal Idle modes when the SLEEP instruction is executed. oscillator block. • Secondary clock (secondary oscillator) • Internal oscillator block (HFINTOSC and INTRC). The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared to select the primary clock on all forms of Reset. 3.2.2 INTERNAL FREQUENCY SELECTION The Internal Oscillator Frequency Select bits (IRCF<2:0>) select the frequency output of the internal oscillator block. The choices are the INTRC source (31.25kHz) and the HFINTOSC source (16MHz) or one of the frequencies derived from the HFINTOSC postscaler (31.25kHz to 16MHz). If the internal oscil- lator block is supplying the main clock, changing the states of these bits will have an immediate change on the internal oscillator’s output. On device Resets, the output frequency of the internal oscillator is set to the default frequency of 1MHz. DS30000684B-page 30  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 3-2: INTERNAL OSCILLATOR MUX BLOCK DIAGRAM IRCF<2:0> INTSRC 3 HF-16 MHz 111 HF-8 MHz 110 HF-4 MHz 101 HF-2 MHz 100 HF-1 MHz 011 HF-500 kHz 010 HF-250 kHz 001 INTOSC HF-31.25 kHz 1 31.25 kHz 000 LF-31.25 kHz 0 TABLE 3-1: PLL_SELECT TRUTH TABLE Primary Clock MUX Source FOSC<3:0> CFGPLLEN PLLSEL PLLEN SPLLMULT PLL_Select 1 x x 3xPLL(1) External Clock (ECHIO/ECHCLKO) 010x 1 0 x x 4xPLL(2) HS Crystal (HSH) 0010 0 x 1 3xPLL(1) 1 0 4xPLL(2) INTOSC (INTOSCIO, INTOSCCLKO) 100x 0 x OFF FOSC (all other modes) xxxx x x x x OFF Note 1: The input clock source must be 16 MHz when 3xPLL is used. 2: The input clock source must be 8 MHz to 12 MHz when 4xPLL is used.  2012-2014 Microchip Technology Inc. DS30000684B-page 31

PIC18(L)F2X/45K50 FIGURE 3-3: SECONDARY OSCILLATOR AND EXTERNAL CLOCK INPUTS SOSCEN SOSCGO T1CON<3> T3CON<3> To Clock Switch Module EN SOSCI Secondary SOSCOUT Oscillator SOSCO T1CKI 1 T3G SOSCEN T1CLK_EXT_SRC T3CKI 0 T1CON<3> SOSCEN T3G SOSCEN 1 0 T3CLK_EXT_SRC 0 T3CKI 1 T3CON<3> T1G T3CMX T1G DS30000684B-page 32  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 3.3 Register Definitions: Oscillator Control REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R-q R-0 R/W-0 R/W-0 IDLEN IRCF<2:0> OSTS(1) HFIOFS SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF<2:0>: Internal RC Oscillator Frequency Select bits 111 = HFINTOSC – (16 MHz) 110 = HFINTOSC/2 – (8 MHz) 101 = HFINTOSC/4 – (4 MHz) 100 = HFINTOSC/8 – (2 MHz) 011 = HFINTOSC/16 – (1 MHz)(2) 010 = HFINTOSC/32 – (500 kHz) 001 = HFINTOSC/64 – (250 kHz) If INTSRC = 1: 000 = HFINTOSC/512 – (31.25 kHz) If INTSRC = 0: 000 = INTRC – (31.25 kHz) bit 3 OSTS: Oscillator Start-up Time-out Status bit 1 = Device is running from the clock defined by FOSC<3:0> of the CONFIG1H register 0 = Device is running from the internal oscillator (HFINTOSC or INTRC) bit 2 HFIOFS: HFINTOSC Frequency Stable bit 1 = HFINTOSC frequency is stable 0 = HFINTOSC frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bit 1x = Internal oscillator block 01 = Secondary (SOSC) oscillator 00 = Primary clock (determined by FOSC<3:0> in CONFIG1H). Note 1: Reset state depends on state of the IESO Configuration bit. 2: Default output frequency of HFINTOSC on Reset.  2012-2014 Microchip Technology Inc. DS30000684B-page 33

PIC18(L)F2X/45K50 REGISTER 3-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 R-0/0 R-0/q R/W-0 R/W-0/0 R/W-0/u R/W-1/1 R-0/0 R-0/0 PLLRDY SOSCRUN INTSRC PLLEN SOSCGO(1) PRISD HFIOFR LFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7 PLLRDY: PLL Run Status bit 1 = System clock comes from PLL 0 = System clock comes from an oscillator, other than PLL bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from secondary SOSC 0 = System clock comes from an oscillator, other than SOSC bit 5 INTSRC: HFINTOSC Divided by 512 Enable bit 1 = HFINTOSC used as the 31.25 kHz system clock reference – high accuracy 0 = INTRC used as the 31.25 kHz system clock reference – low power. bit 4 PLLEN: Software PLL Enable bit If FOSC<3:0> = 100x, 010x or 001x 1 = PLL enabled 0 = PLL disabled Else, No effect on PLL operation. bit 3 SOSCGO(1): Secondary Oscillator Start Control bit 1 = Secondary oscillator is enabled. 0 = Secondary oscillator is shut off if no other sources are requesting it. bit 2 PRISD: Primary Oscillator Drive Circuit Shutdown bit 1 = Oscillator drive circuit on 0 = Oscillator drive circuit off (zero power) bit 1 HFIOFR: HFINTOSC Status bit 1 = HFINTOSC is running 0 = HFINTOSC is not running bit 0 LFIOFS: INTRC Frequency Stable bit 1 = INTRC is stable 0 = INTRC is not stable Note 1: The SOSCGO bit is only reset on a POR Reset. DS30000684B-page 34  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 3.4 Clock Source Modes 3.5 External Clock Modes Clock source modes can be classified as external or 3.5.1 OSCILLATOR START-UP TIMER (OST) internal. When the oscillator module is configured for LP, XT or • External Clock modes rely on external circuitry for HS modes, the Oscillator Start-up Timer (OST) counts the clock source. Examples are: Clock modules 1024 oscillations from OSC1. This occurs following a (EC mode), quartz crystal resonators or ceramic Power-on Reset (POR) and when the Power-up Timer resonators (LP, XT and HS modes) and Resistor- (PWRT) has expired (if configured), or a wake-up from Capacitor (RC mode) circuits. Sleep. During this time, the program counter does not • Internal clock sources are contained internally increment and program execution is suspended. The within the Oscillator block. The Oscillator block OST ensures that the oscillator circuit, using a quartz has two internal oscillators: the 16MHz High- crystal resonator or ceramic resonator, has started and Frequency Internal Oscillator (HFINTOSC) and is providing a stable system clock to the oscillator the 31.25kHz Low-Frequency Internal Oscillator module. When switching between clock sources, a (INTRC). delay is required to allow the new clock to stabilize. The system clock can be selected between external or These oscillator delays are shown in Table3-2. internal clock sources via the System Clock Select In order to minimize latency between external oscillator (SCS<1:0>) bits of the OSCCON register. See start-up and code execution, the Two-Speed Clock Section3.11 “Clock Switching” for additional Start-up mode can be selected (see Section3.12 information. “Two-Speed Clock Start-up Mode”). TABLE 3-2: OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Oscillator Delay INTRC 31.25kHz Sleep/POR Oscillator Warm-Up Delay (TWARM) HFINTOSC 31.25kHz to 16MHz Sleep/POR EC, RC DC – 48MHz 2 instruction cycles INTRC (31.25kHz) EC, RC DC – 48MHz 1 cycle of each Sleep/POR LP, XT, HS 32kHz to 25MHz 1024 Clock Cycles (OST) Sleep/POR PLL 32MHz to 48MHz 1024 Clock Cycles (OST) + 2 ms INTRC (31.25kHz) INTRC 31.25kHz to 16MHz 1s (approx.) HFINTOSC 3.5.2 EC MODE FIGURE 3-4: EXTERNAL CLOCK (EC) MODE OPERATION The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is Clock from OSC1/CLKIN connected to the OSC1 input and the OSC2 is available Ext. System for general purpose I/O. Figure3-4 shows the pin PIC® MCU connections for EC mode. I/O OSC2/CLKO The External Clock (EC) offers different power modes, Low Power (ECL), Medium Power (ECM) and High Power (ECH), selectable by the FOSC<3:0> bits. Each mode is best suited for a certain range of frequencies. The ranges are: • ECL – below 4MHz • ECM – between 4MHz and 16MHz • ECH – above 16MHz The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or Wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.  2012-2014 Microchip Technology Inc. DS30000684B-page 35

PIC18(L)F2X/45K50 3.5.3 LP, XT, HS MODES Note 1: Quartz crystal characteristics vary The LP, XT and HS modes support the use of quartz according to type, package and crystal resonators or ceramic resonators connected to manufacturer. The user should consult the OSC1 and OSC2 (Figure3-5). The mode selects a low, manufacturer data sheets for specifications medium or high gain setting of the internal inverter- and recommended application. amplifier to support various resonator types and speed. 2: Always verify oscillator performance over LP Oscillator mode selects the lowest gain setting of the the VDD and temperature range that is internal inverter-amplifier. LP mode current consumption expected for the application. is the least of the three modes. This mode is best suited 3: For oscillator design assistance, refer to the to drive resonators with a low drive level specification, for following Microchip Application Notes: example, tuning fork type crystals. • AN826, “Crystal Oscillator Basics and XT Oscillator mode selects the intermediate gain Crystal Selection for rfPIC® and PIC® setting of the internal inverter-amplifier. XT mode Devices” (DS00826) current consumption is the medium of the three modes. • AN849, “Basic PIC® Oscillator Design” This mode is best suited to drive resonators with a (DS00849) medium drive level specification. • AN943, “Practical PIC® Oscillator HS Oscillator mode offers a Medium Power (MP) and a Analysis and Design” (DS00943) High Power (HP) option selectable by the FOSC<3:0> • AN949, “Making Your Oscillator Work” bits. The MP selections are best suited for oscillator (DS00949) frequencies between 4 and 16MHz. The HP selection has the highest gain setting of the internal inverter- amplifier and is best suited for frequencies above FIGURE 3-6: CERAMIC RESONATOR 16MHz. HS mode is best suited for resonators that OPERATION require a high drive setting. (XT OR HS MODE) FIGURE 3-5: QUARTZ CRYSTAL PIC® MCU OPERATION (LP, XT OR HS MODE) OSC1/CLKIN C1 To Internal PIC® MCU Logic OSC1/CLKIN RP(3) RF(2) Sleep C1 To Internal Logic Quartz RF(2) Sleep C2 Ceramic RS(1) OSC2/CLKO Crystal Resonator Note 1: A series resistor (RS) may be required for C2 RS(1) OSC2/CLKO ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator 2: The value of RF varies with the Oscillator mode operation. selected (typically between 2M to 10M. DS30000684B-page 36  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 3.5.4 EXTERNAL RC MODES 3.6 Internal Clock Modes The external Resistor-Capacitor (RC) modes support The oscillator module has two independent, internal the use of an external RC circuit. This allows the oscillators that can be configured or selected as the designer maximum flexibility in frequency choice while system clock source. keeping costs to a minimum when clock accuracy is not 1. The HFINTOSC (High-Frequency Internal required. There are two modes: RC and RCIO. Oscillator) is factory calibrated and operates at 3.5.4.1 RC Mode 16MHz. The frequency of the HFINTOSC can be user-adjusted via software using the In RC mode, the RC circuit connects to OSC1. OSC2/ OSCTUNE register (Register3-3). CLKO outputs the RC oscillator frequency divided by 4. 2. The INTRC (Low-Frequency Internal Oscillator) is This signal may be used to provide a clock for external factory calibrated and operates at 31.25kHz. The circuitry, synchronization, calibration, test or other INTRC cannot be user-adjusted, but is designed to application requirements. Figure3-7 shows the be stable over temperature and voltage. external RC mode connections. The system clock speed can be selected via software FIGURE 3-7: EXTERNAL RC MODES using the Internal Oscillator Frequency select bits IRCF<2:0> of the OSCCON register. The INTSRC bit allows users to select which internal oscillator provides VDD PIC® MCU the clock source for the 31.25 kHz frequency option. This is covered in greater detail in Section3.2.3 “Low- REXT Frequency Selection”. OSC1/CLKIN Internal Clock The system clock can be selected between external or CEXT internal clock sources via the System Clock Selection (SCS<1:0>) bits of the OSCCON register. See VSS Section3.11 “Clock Switching” for more information. FOSC/4 or OSC2/CLKO(1) 3.6.1 INTOSC WITH I/O OR CLOCKOUT I/O(2) Two of the clock modes selectable with the FOSC<3:0> bits of the CONFIG1H Configuration Recommended values: 10 k  REXT  100 k register configure the internal oscillator block as the CEXT > 20 pF primary oscillator. Mode selection determines whether OSC2/CLKO/RA6 will be configured as Note 1: Alternate pin functions are listed in general purpose I/O (RA6) or FOSC/4 (CLKO). In both Section1.0 “Device Overview”. modes, OSC1/CLKIN/RA6 is configured as general 2: Output depends upon RC or RCIO clock mode. purpose I/O. See Section26.0 “Special Features of the CPU” for more information. 3.5.4.2 RCIO Mode The CLKO signal may be used to provide a clock for In RCIO mode, the RC circuit is connected to OSC1. external circuitry, synchronization, calibration, test or OSC2 becomes a general purpose I/O pin. other application requirements. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: • input threshold voltage variation • component tolerances • packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used.  2012-2014 Microchip Technology Inc. DS30000684B-page 37

PIC18(L)F2X/45K50 3.6.1.1 OSCTUNE Register The OSCTUNE register also implements the The HFINTOSC oscillator circuits are factory calibrated SPLLMULT bit, which controls whether 3x or 4xPLL but can be adjusted in software by writing to the clock multiplication is used when the PLL is enabled TUN<6:0> bits of the OSCTUNE register dynamically in software. For more details about the (Register3-3). function of the SPLLMULT bit see Section3.8.2 “PLL The default value of the TUN<6:0> is ‘0’. The value is a in HFINTOSC Modes”. 7-bit two’s complement number. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. The TUN<6:0> bits in OSCTUNE do not affect the INTRC frequency. Operation of features that depend on the INTRC clock source frequency, such as the Power- up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. 3.7 Register Definitions: Oscillator Tuning REGISTER 3-3: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPLLMULT TUN<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPLLMULT: Software PLL Multiplier Select bit If PLL Enabled, SPLLMULT changes are ignored. Else, Selects which PLL multiplier will be used: 1 = 3xPLL is selected 0 = 4xPLL is selected bit 6-0 TUN<6:0>: Frequency Tuning bits – affects HFINTOSC(1) 0111111 = Maximum frequency 0111110 = • • • 0000001 = 0000000 = Center frequency. Oscillator module is running at the factory calibrated frequency. 1111111 = • • • 1000000 = Minimum frequency Note 1: The TUN<6:0> bits may be supplied and controlled by the Active Clock Tuning module (see Section3.15 “Active Clock Tuning (ACT) Module”) When the Active Clock Tuning is enabled, the TUN<6:0> bits are read-only. DS30000684B-page 38  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 3.7.1 INTRC 3.7.3.1 Compensating with the EUSART The Low-Frequency Internal Oscillator (INTRC) is a An adjustment may be required when the EUSART 31.25kHz internal clock source. The INTRC is not begins to generate framing errors or receives data with tunable, but is designed to be stable across errors while in Asynchronous mode. Framing errors temperature and voltage. See Section29.0 indicate that the device clock frequency is too high; to “Electrical Specifications” for the INTRC accuracy adjust for this, decrement the value in OSCTUNE to specifications. reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to The output of the INTRC can be a clock source to the compensate, increment OSCTUNE to increase the primary clock or the INTOSC clock (see Figure3-1). The clock frequency. INTRC is also the clock source for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock 3.7.3.2 Compensating with the Timers Monitor (FSCM). This technique compares device clock speed to some 3.7.2 FREQUENCY SELECT BITS (IRCF) reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is The HFINTOSC (16MHz) outputs to a divide circuit clocked by a fixed reference source, such as the Tim- that provides frequencies of 16MHz to 31.25kHz. er1 oscillator. These divide circuit frequencies, along with the 31.25kHz INTRC output, are multiplexed to provide a Both timers are cleared, but the timer clocked by the single INTOSC clock output (see Figure3-1). The reference generates interrupts. When an interrupt IRCF<2:0> bits of the OSCCON register and the occurs, the internally clocked timer is read and both INTSRC bit of the OSCCON2 register select the output timers are cleared. If the internally clocked timer value frequency of the internal oscillators. One of eight is greater than expected, then the internal oscillator frequencies can be selected via software: block is running too fast. To adjust for this, decrement the OSCTUNE register. • 16 MHz • 8 MHz 3.7.3.3 Compensating with the CCP Module • 4 MHz in Capture Mode • 2 MHz A CCP module can use free running Timer1 or Timer3 • 1 MHz (Default after Reset) clocked by the internal oscillator block and an external • 500 kHz event with a known period (i.e., AC power frequency). • 250 kHz The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. • 31 kHz (INTRC or HFINTOSC) When the second event causes a capture, the time of the 3.7.3 INTOSC FREQUENCY DRIFT first event is subtracted from the time of the second event. Since the period of the external event is known, The factory calibrates the internal oscillator block outputs the time difference between events can be calculated. (HFINTOSC) for 16MHz. However, this frequency may drift as VDD or temperature changes. It is possible to If the measured time is much greater than the automatically tune the HFINTOSC frequency using calculated time, the internal oscillator block is running USB or secondary oscillator sources using the active too fast; to compensate, decrement the OSCTUNE clock tuning module (see Section3.15 “Active Clock register. If the measured time is much less than the Tuning (ACT) Module”). The HFINTOSC frequency calculated time, the internal oscillator block is running may be manually adjusted using the TUN<6:0> bits in too slow; to compensate, increment the OSCTUNE the OSCTUNE register. This has no effect on the INTRC register. clock source frequency. Manually tuning the HFINTOSC source requires knowing when to make the adjustment, in which direction it should be made and, in some cases, how large a change is needed. Three possible compensation techniques are discussed in the following sections. However, other techniques may be used.  2012-2014 Microchip Technology Inc. DS30000684B-page 39

PIC18(L)F2X/45K50 3.8 PLL Frequency Multiplier 3.9 Effects of Power-Managed Modes on the Various Clock Sources A Phase-Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency For more information about the modes discussed in this oscillator circuit or to clock the device up to its highest section see Section4.0 “Power-Managed Modes”. A rated frequency from the crystal oscillator. This may be quick reference list is also available in Table4-1. useful for customers who are concerned with EMI due When PRI_IDLE mode is selected, the designated to high-frequency crystals or users who require higher primary oscillator continues to run without interruption. clock speeds from an internal oscillator. For all other power-managed modes, the oscillator 3.8.1 PLL IN EXTERNAL OSCILLATOR using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. MODES In secondary clock modes (SEC_RUN and The PLL can be enabled for any of the external SEC_IDLE), the secondary oscillator (SOSC) is oscillator modes using the OSC1/OSC2 pins. Medium- operating and providing the device clock. The power and low-power oscillator mode selections in secondary oscillator may also run in all power- CONFIG1H<3:0> (FOSC) should not be used with the managed modes if required to clock Timer1 or Timer3. PLL. The PLL can be enabled using the CFGPLLEN/ In internal oscillator modes (INTOSC_RUN and PLLSEL configuration bits in the CONFIG1L register, INTOSC_IDLE), the internal oscillator block provides or by software using the PLLEN/SPLLMULT special the device clock source. The 31.25kHz INTRC output function register bits in OSCCON2 and OSCTUNE, can be used directly to provide the clock and may be respectively. enabled to support various special features, regardless A selectable 3x or 4x frequency multiplier circuit is of the power-managed mode (see Section26.3 provided. This gives greater flexibility in source clock “Watchdog Timer (WDT)”, Section3.12 “Two- Speed Clock Start-up Mode” and Section3.13 “Fail- frequencies that can be used. Source clock Safe Clock Monitor” for more information on WDT, frequencies between 8 and 12 MHz may use the 4x Fail-Safe Clock Monitor and Two-Speed Start-up). The frequency multiplier to achieve operating speeds of 32 HFINTOSC output may be used directly to clock the through 48 MHz. A source clock frequency of 16 MHz device or may be divided down by the postscaler. The may use the 3x frequency multiplier to achieve 48 HFINTOSC output is disabled when the clock is MHz operating speed. provided directly from the INTRC output. 3.8.2 PLL IN HFINTOSC MODES When the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents The PLL can be enabled using the HFINTOSC internal have been stopped, Sleep mode achieves the lowest oscillator block. The frequency select bits (IRCF<2:0> current consumption of the device (only leakage in the OSCCON register) should be configured for 16 currents). MHz when using the HFINTOSC with 3x frequency multiplier. The IRCF bits should be configured for 8 Enabling any on-chip feature that will operate during MHz when using HFINTOSC with 4x frequency Sleep will increase the current consumed during Sleep. multiplier. The INTRC is required to support WDT operation. Other features may be operating that do not require a device clock source (i.e., SSP slave, INTn pins and others). Peripherals that may add significant current consumption are listed in Table29-8. DS30000684B-page 40  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 3.10 Power-up Delays There is a delay of interval TCSD, following POR, while the controller becomes ready to execute instructions. Power-up delays are controlled by two timers, so that This delay runs concurrently with any other delays. no external Reset circuitry is required for most This may be the only delay that occurs when any of the applications. The delays ensure that the device is kept EC, RC or INTIOSC modes are used as the primary in Reset until the device power supply is stable under clock source. normal circumstances and the primary clock is When the HFINTOSC is selected as the primary clock, operating and stable. For additional information on the main system clock can be delayed until the power-up delays, see Section5.7 “Device Reset HFINTOSC is stable. This is user selectable by the Timers”. HFOFST bit of the CONFIG3H Configuration register. The first timer is the Power-up Timer (PWRT), which When the HFOFST bit is cleared, the main system provides a fixed delay on power-up. It is enabled by clock is delayed until the HFINTOSC is stable. When clearing (= 0) the PWRTEN Configuration bit. the HFOFST bit is set, the main system clock starts The second timer is the Oscillator Start-up Timer immediately. (OST), intended to keep the chip in Reset until the In either case, the HFIOFS bit of the OSCCON register crystal oscillator is stable (LP, XT and HS modes). The can be read to determine whether the HFINTOSC is OST does this by counting 1024 oscillator cycles operating and stable. before allowing the oscillator to clock the device. When the PLL is enabled with external oscillator modes, the device runs off of the base external oscilla- tor for 2ms, following the OST delay, so the PLL can lock to the incoming clock frequency. TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTOSC with CLKO Floating, external resistor should pull high At logic low (clock/4 output) RC with IO Floating, external resistor should pull high Configured as PORTA, bit 6 INTOSC with IO Configured as PORTA, bit 7 Configured as PORTA, bit 6 EC with IO Floating, pulled by external clock Configured as PORTA, bit 6 EC with CLKO Floating, pulled by external clock At logic low (clock/4 output) LP, XT, HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table5-2 in Section5.0 “Reset” for time-outs due to Sleep and MCLR Reset.  2012-2014 Microchip Technology Inc. DS30000684B-page 41

PIC18(L)F2X/45K50 3.11 Clock Switching 3.11.3 CLOCK SWITCH TIMING The system clock source can be switched between When switching between one oscillator and another, external and internal clock sources via software using the new oscillator may not be operating which saves the System Clock Select (SCS<1:0>) bits of the power (see Figure3-8). If this is the case, there is a OSCCON register. delay after the SCS<1:0> bits of the OSCCON register are modified before the frequency change takes place. PIC18(L)F2X/45K50 devices contain circuitry to The OSTS and HFIOFR, LFIOFS bits of the OSCCON prevent clock “glitches” when switching between clock and OSCCON2 registers will reflect the current active sources. A short pause in the device clock occurs status of the external and HFINTOSC oscillators. The during the clock switch. The length of this pause is the timing of a frequency selection is as follows: sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula 1. SCS<1:0> bits of the OSCCON register are assumes that the new clock source is stable. modified. 2. The old clock continues to operate until the new Clock transitions are discussed in greater detail in clock is ready. Section4.1.2 “Entering Power-Managed Modes”. 3. Clock switch circuitry waits for two consecutive 3.11.1 SYSTEM CLOCK SELECT rising edges of the old clock after the new clock (SCS<1:0>) BITS ready signal goes true. 4. The system clock is held low starting at the next The System Clock Select (SCS<1:0>) bits of the falling edge of the old clock. OSCCON register select the system clock source that is used for the CPU and peripherals. 5. Clock switch circuitry waits for an additional two rising edges of the new clock. • When SCS<1:0> = 00, the system clock source is 6. On the next falling edge of the new clock the low determined by configuration of the FOSC<3:0> hold on the system clock is released and new bits in the CONFIG1H Configuration register. clock is switched in as the system clock. • When SCS<1:0> = 10, the system clock source is 7. Clock switch is complete. chosen by the internal oscillator frequency selected by the INTSRC bit of the OSCCON2<5> See Figure3-1 for more details. register and the IRCF<2:0> bits of the OSCCON If the HFINTOSC is the source of both the old and new register. frequency, there is no start-up delay before the new • When SCS<1:0> = 01, the system clock source is frequency is active. This is because the old and new the 32.768 kHz secondary oscillator shared with frequencies are derived from the HFINTOSC via the Timer1 and Timer3. postscaler and multiplexer. After a Reset, the SCS<1:0> bits of the OSCCON Start-up delay specifications are located in register are always cleared. Section29.0 “Electrical Specifications”, under AC Specifications (Oscillator Module). Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail- Safe Clock Monitor, does not update the SCS<1:0> bits of the OSCCON register. The user can monitor the SOSCRUN and LFIOFS bits of the OSCCON2 register, and the HFIOFS and OSTS bits of the OSCCON register to determine the current system clock source. 3.11.2 OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCCON register indicates whether the system clock is running from the external clock source, as defined by the FOSC<3:0> bits in the CONFIG1H Configuration register, or from the internal clock source. In particular, when the primary oscillator is the source of the primary clock, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. DS30000684B-page 42  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 3.12 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the HFINTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear. When the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section3.5.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit of the OSCCON register is set, program execution switches to the external oscillator. 3.12.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is enabled when all of the following settings are configured as noted: • Two-Speed Start-up mode is enabled when the IESO of the CONFIG1H Configuration register is set. • SCS<1:0> (of the OSCCON register) = 00. • FOSC<2:0> bits of the CONFIG1H Configuration register are configured for LP, XT or HS mode. Two-Speed Start-up mode becomes active after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep.  2012-2014 Microchip Technology Inc. DS30000684B-page 43

PIC18(L)F2X/45K50 3.12.2 TWO-SPEED START-UP 3.12.3 CHECKING TWO-SPEED CLOCK SEQUENCE STATUS 1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCCON 2. Instructions begin executing by the internal register will confirm if the microcontroller is running oscillator at the frequency set in the IRCF<2:0> from the external clock source, as defined by the bits of the OSCCON register. FOSC<2:0> bits in CONFIG1H Configuration register, or the internal oscillator. OSTS = 0 when the external 3. OST enabled to count 1024 external clock oscillator is not ready, which indicates that the system cycles. is running from the internal oscillator. 4. OST timed out. External clock is ready. 5. OSTS is set. 6. Clock switch finishes according to Figure3-8 FIGURE 3-8: CLOCK SWITCH TIMING High Speed Low Speed Old Clock Start-up Time(1) Clock Sync Running New Clock New Clk Ready IRCF <2:0> Select Old Select New System Clock Low Speed High Speed Old Clock Start-up Time(1) Clock Sync Running New Clock New Clk Ready IRCF <2:0>Select Old Select New System Clock Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode. DS30000684B-page 44  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 3.13 Fail-Safe Clock Monitor 3.13.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared by either one of the to continue operating should the external oscillator fail. following: The FSCM can detect oscillator failure any time after • Any Reset the Oscillator Start-up Timer (OST) has expired. The • By toggling the SCS1 bit of the OSCCON register FSCM is enabled by setting the FCMEN bit in the Both of these conditions restart the OST. While the CONFIG1H Configuration register. The FSCM is OST is running, the device continues to operate from applicable to all external oscillator modes (LP, XT, HS, the INTOSC selected in OSCCON. When the OST EC, RC and RCIO). times out, the Fail-Safe condition is cleared and the device automatically switches over to the external clock FIGURE 3-9: FSCM BLOCK DIAGRAM source. The Fail-Safe condition need not be cleared before the OSCFIF flag is cleared. Clock Monitor Latch External 3.13.4 RESET OR WAKE-UP FROM SLEEP S Q Clock The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after INTRC Oscillator ÷ 64 R Q any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as 31 kHz 488 Hz soon as the Reset or wake-up has completed. (~32 s) (~2 ms) Note: Due to the wide range of oscillator start-up Sample Clock Clock times, the Fail-Safe circuit is not active Failure during oscillator start-up (i.e., after exiting Detected Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify 3.13.1 FAIL-SAFE DETECTION the oscillator start-up and that the system The FSCM module detects a failed oscillator by clock switchover has successfully comparing the external oscillator to the FSCM sample completed. clock. The sample clock is generated by dividing the INTRC by 64 (see Figure3-9). Inside the fail detector block is a latch. The external clock sets the latch on Note: When the device is configured for Fail- each falling edge of the external clock. The sample Safe clock monitoring in either HS, XT, or clock clears the latch on each rising edge of the sample LS oscillator modes then the IESO config- clock. A failure is detected when an entire half-cycle of uration bit should also be set so that the the sample clock elapses before the primary clock goes clock will automatically switch from the low. internal clock to the external oscillator when the OST times out. 3.13.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSCFIF of the PIR2 register. The OSCFIF flag will generate an interrupt if the OSCFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. An automatic transition back to the failed clock source will not occur. The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2012-2014 Microchip Technology Inc. DS30000684B-page 45

PIC18(L)F2X/45K50 FIGURE 3-10: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 3-4: REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 OSCCON IDLEN IRCF<2:0> OSTS HFIOFS SCS<1:0> 33 OSCCON2 PLLRDY SOSCRUN INTSRC PLLEN SOSCGO PRISD HFIOFR LFIOFS 34 OSCTUNE SPLLMULT TUN<6:0> 38 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by clock sources. TABLE 3-5: CONFIGURATION REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG1H IESO FCMEN PCLKEN — FOSC<3:0> 373 CONFIG2L — LPBOR — BORV<1:0> BOREN<1:0> PWRTEN 374 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for clock sources. DS30000684B-page 46  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 3.14 Oscillator Settings for USB 3.14.1 LOW-SPEED OPERATION When the PIC18(L)F2X/45K50 family devices are used The USB clock for Low-Speed mode is derived from the for USB connectivity, a 6 MHz or 48 MHz clock must be primary oscillator or from the PLL. In order to operate provided to the USB module for operation in either the USB module in Low-Speed mode, a 6MHz clock Low-Speed or Full-Speed modes, respectively. This must be provided to the USB module. may require some forethought in selecting an oscillator See Table3-6 and Table3-7 for possible combinations frequency and programming the device. which can be used for low-speed USB operation. The full range of possible oscillator configurations compatible with USB operation is shown in Table3-7. TABLE 3-6: CLOCK FOR LOW-SPEED USB System Clock CPUDIV<1:0> Microcontroller Clock LS48MHZ USB Clock 48 11 48/6 = 8 MHz 1 48/8 = 6 MHz 48 10 48/3 = 16 MHz 1 48/8 = 6 MHz 48 01 48/2 = 24 MHz 1 48/8 = 6 MHz 48 00 48 MHz 1 48/8 = 6 MHz 24 11 24/6 = 4 MHz 0 24/4 = 6 MHz 24 10 24/3 = 8 MHz 0 24/4 = 6 MHz 24 01 24/2 = 12 MHz 0 24/4 = 6 MHz 24 00 24 MHz 0 24/4 = 6 MHz TABLE 3-7: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION Input Clock Mode MCU Clock Division Microcontroller Oscillator Frequency (FOSC<3:0>) (CPUDIV<1:0>) Clock Frequency 6 (11) 8MHz 3 (10) 16MHz 48MHz EC 2 (01) 24MHz None (00) 48MHz 6 (11) 8MHz EC, HS or INTOSC with 3 (10) 16MHz 16MHz 3xPLL 2 (01) 24MHz None (00) 48MHz 6 (11) 8MHz 3 (10) 16MHz 12MHz EC or HS with 4xPLL 2 (01) 24MHz None (00) 48MHz 6 (11) 4MHz 3 (10) 8MHz 24MHz EC or HS(1) 2 (01) 12MHz None (00) 24MHz Note 1: The 24 MHz mode (without PLL) is only compatible with low-speed USB. Full-speed USB requires a 48 MHz system clock.  2012-2014 Microchip Technology Inc. DS30000684B-page 47

PIC18(L)F2X/45K50 3.15 Active Clock Tuning (ACT) Module 3.17 Active Clock Tuning Source Selection The Active Clock Tuning (ACT) module continuously adjusts the 16MHz internal oscillator, using an The ACT reference clock is selected with the ACTSRC available external reference, to achieve ±0.20% bit of the ACTCON register. The reference clock accuracy. This eliminates the need for a high-speed, sources are provided by the: high-accuracy external crystal when the system has an • USB module in full-speed operation (ACT_clk) available lower speed, lower power, high-accuracy clock source available. • Secondary clock at 32.768 kHz (SOSC_clk) Systems implementing a Real-Time Clock Calendar 3.18 ACT Lock Status (RTCC) or a full-speed USB application can take full advantage of the ACT module. The ACTLOCK bit will be set to ‘1’, when the 16MHz internal oscillator is successfully tuned. 3.16 Active Clock Tuning Operation The bit will be cleared by the following conditions: The ACT module defaults to the disabled state after • Out of Lock condition any Reset. When the ACT module is disabled, the user • Device Reset can write to the TUN<6:0> bits in the OSCTUNE • Module is disabled register to manually adjust the 16MHz internal oscillator. 3.19 ACT Out-of-Range Status The module is enabled by setting the ACTEN bit of the ACTCON register. When enabled, the ACT module If the ACT module requires an OSCTUNE value takes control of the OSCTUNE register. The ACT outside the range to achieve ± 0.20% accuracy, then module uses the selected ACT reference clock to tune the ACT Out-of-Range (ACTORS) Status bit will be set the 16MHz internal oscillator to an accuracy of 16 MHz to ‘1’. ±0.2%. The tuning automatically adjusts the An out-of-range status can occur: OSCTUNE register every reference clock cycle. • When the 16MHZ internal oscillator is tuned to its lowest frequency and the next ACT_clk event Note1: When the ACT module is enabled, the requests a lower frequency. OSCTUNE register is only updated by • When the 16MHZ internal oscillator is tuned to its the module. Writes to the OSCTUNE highest frequency and the next ACT_clk event register by the user are inhibited, but requests a higher frequency. reading the register is permitted. When the ACT out-of-range event occurs, the 16MHz 2: After disabling the ACT module, the user internal oscillator will continue to use the last written should wait three instructions before OSCTUNE value. When the OSCTUNE value moves writing to the OSCTUNE register. back within the tunable range and ACTLOCK is established, the ACTORS bit is cleared to ‘0’. FIGURE 3-11: ACTIVE CLOCK TUNING BLOCK DIAGRAM ACTSRC ACTEN FSUSB_clk 1 Enable ACT_clk 16 MHz Internal OSC SOSC_clk 0 Active Clock Tuning Module ACT data sfr data 7 7 Write OSCTUNE<6:0> OSCTUNE ACTUD ACTEN ACTEN DS30000684B-page 48  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 3.20 Active Clock Tuning Update Disable When the ACT module is enabled, the OSCTUNE register is continuously updated every ACT_clk period. Setting the ACT Update Disable bit can be used to suspend updates to the OSCTUNE register, without disabling the module. If the 16MHz internal oscillator drifts out of the accuracy range, the ACT Status bits will change and an interrupt can be generated to notify the application. Clearing the ACTUD bit will engage the ACT updates to OSCTUNE and an interrupt can be generated to notify the application. 3.21 Interrupts The ACT module will set the ACT module Interrupt Flag, (ACTIF) when either of the ACT module Status bits (ACTLOCK or ACTORS) change state, regardless if the interrupt is enabled, (ACTIE = 1). The ACTIF and ACTIE bits are in the PIR1 and PIE1 registers, respec- tively. When ACTIE = 1, an interrupt will be generated whenever the ACT module Status bits change. The ACTIF bit must be cleared in software, regardless of the interrupt enable setting. 3.22 Operation during Sleep This ACT module does not run during Sleep and will not generate interrupts during Sleep.  2012-2014 Microchip Technology Inc. DS30000684B-page 49

PIC18(L)F2X/45K50 3.23 Register Definitions: Active Clock Tuning Control REGISTER 3-4: ACTCON: ACTIVE CLOCK TUNING (ACT) CONTROL REGISTER R/W-0/0 R/W-0/0 U-0 R/W-0/0 R-0/0 U-0 R-0/0 U-0 ACTEN ACTUD — ACTSRC(1) ACTLOCK — ACTORS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACTEN: Active Clock Tuning Selection bit 1 = ACT module is enabled, updates to OSCTUNE are exclusive to the ACT module. 0 = ACT module is disabled bit 6 ACTUD: Active Clock Tuning Update Disable bit 1 = Updates to the OSCTUNE register from ACT module are disabled. 0 = Updates to the OSCTUNE register from ACT module are enabled. bit 5 Unimplemented: Read as ‘0’ bit 4 ACTSRC: Active Clock Tuning Source Selection bit 1 = The HFINTOSC Oscillator is tuned to approximately match the USB host clock tolerance 0 = The HFINTOSC Oscillator is tuned to approximately match the 32.768 kHz SOSC tolerance bit 3 ACTLOCK: Active Clock Tuning Lock Status bit 1 = Locked; 16 MHz internal oscillator is within ±0.20%.Locked 0 = Not locked; 16 MHz internal oscillator tuning has not stabilized within ±0.20% bit 2 Unimplemented: Read as ‘0’ bit 1 ACTORS: Active Clock Tuning Out-of-Range Status bit 1 = Out-of-range; oscillator frequency is outside of the OSCTUNE range 0 = In-range; oscillator frequency is within the OSCTUNE range bit 0 Unimplemented: Read as ‘0’ Note 1: The ACTSRC bit should only be changed when ACTEN = 0. DS30000684B-page 50  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 3-8: SUMMARY OF REGISTERS ASSOCIATED WITH ACT SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page ACTCON ACTEN ACTUD — ACTSRC ACTLOCK — ACTORS — 50 OSCCON IDLEN IRCF<2:0> OSTS HFIOFS SCS<1:0> 33 OSCTUNE SPLLMULT TUN<6:0> 38 OSCCON2 PLLRDY SOSCRUN INTSRC PLLEN SOSCGO PRISD HFIOFR LFIOFS 34 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC RD16 TMR1ON 165 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. TABLE 3-9: SUMMARY OF CONFIGURATION WORD WITH ACT SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG1H IESO FCMEN PCLKEN — FOSC<3:0> 373  2012-2014 Microchip Technology Inc. DS30000684B-page 51

PIC18(L)F2X/45K50 4.0 POWER-MANAGED MODES 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three PIC18(L)F2X/45K50 devices offer a total of seven clock sources for power-managed modes. They are: operating modes for more efficient power management. These modes provide a variety of • the primary clock, as defined by the FOSC<3:0> options for selective power conservation in applications Configuration bits where resources may be limited (i.e., battery-powered • the secondary clock (the SOSC oscillator) devices). • the internal oscillator block There are three categories of power-managed modes: 4.1.2 ENTERING POWER-MANAGED • Run modes MODES • Idle modes Switching from one power-managed mode to another • Sleep mode begins by loading the OSCCON register. The These categories define which portions of the device SCS<1:0> bits select the clock source and determine are clocked and sometimes, what speed. The Run and which Run or Idle mode is to be used. Changing these Idle modes may use any of the three available clock bits causes an immediate switch to the new clock sources (primary, secondary or internal oscillator source, assuming that it is running. The switch may block). The Sleep mode does not use a clock source. also be subject to clock transition delays. Refer to The power-managed modes include several power- Section3.11 “Clock Switching” for more information. saving features offered on previous PIC® microcontroller Entry to the power-managed Idle or Sleep modes is devices. One of the clock switching features allows the triggered by the execution of a SLEEP instruction. The controller to use the secondary oscillator (SOSC) in actual mode that results depends on the status of the place of the primary oscillator. Also included is the Sleep IDLEN bit. mode, offered by all PIC microcontroller devices, where Depending on the current mode and the mode being all device clocks are stopped. switched to, a change to a power-managed mode does not always require setting all of these bits. Many 4.1 Selecting Power-Managed Modes transitions may be done by changing the oscillator select Selecting a power-managed mode requires two bits, or changing the IDLEN bit, prior to issuing a SLEEP decisions: instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP • Whether or not the CPU is to be clocked instruction to switch to the desired mode. • The selection of a clock source The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table4-1. TABLE 4-1: POWER-MANAGED MODES OSCCON Bits Module Clocking Mode Available Clock and Oscillator Source IDLEN(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, RC, EC and Internal Oscillator Block(2). This is the normal full-power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – SOSC Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – SOSC Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes HFINTOSC and HFINTOSC postscaler, as well as the INTRC source. DS30000684B-page 52  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 4.1.3 MULTIPLE FUNCTIONS OF THE Figure4-2). When the clock switch is complete, the SLEEP COMMAND SOSCRUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and The power-managed mode that is invoked with the SCS bits are not affected by the wake-up and the SLEEP instruction is determined by the value of the SOSC oscillator continues to run. IDLEN bit at the time the instruction is executed. If IDLEN = 0, when SLEEP is executed, the device enters the sleep mode and all clocks stop and minimum power 4.2.3 RC_RUN MODE is consumed. If IDLEN = 1, when SLEEP is executed, In RC_RUN mode, the CPU and peripherals are the device enters the IDLE mode and the system clock clocked from the internal oscillator block using the continues to supply a clock to the peripherals but is INTOSC multiplexer. In this mode, the primary clock is disconnected from the CPU. shut down. When using the INTRC source, this mode provides the best power conservation of all the Run 4.2 Run Modes modes, while still executing code. It works well for user applications which are not highly timing-sensitive or do In the Run modes, clocks to both the core and not require high-speed clocks at all times. If the primary peripherals are active. The difference between these clock source is the internal oscillator block – either modes is the clock source. INTRC or HFINTOSC – there are no distinguishable 4.2.1 PRI_RUN MODE differences between the PRI_RUN and RC_RUN modes during execution. Entering or exiting RC_RUN The PRI_RUN mode is the normal, full-power mode, however, causes a clock switch delay. execution mode of the microcontroller. This is also the Therefore, if the primary clock source is the internal default mode upon a device Reset, unless Two-Speed oscillator block, using RC_RUN mode is not Start-up is enabled (see Section3.12 “Two-Speed recommended. Clock Start-up Mode” for details). In this mode, the This mode is entered by setting the SCS1 bit to ‘1’. To device is operated off the oscillator defined by the maintain software compatibility with future devices, it is FOSC<3:0> bits of the CONFIG1H Configuration recommended that the SCS0 bit also be cleared, even register. though the bit is ignored. When the clock source is 4.2.2 SEC_RUN MODE switched to the INTOSC multiplexer (see Figure4-1), the primary oscillator is shut down and the OSTS bit is In SEC_RUN mode, the CPU and peripherals are cleared. The IRCF<2:0> bits (OSCCON<6:4>) may be clocked from the secondary external oscillator. This modified at any time to immediately change the clock gives users the option of lower power consumption speed. while still using a high accuracy clock source. When the IRCF bits and the INTSRC bit are all clear, SEC_RUN mode is entered by setting the SCS<1:0> the INTOSC output (HFINTOSC) is not enabled and bits to ‘01’. When SEC_RUN mode is active, all of the the HFIOFS bit will remain clear. There will be no indi- following are true: cation of the current clock source. The INTRC source • The device clock source is switched to the SOSC is providing the device clocks. oscillator (see Figure4-1) If the IRCF bits are changed from all clear (thus, • The primary oscillator is shut down enabling the INTOSC output) or if INTSRC is set, then • The SOSCRUN bit (OSCCON2<6>) is set the HFIOFS bit is set after the INTOSC output becomes • The OSTS bit (OSCCON<3>) is cleared stable. For details, see Table4-2. Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST. Note: The secondary external oscillator should If the IRCF bits were previously at a non-zero value, or already be running prior to entering if INTSRC was set before setting SCS1 and the SEC_RUN mode. If the SOSCGO bit or INTOSC source was already stable, then the HFIOFS any of the SOSCEN bits are not set when bit will remain set. the SCS<1:0> bits are set to ‘01’, entry to SEC_RUN mode will not occur until the SOSCGO bit is set and secondary external oscillator is ready. On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the SOSC oscillator, while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see  2012-2014 Microchip Technology Inc. DS30000684B-page 53

PIC18(L)F2X/45K50 On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the pri- mary clock occurs (see Figure4-3). When the clock switch is complete, the HFIOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 SOSCI 1 2 3 n-1 n OSC1 Clock Transition(1) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 SOSC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> bits Changed OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS30000684B-page 54  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 4-2: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS IRCF<2:0> INTSRC Selected Oscillator Selected Oscillator Stable when: 000 0 INTRC LFIOFS = 1 000 1 HFINTOSC HFIOFS = 1 001-111 x HFINTOSC HFIOFS = 1 FIGURE 4-3: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> bits Changed OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC.  2012-2014 Microchip Technology Inc. DS30000684B-page 55

PIC18(L)F2X/45K50 4.3 Sleep Mode 4.3.1 VOLTAGE REGULATOR POWER MODE The Power-Managed Sleep mode in the PIC18(L)F2X/ 45K50 devices is identical to the legacy Sleep mode On F devices, an internal voltage regulator provides offered in all other PIC microcontroller devices. It is power to the internal core logic of the chip. During entered by clearing the IDLEN bit of the OSCCON Sleep mode, the internal voltage regulator can be put register and executing the SLEEP instruction. This shuts into a lower-power mode, in exchange for longer down the selected oscillator (Figure4-4) and all clock wake-up time. Similarly, the internal band gap voltage source status bits are cleared. reference may be turned off during Sleep for lower- Entering the Sleep mode from either Run or Idle mode power consumption. See Register4-1. does not require a clock switch. This is because no On LF devices, the internal core logic operates from clocks are needed once the controller has entered VDD and the internal voltage regulator is bypassed. The Sleep. If the WDT is selected, the INTRC source will VREGCON register is, thus, not implemented on LF continue to operate. If the SOSC oscillator is enabled, devices. it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure4-5), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section26.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. REGISTER 4-1: VREGCON – VOLTAGE REGULATOR POWER CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 R-0 R/W-0/0 R/W-0/0 — — — — — — VREGPM<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit x = Bit is unknown -n/n = Value at POR and BOR/Value at all other resets ‘0’ = Bit is cleared ‘1’ = bit is set U = Unimplemented bit, read as ‘0’ bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 VREGPM<1:0>: Voltage Regulator Power mode bits 11 = Band gap not forced in Sleep; LDO off in Sleep; ULP Regulator active 10 = Band gap forced in Sleep; LDO off in Sleep; ULP Regulator active 01 = LDO in Low-Power mode in Sleep, if no peripherals require High-Power mode. 00 = LDO in High-Power mode – always Note 1: Reset state depends on state of the IESO Configuration bit. 2: Default output frequency of HFINTOSC on Reset. DS30000684B-page 56  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 4.4 Idle Modes Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT The Idle modes allow the controller’s CPU to be time-out, or a Reset. When a wake event occurs, CPU selectively shut down while the peripherals continue to execution is delayed by an interval of TCSD while it operate. Selecting a particular Idle mode allows users becomes ready to execute code. When the CPU to further manage power consumption. begins executing code, it resumes with the same clock If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is source for the current Idle mode. For example, when executed, the peripherals will be clocked from the clock waking from RC_IDLE mode, the internal oscillator source selected by the SCS<1:0> bits; however, the CPU block will clock the CPU and peripherals (in other will not be clocked. The clock source status bits are not words, RC_RUN mode). The IDLEN and SCS bits are affected. Setting IDLEN and executing a SLEEP instruc- not affected by the wake-up. tion provides a quick method of switching from a given While in any Idle mode or the Sleep mode, a WDT Run mode to its corresponding Idle mode. time-out will result in a WDT wake-up to the Run mode If the WDT is selected, the INTRC source will continue currently specified by the SCS<1:0> bits. to operate. If the SOSC oscillator is enabled, it will also continue to run. FIGURE 4-4: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 4-5: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS bit set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 4.4.1 PRI_IDLE MODE to be clocked from the primary clock source specified by the FOSC<3:0> Configuration bits. The OSTS bit This mode is unique among the three low-power Idle remains set (see Figure4-6). modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for When a wake event occurs, the CPU is clocked from the the fastest resumption of device operation with its more primary clock source. A delay of interval TCSD is accurate primary clock source, since the clock source required between the wake event and when code does not have to “warm-up” or transition from another execution starts. This is required to allow the CPU to oscillator. become ready to execute instructions. After the wake- up, the OSTS bit remains set. The IDLEN and SCS bits PRI_IDLE mode is entered from PRI_RUN mode by are not affected by the wake-up (see Figure4-7). setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue  2012-2014 Microchip Technology Inc. DS30000684B-page 57

PIC18(L)F2X/45K50 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the SOSC oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS<1:0> bits to ‘01’ and execute SLEEP. When the clock source is switched to the SOSC oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the SOSCRUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the SOSC oscillator. After an interval of TCSD following the wake event, the CPU begins exe- cuting code being clocked by the SOSC oscillator. The IDLEN and SCS bits are not affected by the wake-up; the SOSC oscillator continues to run (see Figure4-7). Note: The SOSC oscillator should already be running prior to entering SEC_IDLE mode. At least one of the secondary oscil- lator enable bits (SOSCEN, T1CON<3> or T3CON<3>) must be set when the SLEEP instruction is executed. Otherwise, the main system clock will continue to operate in the previously selected mode and the corresponding IDLE mode will be entered (i.e., PRI_IDLE or RC_IDLE). FIGURE 4-6: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 4-7: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event DS30000684B-page 58  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 4.4.3 RC_IDLE MODE 4.5 Exiting Idle and Sleep Modes In RC_IDLE mode, the CPU is disabled but the periph- An exit from Sleep mode or any of the Idle modes is erals continue to be clocked from the internal oscillator triggered by any one of the following: block from the HFINTOSC multiplexer output. This • an interrupt mode allows for controllable power conservation during Idle periods. • a Reset • a Watchdog Time-out From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the This section discusses the triggers that cause exits device is in another Run mode, first set IDLEN, then set from power-managed modes. The clocking subsystem the SCS1 bit and execute SLEEP. It is recommended actions are discussed in each of the power-managed that SCS0 also be cleared, although its value is modes (see Section4.2 “Run Modes”, Section4.3 ignored, to maintain software compatibility with future “Sleep Mode” and Section4.4 “Idle Modes”). devices. The HFINTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF 4.5.1 EXIT BY INTERRUPT bits before executing the SLEEP instruction. When the Any of the available interrupt sources can cause the clock source is switched to the HFINTOSC multiplexer, device to exit from an Idle mode or the Sleep mode to the primary oscillator is shut down and the OSTS bit is a Run mode. To enable this functionality, an interrupt cleared. source must be enabled by setting its enable bit in one If the IRCF bits are set to any non-zero value, or the of the INTCON or PIE registers. The exit sequence is INTSRC bits are set, the HFINTOSC output is enabled. initiated when the corresponding interrupt flag bit is set. The HFIOFS bit becomes set after the HFINTOSC The instruction immediately following the SLEEP output stabilizes after an interval of TIOBST. For instruction is executed on all exits by interrupt from Idle information on the HFIOFS bit, see Table4-2. or Sleep modes. Code execution then branches to the Clocks to the peripherals continue while the interrupt vector if the GIE/GIEH bit of the INTCON HFINTOSC source stabilizes. The HFIOFS bit will register is set, otherwise code execution continues remain set if the IRCF bits were previously set at a non- without branching (see Section10.0 “Interrupts”). zero value or if INTSRC was set before the SLEEP A fixed delay of interval TCSD following the wake event instruction was executed and the HFINTOSC source is required when leaving Sleep and Idle modes. This was already stable. If the IRCF bits and INTSRC are all delay is required for the CPU to prepare for execution. clear, the HFINTOSC output will not be enabled, the Instruction execution resumes on the first clock cycle HFIOFS bit will remain clear and there will be no following this delay. indication of the current clock source. 4.5.2 EXIT BY WDT TIME-OUT When a wake event occurs, the peripherals continue to be clocked from the HFINTOSC multiplexer output. A WDT time-out will cause different actions depending After a delay of TCSD following the wake event, the CPU on which power-managed mode the device is in when begins executing code being clocked by the the time-out occurs. HFINTOSC multiplexer. The IDLEN and SCS bits are If the device is not executing code (all Idle modes and not affected by the wake-up. The INTRC source will Sleep mode), the time-out will result in an exit from the continue to run if either the WDT or the Fail-Safe Clock power-managed mode (see Section4.2 “Run Monitor is enabled. Modes” and Section4.3 “Sleep Mode”). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section26.3 “Watchdog Timer (WDT)”). The WDT timer and postscaler are cleared by any one of the following: • executing a SLEEP instruction • executing a CLRWDT instruction • the loss of the currently selected clock source when the Fail-Safe Clock Monitor is enabled • modifying the IRCF bits in the OSCCON register when the internal oscillator block is the device clock source  2012-2014 Microchip Technology Inc. DS30000684B-page 59

PIC18(L)F2X/45K50 4.5.3 EXIT BY RESET 4.6 Selective Peripheral Module Control Exiting Sleep and Idle modes by Reset causes code execution to restart at address 0. See Section5.0 Idle mode allows users to substantially reduce power “Reset” for more details. consumption by stopping the CPU clock. Even so, The exit delay time from Reset to the start of code peripheral modules still remain clocked, and thus, con- execution depends on both the clock sources before sume power. There may be cases where the applica- and after the wake-up and the type of oscillator. tion needs what IDLE mode does not provide: the allocation of power resources to the CPU processing 4.5.4 EXIT WITHOUT AN OSCILLATOR with minimal power consumption from the peripherals. START-UP DELAY PIC18(L)F2X/45K50 family devices address this Certain exits from power-managed modes do not requirement by allowing peripheral modules to be invoke the OST at all. There are two cases: selectively disabled, reducing or eliminating their power consumption. This can be done with control bits • PRI_IDLE mode, where the primary clock source in the Peripheral Module Disable (PMD) registers. is not stopped and These bits generically named XXXMD are located in • the primary clock source is not any of the LP, XT, control registers PMD0 or PMD1. HS or HSPLL modes. Setting the PMD bit for a module disables all clock In these instances, the primary clock source either sources to that module, reducing its power does not require an oscillator start-up delay since it is consumption to an absolute minimum. In this state, already running (PRI_IDLE), or normally does not power to the control and status registers associated require an oscillator start-up delay (RC, EC, INTOSC, with the peripheral is removed. Writes to these and INTOSCIO modes). However, a fixed delay of registers have no effect and read values are invalid. interval TCSD following the wake event is still required Clearing a set PMD bit restores power to the when leaving Sleep and Idle modes to allow the CPU associated control and status registers, thereby setting to prepare for execution. Instruction execution resumes those registers to their default values. on the first clock cycle following this delay. DS30000684B-page 60  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 4.7 Register Definitions: Peripheral Module Disable REGISTER 4-2: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’. bit 6 UARTMD: UART Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 5 USBMD: USB Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 4 ACTMD: Active Clock Tuning Peripheral Module Disable Control bit 1 = Module is disabled and does not draw any digital power 0 = Module is enabled and available for use; will draw digital power bit 3 Unimplemented: Read as ‘0’. bit 2 TMR3MD: Timer3 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 1 TMR2MD: Timer2 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 0 TMR1MD: Timer1 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power  2012-2014 Microchip Technology Inc. DS30000684B-page 61

PIC18(L)F2X/45K50 REGISTER 4-3: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 MSSPMD: MSSP Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 5 CTMUMD: CTMU Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 4 CMP2MD: Comparator 2 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 3 CMP1MD: Comparator 1 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 2 ADCMD: Analog-to-Digital Converter Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 1 CCP2MD: CCP2 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 0 CCP1MD: CCP1 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power DS30000684B-page 62  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 5.0 RESET A simplified block diagram of the On-Chip Reset Circuit is shown in Figure5-1. The PIC18(L)F2X/45K50 devices differentiate between various kinds of Reset: 5.1 RCON Register a) Power-on Reset (POR) Device Reset events are tracked through the RCON b) MCLR Reset during normal operation register (Register5-1). The lower five bits of the c) MCLR Reset during power-managed modes register indicate that a specific Reset event has d) Watchdog Timer (WDT) Reset (during occurred. In most cases, these bits can only be cleared execution) by the event and must be set by the application after e) Programmable Brown-out Reset (BOR) the event. The state of these flag bits, taken together, f) RESET Instruction can be read to indicate the type of Reset that just occurred. This is described in more detail in g) Stack Full Reset Section5.8 “Reset State of Registers”. h) Stack Underflow Reset The RCON register also has control bits for setting This section discusses Resets generated by MCLR, interrupt priority (IPEN) and software control of the POR and BOR and covers the operation of the various BOR (SBOREN). Interrupt priority is discussed in start-up timers. Stack Reset events are covered in Section10.0 “Interrupts”. BOR is covered in Section6.2.1 “Stack Full and Underflow Resets”. Section5.5 “Brown-out Reset (BOR)”. WDT Resets are covered in Section26.3 “Watchdog Timer (WDT)”. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLRE MCLR Idle Sleep WDT Time-out VDD POR Detect VDD Brown-out Reset BOREN S OST/PWRT OST(2) 1024 Cycles Chip_Reset 10-bit Ripple Counter R Q OSC1 32 s PWRT(2) 65.5 ms INTRC 11-bit Ripple Counter Enable PWRT Enable OST(1) Note 1: See Table5-2 for time-out situations. 2: PWRT and OST counters are reset by POR and BOR. See Sections 5.4 and 5.5.  2012-2014 Microchip Technology Inc. DS30000684B-page 63

PIC18(L)F2X/45K50 5.2 Register Definitions: Reset Control REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0/0 R/W-q/u U-0 R/W-1/q R-1/q R-1/q R/W-q/u R/W-0/q IPEN SBOREN(1) — RI TO PD POR(2) BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets x = Bit is unknown u = unchanged q = depends on condition bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN<1:0> = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN<1:0> = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware or Power-on Reset) 0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a code-executed Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit(3) 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs) Note 1: When CONFIG2L[2:1] = 01, then the SBOREN Reset state is ‘1’; otherwise, it is ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section5.8 “Reset State of Registers” for additional information. 3: See Table5-1. Note1: Brown-out Reset is indicated when BOR is ‘0’ and POR is ‘1’ (assuming that both POR and BOR were set to ‘1’ by firmware immediately after POR). 2: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. DS30000684B-page 64  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 5.3 Master Clear (MCLR) FIGURE 5-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering an SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small VDD VDD pulses. An internal weak pull-up is enabled when the pin is configured as the MCLR input. PIC® MCU D R The MCLR pin is not driven low by any internal Resets, R1 including the WDT. MCLR In PIC18(L)F2X/45K50 devices, the MCLR input can C be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section11.6 “PORTE Registers” for more Note 1: External Power-on Reset circuit is required information. only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor 5.4 Power-on Reset (POR) quickly when VDD powers down. A Power-on Reset pulse is generated on-chip 2: 15 k < R < 40k is recommended to make sure that the voltage drop across R does not whenever VDD rises above a certain threshold. This violate the device’s electrical specification. allows the device to start in the initialized state when VDD is adequate for operation. 3: R1  1 k will limit any current flowing into MCLR from external capacitor C, in the event To take advantage of the POR circuitry either leave the of MCLR/VPP pin breakdown, due to pin floating, or tie the MCLR pin through a resistor to Electrostatic Discharge (ESD) or Electrical VDD. This will eliminate external RC components Overstress (EOS). usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified. For a slow rise time, see Figure5-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure proper operation. If these conditions are not met, the device must be held in Reset until the operat- ing conditions are met. POR events are captured by the POR bit of the RCON register. The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user must manually set the bit to ‘1’ by software following any POR.  2012-2014 Microchip Technology Inc. DS30000684B-page 65

PIC18(L)F2X/45K50 5.5 Brown-out Reset (BOR) 5.5.2 SOFTWARE ENABLED BOR PIC18(L)F2X/45K50 devices implement a BOR circuit When BOREN<1:0> = 01, the BOR can be enabled or that provides the user with a number of configuration and disabled by the user in software. This is done with the power-saving options. The BOR is controlled by the SBOREN control bit of the RCON register. Setting BORV<1:0> and BOREN<1:0> bits of the CONFIG2L SBOREN enables the BOR to function as previously Configuration register. There are a total of four BOR described. Clearing SBOREN disables the BOR configurations which are summarized in Table5-1. entirely. The SBOREN bit operates only in this mode; otherwise it is read as ‘0’. The BOR threshold is set by the BORV<1:0> bits. If BOR is enabled (any values of BOREN<1:0>, except Placing the BOR under software control gives the user ‘00’), any drop of VDD below VBOR for greater than the additional flexibility of tailoring the application to the TBOR will reset the device. A Reset may or may not environment without having to reprogram the device to occur if VDD falls below VBOR for less than TBOR. The change BOR configuration. It also allows the user to chip will remain in Brown-out Reset until VDD rises tailor device power consumption in software by above VBOR. eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, If the Power-up Timer is enabled, it will be invoked after it may have some impact in low-power applications. VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT. If VDD drops Note: Even when BOR is under software below VBOR while the Power-up Timer is running, the control, the BOR Reset voltage level is still chip will go back into a Brown-out Reset and the set by the BORV<1:0> Configuration bits. Power-up Timer will be initialized. Once VDD rises It cannot be changed by software. above VBOR, the Power-up Timer will execute the additional time delay. 5.5.3 DISABLING BOR IN SLEEP MODE BOR and the Power-on Timer (PWRT) are When BOREN<1:0> = 10, the BOR remains under independently configured. Enabling BOR Reset does hardware control and operates as previously not automatically enable the PWRT. described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the The BOR circuit has an output that feeds into the POR device returns to any other operating mode, BOR is circuit and rearms the POR within the operating range automatically re-enabled. of the BOR. This early rearming of the POR ensures that the device will remain in Reset in the event that VDD This mode allows for applications to recover from falls below the operating range of the BOR circuitry. brown-out situations, while actively executing code, when the device requires BOR protection the most. At 5.5.1 DETECTING BOR the same time, it saves additional power in Sleep mode When BOR is enabled, the BOR bit always resets to ‘0’ by eliminating the small incremental BOR current. on any BOR or POR event. This makes it difficult to 5.5.4 MINIMUM BOR ENABLE TIME determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to Enabling the BOR also enables the Fixed Voltage simultaneously check the state of both POR and BOR. Reference (FVR) when no other peripheral requiring the This assumes that the POR and BOR bits are reset to FVR is active. The BOR becomes active only after the ‘1’ by software immediately after any POR event. If FVR stabilizes. Therefore, to ensure BOR protection, BOR is ‘0’ while POR is ‘1’, it can be reliably assumed the FVR settling time must be considered when that a BOR event has occurred. enabling the BOR in software or when the BOR is automatically enabled after waking from Sleep. If the BOR is disabled, in software or by reentering Sleep before the FVR stabilizes, the BOR circuit will not sense a BOR condition. The FVRST bit of the VREFCON0 register can be used to determine FVR stability. DS30000684B-page 66  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 5-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN BOR Operation BOREN1 BOREN0 (RCON<6>) 0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR enabled by software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled by hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled by hardware; must be disabled by reprogramming the Configuration bits. 5.6 Low-Power BOR (LPBOR) 5.7.2 OSCILLATOR START-UP TIMER (OST) PIC18(L)F2X/45K50 devices implement a low-power The Oscillator Start-up Timer (OST) provides a 1024 Brown-out Reset circuit (LPBOR). The LPBOR is used oscillator cycle (from OSC1 input) delay after the to monitor the external VDD pin. PWRT delay is over. This ensures that the crystal When low voltage is detected, the device is held in oscillator or resonator has started and stabilized. Reset. When this occurs, the RCON<0> (BOR) bit is The OST time-out is invoked only for XT, LP and HS changed to indicate that a BOR reset has occurred. modes and only on Power-on Reset, or on exit from all This is the same bit in the RCON register that is set for power-managed modes that stop the external oscillator. the traditional BOR. LPBOR provides the user with a lower power BOR 5.7.3 PLL LOCK TIME-OUT option. In exchange for the lower power, the LPBOR With the PLL enabled, the time-out sequence following a circuit trips at a loose voltage range compared to the Power-on Reset is slightly different from other oscillator traditional BOR voltage trip point options. modes. A separate timer is used to provide a fixed time- LPBOR is enabled by the Configuration bit out that is sufficient for the PLL to lock to the main CONFIG2L<6> (LPBOR). The threshold of the LPBOR oscillator frequency. This PLL lock time-out (TPLL) is is not configurable and its range is specified as typically 2 ms and follows the oscillator start-up time-out. parameter D006. 5.7.4 TIME-OUT SEQUENCE 5.7 Device Reset Timers On power-up, the time-out sequence is as follows: PIC18(L)F2X/45K50 devices incorporate three 1. After the POR pulse has cleared, PWRT time-out separate on-chip timers that help regulate the Power- is invoked (if enabled). on Reset process. Their main function is to ensure that 2. Then, the OST is activated. the device clock is stable before code is executed. The total time-out will vary based on oscillator These timers are: configuration and the status of the PWRT. Figure5-3, • Power-up Timer (PWRT) Figure5-4, Figure5-5, Figure5-6 and Figure5-7 all • Oscillator Start-up Timer (OST) depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in • PLL Lock Time-out HS Oscillator mode. Figures 5-3 through 5-6 also 5.7.1 POWER-UP TIMER (PWRT) apply to devices operating in XT or LP modes. For devices in RC mode and with the PWRT disabled, on The Power-up Timer (PWRT) of PIC18(L)F2X/45K50 the other hand, there will be no time-out at all. devices is an 11-bit counter which uses the INTRC Since the time-outs occur from the POR pulse, if MCLR source as the clock input. This yields an approximate is kept low long enough, all time-outs will expire, after time interval of 2048x32s=65.6ms. While the which, bringing MCLR high will allow program PWRT is counting, the device is held in Reset. execution to begin immediately (Figure5-5). This is The power-up time delay depends on the INTRC clock useful for testing purposes or to synchronize more than and will vary from chip-to-chip due to temperature and one PIC MCU device operating in parallel. process variation. The PWRT is enabled by clearing the PWRTEN Configuration bit.  2012-2014 Microchip Technology Inc. DS30000684B-page 67

PIC18(L)F2X/45K50 TABLE 5-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Exit from Configuration Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) — — RC, RCIO 66 ms(1) — — INTOSC, INTOSCIO 66 ms(1) — — Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30000684B-page 68  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  2012-2014 Microchip Technology Inc. DS30000684B-page 69

PIC18(L)F2X/45K50 FIGURE 5-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL  2 ms max. First three stages of the PWRT timer. DS30000684B-page 70  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 5.8 Reset State of Registers Table6-2 describes the Reset states for all of the Special Function Registers. The table identifies Some registers are unaffected by a Reset. Their status differences between Power-On Reset (POR)/Brown- is unknown on POR and unchanged by all other Out Reset (BOR) and all other Resets, (i.e., Master Resets. All other registers are forced to a “Reset state” Clear, WDT Resets, STKFUL, STKUNF, etc.). depending on the type of Reset that occurred. Additionally, the table identifies register bits that are Most registers are not affected by a WDT wake-up, changed when the device receives a wake-up from since this is viewed as the resumption of normal WDT or other interrupts. operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table5-3. These bits are used by software to determine the nature of the Reset. TABLE 5-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter SBOREN RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u(2) 0 u u u u u u Brown-out Reset 0000h u(2) 1 1 1 u 0 u u MCLR during Power-Managed 0000h u(2) u 1 u u u u u Run Modes MCLR during Power-Managed 0000h u(2) u 1 0 u u u u Idle Modes and Sleep Mode WDT Time-out during Full Power 0000h u(2) u 0 u u u u u or Power-Managed Run Mode MCLR during Full Power 0000h u(2) u u u u u u u Execution Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset 0000h u(2) u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u(2) u u u u u u 1 actual Reset, STVREN = 0) WDT Time-out during Power- PC + 2 u(2) u 0 0 u u u u Managed Idle or Sleep Modes Interrupt Exit from Power- PC + 2(1) u(2) u u 0 u u u u Managed Modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled (BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’. TABLE 5-4: REGISTERS ASSOCIATED WITH RESETS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page RCON IPEN SBOREN — RI TO PD POR BOR 64 STKPTR STKFUL STKUNF — STKPTR<4:0> 76 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.  2012-2014 Microchip Technology Inc. DS30000684B-page 71

PIC18(L)F2X/45K50 TABLE 5-5: CONFIGURATION REGISTERS ASSOCIATED WITH RESETS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG2L — LPBOR — BORV<1:0> BOREN<1:0> PWRTEN 374 CONFIG2H — — WDTPS<3:0> WDTEN<1:0> 375 CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 CONFIG4L DEBUG XINST ICPRT — — LVP — STRVEN 377 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets. DS30000684B-page 72  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 6.0 MEMORY ORGANIZATION 6.1 Program Memory Organization There are three types of memory in PIC18 Enhanced PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address will return all ‘0’s (a • Data EEPROM NOP instruction). As Harvard architecture devices, the data and program This family of devices contain the following: memories use separate buses; this allows for • PIC18(L)F24K50: 16Kbytes of Flash memory, up concurrent access of the two memory spaces. The data to 8,192 single-word instructions EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed • PIC18(L)F25K50, PIC18(L)F45K50: 32Kbytes of through a set of control registers. Flash memory, up to 16,384 single-word instructions Additional detailed information on the operation of the Flash program memory is provided in Section7.0 PIC18 devices have two interrupt vectors. The Reset “Flash Program Memory”. Data EEPROM is vector address is at 0000h and the interrupt vector discussed separately in Section8.0 “Data EEPROM addresses are at 0008h and 0018h. Memory”. The program memory map for PIC18(L)F2X/45K50 devices is shown in Figure6-1. Memory block details are shown in Figure21-2. FIGURE 6-1: PROGRAM MEMORY MAP AND STACK FOR PIC18(L)F2X/45K50 DEVICES PC<20:0> CALL,RCALL,RETURN 21 RETFIE,RETLW Stack Level 1    Stack Level 31 Reset Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory On-Chip 3FFFh Program Memory 4000h e c PIC18(L)F24K50 a p S y 7FFFh or 8000h m e M PIC18(L)F25K50 er s U PIC18(L)F45K50 Read ‘0’ Read ‘0’ 1FFFFFh 200000h  2012-2014 Microchip Technology Inc. DS30000684B-page 73

PIC18(L)F2X/45K50 6.1.1 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and is contained in three separate 8-bit registers. The the stack is readable and writable through the Top-of- low byte, known as the PCL register, is both readable Stack (TOS) Special File Registers. Data can also be and writable. The high byte, or PCH register, contains pushed to, or popped from the stack, using these the PC<15:8> bits; it is not directly readable or writable. registers. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack; register contains the PC<20:16> bits; it is also not the Stack Pointer is first incremented and the location directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the register are performed through the PCLATU register. contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred a pop from the stack; the contents of the location to the program counter by any operation that writes pointed to by the STKPTR are transferred to the PC PCL. Similarly, the upper two bytes of the program and then the Stack Pointer is decremented. counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all offsets to the PC (see Section6.2.3.1 “Computed Resets. There is no RAM associated with the location GOTO”). corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is The PC addresses bytes in the program memory. To full or has overflowed or has underflowed. prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to 6.1.2.1 Top-of-Stack Access a value of ‘0’. The PC increments by two to address sequential instructions in the program memory. Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, The CALL, RCALL, GOTO and program branch hold the contents of the stack location pointed to by the instructions write to the program counter directly. For STKPTR register (Figure6-2). This allows users to these instructions, the contents of PCLATH and implement a software stack if necessary. After a CALL, PCLATU are not transferred to the program counter. RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These 6.1.2 RETURN ADDRESS STACK values can be placed on a user defined software stack. At The return address stack allows any combination of up return time, the software can return these values to to 31 program calls and interrupts to occur. The PC is TOSU:TOSH:TOSL and do a return. pushed onto the stack when a CALL or RCALL The user must disable the Global Interrupt Enable (GIE) instruction is executed or an interrupt is Acknowledged. bits while accessing the stack to prevent inadvertent The PC value is pulled off the stack on a RETURN, stack corruption. RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 6-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> 11111 11110 Top-of-Stack Registers Stack Pointer 11101 TOSU TOSH TOSL STKPTR<4:0> 00h 1Ah 34h 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 DS30000684B-page 74  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 6.1.2.2 Return Stack Pointer (STKPTR) The STKPTR register (Register6-1) contains the Stack Pointer value, the STKFUL (stack full) Status bit and the STKUNF (Stack Underflow) Status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Over- flow Reset Enable) Configuration bit. (Refer to Section26.1 “Configuration Bits” for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected.  2012-2014 Microchip Technology Inc. DS30000684B-page 75

PIC18(L)F2X/45K50 6.1.2.3 PUSH and POP Instructions The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads Since the Top-of-Stack is readable and writable, the the current PC value onto the stack. ability to push values onto the stack and pull values off the stack without disturbing normal program execution The POP instruction discards the current TOS by decre- is a desirable feature. The PIC18 instruction set menting the Stack Pointer. The previous value pushed includes two instructions, PUSH and POP, that permit onto the stack then becomes the TOS value. the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. 6.2 Register Definitions: Stack Pointer REGISTER 6-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — STKPTR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack Underflow occurred 0 = Stack Underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 STKPTR<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. 6.2.1 STACK FULL AND UNDERFLOW If both low and high priority interrupts are enabled, the RESETS stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs Device Resets on Stack Overflow and Stack Underflow while servicing a low priority interrupt, the stack register conditions are enabled by setting the STVREN bit in values stored by the low priority interrupt will be Configuration Register 4L. When STVREN is set, a full overwritten. In these cases, users must save the key or underflow will set the appropriate STKFUL or registers by software during a low priority interrupt. STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set If interrupt priority is not used, all interrupts may use the the appropriate STKFUL or STKUNF bit but not cause fast register stack for returns from interrupt. If no a device Reset. The STKFUL or STKUNF bits are interrupts are used, the fast register stack can be used cleared by the user software or a Power-on Reset. to restore the Status, WREG and BSR registers at the end of a subroutine call. To use the fast register stack 6.2.2 FAST REGISTER STACK for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and A fast register stack is provided for the Status, WREG BSR registers to the fast register stack. A and BSR registers, to provide a “fast return” option for RETURN, FAST instruction is then executed to restore interrupts. The stack for each register is only one level these registers from the fast register stack. deep and is neither readable nor writable. It is loaded with the current value of the corresponding register Example6-1 shows a source code example that uses when the processor vectors for an interrupt. All inter- the fast register stack during a subroutine call and rupt sources will push values into the stack registers. return. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. DS30000684B-page 76  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 EXAMPLE 6-1: FAST REGISTER STACK 6.2.3.2 Table Reads and Table Writes CODE EXAMPLE A better method of storing data in program memory CALL SUB1, FAST ;STATUS, WREG, BSR allows two bytes of data to be stored in each instruction ;SAVED IN FAST REGISTER location. ;STACK  Look-up table data may be stored two bytes per  program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte SUB1  address and the Table Latch (TABLAT) register  contains the data that is read from or written to program RETURN, FAST ;RESTORE VALUES SAVED memory. Data is transferred to or from program ;IN FAST REGISTER STACK memory one byte at a time. Table read and table write operations are discussed 6.2.3 LOOK-UP TABLES IN PROGRAM further in Section7.1 “Table Reads and Table MEMORY Writes”. There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • Computed GOTO • Table Reads 6.2.3.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example6-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value ‘nn’ to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. EXAMPLE 6-2: COMPUTED GOTO USING AN OFFSET VALUE MOVF OFFSET, W CALL TABLE ORG nn00h TABLE ADDWF PCL RETLW nnh RETLW nnh RETLW nnh . . .  2012-2014 Microchip Technology Inc. DS30000684B-page 77

PIC18(L)F2X/45K50 6.3 PIC18 Instruction Cycle 6.3.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 6.3.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are The microcontroller clock input, whether from an pipelined in such a manner that a fetch takes one internal or external source, is internally divided by four instruction cycle, while the decode and execute take to generate four non-overlapping quadrature clocks another instruction cycle. However, due to the (Q1, Q2, Q3 and Q4). Internally, the program counter is pipelining, each instruction effectively executes in one incremented on every Q1; the instruction is fetched cycle. If an instruction causes the program counter to from the program memory and latched into the change (e.g., GOTO), then two cycles are required to instruction register during Q4. The instruction is complete the instruction (Example6-3). decoded and executed during the following Q1 through A fetch cycle begins with the Program Counter (PC) Q4. The clocks and instruction execution flow are incrementing in Q1. shown in Figure6-3. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS30000684B-page 78  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 6.3.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruction. Since instructions are always stored on word The program memory is addressed in bytes. boundaries, the data contained in the instruction is a Instructions are stored as either two bytes or four bytes word address. The word address is written to PC<20:1>, in program memory. The Least Significant Byte of an which accesses the desired byte address in program instruction word is always stored in a program memory memory. Instruction #2 in Figure6-4 shows how the location with an even address (LSb = 0). To maintain instruction GOTO 0006h is encoded in the program alignment with instruction boundaries, the PC memory. Program branch instructions, which encode a increments in steps of two and the LSb will always read relative address offset, operate in the same manner. The ‘0’ (see Section6.1.1 “Program Counter”). offset value stored in a branch instruction represents the Figure6-4 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section27.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 6-4: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0  Program Memory 000000h Byte Locations  000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 6.3.4 TWO-WORD INSTRUCTIONS and used by the instruction sequence. If the first word is skipped for some reason and the second word is The standard PIC18 instruction set has four two-word executed by itself, a NOP is executed instead. This is instructions: CALL, MOVFF, GOTO and LSFR. In all necessary for cases when the two-word instruction is cases, the second word of the instruction always has preceded by a conditional instruction that changes the ‘1111’ as its four Most Significant bits; the other 12 bits PC. Example6-4 shows how this works. are literal data, usually a data memory address. Note: See Section6.8 “PIC18 Instruction The use of ‘1111’ in the four MSbs of an instruction Execution and the Extended Instruc- specifies a special form of NOP. If the instruction is tion Set” for information on two-word executed in proper sequence – immediately after the instructions in the extended instruction set. first word – the data in the second word is accessed EXAMPLE 6-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code  2012-2014 Microchip Technology Inc. DS30000684B-page 79

PIC18(L)F2X/45K50 6.4 Data Memory Organization 6.4.2 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section6.7 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit 12-bit address, allowing up to 4096 bytes of data low-order address and a 4-bit Bank Pointer. memory. The memory space is divided into as many as Most instructions in the PIC18 instruction set make use 16banks that contain 256 bytes each. Figures 6-5 of the Bank Pointer, known as the Bank Select Register through 6-7 show the data memory organization for the (BSR). This SFR holds the four Most Significant bits of PIC18(L)F2X/45K50 devices. a location’s address; the instruction itself includes the The data memory contains Special Function Registers eight Least Significant bits. Only the four lower bits of (SFRs) and General Purpose Registers (GPRs). The the BSR are implemented (BSR<3:0>). The upper four SFRs are used for control and status of the controller bits are unused; they will always read ‘0’ and cannot be and peripheral functions, while GPRs are used for data written to. The BSR can be loaded directly by using the storage and scratchpad operations in the user’s MOVLB instruction. application. Any read of an unimplemented location will The value of the BSR indicates the bank in data read as ‘0’s. memory; the eight bits in the instruction show the The instruction set and architecture allow operations location in the bank and can be thought of as an offset across all banks. The entire data memory may be from the bank’s lower boundary. The relationship accessed by Direct, Indirect or Indexed Addressing between the BSR’s value and the bank division in data modes. Addressing modes are discussed later in this memory is shown in Figures 6-5 through 6-7. subsection. Since up to 16 registers may share the same low-order To ensure that commonly used registers (SFRs and address, the user must always be careful to ensure that select GPRs) can be accessed in a single cycle, PIC18 the proper bank is selected before performing a data devices implement an Access Bank. This is a 256-byte read or write. For example, writing what should be memory space that provides fast access to SFRs and program data to an 8-bit address of F9h while the BSR the lower portion of GPR Bank 0 without using the Bank is 0Fh will end up resetting the program counter. Select Register (BSR). Section6.4.3 “Access Bank” While any bank can be selected, only those banks that provides a detailed description of the Access RAM. are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while 6.4.1 USB RAM reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the Banks 4 through 7 of the data memory are actually operation was successful. The data memory maps in mapped to special dual port RAM. When the USB Figures 6-5 through 6-7 indicate which banks are module is disabled, the GPRs in these banks are used implemented. like any other GPR in the data memory space. When the USB module is enabled, the memory in In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the these banks is allocated as buffer RAM for USB source and target registers. This instruction ignores the operation. This area is shared between the BSR completely when it executes. All other instructions microcontroller core and the USB Serial Interface include only the low-order address as an operand and Engine (SIE) and is used to transfer data directly must use either the BSR or the Access Bank to locate between the two. It is theoretically possible to use the their target registers. areas of USB RAM that are not allocated as USB buffers for normal scratchpad memory or other variable storage. In practice, the dynamic nature of buffer allocation makes this risky, at best. Additionally, Bank 4 is used for USB buffer descriptor tables when the module is enabled and should not be used for any other purposes during that time. Additional information on USB RAM and buffer operation is provided in Section24.0 “Universal Serial Bus (USB)”. DS30000684B-page 80  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 6-5: DATA MEMORY MAP FOR PIC18(L)F2X/45K50 DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 96 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 160 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank GPR used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 GPR(2) FFh 4FFh = 0101 00h 500h Bank 5 GPR(2) FFh 5FFh = 0110 00h 600h Bank 6 GPR(2) Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 GPR(2) Access RAM Low 5Fh FFh 7FFh Access RAM High 60h = 1000 Bank 8 00h Unimplemented. 800h (SFRs) FFh Read as 00h. FFh 8FFh = 1001 00h 900h Bank 9 Unimplemented. Read as 00h. FFh 9FFh = 1010 Bank 10 00h Unimplemented. A00h Read as 00h. FFh AFFh = 1011 00h Unimplemented. B00h Bank 11 Read as 00h. FFh BFFh C00h = 1100 00h Unimplemented. Bank 12 Read as 00h. CFFh FFh D00h = 1101 00h Bank 13 Unimplemented. Read as 00h. DFFh FFh 00h E00h = 1110 Unimplemented. Bank 14 Read as 00h. Note 1: Addresses F53h through F5Fh are FFh also used by SFRs, but are not 00h F00h = 1111 Unimplemented F52h part of the Access RAM. Users Bank 15 SFR(1) FF553Fhh madudsrte sasl woary lso auds eth et hper ocpoemr pBlSetRe F60h value to access these registers. 2: These banks also serve as RAM SFR buffer for USB operation. See Section6.4.1 “USB RAM” for FFh FFFh more information.  2012-2014 Microchip Technology Inc. DS30000684B-page 81

PIC18(L)F2X/45K50 FIGURE 6-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) Data Memory From Opcode(2) 7 0 000h 00h 7 0 0 0 0 0 0 0 1 1 Bank 0 FFh 1 1 1 1 1 1 1 1 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS30000684B-page 82  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 6.4.3 ACCESS BANK 6.4.4 GENERAL PURPOSE REGISTER FILE While the use of the BSR with an embedded 8-bit address allows users to address the entire range of PIC18 devices may have banked memory in the GPR data memory, it also means that the user must always area. This is data RAM, which is available for use by all ensure that the correct bank is selected. Otherwise, instructions. GPRs start at the bottom of Bank 0 data may be read from or written to the wrong location. (address 000h) and grow upwards towards the bottom of This can be disastrous if a GPR is the intended target the SFR area. GPRs are not initialized by a Power-on of an operation, but an SFR is written to instead. Reset and are unchanged on all other Resets. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. 6.4.5 SPECIAL FUNCTION REGISTERS To streamline access for the most commonly used data The Special Function Registers (SFRs) are registers memory locations, the data memory is configured with used by the CPU and peripheral modules for controlling an Access Bank, which allows users to access a the desired operation of the device. These registers are mapped block of memory without specifying a BSR. implemented as static RAM. SFRs start at the top of The Access Bank consists of the first 96 bytes of mem- data memory (FFFh) and extend downward to occupy ory (00h-5Fh) in Bank 0 and the last 160 bytes of mem- the top portion of Bank 15 (F53h to FFFh). A list of ory (60h-FFh) in Block 15. The lower half is known as these registers is given in Table6-1 and Table6-2. the “Access RAM” and is composed of GPRs. This The SFRs can be classified into two sets: those upper half is also where the device’s SFRs are associated with the “core” device functionality (ALU, mapped. These two areas are mapped contiguously in Resets and interrupts) and those related to the the Access Bank and can be addressed in a linear peripheral functions. The Reset and interrupt registers fashion by an 8-bit address (Figures 6-5 through 6-7). are described in their respective chapters, while the The Access Bank is used by core PIC18 instructions ALU’s STATUS register is described later in this that include the Access RAM bit (the ‘a’ parameter in section. Registers related to the operation of a the instruction). When ‘a’ is equal to ‘1’, the instruction peripheral feature are described in the chapter for that uses the BSR and the 8-bit address included in the peripheral. opcode for the data memory address. When ‘a’ is ‘0’, The SFRs are typically distributed among the however, the instruction is forced to use the Access peripherals whose functions they control. Unused SFR Bank address map; the current value of the BSR is locations are unimplemented and read as ‘0’s. ignored entirely. Using this “forced” addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section6.7.3 “Mapping the Access Bank in Indexed Literal Offset Mode”.  2012-2014 Microchip Technology Inc. DS30000684B-page 83

PIC18(L)F2X/45K50 TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F2X/45K50 DEVICES Address Name Address Name Address Name Address Name Address Name FFFh TOSU FD7h TMR0H FAFh SPBRG1 F87h IOCC F5Fh ANSELE(3) FFEh TOSH FD6h TMR0L FAEh RCREG1 F86h IOCB F5Eh ANSELD(3) FFDh TOSL FD5h T0CON FADh TXREG1 F85h WPUB F5Dh ANSELC FFCh STKPTR FD4h —(2) FACh TXSTA1 F84h PORTE F5Ch ANSELB FFBh PCLATU FD3h OSCCON FABh RCSTA1 F83h PORTD(3) F5Bh ANSELA FFAh PCLATH FD2h OSCCON2 FAAh — F82h PORTC F5Ah VREGCON(4) FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB F59h CCPTMRS FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA F58h SRCON0 FF7h TBLPTRH FCFh TMR1H FA7h EECON2(1) F7Fh PMD1 F57h SRCON1 FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh PMD0 F56h — FF5h TABLAT FCDh T1CON FA5h IPR3 F7Dh VREFCON0 F55h — FF4h PRODH FCCh T1GCON FA4h PIR3 F7Ch VREFCON1 F54h — FF3h PRODL FCBh SSP1CON3 FA3h PIE3 F7Bh VREFCON2 F53h — FF2h INTCON FCAh SSP1MSK FA2h IPR2 F7Ah SLRCON F52h FF1h INTCON2 FC9h SSP1BUF FA1h PIR2 F79h UEP15 F51h FF0h INTCON3 FC8h SSP1ADD FA0h PIE2 F78h UEP14 F50h FEFh INDF0(1) FC7h SSP1STAT F9Fh IPR1 F77h UEP13 F4Fh FEEh POSTINC0(1) FC6h SSP1CON1 F9Eh PIR1 F76h UEP12 F4Eh FEDh POSTDEC0(1) FC5h SSP1CON2 F9Dh PIE1 F75h UEP11 F4Dh FECh PREINC0(1) FC4h ADRESH F9Ch HLVDCON F74h UEP10 F4Ch FEBh PLUSW0(1) FC3h ADRESL F9Bh OSCTUNE F73h UEP9 F4Bh FEAh FSR0H FC2h ADCON0 F9Ah CM2CON1 F72h UEP8 F4Ah FE9h FSR0L FC1h ADCON1 F99h CM2CON0 F71h UEP7 F49h FE8h WREG FC0h ADCON2 F98h CM1CON0 F70h UEP6 F48h FE7h INDF1(1) FBFh CCPR1H F97h CCP2CON F6Fh UEP5 F47h General FE6h POSTINC1(1) FBEh CCPR1L F96h TRISE(3) F6Eh UEP4 F46h Purpose RAM FE5h POSTDEC1(1) FBDh CCP1CON F95h TRISD(3) F6Dh UEP3 F45h FE4h PREINC1(1) FBCh TMR2 F94h TRISC F6Ch UEP2 F44h FE3h PLUSW1(1) FBBh PR2 F93h TRISB F6Bh UEP1 F43h FE2h FSR1H FBAh T2CON F92h TRISA F6Ah UEP0 F42h FE1h FSR1L FB9h PSTR1CON F91h CCPR2H F69h UFRMH F41h FE0h BSR FB8h BAUDCON1 F90h CCPR2L F68h UFRML F40h FDFh INDF2(1) FB7h PWM1CON F8Fh CTMUCONH F67h UEIR F3Fh FDEh POSTINC2(1) FB6h ECCP1AS F8Eh CTMUCONL F66h UEIE F3Eh FDDh POSTDEC2(1) FB5h STCON F8Dh LATE(3) F65h UIR F3Dh FDCh PREINC2(1) FB4h T3GCON F8Ch LATD(3) F64h UIE F3Ch FDBh PLUSW2(1) FB3h TMR3H F8Bh LATC F63h UADDR F3Bh FDAh FSR2H FB2h TMR3L F8Ah LATB F62h UCNFG F3Ah FD9h FSR2L FB1h T3CON F89h LATA F61h USTAT F39h FD8h STATUS FB0h SPBRGH1 F88h CTMUICONH F60h UCTRL F38h Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: PIC18(L)F45K50 device only. 4: F devices only. DS30000684B-page 84  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 6-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR FFFh TOSU — — — Top-of-Stack, Upper Byte (TOS<20:16>) ---0 0000 FFEh TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 FFDh TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 FFCh STKPTR STKFUL STKUNF — STKPTR<4:0> 00-0 0000 FFBh PCLATU — — — Holding Register for PC<20:16> ---0 0000 FFAh PCLATH Holding Register for PC<15:8> 0000 0000 FF9h PCL Holding Register for PC<7:0> 0000 0000 FF8h TBLPTRU — — Program Memory Table Pointer Upper Byte (TBLPTR<21:16>) --00 0000 FF7h TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 FF6h TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 FF5h TABLAT Program Memory Table Latch 0000 0000 FF4h PRODH Product Register, High Byte xxxx xxxx FF3h PRODL Product Register, Low Byte xxxx xxxx FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 0000 000x FF1h INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP 1111 -1-1 FF0h INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) ---- ---- FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) ---- ---- FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) ---- ---- FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) ---- ---- FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – ---- ---- value of FSR0 offset by W FEAh FSR0H — — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000 FE9h FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx FE8h WREG Working Register xxxx xxxx FE7h INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) ---- ---- FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ---- FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ---- FE4h PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) ---- ---- FE3h PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – ---- ---- value of FSR1 offset by W FE2h FSR1H — — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000 FE1h FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx FE0h BSR — — — — Bank Select Register ---- 0000 FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) ---- ---- FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) ---- ---- FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) ---- ---- FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) ---- ---- FDBh PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – ---- ---- value of FSR2 offset by W FDAh FSR2H — — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000 FD9h FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx FD8h STATUS — — — N OV Z DC C ---x xxxx FD7h TMR0H Timer0 Register, High Byte 0000 0000 FD6h TMR0L Timer0 Register, Low Byte xxxx xxxx FD5h T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS<2:0> 1111 1111 FD3h OSCCON IDLEN IRCF<2:0> OSTS HFIOFS SCS<1:0> 0011 q000 FD2h OSCCON2 PLLRDY SOSCRUN INTSRC PLLEN SOSCGO PRISD HFIOFR LFIOFS 0000 0100 FD1h WDTCON — — — — — — — SWDTEN ---- ---0 FD0h RCON IPEN SBOREN — RI TO PD POR BOR 01-1 1100 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: PIC18(L)F45K50 devices only. 2: PIC18(L)F2XK50 devices only.  2012-2014 Microchip Technology Inc. DS30000684B-page 85

PIC18(L)F2X/45K50 TABLE 6-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES (CONTINUED) Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR FCFh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx FCEh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx FCDh T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC RD16 TMR1ON 0000 0000 FCCh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 DONE FCBh SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 FCAh SSP1MSK SSP1 Mask Register bits 1111 1111 FC9h SSP1BUF SSP1 Receive Buffer/Transmit Register xxxx xxxx FC8h SSP1ADD SSP1 Address Register in I2C™ Slave Mode. SSP1 Baud Rate Reload Register in I2C Master Mode 0000 0000 FC7h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 FC6h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 FC5h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 FC4h ADRESH A/D Result, High Byte xxxx xxxx FC3h ADRESL A/D Result, Low Byt xxxx xxxx FC2h ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 FC1h ADCON1 TRIGSEL — — — PVCFG<1:0> NVCFG<1:0> 0--- 0000 FC0h ADCON2 ADFM — ACQT<2:0> ADCS<2:0> 0-00 0000 FBFh CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxx FBEh CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx FBDh CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 FBCh TMR2 Timer2 Register 0000 0000 FBBh PR2 Timer2 Period Register 1111 1111 FBAh T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 FB9h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 FB8h BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 FB7h PWM1CON P1RSEN P1DC<6:0> 0000 0000 FB6h ECCP1AS ECCP1ASE ECCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 FB5h ACTCON ACTEN ACTUD — ACTSRC ACTLOCK — ACTORS — 00-0 0-0- FB4h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS<1:0> 0000 0x00 DONE FB3h TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx FB2h TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx FB1h T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC RD16 TMR3ON 0000 0000 FB0h SPBRGH1 EUSART Baud Rate Generator, High Byte 0000 0000 FAFh SPBRG1 EUSART Baud Rate Generator, Low Byte 0000 0000 FAEh RCREG1 EUSART Receive Register 0000 0000 FADh TXREG1 EUSART Transmit Register 0000 0000 FACh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 FABh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x FA9h EEADR EEADR<7:0> 0000 0000 FA8h EEDATA EEPROM Data Register 0000 0000 FA7h EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- FA6h EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 FA5h IPR3 — — — — CTMUIP USBIP TMR3GIP TMR1GIP 0000 1111 FA4h PIR3 — — — — CTMUIF USBIF TMR3GIF TMR1GIF 0000 0000 FA3h PIE3 — — — — CTMUIE USBIE TMR3GIE TMR1GIE 0000 0000 FA2h IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 1111 1111 FA1h PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 0000 0000 FA0h PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 0000 0000 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: PIC18(L)F45K50 devices only. 2: PIC18(L)F2XK50 devices only. DS30000684B-page 86  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 6-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES (CONTINUED) Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR F9Fh IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 F9Eh PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 F9Dh PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 F9Ch HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> 0000 0000 F9Bh OSCTUNE SPLLMULT TUN<6:0> 0000 0000 F9Ah CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 0000 0000 F99h CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH<1:0> 0000 1000 F98h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH<1:0> 0000 1000 F97h CCP2CON — — DC2B<1:0> CCP2M<3:0> --00 0000 F96h TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 1--- -111 F95h TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 F94h TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 1111 -111 F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 F92h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 F91h CCPR2H Capture/Compare/PWM Register 2, High Byte xxxx xxxx F90h CCPR2L Capture/Compare/PWM Register 2, Low Byte xxxx xxxx F8Fh CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 0-00 0000 F8Eh CTMUCONL EDG2POL EDG2SEL<1:0> EDG1POL EDG1SEL<1:0> EDG2STAT EDG1STAT 0000 00xx F8Dh LATE(1) — — — — — LATE2 LATE1 LATE0 ---- -xxx F8Ch LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx F8Bh LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 xxxx -xxx F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx F89h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx F88h CTMUICON ITRIM<5:0> IRNG<1:0> 0000 0000 F87h IOCC IOCC7 IOCC6 IOCC5 IOCC4 — IOCC2 IOCC1 IOCC0 0000 -000 F86h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- F85h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 PORTE(2) — — — — RE3 — — — ---- x--- F84h PORTE(1) — — — — RE3 RE2 RE1 RE0 ---- xxxx F83h PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx F82h PORTC RC7 RC6 — — — RC2 RC1 RC0 xx-- -xxx F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx F80h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx F7Fh PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD -000 0000 F7Eh PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD -000 -000 F7Dh VREFCON0 FVREN FVRST FVRS<1:0> — — — — 0001 00-- F7Ch VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 000- 00-0 F7Bh VREFCON2 — — — DACR<4:0> ---0 0000 F7Ah SLRCON — — — SLRE SLRD SLRC SLRB SLRA ---1 1111 F79h UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F78h UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F77h UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F76h UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F75h UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F74h UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F73h UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F72h UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F71h UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F70h UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: PIC18(L)F45K50 devices only. 2: PIC18(L)F2XK50 devices only.  2012-2014 Microchip Technology Inc. DS30000684B-page 87

PIC18(L)F2X/45K50 TABLE 6-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES (CONTINUED) Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR F6Fh UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Eh UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Dh UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Ch UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Bh UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Ah UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F69h UFRMH — — — — — FRM<10:8> ---- -xxx F68h UFRML FRM<7:0> xxxx xxxx F67h UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 F66h UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 F65h UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 F64h UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 F63h UADDR — ADDR<6:0> -000 0000 F62h UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB<1:0> 00-0 0000 F61h USTAT — ENDP<3:0> DIR PPBI — -xxx xxx- F60h UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- F5Fh ANSELE — — — — — ANSE2 ANSE1 ANSE0 ---- -111 F5Eh ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 F5Dh ANSELC ANSC7 ANSC6 — — — ANSC2 — — 11-- -1-- F5Ch ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 F5Bh ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 F5Ah VREGCON — — — — — — VREGPM<1:0> ---- --01 F59h CCPTMRS — — — — C2TSEL — — C1TSEL ---- 0--0 F58h SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 0000 0000 F57h SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 F56h — — — — — — — — — ---- ---- F55h — — — — — — — — — ---- ---- F54h — — — — — — — — — ---- ---- F53h — — — — — — — — — ---- ---- Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: PIC18(L)F45K50 devices only. 2: PIC18(L)F2XK50 devices only. DS30000684B-page 88  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 6.4.6 STATUS REGISTER It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS The STATUS register, shown in Register6-2, contains register, because these instructions do not affect the Z, the arithmetic status of the ALU. As with any other SFR, C, DC, OV or N bits in the STATUS register. it can be the operand for any instruction. For other instructions that do not affect Status bits, see If the STATUS register is the destination for an instruc- the instruction set summaries in Section27.2 tion that affects the Z, DC, C, OV or N bits, the results “Extended Instruction Set” and Table27-3. of the instruction are not written; instead, the STATUS register is updated according to the instruction per- Note: The C and DC bits operate as the Borrow formed. Therefore, the result of an instruction with the and Digit Borrow bits, respectively, in STATUS register as its destination may be different subtraction. than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). 6.5 Register Definitions: Status REGISTER 6-2: STATUS: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (two’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(2) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Digit Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. 2: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.  2012-2014 Microchip Technology Inc. DS30000684B-page 89

PIC18(L)F2X/45K50 6.6 Data Addressing Modes The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR Note: The execution of some instructions in the (Section6.4.2 “Bank Select Register (BSR)”) are core PIC18 instruction set are changed used with the address to determine the complete 12-bit when the PIC18 extended instruction set is address of the register. When ‘a’ is ‘0’, the address is enabled. See Section6.7 “Data Memory interpreted as being a register in the Access Bank. and the Extended Instruction Set” for Addressing that uses the Access RAM is sometimes more information. also known as Direct Forced Addressing mode. While the program memory can be addressed in only A few instructions, such as MOVFF, include the entire one way – through the program counter – information 12-bit address (either source or destination) in their in the data memory space can be addressed in several opcodes. In these cases, the BSR is ignored entirely. ways. For most instructions, the addressing mode is The destination of the operation’s results is determined fixed. Other instructions may use up to three modes, by the destination bit ‘d’. When ‘d’ is ‘1’, the results are depending on which operands are used and whether or stored back in the source register, overwriting its origi- not the extended instruction set is enabled. nal contents. When ‘d’ is ‘0’, the results are stored in The addressing modes are: the W register. Instructions without the ‘d’ argument have a destination that is implicit in the instruction; their • Inherent destination is either the target register being operated • Literal on or the W register. • Direct 6.6.3 INDIRECT ADDRESSING • Indirect Indirect addressing allows the user to access a location An additional addressing mode, Indexed Literal Offset, in data memory without giving a fixed address in the is available when the extended instruction set is instruction. This is done by using File Select Registers enabled (XINST Configuration bit = 1). Its operation is (FSRs) as pointers to the locations which are to be read discussed in greater detail in Section6.7.1 “Indexed or written. Since the FSRs are themselves located in Addressing with Literal Offset”. RAM as Special File Registers, they can also be 6.6.1 INHERENT AND LITERAL directly manipulated under program control. This ADDRESSING makes FSRs very useful in implementing data struc- tures, such as tables and arrays in data memory. Many PIC18 control instructions do not need any argu- ment at all; they either perform an operation that glob- The registers for indirect addressing are also ally affects the device or they operate implicitly on one implemented with Indirect File Operands (INDFs) that register. This addressing mode is known as Inherent permit automatic manipulation of the pointer value with Addressing. Examples include SLEEP, RESET and DAW. auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using Other instructions work in a similar way but require an loops, such as the example of clearing an entire RAM additional explicit argument in the opcode. This is bank in Example6-5. known as Literal Addressing mode because they require some literal value as an argument. Examples EXAMPLE 6-5: HOW TO CLEAR RAM include ADDLW and MOVLW, which respectively, add or (BANK 1) USING move a literal value to the W register. Other examples INDIRECT ADDRESSING include CALL and GOTO, which include a 20-bit program memory address. LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF 6.6.2 DIRECT ADDRESSING ; register then ; inc pointer Direct addressing specifies all or part of the source BTFSS FSR0H,1 ; All done with and/or destination address of the operation within the ; Bank1? opcode itself. The options are specified by the BRA NEXT ; NO, clear next arguments accompanying the instruction. CONTINUE ; YES, continue In the core PIC18 instruction set, bit-oriented and byte- oriented instructions use some version of direct addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section6.4.4 “General Purpose Register File”) or a location in the Access Bank (Section6.4.3 “Access Bank”) as the data source for the instruction. DS30000684B-page 90  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 6.6.3.1 FSR Registers and the INDF 6.6.3.2 FSR Registers and POSTINC, Operand POSTDEC, PREINC and PLUSW At the core of indirect addressing are three sets of reg- In addition to the INDF operand, each FSR register pair isters: FSR0, FSR1 and FSR2. Each represents a pair also has four additional indirect operands. Like INDF, of 8-bit registers, FSRnH and FSRnL. Each FSR pair these are “virtual” registers which cannot be directly holds a 12-bit value, therefore, the four upper bits of the read or written. Accessing these registers actually FSRnH register are not used. The 12-bit FSR value can accesses the location to which the associated FSR address the entire range of the data memory in a linear register pair points, and also performs a specific action fashion. The FSR register pairs, then, serve as pointers on the FSR value. They are: to data memory locations. • POSTDEC: accesses the location to which the Indirect addressing is accomplished with a set of FSR points, then automatically decrements the Indirect File Operands, INDF0 through INDF2. These FSR by 1 afterwards can be thought of as “virtual” registers: they are • POSTINC: accesses the location to which the mapped in the SFR space but are not physically FSR points, then automatically increments the implemented. Reading or writing to a particular INDF FSR by 1 afterwards register actually accesses its corresponding FSR • PREINC: automatically increments the FSR by 1, register pair. A read from INDF1, for example, reads then uses the location to which the FSR points in the data at the address indicated by FSR1H:FSR1L. the operation Instructions that use the INDF registers as operands • PLUSW: adds the signed value of the W register actually use the contents of their corresponding FSR as (range of -128 to +127) to that of the FSR and a pointer to the instruction’s target. The INDF operand uses the location to which the result points in the is just a convenient way of using the pointer. operation. Because indirect addressing uses a full 12-bit address, In this context, accessing an INDF register uses the data RAM banking is not necessary. Thus, the current value in the associated FSR register without changing contents of the BSR and the Access RAM bit have no it. Similarly, accessing a PLUSW register gives the effect on determining the target address. FSR value an offset by that in the W register; however, neither W nor the FSR is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR register. FIGURE 6-7: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 indirect addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 0 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains E00h ECCh. This means the contents of Bank 14 location ECCh will be added to that F00h of the W register and stored back in Bank 15 ECCh. FFFh Data Memory  2012-2014 Microchip Technology Inc. DS30000684B-page 91

PIC18(L)F2X/45K50 Operations on the FSRs with POSTDEC, POSTINC 6.7.1 INDEXED ADDRESSING WITH and PREINC affect the entire register pair; that is, roll- LITERAL OFFSET overs of the FSRnL register from FFh to 00h carry over Enabling the PIC18 extended instruction set changes to the FSRnH register. On the other hand, results of the behavior of indirect addressing using the FSR2 these operations do not change the value of any flags register pair within Access RAM. Under the proper in the STATUS register (e.g., Z, N, OV, etc.). conditions, instructions that use the Access Bank – that The PLUSW register can be used to implement a form is, most bit-oriented and byte-oriented instructions – of indexed addressing in the data memory space. By can invoke a form of indexed addressing using an manipulating the value in the W register, users can offset specified in the instruction. This special reach addresses that are fixed offsets from pointer addressing mode is known as Indexed Addressing with addresses. In some applications, this can be used to Literal Offset, or Indexed Literal Offset mode. implement some powerful program control structure, When using the extended instruction set, this such as software stacks, inside of data memory. addressing mode requires the following: 6.6.3.3 Operations by FSRs on FSRs • The use of the Access Bank is forced (‘a’ = 0) and Indirect addressing operations that target other FSRs • The file address argument is less than or equal to or virtual registers represent special cases. For 5Fh. example, using an FSR to point to one of the virtual Under these conditions, the file address of the registers will not result in successful operations. As a instruction is not interpreted as the lower byte of an specific case, assume that FSR0H:FSR0L contains address (used with the BSR in direct addressing), or as FE7h, the address of INDF1. Attempts to read the an 8-bit address in the Access Bank. Instead, the value value of the INDF1 using INDF0 as an operand will is interpreted as an offset value to an Address Pointer, return 00h. Attempts to write to INDF1 using INDF0 as specified by FSR2. The offset and the contents of the operand will result in a NOP. FSR2 are added to obtain the target address of the On the other hand, using the virtual registers to write to operation. an FSR pair may not occur as planned. In these cases, 6.7.2 INSTRUCTIONS AFFECTED BY the value will be written to the FSR pair but without any INDEXED LITERAL OFFSET MODE incrementing or decrementing. Thus, writing to either the INDF2 or POSTDEC2 register will write the same Any of the core PIC18 instructions that can use direct value to the FSR2H:FSR2L. addressing are potentially affected by the Indexed Since the FSRs are physical registers mapped in the Literal Offset Addressing mode. This includes all SFR space, they can be manipulated through all direct byte-oriented and bit-oriented instructions, or almost operations. Users should proceed cautiously when one-half of the standard PIC18 instruction set. working on these registers, particularly if their code Instructions that only use Inherent or Literal Addressing uses indirect addressing. modes are unaffected. Similarly, operations by indirect addressing are generally Additionally, byte-oriented and bit-oriented instructions permitted on all other SFRs. Users should exercise the are not affected if they do not use the Access Bank appropriate caution that they do not inadvertently change (Access RAM bit is ‘1’), or include a file address of 60h settings that might affect the operation of the device. or above. Instructions meeting these criteria will continue to execute as before. A comparison of the 6.7 Data Memory and the Extended different possible addressing modes when the extended instruction set is enabled is shown in Instruction Set Figure6-8. Enabling the PIC18 extended instruction set (XINST Those who desire to use byte-oriented or bit-oriented Configuration bit = 1) significantly changes certain instructions in the Indexed Literal Offset mode should aspects of data memory and its addressing. Specifi- note the changes to assembler syntax for this mode. cally, the use of the Access Bank for many of the core This is described in more detail in Section27.2.1 PIC18 instructions is different; this is due to the intro- “Extended Instruction Syntax”. duction of a new addressing mode for the data memory space. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. DS30000684B-page 92  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 6-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When ‘a’ = 0 and f  60h: The instruction executes in 060h Direct Forced mode. ‘f’ is inter- Bank 0 preted as a location in the 100h Access RAM between 060h 00h and 0FFh. This is the same as Bank 1 through 60h locations F60h to FFFh Bank 14 (Bank15) of data memory. Valid range for ‘f’ Locations below 60h are not FFh available in this addressing F00h Access RAM mode. Bank 15 F60h SFRs FFFh Data Memory When ‘a’ = 0 and f5Fh: 000h The instruction executes in Indexed Literal Offset mode. ‘f’ 060h Bank 0 is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F60h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When ‘a’ = 1 (all values of f): 000h 00000000 The instruction executes in 060h Direct mode (also known as Bank 0 Direct Long mode). ‘f’ is inter- 100h preted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F60h SFRs FFFh Data Memory  2012-2014 Microchip Technology Inc. DS30000684B-page 93

PIC18(L)F2X/45K50 6.7.3 MAPPING THE ACCESS BANK IN 6.8 PIC18 Instruction Execution and INDEXED LITERAL OFFSET MODE the Extended Instruction Set The use of Indexed Literal Offset Addressing mode Enabling the extended instruction set adds eight effectively changes how the first 96 locations of Access additional commands to the existing PIC18 instruction RAM (00h to 5Fh) are mapped. Rather than containing set. These instructions are executed as described in just the contents of the bottom section of Bank 0, this Section27.2 “Extended Instruction Set”. mode maps the contents from a user defined “window” that can be located anywhere in the data memory space. The value of FSR2 establishes the lower bound- ary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section6.4.3 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure6-9. Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. FIGURE 6-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a FSR2H:FSR2L = 120h Bank 0 Locations in the region from the FSR2 pointer 100h (120h) to the pointer plus Bank 1 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Access RAM (000h-05Fh). 200h Bank 1 “Window” 5Fh Special File Registers at 60h F60h through FFFh are mapped to 60h through Bank 2 FFh, as usual. through SFRs Bank 0 addresses below Bank 14 5Fh can still be addressed FFh by using the BSR. Access Bank F00h Bank 15 F60h SFRs FFFh Data Memory DS30000684B-page 94  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the specified two operations that allow the processor to move bytes VDD ranges. between the program memory space and the data RAM: A read from program memory is executed one byte at • Table Read (TBLRD) a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 64 bytes at a time. Program memory is The program memory space is 16 bits wide, while the erased in blocks of 64 bytes at a time. A bulk erase data RAM space is 8 bits wide. Table reads and table operation cannot be issued from user code. writes move data between these two memory spaces Writing or erasing program memory will cease through an 8-bit register (TABLAT). instruction fetches until the operation is complete. The The table read operation retrieves one byte of data program memory cannot be accessed during the write directly from program memory and places it into the or erase, therefore, code cannot execute. An internal TABLAT register. Figure7-1 shows the operation of a programming timer terminates program memory writes table read. and erases. The table write operation stores one byte of data from the A value written to program memory does not need to be TABLAT register into a write block holding register. The a valid instruction. Executing a program memory procedure to write the contents of the holding registers location that forms an invalid instruction results in a into program memory is detailed in Section7.6 “Writing NOP. to Flash Program Memory”. Figure7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. Tables containing data, rather than program instructions, are not required to be word aligned. Therefore, a table can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory.  2012-2014 Microchip Technology Inc. DS30000684B-page 95

PIC18(L)F2X/45K50 FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR<MSBs>) Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL actually point to an address within the write block holding registers. The MSBs of the Table Pointer deter- mine where the write block will eventually be written. The process for writing the holding registers to the program memory array is discussed in Section7.6 “Writing to Flash Program Memory”. 7.2 Control Registers The FREE bit allows the program memory erase operation. When FREE is set, an erase operation is Several control registers are used in conjunction with initiated on the next WR command. When FREE is the TBLRD and TBLWT instructions. These include the: clear, only writes are enabled. • EECON1 register The WREN bit, when set, will allow a write operation. • EECON2 register The WREN bit is clear on power-up. • TABLAT register The WRERR bit is set by hardware when the WR bit is • TBLPTR registers set and cleared when the internal programming timer expires and the write operation is complete. 7.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is The EECON1 register (Register7-1) is the control read as ‘1’. This can indicate that a write register for memory accesses. The EECON2 register is operation was prematurely terminated by not a physical register; it is used exclusively in the a Reset, or a write operation was memory write and erase sequences. Reading attempted improperly. EECON2 will read all ‘0’s. The EEPGD control bit determines if the access will be The WR control bit initiates write operations. The WR a program or data EEPROM memory access. When bit cannot be cleared, only set, by firmware. The WR bit EEPGD is clear, any subsequent operations will is cleared by hardware at the completion of the write operate on the data EEPROM memory. When EEPGD operation. is set, any subsequent operations will operate on the Note: The EEIF interrupt flag bit of the PIR2 program memory. register is set when the write is complete. The CFGS control bit determines if the access will be The EEIF flag stays set until cleared by to the Configuration/Calibration registers or to program firmware. memory/data EEPROM memory. When CFGS is set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section26.0 “Special Features of the CPU”). When CFGS is clear, memory selection access is determined by EEPGD. DS30000684B-page 96  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 7.3 Register Definitions: Memory Control REGISTER 7-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row (Block) Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) by software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition.  2012-2014 Microchip Technology Inc. DS30000684B-page 97

PIC18(L)F2X/45K50 7.3.1 TABLAT – TABLE LATCH REGISTER When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory The Table Latch (TABLAT) is an 8-bit register mapped directly into the TABLAT register. into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program When a TBLWT is executed the byte in the TABLAT memory and data RAM. register is written, not to Flash memory but, to a holding register in preparation for a program memory write. The 7.3.2 TBLPTR – TABLE POINTER holding registers constitute a write block which varies REGISTER depending on the device (see Table7-1).The six LSbs of the TBLPTRL register determine which specific The Table Pointer (TBLPTR) register addresses a byte address within the holding register block is written to. within the program memory. The TBLPTR is comprised The MSBs of the Table Pointer have no effect during of three SFR registers: Table Pointer Upper Byte, Table TBLWT operations. Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- When a program memory write is executed (WR = 1), ters join to form a 22-bit wide pointer. The low-order the entire holding register block is written to the Flash 21bits allow the device to address up to 2 Mbytes of memory at the address determined by the MSbs of the program memory space. The 22nd bit allows access to TBLPTR. The six LSBs are ignored during Flash mem- the device ID, the user ID and the Configuration bits. ory writes. For more detail, see Section7.6 “Writing to Flash Program Memory”. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can When an erase of program memory is executed, the update the TBLPTR in one of four ways based on the 16MSbs of the Table Pointer register (TBLPTR<21:6>) table operation. These operations on the TBLPTR point to the 64-byte block that will be erased. The Least affect only the low-order 21bits. Significant bits (TBLPTR<5:0>) are ignored. Figure7-3 describes the relevant boundaries of 7.3.3 TABLE POINTER BOUNDARIES TBLPTR based on Flash program memory operations. TBLPTR is used in reads, writes and erases of the Flash program memory. TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 TABLE ERASE/WRITE TABLE WRITE TBLPTR<21:n+1>(1) TBLPTR<n:0>(1) TABLE READ – TBLPTR<21:0> Note1: n = 5 for block sizes of 64 bytes. DS30000684B-page 98  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 7.4 Reading the Flash Program Memory The TBLRD instruction retrieves data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure7-4 shows the interface between the internal program memory and the TABLAT. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVFW TABLAT, W ; get data MOVF WORD_ODD  2012-2014 Microchip Technology Inc. DS30000684B-page 99

PIC18(L)F2X/45K50 7.5 Erasing Flash Program Memory 7.5.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through The sequence of events for erasing a block of internal ICSP control, can larger blocks of program memory be program memory is: bulk erased. Word erase in the Flash array is not 1. Load Table Pointer register with address of supported. block being erased. When initiating an erase sequence from the 2. Set the EECON1 register for the erase operation: microcontroller itself, a block of 64 bytes of program • set EEPGD bit to point to program memory; memory is erased. The Most Significant 16 bits of the • clear the CFGS bit to access program memory; TBLPTR<21:6> point to the block being erased. The • set WREN bit to enable writes; TBLPTR<5:0> bits are ignored. • set FREE bit to enable the erase. The EECON1 register commands the erase operation. 3. Disable interrupts. The EEPGD bit must be set to point to the Flash 4. Write 55h to EECON2. program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase 5. Write 0AAh to EECON2. operation. 6. Set the WR bit. This will begin the block erase cycle. The write initiate sequence for EECON2, shown as steps 4 through 6 in Section7.5.1 “Flash Program 7. The CPU will stall for duration of the erase Memory Erase Sequence”, is used to guard against (about 2ms using internal timer). accidental writes. This is sometimes referred to as a 8. Re-enable interrupts. long write. A long write is necessary for erasing the internal Flash. Instruction execution is halted during the long write cycle. The long write is terminated by the internal programming timer. EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable block Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS30000684B-page 100  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 7.6 Writing to Flash Program Memory The long write is necessary for programming the internal Flash. Instruction execution is halted during a The programming block size is 64 bytes. Word or byte long write cycle. The long write will be terminated by programming is not supported. the internal programming timer. Table writes are used internally to load the holding The EEPROM on-chip timer controls the write time. registers needed to program the Flash memory. There The write/erase voltages are generated by an on-chip are only as many holding registers as there are bytes charge pump, rated to operate over the voltage range in a write block (64 bytes). of the device. Since the Table Latch (TABLAT) is only a single byte, Note: The default value of the holding registers on the TBLWT instruction needs to be executed 64 times device Resets and after write operations is for each programming operation. All of the table write FFh. A write of FFh to a holding register operations will essentially be short writes because only does not modify that byte. This means that the holding registers are written. After all the holding individual bytes of program memory may registers have been written, the programming be modified, provided that the change does operation of that block of memory is started by not attempt to change any bit from a ‘0’ to a configuring the EECON1 register for a program ‘1’. When modifying individual bytes, it is memory write and performing the long write sequence. not necessary to load all holding registers before executing a long write operation. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxx00 TBLPTR = xxxx01 TBLPTR = xxxx02 TBLPTR = xxxxYY(1) Holding Register Holding Register Holding Register Holding Register Program Memory Note1: YY = 3Fh for 64 byte write blocks. 7.6.1 FLASH PROGRAM MEMORY WRITE 8. Disable interrupts. SEQUENCE 9. Write 55h to EECON2. The sequence of events for programming an internal 10. Write 0AAh to EECON2. program memory location should be: 11. Set the WR bit. This will begin the write cycle. 1. Read 64 bytes into RAM. 12. The CPU will stall for duration of the write (about 2ms using internal timer). 2. Update data values in RAM as necessary. 13. Re-enable interrupts. 3. Load Table Pointer register with address being erased. 14. Verify the memory (table read). 4. Execute the block erase procedure. This procedure will require about 6ms to update each 5. Load Table Pointer register with address of first write block of memory. An example of the required code byte being written. is given in Example7-3. 6. Write the 64-byte block into the holding registers Note: Before setting the WR bit, the Table with auto-increment (TBLWT*+ or TBLWT+*). Pointer address needs to be within the 7. Set the EECON1 register for the write operation: intended address range of the bytes in the • set EEPGD bit to point to program memory; holding registers. • clear the CFGS bit to access program memory; • set WREN to enable writes.  2012-2014 Microchip Technology Inc. DS30000684B-page 101

PIC18(L)F2X/45K50 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64’ ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L WRITE_BUFFER_BACK MOVLW BlockSize ; number of bytes in holding register MOVWF COUNTER MOVLW D’64’/BlockSize ; number of write blocks in 64 bytes MOVWF COUNTER2 WRITE_BYTE_TO_HREGS MOVF POSTINC0, W ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DS30000684B-page 102  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) DECFSZ COUNTER ; loop until holding registers are full BRA WRITE_WORD_TO_HREGS PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) DCFSZ COUNTER2 ; repeat for remaining write blocks BRA WRITE_BYTE_TO_HREGS ; BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory 7.6.2 WRITE VERIFY 7.6.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the To protect against spurious writes to Flash program memory should be verified against the original value. memory, the write initiate sequence must also be This should be used in applications where excessive followed. See Section26.0 “Special Features of the writes can stress bits near the specification limit. CPU” for more detail. 7.6.3 UNEXPECTED TERMINATION OF 7.7 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section26.5 “Program Verification and Code location just programmed should be verified and Protection” for details on code protection of Flash reprogrammed if needed. If the write operation is program memory. interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the WRERR bit will be set which the user can check to decide whether a rewrite of the location(s) is needed. TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page TBLPTRU — — Program Memory Table Pointer Upper Byte (TBLPTR<21:16>) — TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) — TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) — TABLAT Program Memory Table Latch — INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 EECON2 EEPROM Control Register 2 (not a physical register) — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 97 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during Flash/EEPROM access.  2012-2014 Microchip Technology Inc. DS30000684B-page 103

PIC18(L)F2X/45K50 8.0 DATA EEPROM MEMORY 8.2 EECON1 and EECON2 Registers The data EEPROM is a nonvolatile memory array, Access to the data EEPROM is controlled by two separate from the data RAM and program memory, registers: EECON1 and EECON2. These are the same which is used for long-term storage of program data. It registers which control access to the program memory is not directly mapped in either the register file or and are used in a similar manner for the data program memory space but is indirectly addressed EEPROM. through the Special Function Registers (SFRs). The The EECON1 register (Register8-1) is the control EEPROM is readable and writable during normal register for data and program memory access. Control operation over the specified VDD range. bit EEPGD determines if the access will be to program Four SFRs are used to read and write to the data or data EEPROM memory. When the EEPGD bit is EEPROM as well as the program memory. They are: clear, operations will access the data EEPROM memory. When the EEPGD bit is set, program memory • EECON1 is accessed. • EECON2 Control bit, CFGS, determines if the access will be to • EEDATA the Configuration registers or to program memory/data • EEADR EEPROM memory. When the CFGS bit is set, The data EEPROM allows byte read and write. When subsequent operations access Configuration registers. interfacing to the data memory block, EEDATA holds When the CFGS bit is clear, the EEPGD bit selects the 8-bit data for read/write, and the EEADR register either program Flash or data EEPROM memory. holds the address of the EEPROM location being The WREN bit, when set, will allow a write operation. accessed. On power-up, the WREN bit is clear. The EEPROM data memory is rated for high erase/write The WRERR bit is set by hardware when the WR bit is cycle endurance. A byte write automatically erases the set and cleared when the internal programming timer location and writes the new data (erase-before-write). expires and the write operation is complete. The write time is controlled by an on-chip timer; it will vary with voltage and temperature as well as from chip- Note: During normal operation, the WRERR to-chip. Please refer to the Data EEPROM Memory may read as ‘1’. This can indicate that a parameters in Section29.0 “Electrical Specifica- write operation was prematurely termi- tions” for limits. nated by a Reset, or a write operation was attempted improperly. 8.1 EEADR Register The WR control bit initiates write operations. The bit The EEADR register is used to address the data can be set but not cleared by software. It is cleared only EEPROM for read and write operations. The 8-bit by hardware at the completion of the write operation. range of the register can address a memory range of Note: The EEIF interrupt flag bit of the PIR2 256 bytes (00h to FFh). register is set when the write is complete. It must be cleared by software. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section7.1 “Table Reads and Table Writes” regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. DS30000684B-page 104  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 8-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row (Block) Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) by software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition.  2012-2014 Microchip Technology Inc. DS30000684B-page 105

PIC18(L)F2X/45K50 8.3 Reading the Data EEPROM Additionally, the WREN bit in EECON1 must be set to Memory enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code To read a data memory location, the user must write the execution (i.e., runaway programs). The WREN bit address to the EEADR register, clear the EEPGD con- should be kept clear at all times, except when updating trol bit of the EECON1 register and then set control bit, the EEPROM. The WREN bit is not cleared by RD. The data is available on the very next instruction hardware. cycle; therefore, the EEDATA register can be read by After a write sequence has been initiated, EECON1, the next instruction. EEDATA will hold this value until EEADR and EEDATA cannot be modified. The WR bit another read operation, or until it is written to by the will be inhibited from being set unless the WREN bit is user (during a write operation). set. Both WR and WREN cannot be set with the same The basic process is shown in Example8-1. instruction. At the completion of the write cycle, the WR bit is 8.4 Writing to the Data EEPROM cleared by hardware and the EEPROM Interrupt Flag Memory bit, EEIF, is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by To write an EEPROM data location, the address must software. first be written to the EEADR register and the data writ- ten to the EEDATA register. The sequence in 8.5 Write Verify Example8-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly Depending on the application, good programming followed (write 55h to EECON2, write 0AAh to practice may dictate that the value written to the EECON2, then set WR bit) for each byte. It is strongly memory should be verified against the original value. recommended that interrupts be disabled during this This should be used in applications where excessive code segment. writes can stress bits near the specification limit. EXAMPLE 8-1: DATA EEPROM READ MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA EXAMPLE 8-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDR_LOW ; MOVWF EEADR ; Data Memory Address to write MOVLW DATA_EE_ADDR_HI ; MOVWF EEADRH ; MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable Interrupts ; User code execution BCF EECON1, WREN ; Disable writes on write complete (EEIF set) DS30000684B-page 106  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 8.6 Operation During Code-Protect The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, Data EEPROM memory has its own code-protect bits in power glitch or software malfunction. Configuration Words. External read and write operations are disabled if code protection is enabled. 8.8 Using the Data EEPROM The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the The data EEPROM is a high-endurance, byte addressable array that has been optimized for the code-protect Configuration bit. Refer to Section26.0 storage of frequently changing information (e.g., “Special Features of the CPU” for additional program variables or other data that are updated often). information. When variables in one section change frequently, while variables in another section do not change, it is possible 8.7 Protection Against Spurious Write to exceed the total number of write cycles to the There are conditions when the user may not want to EEPROM without exceeding the total number of write write to the data EEPROM memory. To protect against cycles to a single byte. Refer to the Data EEPROM spurious EEPROM writes, various mechanisms have Memory parameters in Section29.0 “Electrical been implemented. On power-up, the WREN bit is Specifications” for write cycle limits. If this is the case, cleared. In addition, writes to the EEPROM are blocked then an array refresh must be performed. For this during the Power-up Timer period (TPWRT). reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example8-3. Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification. EXAMPLE 8-3: DATA EEPROM REFRESH ROUTINE CLRF EEADR ; Start at address 0 BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes Loop ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA LOOP ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts  2012-2014 Microchip Technology Inc. DS30000684B-page 107

PIC18(L)F2X/45K50 TABLE 8-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 — EEDATA EEPROM Data Register — EECON2 EEPROM Control Register 2 (not a physical register) — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 105 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during EEPROM access. DS30000684B-page 108  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 9.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 9-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 9.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY operation does not affect any flags in the STATUS ROUTINE register. MOVF ARG1, W Making multiplication a hardware operation allows it to MULWF ARG2 ; ARG1 * ARG2 -> be completed in a single instruction cycle. This has the ; PRODH:PRODL advantages of higher computational throughput and BTFSC ARG2, SB ; Test Sign Bit reduced code size for multiplication algorithms and SUBWF PRODH, F ; PRODH = PRODH allows the PIC18 devices to be used in many applica- ; - ARG1 tions previously reserved for digital signal processors. MOVF ARG2, W BTFSC ARG1, SB ; Test Sign Bit A comparison of various hardware and software SUBWF PRODH, F ; PRODH = PRODH multiply operations, along with the savings in memory ; - ARG2 and execution time, is shown in Table9-1. 9.2 Operation Example9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 48 MHz @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 5.7 s 6.9 s 27.6 s 69 s 8 x 8 unsigned Hardware multiply 1 1 83.3 ns 100 ns 400 ns 1 s Without hardware multiply 33 91 7.5 s 9.1 s 36.4 s 91 s 8 x 8 signed Hardware multiply 6 6 500 ns 600 ns 2.4 s 6 s Without hardware multiply 21 242 20.1 s 24.2 s 96.8 s 242 s 16 x 16 unsigned Hardware multiply 28 28 2.3 s 2.8 s 11.2 s 28 s Without hardware multiply 52 254 21.6 s 25.4 s 102.6 s 254 s 16 x 16 signed Hardware multiply 35 40 3.3 s 4.0 s 16.0 s 40 s  2012-2014 Microchip Technology Inc. DS30000684B-page 109

PIC18(L)F2X/45K50 Example9-3 shows the sequence to do a 16 x 16 EQUATION 9-2: 16 x 16 SIGNED unsigned multiplication. Equation9-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES<3:0>). RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L = (ARG1H  ARG2H  216) + EQUATION 9-1: 16 x 16 UNSIGNED (ARG1H  ARG2L  28) + MULTIPLICATION (ARG1L  ARG2H  28) + ALGORITHM (ARG1L  ARG2L) + (-1  ARG2H<7>  ARG1H:ARG1L  216) + RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L (-1  ARG1H<7>  ARG2H:ARG2L  216) = (ARG1H  ARG2H  216) + (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + EXAMPLE 9-4: 16 x 16 SIGNED (ARG1L  ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 9-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example9-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation9-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers (RES<3:0>). To account for the sign bits of the argu- SIGN_ARG1 ments, the MSb for each argument pair is tested and BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? the appropriate subtractions are done. BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 CONT_CODE : DS30000684B-page 110  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 10.0 INTERRUPTS 10.2 Interrupt Priority The PIC18(L)F2X/45K50 devices have multiple The interrupt priority feature is enabled by setting the interrupt sources and an interrupt priority feature that IPEN bit of the RCON register. When interrupt priority allows most interrupt sources to be assigned a high or is enabled the GIE/GIEH and PEIE/GIEL global inter- low priority level (INT0 does not have a priority bit, it is rupt enable bits of Compatibility mode are replaced by always a high priority). The high priority interrupt vector the GIEH high priority, and GIEL low priority, global is at 0008h and the low priority interrupt vector is at interrupt enables. When set, the GIEH bit of the INT- 0018h. A high priority interrupt event will interrupt a low CON register enables all interrupts that have their priority interrupt that may be in progress. associated IPRx register or INTCONx register priority bit set (high priority). When clear, the GIEH bit disables There are 13 registers used to control interrupt all interrupt sources including those selected as low pri- operation. ority. When clear, the GIEL bit of the INTCON register These registers are: disables only the interrupts that have their associated • INTCON, INTCON2, INTCON3 priority bit cleared (low priority). When set, the GIEL bit enables the low priority sources when the GIEH bit is • PIR1, PIR2, PIR3 also set. • PIE1, PIE2, PIE3 When the interrupt flag, enable bit and appropriate • IPR1, IPR2, IPR3 Global Interrupt Enable (GIE) bit are all set, the • RCON interrupt will vector immediately to address 0008h for It is recommended that the Microchip header files high priority, or 0018h for low priority, depending on supplied with MPLAB® IDE be used for the symbolic bit level of the interrupting source’s priority bit. Individual names in these registers. This allows the assembler/ interrupts can be disabled through their corresponding compiler to automatically take care of the placement of interrupt enable bits. these bits within the specified register. In general, interrupt sources have three bits to control 10.3 Interrupt Response their operation. They are: When an interrupt is responded to, the Global Interrupt • Flag bit to indicate that an interrupt event Enable bit is cleared to disable further interrupts. The occurred GIE/GIEH bit is the global interrupt enable when the • Enable bit that allows program execution to IPEN bit is cleared. When the IPEN bit is set, enabling branch to the interrupt vector address when the interrupt priority levels, the GIEH bit is the high priority flag bit is set global interrupt enable and the GIEL bit is the low • Priority bit to select high priority or low priority priority global interrupt enable. High priority interrupt sources can interrupt a low priority interrupt. Low 10.1 Mid-Range Compatibility priority interrupts are not processed while high priority interrupts are in progress. When the IPEN bit is cleared (default state), the interrupt The return address is pushed onto the stack and the priority feature is disabled and interrupts are compatible PC is loaded with the interrupt vector address (0008h with PIC microcontroller mid-range devices. In or 0018h). Once in the Interrupt Service Routine, the Compatibility mode, the interrupt priority bits of the IPRx source(s) of the interrupt can be determined by polling registers have no effect. The PEIE/GIEL bit of the the interrupt flag bits in the INTCONx and PIRx INTCON register is the global interrupt enable for the registers. The interrupt flag bits must be cleared by peripherals. The PEIE/GIEL bit disables only the software before re-enabling interrupts to avoid peripheral interrupt sources and enables the peripheral repeating the same interrupt. interrupt sources when the GIE/GIEH bit is also set. The GIE/GIEH bit of the INTCON register is the global The “return from interrupt” instruction, RETFIE, exits interrupt enable which enables all non-peripheral the interrupt routine and sets the GIE/GIEH bit (GIEH interrupt sources and disables all interrupt sources, or GIEL if priority levels are used), which re-enables including the peripherals. All interrupts branch to interrupts. address 0008h in Compatibility mode. For external interrupt events, such as the INT pins or the PORTB interrupt-on-change, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one-cycle or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bits or the Global Interrupt Enable bit.  2012-2014 Microchip Technology Inc. DS30000684B-page 111

PIC18(L)F2X/45K50 Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. FIGURE 10-1: PIC18 INTERRUPT LOGIC Wake-up if in INT0IF Idle or Sleep modes INT0IE TMR0IF TMR0IE TMR0IP IOCIF (1) IOCIE IOCIP INT1IF Interrupt to CPU PIR1<7:0> INT1IE Vector to Location PIE1 <7:0> INT1IP 0008h IPR1 <7:0> INT2IF PIR2<7:0> INT2IE PIE2<7:0> INT2IP IPR2<7:0> GIEH/GIE PIR3<7:0> PIE3<7:0> IPR3<7:0> IPEN IPEN GIEL/PEIE IPEN High Priority Interrupt Generation Low Priority Interrupt Generation PIR1<7:0> PIE1 <7:0> IPR1 <7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> TMR0IF IVnetectrorur ptot tLoo CcPatUion TMR0IE 0018h TMR0IP (1) IOCIF IOCIE IOCIP GIEH/GIE GIEL/PEIE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Note 1: The IOCIF interrupt also requires the individual pin IOCB enables. DS30000684B-page 112  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 10.4 INTCON Registers The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. 10.5 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request Flag registers (PIR1, PIR2 and PIR3). 10.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When IPEN = 0, the PEIE/GIEL bit must be set to enable any of these peripheral interrupts. 10.7 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.  2012-2014 Microchip Technology Inc. DS30000684B-page 113

PIC18(L)F2X/45K50 10.8 Register Definitions: Interrupt Control REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts including peripherals When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts including low priority bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority interrupts 0 = Disables all low priority interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 IOCIE: Interrupt-On-Change (IOCx) Interrupt Enable bit(2) 1 = Enables the IOCx port change interrupt 0 = Disables the IOCx port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared by software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared by software) 0 = The INT0 external interrupt did not occur bit 0 IOCIF: Interrupt-On-Change (IOCx) Interrupt Flag bit(1) 1 = At least one of the IOC pins changed state (must be cleared by software) 0 = None of the IOC pins have changed state Note 1: A mismatch condition will continue to set the IOCIF bit. Reading PORTB/PORTC will end the mismatch condition and allow the bit to be cleared. 2: Port change interrupts also require the individual pins IOCBx/IOCCx enables. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS30000684B-page 114  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 10-2: INTCON2: INTERRUPT CONTROL 2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled provided that the pin is an input and the corresponding WPUB bit is set. bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 IOCIP: Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2012-2014 Microchip Technology Inc. DS30000684B-page 115

PIC18(L)F2X/45K50 REGISTER 10-3: INTCON3: INTERRUPT CONTROL 3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared by software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared by software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS30000684B-page 116  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ACTIF: Active Clock Tuning Interrupt Flag bit 1 = An Active Clock Tuning Event generated an interrupt (must be cleared in software) 0 = No Active Clock Tuning interrupt is pending bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared by software) 0 = The A/D conversion is not complete or has not been started bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared by software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared by software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared by software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared by software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared by software) 0 = TMR1 register did not overflow Note1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE/ GIEH of the INTCON register. 2: User software should ensure the appro- priate interrupt flag bits are cleared prior to enabling an interrupt and after servic- ing that interrupt.  2012-2014 Microchip Technology Inc. DS30000684B-page 117

PIC18(L)F2X/45K50 REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software) 0 = Device clock operating bit 6 C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator C1 output has changed (must be cleared by software) 0 = Comparator C1 output has not changed bit 5 C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator C2 output has changed (must be cleared by software) 0 = Comparator C2 output has not changed bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared by software) 0 = The write operation is not complete or has not been started bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared by software) 0 = No bus collision occurred bit 2 HLVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (direction determined by the VDIRMAG bit of the HLVDCON register) 0 = A low-voltage condition has not occurred bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared by software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared by software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared by software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. DS30000684B-page 118  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT (FLAG) REGISTER 3 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CTMUIF USBIF TMR3GIF TMR1GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUIF: CTMU Interrupt Flag bit 1 = CTMU interrupt occurred (must be cleared in software) 0 = No CTMU interrupt occurred bit 2 USBIF: USB Interrupt Flag bit 1 = USB requested an interrupt (must be cleared in software) 0 = No USB interrupt request bit 1 TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate occurred bit 0 TMR1GIF: TMR1 Gate Interrupt Flag bit 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate occurred  2012-2014 Microchip Technology Inc. DS30000684B-page 119

PIC18(L)F2X/45K50 REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ACTIE: Active Clock Tuning Interrupt Enable bit 1 = Enables Active Clock Tuning interrupt 0 = Disables Active Clock Tuning interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS30000684B-page 120  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 C1IE: Comparator C1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 C2IE: Comparator C2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled  2012-2014 Microchip Technology Inc. DS30000684B-page 121

PIC18(L)F2X/45K50 REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 3 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CTMUIE USBIE TMR3GIE TMR1GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUIE: CTMU Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 USBIE: USB Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3GIE: TMR3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1GIE: TMR1 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled DS30000684B-page 122  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ACTIP: Active Clock Tuning Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority  2012-2014 Microchip Technology Inc. DS30000684B-page 123

PIC18(L)F2X/45K50 REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 C1IP: Comparator C1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 C2IP: Comparator C2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: MSSP Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority DS30000684B-page 124  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — CTMUIP USBIP TMR3GIP TMR1GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUIP: CTMU Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 USBIP: USB Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1GIP: TMR1 Gate Interrupt Priority bit 1 = High priority 0 = Low priority  2012-2014 Microchip Technology Inc. DS30000684B-page 125

PIC18(L)F2X/45K50 10.9 INTn Pin Interrupts 10.10 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1 and In 8-bit mode (which is the default), an overflow in the RB2/INT2 pins are edge-triggered. If the corresponding TMR0 register (FFh00h) will set flag bit, TMR0IF. In INTEDGx bit in the INTCON2 register is set (= 1), the 16-bit mode, an overflow in the TMR0H:TMR0L regis- interrupt is triggered by a rising edge; if the bit is clear, ter pair (FFFFh 0000h) will set TMR0IF. The interrupt the trigger is on the falling edge. When a valid edge can be enabled/disabled by setting/clearing enable bit, appears on the RBx/INTx pin, the corresponding flag TMR0IE of the INTCON register. Interrupt priority for bit, INTxF, is set. This interrupt can be disabled by Timer0 is determined by the value contained in the clearing the corresponding enable bit, INTxE. Flag bit, interrupt priority bit, TMR0IP of the INTCON2 register. INTxF, must be cleared by software in the Interrupt See Section12.0 “Timer0 Module” for further details Service Routine before re-enabling the interrupt. on the Timer0 module. All external interrupts (INT0, INT1 and INT2) can wake- 10.11 PORTB/PORTC Interrupt-on- up the processor from Idle or Sleep modes if bit INTxE was set prior to going into those modes. If the Global Change Interrupt Enable bit, GIE/GIEH, is set, the processor An input change on PORTB<7:4> or PORTC<2:0> sets will branch to the interrupt vector following wake-up. flag bit, IOCIF of the INTCON register. The interrupt Interrupt priority for INT1 and INT2 is determined by can be enabled/disabled by setting/clearing enable bit, the value contained in the interrupt priority bits, INT1IP IOCIE of the INTCON register. Pins must also be and INT2IP of the INTCON3 register. There is no prior- individually enabled with the IOCB/IOCC register. ity bit associated with INT0. It is always a high priority Interrupt priority for interrupt-on-change is determined interrupt source. by the value contained in the interrupt priority bit, IOCIP of the INTCON2 register. 10.12 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section6.2.2 “Fast Register Stack”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 10-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS30000684B-page 126  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 10-1: REGISTERS ASSOCIATED WITH INTERRUPTS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP 115 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 116 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 151 IOCC IOCC7 IOCC6 IOCC5 IOCC4 — IOCC2 IOCC1 IOCC0 151 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 IPR3 — — — — CTMUIP USBIP TMR3GIP TMR1GIP 125 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIE3 — — — — CTMUIE USBIE TMR3GIE TMR1GIE 122 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PIR3 — — — — CTMUIF USBIF TMR3GIF TMR1GIF 119 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 146 RCON IPEN SBOREN — RI TO PD POR BOR 64 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for interrupts. TABLE 10-2: CONFIGURATION REGISTERS ASSOCIATED WITH INTERRUPTS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 CONFIG4L DEBUG XINST ICPRT — — LVP — STRVEN 377 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for interrupts.  2012-2014 Microchip Technology Inc. DS30000684B-page 127

PIC18(L)F2X/45K50 11.0 I/O PORTS 11.1 PORTA Registers Depending on the device selected and features PORTA is an 8-bit wide, bidirectional port. The enabled, there are up to five ports available. All pins of corresponding data direction register is TRISA. Setting the I/O ports are multiplexed with one or more alternate a TRISA bit (= 1) will make the corresponding PORTA functions from the peripheral features on the device. In pin an input (i.e., disable the output driver). Clearing a general, when a peripheral is enabled, that pin may not TRISA bit (= 0) will make the corresponding PORTA pin be used as a general purpose I/O pin. an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Each port has five registers for its operation. These registers are: Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the PORT latch. • TRIS register (data direction register) • PORT register (reads the levels on the pins of the The Data Latch (LATA) register is also memory mapped. device) Read-modify-write operations on the LATA register read and write the latched output value for PORTA. • LAT register (output latch) • ANSEL register (analog input control) The RA4 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to • SLRCON register (port slew rate control) become the RA4/T0CKI/C1OUT pin. Pins RA6 and The Data Latch (LAT register) is useful for read-modify- RA7 are multiplexed with the main oscillator pins; they write operations on the value that the I/O pins are are enabled as oscillator or I/O pins by the selection of driving. the main oscillator in the Configuration register (see A simplified model of a generic I/O port, without the Section26.1 “Configuration Bits” for details). When interfaces to other peripherals, is shown in Figure11-1. they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’. FIGURE 11-1: GENERIC I/O PORT The other PORTA pins are multiplexed with analog OPERATION inputs, the analog VREF+ and VREF- inputs, and the comparator voltage reference output. The operation of pins RA<3:0> and RA5 as analog is selected by setting RD LAT TRISx the ANSELA<5, 3:0> bits in the ANSELA register which Data is the default setting after a Power-on Reset. Bus D Q Pins RA0 through RA5 may also be used as comparator WR LAT I/O pin(1) inputs or outputs by setting the appropriate bits in the orPort CK CM1CON0 and CM2CON0 registers. Data Latch Note: On a Power-on Reset, RA5 and RA<3:0> D Q are configured as analog inputs and read ANSELx as ‘0’. RA4 is configured as a digital input. WR TRIS CK The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input. TRIS Latch Input All other PORTA pins have TTL input levels and full Buffer CMOS output drivers. RD TRIS The TRISA register controls the drivers of the PORTA pins, even when they are being used as analog inputs. Q D The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. ENEN EXAMPLE 11-1: INITIALIZING PORTA RD Port MOVLB 0xF ; Set BSR for banked SFRs CLRF LATA ; Initialize PORTA by Note1: I/O pins have diode protection to VDD and VSS. ; clearing output ; data latches CLRF ANSELA ; Configure I/O ; for digital inputs MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs DS30000684B-page 128  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 11-1: PORTA I/O SUMMARY TRIS ANSEL Pin Buffer Pin Name Function Description Setting Setting Type Type RA0/C12IN0-/AN0 RA0 0 x O DIG LATA<0> data output; not affected by analog input. 1 0 I TTL PORTA<0> data input; disabled when analog input enabled. C12IN0- 1 1 I AN Comparators C1 and C2 inverting input. AN0 1 1 I AN Analog input 0. RA1/C12IN1-/AN1 RA1 0 x O DIG LATA<1> data output; not affected by analog input. 1 0 I TTL PORTA<1> data input; disabled when analog input enabled. C12IN1- 1 1 I AN Comparators C1 and C2 inverting input. AN1 1 1 I AN Analog input 1. RA2/C2IN+/AN2/ RA2 0 x O DIG LATA<2> data output; not affected by analog input; disabled DACOUT/VREF- when DACOUT enabled. 1 0 I TTL PORTA<2> data input; disabled when analog input enabled; disabled when DACOUT enabled. C2IN+ 1 1 I AN Comparator C2 non-inverting input. AN2 1 1 I AN Analog output 2. DACOUT x 1 O AN DAC Reference output. VREF- 1 1 I AN A/D reference voltage (low) input. RA3/C1IN+/AN3/ RA3 0 x O DIG LATA<3> data output; not affected by analog input. VREF+ 1 0 I TTL PORTA<3> data input; disabled when analog input enabled. C1IN+ 1 1 I AN Comparator C1 non-inverting input. AN3 1 1 I AN Analog input 3. VREF+ 1 1 I AN A/D reference voltage (high) input. RA4/C1OUT/SRQ/ RA4 0 — O DIG LATA<4> data output. T0CKI 1 — I ST PORTA<4> data input; default configuration on POR. C1OUT 0 — O DIG Comparator C1 output. SRQ 0 — O DIG SR latch Q output; take priority over CCP 5 output. T0CKI 1 — I ST Timer0 external clock input. RA5/C2OUT/ RA5 0 x O DIG LATA<5> data output; not affected by analog input. SRNQ/SS1/ 1 0 I TTL PORTA<5> data input; disabled when analog input enabled. HLVDIN/AN4 C2OUT 0 0 O DIG Comparator C2 output. SRNQ 0 0 O DIG SR latch Q output. SS1 1 0 I TTL SPI slave select input (MSSP). HLVDIN 1 1 I AN High/Low-Voltage Detect input. AN4 1 1 I AN A/D input 4. RA6/CLKO/OSC2 RA6 0 — O DIG LATA<6> data output; enabled in INTOSC modes when CLKO is not enabled. 1 — I TTL PORTA<6> data input; enabled in INTOSC modes when CLKO is not enabled. CLKO x — O DIG In RC mode, OSC2 pin outputs CLKO which has 1/4 the fre- quency of OSC1 and denotes the instruction cycle rate. OSC2 x — O XTAL Oscillator crystal output; connects to crystal or resonator in Crystal Oscillator mode. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C.  2012-2014 Microchip Technology Inc. DS30000684B-page 129

PIC18(L)F2X/45K50 TABLE 11-1: PORTA I/O SUMMARY (CONTINUED) TRIS ANSEL Pin Buffer Pin Name Function Description Setting Setting Type Type RA7/CLKI/OSC1 RA7 0 — O DIG LATA<7> data output; disabled in external oscillator modes. 1 — I TTL PORTA<7> data input; disabled in external oscillator modes. CLKI x — I AN External clock source input; always associated with pin function OSC1. OSC1 x — I XTAL Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C. TABLE 11-2: REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 147 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH<1:0> 307 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH<1:0> 307 VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 334 VREFCON2 — — — DACR<4:0> 335 HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> 364 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 146 LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 150 SLRCON — — — SLRE SLRD SLRC SLRB SLRA 152 SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 328 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 252 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS<2:0> 153 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTA. TABLE 11-3: CONFIGURATION REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG1H IESO FCMEN PCLKEN — FOSC<3:0> 373 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTA. DS30000684B-page 130  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 11.1.1 PORTA OUTPUT PRIORITY Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table11-4 lists the PORTA pin functions from the highest to the lowest priority. Analog input functions, such as ADC and comparator, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below.  2012-2014 Microchip Technology Inc. DS30000684B-page 131

PIC18(L)F2X/45K50 TABLE 11-4: PORT PIN FUNCTION PRIORITY Port Function Priority by Port Pin Port bit PORTA PORTB PORTC PORTD(2) PORTE(2) 0 RA0 SDA SOSCO RB0 RC0 RD0 RE0 1 RA1 SCL SOSCI SCK CCP2(3) RE1 P1C(1) RD1 RB1 RC1 2 DACOUT CCP1 RA2 P1B(1) P1A RD2 RE2 RB2 CTPLS RC2 3 RA3 SDO(3) MCLR CCP2(4) RD3 VPP RE3 RB3 4 SRQ P1D(1) D- C1OUT RB4 RD4 RA4 5 SRNQ D+ P1B C2OUT RD5 RA5 RB5 6 OSC2 PGC TX/CK CLKO ICDCK P1C RA6 RB6 RD6 RC6 7 OSC1 PGD RX/DT RA7 ICDDT P1D RB7 RC7 RD7 Note 1: PIC18(L)F2XK50 devices. 2: PIC18(L)F45K50 devices. 3: Function default pin. 4: Function alternate pin. DS30000684B-page 132  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 11.2 PORTB Registers 11.3 Additional PORTB Pin Functions PORTB is an 8-bit wide, bidirectional port. The PORTB pins RB<7:4> have an interrupt-on-change corresponding data direction register is TRISB. Setting option. All PORTB pins have a weak pull-up option. a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a 11.3.1 WEAK PULL-UPS TRISB bit (= 0) will make the corresponding PORTB Each of the PORTB pins has an individually controlled pin an output (i.e., enable the output driver and put the weak internal pull-up. When set, each bit of the WPUB contents of the output latch on the selected pin). register enables the corresponding pin pull-up. When The Data Latch register (LATB) is also memory cleared, the RBPU bit of the INTCON2 register enables mapped. Read-modify-write operations on the LATB pull-ups on all pins which also have their corresponding register read and write the latched output value for WPUB bit set. When set, the RBPU bit disables all PORTB. weak pull-ups. The weak pull-up is automatically turned off when the port pin is configured as an output. The EXAMPLE 11-2: INITIALIZING PORTB pull-ups are disabled on a Power-on Reset. MOVLB 0xF ; Set BSR for banked SFRs Note: On a Power-on Reset, RB<5:0> are CLRF LATB ; Initialize PORTB by configured as analog inputs by default and ; clearing output read as ‘0’; RB<7:6> are configured as ; data latches digital inputs. MOVLW 0F0h ; Value for init MOVWF ANSELB ; Enable RB<3:0> for When the PBADEN Configuration bit is ; digital input pins set to ‘0’, RB<5:0> will alternatively be ; (not required if config bit configured as digital inputs on POR. ; PBADEN is clear) MOVLW 0CFh ; Value used to 11.3.2 INTERRUPT-ON-CHANGE ; initialize data ; direction Four of the PORTB pins (RB<7:4>) are individually MOVWF TRISB ; Set RB<3:0> as inputs configurable as interrupt-on-change pins. Control bits ; RB<5:4> as outputs in the IOCB register enable (when set) or disable (when ; RB<7:6> as inputs clear) the interrupt function for each pin. When set, the IOCIE bit of the INTCON register enables interrupts on all pins which also have their corresponding IOCB bit set. When clear, the IOCIE bit disables all interrupt-on-changes. 11.2.1 PORTB OUTPUT PRIORITY Only pins configured as inputs can cause this interrupt Each PORTB pin is multiplexed with other functions. to occur (i.e., any RB<7:4> pin configured as an output The pins, their combined functions and their output is excluded from the interrupt-on-change comparison). priorities are briefly described here. For additional For enabled interrupt-on-change pins, the values are information, refer to the appropriate section in this data compared with the old value latched on the last read of sheet. PORTB. The ‘mismatch’ outputs of the last read are When multiple outputs are enabled, the actual pin OR’d together to set the interrupt-on-change Interrupt control goes to the peripheral with the higher priority. flag bit (IOCIF) in the INTCON register. Table11-4 lists the PORTB pin functions from the This interrupt can wake the device from the Sleep highest to the lowest priority. mode, or any of the Idle modes. The user, in the Analog input functions, such as ADC, comparator and Interrupt Service Routine, can clear the interrupt in the SR latch inputs, are not shown in the priority lists. following manner: These inputs are active when the I/O pin is set for a) Any read or write of PORTB to clear the mis- Analog mode using the ANSELx registers. Digital match condition (except when PORTB is the output functions may control the pin when it is in Analog source or destination of a MOVFF instruction). mode with the priority shown below. b) Execute at least one instruction after reading or writing PORTB, then clear the flag bit, IOCIF.  2012-2014 Microchip Technology Inc. DS30000684B-page 133

PIC18(L)F2X/45K50 A mismatch condition will continue to set the IOCIF flag 11.3.3 ALTERNATE FUNCTIONS bit. Reading or writing PORTB will end the mismatch PORTB is multiplexed with several peripheral functions condition and allow the IOCIF bit to be cleared. The latch (Table11-5). The pins have TTL input buffers. Some of holding the last read value is not affected by a MCLR nor these pin functions can be relocated to alternate pins Brown-out Reset. After either one of these Resets, the using the Control fuse bits in CONFIG3H. RB3 is the IOCIF flag will continue to be set if a mismatch is present. default pin for SDO. Clearing the SDOMX bit moves the Note: If a change on the I/O pin should occur SDO pin function to RC7. when the read operation is being executed Two other pin functions, T3CKI and CCP2, can be (start of the Q2 cycle), then the IOCIF relocated from their default pins to PORTB pins by interrupt flag may not getset. Furthermore, clearing the control fuses in CONFIG3H. Clearing since a read or write on a port affects all T3CMX and CCP2MX moves the pin functions to RB5 bits of that port, care must be taken when and RB3, respectively. using multiple pins in Interrupt-on-Change mode. Changes on one pin may not be seen while servicing changes on another pin. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. TABLE 11-5: PORTB I/O SUMMARY TRIS ANSEL Pin Buffer Pin Function Description Setting Setting Type Type RB0/INT0/FLT0/ RB0 0 x O DIG LATB<0> data output; not affected by analog input. SRI/SDA/SDI/AN12 1 0 I TTL PORTB<0> data input; disabled when analog input enabled. INT0 1 0 I ST External interrupt 0. FLT0 1 0 I ST PWM Fault input for ECCP auto-shutdown. SRI 1 0 I ST SR latch input. SDA 1 0 I/O I2C™ I2C Data I/O (MSSP). SDI 1 0 I ST SPI Data in (MSSP). AN12 1 1 I AN Analog input 12. RB1/INT1/P1C/ RB1 0 x O DIG LATB<1> data output; not affected by analog input. SCK/SCL/C12IN3-/ 1 0 I TTL PORTB<1> data input; disabled when analog input AN10 enabled. INT1 1 0 I ST External Interrupt 1. P1C(3) 0 0 O DIG Enhanced CCP1 PWM output 3. SCK 0 0 O DIG MSSP SPI Clock output. 1 0 I ST MSSP SPI Clock input. SCL 0 0 O DIG MSSP I2C Clock output. 1 0 I I2C MSSP I2C Clock input. C12IN3- 1 1 I AN Comparators C1 and C2 inverting input. AN10 1 1 I AN Analog input 10. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Note 1: Default pin assignment for SDO when Configuration bit SDOMX is set. 2: Alternate pin assignment for T3CKI and CCP2 when Configuration bits T3CMX and CCP2MX are clear. 3: Function is on PORTD/PORTE for PIC18(L)F45K50 devices. DS30000684B-page 134  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 11-5: PORTB I/O SUMMARY (CONTINUED) TRIS ANSEL Pin Buffer Pin Function Description Setting Setting Type Type RB2/INT2/CTED1/ RB2 0 x O DIG LATB<2> data output; not affected by analog input. P1B/AN8 1 0 I TTL PORTB<2> data input; disabled when analog input enabled. INT2 1 0 I ST External interrupt 2. CTED1 1 0 I ST CTMU Edge 1 input. P1B(3) 0 0 O DIG Enhanced CCP1 PWM output 2. AN8 1 1 I AN Analog input 8. RB3/CTED2/CCP2/ RB3 0 x O DIG LATB<3> data output; not affected by analog input. SDO/C12IN2-/AN9 1 0 I TTL PORTB<3> data input; disabled when analog input enabled. CTED2 1 0 I ST CTMU Edge 2 input. CCP2(2) 0 0 O DIG Compare 2 output/PWM 2 output. 1 0 I ST Capture 2 input. SDO(1) 0 0 O DIG MSSP SPI data output. C12IN2- 1 1 I AN Comparators C1 and C2 inverting input. AN9 1 1 I AN Analog input 9. RB4/IOCB4/P1D/ RB4 0 x O DIG LATB<4> data output; not affected by analog input. AN11 1 0 I TTL PORTB<4> data input; disabled when analog input enabled. IOCB4 1 0 I TTL Interrupt-on-change pin. P1D(3) 0 0 O DIG Enhanced CCP1 PWM output 4. AN11 1 1 I AN Analog input 11. RB5/IOCB5/T3CKI/ RB5 0 x O DIG LATB<5> data output; not affected by analog input. T1G/AN13 1 0 I TTL PORTB<5> data input; disabled when analog input enabled. IOCB5 1 0 I TTL Interrupt-on-change pin 1. T3CKI(2) 1 0 I ST Timer3 clock input. T1G 1 0 I ST Timer1 external clock gate input. AN13 1 1 I AN Analog input 13. RB6/IOCB6/PGC RB6 0 — O DIG LATB<6> data output; not affected by analog input. 1 — I TTL PORTB<6> data input; disabled when analog input enabled. IOCB6 1 — I TTL Interrupt-on-change pin. PGC x — I ST In-Circuit Debugger and ICSPTM programming clock input. RB7/IOCB7/PGD RB7 0 — O DIG LATB<7> data output; not affected by analog input. 1 — I TTL PORTB<7> data input; disabled when analog input enabled. IOCB7 1 — I TTL Interrupt-on-change pin. PGD x — O DIG In-Circuit Debugger and ICSPTM programming data output. x — I ST In-Circuit Debugger and ICSPTM programming data input. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Note 1: Default pin assignment for SDO when Configuration bit SDOMX is set. 2: Alternate pin assignment for T3CKI and CCP2 when Configuration bits T3CMX and CCP2MX are clear. 3: Function is on PORTD/PORTE for PIC18(L)F45K50 devices.  2012-2014 Microchip Technology Inc. DS30000684B-page 135

PIC18(L)F2X/45K50 TABLE 11-6: REGISTERS ASSOCIATED WITH PORTB Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148 ECCP1AS ECCP1ASE ECCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 201 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 197 CCP2CON — — DC2B<1:0> CCP2M<3:0> 197 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP 115 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 116 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 151 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 150 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 146 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 152 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 166 T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC RD16 TMR3ON 165 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 150 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB. Note 1: Available on PIC18(L)F45K50 devices only. TABLE 11-7: CONFIGURATION REGISTERS ASSOCIATED WITH PORTB Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 CONFIG4L DEBUG XINST ICPRT — — LVP(1) — STRVEN 377 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB. Note 1: Can only be changed when in high voltage programming mode. DS30000684B-page 136  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 11.4 PORTC Registers 11.4.1 PORTC OUTPUT PRIORITY PORTC is an 8-bit wide, bidirectional port. The Each PORTC pin is multiplexed with other functions. corresponding data direction register is TRISC. Setting The pins, their combined functions and their output a TRISC bit (= 1) will make the corresponding PORTC priorities are briefly described here. For additional pin an input (i.e., disable the output driver). Clearing a information, refer to the appropriate section in this data TRISC bit (= 0) will make the corresponding PORTC sheet. pin an output (i.e., enable the output driver and put the When multiple outputs are enabled, the actual pin contents of the output latch on the selected pin). control goes to the peripheral with the higher priority. The Data Latch register (LATC) is also memory Table11-4 lists the PORTC pin functions from the mapped. Read-modify-write operations on the LATC highest to the lowest priority. register read and write the latched output value for Analog input functions, such as ADC, comparator and PORTC. SR latch inputs, are not shown in the priority lists. PORTC is multiplexed with several peripheral functions These inputs are active when the I/O pin is set for (Table11-8). The pins have Schmitt Trigger input buf- Analog mode using the ANSELx registers. Digital fers. output functions may control the pin when it is in Analog Some of these pin functions can be relocated to alter- mode with the priority shown below. nate pins using the Control fuse bits in CONFIG3H. 11.4.2 INTERRUPT-ON-CHANGE RC0 is the default pin for T3CKI. Clearing the T3CMX bit moves the pin function to RB5. RC1 is the default pin All of the PORTC pins (RC<7:4> and RC<2:0>) are for the CCP2 peripheral pin. Clearing the CCP2MX bit individually configurable as interrupt-on-change pins. moves the pin function to the RB3 pin. Control bits in the IOCC register enable (when set) or When enabling peripheral functions, care should be disable (when clear) the interrupt function for each pin. taken in defining TRIS bits for each PORTC pin. The See Section11.3.2 “Interrupt-on-Change” for EUSART and MSSP peripherals override the TRIS bit details on operation of interrupt-on-change. to make a pin an output or an input, depending on the peripheral configuration. Refer to the corresponding peripheral section for additional information. Note: On a Power-on Reset, these pins are configured as analog inputs. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. EXAMPLE 11-3: INITIALIZING PORTC MOVLB 0xF ; Set BSR for banked SFRs CLRF LATC ; Initialize PORTC by ; clearing output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs MOVLW 30h ; Value used to ; enable digital inputs MOVWF ANSELC ; RC<3:2> dig input enable ; No ANSEL bits for RC<1:0> ; RC<7:6> dig input enable  2012-2014 Microchip Technology Inc. DS30000684B-page 137

PIC18(L)F2X/45K50 TABLE 11-8: PORTC I/O SUMMARY TRIS ANSEL Pin Buffer Pin Name Function Description Setting setting Type Type RC0/IOCC0/T3CKI/ RC0 0 — O DIG LATC<0> data output; not affected by analog input. T3G/T1CKI/SOSCO 1 — I ST PORTC<0> data input; disabled when analog input enabled. IOCC0 1 — I TTL Interrupt-on-change pin. T3CKI(1) 1 — I ST Timer3 clock input. T3G 1 — I ST Timer3 external clock gate input. T1CKI 1 — I ST Timer1 clock input. SOSCO x — O XTAL Secondary oscillator output. RC1/IOCC1/CCP2/ RC1 0 — O DIG LATC<1> data output; not affected by analog input. SOSCI 1 — I ST PORTC<1> data input; disabled when analog input enabled. IOCC1 1 — I TTL Interrupt-on-change pin. CCP2(1) 0 — O DIG Compare 2 output/PWM 2 output. 1 — I ST Capture 2 input. SOSCI x — I XTAL Secondary oscillator input. RC2/CTPLS/P1A/ RC2 0 0 O DIG LATC<2> data output; not affected by analog input. CCP1/IOCC2/AN14 1 0 I ST PORTC<2> data input; disabled when analog input enabled. CTPLS 0 0 O DIG CTMU pulse generator output. P1A 0 0 O DIG Enhanced CCP1 PWM output 1. CCP1 0 0 O DIG Compare 1 output/PWM 1 output. 1 0 I ST Capture 1 input. IOCC2 1 — I TTL Interrupt-on-change pin. AN14 1 1 I AN Analog input 14. D-/IOCC4 D- — — I XCVR USB bus differential minus line input. — — O XCVR USB bus differential minus line output. IOCC4 — — I ST Interrupt-on-change pin. D+/IOCC5 D+ — — I XCVR USB bus differential minus line input. — — O XCVR USB bus differential minus line output. IOCC5 — — I ST Interrupt-on-change pin. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C. Note 1: Default pin assignment for T3CKI and CCP2 when Configuration bits T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO when Configuration bit SDOMX is clear. 3: Function is on PORTD/PORTE for PIC18(L)F45K50 devices. DS30000684B-page 138  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 11-8: PORTC I/O SUMMARY (CONTINUED) TRIS ANSEL Pin Buffer Pin Name Function Description Setting setting Type Type RC6/IOCC6/TX/CK/ RC6 0 0 O DIG LATC<6> data output; not affected by analog input. AN18 1 0 I ST PORTC<6> data input; disabled when analog input enabled. IOCC6 1 0 I TTL Interrupt-on-change pin. TX 1 0 O DIG EUSART asynchronous transmit data output. CK 1 0 O DIG EUSART synchronous serial clock output. 1 0 I ST EUSART synchronous serial clock input. AN18 1 1 I AN Analog input 18. RC7/IOCC7/SDO/RX/ RC7 0 0 O DIG LATC<7> data output; not affected by analog input. DT/AN19 1 0 I ST PORTC<7> data input; disabled when analog input enabled. IOCC7 1 0 I TTL Interrupt-on-change pin. SDO(2) 1 0 O DIG Alternate MSSP SPI data output. RX 1 0 I ST EUSART asynchronous receive data in. DT 1 0 O DIG EUSART synchronous serial data output. 1 0 I ST EUSART synchronous serial data input. AN19 1 1 I AN Analog input 19. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C. Note 1: Default pin assignment for T3CKI and CCP2 when Configuration bits T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO when Configuration bit SDOMX is clear. 3: Function is on PORTD/PORTE for PIC18(L)F45K50 devices.  2012-2014 Microchip Technology Inc. DS30000684B-page 139

PIC18(L)F2X/45K50 TABLE 11-9: REGISTERS ASSOCIATED WITH PORTC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page ANSELC ANSC7 ANSC6 — — — ANSC2 — — 148 ECCP1AS ECCP1ASE ECCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 201 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 197 CCP2CON — — DC2B<1:0> CCP2M<3:0> 197 CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 322 LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 150 PORTC RC7 RC6 — — — RC2 RC1 RC0 146 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 269 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 152 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 252 T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC RD16 TMR1ON 165 T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC RD16 TMR3ON 165 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS 166 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC. Note 1: Available on PIC18(L)F45K50 devices only. TABLE 11-10: CONFIGURATION REGISTERS ASSOCIATED WITH PORTC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC. DS30000684B-page 140  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 11.5 PORTD Registers 11.5.1 PORTD OUTPUT PRIORITY Each PORTD pin is multiplexed with other functions. Note: PORTD is only available on 40-pin and The pins, their combined functions and their output 44-pin devices. priorities are briefly described here. For additional PORTD is an 8-bit wide, bidirectional port. The information, refer to the appropriate section in this data corresponding data direction register is TRISD. Setting sheet. a TRISD bit (= 1) will make the corresponding PORTD When multiple outputs are enabled, the actual pin pin an input (i.e., disable the output driver). Clearing a control goes to the peripheral with the higher priority. TRISD bit (= 0) will make the corresponding PORTD Table11-4 lists the PORTD pin functions from the pin an output (i.e., enable the output driver and put the highest to the lowest priority. contents of the output latch on the selected pin). Analog input functions, such as ADC, comparator and The Data Latch register (LATD) is also memory SR latch inputs, are not shown in the priority lists. mapped. Read-modify-write operations on the LATD These inputs are active when the I/O pin is set for register read and write the latched output value for Analog mode using the ANSELx registers. Digital PORTD. output functions may control the pin when it is in Analog All pins on PORTD are implemented with Schmitt mode with the priority shown below. Trigger input buffers. Each pin is individually configurable as an input or output. All of the PORTD pins are multiplexed with analog and digital peripheral modules. See Table11-11. Note: On a Power-on Reset, these pins are configured as analog inputs. EXAMPLE 11-4: INITIALIZING PORTD MOVLB 0xF ; Set BSR for banked SFRs CLRF LATD ; Initialize PORTD by ; clearing output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs MOVLW 30h ; Value used to ; enable digital inputs MOVWF ANSELD ; RD<3:0> dig input enable ; RC<7:6> dig input enable  2012-2014 Microchip Technology Inc. DS30000684B-page 141

PIC18(L)F2X/45K50 TABLE 11-11: PORTD I/O SUMMARY TRIS ANSEL Pin Buffer Pin Name Function Description Setting setting Type Type RD0/AN20 RD0 0 0 O DIG LATD<0> data output; not affected by analog input. 1 0 I ST PORTD<0> data input; disabled when analog input enabled. AN20 1 1 I AN Analog input 20. RD1/AN21 RD1 0 0 O DIG LATD<1> data output; not affected by analog input. 1 0 I ST PORTD<1> data input; disabled when analog input enabled. AN21 1 1 I AN Analog input 21. RD2/AN22 RD2 0 0 O DIG LATD<2> data output; not affected by analog input. 1 0 I ST PORTD<2> data input; disabled when analog input enabled. AN22 1 1 I AN Analog input 22. RD3/AN23 RD3 0 0 O DIG LATD<3> data output; not affected by analog input. 1 0 I ST PORTD<3> data input; disabled when analog input enabled. AN23 1 1 I AN Analog input 23. RD4/AN24 RD4 0 0 O DIG LATD<4> data output; not affected by analog input. 1 0 I ST PORTD<4> data input; disabled when analog input enabled. AN24 1 1 I AN Analog input 24. RD5/P1B/AN25 RD5 0 0 O DIG LATD<5> data output; not affected by analog input. 1 0 I ST PORTD<5> data input; disabled when analog input enabled. P1B 0 0 O DIG Enhanced CCP1 PWM output 2. AN25 1 1 I AN Analog input 25. RD6/P1C/AN26 RD6 0 0 O DIG LATD<6> data output; not affected by analog input. 1 0 I ST PORTD<6> data input; disabled when analog input enabled. P1C 0 0 O DIG Enhanced CCP1 PWM output 3. AN26 1 1 I AN Analog input 26. RD7/P1D/AN27 RD7 0 0 O DIG LATD<7> data output; not affected by analog input. 1 0 I ST PORTD<7> data input; disabled when analog input enabled. P1D 0 0 O DIG Enhanced CCP1 PWM output 4. AN27 1 1 I AN Analog input 27. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C. DS30000684B-page 142  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 11-12: REGISTERS ASSOCIATED WITH PORTD Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 page ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 148 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 197 LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 150 PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 146 SLRCON(1) — — — SLRE SLRD SLRC SLRB SLRA 152 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 252 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 149 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD. Note 1: Available on PIC18(L)F45K50 devices only.  2012-2014 Microchip Technology Inc. DS30000684B-page 143

PIC18(L)F2X/45K50 11.6 PORTE Registers 11.6.2 PORTE ON 28-PIN DEVICES Depending on the particular PIC18(L)F2X/45K50 For PIC18(L)F2XK50 devices, PORTE is only available when Master Clear functionality is disabled device selected, PORTE is implemented in two (MCLR=0). In these cases, PORTE is a single bit, different ways. input-only port comprised of RE3 only. The pin oper- 11.6.1 PORTE ON 40/44-PIN DEVICES ates as previously described. For PIC18(L)F2X/45K50 devices, PORTE is a 4-bit 11.6.3 RE3 WEAK PULL-UP wide port. Three pins (RE0/AN5, RE1/AN6 and RE2/ The port RE3 pin has an individually controlled weak AN7) are individually configurable as inputs or outputs. internal pull-up. When set, the WPUE3 (TRISE<7>) bit These pins have Schmitt Trigger input buffers. When enables the RE3 pin pull-up. The RBPU bit of the INT- selected as an analog input, these pins will read as ‘0’s. CON2 register controls pull-ups on both PORTB and The corresponding data direction register is TRISE. PORTE. When RBPU = 0, the weak pull-ups become Setting a TRISE bit (= 1) will make the corresponding active on all pins which have the WPUE3 or WPUBx PORTE pin an input (i.e., disable the output driver). bits set. When set, the RBPU bit disables all weak pull- Clearing a TRISE bit (= 0) will make the corresponding ups. The pull-ups are disabled on a Power-on Reset. PORTE pin an output (i.e., enable the output driver and When the RE3 port pin is configured as MCLR, (CON- put the contents of the output latch on the selected pin). FIG3H<7>, MCLRE = 1 and CONFIG4L<2>, LVP = 0), TRISE controls the direction of the REx pins, even or configured for Low-Voltage Programming, (MCLRE when they are being used as analog inputs. The user = x and LVP = 1), the pull-up is always enabled and the must make sure to keep the pins configured as inputs WPUE3 bit has no effect. when using them as analog inputs. 11.6.4 PORTE OUTPUT PRIORITY The Data Latch register (LATE) is also memory Each PORTE pin is multiplexed with other functions. mapped. Read-modify-write operations on the LATE The pins, their combined functions and their output register read and write the latched output value for priorities are briefly described here. For additional PORTE. information, refer to the appropriate section in this data Note: On a Power-on Reset, RE<2:0> are sheet. configured as analog inputs. When multiple outputs are enabled, the actual pin The fourth pin of PORTE (MCLR/VPP/RE3) is an input- control goes to the peripheral with the higher priority. only pin. Its operation is controlled by the MCLRE Table11-4 lists the PORTE pin functions from the Configuration bit. When selected as a port pin highest to the lowest priority. (MCLRE=0), it functions as a digital input-only pin; as Analog input functions, such as ADC, comparator and such, it does not have TRIS or LAT bits associated with its SR latch inputs, are not shown in the priority lists. operation. Otherwise, it functions as the device’s Master These inputs are active when the I/O pin is set for Clear input. In either configuration, RE3 also functions as Analog mode using the ANSELx registers. Digital the programming voltage input during programming. output functions may control the pin when it is in Analog Note: On a Power-on Reset, RE3 is enabled as mode with the priority shown below. a digital input-only if Master Clear functionality is disabled. EXAMPLE 11-5: INITIALIZING PORTE CLRF LATE ; Initialize PORTE by ; clearing output ; data latches CLRF ANSELE ; Configure analog pins ; for digital only MOVLW 05h ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<0> as input ; RE<1> as output ; RE<2> as input DS30000684B-page 144  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 11-13: PORTE I/O SUMMARY TRIS ANSEL Pin Buffer Pin Function Description Setting Setting Type Type RE0/AN5 RE0 0 0 O DIG LATE<0> data output; not affected by analog input. 1 0 I ST PORTE<0> data input; disabled when analog input enabled. AN5 1 1 I AN Analog input 5. RE1/AN6 RE1 0 0 O DIG LATE<1> data output; not affected by analog input. 1 0 I ST PORTE<1> data input; disabled when analog input enabled. AN6 1 1 I AN Analog input 6. RE2/AN7 RE2 0 0 O DIG LATE<2> data output; not affected by analog input. 1 0 I ST PORTE<2> data input; disabled when analog input enabled. AN7 1 1 I AN Analog input 7. RE3/VPP/MCLR RE3 — — I ST PORTE<3> data input; enabled when Configuration bit MCLRE = 0. VPP — — P AN Programming voltage input; always available MCLR — — I ST Active-low Master Clear (device Reset) input; enabled when configuration bit MCLRE = 1. Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C. TABLE 11-14: REGISTERS ASSOCIATED WITH PORTE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 149 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP 115 LATE(1) — — — — — LATE2 LATE1 LATE0 150 PORTE — — — — RE3 RE2(1) RE1(1) RE0(1) 147 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 152 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 149 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTE. Note 1: Available on PIC18(L)F45K50 devices only. TABLE 11-15: CONFIGURATION REGISTERS ASSOCIATED WITH PORTE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 CONFIG4L DEBUG XINST — — — LVP(1) — STRVEN 377 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for interrupts. Note 1: Can only be changed when in high-voltage programming mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 145

PIC18(L)F2X/45K50 11.7 Port Analog Control 11.8 Port Slew Rate Control Most port pins are multiplexed with analog functions The output slew rate of each port is programmable to such as the Analog-to-Digital Converter and select either the standard transition rate or a reduced comparators. When these I/O pins are to be used as transition rate of approximately 0.1 times the standard analog inputs it is necessary to disable the digital input to minimize EMI. The reduced transition time is the buffer to avoid excessive current caused by improper default slew rate for all ports. biasing of the digital input. Individual control of the digital input buffers on pins which share analog functions is provided by the ANSELA, ANSELB, ANSELC, ANSELD and ANSELE registers. Setting an ANSx bit high will disable the associated digital input buffer and cause all reads of that pin to return ‘0’ while allowing analog functions of that pin to operate correctly. The state of the ANSx bits has no affect on digital output functions. A pin with the associated TRISx bit clear and ANSx bit set will still operate as a digital output but the input mode will be analog. This can cause unexpected behavior when performing read- modify-write operations on the affected port. All ANSEL register bits default to ‘1’ upon POR and BOR, disabling digital inputs for their associated port pins. All TRIS register bits default to ‘1’ upon POR or BOR, disabling digital outputs for their associated port pins. As a result, all port pins that have an ANSEL register will default to analog inputs upon POR or BOR. 11.9 Register Definitions – Port Control REGISTER 11-1: PORTx(1): PORTx REGISTER R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 Rx<7:0>: PORTx I/O bit values(2) Note 1: Register Description for PORTA, PORTB, PORTC and PORTD. 2: Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O pin values. DS30000684B-page 146  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 11-2: PORTE: PORTE REGISTER U-0 U-0 U-0 U-0 R/W-u/x R/W-u/x R/W-u/x R/W-u/x — — — — RE3(1) RE2(2), (3) RE1(2), (3) RE0(2), (3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 Unimplemented: Read as ‘0’ bit 3 RE3: PORTE Input bit value(1) bit 2-0 RE<2:0>: PORTE I/O bit values(2), (3) Note 1: Port is available as input-only when MCLRE = 0. 2: Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O pin values. 3: Available on PIC18(L)F45K50 devices. REGISTER 11-3: ANSELA – PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 ANSA5: RA5 Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled bit 4 Unimplemented: Read as ‘0’ bit 3-0 ANSA<3:0>: RA<3:0> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled  2012-2014 Microchip Technology Inc. DS30000684B-page 147

PIC18(L)F2X/45K50 REGISTER 11-4: ANSELB – PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: RB<5:0> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled REGISTER 11-5: ANSELC – PORTC ANALOG SELECT REGISTER R/W-1 R/W-1 U-0 U-0 U-0 R/W-1 U-0 U-0 ANSC7 ANSC6 — — — ANSC2 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ANSC<7:6>: RC<7:6> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled bit 5-3 Unimplemented: Read as ‘0’ bit 2 ANSC<2>: RC<2> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled bit 1-0 Unimplemented: Read as ‘0’ REGISTER 11-6: ANSELD – PORTD ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ANSD<7:0>: RD<7:0> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled DS30000684B-page 148  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 11-7: ANSELE – PORTE ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 — — — — — ANSE2(1) ANSE1(1) ANSE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSE<2:0>: RE<2:0> Analog Select bit(1) 1 = Digital input buffer disabled 0 = Digital input buffer enabled Note 1: Available on PIC18(L)F45K50 devices only. REGISTER 11-8: TRISx: PORTx TRI-STATE REGISTER(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISx7 TRISx6 TRISx5 TRISx4 TRISx3 TRISx2 TRISx1 TRISx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TRISx<7:0>: PORTx Tri-State Control bit 1 = PORTx pin configured as an input (tri-stated) 0 = PORTx pin configured as an output Note 1: Register description for TRISA, TRISB, TRISC and TRISD. REGISTER 11-9: TRISE: PORTE TRI-STATE REGISTER R/W-1 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WPUE3: Weak Pull-up Register bits 1 = Pull-up enabled on PORT pin 0 = Pull-up disabled on PORT pin bit 6-3 Unimplemented: Read as ‘0’ bit 2-0 TRISE<2:0>: PORTE Tri-State Control bit(1) 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output Note 1: Available on PIC18(L)F45K50 devices only.  2012-2014 Microchip Technology Inc. DS30000684B-page 149

PIC18(L)F2X/45K50 REGISTER 11-10: LATx: PORTx OUTPUT LATCH REGISTER(1) R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATx7 LATx6 LATx5 LATx4 LATx3 LATx2 LATx1 LATx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 LATx<7:0>: PORTx Output Latch bit value(2) Note 1: Register Description for LATA, LATB, LATC and LATD. 2: Writes to PORTA are written to corresponding LATA register. Reads from PORTA register is return of I/O pin values. REGISTER 11-11: LATE: PORTE OUTPUT LATCH REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u — — — — — LATE2 LATE1 LATE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LATE<2:0>: PORTE Output Latch bit value(2) Note 1: Available on PIC18(L)F45K50 devices only. 2: Writes to PORTE are written to corresponding LATE register. Reads from PORTE register is return of I/O pin values. REGISTER 11-12: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled on PORTB pin 0 = Pull-up disabled on PORTB pin DS30000684B-page 150  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 11-13: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IOCB7 IOCB6 IOCB5 IOCB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTB control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: Interrupt-on-change requires that the IOCIE bit (INTCON<3>) is set. REGISTER 11-14: IOCC: INTERRUPT-ON-CHANGE PORTC CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 IOCC7 IOCC6 IOCC5 IOCC4 — IOCC2 IOCC1 IOCC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 IOCC<7:4>: Interrupt-on-Change PORTC control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 IOCC<2:0>: Interrupt-on-Change PORTC control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled Note 1: Interrupt-on-change requires that the IOCIE bit (INTCON<3>) is set.  2012-2014 Microchip Technology Inc. DS30000684B-page 151

PIC18(L)F2X/45K50 REGISTER 11-15: SLRCON: SLEW RATE CONTROL REGISTER U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SLRE(1) SLRD(1) SLRC SLRB SLRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 SLRE: PORTE Slew Rate Control bit(1) 1 = All outputs on PORTE slew at a limited rate 0 = All outputs on PORTE slew at the standard rate bit 3 SLRD: PORTD Slew Rate Control bit(1) 1 = All outputs on PORTD slew at a limited rate 0 = All outputs on PORTD slew at the standard rate bit 2 SLRC: PORTC Slew Rate Control bit 1 = All outputs on PORTC slew at a limited rate 0 = All outputs on PORTC slew at the standard rate bit 1 SLRB: PORTB Slew Rate Control bit 1 = All outputs on PORTB slew at a limited rate 0 = All outputs on PORTB slew at the standard rate bit 0 SLRA: PORTA Slew Rate Control bit 1 = All outputs on PORTA slew at a limited rate(2) 0 = All outputs on PORTA slew at the standard rate Note 1: These bits are available on PIC18(L)F45K50 devices. 2: The slew rate of RA6 defaults to standard rate when the pin is used as CLKO. DS30000684B-page 152  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 12.0 TIMER0 MODULE The T0CON register (Register12-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or A simplified block diagram of the Timer0 module in 8-bit counter in both 8-bit or 16-bit modes mode is shown in Figure12-1. Figure12-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow 12.1 Register Definitions: Timer0 Control REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA TOPS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value  2012-2014 Microchip Technology Inc. DS30000684B-page 153

PIC18(L)F2X/45K50 12.2 Timer0 Operation 12.3 Timer0 Reads and Writes in 16-Bit Mode Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit of the T0CON TMR0H is not the actual high byte of Timer0 in 16-bit register. In Timer mode (T0CS = 0), the module mode; it is actually a buffered version of the real high increments on every clock by default unless a different byte of Timer0 which is neither directly readable nor prescaler value is selected (see Section12.4 writable (refer to Figure12-2). TMR0H is updated with “Prescaler”). Timer0 incrementing is inhibited for two the contents of the high byte of Timer0 during a read of instruction cycles following a TMR0 register write. The TMR0L. This provides the ability to read all 16 bits of user can work around this by adjusting the value written Timer0 without the need to verify that the read of the to the TMR0 register to compensate for the anticipated high and low byte were valid. Invalid reads could missing increments. otherwise occur due to a rollover between successive The Counter mode is selected by setting the T0CS bit reads of the high and low byte. (= 1). In this mode, Timer0 increments either on every Similarly, a write to the high byte of Timer0 must also rising or falling edge of pin RA4/T0CKI. The increment- take place through the TMR0H Buffer register. Writing ing edge is determined by the Timer0 Source Edge to TMR0H does not directly affect Timer0. Instead, the Select bit, T0SE of the T0CON register; clearing this bit high byte of Timer0 is updated with the contents of selects the rising edge. Restrictions on the external TMR0H when a write occurs to TMR0L. This allows all clock input are discussed below. 16 bits of Timer0 to be updated at once. An external clock source can be used to drive Timer0; however, it must meet certain requirements (see Table29-22) to ensure that the external clock can be synchronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) 8 T0CS 3 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS30000684B-page 154  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 1 SIynntecr nwaitlh TMR0L HTigMh RB0yte STMetR 0IF T0CKI pin ProPgrreasmcamlearble 0 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 12.4 Prescaler 12.4.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software its value is set by the PSA and T0PS<2:0> bits of the control and can be changed “on-the-fly” during program T0CON register which determine the prescaler execution. assignment and prescale ratio. 12.5 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When the prescaler is assigned, The TMR0 interrupt is generated when the TMR0 reg- prescale values from 1:2 through 1:256 in integer ister overflows from FFh to 00h in 8-bit mode, or from power-of-2 increments are selectable. FFFFh to 0000h in 16-bit mode. This overflow sets the When assigned to the Timer0 module, all instructions TMR0IF flag bit. The interrupt can be masked by clear- writing to the TMR0 register (e.g., CLRF TMR0, MOVWF ing the TMR0IE bit of the INTCON register. Before TMR0, BSF TMR0, etc.) clear the prescaler count. re-enabling the interrupt, the TMR0IF bit must be cleared by software in the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP 115 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS<2:0> 153 TMR0H Timer0 Register, High Byte — TMR0L Timer0 Register, Low Byte — TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Timer0.  2012-2014 Microchip Technology Inc. DS30000684B-page 155

PIC18(L)F2X/45K50 13.0 TIMER1/3 MODULE WITH GATE • Special Event Trigger (with CCP/ECCP) CONTROL • Selectable Gate Source Polarity • Gate Toggle mode The Timer1/3 module is a 16-bit timer/counter with the • Gate Single-pulse mode following features: • Gate Value Status • 16-bit timer/counter register pair (TMRxH:TMRxL) • Gate Event Interrupt • Programmable internal or external clock source Figure13-1 is a block diagram of the Timer1/3 module. • 2-bit prescaler • Dedicated Secondary 32 kHz oscillator circuit • Optionally synchronized comparator out • Multiple Timer1/3 gate (count enable) sources • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • 16-Bit Read/Write Operation • Time base for the Capture/Compare function FIGURE 13-1: TIMER1/3 BLOCK DIAGRAM TxGSS<1:0> TxG 00 TxGSPM TimPRer22 Match 01 TxG_IN 0 0 TxGVAL D Q Data Bus sync_C1OUT(7) 10 SAicnqg.l eC Ponutlrsoel 1 Q1 EN TXGRCDON D Q 1 sync_C2OUT(7) 11 CK Q TxGGO/DONE Interrupt Set TMRxON R det TMRxGIF TxGPOL TxGTM TMRxGE Set flag bit TMRxON TMRxIF on To Comparator Module Overflow TMRx(2),(4) EN Synchronized TMRxH TMRxL TxCLK 0 clock input Q D 1 Secondary TMRxCS<1:0> TxSYNC Oscillator SOSCOUT Module See Figure 2-4 Reserved 11 Prescaler Synchronize(3),(7) 1 1, 2, 4, 8 TxCLK_EXT_SRC det (5),(6) (1) 10 2 TxCKI 0 FOSC TxCKPS<1:0> Internal 01 SOSCEN Clock IFnOteSrCn/a2l Sleep input FOSC/4 Clock Internal 00 Clock Note 1: ST Buffer is high speed type when using TxCKI. 2: Timer1/3 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 4: See Figure13-2 for 16-Bit Read/Write Mode Block Diagram. 5: T1CKI is not available when the secondary oscillator is enabled. (SOSCGO = 1 or SOSCEN = 1) 6: T3CKI is not available when the secondary oscillator is enabled, unless T3CMX = 1. 7: Synchronized comparator output should not be used in conjunction with synchronized TxCKI. DS30000684B-page 156  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 13.1 Timer1/3 Operation 13.2.1 INTERNAL CLOCK SOURCE The Timer1/3 module is a 16-bit incrementing counter When the internal clock source is selected the which is accessed through the TMRxH:TMRxL register TMRxH:TMRxL register pair will increment on multiples pair. Writes to TMRxH or TMRxL directly update the of FOSC as determined by the Timer1/3 prescaler. counter. When the FOSC internal clock source is selected, the Timer1/3 register value will increment by four counts When used with an internal clock source, the module is every instruction clock cycle. Due to this condition, a a timer and increments on every instruction cycle. 2LSB error in resolution will occur when reading the When used with an external clock source, the module Timer1/3 value. To utilize the full resolution of Timer1/3, can be used as either a timer or counter and an asynchronous input signal must be used to gate the increments on every selected edge of the external Timer1/3 clock input. source. The following asynchronous sources may be used: Timer1/3 is enabled by configuring the TMRxON and TMRxGE bits in the TxCON and TxGCON registers, • Asynchronous event on the TxG pin to Timer1/3 respectively. Table13-1 displays the Timer1/3 enable gate selections. • C1 or C2 comparator input to Timer1/3 gate 13.2.2 EXTERNAL CLOCK SOURCE TABLE 13-1: TIMER1/3 ENABLE SELECTIONS When the external clock source is selected, the Timer1/3 module may work as a timer or a counter. Timer1/3 TMRxON TMRxGE Operation When enabled to count, Timer1/3 is incremented on the rising edge of the external clock input of the TxCKI pin. 0 0 Off This external clock source can be synchronized to the 0 1 Off microcontroller system clock or it can run 1 0 Always On asynchronously. 1 1 Count Enabled When used as a timer with a clock oscillator, an external 32.768kHz crystal can be used in conjunction with the dedicated secondary internal oscillator circuit. 13.2 Clock Source Selection Note: In Counter mode, a falling edge must be The TMRxCS<1:0> and SOSCEN bits of the TxCON registered by the counter prior to the first register are used to select the clock source for Timer1/3. incrementing rising edge after any one or The dedicated secondary oscillator circuit can be used more of the following conditions: as the clock source for Timer1 and Timer3, simultaneously. Any of the SOSCEN bits will enable the • Timer1/3 enabled after POR secondary oscillator circuit and select it as the clock • Write to TMRxH or TMRxL source for that particular timer. Table13-2 displays the • Timer1/3 is disabled clock source selections. • Timer1/3 is disabled (TMRxON = 0) when TxCKI is high then Timer1/3 is enabled (TMRxON=1) when TxCKI is low. TABLE 13-2: CLOCK SOURCE SELECTIONS TMRxCS1 TMRxCS0 SOSCEN Clock Source 0 1 x System Clock (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 0 0 External Clocking on TxCKI Pin 1 0 1 Oscillator Circuit on SOSCI/SOSCO Pins  2012-2014 Microchip Technology Inc. DS30000684B-page 157

PIC18(L)F2X/45K50 13.3 Timer1/3 Prescaler 13.5.1 READING AND WRITING TIMER1/3 IN ASYNCHRONOUS COUNTER Timer1/3 has four prescaler options allowing 1, 2, 4 or 8 MODE divisions of the clock input. The TxCKPS bits of the TxCON register control the prescale counter. The Reading TMRxH or TMRxL while the timer is running prescale counter is not directly readable or writable; from an external asynchronous clock will ensure a valid however, the prescaler counter is cleared upon a write to read (taken care of in hardware). However, the user TMRxH or TMRxL. should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the 13.4 Secondary Oscillator timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and A dedicated secondary low-power 32.768kHz write the desired values. A write contention may occur oscillator circuit is built-in between pins SOSCI (input) by writing to the timer registers, while the register is and SOSCO (amplifier output). This internal circuit is to incrementing. This may produce an unpredictable be used in conjunction with an external 32.768kHz value in the TMRxH:TMRxL register pair. crystal. The oscillator circuit is enabled by setting the SOSCEN 13.6 Timer1/3 16-Bit Read/Write Mode bit of the TxCON register, the SOSCGO bit of the Timer1/3 can be configured to read and write all 16 bits OSCCON2 register or by selecting the secondary of data, to and from, the 8-bit TMRxL and TMRxH reg- oscillator as the system clock by setting SCS<1:0> = isters, simultaneously. The 16-bit read and write opera- 01 in the OSCCON register. The oscillator will continue tions are enabled by setting the RD16 bit of the TxCON to run during Sleep. register. Note: The oscillator requires a start-up and To accomplish this function, the TMRxH register value stabilization time before use. Thus, is mapped to a buffer register called the TMRxH buffer SOSCEN should be set and a suitable register. While in 16-Bit mode, the TMRxH register is delay observed prior to enabling Timer1/3. not directly readable or writable and all read and write operations take place through the use of this TMRxH 13.5 Timer1/3 Operation in buffer register. Asynchronous Counter Mode When a read from the TMRxL register is requested, the value of the TMRxH register is simultaneously loaded If control bit TxSYNC of the TxCON register is set, the into the TMRxH buffer register. When a read from the external clock input is not synchronized. The timer TMRxH register is requested, the value is provided increments asynchronously to the internal phase from the TMRxH buffer register instead. This provides clocks. If external clock source is selected then the the user with the ability to accurately read all 16 bits of timer will continue to run during Sleep and can the Timer1/3 value from a single instance in time. generate an interrupt on overflow, which will wake-up the processor. However, special precautions in In contrast, when not in 16-Bit mode, the user must software are needed to read/write the timer (see read each register separately and determine if the Section13.5.1 “Reading and Writing Timer1/3 in values have become invalid due to a rollover that may Asynchronous Counter Mode”). have occurred between the read operations. When a write request of the TMRxL register is Note: When switching from synchronous to requested, the TMRxH buffer register is simultaneously asynchronous operation, it is possible to updated with the contents of the TMRxH register. The skip an increment. When switching from value of TMRxH must be preloaded into the TMRxH asynchronous to synchronous operation, buffer register prior to the write request for the TMRxL it is possible to produce an additional register. This provides the user with the ability to write increment. all 16 bits to the TMRxL:TMRxH register pair at the same time. Any requests to write to the TMRxH directly does not clear the Timer1/3 prescaler value. The prescaler value is only cleared through write requests to the TMRxL register. DS30000684B-page 158  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 13-2: TIMER1/3 16-BIT 13.7.2 TIMER1/3 GATE SOURCE READ/WRITE MODE SELECTION BLOCK DIAGRAM The Timer1/3 gate source can be selected from one of four different sources. Source selection is controlled by From the TxGSS bits of the TxGCON register. The polarity Timer1/3 Circuitry for each available source is also selectable. Polarity TMR1 Set selection is controlled by the TxGPOL bit of the TMR1L High Byte TMR1IF TxGCON register. on Overflow 8 TABLE 13-4: TIMER1/3 GATE SOURCES Read TMR1L Write TMR1L TxGSS Timer1/3 Gate Source 8 8 00 Timer1/3 Gate Pin (TxG) TMR1H 01 Timer2 Match to PR2 (TMR2 increments to match PR2) 8 8 10 Comparator 1 Output sync_C1OUT Internal Data Bus (optionally Timer1/3 synchronized output) 11 Comparator 2 Output sync_C2OUT (optionally Timer1/3 synchronized output) 13.7 Timer1/3 Gate 13.7.2.1 TxG Pin Gate Operation Timer1/3 can be configured to count freely or the count The TxG pin is one source for Timer1/3 gate control. It can be enabled and disabled using Timer1/3 gate can be used to supply an external source to the Tim- circuitry. This is also referred to as Timer1/3 Gate er1/3 gate circuitry. Enable. Timer1/3 gate can also be driven by multiple selectable 13.7.2.2 Timer2 Match Gate Operation sources. The TMR2 register will increment until it matches the value in the PR2 register. On the very next increment 13.7.1 TIMER1/3 GATE ENABLE cycle, TMR2 will be reset to 00h. When this Reset The Timer1/3 Gate Enable mode is enabled by setting occurs, a low-to-high pulse will automatically be gener- the TMRxGE bit of the TxGCON register. The polarity ated and internally supplied to the Timer1/3 gate of the Timer1/3 Gate Enable mode is configured using circuitry. See Section13.7.2 “Timer1/3 Gate Source the TxGPOL bit of the TxGCON register. Selection” for more information. When Timer1/3 Gate Enable mode is enabled, 13.7.2.3 Comparator C1 Gate Operation Timer1/3 will increment on the rising edge of the Timer1/3 clock source. When Timer1/3 Gate Enable The output resulting from a Comparator 1 operation can mode is disabled, no incrementing will occur and be selected as a source for Timer1/3 gate control. The Timer1/3 will hold the current count. See Figure13-4 Comparator 1 output (sync_C1OUT) can be for timing details. synchronized to the Timer1/3 clock or left asynchronous. For more information see Section19.8.3 “Synchronizing Comparator Output to Timer1”. TABLE 13-3: TIMER1/3 GATE ENABLE SELECTIONS 13.7.2.4 Comparator C2 Gate Operation Timer1/3 The output resulting from a Comparator 2 operation TxCLK TxGPOL TxG Operation can be selected as a source for Timer1/3 gate control. The Comparator 2 output (sync_C2OUT) can be  0 0 Counts synchronized to the Timer1/3 clock or left  0 1 Holds Count asynchronous. For more information see  1 0 Holds Count Section19.8.3 “Synchronizing Comparator Output  1 1 Counts to Timer1”.  2012-2014 Microchip Technology Inc. DS30000684B-page 159

PIC18(L)F2X/45K50 13.7.3 TIMER1/3 GATE TOGGLE MODE 13.7.4 TIMER1/3 GATE SINGLE-PULSE MODE When Timer1/3 Gate Toggle mode is enabled, it is pos- sible to measure the full-cycle length of a Timer1/3 gate When Timer1/3 Gate Single-Pulse mode is enabled, it signal, as opposed to the duration of a single level is possible to capture a single-pulse gate event. pulse. Timer1/3 Gate Single-Pulse mode is first enabled by The Timer1/3 gate source is routed through a flip-flop setting the TxGSPM bit in the TxGCON register. Next, the TxGGO/DONE bit in the TxGCON register must be that changes state on every incrementing edge of the set. The Timer1/3 will be fully enabled on the next signal. See Figure13-5 for timing details. incrementing edge. On the next trailing edge of the Timer1/3 Gate Toggle mode is enabled by setting the pulse, the TxGGO/DONE bit will automatically be TxGTM bit of the TxGCON register. When the TxGTM cleared. No other gate events will be allowed to bit is cleared, the flip-flop is cleared and held clear. This increment Timer1/3 until the TxGGO/DONE bit is once is necessary in order to control which edge is again set in software. measured. Clearing the TxGSPM bit of the TxGCON register will Note: Enabling Toggle mode at the same time also clear the TxGGO/DONE bit. See Figure13-6 for as changing the gate polarity may result in timing details. indeterminate operation. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1/3 gate source to be measured. See Figure13-7 for timing details. 13.7.5 TIMER1/3 GATE VALUE STATUS When Timer1/3 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the TxGVAL bit in the TxGCON register. The TxGVAL bit is valid even when the Timer1/3 gate is not enabled (TMRxGE bit is cleared). 13.7.6 TIMER1/3 GATE EVENT INTERRUPT When Timer1/3 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of TxGVAL occurs, the TMRxGIF flag bit in the PIR3 register will be set. If the TMRxGIE bit in the PIE3 register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Tim- er1/3 gate is not enabled (TMRxGE bit is cleared). For more information on selecting high or low priority status for the Timer1/3 Gate Event Interrupt see Section10.0 “Interrupts”. DS30000684B-page 160  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 13.8 Timer1/3 Interrupt The secondary oscillator will continue to operate in Sleep regardless of the TxSYNC bit setting. The Timer1/3 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When 13.10 ECCP/CCP Capture/Compare Time Timer1/3 rolls over, the Timer1/3 interrupt flag bit of the Base PIR1/2 register is set. To enable the interrupt on rollover, you must set these bits: The CCP modules use the TMRxH:TMRxL register pair • TMRxON bit of the TxCON register as the time base when operating in Capture or Compare mode. • TMRxIE bits of the PIE1 or PIE2 registers • PEIE/GIEL bit of the INTCON register In Capture mode, the value in the TMRxH:TMRxL • GIE/GIEH bit of the INTCON register register pair is copied into the CCPRxH:CCPRxL register pair on a configured event. The interrupt is cleared by clearing the TMRxIF bit in the Interrupt Service Routine. In Compare mode, an event is triggered when the value CCPRxH:CCPRxL register pair matches the value in For more information on selecting high or low priority the TMRxH:TMRxL register pair. This event can be a status for the Timer1/3 Overflow Interrupt, see Special Event Trigger. Section10.0 “Interrupts”. For more information, see Section15.0 Note: The TMRxH:TMRxL register pair and the “Capture/Compare/PWM Modules”. TMRxIF bit should be cleared before enabling interrupts. 13.11 ECCP/CCP Special Event Trigger 13.9 Timer1/3 Operation During Sleep When any of the CCP’s are configured to trigger a special event, the trigger will clear the TMRxH:TMRxL Timer1/3 can only operate during Sleep when set up in register pair. This special event does not cause a Asynchronous Counter mode. In this mode, an external Timer1/3 interrupt. The CCP module may still be crystal or clock source can be used to increment the configured to generate a CCP interrupt. counter. To set up the timer to wake the device: In this mode of operation, the CCPRxH:CCPRxL • TMRxON bit of the TxCON register must be set register pair becomes the period register for Timer1/3. • TMRxIE bit of the PIE1/2 register must be set Timer1/3 should be synchronized and FOSC/4 should • PEIE/GIEL bit of the INTCON register must be set be selected as the clock source in order to utilize the • TxSYNC bit of the TxCON register must be set Special Event Trigger. Asynchronous operation of Tim- er1/3 can cause a Special Event Trigger to be missed. • TMRxCS bits of the TxCON register must be configured In the event that a write to TMRxH or TMRxL coincides • SOSCEN bit of the TxCON register must be with a Special Event Trigger from the CCP, the write will configured take precedence. The device will wake-up on an overflow and execute For more information, see Section18.2.8 “Special the next instruction. If the GIE/GIEH bit of the INTCON Event Trigger”. register is set, the device will call the Interrupt Service Routine. FIGURE 13-3: TIMER1/3 INCREMENTING EDGE TXCKI = 1 when TMRx Enabled TXCKI = 0 when TMRX Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2012-2014 Microchip Technology Inc. DS30000684B-page 161

PIC18(L)F2X/45K50 FIGURE 13-4: TIMER1/3 GATE ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3 N N + 1 N + 2 N + 3 N + 4 FIGURE 13-5: TIMER1/3 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxTxG_IN TxCKI TxGVAL Timer1/3 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 DS30000684B-page 162  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 13-6: TIMER1/3 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM Cleared by hardware on TxGGO/ Set by software falling edge of TxGVAL DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL Timer1/3 N N + 1 N + 2 Cleared by TMRxGIF Cleared by software Set by hardware on software falling edge of TxGVAL  2012-2014 Microchip Technology Inc. DS30000684B-page 163

PIC18(L)F2X/45K50 FIGURE 13-7: TIMER1/3 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM Cleared by hardware on TxGGO/ Set by software falling edge of TxGVAL DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL Timer1/3 N N + 1 N + 2 N + 3 N + 4 Set by hardware on Cleared by TMRxGIF Cleared by software falling edge of TxGVAL software 13.12 Peripheral Module Disable When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power con- sumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bits for Timer1 (TMR1MD) and Timer3 (TMR3MD) are in the PMD0 Register. See Section4.0 “Power-Managed Modes” for more information. DS30000684B-page 164  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 13.13 Register Definitions: Timer1/3 Control REGISTER 13-1: TxCON: TIMER1/3 CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/0 R/W-0/u TMRxCS<1:0> TxCKPS<1:0> SOSCEN TxSYNC RD16 TMRxON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMRxCS<1:0>: Timer1/3 Clock Source Select bits 11 =Reserved. Do not use. 10 =Timer1/3 clock source is pin or oscillator: If SOSCEN = 0: External clock from TxCKI pin (on the rising edge) If SOSCEN = 1: Crystal oscillator on SOSCI/SOSCO pins 01 =Timer1/3 clock source is system clock (FOSC) 00 =Timer1/3 clock source is instruction clock (FOSC/4) bit 5-4 TxCKPS<1:0>: Timer1/3 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 SOSCEN: Secondary Oscillator Enable Control bit 1 = Dedicated secondary oscillator circuit enabled 0 = Dedicated secondary oscillator circuit disabled bit 2 TxSYNC: Timer1/3 External Clock Input Synchronization Control bit TMRxCS<1:0> = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMRxCS<1:0> = 0X This bit is ignored. Timer1/3 uses the internal clock when TMRxCS<1:0> = 0X. bit 1 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1/3 in one 16-bit operation 0 = Enables register read/write of Timer1/3 in two 8-bit operation bit 0 TMRxON: Timer1/3 On bit 1 = Enables Timer1/3 0 = Stops Timer1/3 Clears Timer1/3 Gate flip-flop  2012-2014 Microchip Technology Inc. DS30000684B-page 165

PIC18(L)F2X/45K50 REGISTER 13-2: TxGCON: TIMER1/3 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u TMRxGE TxGPOL TxGTM TxGSPM TxGGO/DONE TxGVAL TxGSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMRxGE: Timer1/3 Gate Enable bit If TMRxON = 0: This bit is ignored If TMRxON = 1: 1 = Timer1/3 counting is controlled by the Timer1/3 gate function 0 = Timer1/3 counts regardless of Timer1/3 gate function bit 6 TxGPOL: Timer1/3 Gate Polarity bit 1 = Timer1/3 gate is active-high (Timer1/3 counts when gate is high) 0 = Timer1/3 gate is active-low (Timer1/3 counts when gate is low) bit 5 TxGTM: Timer1/3 Gate Toggle Mode bit 1 = Timer1/3 Gate Toggle mode is enabled 0 = Timer1/3 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1/3 gate flip-flop toggles on every rising edge. bit 4 TxGSPM: Timer1/3 Gate Single-Pulse Mode bit 1 = Timer1/3 gate Single-Pulse mode is enabled and is controlling Timer1/3 gate 0 = Timer1/3 gate Single-Pulse mode is disabled bit 3 TxGGO/DONE: Timer1/3 Gate Single-Pulse Acquisition Status bit 1 = Timer1/3 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1/3 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when TxGSPM is cleared. bit 2 TxGVAL: Timer1/3 Gate Current State bit Indicates the current state of the Timer1/3 gate that could be provided to TMRxH:TMRxL. Unaffected by Timer1/3 Gate Enable (TMRxGE). bit 1-0 TxGSS<1:0>: Timer1/3 Gate Source Select bits 00 = Timer1/3 Gate pin 01 = Timer2 Match PR2 output 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 11 = Comparator 2 optionally synchronized output (sync_C2OUT) DS30000684B-page 166  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 13-5: REGISTERS ASSOCIATED WITH TIMER1/3 AS A TIMER/COUNTER Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 IPR3 — — — — CTMUIP USBIP TMR3GIP TMR1GIP 125 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIE3 — — — — CTMUIE USBIE TMR3GIE TMR1GIE 122 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PIR3 — — — — CTMUIF USBIF TMR3GIF TMR1GIF 119 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC RD16 TMR1ON 165 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 166 T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC RD16 TMR3ON 165 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 166 TMRxH Timer1/3 Register, High Byte — TMRxL Timer1/3 Register, Low Byte — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 TABLE 13-6: CONFIGURATION REGISTERS ASSOCIATED WITH TIMER1/3 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376  2012-2014 Microchip Technology Inc. DS30000684B-page 167

PIC18(L)F2X/45K50 14.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP module See Figure14-1 for a block diagram of Timer2. FIGURE 14-1: TIMER2 BLOCK DIAGRAM Sets Flag TMRx bit TMRxIF Output Prescaler Reset FOSC/4 TMRx 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 TxCKPS<1:0> PRx 4 TxOUTPS<3:0> DS30000684B-page 168  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 14.1 Timer2 Operation 14.2 Timer2 Interrupt The clock input to the Timer2 module is the system Timer2 can also generate an optional device interrupt. instruction clock (FOSC/4). The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This TMR2 increments from 00h on each clock edge. counter generates the TMR2 match interrupt flag which A 4-bit counter/prescaler on the clock input allows direct is latched in TMR2IF of the PIR1 register. The interrupt input, divide-by-4 and divide-by-16 prescale options. is enabled by setting the TMR2 Match Interrupt Enable These options are selected by the prescaler control bits, bit, TMR2IE of the PIE1 register. Interrupt Priority is T2CKPS<1:0> of the T2CON register. The value of selected with the TMR2IP bit in the IPR1 register. TMR2 is compared to that of the Period register, PR2, on A range of 16 postscale options (from 1:1 through 1:16 each clock cycle. When the two values match, the inclusive) can be selected with the postscaler control comparator generates a match signal as the timer bits, T2OUTPS<3:0>, of the T2CON register. output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output 14.3 Timer2 Output counter/postscaler (see Section14.2 “Timer2 Interrupt”). The unscaled output of TMR2 is available primarily to The TMR2 and PR2 registers are both directly readable the CCP modules, where it is used as a time base for and writable. The TMR2 register is cleared on any operations in PWM mode. device Reset, whereas the PR2 register initializes to Timer2 can be optionally used as the shift clock source FFh. Both the prescaler and postscaler counters are for the MSSP module operating in SPI mode by setting cleared on the following events: SSPM<3:0> = 0011 in the SSPxCON1 register. • a write to the TMR2 register Additional information is provided in Section16.0 • a write to the T2CON register “Master Synchronous Serial Port (MSSP) Module”. • Power-on Reset (POR) 14.4 Timer2 Operation During Sleep • Brown-out Reset (BOR) • MCLR Reset The Timer2 timers cannot be operated while the • Watchdog Timer (WDT) Reset processor is in Sleep mode. The contents of the TMR2 • Stack Overflow Reset and PR2 registers will remain unchanged while the processor is in Sleep mode. • Stack Underflow Reset • RESET Instruction 14.5 Peripheral Module Disable Note: TMR2 is not cleared when T2CON is written. When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power con- sumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bit for Tim- er2 (TMR2MD) is in the PMD0 register. See Section4.0 “Power-Managed Modes” for more information.  2012-2014 Microchip Technology Inc. DS30000684B-page 169

PIC18(L)F2X/45K50 14.6 Register Definitions: Timer2 Control REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2-type Clock Prescale Select bits 00 =Prescaler is 1 01 =Prescaler is 4 1x =Prescaler is 16 DS30000684B-page 170  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 PR2 Timer2 Period Register — T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 165 TMR2 Timer2 Register — Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Timer2.  2012-2014 Microchip Technology Inc. DS30000684B-page 171

PIC18(L)F2X/45K50 15.0 CAPTURE/COMPARE/PWM 15.1 Capture Mode MODULES The Capture mode function described in this section is identical for all CCP and ECCP modules available on The Capture/Compare/PWM module is a peripheral this device family. which allows the user to time and control different events, and to generate Pulse-Width Modulation Capture mode makes use of the 16-bit Timer (PWM) signals. In Capture mode, the peripheral allows resources, Timer1 and Timer3. The timer resources for the timing of the duration of an event. The Compare each CCP capture function are independent and are mode allows the user to trigger an external event when selected using the CCPTMRS register. When an event a predetermined amount of time has expired. The occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL PWM mode can generate Pulse-Width Modulated register pair captures and stores the 16-bit value of the signals of varying frequency and duty cycle. TMRxH:TMRxL register pair, respectively. An event is defined as one of the following and is configured by the This family of devices contains one Enhanced Capture/ CCPxM<3:0> bits of the CCPxCON register: Compare/PWM module (ECCP1) and one standard Capture/Compare/PWM module (CCP2). • Every falling edge The Capture and Compare functions are identical for • Every rising edge the CCP/ECCP modules. The difference between CCP • Every 4th rising edge and ECCP modules are in the Pulse-Width Modulation • Every 16th rising edge (PWM) function. In CCP modules, the standard PWM When a capture is made, the corresponding Interrupt function is identical. In ECCP modules, the Enhanced Request Flag bit CCPxIF of the PIR1 and PIR2 register PWM function has either full-bridge or half-bridge PWM is set. The interrupt flag must be cleared in software. If output. Full-bridge ECCP modules have four available another capture occurs before the value in the I/O pins while half-bridge ECCP modules only have two CCPRxH:CCPRxL register pair is read, the old available I/O pins. ECCP PWM modules are backward captured value is overwritten by the new captured compatible with CCP PWM modules and can be value. configured as standard PWM modules. Figure15-1 shows a simplified diagram of the Capture Note1: In devices with more than one CCP operation. module, it is very important to pay close attention to the register names used. A FIGURE 15-1: CAPTURE MODE number placed after the module acronym OPERATION BLOCK is used to distinguish between separate DIAGRAM modules. For example, the CCP1CON and CCP2CON control the same Set Flag bit CCPxIF operational aspects of two completely Prescaler (PIRx register) different CCP modules.  1, 4, 16 2: Throughout this section, generic CCPx CCPRxH CCPRxL pin references to a CCP module in any of its operating modes may be interpreted as and Capture Edge Detect Enable being equally applicable to ECCP1 and CCP2. Register names, module signals, TMRxH TMRxL I/O pins and bit names may use the CCPxM<3:0> generic designator ‘x’ to indicate the use of System Clock (FOSC) a numeral to distinguish a particular module, when required. DS30000684B-page 172  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 15.1.1 CCP PIN CONFIGURATION In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Some CCPx outputs are multiplexed on a couple of pins. Table15-1 shows the CCP output pin multiplexing. Selection of the output pin is determined by the CCPxMX bits in Configuration register 3H (CONFIG3H). Refer to Register26-5 for more details. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. TABLE 15-1: CCP PIN MULTIPLEXING CCP OUTPUT CONFIG 3H Control Bit Bit Value I/O pin 0 RB3 CCP2 CCP2MX 1(*) RC1 Legend: * = Default 15.1.2 TIMER1 MODE RESOURCE The 16-bit Timer resource must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. See Section13.0 “Timer1/3 Module with Gate Control” for more information on configuring the 16-bit Timers. 15.1.3 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. Note: Clocking the 16-bit Timer resource from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, the Timer resource must be clocked from the instruction clock (FOSC/4) or from an external clock source.  2012-2014 Microchip Technology Inc. DS30000684B-page 173

PIC18(L)F2X/45K50 15.1.4 CCP PRESCALER 15.1.5 CAPTURE DURING SLEEP There are four prescaler settings specified by the Capture mode requires a 16-bit TimerX module for use CCPxM<3:0> bits of the CCPxCON register. Whenever as a time base. There are four options for driving the the CCP module is turned off, or the CCP module is not 16-bit TimerX module in Capture mode. It can be driven in Capture mode, the prescaler counter is cleared. Any by the system clock (FOSC), the instruction clock (FOSC/ Reset will clear the prescaler counter. 4), or by the external clock sources, the Secondary Switching from one capture prescaler to another does Oscillator (SOSC), or the TxCKI clock input. When the not clear the prescaler and may generate a false 16-bit TimerX resource is clocked by FOSC or FOSC/4, TimerX will not increment during Sleep. When the interrupt. To avoid this unexpected operation, turn the device wakes from Sleep, TimerX will continue from its module off by clearing the CCPxCON register before previous state. Capture mode will operate during Sleep changing the prescaler. Example15-1 demonstrates when the 16-bit TimerX resource is clocked by one of the code to perform this function. the external clock sources (SOSC or the TxCKI pin). EXAMPLE 15-1: CHANGING BETWEEN CAPTURE PRESCALERS #define NEW_CAPT_PS 0x06 //Capture // Prescale 4th ... // rising edge CCPxCON = 0; // Turn the CCP // Module Off CCPxCON = NEW_CAPT_PS; // Turn CCP module // on with new // prescale value DS30000684B-page 174  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 15-2: REGISTERS ASSOCIATED WITH CAPTURE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 197 CCP2CON — — DC2B<1:0> CCP2M<3:0> 197 CCPR1H Capture/Compare/PWM Register 1, High Byte (MSB) — CCPR1L Capture/Compare/PWM Register 1, Low Byte (LSB) — CCPR2H Capture/Compare/PWM Register 2, High Byte (MSB) — CCPR2L Capture/Compare/PWM Register 2, Low Byte (LSB) — CCPTMRS — — — — C2TSEL — — C1TSEL 200 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC RD16 TMR1ON 165 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 166 T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC RD16 TMR3ON 165 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 166 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register — TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register — TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. TABLE 15-3: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 175

PIC18(L)F2X/45K50 15.2 Compare Mode 15.2.1 CCP PIN CONFIGURATION The Compare mode function described in this section The user must configure the CCPx pin as an output by is identical for all CCP and ECCP modules available on clearing the associated TRIS bit. this device family. Some CCPx outputs are multiplexed on a couple of Compare mode makes use of the 16-bit Timer pins. Table15-1 shows the CCP output pin resources, Timer1 and Timer3. The 16-bit value of the multiplexing. Selection of the output pin is determined CCPRxH:CCPRxL register pair is constantly compared by the CCPxMX bits in Configuration register 3H against the 16-bit value of the TMRxH:TMRxL register (CONFIG3H). Refer to Register26-5 for more details. pair. When a match occurs, one of the following events Note: Clearing the CCPxCON register will force can occur: the CCPx compare output latch to the • Toggle the CCPx output default low level. This is not the PORT I/O data latch. • Set the CCPx output • Clear the CCPx output 15.2.2 TimerX MODE RESOURCE • Generate a Special Event Trigger In Compare mode, 16-bit TimerX resource must be • Generate a Software Interrupt running in either Timer mode or Synchronized Counter The action on the pin is based on the value of the mode. The compare operation may not work in CCPxM<3:0> control bits of the CCPxCON register. At Asynchronous Counter mode. the same time, the interrupt flag CCPxIF bit is set. See Section13.0 “Timer1/3 Module with Gate All Compare modes can generate an interrupt. Control” for more information on configuring the 16-bit Figure15-2 shows a simplified diagram of the TimerX resources. Compare operation. Note: Clocking TimerX from the system clock (FOSC) should not be used in Compare FIGURE 15-2: COMPARE MODE mode. In order for Compare mode to OPERATION BLOCK recognize the trigger event on the CCPx DIAGRAM pin, TimerX must be clocked from the instruction clock (FOSC/4) or from an CCPxM<3:0> Mode Select external clock source. Set CCPxIF Interrupt Flag 15.2.3 SOFTWARE INTERRUPT MODE (PIRx) CCPx 4 When Generate Software Interrupt mode is chosen Pin CCPRxH CCPRxL (CCPxM<3:0>=1010), the CCPx module does not Q S assert control of the CCPx pin (see the CCPxCON Output Comparator R Logic Match register). TMRxH TMRxL TRIS Output Enable Special Event Trigger Special Event Trigger function on • ECCP1 and CCP2 will: - Reset TimerX – TMRxH:TMRxL = 0x0000 - TimerX Interrupt Flag, (TMRxIF) is not set Additional Function on • CCP2 will - Set ADCON0<1>, GO/DONE bit to start an ADC Conversion if ADCON<0>, ADON = 1, and if ADCON1<7>, TRIGSEL = 0. DS30000684B-page 176  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 15.2.4 SPECIAL EVENT TRIGGER 15.2.5 COMPARE DURING SLEEP When Special Event Trigger mode is selected The Compare mode is dependent upon the system (CCPxM<3:0>=1011), and a match of the clock (FOSC) for proper operation. Since FOSC is shut TMRxH:TMRxL and the CCPRxH:CCPRxL registers down during Sleep mode, the Compare mode will not occurs, all CCPx and ECCPx modules will immediately: function properly during Sleep. • Set the CCP interrupt flag bit – CCPxIF • CCP2 will start an ADC conversion, if the ADC is enabled and TRIGSEL is configured for CCP2. On the next TimerX rising clock edge: • A Reset of TimerX register pair occurs – TMRxH:TMRxL = 0x0000, This Special Event Trigger mode does not: • Assert control over the CCPx or ECCPx pins. • Set the TMRxIF interrupt bit when the TMRxH:TMRxL register pair is reset. (TMRxIF gets set on a TimerX overflow.) If the value of the CCPRxH:CCPRxL registers are modified when a match occurs, the user should be aware that the automatic reset of TimerX occurs on the next rising edge of the clock. Therefore, modifying the CCPRxH:CCPRxL registers before this reset occurs will allow the TimerX to continue without being reset, inadvertently resulting in the next event being advanced or delayed. The Special Event Trigger mode allows the CCPRxH:CCPRxL register pair to effectively provide a 16-bit programmable period register for TimerX.  2012-2014 Microchip Technology Inc. DS30000684B-page 177

PIC18(L)F2X/45K50 TABLE 15-4: REGISTERS ASSOCIATED WITH COMPARE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 197 CCP2CON — — DC2B<1:0> CCP2M<3:0> 197 CCPR1H Capture/Compare/PWM Register 1, High Byte (MSB) — CCPR1L Capture/Compare/PWM Register 1, Low Byte (LSB) — CCPR2H Capture/Compare/PWM Register 2, High Byte (MSB) — CCPR2L Capture/Compare/PWM Register 2, Low Byte (LSB) — CCPTMRS — — — — C2TSEL — — C1TSEL 200 ADCON1 TRIGSEL — — — PVCFG<1:0> NVCFG<1:0> 295 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC RD16 TMR1ON 165 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 166 T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC RD16 TMR3ON 165 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 166 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register — TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register — TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. TABLE 15-5: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. DS30000684B-page 178  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 15.3 PWM Overview FIGURE 15-3: CCP PWM OUTPUT SIGNAL Pulse-Width Modulation (PWM) is a scheme that Period provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles Pulse Width a square wave where the high portion of the signal is TMR2 = PR2 considered the on state and the low portion of the signal TMR2 = CCPRxH:CCPxCON<5:4> is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in TMR2 = 0 steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to FIGURE 15-4: SIMPLIFIED PWM BLOCK the load. Lowering the number of steps applied, which DIAGRAM shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete CCPxCON<5:4> cycle or the total amount of on and off time combined. Duty Cycle Registers PWM resolution defines the maximum number of steps CCPRxL that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. CCPRxH(2) (Slave) CCPx The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, Comparator R Q where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher S TMR2 (1) duty cycle corresponds to more power applied. TRIS Figure15-3 shows a typical waveform of the PWM signal. Comparator Clear Timer, toggle CCPx pin and 15.3.1 STANDARD PWM OPERATION latch duty cycle PR2 The standard PWM function described in this section is Note 1: The 8-bit timer TMR2 register is concatenated available and identical for CCP and ECCP modules. with the 2-bit internal system clock (FOSC), or The standard PWM mode generates a Pulse-Width two bits of the prescaler, to create the 10-bit Modulation (PWM) signal on the CCPx pin with up to 10 time base. bits of resolution. The period, duty cycle, and resolution 2: In PWM mode, CCPRxH is a read-only register. are controlled by the following registers: • PR2 register 15.3.2 SETUP FOR PWM OPERATION • T2CON register The following steps should be taken when configuring • CCPRxL registers the CCP module for standard PWM operation: • CCPxCON registers 1. Disable the CCPx pin output driver by setting the Figure15-4 shows a simplified block diagram of PWM associated TRIS bit. operation. 2. Load the PR2 register for Timer2 with the PWM period value. 3. Configure the CCP module for the PWM mode Note1: The corresponding TRIS bit must be by loading the CCPxCON register with the cleared to enable the PWM output on the appropriate values. CCPx pin. 4. Load the CCPRxL register and the DCxB<1:0> 2: Clearing the CCPxCON register will bits of the CCPxCON register, with the PWM relinquish control of the CCPx pin. duty cycle value.  2012-2014 Microchip Technology Inc. DS30000684B-page 179

PIC18(L)F2X/45K50 5. Configure and start the 8-bit Timer2: 15.3.4 PWM DUTY CYCLE • Clear the TMR2IF interrupt flag bit of the The PWM duty cycle is specified by writing a 10-bit PIR1 register. See Note1 below. value to multiple registers: CCPRxL register and • Configure the T2CKPS bits of the T2CON DCxB<1:0> bits of the CCPxCON register. The register with the Timer prescale value. CCPRxL contains the eight MSbs and the DCxB<1:0> • Enable the Timer by setting the TMR2ON bits of the CCPxCON register contain the two LSbs. bit of the T2CON register. CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle 6. Enable PWM output pin: value is not latched into CCPRxH until after the period • Wait until the Timer overflows and the completes (i.e., a match between PR2 and TMR2 TMR2IF bit of the PIR1 register is set. See registers occurs). While using the PWM, the CCPRxH Note1 below. register is read-only. • Enable the CCPx pin output driver by clearing the associated TRIS bit. Equation15-2 is used to calculate the PWM pulse width. Note1: In order to send a complete duty cycle and period on the first PWM output, the Equation15-3 is used to calculate the PWM duty cycle above steps must be included in the ratio. setup sequence. If it is not critical to start with a complete PWM signal on the first EQUATION 15-2: PULSE WIDTH output, then step 5 may be ignored. Pulse Width = CCPRxL:CCPxCON<5:4>  15.3.3 PWM PERIOD TOSC  (TMR2 Prescale Value) The PWM period is specified by the PR2 register of 8-bit Timer2. The PWM period can be calculated using the formula of Equation15-1. EQUATION 15-3: DUTY CYCLE RATIO EQUATION 15-1: PWM PERIOD CCPRxL:CCPxCON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------- 4PR2+1 PWM Period = PR2+14TOSC (TMR2 Prescale Value) The CCPRxH register and a 2-bit internal latch are Note 1: TOSC = 1/FOSC used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When TMR2 is equal to PR2, the following three events The 8-bit timer TMR2 register is concatenated with occur on the next increment cycle: either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The • TMR2 is cleared system clock is used if the Timer2 prescaler is set to 1:1. • The CCPx pin is set. (Exception: If the PWM duty cycle=0%, the pin will not be set.) When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see • The PWM duty cycle is latched from CCPRxL into Figure15-4). CCPRxH. Note: The Timer postscaler (see Section14.0 “Timer2 Module”) is not used in the determination of the PWM frequency. DS30000684B-page 180  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 15.3.5 PWM RESOLUTION EQUATION 15-4: PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution log4PR2+1 Resolution = ------------------------------------------ bits will result in 1024 discrete duty cycles, whereas an 8-bit log2 resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is Note: If the pulse width value is greater than the 255. The resolution is a function of the PR2 register period the assigned PWM pin(s) will value as shown by Equation15-4. remain unchanged. TABLE 15-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz) PWM Frequency 1.95 kHz 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 15-7: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 15-8: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 15.3.6 OPERATION IN SLEEP MODE 15.3.8 EFFECTS OF RESET In Sleep mode, the TMR2register will not increment Any Reset will force all ports to Input mode and the and the state of the module will not change. If the CCPx CCP registers to their Reset states. pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 15.3.7 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section3.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details.  2012-2014 Microchip Technology Inc. DS30000684B-page 181

PIC18(L)F2X/45K50 TABLE 15-9: REGISTERS ASSOCIATED WITH STANDARD PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 197 CCP2CON — — DC2B<1:0> CCP2M<3:0> 197 CCPTMRS — — — — C2TSEL — — C1TSEL 200 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 PR2 Timer2 Period Register — T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 170 TMR2 Timer2 Period Register — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. TABLE 15-10: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. DS30000684B-page 182  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 15.4 PWM (Enhanced Mode) To select an Enhanced PWM Output mode, the PxM<1:0> bits of the CCPxCON register must be The enhanced PWM function described in this section is configured appropriately. available for CCP module ECCP1. The PWM outputs are multiplexed with I/O pins and are The enhanced PWM mode generates a Pulse-Width designated PxA, PxB, PxC and PxD. The polarity of the Modulation (PWM) signal on up to four different output PWM pins is configurable and is selected by setting the pins with up to 10 bits of resolution. The period, duty CCPxM bits in the CCPxCON register appropriately. cycle, and resolution are controlled by the following Figure15-5 shows an example of a simplified block registers: diagram of the Enhanced PWM module. • PR2 register Table15-11 shows the pin assignments for various • T2CON register Enhanced PWM modes. • CCPRxL registers Note 1: The corresponding TRIS bit must be • CCPxCON registers cleared to enable the PWM output on the The ECCP modules have the following additional PWM CCPx pin. registers which control Auto-shutdown, Auto-restart, 2: Clearing the CCPxCON register will Dead-band Delay and PWM Steering modes: relinquish control of the CCPx pin. • ECCPxAS registers 3: Any pin not used in the enhanced PWM • PSTRxCON registers mode is available for alternate pin • PWMxCON registers functions, if applicable. The enhanced PWM module can generate the following 4: To prevent the generation of an five PWM Output modes: incomplete waveform when the PWM is • Single PWM first enabled, the ECCP module waits • Half-Bridge PWM until the start of a new PWM period before generating a PWM signal. • Full-Bridge PWM, Forward mode • Full-Bridge PWM, Reverse mode • Single PWM with PWM Steering mode FIGURE 15-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DCxB<1:0> PxM<1:0> CCPxM<3:0> Duty Cycle Registers 2 4 CCPRxL CCPx/PxA CCPx/PxA TRISx CCPRxH (Slave) PxB PxB Output TRISx Comparator R Q Controller PxC PxC(2) TMR2 (1) S TRISx PxD PxD(2) Comparator Clear Timer, TRISx toggle PWM pin and latch duty cycle PR2 PWMxCON Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or two bits of the prescaler to create the 10-bit time base. 2: PxC and PxD are not available on half-bridge ECCP modules.  2012-2014 Microchip Technology Inc. DS30000684B-page 183

PIC18(L)F2X/45K50 TABLE 15-11: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> CCPx/PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: PWM Steering enables outputs in Single mode. FIGURE 15-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse PRX+1 PxM<1:0> Signal 0 Width Period 00 (Single Output) PxA Modulated Delay(1) Delay(1) PxA Modulated 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>) Note 1: Dead-band delay is programmed using the PWMxCON register (Section15.4.5 “Programmable Dead-Band Delay Mode”). DS30000684B-page 184  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 15-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal 0 Pulse PRx+1 Width Period 00 (Single Output) PxA Modulated PxA Modulated Delay(1) Delay(1) 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>) Note 1: Dead-band delay is programmed using the PWMxCON register (Section15.4.5 “Programmable Dead-Band Delay Mode”).  2012-2014 Microchip Technology Inc. DS30000684B-page 185

PIC18(L)F2X/45K50 15.4.1 HALF-BRIDGE MODE Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be In Half-Bridge mode, two pins are used as outputs to cleared to configure PxA and PxB as outputs. drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM FIGURE 15-8: EXAMPLE OF HALF- output signal is output on the PxB pin (see Figure15-9). BRIDGE PWM OUTPUT This mode can be used for half-bridge applications, as shown in Figure15-9, or for full-bridge applications, Period Period where four power switches are being modulated with two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay PxA(2) can be used to prevent shoot-through current in half- td bridge power devices. The value of the PDC<6:0> bits of td the PWMxCON register sets the number of instruction PxB(2) cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output (1) (1) (1) remains inactive during the entire cycle. See Section15.4.5 “Programmable Dead-Band Delay td = Dead-Band Delay Mode” for more details of the dead-band delay Note 1: At this time, the TMRx register is equal to the operations. PRx register. 2: Output signals are shown as active-high. FIGURE 15-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA - Load FET Driver + PxB - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver PxA Load FET FET Driver Driver PxB DS30000684B-page 186  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 15.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of full-bridge application is shown in Figure15-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure15-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure15-11. PxA, PxB, PxC and PxD outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs. FIGURE 15-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver PxA Load PxB FET FET Driver Driver PxC QB QD V- PxD  2012-2014 Microchip Technology Inc. DS30000684B-page 187

PIC18(L)F2X/45K50 FIGURE 15-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA(2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) (1) Note 1: At this time, the TMRx register is equal to the PRx register. 2: Output signal is shown as active-high. DS30000684B-page 188  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 15.4.2.1 Direction Change in Full-Bridge The Full-Bridge mode does not provide dead-band Mode delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation In the Full-Bridge mode, the PxM1 bit in the CCPxCON where dead-band delay is required. This situation register allows users to control the forward/reverse occurs when both of the following conditions are true: direction. When the application firmware changes this direction control bit, the module will change to the new 1. The direction of the PWM output changes when direction on the next PWM cycle. the duty cycle of the output is at or near 100%. 2. The turn off time of the power switch, including A direction change is initiated in software by changing the power device and driver circuit, is greater the PxM1 bit of the CCPxCON register. The following than the turn on time. sequence occurs four Timer cycles prior to the end of the current PWM period: Figure15-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty • The modulated outputs (PxB and PxD) are placed cycle. In this example, at time t1, the output PxA and in their inactive state. PxD become inactive, while output PxC becomes • The associated unmodulated outputs (PxA and active. Since the turn off time of the power devices is PxC) are switched to drive in the opposite longer than the turn on time, a shoot-through current direction. will flow through power devices QC and QD (see • PWM modulation resumes at the beginning of the Figure15-10) for the duration of ‘t’. The same next period. phenomenon will occur to power devices QA and QB See Figure15-12 for an illustration of this sequence. for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 15-12: EXAMPLE OF PWM DIRECTION CHANGE Signal Period(1) Period PxA (Active-High) PxB (Active-High) Pulse Width PxC (Active-High) (2) PxD (Active-High) Pulse Width Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle. 2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is (Timer2 Prescale)/FOSC.  2012-2014 Microchip Technology Inc. DS30000684B-page 189

PIC18(L)F2X/45K50 FIGURE 15-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential T = TOFF – TON Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver. 15.4.3 ENHANCED PWM AUTO- of each pin pair is determined by the PSSxAC<1:0> and SHUTDOWN MODE PSSxBD<1:0> bits of the ECCPxAS register. Each pin pair may be placed into one of three states: The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external • Drive logic ‘1’ shutdown event occurs. Auto-Shutdown mode places • Drive logic ‘0’ the PWM output pins into a predetermined state. This • Tri-state (high-impedance) mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the Note1: The auto-shutdown condition is a level- based signal, not an edge-based signal. ECCPxAS register. A shutdown event may be generated As long as the level is present, the auto- by: shutdown will persist. • A logic ‘0’ on the FLTx pin 2: Writing to the ECCPxASE bit is disabled • Comparator Cx (async_CxOUT) while an auto-shutdown condition • Setting the ECCPxASE bit in firmware persists. A shutdown condition is indicated by the ECCPxASE 3: Once the auto-shutdown condition has (Auto-Shutdown Event Status) bit of the ECCPxAS been removed and the PWM restarted register. If the bit is a ‘0’, the PWM pins are operating (either through firmware or auto-restart), normally. If the bit is a ‘1’, the PWM outputs are in the the PWM signal will always restart at the shutdown state. beginning of the next PWM period. When a shutdown event occurs, two things happen: The ECCPxASE bit is set to ‘1’. The ECCPxASE will remain set until cleared in firmware or an auto-restart occurs (see Section15.4.4 “Auto-Restart Mode”). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [PxA/PxC] and [PxB/PxD]. The state DS30000684B-page 190  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 15-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0) Missing Pulse Missing Pulse (Auto-Shutdown) (ECCPxASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent ECCPxASE bit PWM Shutdown Shutdown Resumes Event Occurs Event Clears ECCPxASE Cleared by Firmware 15.4.4 AUTO-RESTART MODE If auto-restart is enabled, the ECCPxASE bit will remain set as long as the auto-shutdown condition is The Enhanced PWM can be configured to active. When the auto-shutdown condition is removed, automatically restart the PWM signal once the auto- the ECCPxASE bit will be cleared via hardware and shutdown condition has been removed. Auto-restart is normal operation will resume. enabled by setting the PxRSEN bit in the PWMxCON register. FIGURE 15-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1) Missing Pulse Missing Pulse (Auto-Shutdown) (ECCPxASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent ECCPxASE bit PWM Shutdown Resumes Event Occurs Shutdown ECCPxASE Event Clears Cleared by Hardware  2012-2014 Microchip Technology Inc. DS30000684B-page 191

PIC18(L)F2X/45K50 15.4.5 PROGRAMMABLE DEAD-BAND FIGURE 15-16: EXAMPLE OF HALF- DELAY MODE BRIDGE PWM OUTPUT In half-bridge applications where all power switches are Period Period modulated at the PWM frequency, the power switches Pulse Width normally require more time to turn off than to turn on. If both the upper and lower power switches are switched PxA(2) at the same time (one turned on, and the other turned td off), both switches may be on for a short period of time td until one switch completely turns off. During this brief PxB(2) interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge (1) (1) (1) supply. To avoid this potentially destructive shoot- through current from flowing during switching, turning td = Dead-Band Delay on either of the power switches is normally delayed to allow the other switch to completely turn off. Note 1: At this time, the TMRx register is equal to the PRx register. In Half-Bridge mode, a digitally programmable dead- band delay is available to avoid shoot-through current 2: Output signals are shown as active-high. from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure15-16 for illustration. The lower seven bits of the associated PWMxCON register (Register15-5) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 15-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA V - Load FET Driver + PxB V - V- DS30000684B-page 192  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 15.4.6 PWM STEERING MODE FIGURE 15-18: SIMPLIFIED STEERING BLOCK DIAGRAM In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the STRxA same PWM signal can be simultaneously available on multiple pins. PxA Signal PxA pin CCPxM1 1 Once the Single Output mode is selected (CCPxM<3:2>=11 and PxM<1:0>=00 of the PORT Data CCPxCON register), the user firmware can bring out 0 TRIS the same PWM signal to one, two, three or four output STRxB pins by setting the appropriate Steering Enable bits (STRxA, STRxB, STRxC and/or STRxD) of the CCPxM0 1 PxB pin PSTRxCON register, as shown in Table15-12. PORT Data 0 TRIS Note: The associated TRIS bits must be set to STRxC output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. CCPxM1 1 PxC pin While the PWM Steering mode is active, CCPxM<1:0> PORT Data 0 bits of the CCPxCON register select the PWM output TRIS polarity for the PxD, PxC, PxB and PxA pins. STRxD The PWM auto-shutdown operation also applies to PWM Steering mode as described in Section15.4.3 CCPxM0 1 PxD pin “Enhanced PWM Auto-Shutdown Mode”. An auto- shutdown event will only affect pins that have PWM PORT Data 0 outputs enabled. TRIS Note 1: Port outputs are configured as shown when the CCPxCON register bits PxM<1:0>=00 and CCPxM<3:2>=11. 2: Single PWM output requires setting at least one of the STRx bits. 15.4.6.1 Steering Synchronization The STRxSYNC bit of the PSTRxCON register gives the user two selections of when the steering event will happen. When the STRxSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the PxA, PxB, PxC and PxD pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. When the STRxSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. Figures 15-19 and 15-20 illustrate the timing diagrams of the PWM steering depending on the STRxSYNC setting.  2012-2014 Microchip Technology Inc. DS30000684B-page 193

PIC18(L)F2X/45K50 15.4.7 START-UP CONSIDERATIONS modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM When any PWM mode is used, the application pin output drivers. The completion of a full PWM cycle hardware must use the proper external pull-up and/or is indicated by the TMR2IF bit of the PIR1 register pull-down resistors on the PWM output pins. being set as the second PWM period begins. The CCPxM<1:0> bits of the CCPxCON register allow the user to choose whether the PWM output signals are Note: When the microcontroller is released from Reset, all of the I/O pins are in the high- active-high or active-low for each pair of PWM output impedance state. The external circuits pins (PxA/PxC and PxB/PxD). The PWM output must keep the power switch devices in the polarities must be selected before the PWM pin output Off state until the microcontroller drives drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are the I/O pins with the proper signal levels or activates the PWM output(s). enabled is not recommended since it may result in damage to the application circuits. The PxA, PxB, PxC and PxD output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM FIGURE 15-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0) PWM Period PWM STRx P1<D:A> PORT Data PORT Data P1n = PWM FIGURE 15-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRxSYNC = 1) PWM STRx P1<D:A> PORT Data PORT Data P1n = PWM DS30000684B-page 194  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 15.4.8 SETUP FOR ECCP PWM 9. Configure and start TMR2: OPERATION USING ECCP1 AND • Set the TMR2 prescale value by loading the TIMER2 T2CKPS bits of the T2CON register. The following steps should be taken when configuring • Start Timer2 by setting the TMR2ON bit. the ECCP1 module for PWM operation using Timer2: 10. Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. 1. Configure the PWM pins to be used (P1A, P1B, 11. Start the PWM: P1C, and P1D): • If shutdown auto-restart is used, then set the • Configure PWM outputs to be used as inputs P1RSEN bit of the PWM1CON register. by setting the corresponding TRIS bits. This prevents spurious outputs during setup. • If shutdown auto-restart is not used, then • Set the PSTR1CON bits for each PWM clear the CCP1ASE bit of the ECCP1AS register. output to be used. 2. Set the PWM period by loading the PR2 register. 3. Configure auto-shutdown as OFF or select the source with the CCP1AS<2:0> bits of the ECCP1AS register. 4. Configure the auto-shutdown sources as needed: • Configure each comparator used. • Configure the comparator inputs as analog. • Configure the FLT0 input pin and clear ANSB0. 5. Force a shutdown condition (OFF included): • Configure safe starting output levels by setting the default shutdown drive states with the PSS1AC<1:0> and PSS1BD<1:0> bits of the ECCP1AS register. • Clear the P1RSEN bit of the PWM1CON register. • Set the CCP1AS bit of the ECCP1AS register. 6. Configure the ECCP1 module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: • Select one of the available output configura- tions and direction with the P1M<1:0> bits. • Select the polarities of the PWM output signals with the CCP1M<3:0> bits. 7. Set the 10-bit PWM duty cycle: • Load the eight MS bits into the CCPR1L register. • Load the two LS bits into the DC<1:0> bits of the CCP1CON register. 8. For Half-Bridge Output mode, set the dead- band delay by loading P1DC<6:0> bits of the PWM1CON register with the appropriate value.  2012-2014 Microchip Technology Inc. DS30000684B-page 195

PIC18(L)F2X/45K50 TABLE 15-12: REGISTERS ASSOCIATED WITH ENHANCED PWM Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 page ECCP1AS ECCP1ASE ECCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 201 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 197 CCPTMRS — — — — C2TSEL — — C1TSEL 200 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 PR2 Timer2 Period Register — PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A 202 PWM1CON P1RSEN P1DC<6:0> 202 T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 170 TMR2 Timer2 Period Register — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 149 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. Note 1: These registers/bits are available on PIC18(L)F45K50 devices. DS30000684B-page 196  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 15.5 Register Definitions: ECCP Control REGISTER 15-1: CCPxCON: STANDARD CCPx CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB<1:0> CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unused bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets the module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set) 1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set) 1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected, CCPxIF is set) 1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set) TimerX (selected by CxTSEL bits) is reset ADON is set, starting A/D conversion if A/D module is enabled and TRIGSEL is clear(1) 11xx =: PWM mode Note 1: This feature is available on CCP2 only.  2012-2014 Microchip Technology Inc. DS30000684B-page 197

PIC18(L)F2X/45K50 REGISTER 15-2: CCPxCON: ENHANCED CCPx CONTROL REGISTER R/x-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM<1:0> DCxB<1:0> CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: (Capture/Compare modes) xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins Half-Bridge ECCP Modules(1): If CCPxM<3:2> = 11: (PWM modes) 0x = Single output; PxA modulated; PxB assigned as port pin 1x = Half-bridge output; PxA, PxB modulated with dead-band control Full-Bridge ECCP Modules(1): If CCPxM<3:2> = 11: (PWM modes) 00 = Single output; PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-bridge output forward; PxD modulated; PxA active; PxB, PxC inactive 10 = Half-bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins 11 = Full-bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. Note 1: See Table15-1 to determine full-bridge and half-bridge ECCPs for the device being used. DS30000684B-page 198  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 15-2: CCPxCON: ENHANCED CCPx CONTROL REGISTER (CONTINUED) bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets the module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set) 1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set) 1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected, CCPxIF is set) 1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set) TimerX is reset Half-Bridge ECCP Modules(1): 1100 = PWM mode: PxA active-high; PxB active-high 1101 = PWM mode: PxA active-high; PxB active-low 1110 = PWM mode: PxA active-low; PxB active-high 1111 = PWM mode: PxA active-low; PxB active-low Full-Bridge ECCP Modules(1): 1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low Note 1: See Table15-1 to determine full-bridge and half-bridge ECCPs for the device being used.  2012-2014 Microchip Technology Inc. DS30000684B-page 199

PIC18(L)F2X/45K50 REGISTER 15-3: CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER 0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 — — — — C2TSEL — — C1TSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 C2TSEL: CCP2 Timer Selection bit 0 = CCP2 – Capture/Compare modes use TMR1, PWM modes use TMR2 1 = CCP2 – Capture/Compare modes use TMR3, PWM modes use TMR2 bit 2-1 Unimplemented: Read as ‘0’ bit 0 C1TSEL: ECCP1 Timer Selection bit 0 = ECCP1 – Capture/Compare modes use TMR1, PWM modes use TMR2 1 = ECCP1 – Capture/Compare modes use TMR3, PWM modes use TMR2 DS30000684B-page 200  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 15-4: ECCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPxASE ECCPxAS<2:0> PSSxAC<1:0> PSSxBD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ECCPxASE: CCPx Auto-shutdown Event Status bit if PxRSEN = 1; 1 = An Auto-shutdown event occurred; ECCPxASE bit will automatically clear when event goes away; CCPx outputs in shutdown state 0 = CCPx outputs are operating if PxRSEN = 0; 1 = An Auto-shutdown event occurred; bit must be cleared in software to restart PWM; CCPx outputs in shutdown state 0 = CCPx outputs are operating bit 6-4 ECCPxAS<2:0>: CCPx Auto-Shutdown Source Select bits (1) 000 =Auto-shutdown is disabled 001 =Comparator C1 (async_C1OUT) – output high will cause shutdown event 010 =Comparator C2 (async_C2OUT) – output high will cause shutdown event 011 =Either Comparator C1 or C2 – output high will cause shutdown event 100 =FLT0 pin - low level will cause shutdown event 101 =FLT0 pin or Comparator C1 (async_C1OUT) – low level will cause shutdown event 110 =FLT0 pin or Comparator C2 (async_C2OUT) – low level will cause shutdown event 111 =FLT0 pin or Comparators C1 or C2 – low level will cause shutdown event bit 3-2 PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits 00 = Drive pins PxA and PxC to ‘0’ 01 = Drive pins PxA and PxC to ‘1’ 1x = Pins PxA and PxC tri-state bit 1-0 PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits 00 = Drive pins PxB and PxD to ‘0’ 01 = Drive pins PxB and PxD to ‘1’ 1x = Pins PxB and PxD tri-state Note 1: If C1SYNC or C2SYNC bits in the CM2CON1 register are enabled, the shutdown will be delayed by Tim- er1.  2012-2014 Microchip Technology Inc. DS30000684B-page 201

PIC18(L)F2X/45K50 REGISTER 15-5: PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPxASE must be cleared in software to restart the PWM bit 6-0 PxDC<6:0>: PWM Delay Count bits PxDCx = Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active REGISTER 15-6: PSTRxCON: PWM STEERING CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — — STRxSYNC STRxD STRxC STRxB STRxA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRxSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRxD: Steering Enable bit D 1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxD pin is assigned to port pin bit 2 STRxC: Steering Enable bit C 1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxC pin is assigned to port pin bit 1 STRxB: Steering Enable bit B 1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxB pin is assigned to port pin bit 0 STRxA: Steering Enable bit A 1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxA pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2>=11 and PxM<1:0>=00. DS30000684B-page 202  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.0 MASTER SYNCHRONOUS The SPI interface supports the following modes and SERIAL PORT (MSSP) features: MODULE • Master mode • Slave mode 16.1 Module Overview • Clock Parity • Slave Select Synchronization (Slave mode only) The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other • Daisy chain connection of slave devices peripheral or microcontroller devices. These peripheral Figure16-1 is a block diagram of the SPI interface devices may be Serial EEPROMs, shift registers, module. display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) FIGURE 16-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SDI SSPxSR Reg SDO bit 0 Shift Clock SS SS Control 2 (CKP, CKE) Enable Clock Select Edge Select SSPxM<3:0> 4 ( T M R 2 O u tp u t ) 2 SCK Edge Prescaler TOSC Select 4, 16, 64 Baud Rate Generator TRIS bit (SSPxADD)  2012-2014 Microchip Technology Inc. DS30000684B-page 203

PIC18(L)F2X/45K50 The I2C interface supports the following modes and • General call address matching features: • Address masking • Master mode • Address Hold and Data Hold modes • Slave mode • Selectable SDA hold times • Byte NACKing (Slave mode) Figure16-2 is a block diagram of the I2C interface • Limited Multi-master support module in Master mode. Figure16-3 is a diagram of the • 7-bit and 10-bit addressing I2C interface module in Slave mode. • Start and Stop interrupts • Interrupt masking • Clock stretching • Bus collision detection FIGURE 16-2: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE) Internal Data Bus [SSPxM 3:0] Read Write SSPxBUF Baud Rate Generator (SSPxADD) SDA Shift SDA in Clock SSPxSR ect MSb LSb ntl Det e) Enable (RCEN) GenSetAararcttk ebn i(otS,w SSletPodxpgC ebOit,N2) Clock C Arbitrate/BCOL d off clock sourc SCL ceive Clock (Hol e R Start bit Detect, Stop bit Detect SCL in Write Collision Detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV Clock Arbitration Reset SEN, PEN (SSPxCON2) Bus Collision State Counter for Set SSPIF, BCLIF end of XMIT/RCV Address Match Detect DS30000684B-page 204  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 16-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCL Shift Clock SSPxSR Reg SDA MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Set, Reset Stop bit Detect S, P bits (SSPxSTAT Reg)  2012-2014 Microchip Technology Inc. DS30000684B-page 205

PIC18(L)F2X/45K50 16.2 SPI Mode Overview register and the master device is reading this bit from that same line and saving it as the LSb of its shift The Serial Peripheral Interface (SPI) bus is a register. synchronous serial data communication bus that After eight bits have been shifted out, the master and operates in Full-Duplex mode. Devices communicate slave have exchanged register values. in a master/slave environment where the master device initiates the communication. A slave device is If there is more data to exchange, the shift registers are controlled through a chip select known as Slave Select. loaded with new data and the process repeats itself. The SPI bus specifies four signal connections: Whether the data is meaningful or not (dummy data), depends on the application software. This leads to • Serial Clock (SCK) three scenarios for data transmission: • Serial Data Out (SDO) • Master sends useful data and slave sends dummy • Serial Data In (SDI) data. • Slave Select (SS) • Master sends useful data and slave sends useful Figure16-1 shows the block diagram of the MSSP data. module when operating in SPI Mode. • Master sends dummy data and slave sends useful The SPI bus operates with a single master device and data. one or more slave devices. When multiple slave Transmissions may involve any number of clock devices are used, an independent Slave Select cycles. When there is no more data to be transmitted, connection is required from the master device to each the master stops sending the clock signal and it slave device. deselects the slave. Figure16-4 shows a typical connection between a Every slave device connected to the bus that has not master device and multiple slave devices. been selected through its slave select line must disre- The master selects only one slave at a time. Most slave gard the clock and transmission signals and must not devices have tri-state outputs so their output signal transmit out any data of its own. appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure16-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits infor- mation out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that at the same time, the slave device is sending out the MSb from its shift DS30000684B-page 206  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 16-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SCLK SCLK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS General I/O General I/O SCLK SDI SPI Slave SDO #2 SS SCLK SDI SPI Slave SDO #3 SS 16.2.1 SPI MODE REGISTERS 16.2.2 SPI MODE OPERATION The MSSP module has five registers for SPI mode When initializing the SPI, several options need to be operation. These are: specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). • MSSP STATUS register (SSPxSTAT) These control bits allow the following to be specified: • MSSP Control register 1 (SSPxCON1) • Master mode (SCK is the clock output) • MSSP Control register 3 (SSPxCON3) • Slave mode (SCK is the clock input) • MSSP Data Buffer register (SSPxBUF) • Clock Polarity (Idle state of SCK) • MSSP Address register (SSPxADD) • Data Input Sample Phase (middle or end of data • MSSP Shift register (SSPxSR) output time) (Not directly accessible) • Clock Edge (output data on rising/falling edge of SSPxCON1 and SSPxSTAT are the control and SCK) STATUS registers in SPI mode operation. The • Clock Rate (Master mode only) SSPxCON1 register is readable and writable. The lower six bits of the SSPxSTAT are read-only. The • Slave Select mode (Slave mode only) upper two bits of the SSPxSTAT are read/write. To enable the serial port, SSPx Enable bit, SSPxEN of In one SPI Master mode, SSPxADD can be loaded the SSPxCON1 register, must be set. To reset or recon- with a value used in the Baud Rate Generator. More figure SPI mode, clear the SSPxEN bit, re-initialize the information on the Baud Rate Generator is available in SSPxCONx registers and then set the SSPxEN bit. Section16.7 “Baud Rate Generator”. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port SSPxSR is the shift register used for shifting data in function, some must have their data direction bits (in and out. SSPxBUF provides indirect access to the the TRIS register) appropriately programmed as SSPxSR register. SSPxBUF is the buffer register to follows: which data bytes are written, and from which data bytes are read. • SDI must have corresponding TRIS bit set • SDO must have corresponding TRIS bit cleared In receive operations, SSPxSR and SSPxBUF together create a buffered receiver. When SSPxSR • SCK (Master mode) must have corresponding receives a complete byte, it is transferred to SSPxBUF TRIS bit cleared and the SSPIF interrupt is set. • SCK (Slave mode) must have corresponding TRIS bit set During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and • SS must have corresponding TRIS bit set SSPxSR.  2012-2014 Microchip Technology Inc. DS30000684B-page 207

PIC18(L)F2X/45K50 Any serial port function that is not desired may be register, will be set. User software must clear the overridden by programming the corresponding data WCOL bit to allow the following write(s) to the direction (TRIS) register to the opposite value. SSPxBUF register to complete successfully. The MSSP consists of a transmit/receive shift register When the application software is expecting to receive (SSPxSR) and a buffer register (SSPxBUF). The valid data, the SSPxBUF should be read before the SSPxSR shifts the data in and out of the device, MSb next byte of data to transfer is written to the SSPxBUF. first. The SSPxBUF holds the data that was written to The Buffer Full bit, BF of the SSPxSTAT register, the SSPxSR until the received data is ready. Once the indicates when SSPxBUF has been loaded with the eight bits of data have been received, that byte is received data (transmission is complete). When the moved to the SSPxBUF register. Then, the Buffer Full SSPxBUF is read, the BF bit is cleared. This data may Detect bit, BF of the SSPxSTAT register, and the be irrelevant if the SPI is only a transmitter. Generally, interrupt flag bit, SSPIF, are set. This double-buffering the MSSP interrupt is used to determine when the of the received data (SSPxBUF) allows the next byte to transmission/reception has completed. If the interrupt start reception before reading the data that was just method is not going to be used, then software polling received. Any write to the SSPxBUF register during can be done to ensure that a write collision does not transmission/reception of data will be ignored and the occur. write collision detect bit, WCOL of the SSPxCON1 FIGURE 16-5: SPI MASTER/SLAVE CONNECTION SPI Master SSPxM<3:0> = 00xx SPI Slave SSPxM<3:0> = 010x = 1010 SDO SDI Serial Input Buffer Serial Input Buffer (SSPx) (SSPxBUF) SDI SDO Shift Register Shift Register (SSPxSR) (SSPxSR) MSb LSb MSb LSb Serial Clock SCK SCK Slave Select General I/O SS Processor 1 (optional) Processor 2 DS30000684B-page 208  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.2.3 SPI MASTER MODE The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register The master can initiate the data transfer at any time and the CKE bit of the SSPxSTAT register. This then, because it controls the SCK line. The master would give waveforms for SPI communication as determines when the slave (Processor 2, Figure16-5) shown in Figure16-6, Figure16-8 and Figure16-9, is to broadcast data by the software protocol. where the MSB is transmitted first. In Master mode, the In Master mode, the data is transmitted/received as SPI clock rate (bit rate) is user programmable to be one soon as the SSPxBUF register is written to. If the SPI of the following: is only going to receive, the SDO output could be dis- • FOSC/4 (or TCY) abled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDI pin • FOSC/16 (or 4 * TCY) at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY) received, it will be loaded into the SSPxBUF register as • Timer2 output/2 if a normal received byte (interrupts and Status bits • FOSC/(4 * (SSPxADD + 1)) appropriately set). Figure16-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. FIGURE 16-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF SSPxSR to SSPxBUF  2012-2014 Microchip Technology Inc. DS30000684B-page 209

PIC18(L)F2X/45K50 16.2.4 SPI SLAVE MODE 16.2.5 SLAVE SELECT SYNCHRONIZATION In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last The Slave Select can also be used to synchronize bit is latched, the SSPIF interrupt flag bit is set. communication. The Slave Select line is held high until the master device is ready to communicate. When the Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a new transmission is starting. be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. If the slave fails to receive the communication properly, While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the the external clock source on the SCK pin. This external Slave Select line returns to a high state. The slave is clock must meet the minimum high and low times as then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select specified in the electrical specifications. line is not used, there is a risk that the slave will even- While in Sleep mode, the slave can transmit/receive tually become out of sync with the master. If the slave data. The shift register is clocked from the SCK pin misses a bit, it will always be one bit off in future trans- input and when a byte is received, the device will gen- missions. Use of the Slave Select line allows the slave erate an interrupt. If enabled, the device will wake-up and master to align themselves at the beginning of from Sleep. each transmission. 16.2.4.1 Daisy-Chain Configuration The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled The SPI bus can sometimes be connected in a daisy- (SSPxCON1<3:0> = 0100). chain configuration. The first slave output is connected to the second slave input, the second slave output is When the SS pin is low, transmission and reception are connected to the third slave input, and so on. The final enabled and the SDO pin is driven. slave output is connected to the master input. Each When the SS pin goes high, the SDO pin is no longer slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down first group of clock pulses. The whole chain acts as resistors may be desirable depending on the applica- one large communication shift register. The daisy- tion. chain feature only requires a single Slave Select line Note 1: When the SPI is in Slave mode with SS pin from the master device. control enabled (SSPxCON1<3:0> = Figure16-7 shows the block diagram of a typical 0100), the SPI module will reset if the SS daisy-chain connection when operating in SPI mode. pin is set to VDD. In a daisy-chain configuration, only the most recent 2: When the SPI is used in Slave mode with byte on the bus is required by the slave. Setting the CKE set; the user must enable SS pin BOEN bit of the SSPxCON3 register will enable writes control. to the SSPxBUF register, even if the previous byte has 3: While operated in SPI Slave mode the not been read. This allows the software to ignore data SMP bit of the SSPxSTAT register must that may not apply to it. remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPxEN bit. DS30000684B-page 210  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 16-7: SPI DAISY-CHAIN CONNECTION SCLK SCLK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS SCLK SDI SPI Slave SDO #2 SS SCLK SDI SPI Slave SDO #3 SS FIGURE 16-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDO bit 7 bit 6 bit 7 bit 6 bit 0 SDI bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPxSR to SSPxBUF  2012-2014 Microchip Technology Inc. DS30000684B-page 211

PIC18(L)F2X/45K50 FIGURE 16-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE=0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSPIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 16-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSPIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active DS30000684B-page 212  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/ In SPI Master mode, module clocks may be operating reception will remain in that state until the device at a different speed than when in Full-Power mode; in wakes. After the device returns to Run mode, the the case of the Sleep mode, all clocks are halted. module will resume transmitting and receiving data. Special care must be taken by the user when the MSSP In SPI Slave mode, the SPI Transmit/Receive Shift clock is much faster than the system clock. register operates asynchronously to the device. This In Slave mode, when MSSP interrupts are enabled, allows the device to be placed in Sleep mode and data after the master completes sending data, an MSSP to be shifted into the SPI Transmit/Receive Shift interrupt will wake the controller from Sleep. register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will If an exit from Sleep mode is not desired, MSSP wake the device. interrupts should be disabled. TABLE 16-1: REGISTERS ASSOCIATED WITH SPI OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 147 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 SSP1BUF SSP1 Receive Buffer/Transmit Register — SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 252 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 255 SSP1STAT SMP CKE D/A P S R/W UA BF 251 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 Legend: Shaded bits are not used by the MSSP in SPI mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 213

PIC18(L)F2X/45K50 16.3 I2C Mode Overview FIGURE 16-11: I2C™ MASTER/ SLAVE CONNECTION The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master VDD devices initiate the communication. A slave device is controlled through addressing. SCL SCL The I2C bus specifies two signal connections: VDD • Serial Clock (SCL) Master Slave • Serial Data (SDA) SDA SDA Figure16-11 shows the block diagram of the MSSP module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal, supply voltage. Pulling the line to ground is considered which holds the SDA line low to indicate to the a logical zero and letting the line float is considered a transmitter that the slave device has received the logical one. transmitted data and is ready to receive more. Figure16-11 shows a typical connection between two The transition of data bits is always performed while the processors configured as master and slave devices. SCL line is held low. Transitions that occur while the The I2C bus can operate with one or more master SCL line is held high are used to indicate Start and Stop devices and one or more slave devices. bits. There are four potential modes of operation for a given If the master intends to write to the slave, then it device: repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this • Master Transmit mode example, the master device is in Master Transmit mode (master is transmitting data to a slave) and the slave is in Slave Receive mode. • Master Receive mode If the master intends to read from the slave, then it (master is receiving data from a slave) repeatedly receives a byte of data from the slave, and • Slave Transmit mode responds after each byte with an ACK bit. In this (slave is transmitting data to a master) example, the master device is in Master Receive mode • Slave Receive mode and the slave is Slave Transmit mode. (slave is receiving data from the master) On the last byte of data communicated, the master To begin communication, a master device starts out in device may end the transmission by sending a Stop bit. Master Transmit mode. The master device sends out a If the master device is in Receive mode, it sends the Start bit followed by the address byte of the slave it Stop bit in place of the last ACK bit. A Stop bit is intends to communicate with. This is followed by a sin- indicated by a low-to-high transition of the SDA line gle Read/Write bit, which determines whether the mas- while the SCL line is held high. ter intends to transmit to or receive data from the slave In some cases, the master may want to maintain con- device. trol of the bus and re-initiate another transmission. If If the requested slave exists on the bus, it will respond so, the master device may send another Start bit in with an Acknowledge bit, otherwise known as an ACK. place of the Stop bit or last ACK bit when it is in receive The master then continues in either Transmit mode or mode. Receive mode and the slave continues in the comple- The I2C bus specifies three message protocols; ment, either in Receive mode or Transmit mode, respectively. • Single message where a master writes data to a slave. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and • Single message where a master reads data from data bytes are sent out, Most Significant bit (MSb) first. a slave. The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a out as a logical zero when it intends to write data to the combination of writes and reads, to one or more slave. slaves. DS30000684B-page 214  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 When one device is transmitting a logical one, or letting 16.3.2 ARBITRATION the line float, and a second device is transmitting a Each master device must monitor the bus for Start and logical zero, or holding the line low, the first device can Stop bits. If the device detects that the bus is busy, it detect that the line is not a logical one. This detection, cannot begin a new message until the bus returns to an when used on the SCL line, is called clock stretching. Idle state. Clock stretching give slave devices a mechanism to control the flow of data. When this detection is used on However, two master devices may try to initiate a the SDA line, it is called arbitration. Arbitration ensures transmission on or about the same time. When this that there is only one master device communicating at occurs, the process of arbitration begins. Each any single time. transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first 16.3.1 CLOCK STRETCHING transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the When a slave device has not completed processing SDA line. data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device For example, if one transmitter holds the SDA line to a may hold the SCL clock line low after receiving or logical one (lets it float) and a second transmitter holds sending a bit, indicating that it is not yet ready to it to a logical zero (pulls it low), the result is that the continue. The master that is communicating with the SDA line will be low. The first transmitter then observes slave will attempt to raise the SCL line in order to that the level of the line is different than expected and transfer the next bit, but will detect that the clock line concludes that another transmitter is communicating. has not yet been released. Because the SCL The first transmitter to notice this difference is the one connection is open-drain, the slave has the ability to that loses arbitration and must stop driving the SDA hold that line low until it is ready to continue line. If this transmitter is also a master device, it also communicating. must stop driving the SCL line. It then can monitor the Clock stretching allows receivers that cannot keep up lines for a Stop condition before trying to reissue its with a transmitter to control the flow of incoming data. transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.  2012-2014 Microchip Technology Inc. DS30000684B-page 215

PIC18(L)F2X/45K50 16.4 I2C Mode Operation TABLE 16-2: I2C™ BUS TERMS All MSSP I2C communication is byte oriented and TERM Description shifted out MSb first. Six SFR registers and two Transmitter The device which shifts data out interrupt flags interface the module with the PIC onto the bus. microcontroller and user software. Two pins, SDA and Receiver The device which shifts data in SCL, are exercised by the module to communicate from the bus. with other external I2C devices. Master The device that initiates a transfer, generates clock signals and 16.4.1 BYTE FORMAT terminates a transfer. All communication in I2C is done in 9-bit segments. A Slave The device addressed by the byte is sent from a master to a slave or vice-versa, master. followed by an Acknowledge bit sent back. After the Multi-master A bus with more than one device 8th falling edge of the SCL line, the device outputting that can initiate data transfers. data on the SDA changes that pin to an input and Arbitration Procedure to ensure that only one reads in an acknowledge value on the next clock master at a time controls the bus. pulse. Winning arbitration ensures that The clock signal, SCL, is provided by the master. Data the message is not corrupted. is valid to change while the SCL signal is low, and Synchronization Procedure to synchronize the sampled on the rising edge of the clock. Changes on clocks of two or more devices on the SDA line while the SCL line is high define special the bus. conditions on the bus, explained below. Idle No master is controlling the bus, 16.4.2 DEFINITION OF I2C TERMINOLOGY and both SDA and SCL lines are high. There is language and terminology in the description Active Any time one or more master of I2C communication that have definitions specific to devices are controlling the bus. I2C. That word usage is defined below and may be Addressed Slave device that has received a used in the rest of this document without explana- Slave matching address and is actively tion. This table was adapted from the Phillips I2C being clocked by a master. specification. Matching Address byte that is clocked into a 16.4.3 SDA AND SCL PINS Address slave that matches the value stored in SSPxADD. Selection of any I2C mode with the SSPxEN bit set, Write Request Slave receives a matching forces the SCL and SDA pins to be open-drain. These address with R/W bit clear, and is pins should be set by the user to inputs by setting the ready to clock in data. appropriate TRIS bits. Read Request Master sends an address byte with Note: Data is tied to output zero when an I2C™ the R/W bit set, indicating that it mode is enabled. wishes to clock data out of the Slave. This data is the next and all 16.4.4 SDA HOLD TIME following bytes until a Restart or Stop. The hold time of the SDA pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time Clock Stretching When a device on the bus holds SDA is held valid after the falling edge of SCL. Setting SCL low to stall communication. the SDAHT bit selects a longer 300ns minimum hold Bus Collision Any time the SDA line is sampled time and may help on buses with large capacitance. low by the module while it is out- putting and expected high state. DS30000684B-page 216  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.4.5 START CONDITION 16.4.7 RESTART CONDITION The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid. transition of SDA from a high-to-low state while SCL A master can issue a Restart if it wishes to hold the line is high. A Start condition is always generated by bus after terminating the current transfer. A Restart the master and signifies the transition of the bus from has the same effect on the slave that a Start would, an Idle to an active state. Figure16-10 shows wave resetting all slave logic and preparing it to clock in an forms for Start and Stop conditions. address. The master may want to address the same or another slave. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it In 10-bit Addressing Slave mode a Restart is required low. This does not conform to the I2C specification that for the master to clock data out of the addressed slave. states no bus collision can occur on a Start. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a 16.4.6 STOP CONDITION Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to A Stop condition is a transition of the SDA line from a clock out data. low-to-high state while the SCL line is high. After a full match with R/W clear in 10-bit mode, a prior Note: At least one SCL low time must appear match flag is set and maintained. Until a Stop before a Stop is valid, therefore, if the SDA condition, a high address with R/W clear, or high line goes low then high again while the SCL address match fails. line stays high, only the Start condition is detected. 16.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 16-12: I2C™ START AND STOP CONDITIONS SDA SCL S P Change of Change of Data Allowed Data Allowed Start Stop Condition Condition FIGURE 16-13: I2C™ RESTART CONDITION Sr Change of Change of Data Allowed Data Allowed Restart Condition  2012-2014 Microchip Technology Inc. DS30000684B-page 217

PIC18(L)F2X/45K50 16.4.9 ACKNOWLEDGE SEQUENCE 16.5 I2C Slave Mode Operation The 9th SCL pulse for any transferred byte in I2C is The MSSP Slave mode operates in one of four modes dedicated as an Acknowledge. It allows receiving selected in the SSPxM bits of SSPxCON1 register. The devices to respond back to the transmitter by pulling modes can be divided into 7-bit and 10-bit Addressing the SDA line low. The transmitter must release control mode. 10-bit Addressing modes operate the same as of the line during this time to shift in the response. The 7-bit with some additional overhead for handling the Acknowledge (ACK) is an active-low signal, pulling the larger addresses. SDA line low indicated to the transmitter that the Modes with Start and Stop bit interrupts operated the device has received the transmitted data and is ready same as the other modes with SSPIF additionally get- to receive more. ting set upon detection of a Start, Restart, or Stop The result of an ACK is placed in the ACKSTAT bit of condition. the SSPxCON2 register. 16.5.1 SLAVE MODE ADDRESSES Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to The SSPxADD register (Register16-6) contains the the transmitter. The ACKDT bit of the SSPxCON2 Slave mode address. The first byte received after a register is set/cleared to determine the response. Start or Restart condition is compared against the Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the AHEN and DHEN bits of the SSPxCON3 register are value is loaded into the SSPxBUF register and an clear. interrupt is generated. If the value does not match, the module goes Idle and no indication is given to the There are certain conditions where an ACK will not be software that anything happened. sent by the slave. If the BF bit of the SSPxSTAT register or the SSPOV bit of the SSPxCON1 register The SSPx Mask register (Register16-5) affects the are set when a byte is received. address matching process. See Section16.5.9 “SSPx Mask Register” for more information. When the module is addressed, after the 8th falling edge of SCL on the bus, the ACKTIM bit of the SSPx- 16.5.1.1 I2C Slave 7-Bit Addressing Mode CON3 register is set. The ACKTIM bit indicates the In 7-bit Addressing mode, the LSb of the received data acknowledge time of the active bus. byte is ignored when determining if there is an address The ACKTIM Status bit is only active when the AHEN match. bit or DHEN bit is enabled. 16.5.1.2 I2C Slave 10-Bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPIF and UA are set, and SCL is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS30000684B-page 218  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.5.2 SLAVE RECEPTION 16.5.2.2 7-Bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte Slave device reception with AHEN and DHEN set is clear, the R/W bit of the SSPxSTAT register is operate the same as without these options with extra cleared. The received address is loaded into the interrupts and clock stretching added after the 8th fall- SSPxBUF register and acknowledged. ing edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the When the overflow condition exists for a received receive address or data byte, rather than the hard- address, then not Acknowledge is given. An overflow ware. This functionality adds support for PMBus™ that condition is defined as either bit BF of the SSPxSTAT was not present on previous versions of this module. register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modi- This list describes the steps that need to be taken by fies this operation. For more information see slave software to use these options for I2C Register16-4. communication. Figure16-15 displays a module using both address and data holding. Figure16-16 includes An MSSP interrupt is generated for each transferred the operation with the SEN bit of the SSPxCON2 data byte. Flag bit, SSPIF, must be cleared by software. register set. When the SEN bit of the SSPxCON2 register is set, 1. S bit of SSPxSTAT is set; SSPIF is set if interrupt SCL will be held low (clock stretch) following each on Start detect is enabled. received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except 2. Matching address with R/W bit clear is clocked sometimes in 10-bit mode. See Section16.2.3 “SPI in. SSPIF is set and CKP cleared after the 8th Master Mode” for more detail. falling edge of SCL. 3. Slave clears the SSPIF. 16.5.2.1 7-Bit Addressing Reception 4. Slave can look at the ACKTIM bit of the SSPx- This section describes a standard sequence of CON3 register to determine if the SSPIF was events for the MSSP module configured as an I2C after or before the ACK. slave in 7-bit Addressing mode. All decisions made 5. Slave reads the address value from SSPxBUF, by hardware or software and their effect on reception. clearing the BF flag. Figure16-13 and Figure16-14 is used as a visual 6. Slave sets ACK value clocked out to the master reference for this description. by setting ACKDT. This is a step by step process of what typically must 7. Slave releases the clock by setting CKP. be done to accomplish I2C communication. 8. SSPIF is set after an ACK, not after a NACK. 1. Start bit detected. 9. If SEN=1 the slave hardware will stretch the 2. S bit of SSPxSTAT is set; SSPIF is set if interrupt clock after the ACK. on Start detect is enabled. 10. Slave clears SSPIF. 3. Matching address with R/W bit clear is received. Note: SSPIF is still set after the 9th falling edge of 4. The slave pulls SDA low sending an ACK to the SCL even if there is no clock stretching and master, and sets SSPIF bit. BF has been cleared. Only if NACK is sent 5. Software clears the SSPIF bit. to master is SSPIF not set. 6. Software reads received address from 11. SSPIF set and CKP cleared after 8th falling SSPxBUF clearing the BF flag. edge of SCL for a received data byte. 7. If SEN=1; Slave software sets CKP bit to 12. Slave looks at ACKTIM bit of SSPxCON3 to release the SCL line. determine the source of the interrupt. 8. The master clocks out a data byte. 13. Slave reads the received data from SSPxBUF 9. Slave drives SDA low sending an ACK to the clearing BF. master, and sets SSPIF bit. 14. Steps 7-14 are the same for each received data 10. Software clears SSPIF. byte. 11. Software reads the received byte from 15. Communication is ended by either the slave SSPxBUF clearing BF. sending an ACK=1, or the master sending a Stop condition. If a Stop is sent and Interrupt on 12. Steps 8-12 are repeated for all received bytes Stop detect is disabled, the slave will only know from the master. by polling the P bit of the SSTSTAT register. 13. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes Idle.  2012-2014 Microchip Technology Inc. DS30000684B-page 219

PIC18(L)F2X/45K50 FIGURE 16-14: I2C™ SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=0, DHEN=0) s d Bus Master senStop condition 1 P SSPIF set on 9thfalling edge of SCL = K 9 C A D0 8 Master eceiving Data D4D3D2D1 4567 eared by software SSPOV set becauseSSPxBUF is still full. ACK is not sent. e to R D5 3 Cl From Slav D7D6K 12 First byte of data is available in SSPxBUF C 9 A D0 8 D1 7 ad e a D2 6 ware F is r Receiving Dat D5D4D3 345 Cleared by soft SSPxBU D6 2 D7 1 K 9 C A 8 A1 7 2 6 A s s dre A3 5 d A ng A4 4 vi ecei A5 3 R A6 2 A7 1 S V F O A L PI P D C S F S S S S B S DS30000684B-page 220  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 16-15: I2C™ SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) Bus Master sends Stop condition P SSPIF set on 9thfalling edge of SCL SCL is not heldlow becauseACK=1 K C 9 A D0 8 Receive Data D7D6D5D4D3D2D1 1234567 Cleared by software First byte of data is available in SSPxBUF SSPOV set becauseSSPxBUF is still full. ACK is not sent. CKP is written to ‘’ in software, 1releasing SCL N E S K AC 9 D0 8 ’1 o ‘ Data D2D1 67 KP is set t oftware, Receive D7D6D5D4D3 12345 Clock is held low until C Cleared by software SSPxBUF is read CKP is written to ‘’ in s1releasing SCL N E S K C A 9 0 = W R/ 8 A1 7 2 6 A s s dre A3 5 d e A A4 4 v ei ec A5 3 R 6 2 A A7 1 S V F O P SDA SCL SSPI BF SSP CK  2012-2014 Microchip Technology Inc. DS30000684B-page 221

PIC18(L)F2X/45K50 FIGURE 16-16: I2C™ SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=1) Master sendsStop condition =1 P No interruptafter not ACKfrom Slave CK 9 A are T to Received DataCKD7D6D5D4D3D2D1D0 912345678 Cleared by software a is read from SSPxBUF Slave softwsets ACKDnot ACK CKP set by software, SCL is released ACKTIM set by hardwareon 8th falling edge of SCL A at D D0 8 g Receiving Data D6D5D4D3D2D1 234567 SPIF is set on h falling edge of CL, after ACK When DHEN=:1CKP is cleared byhardware on 8th fallinedge of SCL KTIM cleared bydware in 9th ng edge of SCL D7 1 S9tS ACharrisi K 9 ce C n A e Au Dq ses SCK se aA eleor Master Rto slave f Receiving Address A6A5A4A3A2A1 2345678 If AHEN=:1SSPIF is set Address isread from SSBUF Slave softwareclears ACKDT to ACK the receivedbyte When AHEN=:1CKP is cleared by hardwareand SCL is stretched ACKTIM set by hardwareon 8th falling edge of SCL A7 1 S M SDA SCL SSPIF BF ACKDT CKP ACKTI S P DS30000684B-page 222  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 16-17: I2C™ SLAVE, 7-BIT ADDRESS, RECEPTION (SEN= 1, AHEN=1, DHEN=1) Master sendsStop condition P No interrupt afterif not ACKfrom Slave CKP is not clearedif not ACK K 9 C A D0 8 s d D1 7 enK Receive Data D6D5D4D3D2 23456 SSPxBUF can beread any time beforenext byte is loaded Slave snot AC Set by software,release SCL D7 1 K C 9 A D0 8 F e K sequence Receive Data D7D6D5D4D3D2D1 1245673 Cleared by software Received data isavailable on SSPxBU When DHEN = ;1on the 8th falling edgeof SCL of a receiveddata byte, CKP is cleared ACKTIM is cleared by hardwaron 9th rising edge of SCL C A ster releasesA to slave for ACK 9 aD MS 8 s R/W = 0 Receiving Address A6A5A4A3A2A1 342567 Received address is loaded into SSPxBUF Slave software clearACKDT to ACKthe received byte When AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared KTIM is set by hardware8th falling edge of SCL A7 1 ACon S M TI SDA SCL SPIF BF CKDT CKP ACK S P S A  2012-2014 Microchip Technology Inc. DS30000684B-page 223

PIC18(L)F2X/45K50 16.5.3 SLAVE TRANSMISSION 16.5.3.2 7-Bit Transmission When the R/W bit of the incoming address byte is set A master device can transmit a read request to a and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list SSPxSTAT register is set. The received address is below outlines what software for a slave will need to do loaded into the SSPxBUF register, and an ACK pulse is to accomplish a standard transmission. Figure16-17 sent by the slave on the ninth bit. can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and and the SCL pin is held low (see Section16.5.6 SCL. “Clock Stretching” for more detail). By stretching the 2. S bit of SSPxSTAT is set; SSPIF is set if interrupt clock, the master will be unable to assert another clock on Start detect is enabled. pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by data. the slave setting SSPIF bit. The transmit data must be loaded into the SSPxBUF 4. Slave hardware generates an ACK and sets register which also loads the SSPxSR register. Then SSPIF. the SCL pin should be released by setting the CKP bit 5. SSPIF bit is cleared by user. of the SSPxCON1 register. The eight data bits are 6. Software reads the received address from shifted out on the falling edge of the SCL input. This SSPxBUF, clearing BF. ensures that the SDA signal is valid during the SCL 7. R/W is set so CKP was automatically cleared high time. after the ACK. The ACK pulse from the master-receiver is latched on 8. The slave software loads the transmit data into the rising edge of the ninth SCL input pulse. This ACK SSPxBUF. value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data 9. CKP bit is set releasing SCL, allowing the mas- transfer is complete. In this case, when the not ACK is ter to clock the data out of the slave. latched by the slave, the slave goes Idle and waits for 10. SSPIF is set after the ACK response from the another occurrence of the Start bit. If the SDA line was master is loaded into the ACKSTAT register. low (ACK), the next transmit data must be loaded into 11. SSPIF bit is cleared. the SSPxBUF register. Again, the SCL pin must be 12. The slave software checks the ACKSTAT bit to released by setting bit CKP. see if the master wants to clock out more data. An MSSP interrupt is generated for each data transfer Note 1: If the master ACKs the clock will be byte. The SSPIF bit must be cleared by software and stretched. the SSPxSTAT register is used to determine the status 2: ACKSTAT is the only bit updated on the of the byte. The SSPIF bit is set on the falling edge of rising edge of SCL (9th) rather than the the ninth clock pulse. falling. 16.5.3.1 Slave Mode Bus Collision 13. Steps 9-13 are repeated for each transmitted A slave receives a Read request and begins shifting byte. data out on the SDA line. If a bus collision is detected 14. If the master sends a not ACK; the clock is not and the SBCDE bit of the SSPxCON3 register is set, held, but SSPIF is still set. the BCLIF bit of the PIRx register is set. Once a bus col- 15. The master sends a Restart condition or a Stop. lision is detected, the slave goes Idle and waits to be 16. The slave is no longer addressed. addressed again. User software can use the BCLIF bit to handle a slave bus collision. DS30000684B-page 224  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 16-18: I2C™ SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=0) sn do enditi er scon P stp ao MSt K C 9 A Transmitting Data D7D6D5D4D3D2D1D0 12345678 BF is automatically cleared after 8th fallingedge of SCL CKP is not held for not ACK Masters not ACKis copied to ACKSTAT c ati m o ut A K AC 9 D0 8 1 D 7 a Dat D2 6 F Transmitting D7D6D5D4D3 12345 Cleared by software Data to transmit isloaded into SSPxBU Set by software c ati m o ut A 1CK =A 9 W eceiving AddressR/A5A4A3A2A1 345678 Received addressis read from SSPxBUF When R/W is setSCL is alwaysheld low after 9th SCLfalling edge R/W is copied from the matching address byte Indicates an address has been received R 6 A 2 7 A 1 S T F TA SDA SCL SSPI BF CKP ACKS R/W D/A S P  2012-2014 Microchip Technology Inc. DS30000684B-page 225

PIC18(L)F2X/45K50 16.5.3.3 7-Bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure16-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. Bus starts Idle. 2. Master sends Start condition; the S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCL line the CKP bit is cleared and SSPIF interrupt is generated. 4. Slave software clears SSPIF. 5. Slave software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSPxCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPIF after the ACK if the R/W bit is set. 11. Slave software clears SSPIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS30000684B-page 226  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 16-19: I2C™ SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=1) endsdition sn aster op co P MSt K C A 9 0 D 8 Transmitting Data D6D5D4D3D2D1 234567 BF is automatically cleared after 8th fallingedge of SCL Master’s ACKresponse is copiedto SSPxSTAT CKP not cleared after not ACK 7 D 1 c ati m o AutK C A 9 D0 8 1 a D 7 at D 2 ence omaticTransmitting D7D6D5D4D3D 123456 Cleared by software Data to transmit isloaded into SSPxBUF Set by software,releases SCL KTIM is cleared9th rising edge of SCL DAequ Aut ACon Ss K Master releases to slave for ACK W=1AC 9 When R/W = ;1CKP is alwayscleared after ACK R/ 8 UF K Receiving Address A7A6A5A4A3A2A1 1234567 Received addressis read from SSPxB Slave clearsACKDT to ACaddress When AHEN = ;1CKP is cleared by hardwareafter receiving matchingaddress. ACKTIM is set on 8th fallingedge of SCL S SDA SCL SSPIF BF ACKDT KSTAT CKP CKTIM R/W D/A C A A  2012-2014 Microchip Technology Inc. DS30000684B-page 227

PIC18(L)F2X/45K50 16.5.4 SLAVE MODE 10-BIT ADDRESS 16.5.5 10-BIT ADDRESSING WITH ADDRESS RECEPTION OR DATA HOLD This section describes a standard sequence of Reception using 10-bit addressing with AHEN or events for the MSSP module configured as an I2C DHEN set is the same as with 7-bit modes. The only slave in 10-bit Addressing mode. difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the Figure16-19 and is used as a visual reference for this CKP bit is cleared and SCL line is held low are the description. same. Figure16-20 can be used as a reference of a This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set. slave software to accomplish I2C communication. Figure16-21 shows a standard waveform for a slave 1. Bus starts Idle. transmitter in 10-bit Addressing mode. 2. Master sends Start condition; S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. 4. Slave sends ACK and SSPIF is set. 5. Software clears the SSPIF bit. 6. Software reads received address from SSPxBUF clearing the BF flag. 7. Slave loads low address into SSPxADD, releasing SCL. 8. Master sends matching low address byte to the slave; UA bit is set. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPIF is set. Note: If the low address does not match, SSPIF and UA are still set so that the slave soft- ware can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCL pulse; SSPIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS30000684B-page 228  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 16-20: I2C™ SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) endsdition er scon P stp ao MSt K C 9 A 0 8 D ata D1 7 dBUF Receive D D6D5D4D3D2 23456 SCL is held lowwhile CKP = 0 Data is reafrom SSPx Set by software,releasing SCLyte D7 1 d b e v K cei Receive Data D6D5D4D3D2D1D0AC 92345678 Cleared by software Receive address isread from SSPxBUF When SEN = ;1CKP is cleared after9th falling edge of re D7 1 K C e A 9 Byt A0 8 DD s A es A1 7 Px Receive Second Addr A6A5A4A3A2 23456 Software updates SSand releases SCL A7 1 K C 9 ve First Address Byte A0A9A811 345678 Set by hardwareon 9th falling edge If address matchesSSPxADD it is loaded into SSPxBUF When UA = ;1SCL is held low ei 1 2 c e R 1 1 S A L F F A P D C PI B U K S S S C S  2012-2014 Microchip Technology Inc. DS30000684B-page 229

PIC18(L)F2X/45K50 FIGURE 16-21: I2C™ SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=0) a Receive Data D7D6D5 12 Received datis read from SSPxBUF K C 9 A D0 8 D1 7 s D,se Receive Data D6D5D4D3D2 23456 eared by software Update of SSPxADclears UA and releaSCL CKP with software ases SCL D7 1 Cl Set rele A U K C 9 A 0 A 8 Receive Second Address Byte A6A5A4A3A2A1 345672 ed by software SSPxBUF can beread anytime beforethe next received byte ate to SSPxADD isallowed until 9thng edge of SCL A7 1 Clear Updnot falli A U K C 9 A 0 = W 8 R/ e eive First Address Byte A9A8110 34567 Set by hardwareon 9th falling edge Slave software clearsACKDT to ACKthe received byte If when AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared ACKTIM is set by hardwaron 8th falling edge of SCL ec 1 2 R 1 1 S F T M SDA SCL SSPI BF ACKD UA CKP ACKTI DS30000684B-page 230  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 16-22: I2C™ SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN=0, AHEN=0, DHEN=0) ends dition er scon P MastStop K = 1 ds AC 9 en D0 8 K Master snot ACK Transmitting Data Byte D7D6D5D4D3D2D1 1723456 Data to transmit isloaded into SSPxBUF Set by softwarereleases SCL Masters not ACis copied K C A 9 e 8 aster sends estart event Receive First Address Byt A9A811110 1672345Sr Set by hardware Received address isread from SSPxBUF High address is loadedback into SSPxADD When R/W = ;1CKP is cleared on9th falling edge of SCL R/W is copied from thematching address byte MR K yte AC 9 s B A0 8 ed eiving Second Addres A6A5A4A3A2A1 672345 Cleared by software After SSPxADD isupdated, UA is clearand SCL is released c Re A7 1 K = 0 AC 9 W 8 Receiving AddressR/ A9A811110 1672345 Set by hardware SSPxBUF loadedwith received address UA indicates SSPxADDmust be updated Indicates an addresshas been received S AT T S SDA SCL SPIF BF UA CKP ACK R/W D/A S  2012-2014 Microchip Technology Inc. DS30000684B-page 231

PIC18(L)F2X/45K50 16.5.6 CLOCK STRETCHING 16.5.6.2 10-Bit Addressing Mode Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set, the holds the SCL line low effectively pausing communica- clock is always stretched. This is the only time the SCL tion. The slave may stretch the clock to allow more is stretched without CKP being cleared. SCL is time to handle data or prepare a response for the mas- released immediately after a write to SSPxADD. ter device. A master device is not concerned with Note: Previous versions of the module did not stretching as anytime it is active on the bus and not stretch the clock if the second address byte transferring data it is stretching. Any stretching done did not match. by a slave is invisible to the master software and han- dled by the hardware that generates SCL. 16.5.6.3 Byte NACKing The CKP bit of the SSPxCON1 register is used to When the AHEN bit of SSPxCON3 is set; CKP is control stretching in software. Any time the CKP bit is cleared by hardware after the 8th falling edge of SCL cleared, the module will wait for the SCL line to go low for a received matching address byte. When the and then hold it. Setting CKP will release SCL and DHEN bit of SSPxCON3 is set; CKP is cleared after allow more communication. the 8th falling edge of SCL for received data. 16.5.6.1 Normal Clock Stretching Stretching after the 8th falling edge of SCL allows the Following an ACK if the R/W bit of SSPxSTAT is set, a slave to look at the received address or data and read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data. allows the slave time to update SSPxBUF with data to 16.5.7 CLOCK SYNCHRONIZATION AND transfer to the master. If the SEN bit of SSPxCON2 is THE CKP BIT set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait is set by software and communication resumes. for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low Note 1: The BF bit has no effect on whether the until the SCL output is already sampled low. There- clock will be stretched or not. This is fore, the CKP bit will not assert the SCL line until an different than previous versions of the external I2C master device has already asserted the module that would not stretch the clock, SCL line. The SCL output will remain low until the CKP clear CKP, if SSPxBUF was read before bit is set and all other devices on the I2C bus have the 9th falling edge of SCL. released SCL. This ensures that a write to the CKP bit 2: Previous versions of the module did not will not violate the minimum high time requirement for stretch the clock for a transmission if SCL (see Figure16-22). SSPxBUF was loaded before the 9th fall- ing edge of SCL. It is now always cleared for read requests. FIGURE 16-23: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX ‚ – 1 SCL Master device CKP asserts clock Master device releases clock WR SSPxCON1 DS30000684B-page 232  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave The addressing procedure for the I2C bus is such that will prepare to receive the second byte as data, just as the first byte after the Start condition usually it would in 7-bit mode. determines which device will be the slave addressed If the AHEN bit of the SSPxCON3 register is set, just by the master device. The exception is the general call as with any other address reception, the slave address which can address all devices. When this hardware will stretch the clock after the 8th falling address is used, all devices should, in theory, respond edge of SCL. The slave must then set its ACKDT with an acknowledge. value and release the clock with communication The general call address is a reserved address in the progressing as it would normally. I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave soft- ware can read SSPxBUF and respond. Figure16-23 shows a general call reception sequence. FIGURE 16-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPxSTAT<0>) Cleared by software SSPxBUF is read GCEN (SSPxCON2<7>) ’1’ 16.5.9 SSPx MASK REGISTER An SSPx Mask (SSPxMSK) register (Register16-5) is available in I2C Slave mode as a mask for the value held in the SSPxSR register during an address comparison operation. A zero (‘0’) bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSPx operation until written with a mask value. The SSPx Mask register is active during: • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSPx mask has no effect during the reception of the first (high) byte of the address.  2012-2014 Microchip Technology Inc. DS30000684B-page 233

PIC18(L)F2X/45K50 16.6 I2C Master Mode 16.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the The master device generates all of the serial clock appropriate SSPxM bits in the SSPxCON1 register and pulses and the Start and Stop conditions. A transfer is by setting the SSPxEN bit. In Master mode, the SCL ended with a Stop condition or with a Repeated Start and SDA lines are set as inputs and are manipulated by condition. Since the Repeated Start condition is also the MSSP hardware. the beginning of the next serial transfer, the I2C bus will not be released. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop con- In Master Transmitter mode, serial data is output ditions. The Stop (P) and Start (S) bits are cleared from through SDA, while SCL outputs the serial clock. The a Reset or when the MSSP module is disabled. Control first byte transmitted contains the slave address of the of the I2C bus may be taken when the P bit is set, or the receiving device (7 bits) and the Read/Write (R/W) bit. bus is Idle. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is trans- In Firmware Controlled Master mode, user code mitted, an Acknowledge bit is received. Start and Stop conducts all I2C bus operations based on Start and conditions are output to indicate the beginning and the Stop bit condition detection. Start and Stop condition end of a serial transfer. detection is the only active circuitry in this mode. All other communication is done by the user software In Master Receive mode, the first byte transmitted con- directly manipulating the SDA and SCL lines. tains the slave address of the transmitting device (7bits) and the R/W bit. In this case, the R/W bit will be The following events will cause the SSPx Interrupt Flag logic ‘1’. Thus, the first byte transmitted is a 7-bit slave bit, SSPIF, to be set (SSPx interrupt, if enabled): address followed by a ‘1’ to indicate the receive bit. • Start condition detected Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. • Stop condition detected After each byte is received, an Acknowledge bit is • Data transfer byte transmitted/received transmitted. Start and Stop conditions indicate the • Acknowledge transmitted/received beginning and end of transmission. • Repeated Start generated A Baud Rate Generator is used to set the clock Note 1: The MSSP module, when configured in frequency output on SCL. See Section16.7 “Baud I2C Master mode, does not allow queuing Rate Generator” for more detail. of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. DS30000684B-page 234  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Gen- erator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sam- pled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure16-25). FIGURE 16-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX ‚ – 1 SCL deasserted but slave holds SCLSCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload 16.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not Idle. Note: Because queuing of events is not allowed, writing to the lower five bits of SSPxCON2 is disabled until the Start condition is complete.  2012-2014 Microchip Technology Inc. DS30000684B-page 235

PIC18(L)F2X/45K50 16.6.4 I2C MASTER MODE START CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN, of the SSPxCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Gen- erator is reloaded with the contents of SSPxADD<7:0> and resumes its count. When the Baud Rate Genera- tor times out (TBRG), the SEN bit of the SSPxCON2 register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sam- pled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start. FIGURE 16-26: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPxSTAT<3>) At completion of Start bit, SDA = 1, hardware clears SEN bit SCL = 1 and sets SSPIF bit TBRG TBRG Write to SSPxBUF occurs here SDA 1st bit 2nd bit TBRG SCL S TBRG DS30000684B-page 236  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit of the SSPxCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA=0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the SSPx- CON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPxSTAT register will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. Note1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. FIGURE 16-27: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here At completion of Start bit, SDA = 1, SDA = 1, hardware clears RSEN bit SCL (no change) SCL = 1 and sets SSPIF TBRG TBRG TBRG SDA 1st bit Write to SSPxBUF occurs here TBRG SCL Sr TBRG Repeated Start  2012-2014 Microchip Technology Inc. DS30000684B-page 237

PIC18(L)F2X/45K50 16.6.6 I2C MASTER MODE TRANSMISSION 16.6.6.3 ACKSTAT Status Flag Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit of the SSPxCON2 other half of a 10-bit address is accomplished by simply register is cleared when the slave has sent an writing a value to the SSPxBUF register. This action will Acknowledge (ACK=0) and is set when the slave set the Buffer Full flag bit, BF, and allow the Baud Rate does not Acknowledge (ACK=1). A slave sends an Generator to begin counting and start the next trans- Acknowledge when it has recognized its address (including a general call), or when the slave has mission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is properly received its data. asserted. SCL is held low for one Baud Rate Generator 16.6.6.4 Typical Transmit Sequence: rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it 1. The user generates a Start condition by setting is held that way for TBRG. The data on the SDA pin the SEN bit of the SSPxCON2 register. must remain stable for that duration and some hold 2. SSPIF is set by hardware on completion of the time after the next falling edge of SCL. After the eighth Start. bit is shifted out (the falling edge of the eighth clock), 3. SSPIF is cleared by software. the BF flag is cleared and the master releases SDA. 4. The MSSP module will wait the required start This allows the slave device being addressed to time before any other operation takes place. respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received prop- 5. The user loads the SSPxBUF with the slave erly. The status of ACK is written into the ACKSTAT bit address to transmit. on the rising edge of the ninth clock. If the master 6. Address is shifted out the SDA pin until all eight receives an Acknowledge, the Acknowledge Status bit, bits are transmitted. Transmission begins as ACKSTAT, is cleared. If not, the bit is set. After the ninth soon as SSPxBUF is written to. clock, the SSPIF bit is set and the master clock (Baud 7. The MSSP module shifts in the ACK bit from the Rate Generator) is suspended until the next data byte slave device and writes its value into the is loaded into the SSPxBUF, leaving SCL low and SDA ACKSTAT bit of the SSPxCON2 register. unchanged (Figure16-27). 8. The MSSP module generates an interrupt at the After the write to the SSPxBUF, each bit of the address end of the ninth clock cycle by setting the SSPIF will be shifted out on the falling edge of SCL until all bit. seven address bits and the R/W bit are completed. On 9. The user loads the SSPxBUF with eight bits of the falling edge of the eighth clock, the master will data. release the SDA pin, allowing the slave to respond with 10. Data is shifted out the SDA pin until all eight bits an Acknowledge. On the falling edge of the ninth clock, are transmitted. the master will sample the SDA pin to see if the address 11. The MSSP module shifts in the ACK bit from the was recognized by a slave. The status of the ACK bit is slave device and writes its value into the loaded into the ACKSTAT Status bit of the SSPxCON2 ACKSTAT bit of the SSPxCON2 register. register. Following the falling edge of the ninth clock 12. Steps 8-11 are repeated for all transmitted data transmission of the address, the SSPIF is set, the BF bytes. flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, 13. The user generates a Stop or Restart condition holding SCL low and allowing SDA to float. by setting the PEN or RSEN bits of the SSPx- CON2 register. Interrupt is generated once the 16.6.6.1 BF Status Flag Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted out. 16.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. DS30000684B-page 238  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 16-28: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e ACKSTAT in SSPxCON2 = P ared by softwar K e C 9 Cl A > 6 2< D0 8 e N n slave, clear ACKSTAT bit SSPxCO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared by software service routifrom SSPx interrupt SSPxBUF is written by software From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to CK re = 0 A W 9 are R/W A1 ess and R/ 78 d by hardw ave A2 addr 6 eare PxCON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPxBUF written with 7-bit start transmit 12345 Cleared by software SSPxBUF written After Start condition, SEN cl Sn Write SStart co S T<0>) A T S x P SDA SCL SSPIF BF (SS SEN PEN R/W  2012-2014 Microchip Technology Inc. DS30000684B-page 239

PIC18(L)F2X/45K50 16.6.7 I2C MASTER MODE RECEPTION 16.6.7.4 Typical Receive Sequence: Master mode reception is enabled by programming the 1. The user generates a Start condition by setting Receive Enable bit, RCEN, of the SSPxCON2 register. the SEN bit of the SSPxCON2 register. Note: The MSSP module must be in an Idle 2. SSPIF is set by hardware on completion of the state before the RCEN bit is set or the Start. RCEN bit will be disregarded. 3. SSPIF is cleared by software. The Baud Rate Generator begins counting and on each 4. User writes SSPxBUF with the slave address to rollover, the state of the SCL pin changes (high-to-low/ transmit and the R/W bit set. low-to-high) and data is shifted into the SSPxSR. After 5. Address is shifted out the SDA pin until all eight the falling edge of the eighth clock, the receive enable bits are transmitted. Transmission begins as flag is automatically cleared, the contents of the soon as SSPxBUF is written to. SSPxSR are loaded into the SSPxBUF, the BF flag bit 6. The MSSP module shifts in the ACK bit from the is set, the SSPIF flag bit is set and the Baud Rate Gen- slave device and writes its value into the erator is suspended from counting, holding SCL low. ACKSTAT bit of the SSPxCON2 register. The MSSP is now in Idle state awaiting the next com- 7. The MSSP module generates an interrupt at the mand. When the buffer is read by the CPU, the BF flag end of the ninth clock cycle by setting the SSPIF bit is automatically cleared. The user can then send an bit. Acknowledge bit at the end of reception by setting the 8. User sets the RCEN bit of the SSPxCON2 regis- Acknowledge Sequence Enable bit, ACKEN, of the ter and the Master clocks in a byte from the slave. SSPxCON2 register. 9. After the 8th falling edge of SCL, SSPIF and BF 16.6.7.1 BF Status Flag are set. 10. Master clears SSPIF and reads the received In receive operation, the BF bit is set when an address byte from SSPxUF, clears BF. or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read. 11. Master sets ACK value sent to slave in ACKDT bit of the SSPxCON2 register and initiates the 16.6.7.2 SSPOV Status Flag ACK by setting the ACKEN bit. In receive operation, the SSPOV bit is set when eight 12. Masters ACK is clocked out to the slave and bits are received into the SSPxSR and the BF flag bit is SSPIF is set. already set from a previous reception. 13. User clears SSPIF. 14. Steps 8-13 are repeated for each received byte 16.6.7.3 WCOL Status Flag from the slave. If the user writes the SSPxBUF when a receive is 15. Master sends a not ACK or Stop to end already in progress (i.e., SSPxSR is still shifting in a communication. data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). DS30000684B-page 240  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 16-29: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPxCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPxCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from MasterMaster configured as a receiverSDA = ACKDT = SDA = ACKDT = 10by programming SSPxCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten hereom Slavenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1ACKD0W ACK Bus masterACK is not sentterminatestransfer9967895876512343124PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared by softwareCleared by softwareCleared by software(SSPxSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPxSR andcontents are unloaded into SSPxBUF SSPOV is set becauseSSPxBUF is still full Master configured as a receiverRCEN clearedACK from MasterRCEN clearedSDA = ACKDT = automatically0by programming SSPxCON2<3> (RCEN = )automatically1 K fr R/ 8 AC A1 7 e, Write to SSPxCON2<0>(SEN = ),1begin Start condition SEN = 0Write to SSPxBUF occurs herstart XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 631245SCLS SSPIF Cleared by softwareSDA = , SCL = 01while CPU responds to SSPIF BF (SSPxSTAT<0>) SSPOV ACKEN RCEN  2012-2014 Microchip Technology Inc. DS30000684B-page 241

PIC18(L)F2X/45K50 16.6.8 ACKNOWLEDGE SEQUENCE 16.6.9 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN, of the bit, PEN, of the SSPxCON2 register. At the end of a SSPxCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDA pin. If the user wishes to gen- the master will assert the SDA line low. When the SDA erate an Acknowledge, then the ACKDT bit should be line is sampled low, the Baud Rate Generator is cleared. If not, the user should set the ACKDT bit before reloaded and counts down to ‘0’. When the Baud Rate starting an Acknowledge sequence. The Baud Rate Generator times out, the SCL pin will be brought high Generator then counts for one rollover period (TBRG) and one TBRG (Baud Rate Generator rollover count) and the SCL pin is deasserted (pulled high). When the later, the SDA pin will be deasserted. When the SDA SCL pin is sampled high (clock arbitration), the Baud pin is sampled high while SCL is high, the P bit of the Rate Generator counts for TBRG. The SCL pin is then SSPxSTAT register is set. A TBRG later, the PEN bit is pulled low. Following this, the ACKEN bit is automatically cleared and the SSPIF bit is set (Figure16-30). cleared, the Baud Rate Generator is turned off and the 16.6.9.1 WCOL Status Flag MSSP module then goes into Idle mode (Figure16-29). If the user writes the SSPxBUF when a Stop sequence 16.6.8.1 WCOL Status Flag is in progress, then the WCOL bit is set and the If the user writes the SSPxBUF when an Acknowledge contents of the buffer are unchanged (the write does sequence is in progress, then WCOL is set and the not occur). contents of the buffer are unchanged (the write does not occur). FIGURE 16-30: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPxCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in SSPIF set at Cleared in software the end of receive software SSPIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 16-31: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPxCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPxSTAT<4>) is set. Falling edge of PEN bit (SSPxCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. DS30000684B-page 242  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.6.10 SLEEP OPERATION 16.6.12 MULTI-MASTER MODE While in Sleep mode, the I2C slave module can receive In Multi-Master mode, the interrupt generation on the addresses or data and when an address match or detection of the Start and Stop conditions allows the complete byte transfer occurs, wake the processor determination of when the bus is free. The Stop (P) and from Sleep (if the MSSP interrupt is enabled). Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus may 16.6.11 EFFECTS OF A RESET be taken when the P bit of the SSPxSTAT register is A Reset disables the MSSP module and terminates the set, or the bus is Idle, with both the S and P bits clear. current transfer. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: • Address Transfer • Data Transfer • A Start Condition • A Repeated Start Condition • An Acknowledge Condition  2012-2014 Microchip Technology Inc. DS30000684B-page 243

PIC18(L)F2X/45K50 16.6.13 MULTI -MASTER COMMUNICATION, If a Start, Repeated Start, Stop or Acknowledge BUS COLLISION AND BUS condition was in progress when the bus collision ARBITRATION occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in Multi-Master mode support is achieved by bus the SSPxCON2 register are cleared. When the user arbitration. When the master outputs address/data bits services the bus collision Interrupt Service Routine and onto the SDA pin, arbitration takes place when the if the I2C bus is free, the user can resume master outputs a ‘1’ on SDA, by letting SDA float high communication by asserting a Start condition. and another master asserts a ‘0’. When the SCL pin The master will continue to monitor the SDA and SCL floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is pins. If a Stop condition occurs, the SSPIF bit will be set. ‘0’, then a bus collision has taken place. The master will A write to the SSPxBUF will start the transmission of set the Bus Collision Interrupt Flag, BCLIF, and reset data at the first data bit, regardless of where the the I2C port to its Idle state (Figure16-31). transmitter left off when the bus collision occurred. If a transmit was in progress when the bus collision In Multi-Master mode, the interrupt generation on the occurred, the transmission is halted, the BF flag is detection of Start and Stop conditions allows the cleared, the SDA and SCL lines are deasserted and the determination of when the bus is free. Control of the I2C SSPxBUF can be written to. When the user services bus can be taken when the P bit is set in the SSPxSTAT the bus collision Interrupt Service Routine and if the I2C register, or the bus is Idle and the S and P bits are bus is free, the user can resume communication by cleared. asserting a Start condition. FIGURE 16-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data does not match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF DS30000684B-page 244  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.6.13.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure16-34). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure16-32). counts down to zero; if the SCL pin is sampled as ‘0’ b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the (Figure16-33). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a pins are monitored. factor during a Start condition is that no two bus masters can assert a Start condi- If the SDA pin is already low, or the SCL pin is already tion at the exact same time. Therefore, low, then all of the following occur: one master will always assert SDA before • the Start condition is aborted, the other. This condition does not cause a • the BCLIF flag is set and bus collision because the two masters • the MSSP module is reset to its Idle state must be allowed to arbitrate the first (Figure16-32). address following the Start condition. If the The Start condition begins with the SDA and SCL pins address is the same, arbitration must be deasserted. When the SDA pin is sampled high, the allowed to continue into the data portion, Baud Rate Generator is loaded and counts down. If the Repeated Start or Stop conditions. SCL pin is sampled low while SDA is high, a bus colli- sion occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 16-33: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSPx module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared by software S SSPIF SSPIF and BCLIF are cleared by software  2012-2014 Microchip Technology Inc. DS30000684B-page 245

PIC18(L)F2X/45K50 FIGURE 16-34: BUS COLLISION DURING START CONDITION (SCL=0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared by software S ’0’ ’0’ SSPIF ’0’ ’0’ FIGURE 16-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCLIF ’0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF by software DS30000684B-page 246  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.6.13.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure16-35). If SDA is sampled high, the BRG is reloaded and begins During a Repeated Start condition, a bus collision counting. If SDA goes from high-to-low before the BRG occurs if: times out, no bus collision occurs because no two a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time. from low level to high level. If SCL goes from high-to-low before the BRG times out b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision indicating that another master is attempting to occurs. In this case, another master is attempting to transmit a data ‘1’. transmit a data ‘1’ during the Repeated Start condition, When the user releases SDA and the pin is allowed to see Figure16-36. float high, the BRG is loaded with SSPxADD and If, at the end of the BRG time-out, both SCL and SDA counts down to zero. The SCL pin is then deasserted are still high, the SDA pin is driven low and the BRG is and when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 16-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared by software S ’0’ SSPIF ’0’ FIGURE 16-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared by software RSEN ’0’ S SSPIF  2012-2014 Microchip Technology Inc. DS30000684B-page 247

PIC18(L)F2X/45K50 16.6.13.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPxADD and a) After the SDA pin has been deasserted and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure16-37). If the SCL pin is sampled low before SDA goes high. low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure16-38). FIGURE 16-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ’0’ SSPIF ’0’ FIGURE 16-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ’0’ SSPIF ’0’ DS30000684B-page 248  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 16-3: REGISTERS ASSOCIATED WITH I2C™ OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 SSP1ADD SSP1 Address Register in I2C™ Slave Mode. SSP1 Baud Rate Reload Register in I2C Master mode. 257 SSP1BUF SSP1 Receive Buffer/Transmit Register — SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 252 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 254 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 255 SSP1MSK SSP1 MASK Register bits 256 SSP1STAT SMP CKE D/A P S R/W UA BF 251 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 Legend: Shaded bits are not used by the MSSP in I2C mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 249

PIC18(L)F2X/45K50 16.7 Baud Rate Generator Table16-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into The MSSP module has a Baud Rate Generator avail- SSPxADD. able for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value EQUATION 16-1: is placed in the SSPxADD register (Register16-6). When a write occurs to SSPxBUF, the Baud Rate Gen- FOSC erator will automatically begin counting down. FCLOCK = ------------------------------------------------- SSPxADD+14 Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. An internal signal “Reload” in Figure16-39 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. FIGURE 16-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPxM<3:0> SSPxADD<7:0> SSPxM<3:0> Reload Reload SCL Control SSPxCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C™. This is an implementa- tion limitation. TABLE 16-4: MSSP CLOCK RATE W/BRG FCLOCK FOSC FCY BRG Value (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz(1) 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. DS30000684B-page 250  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 16.8 Register Definitions: MSSP Control REGISTER 16-1: SSPxSTAT: SSPx STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I 2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I 2 C™ mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C™ mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPxEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPxEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I 2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty  2012-2014 Microchip Technology Inc. DS30000684B-page 251

PIC18(L)F2X/45K50 REGISTER 16-2: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0 R/C/HS-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPxBUF register was attempted while the I2C™ conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new recep- tion (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software). 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I 2 C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C Master mode: Unused in this mode DS30000684B-page 252  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 16-2: SSPxCON1: SSPx CONTROL REGISTER 1 (CONTINUED) bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPxADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1)) 1011 = I2C firmware controlled Master mode (slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: When enabled, the SDA and SCL pins must be configured as inputs. 4: SSPxADD values of 0, 1 or 2 are not supported for I2C mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 253

PIC18(L)F2X/45K50 REGISTER 16-3: SSPxCON2: SSPx CONTROL REGISTER 2 R/W-0 R-0 R/W-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/W/HC-0 GCEN ACKSTAT ACKDT ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C™ Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN(1): Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN(1): Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN(1): Stop Condition Enable bit (in I2C Master mode only) SCK Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN(1): Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN(1): Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). DS30000684B-page 254  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 16-4: SSPxCON3: SSPx CONTROL REGISTER 3 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C™ mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the SSPxCON1 register is set, and the buffer is not updated In I2C Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPxBUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSPx- CON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF=1, but hardware continues to write the most recent byte to SSPxBUF. 2: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as enabled. 3: The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set.  2012-2014 Microchip Technology Inc. DS30000684B-page 255

PIC18(L)F2X/45K50 REGISTER 16-4: SSPxCON3: SSPx CONTROL REGISTER 3 (CONTINUED) bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCL is held low. 0 = Data holding is disabled Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF=1, but hardware continues to write the most recent byte to SSPxBUF. 2: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as enabled. 3: The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set. REGISTER 16-5: SSPxMSK: SSPx MASK REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD<n> to detect I2C™ address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPxM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored DS30000684B-page 256  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 16-6: SSPxADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C™ specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode — Least Significant Address byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.  2012-2014 Microchip Technology Inc. DS30000684B-page 257

PIC18(L)F2X/45K50 17.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer • Half-duplex synchronous master independent of device program execution. The • Half-duplex synchronous slave EUSART, also known as a Serial Communications • Programmable clock and data polarity Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous The EUSART module implements the following system. Full-Duplex mode is useful for additional features, making it ideally suited for use in communications with peripheral systems, such as CRT Local Interconnect Network (LIN) bus systems: terminals and personal computers. Half-Duplex • Automatic detection and calibration of the baud rate Synchronous mode is intended for communications • Wake-up on Break reception with peripheral devices, such as A/D or D/A integrated • 13-bit Break character transmit circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for Block diagrams of the EUSART transmitter and baud rate generation and require the external clock receiver are shown in Figure17-1 and Figure17-2. signal provided by a master synchronous device. FIGURE 17-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREGx Register TXIF 8 MSb LSb TX/CK pin (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT Baud Rate Generator FOSC ÷ n TX9 BRG16 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 X 0 0 0 SPBRGHx SPBRGx BRGH X 1 1 0 0 BRG16 X 1 0 1 0 DS30000684B-page 258  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 17-2: EUSART RECEIVE BLOCK DIAGRAM CREN OERR RCIDL RX/DT pin MSb RSR Register LSb Panind BCuoffnetrrol DReactaovery Stop (8) 7 • • • 1 0 START Baud Rate Generator FOSC RX9 ÷ n BRG16 n + 1 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 FIFO SPBRGHx SPBRGx BRGH X 1 1 0 0 FERR RX9D RCREGx Register BRG16 X 1 0 1 0 8 Data Bus RCIF Interrupt RCIE The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTAx) • Receive Status and Control (RCSTAx) • Baud Rate Control (BAUDCONx) These registers are detailed in Register17-1, Register17-2 and Register17-3, respectively. For all modes of EUSART operation, the TRIS control bits corresponding to the RX/DT and TX/CK pins should be set to ‘1’. The EUSART control will automatically reconfigure the pin from input to output, as needed. When the receiver or transmitter section is not enabled then the corresponding RX/DT or TX/CK pin may be used for general purpose input and output.  2012-2014 Microchip Technology Inc. DS30000684B-page 259

PIC18(L)F2X/45K50 17.1 EUSART Asynchronous Mode 17.1.1.2 Transmitting Data The EUSART transmits and receives data using the A transmission is initiated by writing a character to the standard non-return-to-zero (NRZ) format. NRZ is TXREGx register. If this is the first character, or the implemented with two levels: a VOH mark state which previous character has been completely flushed from represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXREGx is immediately represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains consecutively transmitted data bits of the same value all or part of a previous character, the new character stay at the output level of that bit without returning to a data is held in the TXREGx until the Stop bit of the neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending transmission port idles in the mark state. Each character character in the TXREGx is then transferred to the TSR transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits or nine data bits and is always terminated by one or and Stop bit sequence commences immediately more Stop bits. The Start bit is always a space and the following the transfer of the data to the TSR from the Stop bits are always marks. The most common data TXREGx. format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud 17.1.1.3 Transmit Data Polarity Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table17-5 The polarity of the transmit data can be controlled with for examples of baud rate configurations. the TXCKP bit of the BAUDCONx register. The default state of this bit is ‘0’ which selects high true transmit The EUSART transmits and receives the LSb first. The idle and data bits. Setting the TXCKP bit to ‘1’ will invert EUSART’s transmitter and receiver are functionally the transmit data resulting in low true idle and data bits. independent, but share the same data format and baud The TXCKP bit controls transmit data polarity only in rate. Parity is not supported by the hardware, but can Asynchronous mode. In Synchronous mode the be implemented in software and stored as the ninth TXCKP bit has a different function. data bit. 17.1.1.4 Transmit Interrupt Flag 17.1.1 EUSART ASYNCHRONOUS TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no The EUSART transmitter block diagram is shown in character is being held for transmission in the TXREGx. Figure17-1. The heart of the transmitter is the serial In other words, the TXIF bit is only clear when the TSR Transmit Shift Register (TSR), which is not directly is busy with a character and a new character has been accessible by software. The TSR obtains its data from queued for transmission in the TXREGx. The TXIF flag the transmit buffer, which is the TXREGx register. bit is not cleared immediately upon writing TXREGx. 17.1.1.1 Enabling the Transmitter TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately The EUSART transmitter is enabled for asynchronous following the TXREGx write will return invalid results. operations by configuring the following three control The TXIF bit is read-only, it cannot be set or cleared by bits: software. • TXEN = 1 The TXIF interrupt can be enabled by setting the TXIE • SYNC = 0 interrupt enable bit of the PIE1 register. However, the • SPEN = 1 TXIF flag bit will be set whenever the TXREGx is empty, regardless of the state of TXIE enable bit. All other EUSART control bits are assumed to be in their default state. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the Setting the TXEN bit of the TXSTAx register enables the TXIE interrupt enable bit upon writing the last character transmitter circuitry of the EUSART. Clearing the SYNC of the transmission to the TXREGx. bit of the TXSTAx register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTAx register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: The TXIF transmitter interrupt flag is set when the TXEN enable bit is set. DS30000684B-page 260  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 17.1.1.5 TSR Status 17.1.1.7 Asynchronous Transmission Setup The TRMT bit of the TXSTAx register indicates the 1. Initialize the SPBRGHx:SPBRGx register pair status of the TSR register. This is a read-only bit. The and the BRGH and BRG16 bits to achieve the TRMT bit is set when the TSR register is empty and is desired baud rate (see Section17.4 “EUSART cleared when a character is transferred to the TSR Baud Rate Generator (BRG)”). register from the TXREGx. The TRMT bit remains clear 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. until all bits have been shifted out of the TSR register. 3. Enable the asynchronous serial port by clearing No interrupt logic is tied to this bit, so the user needs to the SYNC bit and setting the SPEN bit. poll this bit to determine the TSR status. 4. If 9-bit transmission is desired, set the TX9 Note: The TSR register is not mapped in data control bit. A set ninth data bit will indicate that memory, so it is not available to the user. the eight Least Significant data bits are an address when the receiver is set for address 17.1.1.6 Transmitting 9-Bit Characters detection. The EUSART supports 9-bit character transmissions. 5. Set the TXCKP control bit if inverted transmit When the TX9 bit of the TXSTAx register is set the data polarity is desired. EUSART will shift 9 bits out for each character transmit- 6. Enable the transmission by setting the TXEN ted. The TX9D bit of the TXSTAx register is the ninth, control bit. This will cause the TXIF interrupt bit and Most Significant, data bit. When transmitting 9-bit to be set. data, the TX9D data bit must be written before writing 7. If interrupts are desired, set the TXIE interrupt the 8 Least Significant bits into the TXREGx. All nine enable bit. An interrupt will occur immediately bits of data will be transferred to the TSR shift register provided that the GIE/GIEH and PEIE/GIEL bits immediately after the TXREGx is written. of the INTCON register are also set. A special 9-bit Address mode is available for use with 8. If 9-bit transmission is selected, the ninth bit multiple receivers. See Section17.1.2.8 “Address should be loaded into the TX9D data bit. Detection” for more information on the Address mode. 9. Load 8-bit data into the TXREGx register. This will start the transmission. FIGURE 17-3: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TX/CKpin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag)  2012-2014 Microchip Technology Inc. DS30000684B-page 261

PIC18(L)F2X/45K50 FIGURE 17-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY TRMT bit Word 1 Word 2 Reg(T. rEamnspmtyi tF Slahgif)t Transmit Shift Reg Transmit Shift Reg Note: This timing diagram shows two consecutive transmissions. TABLE 17-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 269 SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — TXREG1 EUSART Transmit Register — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission. DS30000684B-page 262  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 17.1.2 EUSART ASYNCHRONOUS 17.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode would typically be used in reception on the falling edge of the first bit. The first bit, RS-232 systems. The receiver block diagram is shown also known as the Start bit, is always a zero. The data in Figure17-2. The data is received on the RX/DT pin recovery circuit counts one-half bit time to the center of and drives the data recovery block. The data recovery the Start bit and verifies that the bit is still a zero. If it is block is actually a high-speed shifter operating at 16 not a zero then the data recovery circuit aborts times the baud rate, whereas the serial Receive Shift character reception, without generating an error, and Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data are immediately transferred to a two character First-In- recovery circuit counts a full bit time to the center of the First-Out (FIFO) memory. The FIFO buffering allows next bit. The bit is then sampled by a majority detect reception of two complete characters and the start of a circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. third character before software must start servicing the This repeats until all data bits have been sampled and EUSART receiver. The FIFO and RSR registers are not shifted into the RSR. One final bit time is measured and directly accessible by software. Access to the received the level sampled. This is the Stop bit, which is always data is via the RCREGx register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this 17.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this character. See Section17.1.2.5 “Receive Framing The EUSART receiver is enabled for asynchronous Error” for more information on framing errors. operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have • CREN = 1 been received, the character in the RSR is transferred • SYNC = 0 to the EUSART receive FIFO and the RCIF interrupt • SPEN = 1 flag bit of the PIR1 register is set. The top character in All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the their default state. RCREGx register. Setting the CREN bit of the RCSTAx register enables Note: If the receive FIFO is overrun, no additional the receiver circuitry of the EUSART. Clearing the characters will be received until the overrun SYNC bit of the TXSTAx register configures the condition is cleared. See Section17.1.2.6 EUSART for asynchronous operation. Setting the “Receive Overrun Error” for more SPEN bit of the RCSTAx register enables the information on overrun errors. EUSART. The RX/DT I/O pin must be configured as an input by setting the corresponding TRIS control bit. If 17.1.2.3 Receive Data Polarity the RX/DT pin is shared with an analog peripheral the The polarity of the receive data can be controlled with analog I/O function must be disabled by clearing the the RXDTP bit of the BAUDCONx register. The default corresponding ANSEL bit. state of this bit is ‘0’ which selects high true receive Idle and data bits. Setting the RXDTP bit to ‘1’ will invert the receive data resulting in low true Idle and data bits. The RXDTP bit controls receive data polarity only in Asynchronous mode. In Synchronous mode the RXDTP bit has a different function.  2012-2014 Microchip Technology Inc. DS30000684B-page 263

PIC18(L)F2X/45K50 17.1.2.4 Receive Interrupts 17.1.2.7 Receiving 9-Bit Characters The RCIF interrupt flag bit of the PIR1 register is set The EUSART supports 9-bit character reception. When whenever the EUSART receiver is enabled and there is the RX9 bit of the RCSTAx register is set, the EUSART an unread character in the receive FIFO. The RCIF will shift nine bits into the RSR for each character interrupt flag bit is read-only, it cannot be set or cleared received. The RX9D bit of the RCSTAx register is the by software. ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data RCIF interrupts are enabled by setting the following from the receive FIFO buffer, the RX9D data bit must bits: be read before reading the eight Least Significant bits • RCIE interrupt enable bit of the PIE1 register from the RCREGx. • PEIE/GIEL peripheral interrupt enable bit of the INTCON register 17.1.2.8 Address Detection • GIE/GIEH global interrupt enable bit of the A special Address Detection mode is available for use INTCON register when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is The RCIF interrupt flag bit will be set when there is an enabled by setting the ADDEN bit of the RCSTAx unread character in the FIFO, regardless of the state of register. interrupt enable bits. Address detection requires 9-bit character reception. 17.1.2.5 Receive Framing Error When address detection is enabled, only characters Each character in the receive FIFO buffer has a with the ninth data bit set will be transferred to the corresponding framing error Status bit. A framing error receive FIFO buffer, thereby setting the RCIF interrupt indicates that a Stop bit was not seen at the expected bit. All other characters will be ignored. time. The framing error status is accessed via the Upon receiving an address character, user software FERR bit of the RCSTAx register. The FERR bit determines if the address matches its own. Upon represents the status of the top unread character in the address match, user software must disable address receive FIFO. Therefore, the FERR bit must be read detection by clearing the ADDEN bit before the next before reading the RCREGx. Stop bit occurs. When user software detects the end of The FERR bit is read-only and only applies to the top the message, determined by the message protocol unread character in the receive FIFO. A framing error used, software places the receiver back into the (FERR = 1) does not preclude reception of additional Address Detection mode by setting the ADDEN bit. characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTAx register which resets the EUSART. Clearing the CREN bit of the RCSTAx register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREGx will not clear the FERR bit. 17.1.2.6 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTAx register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTAx register or by resetting the EUSART by clearing the SPEN bit of the RCSTAx register. DS30000684B-page 264  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 17.1.2.9 Asynchronous Reception Setup: 17.1.2.10 9-Bit Address Detection Mode Setup 1. Initialize the SPBRGHx:SPBRGx register pair This mode would typically be used in RS-485 systems. and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section17.4 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGHx, SPBRGx register pair 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. and the BRGH and BRG16 bits to achieve the 3. Enable the serial port by setting the SPEN bit desired baud rate (see Section17.4 “EUSART and the RX/DT pin TRIS bit. The SYNC bit must Baud Rate Generator (BRG)”). be clear for asynchronous operation. 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. 4. If interrupts are desired, set the RCIE interrupt 3. Enable the serial port by setting the SPEN bit. enable bit and set the GIE/GIEH and PEIE/GIEL The SYNC bit must be clear for asynchronous bits of the INTCON register. operation. 5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE interrupt 6. Set the RXDTP if inverted receive polarity is enable bit and set the GIE/GIEH and PEIE/GIEL desired. bits of the INTCON register. 7. Enable reception by setting the CREN bit. 5. Enable 9-bit reception by setting the RX9 bit. 8. The RCIF interrupt flag bit will be set when a 6. Enable address detection by setting the ADDEN character is transferred from the RSR to the bit. receive buffer. An interrupt will be generated if 7. Set the RXDTP if inverted receive polarity is the RCIE interrupt enable bit was also set. desired. 9. Read the RCSTAx register to get the error flags 8. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 9. The RCIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 10. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREGx will be generated if the RCIE interrupt enable bit register. was also set. 11. If an overrun occurred, clear the OERR flag by 10. Read the RCSTAx register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 11. Get the received eight Least Significant data bits from the receive buffer by reading the RCREGx register. Software determines if this is the device’s address. 12. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 13. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts.  2012-2014 Microchip Technology Inc. DS30000684B-page 265

PIC18(L)F2X/45K50 FIGURE 17-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 RCREGx RCREGx RCIDL Read Rcv Buffer Reg RCREGx RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX/DT input. The RCREGx (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. TABLE 17-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 RCREG1 EUSART Receive Register — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 269 SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception. DS30000684B-page 266  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 17.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See 3.6 “Internal Clock Modes” for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section17.4.1 “Auto- Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.  2012-2014 Microchip Technology Inc. DS30000684B-page 267

PIC18(L)F2X/45K50 17.3 Register Definitions: EUSART Control REGISTER 17-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS30000684B-page 268  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 17-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREGx register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.  2012-2014 Microchip Technology Inc. DS30000684B-page 269

PIC18(L)F2X/45K50 REGISTER 17-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been detected and the receiver is active Synchronous mode: Don’t care bit 5 RXDTP: Data/Receive Polarity Select bit Asynchronous mode: 1 = Receive data (RX) is inverted (active-low) 0 = Receive data (RX) is not inverted (active-high) Synchronous mode: 1 = Data (DT) is inverted (active-low) 0 = Data (DT) is not inverted (active-high) bit 4 TXCKP: Clock/Transmit Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TX) is low 0 = Idle state for transmit (TX) is high Synchronous mode: 1 = Data changes on the falling edge of the clock and is sampled on the rising edge of the clock 0 = Data changes on the rising edge of the clock and is sampled on the falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used (SPBRGHx:SPBRGx) 0 = 8-bit Baud Rate Generator is used (SPBRGx) bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received but RCIF will be set on the falling edge. WUE will automatically clear on the rising edge. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS30000684B-page 270  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 17.4 EUSART Baud Rate Generator If the system clock is changed during an active receive (BRG) operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to The Baud Rate Generator (BRG) is an 8-bit or 16-bit make sure that the receive operation is Idle before timer that is dedicated to the support of both the changing the system clock. asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the EXAMPLE 17-1: CALCULATING BAUD BRG16 bit of the BAUDCONx register selects 16-bit RATE ERROR mode. For a device with FOSC of 16 MHz, desired baud rate The SPBRGHx:SPBRGx register pair determines the of 9600, Asynchronous mode, 8-bit BRG: period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate Desired Baud Rate = -------------------------------F----O----S--C--------------------------------- 64[SPBRGHx:SPBRGx]+1 period is determined by both the BRGH bit of the TXSTAx register and the BRG16 bit of the BAUDCONx Solving for SPBRGHx:SPBRGx: register. In Synchronous mode, the BRGH bit is ignored. FOSC --------------------------------------------- Table17-3 contains the formulas for determining the Desired Baud Rate X = ---------------------------------------------–1 baud rate. Example17-1 provides a sample calculation 64 for determining the baud rate and baud rate error. 16000000 ------------------------ Typical baud rates and error values for various 9600 = ------------------------–1 Asynchronous modes have been computed for your 64 convenience and are shown in Table17-5. It may be = 25.042 = 25 advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate Calculated Baud Rate = --1---6---0---0---0---0---0---0---- 6425+1 error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. = 9615 Writing a new value to the SPBRGHx, SPBRGx Calc. Baud Rate–Desired Baud Rate register pair causes the BRG timer to be reset (or Error = -------------------------------------------------------------------------------------------- Desired Baud Rate cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. 9615–9600 = ---------------------------------- = 0.16% 9600 TABLE 17-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGHx, SPBRGx register pair.  2012-2014 Microchip Technology Inc. DS30000684B-page 271

PIC18(L)F2X/45K50 TABLE 17-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 269 SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the BRG. TABLE 17-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRxG SPBRGx SPBRGx SPBRGx Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 — — — 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9615 0.16 77 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 71 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.23k 0.16 38 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k 57.69k 0.16 12 57.60k 0.00 7 — — — 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRGx SPBRGx SPBRGx SPBRGx Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — DS30000684B-page 272  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 17-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRGx SPBRGx SPBRGx SPBRGx Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 — — — 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 — — — 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.97k 0.16 51 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 115.39k 0.16 25 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5 SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRGx SPBRGx SxBRGx SPBRGx Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRGHx: SPBRGHx: SPBRGHx SPBRGHx: Actual % Actual % Actual % Actual % SPBRGx SPBRGx :SPBRGx SPBRGx Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 9999 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200 0.00 2499 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2400 0.00 1249 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9585 -0.16 312 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 287 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.69k 0.16 51 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 115.39k 0.16 25 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5  2012-2014 Microchip Technology Inc. DS30000684B-page 273

PIC18(L)F2X/45K50 TABLE 17-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRGHx: SPBRGHx: SPBRGHx SPBRGHx: Actual % Actual % Actual % Actual % SPBRGx SPBRGx :SPBRGx SPBRGx Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRGHx: SPBRGHx: SPBRGHx SPBRGHx: Actual % Actual % Actual % Actual % SPBRGx SPBRGx :SPBRGx SPBRGx Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300 0.00 39999 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 0.00 9999 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.00 4999 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9600 0.00 1249 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 1151 10425 0.08 441 10417 0.00 383 10433 0.16 264 19.2k 19.2k 0.00 624 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.69k 0.16 207 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 115.39k 0.16 103 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRGHx: SPBRGHx: SPBRGHx SPBRGHx: Actual % Actual % Actual % Actual % SPBRGx SPBRGx :SPBRGx SPBRGx Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — — DS30000684B-page 274  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 17.4.1 AUTO-BAUD DETECT and SPBRGx registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the Note1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. following the Break character (see Section17.4.3 “Auto-Wake-up on The Baud Rate Generator is used to time the period of Break”). a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the that it has five rising edges including the Stop bit edge. incoming character baud rate is within the Setting the ABDEN bit of the BAUDCONx register range of the selected BRG clock source. Some combinations of oscillator frequency starts the auto-baud calibration sequence (Section17.4.2 “Auto-Baud Overflow”). While the and EUSART baud rates are not possible. ABD sequence takes place, the EUSART state 3: During the auto-baud process, the auto- machine is held in Idle. On the first rising edge of the baud counter starts counting at 1. Upon receive line, after the Start bit, the SPBRGx begins completion of the auto-baud sequence, to counting up using the BRG counter clock as shown in achieve maximum accuracy, subtract 1 Table17-6. The fifth rising edge will occur on the RX/ from the SPBRGHx:SPBRGx register pair. DT pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPBRGHx:SPBRGx register pair, the TABLE 17-6: BRG COUNTER CLOCK ABDEN bit is automatically cleared, and the RCIF RATES interrupt flag is set. A read operation on the RCREGx BRG Base BRG ABD needs to be performed to clear the RCIF interrupt. BRG16 BRGH Clock Clock RCREGx content should be discarded. When calibrating for modes that do not use the SPBRGHx 0 0 FOSC/64 FOSC/512 register the user can verify that the SPBRGx register 0 1 FOSC/16 FOSC/128 did not overflow by checking for 00h in the SPBRGHx register. 1 0 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 1 1 FOSC/4 FOSC/32 and BRGH bits as shown in Table17-6. During ABD, Note: During the ABD sequence, SPBRGx and both the SPBRGHx and SPBRGx registers are used as SPBRGHx registers are both used as a a 16-bit counter, independent of the BRG16 bit setting. 16-bit counter, independent of BRG16 While calibrating the baud rate period, the SPBRGHx setting. FIGURE 17-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX/DT pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREGx SPBRGx XXh 1Ch SPBRGHx XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 275

PIC18(L)F2X/45K50 17.4.2 AUTO-BAUD OVERFLOW 17.4.3.1 Special Considerations During the course of automatic baud detection, the Break Character ABDOVF bit of the BAUDCONx register will be set if the To avoid character errors or character fragments during baud rate counter overflows before the fifth rising edge a wake-up event, the wake-up character must be all is detected on the RX pin. The ABDOVF bit indicates zeros. that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGHx:SPBRGx register When the wake-up is enabled the function works pair. After the ABDOVF has been set, the counter con- independent of the low time on the data stream. If the tinues to count until the fifth rising edge is detected on WUE bit is set and a valid non-zero character is the RX/DT pin. Upon detecting the fifth RX/DT edge, the received, the low time from the Start bit to the first rising hardware will set the RCIF interrupt flag and clear the edge will be interpreted as the wake-up event. The ABDEN bit of the BAUDCONx register. The RCIF flag remaining bits in the character will be received as a can be subsequently cleared by reading the RCREGx. fragmented character and subsequent characters can The ABDOVF flag can be cleared by software directly. result in framing or overrun errors. To terminate the auto-baud process before the RCIF Therefore, the initial character in the transmission must flag is set, clear the ABDEN bit then clear the ABDOVF be all ‘0’s. This must be 10 or more bit times, 13-bit bit. The ABDOVF bit will remain set if the ABDEN bit is times recommended for LIN bus, or any number of bit not cleared first. times for standard RS-232 devices. Oscillator Startup Time 17.4.3 AUTO-WAKE-UP ON BREAK Oscillator start-up time must be considered, especially During Sleep mode, all clocks to the EUSART are in applications using oscillators with longer start-up suspended. Because of this, the Baud Rate Generator intervals (i.e., LP, XT or HS/PLL mode). The Sync is inactive and a proper character reception cannot be Break (or wake-up signal) character must be of performed. The Auto-Wake-up feature allows the sufficient length, and be followed by a sufficient controller to wake-up due to activity on the RX/DT line. interval, to allow enough time for the selected oscillator This feature is available only in Asynchronous mode. to start and provide proper initialization of the EUSART. The Auto-Wake-up feature is enabled by setting the WUE Bit WUE bit of the BAUDCONx register. Once set, the The wake-up event causes a receive interrupt by normal receive sequence on RX/DT is disabled, and setting the RCIF bit. The WUE bit is cleared by the EUSART remains in an Idle state, monitoring for a hardware by a rising edge on RX/DT. The interrupt wake-up event independent of the CPU mode. A wake- condition is then cleared by software by reading the up event consists of a high-to-low transition on the RX/ RCREGx register and discarding its contents. DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process The EUSART module generates an RCIF interrupt before setting the WUE bit. If a receive operation is not coincident with the wake-up event. The interrupt is occurring, the WUE bit may then be set just prior to generated synchronously to the Q clocks in normal CPU entering the Sleep mode. operating modes (Figure17-7), and asynchronously if the device is in Sleep mode (Figure17-8). The interrupt condition is cleared by reading the RCREGx register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. DS30000684B-page 276  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 17-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREGx Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 17-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RX/DT Line Note 1 RCIF Cleared due to User Read of RCREGx Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set.  2012-2014 Microchip Technology Inc. DS30000684B-page 277

PIC18(L)F2X/45K50 17.4.4 BREAK CHARACTER SEQUENCE 17.4.5 RECEIVING A BREAK CHARACTER The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break special Break character sequences that are required by character in two ways. the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTAx register and the Received To send a Break character, set the SENDB and TXEN data as indicated by RCREGx. The Baud Rate bits of the TXSTAx register. The Break character trans- Generator is assumed to have been initialized to the mission is then initiated by a write to the TXREGx. The expected baud rate. value of data written to TXREGx will be ignored and all A Break character has been received when; ‘0’s will be transmitted. • RCIF bit is set The SENDB bit is automatically reset by hardware after • FERR bit is set the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte • RCREGx = 00h following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature character in the LIN specification). described in Section17.4.3 “Auto-Wake-up on The TRMT bit of the TXSTAx register indicates when the Break”. By enabling this feature, the EUSART will transmit operation is active or Idle, just as it does during sample the next two transitions on RX/DT, cause an normal transmission. See Figure17-9 for the timing of RCIF interrupt, and receive the next data byte followed the Break character sequence. by another interrupt. Note that following a Break character, the user will 17.4.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature. The following sequence will start a message frame For both methods, the user can set the ABDEN bit of header made up of a Break, followed by an auto-baud the BAUDCONx register before placing the EUSART in Sync byte. This sequence is typical of a LIN bus Sleep mode. master. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to enable the Break sequence. 3. Load the TXREGx with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREGx to load the Sync charac- ter into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREGx becomes empty, as indicated by the TXIF, the next data byte can be written to TXREGx. FIGURE 17-9: SEND BREAK CHARACTER SEQUENCE Write to TXREGx Dummy Write BRG Output (Shift Clock) TX/CK (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit) DS30000684B-page 278  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 17.5 EUSART Synchronous Mode 17.5.1.2 Clock Polarity Synchronous serial communications are typically used A clock polarity option is provided for Microwire in systems with a single master and one or more compatibility. Clock polarity is selected with the TXCKP slaves. The master device contains the necessary bit of the BAUDCONx register. Setting the TXCKP bit circuitry for baud rate generation and supplies the clock sets the clock Idle state as high. When the TXCKP bit for all devices in the system. Slave devices can take is set, the data changes on the falling edge of each advantage of the master clock by eliminating the clock and is sampled on the rising edge of each clock. internal clock generation circuitry. Clearing the TXCKP bit sets the Idle state as low. When the TXCKP bit is cleared, the data changes on the There are two signal lines in Synchronous mode: a rising edge of each clock and is sampled on the falling bidirectional data line and a clock line. Slaves use the edge of each clock. external clock supplied by the master to shift the serial data into and out of their respective receive and 17.5.1.3 Synchronous Master Transmission transmit shift registers. Since the data line is Data is transferred out of the device on the RX/DT pin. bidirectional, synchronous operation is half-duplex The RX/DT and TX/CK pin output drivers are automat- only. Half-duplex refers to the fact that master and ically enabled when the EUSART is configured for slave devices can receive and transmit data but not synchronous master transmit operation. both simultaneously. The EUSART can operate as either a master or slave device. A transmission is initiated by writing a character to the TXREGx register. If the TSR still contains all or part of Start and Stop bits are not used in synchronous a previous character the new character data is held in transmissions. the TXREGx until the last bit of the previous character 17.5.1 SYNCHRONOUS MASTER MODE has been transmitted. If this is the first character, or the previous character has been completely flushed from The following bits are used to configure the EUSART the TSR, the data in the TXREGx is immediately trans- for Synchronous Master operation: ferred to the TSR. The transmission of the character • SYNC = 1 commences immediately following the transfer of the • CSRC = 1 data to the TSR from the TXREGx. • SREN = 0 (for transmit); SREN = 1 (for receive) Each data bit changes on the leading edge of the • CREN = 0 (for transmit); CREN = 1 (for receive) master clock and remains valid until the subsequent leading clock edge. • SPEN = 1 Setting the SYNC bit of the TXSTAx register configures Note: The TSR register is not mapped in data the device for synchronous operation. Setting the CSRC memory, so it is not available to the user. bit of the TXSTAx register configures the device as a 17.5.1.4 Data Polarity master. Clearing the SREN and CREN bits of the RCSTAx register ensures that the device is in the The polarity of the transmit and receive data can be Transmit mode, otherwise the device will be configured controlled with the RXDTP bit of the BAUDCONx to receive. Setting the SPEN bit of the RCSTAx register register. The default state of this bit is ‘0’ which selects enables the EUSART. If the RX/DT or TX/CK pins are high true transmit and receive data. Setting the RXDTP shared with an analog peripheral the analog I/O functions bit to ‘1’ will invert the data resulting in low true transmit must be disabled by clearing the corresponding ANSEL and receive data. bits. The TRIS bits corresponding to the RX/DT and TX/ CK pins should be set. 17.5.1.1 Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits.  2012-2014 Microchip Technology Inc. DS30000684B-page 279

PIC18(L)F2X/45K50 17.5.1.5 Synchronous Master Transmission 4. Disable Receive mode by clearing bits SREN Setup and CREN. 5. Enable Transmit mode by setting the TXEN bit. 1. Initialize the SPBRGHx, SPBRGx register pair and the BRGH and BRG16 bits to achieve the 6. If 9-bit transmission is desired, set the TX9 bit. desired baud rate (see Section17.4 “EUSART 7. If interrupts are desired, set the TXIE, GIE/GIEH Baud Rate Generator (BRG)”). and PEIE/GIEL interrupt enable bits. 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. 8. If 9-bit transmission is selected, the ninth bit 3. Enable the synchronous master serial port by should be loaded in the TX9D bit. setting bits SYNC, SPEN and CSRC. Set the 9. Start transmission by loading data to the TRIS bits corresponding to the RX/DT and TX/ TXREGx register. CK I/O pins. FIGURE 17-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREGx Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. FIGURE 17-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREGx reg TXIF bit TRMT bit TXEN bit DS30000684B-page 280  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 17-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 269 SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 TXREG1 EUSART Transmit Register — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master transmission.  2012-2014 Microchip Technology Inc. DS30000684B-page 281

PIC18(L)F2X/45K50 17.5.1.6 Synchronous Master Reception If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the Data is received at the RX/DT pin. The RX/DT pin CREN bit of the RCSTAx register or by clearing the output driver must be disabled by setting the SPEN bit which resets the EUSART. corresponding TRIS bits when the EUSART is configured for synchronous master receive operation. 17.5.1.9 Receiving 9-Bit Characters In Synchronous mode, reception is enabled by setting The EUSART supports 9-bit character reception. When either the Single Receive Enable bit (SREN of the the RX9 bit of the RCSTAx register is set the EUSART RCSTAx register) or the Continuous Receive Enable will shift 9-bits into the RSR for each character bit (CREN of the RCSTAx register). received. The RX9D bit of the RCSTAx register is the When SREN is set and CREN is clear, only as many ninth, and Most Significant, data bit of the top unread clock cycles are generated as there are data bits in a character in the receive FIFO. When reading 9-bit data single character. The SREN bit is automatically cleared from the receive FIFO buffer, the RX9D data bit must at the completion of one character. When CREN is set, be read before reading the eight Least Significant bits clocks are continuously generated until CREN is from the RCREGx. cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial charac- 17.5.1.10 Synchronous Master Reception ter is discarded. If SREN and CREN are both set, then Setup SREN is cleared at the completion of the first character 1. Initialize the SPBRGHx, SPBRGx register pair and CREN takes precedence. for the appropriate baud rate. Set or clear the To initiate reception, set either SREN or CREN. Data is BRGH and BRG16 bits, as required, to achieve sampled at the RX/DT pin on the trailing edge of the the desired baud rate. TX/CK clock pin and is shifted into the Receive Shift 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. Register (RSR). When a complete character is 3. Enable the synchronous master serial port by received into the RSR, the RCIF bit is set and the setting bits SYNC, SPEN and CSRC. Disable character is automatically transferred to the two RX/DT and TX/CK output drivers by setting the character receive FIFO. The Least Significant eight bits corresponding TRIS bits. of the top character in the receive FIFO are available in 4. Ensure bits CREN and SREN are clear. RCREGx. The RCIF bit remains set as long as there are un-read characters in the receive FIFO. 5. If using interrupts, set the GIE/GIEH and PEIE/ GIEL bits of the INTCON register and set RCIE. 17.5.1.7 Slave Clock 6. If 9-bit reception is desired, set bit RX9. Synchronous data transfers use a separate clock line, 7. Start reception by setting the SREN bit or for which is synchronous with the data. A device configured continuous reception, set the CREN bit. as a slave receives the clock on the TX/CK line. The TX/ 8. Interrupt flag bit RCIF will be set when reception CK pin output driver must be disabled by setting the of a character is complete. An interrupt will be associated TRIS bit when the device is configured for generated if the enable bit RCIE was set. synchronous slave transmit or receive operation. Serial 9. Read the RCSTAx register to get the ninth bit (if data bits change on the leading edge to ensure they are enabled) and determine if any error occurred valid at the trailing edge of each clock. One data bit is during reception. transferred for each clock cycle. Only as many clock 10. Read the 8-bit received data by reading the cycles should be received as there are data bits. RCREGx register. 17.5.1.8 Receive Overrun Error 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTAx The receive FIFO buffer can hold two characters. An register or by clearing the SPEN bit which resets overrun error will be generated if a third character, in its the EUSART. entirety, is received before RCREGx is read to access the FIFO. When this happens the OERR bit of the RCSTAx register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREGx. DS30000684B-page 282  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 17-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREGx Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 17-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 RCREG1 EUSART Receive Register — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 269 SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.  2012-2014 Microchip Technology Inc. DS30000684B-page 283

PIC18(L)F2X/45K50 17.5.2 SYNCHRONOUS SLAVE MODE 17.5.2.1 EUSART Synchronous Slave Transmit The following bits are used to configure the EUSART for Synchronous slave operation: The operation of the Synchronous Master and Slave • SYNC = 1 modes are identical (see Section17.5.1.3 “Synchronous Master Transmission”), except in the • CSRC = 0 case of the Sleep mode. • SREN = 0 (for transmit); SREN = 1 (for receive) If two words are written to the TXREGx and then the • CREN = 0 (for transmit); CREN = 1 (for receive) SLEEP instruction is executed, the following will occur: • SPEN = 1 1. The first character will immediately transfer to Setting the SYNC bit of the TXSTAx register configures the TSR register and transmit. the device for synchronous operation. Clearing the 2. The second word will remain in TXREGx CSRC bit of the TXSTAx register configures the device as register. a slave. Clearing the SREN and CREN bits of the RCSTAx register ensures that the device is in the 3. The TXIF bit will not be set. Transmit mode, otherwise the device will be configured to 4. After the first character has been shifted out of receive. Setting the SPEN bit of the RCSTAx register TSR, the TXREGx register will transfer the enables the EUSART. If the RX/DT or TX/CK pins are second character to the TSR and the TXIF bit will shared with an analog peripheral the analog I/O functions now be set. must be disabled by clearing the corresponding ANSEL 5. If the PEIE/GIEL and TXIE bits are set, the bits. interrupt will wake the device from Sleep and RX/DT and TX/CK pin output drivers must be disabled execute the next instruction. If the GIE/GIEH bit by setting the corresponding TRIS bits. is also set, the program will call the Interrupt Service Routine. 17.5.2.2 Synchronous Slave Transmission Setup: 1. Set the SYNC and SPEN bits and clear the CSRC bit. 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. 3. Clear the CREN and SREN bits. 4. If using interrupts, ensure that the GIE/GIEH and PEIE/GIEL bits of the INTCON register are set and set the TXIE bit. 5. If 9-bit transmission is desired, set the TX9 bit. 6. Enable transmission by setting the TXEN bit. 7. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 8. Start transmission by writing the Least Significant eight bits to the TXREGx register. DS30000684B-page 284  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 17-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSP1F CCP1IF TMR2IF TMR1IF 117 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 269 SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 TXREG1 EUSART Transmit Register — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave transmission.  2012-2014 Microchip Technology Inc. DS30000684B-page 285

PIC18(L)F2X/45K50 17.5.2.3 EUSART Synchronous Slave 17.5.2.4 Synchronous Slave Reception Setup Reception 1. Set the SYNC and SPEN bits and clear the The operation of the Synchronous Master and Slave CSRC bit. modes is identical (Section17.5.1.6 “Synchronous 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. Master Reception”), with the following exceptions: 3. If using interrupts, ensure that the GIE/GIEH • Sleep and PEIE/GIEL bits of the INTCON register are set and set the RCIE bit. • CREN bit is always set, therefore the receiver is never Idle 4. If 9-bit reception is desired, set the RX9 bit. • SREN bit, which is a “don’t care” in Slave mode 5. Set the CREN bit to enable reception. 6. The RCIF bit will be set when reception is A character may be received while in Sleep mode by complete. An interrupt will be generated if the setting the CREN bit prior to entering Sleep. Once the RCIE bit was set. word is received, the RSR register will transfer the data to the RCREGx register. If the RCIE enable bit is set, 7. If 9-bit mode is enabled, retrieve the Most the interrupt generated will wake the device from Sleep Significant bit from the RX9D bit of the RCSTAx and execute the next instruction. If the GIE/GIEH bit is register. also set, the program will branch to the interrupt vector. 8. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREGx register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTAx register or by clearing the SPEN bit which resets the EUSART. TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 RCREG1 EUSART Receive Register — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 269 SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception. DS30000684B-page 286  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 18.0 ANALOG-TO-DIGITAL The ADC voltage reference is software selectable to CONVERTER (ADC) MODULE either VDD or a voltage applied to the external reference pins. The Analog-to-Digital Converter (ADC) allows The ADC can generate an interrupt upon completion of conversion of an analog input signal to a 10-bit binary a conversion. This interrupt can be used to wake-up the representation of that signal. This device uses analog device from Sleep. inputs, which are multiplexed into a single sample and Figure18-1 shows the block diagram of the ADC. hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). FIGURE 18-1: ADC BLOCK DIAGRAM 5 CHS<4:0> 11111 FVR BUF2 11110 DAC 11101 CTMU 11100 Temperature Diode 11011 AN27(1) ADCMD AN5(1) 00101 ADON 10-Bit ADC GO/DONE 00100 AN4 10 00011 AN3 00010 AN2 0 = Left Justify ADFM 00001 1 = Right Justify AN1 00000 AN0 10 2 PVCFG<1:0> ADRESH ADRESL AVDD 00 01 VREF+/AN3 10 FVR BUF2 Reserved 11 2 NVCFG<1:0> AVSS 00 01 VREF-/AN2 10 Reserved Reserved 11 Note: Additional ADC channels AN5-AN7 and AN20-AN27 are only available on PIC18(L)F45K50 devices.  2012-2014 Microchip Technology Inc. DS30000684B-page 287

PIC18(L)F2X/45K50 18.1 ADC Configuration 18.1.3 ADC VOLTAGE REFERENCE When configuring and using the ADC the following The PVCFG<1:0> and NVCFG<1:0> bits of the functions must be considered: ADCON1 register provide independent control of the positive and negative voltage references. • Port configuration The positive voltage reference can be: • Channel selection • ADC voltage reference selection • VDD • ADC conversion clock source • the fixed voltage reference (FVR BUF2) • Interrupt control • an external voltage source (VREF+) • Results formatting The negative voltage reference can be: • VSS 18.1.1 PORT CONFIGURATION • an external voltage source (VREF-) The ANSELx and TRISx registers configure the A/D port pins. Any port pin needed as an analog input 18.1.4 SELECTING AND CONFIGURING should have its corresponding ANSx bit set to disable ACQUISITION TIME the digital input buffer and TRISx bit set to disable the The ADCON2 register allows the user to select an digital output driver. If the TRISx bit is cleared, the acquisition time that occurs each time the GO/DONE digital output level (VOH or VOL) will be converted. bit is set. The A/D operation is independent of the state of the Acquisition time is set with the ACQT<2:0> bits of the ANSx bits and the TRIS bits. ADCON2 register. Acquisition delays cover a range of Note1: When reading the PORT register, all pins 2 to 20TAD. When the GO/DONE bit is set, the A/D with their corresponding ANSx bit set module continues to sample the input for the selected read as cleared (a low level). However, acquisition time, then automatically begins a analog conversion of pins configured as conversion. Since the acquisition time is programmed, digital inputs (ANSx bit cleared and there is no need to wait for an acquisition time between TRISx bit set) will be accurately selecting a channel and setting the GO/DONE bit. converted. Manual acquisition is selected when 2: Analog levels on any pin with the corre- ACQT<2:0>=000. When the GO/DONE bit is set, sponding ANSx bit cleared may cause sampling is stopped and a conversion begins. The user the digital input buffer to consume current is responsible for ensuring the required acquisition time out of the device’s specification limits. has passed between selecting the desired input channel and setting the GO/DONE bit. This option is 3: The PBADEN bit in Configuration also the default Reset state of the ACQT<2:0> bits and Register 3H configures PORTB pins to is compatible with devices that do not offer reset as analog or digital pins by programmable acquisition times. controlling how the bits in ANSELB are reset. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the 18.1.2 CHANNEL SELECTION A/D begins sampling the currently selected channel again. When an acquisition time is programmed, there The CHS bits of the ADCON0 register determine which is no indication of when the acquisition time ends and channel is connected to the sample and hold circuit. the conversion begins. When changing channels, a delay is required before starting the next conversion. Refer to Section18.2 “ADC Operation” for more information. DS30000684B-page 288  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 18.1.5 CONVERSION CLOCK 18.1.6 INTERRUPTS The source of the conversion clock is software The ADC module allows for the ability to generate an selectable via the ADCS bits of the ADCON2 register. interrupt upon completion of an Analog-to-Digital There are seven possible clock options: Conversion. The ADC interrupt enable is the ADIE bit in the PIE1 register and the interrupt priority is the ADIP • FOSC/2 bit in the IPR1 register. The ADC interrupt flag is the • FOSC/4 ADIF bit in the PIR1 register. The ADIF bit must be • FOSC/8 cleared by software. • FOSC/16 Note: The ADIF bit is set at the completion of • FOSC/32 every conversion, regardless of whether • FOSC/64 or not the ADC interrupt is enabled. • FRC (dedicated internal oscillator) This interrupt can be generated while the device is The time to complete one bit conversion is defined as operating or while in Sleep. If the device is in Sleep, the TAD. One full 10-bit conversion requires 11 TAD periods interrupt will wake-up the device. Upon waking from as shown in Figure18-3. Sleep, the next instruction following the SLEEP For correct conversion, the appropriate TAD specification instruction is always executed. If the user is attempting must be met. See A/D conversion requirements in to wake-up from Sleep and resume in-line code Table29-33 for more information. Table18-1 gives execution, the global interrupt must be disabled. If the examples of appropriate ADC clock selections. global interrupt is enabled, execution will switch to the Interrupt Service Routine. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. TABLE 18-1: ADC CLOCK PERIOD (TAD) vs. DEVICE OPERATING FREQUENCIES AD Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 48 MHz 16 MHz 4 MHz 1 MHz FOSC/2 000 41.17 ns(2) 125 ns(2) 500 ns(2) 2.0 s FOSC/4 100 83.3 ns(2) 250 ns(2) 1.0 s 4.0 s(3) FOSC/8 001 166.7 ns(2) 500 ns(2) 2.0 s 8.0 s(3) FOSC/16 101 333.3 ns(2) 1.0 s 4.0 s(3) 16.0 s(3) FOSC/32 010 666.7 ns(2) 2.0 s 8.0 s(3) 32.0 s(3) FOSC/64 110 1.3 s 4.0 s(3) 16.0 s(3) 64.0 s(3) FRC 011 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4) Legend: Shaded cells are outside the recommended range. Note 1: The FRC source has a typical TAD time of 1.7 s. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the F clock source is only recommended if the RC conversion will be performed during Sleep.  2012-2014 Microchip Technology Inc. DS30000684B-page 289

PIC18(L)F2X/45K50 18.1.7 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON2 register controls the output format. Figure18-2 shows the two output formats. FIGURE 18-2: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result DS30000684B-page 290  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 18.2 ADC Operation Figure18-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT<2:0> bits 18.2.1 STARTING A CONVERSION are cleared. A conversion is started after the following instruction to allow entry into SLEEP mode before the To enable the ADC module, the ADON bit of the conversion begins. ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will, depend- Figure18-4 shows the operation of the A/D converter ing on the ACQT bits of the ADCON2 register, either after the GO bit has been set and the ACQT<2:0> bits immediately start the Analog-to-Digital conversion or are set to ‘010’ which selects a 4 TAD acquisition time start an acquisition delay followed by the Analog-to- before the conversion starts. Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section18.2.10 “A/D Conver- sion Procedure”. FIGURE 18-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 2 TAD b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Discharge Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 18-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 2 TAD b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Discharge Time (Holding capacitor is disconnected from analog input) Set GO bit (Holding capacitor continues On the following cycle: acquiring input) ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.  2012-2014 Microchip Technology Inc. DS30000684B-page 291

PIC18(L)F2X/45K50 18.2.2 COMPLETION OF A CONVERSION 18.2.7 ADC OPERATION DURING SLEEP When the conversion is complete, the ADC module will: The ADC module can operate during Sleep. This • Clear the GO/DONE bit requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the • Set the ADIF flag bit ADC waits one additional instruction before starting the • Update the ADRESH:ADRESL registers with new conversion. This allows the SLEEP instruction to be conversion result executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device 18.2.3 DISCHARGE will wake-up from Sleep when the conversion The discharge phase is used to initialize the value of completes. If the ADC interrupt is disabled, the ADC the capacitor array. The array is discharged after every module is turned off after the conversion completes, sample. This feature helps to optimize the unity-gain although the ADON bit remains set. amplifier, as the circuit always needs to charge the When the ADC clock source is something other than capacitor array, rather than charge/discharge based on FRC, a SLEEP instruction causes the present previous measure values. conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 18.2.4 TERMINATING A CONVERSION If a conversion must be terminated before completion, 18.2.8 SPECIAL EVENT TRIGGER the GO/DONE bit can be cleared by software. The Two Special Event Triggers are available to start an A/D ADRESH:ADRESL registers will not be updated with conversion: CTMU and CCP2. The Special Event the partially complete Analog-to-Digital conversion Trigger source is selected using the TRIGSEL bit in sample. Instead, the ADRESH:ADRESL register pair ADCON1. will retain the value of the previous conversion. When TRIGSEL = 0, the CCP2 module is selected as Note: A device Reset forces all registers to their the Special Event Trigger source. To enable the Special Reset state. Thus, the ADC module is Event Trigger in the CCP module, set CCP2M<3:0> = turned off and any pending conversion is 1011, in the CCP2CON register. terminated. When TRIGSEL = 1, the CTMU module is selected. The CTMU module requires that the CTTRIG bit in 18.2.5 DELAY BETWEEN CONVERSIONS CTMUCONH is set to enable the Special Event Trigger. After the A/D conversion is completed or aborted, a In addition to the TRIGSEL bit, the following steps are 2TAD wait is required before the next acquisition can required to start an A/D conversion: be started. After this wait, the currently selected channel is reconnected to the charge holding capacitor • The A/D module must be enabled (ADON = 1) commencing the next acquisition. • The appropriate analog input channel selected • The minimum acquisition period set one of these 18.2.6 ADC OPERATION IN POWER- ways: MANAGED MODES - Timing provided by the user - Selection made of an appropriate TACQ time The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock With these conditions met, the trigger sets the GO/DONE source and frequency while in a power-managed mode. bit and the A/D acquisition starts. If the A/D is expected to operate while the device is in If the A/D module is not enabled (ADON = 0), the a power-managed mode, the ACQT<2:0> and module ignores the Special Event Trigger. ADCS<2:0> bits in ADCON2 should be updated in 18.2.9 PERIPHERAL MODULE DISABLE accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or When a peripheral module is not used or inactive, the conversion may be started. Once started, the device module can be disabled by setting the Module Disable should continue to be clocked by the same clock bit in the PMD registers. This will reduce power source until the conversion has been completed. consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the If desired, the device may be placed into the module’s clock source. The Module Disable bit for the corresponding Idle mode during the conversion. If the ADC module is ADCMD in the PMD1 Register. See device clock frequency is less than 1MHz, the A/D FRC clock source should be selected. Section4.0 “Power-Managed Modes” for more information. DS30000684B-page 292  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 18.2.10 A/D CONVERSION PROCEDURE EXAMPLE 18-1: A/D CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss as reference, Frc clock and AN0 input. 1. Configure Port: ; • Disable pin output driver (See TRIS register) ;Conversion start & polling for completion • Configure pin as analog ; are included. ; 2. Configure the ADC module: MOVLW B’10101111’ ;right justify, Frc, • Select ADC conversion clock MOVWF ADCON2 ; & 12 TAD ACQ time • Configure voltage reference MOVLW B’00000000’ ;ADC ref = Vdd,Vss MOVWF ADCON1 ; • Select ADC input channel BSF TRISA,0 ;Set RA0 to input • Select result format BSF ANSEL,0 ;Set RA0 to analog • Select acquisition delay MOVLW B’00000001’ ;AN0, ADC on • Turn on ADC module MOVWF ADCON0 ; BSF ADCON0,GO ;Start conversion 3. Configure ADC interrupt (optional): ADCPoll: • Clear ADC interrupt flag BTFSC ADCON0,GO ;Is conversion done? • Enable ADC interrupt BRA ADCPoll ;No, test again ; Result is complete - store 2 MSbits in • Enable peripheral interrupt ; RESULTHI and 8 LSbits in RESULTLO • Enable global interrupt(1) MOVFF ADRESH,RESULTHI 4. Wait the required acquisition time(2). MOVFF ADRESL,RESULTLO 5. Start conversion by setting the GO/DONE bit. 6. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Software delay required if ACQT bits are set to zero delay. See Section18.4 “A/D Acquisition Requirements”.  2012-2014 Microchip Technology Inc. DS30000684B-page 293

PIC18(L)F2X/45K50 18.3 Register Definitions: ADC Control Note: Analog pin control is determined by the ANSELx registers (see Register11-2) REGISTER 18-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CHS<4:0> GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4 00101 = AN5(1) 00110 = AN6(1) 00111 = AN7(1) 01000 = AN8 01001 = AN9 01010 = AN10 01011 = AN11 01100 = AN12 01101 = AN13 01110 = AN14 01111 = AN15 10000 = AN16 10001 = AN17 10010 = AN18 10011 = AN19 10100 = AN20(1) 10101 = AN21(1) 10110 = AN22(1) 10111 = AN23(1) 11000 = AN24(1) 11001 = AN25(1) 11010 = AN26(1) 11011 = AN27(1) 11100 = Temperature Diode 11101 = CTMU 11110 = DAC 11111 = FVR BUF2 (1.024V/2.048V/4.096V Fixed Voltage Reference)(2) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: Available on PIC18(L)F45K50 devices only. 2: Allow greater than 15s acquisition time when measuring the Fixed Voltage Reference. DS30000684B-page 294  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 18-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 TRIGSEL — — — PVCFG<1:0> NVCFG<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TRIGSEL: Special Trigger Select bit 1 = Selects the special trigger from CTMU 0 = Selects the special trigger from CCP2 bit 6-4 Unimplemented: Read as ‘0’ bit 3-2 PVCFG<1:0>: Positive Voltage Reference Configuration bits 00 = A/D VREF+ connected to internal signal, AVDD 01 = A/D VREF+ connected to external pin, VREF+ 10 = A/D VREF+ connected to internal signal, FVR BUF2 11 = Reserved bit 1-0 NVCFG<1:0>: Negative Voltage Reference Configuration bits 00 = A/D VREF- connected to internal signal, AVSS 01 = A/D VREF- connected to external pin, VREF- 10 = Reserved 11 = Reserved  2012-2014 Microchip Technology Inc. DS30000684B-page 295

PIC18(L)F2X/45K50 REGISTER 18-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT<2:0> ADCS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition time select bits. Acquisition time is the duration that the A/D charge holding capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until conversions begins. 000 = 0(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) Note 1: When the A/D clock source is selected as FRC then the start of conversion is delayed by one instruction cycle after the GO/DONE bit is set to allow the SLEEP instruction to be executed. DS30000684B-page 296  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 18-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 18-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES<1:0> r r r r r r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 18-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x r r r r r r ADRES<9:8> bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 18-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result  2012-2014 Microchip Technology Inc. DS30000684B-page 297

PIC18(L)F2X/45K50 18.4 A/D Acquisition Requirements an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition For the ADC to meet its specified accuracy, the charge time, Equation18-1 may be used. This equation holding capacitor (CHOLD) must be allowed to fully assumes that 1/2 LSb error is used (1024 steps for the charge to the input channel voltage level. The Analog ADC). The 1/2 LSb error is the maximum error allowed Input model is shown in Figure18-5. The source for the ADC to meet its specified resolution. impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure18-5. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), EQUATION 18-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 3.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 5µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– 2---0---4---7--- = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb –TC  ---------- VAPPLIED1–eRC = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– 2---0---4---7--- ;combining [1] and [2]   Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/2047) = –13.5pF1k+700+10k ln(0.0004885) = 1.20µs Therefore: TACQ = 5µs+1.20µs+50°C- 25°C0.05s/°C = 7.45µs Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification. DS30000684B-page 298  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 18-5: ANALOG INPUT MODEL VDD Sampling Switch Rs ANx RIC  1k SS Rss VA CPIN I LEAKAGE(1) CHOLD = 13.5 pF 5 pF Discharge VSS/VREF- Switch 3.5V Legend: CPIN = Input Capacitance 3.0V I LEAKAGE = Lvaeraiokaugs eju cnucrtrieonnts at the pin due to DD 2.5V V RIC = Interconnect Resistance 2.0V SS = Sampling Switch 1.5V CHOLD = Sample/Hold Capacitance .1 1 10 100 Rss (k) Note 1: See Section29.0 “Electrical Specifications”. FIGURE 18-6: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh de 3FCh 1/2 LSB ideal o C 3FBh ut p ut Full-Scale O C 004h Transition D A 003h 002h 001h 000h Analog Input Voltage 1/2 LSB ideal VSS/VREF- Zero-Scale VDD/VREF+ Transition  2012-2014 Microchip Technology Inc. DS30000684B-page 299

PIC18(L)F2X/45K50 TABLE 18-2: REGISTERS ASSOCIATED WITH A/D OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page ADCON0 — CHS<4:0> GO/DONE ADON 294 ADCON1 TRIGSEL — — — PVCFG<1:0> NVCFG<1:0> 295 ADCON2 ADFM — ACQT<2:0> ADCS<2:0> 296 ADRESH A/D Result, High Byte 297 ADRESL A/D Result, Low Byte 297 ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 147 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148 ANSELC ANSC7 ANSC6 — — — ANSC2 — — 148 ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 148 ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 149 CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 322 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 149 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 149 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by this module. Note 1: Available on PIC18(L)F45K50 devices. TABLE 18-3: CONFIGURATION REGISTERS ASSOCIATED WITH THE ADC MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by the ADC module. DS30000684B-page 300  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 19.0 COMPARATOR MODULE FIGURE 19-1: SINGLE COMPARATOR Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and VIN+ + providing a digital indication of their relative magnitudes. Output The comparators are very useful mixed signal building VIN- – blocks because they provide analog functionality independent of the program execution. The analog comparator module includes the following features: • Independent comparator control VIN- • Programmable input selection VIN+ • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change Output • Wake-up from Sleep • Programmable Speed/Power optimization • PWM shutdown Note: The black areas of the output of the • Programmable and fixed voltage reference comparator represents the uncertainty 19.1 Comparator Overview due to input offsets and response time. A single comparator is shown in Figure19-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level.  2012-2014 Microchip Technology Inc. DS30000684B-page 301

PIC18(L)F2X/45K50 FIGURE 19-2: COMPARATOR C1/C2 SIMPLIFIED BLOCK DIAGRAM CxCH<1:0> 2 CxON(1) To CMxCON0 (CxOUT) CxSP C12IN0- 0 CM2CON1 (MCxOUT) D Q C12IN1- 1 CxVIN- Q1(2),(3) EN - C12IN2- 2 Cx CxVIN+ + C12IN3- 3 D Q Q3(2) To Interrupts EN (CxIF) CxR CL Read or Write of CMxCON0 CxIN+ 0 Reset async_CXOUT DAC Output 0 1 CxPOL to PWM Logic CxSYNC CxOE TRIS bit FVR BUF1 1 CXVREF 0 CXRSEL D Q 1 CxOUT Timer1 Clock sync_CxOUT - to SR Latch - to TxG MUX(4) Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. 4: Synchronized comparator output should not be used to gate Timer1 in conjunction with synchronized T1CKI. DS30000684B-page 302  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 19.2 Comparator Control Each comparator has a separate control and Note1: The CxOE bit overrides the PORT data Configuration register: CM1CON0 for Comparator C1 latch. Setting the CxON has no impact on and CM2CON0 for Comparator C2. In addition, the port override. Comparator C2 has a second control register, 2: The internal output of the comparator is CM2CON1, for controlling the interaction with Timer1 and latched with each instruction cycle. simultaneous reading of both comparator outputs. Unless otherwise specified, external The CM1CON0 and CM2CON0 registers (see outputs are not latched. Register19-1) contain the control and status bits for the following: 19.2.5 COMPARATOR OUTPUT POLARITY • Enable Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The • Input selection polarity of the comparator output can be inverted by • Reference selection setting the CxPOL bit of the CMxCON0 register. • Output selection Clearing the CxPOL bit results in a non-inverted output. • Output polarity Table19-1 shows the output state versus input • Speed selection conditions, including polarity control. 19.2.1 COMPARATOR ENABLE TABLE 19-1: COMPARATOR OUTPUT STATE VS. INPUT Setting the CxON bit of the CMxCON0 register enables CONDITIONS the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current Input Condition CxPOL CxOUT consumption. CxVIN- > CxVIN+ 0 0 19.2.2 COMPARATOR INPUT SELECTION CxVIN- < CxVIN+ 0 1 The CxCH<1:0> bits of the CMxCON0 register direct CxVIN- > CxVIN+ 1 1 one of four analog input pins to the comparator CxVIN- < CxVIN+ 1 0 inverting input. 19.2.6 COMPARATOR SPEED SELECTION Note: To use CxIN+ and C12INx- pins as analog inputs, the appropriate bits must be set in The trade-off between speed or power can be the ANSEL register and the optimized during program execution with the CxSP corresponding TRIS bits must also be set control bit. The default state for this bit is ‘1’ which to disable the output drivers. selects the normal speed mode. Device power consumption can be optimized at the cost of slower 19.2.3 COMPARATOR REFERENCE comparator propagation delay by clearing the CxSP bit SELECTION to ‘0’. Setting the CxR bit of the CMxCON0 register directs an 19.3 Comparator Response Time internal voltage reference or an analog input pin to the non-inverting input of the comparator. See The comparator output is indeterminate for a period of Section22.0 “Fixed Voltage Reference (FVR)” for time after the change of an input source or the selection more information on the Internal Voltage Reference of a new reference voltage. This period is referred to as module. the response time. The response time of the comparator differs from the settling time of the voltage 19.2.4 COMPARATOR OUTPUT reference. Therefore, both of these times must be SELECTION considered when determining the total response time The output of the comparator can be monitored by to a comparator input change. See the Comparator and reading either the CxOUT bit of the CMxCON0 register Voltage Reference Specifications in Section29.0 or the MCxOUT bit of the CM2CON1 register. In order “Electrical Specifications” for more details. to make the output available for an external connection, the following conditions must be true: • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set  2012-2014 Microchip Technology Inc. DS30000684B-page 303

PIC18(L)F2X/45K50 19.4 Comparator Interrupt Operation 19.4.1 PRESETTING THE MISMATCH LATCHES The comparator interrupt flag will be set whenever there is a change in the output value of the comparator. The comparator mismatch latches can be preset to the Changes are recognized by means of a mismatch desired state before the comparators are enabled. circuit which consists of two latches and an exclusive- When the comparator is off the CxPOL bit controls the or gate (see Figure19-2). The first latch is updated with CxOUT level. Set the CxPOL bit to the desired CxOUT the comparator output value, when the CMxCON0 non-interrupt level while the CxON bit is cleared. Then, register is read or written. The value is latched on the configure the desired CxPOL level in the same instruc- third cycle of the system clock, also known as Q3. This tion that the CxON bit is set. Since all register writes are first latch retains the comparator value until another performed as a read-modify-write, the mismatch read or write of the CMxCON0 register occurs or a latches will be cleared during the instruction read Reset takes place. The second latch is updated with phase and the actual configuration of the CxON and the comparator output value on every first cycle of the CxPOL bits will be occur in the final write phase. system clock, also known as Q1. When the output value of the comparator changes, the second latch is FIGURE 19-3: COMPARATOR updated and the output values of both latches no INTERRUPT TIMING W/O longer match one another, resulting in a mismatch CMxCON0 READ condition. The latch outputs are fed directly into the inputs of an exclusive-or gate. This mismatch condition Q1 is detected by the exclusive-or gate and sent to the Q3 interrupt circuitry. The mismatch condition will persist CxIN+ TRT until the first latch value is updated by performing a CxIN read of the CMxCON0 register or the comparator Set CxIF (edge) output returns to the previous state. CxIF Note 1: A write operation to the CMxCON0 Reset by Software register will also clear the mismatch condition because all writes include a read FIGURE 19-4: COMPARATOR operation at the beginning of the write INTERRUPT TIMING WITH cycle. CMxCON0 READ 2: Comparator interrupts will operate correctly regardless of the state of CxOE. Q1 When the mismatch condition occurs, the comparator Q3 interrupt flag is set. The interrupt flag is triggered by the CxIN+ TRT edge of the changing value coming from the exclusive- CxOUT or gate. This means that the interrupt flag can be reset Set CxIF (edge) once it is triggered without the additional step of read- CxIF ing or writing the CMxCON0 register to clear the mis- match latches. When the mismatch registers are Cleared by CMxCON0 Read Reset by Software cleared, an interrupt will occur upon the comparator’s return to the previous state, otherwise no interrupt will be generated. Note1: If a change in the CMxCON0 register Software will need to maintain information about the (CxOUT) should occur when a read oper- status of the comparator output, as read from the ation is being executed (start of the Q2 CMxCON0 register, or CM2CON1 register, to determine cycle), then the CxIF interrupt flag of the the actual change that has occurred. See Figures19-3 PIR2 register may not get set. and19-4. 2: When either comparator is first enabled, The CxIF bit of the PIR2 register is the comparator bias circuitry in the comparator module interrupt flag. This bit must be reset by software by may cause an invalid output from the clearing it to ‘0’. Since it is also possible to write a ‘1’ to comparator until the bias circuitry is this register, an interrupt can be generated. stable. Allow about 1 s for bias settling In mid-range Compatibility mode the CxIE bit of the then clear the mismatch condition and PIE2 register and the PEIE/GIEL and GIE/GIEH bits of interrupt flags before enabling comparator the INTCON register must all be set to enable compar- interrupts. ator interrupts. If any of these bits are cleared, the inter- rupt is not enabled, although the CxIF bit of the PIR2 register will still be set if an interrupt condition occurs. DS30000684B-page 304  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 19.5 Operation During Sleep 19.7 Analog Input Connection Considerations The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current A simplified circuit for an analog input is shown in consumed by the comparator is shown separately in Figure19-5. Since the analog input pins share their Section29.0 “Electrical Specifications”. If the connection with a digital input, they have reverse comparator is not used to wake the device, power biased ESD protection diodes to VDD and VSS. The consumption can be minimized while in Sleep mode by analog input, therefore, must be between VSS and VDD. turning off the comparator. Each comparator is turned off If the input voltage deviates from this range by more by clearing the CxON bit of the CMxCON0 register. than 0.6V in either direction, one of the diodes is A change to the comparator output can wake-up the forward biased and a latch-up may occur. device from Sleep. To enable the comparator to wake A maximum source impedance of 10 k is recommended the device from Sleep, the CxIE bit of the PIE2 register for the analog sources. Also, any external component and the PEIE/GIEL bit of the INTCON register must be connected to an analog input pin, such as a capacitor or set. The instruction following the SLEEP instruction a Zener diode, should have very little leakage current to always executes following a wake from Sleep. If the minimize inaccuracies introduced. GIE/GIEH bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. Note1: When reading a PORT register, all pins 19.6 Effects of a Reset configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will A device Reset forces the CMxCON0 and CM2CON1 convert as an analog input, according to registers to their Reset states. This forces both the input specification. comparators and the voltage references to their Off 2: Analog levels on any pin defined as a states.Comparator Control Registers. digital input, may cause the input buffer to consume more current than is specified. FIGURE 19-5: ANALOG INPUT MODEL VDD Rs < 10K VT  0.6V RIC To Comparator AIN VA C5 PpIFN VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage Note1: See Section29.0 “Electrical Specifications”.  2012-2014 Microchip Technology Inc. DS30000684B-page 305

PIC18(L)F2X/45K50 19.8 Additional Comparator Features 19.8.3 SYNCHRONIZING COMPARATOR OUTPUT TO TIMER1 There are four additional comparator features: The Comparator Cx output can be synchronized with • Simultaneous read of comparator outputs Timer1 by setting the CxSYNC bit of the CM2CON1 • Internal reference selection register. When enabled, the Cx output is latched on • Hysteresis selection the falling edge of the Timer1 source clock. To prevent • Output Synchronization a race condition when gating Timer1 clock with the comparator output, Timer1 increments on the rising 19.8.1 SIMULTANEOUS COMPARATOR edge of its clock source, and the falling edge latches OUTPUT READ the comparator output. See the Comparator Block Diagram (Figure19-2) and the Timer1 Block Diagram The MC1OUT and MC2OUT bits of the CM2CON1 (Figure13-1) for more information. register are mirror copies of both comparator outputs. The ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers. Note1: The comparator synchronized output should not be used to gate the external Note1: Obtaining the status of C1OUT or Timer1 clock when the Timer1 C2OUT by reading CM2CON1 does not synchronizer is enabled. affect the comparator interrupt mismatch 2: The Timer1 prescale should be set to 1:1 registers. when synchronizing the comparator 19.8.2 INTERNAL REFERENCE output as unexpected results may occur with other prescale values. SELECTION There are two internal voltage references available to the non-inverting input of each comparator. One of these is the Fixed Voltage Reference (FVR) and the other is the variable Digital-to-Analog Converter (DAC). The CxRSEL bit of the CM2CON1 register determines which of these references is routed to the Comparator Voltage reference output (CXVREF). Further routing to the comparator is accomplished by the CxR bit of the CMxCON0 register. See Section22.0 “Fixed Voltage Reference (FVR)” and Figure19-2 for more detail. DS30000684B-page 306  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 19.9 Register Definitions: Comparator Control REGISTER 19-1: CMxCON0: COMPARATOR x CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 CxON CxOUT CxOE CxPOL CxSP CxR CxCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CxON: Comparator Cx Enable bit 1 = Comparator Cx is enabled 0 = Comparator Cx is disabled bit 6 CxOUT: Comparator Cx Output bit If CxPOL = 1 (inverted polarity): CxOUT = 0 when CxVIN+ > CxVIN- CxOUT = 1 when CxVIN+ < CxVIN- If CxPOL = 0 (non-inverted polarity): CxOUT = 1 when CxVIN+ > CxVIN- CxOUT = 0 when CxVIN+ < CxVIN- bit 5 CxOE: Comparator Cx Output Enable bit 1 =CxOUT is present on the CxOUT pin(1) 0 =CxOUT is internal only bit 4 CxPOL: Comparator Cx Output Polarity Select bit 1 = CxOUT logic is inverted 0 = CxOUT logic is not inverted bit 3 CxSP: Comparator Cx Speed/Power Select bit 1 = Cx operates in normal power, higher speed mode 0 = Cx operates in low-power, low-speed mode bit 2 CxR: Comparator Cx Reference Select bit (non-inverting input) 1 = CxVIN+ connects to CXVREF output 0 = CxVIN+ connects to C12IN+ pin bit 1-0 CxCH<1:0>: Comparator Cx Channel Select bit 00 = C12IN0- pin of Cx connects to CxVIN- 01 = C12IN1- pin of Cx connects to CXVIN- 10 = C12IN2- pin of Cx connects to CxVIN- 11 = C12IN3- pin of Cx connects to CxVIN- Note 1: Comparator output requires the following three conditions: CxOE = 1, CxON = 1 and corresponding port TRIS bit = 0.  2012-2014 Microchip Technology Inc. DS30000684B-page 307

PIC18(L)F2X/45K50 REGISTER 19-2: CM2CON1: COMPARATOR 1 AND 2 CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 MC1OUT MC2OUT C1RSEL C2RSEL — — C1SYNC C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 C1RSEL: Comparator C1 Reference Select bit 1 = FVR BUF1 routed to C1VREF input 0 = DAC routed to C1VREF input bit 4 C2RSEL: Comparator C2 Reference Select bit 1 = FVR BUF1 routed to C2VREF input 0 = DAC routed to C2VREF input bit 3-2 Reserved: Maintain these bits clear bit 1 C1SYNC: C1 Output Synchronous Mode bit 1 = C1 output is synchronized to rising edge of TMR1 clock (T1CLK) 0 = C1 output is asynchronous bit 0 C2SYNC: C2 Output Synchronous Mode bit 1 = C2 output is synchronized to rising edge of TMR1 clock (T1CLK) 0 = C2 output is asynchronous DS30000684B-page 308  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 19-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 147 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 308 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH<1:0> 307 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH<1:0> 307 VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 334 VREFCON2 — — — DACR<4:0> 335 VREFCON0 FVREN FVRST FVRS<1:0> — — — — 331 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by the comparator module.  2012-2014 Microchip Technology Inc. DS30000684B-page 309

PIC18(L)F2X/45K50 20.0 CHARGE TIME • High precision time measurement MEASUREMENT UNIT (CTMU) • Time delay of external or internal signal asynchronous to system clock The Charge Time Measurement Unit (CTMU) is a • Accurate current source suitable for capacitive flexible analog module that provides accurate measurement differential time measurement between pulse sources, The CTMU works in conjunction with the A/D Converter as well as asynchronous pulse generation. By working to provide up to 28(1) channels for time or charge with other on-chip analog modules, the CTMU can be measurement, depending on the specific device and used to precisely measure time, measure capacitance, the number of A/D channels available. When config- measure relative changes in capacitance or generate ured for time delay, the CTMU is connected to the output pulses with a specific time delay. The CTMU is C12IN1- input of Comparator 2. The level-sensitive ideal for interfacing with capacitive-based sensors. input edge sources can be selected from four sources: The module includes the following key features: two external input pins (CTED1/CTED2) or the ECCP1/ • Up to 28(1) channels available for capacitive or CCP2 Special Event Triggers. time measurement input Figure20-1 provides a block diagram of the CTMU. • On-chip precision current source • Four-edge input trigger sources • Polarity control for each edge source Note1: PIC18(L)F2XK50 devices have up to 17 • Control of edge sequence channels available. • Control of response to edges FIGURE 20-1: CTMU BLOCK DIAGRAM CTMUCONH/CTMUCONL CTMUICON EDGEN EDGSEQEN EDG1SELx ITRIM<5:0> TGEN EDG1POL IRNG<1:0> IDISSEN EDG2SELx EDG1STAT CTTRIG Current Source EDG2POL EDG2STAT CTED1 Edge CTMU Control Control CTED2 Logic Current Logic Control CCP2 Pulse CTPLS ECCP1 Generator Comparator 2 Output Comparator C1/C2 Input A/D Converter A/D Special Event Trigger DS30000684B-page 310  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 20.1 CTMU Operation 20.1.2 CURRENT SOURCE The CTMU works by using a fixed current source to At the heart of the CTMU is a precision current source, charge a circuit. The type of circuit depends on the type designed to provide a constant reference for measure- of measurement being made. In the case of charge ments. The level of current is user selectable across measurement, the current is fixed and the amount of three ranges or a total of two orders of magnitude, with time the current is applied to the circuit is fixed. The the ability to trim the output in ±2% increments amount of voltage read by the A/D is then a measure- (nominal). The current range is selected by the ment of the capacitance of the circuit. In the case of IRNG<1:0> bits (CTMUICON<1:0>), with a value of time measurement, the current, as well as the capaci- ‘01’ representing the lowest range. tance of the circuit, is fixed. In this case, the voltage Current trim is provided by the ITRIM<5:0> bits read by the A/D is then representative of the amount of (CTMUICON<7:2>). These six bits allow trimming of time elapsed from the time the current source starts the current source in steps of approximately 2% per and stops charging the circuit. step. Note that half of the range adjusts the current If the CTMU is being used as a time delay, both capaci- source positively and the other half reduces the current tance and current source are fixed, as well as the voltage source. A value of ‘000000’ is the neutral position (no supplied to the comparator circuit. The delay of a signal change). A value of ‘100001’ is the maximum negative is determined by the amount of time it takes the voltage adjustment (approximately -62%) and ‘011111’ is the to charge to the comparator threshold voltage. maximum positive adjustment (approximately +62%). 20.1.1 THEORY OF OPERATION 20.1.3 EDGE SELECTION AND CONTROL The operation of the CTMU is based on the following CTMU measurements are controlled by edge events equation for charge: occurring on the module’s two input channels. Each channel, referred to as Edge 1 and Edge 2, can be con- dV I = C • figured to receive input pulses from one of the edge dT input pins (CTED1 and CTED2), Timer1 or Output Compare Module 1. The input channels are level- More simply, the amount of charge measured in sensitive, responding to the instantaneous level on the coulombs in a circuit is defined as current in amperes channel rather than a transition between levels. The (I) multiplied by the amount of time in seconds that the inputs are selected using the EDG1SEL and EDG2SEL current flows (t). Charge is also defined as the bit pairs (CTMUCONL<3:2> and <6:5>). capacitance in farads (C) multiplied by the voltage of the circuit (V). It follows that: In addition to source, each channel can be configured for event polarity using the EDGE2POL and EDGE1POL It = CV. bits (CTMUCONL<7,4>). The input channels can also The CTMU module provides a constant, known current be filtered for an edge event sequence (Edge 1 occur- source. The A/D Converter is used to measure (V) in ring before Edge 2) by setting the EDGSEQEN bit the equation, leaving two unknowns: capacitance (C) (CTMUCONH<2>). and time (t). The above equation can be used to calcu- late capacitance or time, by either the relationship using the known fixed capacitance of the circuit: t = CVI or by: C = ItV using a fixed time that the current source is applied to the circuit.  2012-2014 Microchip Technology Inc. DS30000684B-page 311

PIC18(L)F2X/45K50 20.1.4 EDGE STATUS 20.2 CTMU Module Initialization The CTMUCONL register also contains two status bits: The following sequence is a general guideline used to EDG2STAT and EDG1STAT (CTMUCONL<1:0>). initialize the CTMU module: Their primary function is to show if an edge response 1. Select the current source range using the IRNG has occurred on the corresponding channel. The bits (CTMUICON<1:0>). CTMU automatically sets a particular bit when an edge response is detected on its channel. The level-sensitive 2. Adjust the current source trim using the ITRIM nature of the input channels also means that the status bits (CTMUICON<7:2>). bits become set immediately if the channel’s configura- 3. Configure the edge input sources for Edge 1 and tion is changed and is the same as the channel’s Edge 2 by setting the EDG1SEL and EDG2SEL current state. bits (CTMUCONL<3:2 and 6:5>). The module uses the edge status bits to control the cur- 4. Configure the input polarities for the edge inputs rent source output to external analog modules (such as using the EDG1POL and EDG2POL bits the A/D Converter). Current is only supplied to external (CTMUCONL<4,7>). The default configuration modules when only one (but not both) of the status bits is for negative edge polarity (high-to-low is set, and shuts current off when both bits are either transitions). set or cleared. This allows the CTMU to measure cur- 5. Enable edge sequencing using the EDGSEQEN rent only during the interval between edges. After both bit (CTMUCONH<2>). By default, edge status bits are set, it is necessary to clear them before sequencing is disabled. another measurement is taken. Both bits should be 6. Select the operating mode (Measurement or cleared simultaneously, if possible, to avoid re-enabling Time Delay) with the TGEN bit. The default the CTMU current source. mode is Time/Capacitance Measurement. In addition to being set by the CTMU hardware, the 7. Discharge the connected circuit by setting the edge status bits can also be set by software. This is IDISSEN bit (CTMUCONH<1>); after waiting a also the user’s application to manually enable or sufficient time for the circuit to discharge, clear disable the current source. Setting either one (but not IDISSEN. both) of the bits enables the current source. Setting or 8. Disable the module by clearing the CTMUEN bit clearing both bits at once disables the source. (CTMUCONH<7>). 9. Enable the module by setting the CTMUEN bit. 20.1.5 INTERRUPTS 10. Clear the Edge Status bits: EDG2STAT and The CTMU sets its interrupt flag (PIR3<3>) whenever EDG1STAT (CTMUCONL<1:0>). the current source is enabled, then disabled. An 11. Enable both edge inputs by setting the EDGEN interrupt is generated only if the corresponding bit (CTMUCONH<3>). interrupt enable bit (PIE3<3>) is also set. If edge sequencing is not enabled (i.e., Edge 1 must occur Depending on the type of measurement or pulse before Edge 2), it is necessary to monitor the edge generation being performed, one or more additional Status bits and determine which edge occurred last and modules may also need to be initialized and configured caused the interrupt. with the CTMU module: • Edge Source Generation: In addition to the external edge input pins, both Timer1 and the Output Compare/PWM1 module can be used as edge sources for the CTMU. • Capacitance or Time Measurement: The CTMU module uses the A/D Converter to measure the voltage across a capacitor that is connected to one of the analog input channels. • Pulse Generation: When generating system clock independent output pulses, the CTMU module uses Comparator 2 and the associated comparator voltage reference. DS30000684B-page 312  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 20.3 Calibrating the CTMU Module FIGURE 20-2: CTMU CURRENT SOURCE CALIBRATION CIRCUIT The CTMU requires calibration for precise measurements of capacitance and time, as well as for accurate time delay. If the application only requires PIC18(L)FXXK50 Device measurement of a relative change in capacitance or CTMU Current Source time, calibration is usually not necessary. An example of this type of application would include a capacitive touch switch, in which the touch circuit has a baseline capacitance, and the added capacitance of the human body changes the overall capacitance of a circuit. A/D Converter If actual capacitance or time measurement is required, two hardware calibrations must take place: the current source needs calibration to set it to a precise current, ANx A/D and the circuit being measured needs calibration to measure and/or nullify all other capacitance other than RCAL MUX that to be measured. 20.3.1 CURRENT SOURCE CALIBRATION A value of 70% of full-scale voltage is chosen to make The current source on the CTMU module is trimmable. sure that the A/D Converter was in a range that is well Therefore, for precise measurements, it is possible to above the noise floor. Keep in mind that if an exact cur- measure and adjust this current source by placing a rent is chosen, that is to incorporate the trimming bits high precision resistor, RCAL, onto an unused analog channel. An example circuit is shown in Figure20-2. from CTMUICON, the resistor value of RCAL may need The current source measurement is performed using to be adjusted accordingly. RCAL may also be adjusted the following steps: to allow for available resistor values. RCAL should be of the highest precision available, keeping in mind the 1. Initialize the A/D Converter. amount of precision needed for the circuit that the 2. Initialize the CTMU. CTMU will be used to measure. A recommended 3. Enable the current source by setting EDG1STAT minimum would be 0.1% tolerance. (CTMUCONL<0>). The following examples show one typical method for 4. Issue settling time delay. performing a CTMU current calibration. Example20-1 5. Perform A/D conversion. demonstrates how to initialize the A/D Converter and 6. Calculate the current source current using the CTMU; this routine is typical for applications using I=V/RCAL, where RCAL is a high precision both modules. Example20-2 demonstrates one resistance and V is measured by performing an method for the actual calibration routine. A/D conversion. The CTMU current source may be trimmed with the trim bits in CTMUICON using an iterative process to get an exact desired current. Alternatively, the nominal value without adjustment may be used; it may be stored by the software for use in all subsequent capacitive or time measurements. To calculate the value for RCAL, the nominal current must be chosen, and then the resistance can be calculated. For example, if the A/D Converter reference voltage is 3.3V, use 70% of full scale, or 2.31V as the desired approximate voltage to be read by the A/D Converter. If the range of the CTMU current source is selected to be 0.55 A, the resistor value needed is cal- culated as RCAL=2.31V/0.55A, for a value of 4.2MΩ. Similarly, if the current source is chosen to be 5.5A, RCAL would be 420,000Ω, and 42,000Ω if the current source is set to 55A.  2012-2014 Microchip Technology Inc. DS30000684B-page 313

PIC18(L)F2X/45K50 EXAMPLE 20-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.h" /**************************************************************************/ /*Set up CTMU *****************************************************************/ /**************************************************************************/ void setup(void) { //CTMUCONH/1 - CTMU Control registers CTMUCONH = 0x00; //make sure CTMU is disabled CTMUCONL = 0x90; //CTMU continues to run when emulator is stopped,CTMU continues //to run in idle mode,Time Generation mode disabled, Edges are blocked //No edge sequence order, Analog current source not grounded, trigger //output disabled, Edge2 polarity = positive level, Edge2 source = //source 0, Edge1 polarity = positive level, Edge1 source = source 0, //CTMUICON - CTMU Current Control Register CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment /**************************************************************************/ //Set up AD converter; /**************************************************************************/ TRISA=0x04; //set channel 2 as an input // Configure AN2 as an analog channel ANSELAbits.ANSA2=1; TRISAbits.TRISA2=1; // ADCON2 ADCON2bits.ADFM=1; // Results format 1= Right justified ADCON2bits.ACQT=1; // Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD ADCON2bits.ADCS=2; // Clock conversion bits 6= FOSC/64 2=FOSC/32 // ADCON1 ADCON1bits.PVCFG0 =0; // Vref+ = AVdd ADCON1bits.NVCFG1 =0; // Vref- = AVss // ADCON0 ADCON0bits.CHS=2; // Select ADC channel ADCON0bits.ADON=1; // Turn on ADC } DS30000684B-page 314  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 EXAMPLE 20-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 //@ 8MHz = 125uS. #define DELAY for(i=0;i<COUNT;i++) #define RCAL .027 //R value is 4200000 (4.2M) //scaled so that result is in //1/100th of uA #define ADSCALE 1023 //for unsigned conversion 10 sig bits #define ADREF 3.3 //Vdd connected to A/D Vr+ int main(void) { int i; int j = 0; //index for loop unsigned int Vread = 0; double VTot = 0; float Vavg=0, Vcal=0, CTMUISrc = 0; //float values stored for calcs //assume CTMU and A/D have been set up correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero CTMUCONLbits.EDG2STAT = 0; for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag VTot += Vread; //Add the reading to the total } Vavg = (float)(VTot/10.000); //Average of 10 readings Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA }  2012-2014 Microchip Technology Inc. DS30000684B-page 315

PIC18(L)F2X/45K50 20.3.2 CAPACITANCE CALIBRATION There is a small amount of capacitance from the internal A/D Converter sample capacitor as well as stray capacitance from the circuit board traces and pads that affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by making sure the desired capacitance to be measured has been removed. The measurement is then performed using the following steps: 1. Initialize the A/D Converter and the CTMU. 2. Set EDG1STAT (=1). 3. Wait for a fixed delay of time t. 4. Clear EDG1STAT. 5. Perform an A/D conversion. 6. Calculate the stray and A/D sample capacitances: C = C +C = ItV OFFSET STRAY AD where I is known from the current source measurement step, t is a fixed delay and V is measured by performing an A/D conversion. This measured value is then stored and used for calculations of time measurement or subtracted for capacitance measurement. For calibration, it is expected that the capacitance of CSTRAY+CAD is approximately known. CAD is approximately 4pF. An iterative process may need to be used to adjust the time, t, that the circuit is charged to obtain a reasonable voltage reading from the A/D Converter. The value of t may be determined by setting COFFSET to a theoretical value, then solving for t. For example, if CSTRAY is theoretically calculated to be 11pF, and V is expected to be 70% of VDD, or 2.31V, then t would be: (4 pF + 11 pF) • 2.31V/0.55 A or 63s. See Example20-3 for a typical routine for CTMU capacitance calibration. DS30000684B-page 316  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 EXAMPLE 20-3: CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 25 //@ 8MHz INTFRC = 62.5 us. #define ETIME COUNT*2.5 //time in uS #define DELAY for(i=0;i<COUNT;i++) #define ADSCALE 1023 //for unsigned conversion 10 sig bits #define ADREF 3.3 //Vdd connected to A/D Vr+ #define RCAL .027 //R value is 4200000 (4.2M) //scaled so that result is in //1/100th of uA int main(void) { int i; int j = 0; //index for loop unsigned int Vread = 0; float CTMUISrc, CTMUCap, Vavg, VTot, Vcal; //assume CTMU and A/D have been set up correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero CTMUCONLbits.EDG2STAT = 0; for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag VTot += Vread; //Add the reading to the total } Vavg = (float)(VTot/10.000); //Average of 10 readings Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA CTMUCap = (CTMUISrc*ETIME/Vcal)/100; }  2012-2014 Microchip Technology Inc. DS30000684B-page 317

PIC18(L)F2X/45K50 20.4 Measuring Capacitance with the 20.4.2 RELATIVE CHARGE CTMU MEASUREMENT An application may not require precise capacitance There are two separate methods of measuring measurements. For example, when detecting a valid capacitance with the CTMU. The first is the absolute press of a capacitance-based switch, detecting a rela- method, in which the actual capacitance value is tive change of capacitance is of interest. In this type of desired. The second is the relative method, in which application, when the switch is open (or not touched), the actual capacitance is not needed, rather an the total capacitance is the capacitance of the combina- indication of a change in capacitance is required. tion of the board traces, the A/D Converter, etc. A larger 20.4.1 ABSOLUTE CAPACITANCE voltage will be measured by the A/D Converter. When MEASUREMENT the switch is closed (or is touched), the total capacitance is larger due to the addition of the For absolute capacitance measurements, both the capacitance of the human body to the above listed current and capacitance calibration steps found in capacitances, and a smaller voltage will be measured Section 20.3 “Calibrating the CTMU Module” by the A/D Converter. should be followed. Capacitance measurements are Detecting capacitance changes is easily accomplished then performed using the following steps: with the CTMU using these steps: 1. Initialize the A/D Converter. 1. Initialize the A/D Converter and the CTMU. 2. Initialize the CTMU. 2. Set EDG1STAT. 3. Set EDG1STAT. 3. Wait for a fixed delay. 4. Wait for a fixed delay, T. 4. Clear EDG1STAT. 5. Clear EDG1STAT. 5. Perform an A/D conversion. 6. Perform an A/D conversion. The voltage measured by performing the A/D 7. Calculate the total capacitance, CTOTAL = (I * T)/V, conversion is an indication of the relative capacitance. where I is known from the current source Note that in this case, no calibration of the current measurement step (see Section 20.3.1 “Current source or circuit capacitance measurement is needed. Source Calibration”), T is a fixed delay and V is See Example20-4 for a sample software routine for a measured by performing an A/D conversion. capacitive touch switch. 8. Subtract the stray and A/D capacitance (COFFSET from Section 20.3.2 “Capacitance Calibration”) from CTOTAL to determine the measured capacitance. DS30000684B-page 318  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 EXAMPLE 20-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define COUNT 500 //@ 8MHz = 125uS. #define DELAY for(i=0;i<COUNT;i++) #define OPENSW 1000 //Un-pressed switch value #define TRIP 300 //Difference between pressed //and un-pressed switch #define HYST 65 //amount to change //from pressed to un-pressed #define PRESSED 1 #define UNPRESSED 0 int main(void) { unsigned int Vread; //storage for reading unsigned int switchState; int i; //assume CTMU and A/D have been set up correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; // Enable the CTMU CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero CTMUCONLbits.EDG2STAT = 0; CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D if(Vread < OPENSW - TRIP) { switchState = PRESSED; } else if(Vread > OPENSW - TRIP + HYST) { switchState = UNPRESSED; } }  2012-2014 Microchip Technology Inc. DS30000684B-page 319

PIC18(L)F2X/45K50 20.5 Measuring Time with the CTMU It is assumed that the time measured is small enough Module that the capacitance, COFFSET, provides a valid voltage to the A/D Converter. For the smallest time measure- Time can be precisely measured after the ratio (C/I) is ment, always set the A/D Channel Select register measured from the current and capacitance calibration (AD1CHS) to an unused A/D channel; the correspond- step by following these steps: ing pin for which is not connected to any circuit board 1. Initialize the A/D Converter and the CTMU. trace. This minimizes added stray capacitance, keep- ing the total circuit capacitance close to that of the A/D 2. Set EDG1STAT. Converter itself (4-5pF). To measure longer time 3. Set EDG2STAT. intervals, an external capacitor may be connected to an 4. Perform an A/D conversion. A/D channel and this channel selected when making a 5. Calculate the time between edges as T = (C/I) * V, time measurement. where I is calculated in the current calibration step (Section 20.3.1 “Current Source Calibration”), C is calculated in the capacitance calibration step (Section 20.3.2 “Capacitance Calibration”) and V is measured by performing the A/D conversion. FIGURE 20-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC18(L)FXXK22 Device CTMU CTED1 EDG1 Current Source CTED2 EDG2 Output Pulse A/D Converter ANX CAD RPR DS30000684B-page 320  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 20.6 Creating a Delay with the CTMU An example use of this feature is for interfacing with Module variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the pulse width output A unique feature on board the CTMU module is its on CTPLS will vary. The CTPLS output pin can be con- ability to generate system clock independent output nected to an input capture pin and the varying pulse pulses based on an external capacitor value. This is width is measured to determine the humidity in the accomplished using the internal comparator voltage application. reference module, Comparator 2 input pin and an Follow these steps to use this feature: external capacitor. The pulse is output onto the CTPLS pin. To enable this mode, set the TGEN bit. 1. Initialize Comparator 2. 2. Initialize the comparator voltage reference. See Figure20-4 for an example circuit. CPULSE is chosen by the user to determine the output pulse width 3. Initialize the CTMU and enable time delay on CTPLS. The pulse width is calculated by generation by setting the TGEN bit. T=(CPULSE/I)*V, where I is known from the current 4. Set EDG1STAT. source measurement step (Section 20.3.1 “Current 5. When CPULSE charges to the value of the voltage Source Calibration”) and V is the internal reference reference trip point, an output pulse is generated voltage (CVREF). on CTPLS. FIGURE 20-4: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC18(L)FXXK22 Device CTMU CTED1 EDG1 CTPLS Current Source Comparator C12IN1- C2 CPULSE CVREF 20.7 Operation During Sleep/Idle 20.7.2 IDLE MODE Modes The behavior of the CTMU in Idle mode is determined by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL 20.7.1 SLEEP MODE is cleared, the module will continue to operate in Idle When the device enters any Sleep mode, the CTMU mode. If CTMUSIDL is set, the module’s current source module current source is always disabled. If the CTMU is disabled when the device enters Idle mode. If the is performing an operation that depends on the current module is performing an operation when Idle mode is source when Sleep mode is invoked, the operation may invoked, in this case, the results will be similar to those not terminate correctly. Capacitance and time with Sleep mode. measurements may return erroneous values. 20.8 CTMU Peripheral Module Disable (PMD) When this peripheral is not used, the Peripheral Module Disable bit can be set to disconnect all clock sources to the module, reducing power consumption to an absolute minimum. See Section4.6 “Selective Peripheral Module Control”.  2012-2014 Microchip Technology Inc. DS30000684B-page 321

PIC18(L)F2X/45K50 20.9 Effects of a Reset on CTMU 20.10 Registers Upon Reset, all registers of the CTMU are cleared. This There are three control registers for the CTMU: leaves the CTMU module disabled, its current source is • CTMUCONH turned off and all configuration options return to their • CTMUCONL default settings. The module needs to be re-initialized following any Reset. • CTMUICON The CTMUCONH and CTMUCONL registers If the CTMU is in the process of taking a measurement at (Register20-1 and Register20-2) contain control bits the time of Reset, the measurement will be lost. A partial for configuring the CTMU module edge source selec- charge may exist on the circuit that was being measured, tion, edge source polarity selection, edge sequencing, and should be properly discharged before the CTMU makes subsequent attempts to make a measurement. A/D trigger, analog circuit capacitor discharge and enables. The CTMUICON register (Register20-3) has The circuit is discharged by setting and then clearing the IDISSEN bit (CTMUCONH<1>) while the A/D Converter bits for selecting the current source range and current source trim. is connected to the appropriate channel. 20.11 Register Definitions: CTMU Control REGISTER 20-1: CTMUCONH: CTMU CONTROL REGISTER 0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 4 TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation bit 3 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 2 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 1 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 0 CTTRIG: CTMU Special Event Trigger Control Bit 1 = CTMU Special Event Trigger is enabled 0 = CTMU Special Event Trigger is disabled DS30000684B-page 322  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 20-2: CTMUCONL: CTMU CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL<1:0> EDG1POL EDG1SEL<1:0> EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = CCP2 Special Event Trigger bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = CCP2 Special Event Trigger bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred  2012-2014 Microchip Technology Inc. DS30000684B-page 323

PIC18(L)F2X/45K50 REGISTER 20-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM<5:0> IRNG<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current bit 1-0 IRNG<1:0>: Current Source Range Select bits (see Table29-14) 11 = 100  Base current 10 = 10  Base current 01 = Base current level 00 = Current source disabled TABLE 20-1: REGISTERS ASSOCIATED WITH CTMU MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 322 CTMUCONL EDG2POL EDG2SEL<1:0> EDG1POL EDG1SEL<1:0> EDG2STAT EDG1STAT 323 CTMUICON ITRIM<5:0> IRNG<1:0> 324 IPR3 — — — — CTMUIP USBIP TMR3GIP TMR1GIP 125 PIE3 — — — — CTMUIE USBIE TMR3GIE TMR1GIE 122 PIR3 — — — — CTMUIF USBIF TMR3GIF TMR1GIF 119 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 Legend: — = Unimplemented, read as ‘0’. Shaded bits are not used during CTMU operation. DS30000684B-page 324  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 21.0 SR LATCH 21.2 Latch Output The module consists of a single SR latch with multiple The SRQEN and SRNQEN bits of the SRCON0 register Set and Reset inputs as well as separate latch outputs. control the Q and Q latch outputs. Both of the SR latch The SR latch module includes the following features: outputs may be directly output to I/O pins at the same time. Control is determined by the state of bits SRQEN • Programmable input selection and SRNQEN in the SRCON0 register. • SR latch output is available internally/externally The applicable TRIS bit of the corresponding port must • Selectable Q and Q output be cleared to enable the port pin output driver. • Firmware Set and Reset The SR latch can be used in a variety of analog 21.3 DIVSRCLK Clock Generation applications, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing The DIVSRCLK clock signal is generated from the applications. peripheral clock which is pre-scaled by a value determined by the SRCLK<2:0> bits. See Figure21-1 21.1 Latch Operation and Table21-1 for additional detail. The latch is a Set-Reset Latch that does not depend on 21.4 Effects of a Reset a clock source. Each of the Set and Reset inputs are active-high. The latch can be set or reset by: Upon any device Reset, the SR latch is not initialized, and the SRQ and SRNQ outputs are unknown. The • Software control (SRPS and SRPR bits) user’s firmware is responsible to initialize the latch • Comparator C1 output (sync_C1OUT) output before enabling it to the output pins. • Comparator C2 output (sync_C2OUT) • SRI Pin • Programmable clock (DIVSRCLK) The SRPS and the SRPR bits of the SRCON0 register may be used to set or reset the SR latch, respectively. The latch is Reset-dominant. Therefore, if both Set and Reset inputs are high, the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset operation. The output from Comparator C1 or C2 can be used as the Set or Reset inputs of the SR latch. The output of either Comparator can be synchronized to the Timer1 clock source. See Section19.0 “Comparator Module” and Section13.0 “Timer1/3 Module with Gate Control” for more information. An external source on the SRI pin can be used as the Set or Reset inputs of the SR latch. An internal clock source, DIVSRCLK, is available and it can periodically set or reset the SR latch. The SRCLK<2:0> bits in the SRCON0 register are used to select the clock source period. The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to set or reset the SR latch, respectively.  2012-2014 Microchip Technology Inc. DS30000684B-page 325

PIC18(L)F2X/45K50 FIGURE 21-1: DIVSRCLK BLOCK DIAGRAM 3 SRCLK<2:0> Programmable SRCLK divider Peripheral 1:4 to 1:512 DIVSRCLK Clock 4-512 cycles ... t0 t0+4 t0+8 t0+12 Tosc SRCLK<2:0> = "001" 1:8 FIGURE 21-2: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRLEN SRPS Pulse SRQEN Gen(2) SRI SRSPE S Q DIVSRCLK SRQ SRSCKE sync_C2OUT(3) SRSC2E sync_C1OUT(3) SR SRSC1E Latch(1) SRPR Pulse Gen(2) SRI SRRPE R Q DIVSRCLK SRNQ SRRCKE SRLEN sync_C2OUT(3) SRNQEN SRRC2E sync_C1OUT(3) SRRC1E Note 1: If R=1 and S=1 simultaneously, Q=0, Q=1 2: Pulse generator causes a pulse width of 2 TOSC clock cycles. 3: Name denotes the connection point at the comparator output. DS30000684B-page 326  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 21-1: DIVSRCLK FREQUENCY TABLE SRCLK<2:0> Divider FOSC = 20 MHz FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 25.6 s 32 s 64 s 128 s 512 s 110 256 12.8 s 16 s 32 s 64 s 256 s 101 128 6.4 s 8 s 16 s 32 s 128 s 100 64 3.2 s 4 s 8 s 16 s 64 s 011 32 1.6 s 2 s 4 s 8 s 32 s 010 16 0.8 s 1 s 2 s 4 s 16 s 001 8 0.4 s 0.5 s 1 s 2 s 8 s 000 4 0.2 s 0.25 s 0.5 s 1 s 4 s  2012-2014 Microchip Technology Inc. DS30000684B-page 327

PIC18(L)F2X/45K50 21.5 Register Definitions: SR Latch Control REGISTER 21-1: SRCON0: SR LATCH CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SRLEN: SR Latch Enable bit(1) 1 = SR latch is enabled 0 = SR latch is disabled bit 6-4 SRCLK<2:0>: SR Latch Clock Divider Bits 000 = Generates a 2 TOSC wide pulse on DIVSRCLK every 4 peripheral clock cycles 001 = Generates a 2 TOSC wide pulse on DIVSRCLK every 8 peripheral clock cycles 010 = Generates a 2 TOSC wide pulse on DIVSRCLK every 16 peripheral clock cycles 011 = Generates a 2 TOSC wide pulse on DIVSRCLK every 32 peripheral clock cycles 100 = Generates a 2 TOSC wide pulse on DIVSRCLK every 64 peripheral clock cycles 101 = Generates a 2 TOSC wide pulse on DIVSRCLK every 128 peripheral clock cycles 110 = Generates a 2 TOSC wide pulse on DIVSRCLK every 256 peripheral clock cycles 111 = Generates a 2 TOSC wide pulse on DIVSRCLK every 512 peripheral clock cycles bit 3 SRQEN: SR Latch Q Output Enable bit 1 = Q is present on the SRQ pin 0 = Q is internal only bit 2 SRNQEN: SR Latch Q Output Enable bit 1 = Q is present on the SRNQ pin 0 = Q is internal only bit 1 SRPS: Pulse Set Input of the SR Latch bit(2) 1 = Pulse set input for 2 TOSC clock cycles 0 = No effect on set input bit 0 SRPR: Pulse Reset Input of the SR Latch bit(2) 1 = Pulse Reset input for 2 TOSC clock cycles 0 = No effect on Reset input Note 1: Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the Set and Reset inputs of the latch. 2: Set only, always reads back ‘0’. DS30000684B-page 328  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 21-2: SRCON1: SR LATCH CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SRI pin status sets SR latch 0 = SRI pin status has no effect on SR latch bit 6 SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR latch is pulsed with DIVSRCLK 0 = Set input of SR latch is not pulsed with DIVSRCLK bit 5 SRSC2E: SR Latch C2 Set Enable bit 1 = C2 Comparator output sets SR latch 0 = C2 Comparator output has no effect on SR latch bit 4 SRSC1E: SR Latch C1 Set Enable bit 1 = C1 Comparator output sets SR latch 0 = C1 Comparator output has no effect on SR latch bit 3 SRRPE: SR Latch Peripheral Reset Enable bit 1 = SRI pin resets SR latch 0 = SRI pin has no effect on SR latch bit 2 SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR latch is pulsed with DIVSRCLK 0 = Reset input of SR latch is not pulsed with DIVSRCLK bit 1 SRRC2E: SR Latch C2 Reset Enable bit 1 = C2 Comparator output resets SR latch 0 = C2 Comparator output has no effect on SR latch bit 0 SRRC1E: SR Latch C1 Reset Enable bit 1 = C1 Comparator output resets SR latch 0 = C1 Comparator output has no effect on SR latch TABLE 21-2: REGISTERS ASSOCIATED WITH THE SR LATCH Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 328 SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 329 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 150 Legend: Shaded bits are not used with this module.  2012-2014 Microchip Technology Inc. DS30000684B-page 329

PIC18(L)F2X/45K50 22.0 FIXED VOLTAGE REFERENCE 22.1 Independent Gain Amplifiers (FVR) The output of the FVR supplied to the ADC, Comparators and DAC is routed through an The Fixed Voltage Reference, or FVR, is a stable independent programmable gain amplifier. The voltage reference, independent of VDD, with 1.024V, amplifier can be configured to amplify the 1.024V 2.048V or 4.096V selectable output levels. The output reference voltage by 1x, 2x or 4x, to produce the three of the FVR can be configured to supply a reference possible voltage levels. voltage to the following: The FVRS<1:0> bits of the VREFCON0 register are • ADC input channel used to enable and configure the gain amplifier settings • ADC positive reference for the reference supplied to the DAC and Comparator • Comparator positive input modules. When the ADC module is configured to use • Digital-to-Analog Converter (DAC) the FVR output, (FVR BUF2) the reference is buffered The FVR can be enabled by setting the FVREN bit of through an additional unity gain amplifier. This buffer is the VREFCON0 register. disabled if the ADC is not configured to use the FVR. For specific use of the FVR, refer to the specific module sections: Section18.0 “Analog-to-Digital Converter (ADC) Module”, Section23.0 “Digital-to- Analog Converter (DAC) Module” and Section19.0 “Comparator Module”. 22.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRST bit of the VREFCON0 register will be set. See Table29-13 for the minimum delay requirement. FIGURE 22-1: VOLTAGE REFERENCE BLOCK DIAGRAM X1 FVR BUF2 (To ADC Module) FVRS<1:0> 2 X1 X2 FVR BUF1 X4 (To Comparators, DAC) + FVREN 1.024V Fixed FVRST _ Reference DS30000684B-page 330  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 22.3 Register Definitions: FVR Control REGISTER 22-1: VREFCON0: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-1 U-0 U-0 U-0 U-0 FVREN FVRST FVRS<1:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled bit 6 FVRST: Fixed Voltage Reference Ready Flag bit 0 = Fixed Voltage Reference output is not ready or not enabled 1 = Fixed Voltage Reference output is ready for use bit 5-4 FVRS<1:0>: Fixed Voltage Reference Selection bits 00 =Fixed Voltage Reference Peripheral output is off 01 =Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 =Fixed Voltage Reference Peripheral output is 2x (2.048V)(1) 11 = Fixed Voltage Reference Peripheral output is 4x (4.096V)(1) bit 3-2 Reserved: Read as ‘0’. Maintain these bits clear. bit 1-0 Unimplemented: Read as ‘0’. Note1: Fixed Voltage Reference output cannot exceed VDD. TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page VREFCON0 FVREN FVRST FVRS<1:0> — — — — 331 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by the FVR module.  2012-2014 Microchip Technology Inc. DS30000684B-page 331

PIC18(L)F2X/45K50 23.0 DIGITAL-TO-ANALOG The negative voltage source is disabled by setting the CONVERTER (DAC) MODULE DACLPS bit in the VREFCON1 register. Clearing the DACLPS bit in the VREFCON1 register disables the The Digital-to-Analog Converter supplies a variable positive voltage source. voltage reference, ratiometric with the input source, with 32 selectable output levels. 23.4 Output Clamped to Positive The input of the DAC can be connected to: Voltage Source • External VREF pins The DAC output voltage can be set to VSRC+ with the • VDD supply voltage least amount of power consumption by performing the • FVR (Fixed Voltage Reference) following: The output of the DAC can be configured to supply a • Clearing the DACEN bit in the VREFCON1 reference voltage to the following: register. • Setting the DACLPS bit in the VREFCON1 • Comparator positive input register. • ADC input channel • Configuring the DACPSS bits to the proper • DACOUT pin positive source. The Digital-to-Analog Converter (DAC) can be enabled • Configuring the DACRx bits to ‘11111’ in the by setting the DACEN bit of the VREFCON1 register. VREFCON2 register. This is also the method used to output the voltage level 23.1 Output Voltage Selection from the FVR to an output pin. See Section23.6 “DAC The DAC has 32 voltage level ranges. The 32 levels Voltage Reference Output” for more information. are set with the DACR<4:0> bits of the VREFCON2 register. 23.5 Output Clamped to Negative Voltage Source The DAC output voltage is determined by the following equations: The DAC output voltage can be set to VSRC- with the least amount of power consumption by performing the EQUATION 23-1: DAC OUTPUT VOLTAGE following: VOUT = VSRC+–VSRC--D----A----C---2-R---5-<---4----:-0--->--- + VSRC- • Crelgeiasrtienrg. the DACEN bit in the VREFCON1 • Clearing the DACLPS bit in the VREFCON1 VSRC+ = VDD, VREF+ or FVR1 register. • Configuring the DACPSS bits to the proper negative source. VSRC- = VSS or VREF- • Configuring the DACRx bits to ‘00000’ in the VREFCON2 register. 23.2 Ratiometric Output Level This allows the comparator to detect a zero-crossing while not consuming additional current through the DAC The DAC output value is derived using a resistor ladder module. with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage 23.6 DAC Voltage Reference Output of either input source fluctuates, a similar fluctuation will result in the DAC output value. The DAC can be output to the DACOUT pin by setting the DACOE bit of the VREFCON1 register to ‘1’. The value of the individual resistors within the ladder Selecting the DAC reference voltage for output on the can be found in Section29.0 “Electrical DACOUT pin automatically overrides the digital output Specifications”. buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been 23.3 Low-Power Voltage State configured for DAC reference voltage output will always return a ‘0’. In order for the DAC module to consume the least amount of power, one of the two voltage reference input Due to the limited current drive capability, a buffer must sources to the resistor ladder must be disconnected. be used on the DAC voltage reference output for Either the positive voltage source, (VSRC+), or the external connections to DACOUT. Figure23-2 shows negative voltage source, (VSRC-) can be disabled. an example buffering technique. DS30000684B-page 332  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 23-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) Reserved 11 FVR BUF1 10 VSRC+ VREF+ 01 DACR<4:0> 5 VDD 00 R 2 R 11111 DACPSS<1:0> 11110 R DACEN DACLPS R R X 32 U Steps 1 M DAC Output o- (to Comparators and 2-t ADC Modules) R 3 R 00001 DACOUT R 00000 DACOE DACNSS VREF- 1 VSRC- VSS 0 FIGURE 23-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC R Module + Voltage DACOUT – Buffered DAC Output Reference Output Impedance  2012-2014 Microchip Technology Inc. DS30000684B-page 333

PIC18(L)F2X/45K50 23.7 Operation During Sleep 23.8 Effects of a Reset When the device wakes up from Sleep through an A device Reset affects the following: interrupt or a Watchdog Timer time-out, the contents of • DAC is disabled the VREFCON1 register are not affected. To minimize • DAC output voltage is removed from the current consumption in Sleep mode, the voltage DACOUT pin reference should be disabled. • The DACR<4:0> range select bits are cleared 23.9 Register Definitions: DAC Control REGISTER 23-1: VREFCON1: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 DACLPS: DAC Low-Power Voltage Source Select bit 1 = DAC Positive reference source selected 0 = DAC Negative reference source selected bit 5 DACOE: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin bit 4 Unimplemented: Read as ‘0’ bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits 00 = VDD 01 = VREF+ 10 = FVR BUF1 output 11 = Reserved, do not use bit 1 Unimplemented: Read as ‘0’ bit 0 DACNSS: DAC Negative Source Select bits 1 = VREF- 0 = VSS DS30000684B-page 334  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 23-2: VREFCON2: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DACR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR<4:0>: DAC Voltage Output Select bits VOUT = ((VSRC+) - (VSRC-))*(DACR<4:0>/(25)) + VSRC- TABLE 23-1: REGISTERS ASSOCIATED WITH DAC MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 334 VREFCON2 — — — DACR<4:0> 335 Legend: — = Unimplemented locations, read as ‘0’. Shaded bits are not used by the DAC module.  2012-2014 Microchip Technology Inc. DS30000684B-page 335

PIC18(L)F2X/45K50 24.0 UNIVERSAL SERIAL BUS host and the PIC microcontroller. The SIE can be inter- (USB) faced directly to the USB by utilizing the internal trans- ceiver. This section describes the details of the USB Some special hardware features have been included to peripheral. Because of the very specific nature of the improve performance. Dual access port memory in the module, knowledge of USB is expected. Some device’s data memory space (USB RAM) has been high-level USB information is provided in Section3.14 supplied to share direct memory access between the “Oscillator Settings for USB” only for application microcontroller core and the SIE. Buffer descriptors are design reference. Designers are encouraged to refer to also provided, allowing users to freely program end- the official specification published by the USB point memory usage within the USB RAM space. Implementers Forum (USB-IF) for the latest Figure24-1 presents a general overview of the USB information. peripheral and its features. 24.1 Overview of the USB Peripheral PIC18F2X/45K50 devices contain a full-speed and low-speed compatible USB Serial Interface Engine (SIE) that allows fast communication between any USB FIGURE 24-1: USB PERIPHERAL AND OPTIONS PIC18(L)F2XK50/PIC18(L)F45K50 Family VUSB3V3(3) 3.3V LDO Regulator(2) P FSEN P UPUEN Internal Pull-ups UTRDIS Transceiver USB Bus USB Clock from the FS D+ Oscillator Module UOE D- USB Control and Configuration USB SIE 1kbyte USB RAM Note 1: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used. 2: PIC18F2X/45K50 devices only. 3: See Section2.4 “Voltage Regulator Pins (VUSB3V3)” for details on how to connect this pin. DS30000684B-page 336  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 24.2 USB Status and Control In addition, the USB Control register contains a status bit, SE0 (UCON<5>), which is used to indicate the The operation of the USB module is configured and occurrence of a single-ended zero on the bus. When managed through three control registers. In addition, a the USB module is enabled, this bit should be moni- total of 14 registers are used to manage the actual USB tored to determine whether the differential data lines transactions. The registers are: have come out of a single-ended zero condition. This • USB Control register (UCON) helps to differentiate the initial power-up state from the • USB Configuration register (UCFG) USB Reset signal. • USB Transfer Status register (USTAT) The overall operation of the USB module is controlled • USB Device Address register (UADDR) by the USBEN bit (UCON<3>). Setting this bit activates • Frame Number registers (UFRMH:UFRML) the module and resets all of the PPBI bits in the Buffer • Endpoint Enable registers 0 through 7 (UEPn) Descriptor Table to ‘0’. This bit also activates the inter- nal pull-up resistors, if they are enabled. Thus, this bit 24.2.1 USB CONTROL REGISTER (UCON) can be used as a soft attach/detach to the USB. Although all Status and control bits are ignored when The USB Control register (Register24-1) contains bits this bit is clear, the module needs to be fully preconfig- needed to control the module behavior during transfers. ured prior to setting this bit. This bit cannot be set until The register contains bits that control the following: the USB module is supplied with an active clock • Main USB Peripheral Enable source. If the PLL is being used, it should be enabled • Ping-Pong Buffer Pointer Reset at least two milliseconds (enough time for the PLL to • Control of the Suspend mode lock) before attempting to set the USBEN bit. • Packet Transfer Disable Note: When disabling the USB module, make sure the SUSPND bit (UCON<1>) is clear prior to clearing the USBEN bit. Clearing the USBEN bit, when the module is in the suspended state, may prevent the module from fully powering down.  2012-2014 Microchip Technology Inc. DS30000684B-page 337

PIC18(L)F2X/45K50 REGISTER 24-1: UCON: USB CONTROL REGISTER U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0 — PPBRST SE0 PKTDIS USBEN(1) RESUME SUSPND — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks 0 = Ping-Pong Buffer Pointers not being reset bit 5 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero active on the USB bus 0 = No single-ended zero detected bit 4 PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing disabled, automatically set when a SETUP token is received 0 = SIE token and packet processing enabled bit 3 USBEN: USB Module Enable bit(1) 1 = USB module and supporting circuitry enabled (device attached) 0 = USB module and supporting circuitry disabled (device detached) bit 2 RESUME: Resume Signaling Enable bit 1 = Resume signaling activated 0 = Resume signaling disabled bit 1 SUSPND: Suspend USB bit 1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive 0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate bit 0 Unimplemented: Read as ‘0’ Note 1: This bit cannot be set if the USB module does not have an appropriate clock source. DS30000684B-page 338  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 The PPBRST bit (UCON<6>) controls the Reset status 24.2.2 USB CONFIGURATION REGISTER when Double-Buffering mode (ping-pong buffering) is (UCFG) used. When the PPBRST bit is set, all Ping-Pong Buf- Prior to communicating over USB, the module’s fer Pointers are set to the Even buffers. PPBRST has associated internal and/or external hardware must be to be cleared by firmware. This bit is ignored in buffer- configured. Most of the configuration is performed with ing modes not using ping-pong buffering. the UCFG register (Register24-2).The UCFG register The PKTDIS bit (UCON<4>) is a flag indicating that the contains most of the bits that control the system level SIE has disabled packet transmission and reception. behavior of the USB module. These include: This bit is set by the SIE when a SETUP token is • Bus Speed (full speed versus low speed) received to allow setup processing. This bit cannot be • On-Chip Pull-up Resistor Enable set by the microcontroller, only cleared; clearing it • Ping-Pong Buffer Usage allows the SIE to continue transmission and/or reception. Any pending events within the Buffer The UTEYE bit, UCFG<7>, enables eye pattern gener- Descriptor Table will still be available, indicated within ation, which aids in module testing, debugging and the USTAT register’s FIFO buffer. USB certifications. The RESUME bit (UCON<2>) allows the peripheral to Note: The USB speed, transceiver and pull-up perform a remote wake-up by executing Resume should only be configured during the signaling. To generate a valid remote wake-up, module setup phase. It is not firmware must set RESUME for 10ms and then clear recommended to switch these settings the bit. For more information on “resume signaling”, while the module is enabled. see the “Universal Serial Bus Specification Revision 2.0”. 24.2.2.1 Internal Transceiver The SUSPND bit (UCON<1>) places the module and The USB peripheral has a built-in, USB 2.0, full-speed supporting circuitry in a Low-Power mode. The input and low-speed capable transceiver, internally con- clock to the SIE is also disabled. This bit should be set nected to the SIE. This feature is useful for low-cost, by the software in response to an IDLEIF interrupt. It single chip applications. Enabling the USB module should be reset by the microcontroller firmware after an (USBEN = 1) will also enable the internal transceiver. ACTVIF interrupt is observed. When this bit is active, The FSEN bit (UCFG<2>) controls the transceiver the device remains attached to the bus but the trans- speed; setting the bit enables full-speed operation. ceiver outputs remain Idle. The voltage on the VUSB3V3 pin may vary depending on the value of this bit. Setting The on-chip USB pull-up resistors are controlled by the this bit before a IDLEIF request will result in unpredict- UPUEN bit (UCFG<4>). They can only be selected able bus behavior. when the on-chip transceiver is enabled. The internal USB transceiver obtains power from the Note: While in Suspend mode, a typical VUSB3V3 pin. In order to meet USB signaling level bus-powered USB device is limited to specifications, VUSB3V3 must be supplied with a voltage 2.5mA of current. This is the complete current which may be drawn by the PIC® source between 3.0V and 3.6V. The best electrical signal quality is obtained when a 3.3V supply is used device and its supporting circuitry. Care and locally bypassed with a high quality ceramic should be taken to assure minimum capacitor. The capacitor should be placed as close as current draw when the device enters possible to the VUSB3V3 and VSS pins found on the Suspend mode. same edge of the package. The D+ and D- signal lines can be routed directly to their respective pins on the USB connector or cable (for hard-wired applications). No additional resistors, capacitors, or magnetic components are required as the D+ and D- drivers have controlled slew rate and output impedance intended to match with the characteristic impedance of the USB cable. In order to meet the USB specifications, the traces should be less than 30cm long. Ideally, these traces should be designed to have a characteristic impedance matching that of the USB cable.  2012-2014 Microchip Technology Inc. DS30000684B-page 339

PIC18(L)F2X/45K50 REGISTER 24-2: UCFG: USB CONFIGURATION REGISTER (BANKED F39h) R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UTEYE UOEMON — UPUEN(1,2) UTRDIS(1,3) FSEN(1) PPB<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test is enabled 0 = Eye pattern test is disabled bit 6 UOEMON: USB OE Monitor Enable bit 1 = UOE signal is active, indicating intervals during which the D+/D- lines are driving 0 = UOE signal is inactive bit 5 Unimplemented: Read as ‘0’ bit 4 UPUEN: USB On-Chip Pull-up Enable bit(1,2) 1 = On-chip pull-up is enabled (pull-up on D+ with FSEN=1 or D- with FSEN=0) 0 = On-chip pull-up is disabled bit 3 UTRDIS: On-Chip Transceiver Disable bit(1,3) 1 = On-chip transceiver is disabled 0 = On-chip transceiver is active bit 2 FSEN: Full-Speed Enable bit(1) 1 = Full-speed device: controls transceiver edge rates; requires input clock at 48MHz 0 = Low-speed device: controls transceiver edge rates; requires input clock at 6MHz bit 1-0 PPB<1:0>: Ping-Pong Buffers Configuration bits 11 = Even/Odd ping-pong buffers are enabled for Endpoints 1 to 15 10 = Even/Odd ping-pong buffers are enabled for all endpoints 01 = Even/Odd ping-pong buffer are enabled for OUT Endpoint 0 00 = Even/Odd ping-pong buffers are disabled Note 1: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These values must be preconfigured prior to enabling the module. 2: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored. 3: If UTRDIS is set, the UOE signal will be active, independent of the UOEMON bit setting. DS30000684B-page 340  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 24.2.2.2 Internal Pull-up Resistors 24.2.2.4 Ping-Pong Buffer Configuration The PIC18F2X/45K50 devices have built-in pull-up The usage of ping-pong buffers is configured using the resistors designed to meet the requirements for PPB<1:0> bits. Refer to Section24.4.4 “Ping-Pong low-speed and full-speed USB. The UPUEN bit Buffering” for a complete explanation of the ping-pong (UCFG<4>) enables the internal pull-ups. Figure24-1 buffers. shows the pull-ups and their control. 24.2.2.5 Eye Pattern Test Enable Note: The official USB specifications require that USB devices must never source any An automatic eye pattern test can be generated by the module when the UCFG<7> bit is set. The eye pattern current onto the +5V VBUS line of the USB output will be observable based on module settings, cable. Additionally, USB devices must meaning that the user is first responsible for configuring never source any current on the D+ and the SIE clock settings, pull-up resistor and Transceiver D- data lines whenever the +5V VBUS line mode. In addition, the module has to be enabled. is less than 1.17V. In order to meet this requirement, applications which are not Once UTEYE is set, the module emulates a switch from purely bus powered should monitor the a receive to transmit state and will start transmitting a J-K-J-K bit sequence (K-J-K-J for full speed). The VBUS line and avoid turning on the USB sequence will be repeated indefinitely while the Eye module and the D+ or D- pull-up resistor Pattern Test mode is enabled. until VBUS is greater than 1.17V. VBUS can be connected to a resistive divider and Note that this bit should never be set while the module monitored by an analog capable pin. is connected to an actual USB system. This Test mode is intended for board verification to aid with USB certi- 24.2.2.3 External Pull-up Resistors fication tests. It is intended to show a system developer the noise integrity of the USB signals which can be External pull-up may also be used. The VUSB3V3 pin may affected by board traces, impedance mismatches and be used to pull up D+ or D-. The pull-up resistor must be proximity to other system components. It does not 1.5k (±5%) as required by the USB specifications. properly test the transition from a receive to a transmit Figure24-2 shows an example. state. Although the eye pattern is not meant to replace the more complex USB certification test, it should aid FIGURE 24-2: EXTERNAL CIRCUITRY during first order system debugging. PIC® Host Microcontroller Controller/HUB VUSB 1.5 k D+ D- Note: The above setting shows a typical connection for a full-speed configuration using an on-chip regulator and an external pull-up resistor.  2012-2014 Microchip Technology Inc. DS30000684B-page 341

PIC18(L)F2X/45K50 24.2.3 USB STATUS REGISTER (USTAT) Clearing the transfer complete flag bit, TRNIF, causes the SIE to advance the FIFO. If the next data in the The USB Status register reports the transaction status FIFO holding register is valid, the SIE will reassert the within the SIE. When the SIE issues a USB transfer interrupt within 6 TCY of clearing TRNIF. If no additional complete interrupt, USTAT should be read to determine data is present, TRNIF will remain clear; USTAT data the status of the transfer. USTAT contains the transfer will no longer be reliable. endpoint number, direction and Ping-Pong Buffer Pointer value (if used). Note: If an endpoint request is received while the USTAT FIFO is full, the SIE will Note: The data in the USB Status register is automatically issue a NAK back to the valid two SIE clocks after the TRNIF inter- host. rupt flag is asserted. In low-speed operation with the system FIGURE 24-3: USTAT FIFO clock operating at 48MHz, a delay may be required between receiving the TRNIF USTAT from SIE interrupt and processing the data in the USTAT register. The USTAT register is actually a read window into a four-byte status FIFO, maintained by the SIE. It allows the microcontroller to process one transfer while the 4-Byte FIFO ClearingTRNIF for USTAT AdvancesFIFO SIE processes additional endpoints (Figure24-3). When the SIE completes using a buffer for reading or writing data, it updates the USTAT register. If another USB transfer is performed before a transaction Data Bus complete interrupt is serviced, the SIE will store the status of the next transfer into the status FIFO. REGISTER 24-3: USTAT: USB STATUS REGISTER (ACCESS F64h) U-0 R-x R-x R-x R-x R-x R-x U-0 — ENDP<3:0> DIR PPBI(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 ENDP<3:0>: Encoded Number of Last Endpoint Activity bits (represents the number of the BDT updated by the last USB transfer) 1111 = Endpoint 15 1110 = Endpoint 14 . . . 0001 = Endpoint 1 0000 = Endpoint 0 bit 2 DIR: Last BD Direction Indicator bit 1 = The last transaction was an IN token 0 = The last transaction was an OUT or SETUP token bit 1 PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the Odd BD bank 0 = The last transaction was to the Even BD bank bit 0 Unimplemented: Read as ‘0’ Note 1: This bit is only valid for endpoints with available Even and Odd BD registers. DS30000684B-page 342  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 24.2.4 USB ENDPOINT CONTROL transactions. For Endpoint 0, this bit should always be cleared since the USB specifications identify Each of the 16 possible bidirectional endpoints has its Endpoint0 as the default control endpoint. own independent control register, UEPn (where ‘n’ rep- resents the endpoint number). Each register has an The EPOUTEN bit (UEPn<2>) is used to enable or dis- identical complement of control bits. The prototype is able USB OUT transactions from the host. Setting this shown in Register24-4. bit enables OUT transactions. Similarly, the EPINEN bit (UEPn<1>) enables or disables USB IN transactions The EPHSHK bit (UEPn<4>) controls handshaking for from the host. the endpoint; setting this bit enables USB handshaking. Typically, this bit is always set except when using The EPSTALL bit (UEPn<0>) is used to indicate a isochronous endpoints. STALL condition for the endpoint. If a STALL is issued on a particular endpoint, the EPSTALL bit for that end- The EPCONDIS bit (UEPn<3>) is used to enable or point pair will be set by the SIE. This bit remains set disable USB control operations (SETUP) through the until it is cleared through firmware, or until the SIE is endpoint. Clearing this bit enables SETUP transac- reset. tions. Note that the corresponding EPINEN and EPOUTEN bits must be set to enable IN and OUT REGISTER 24-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake enabled 0 = Endpoint handshake disabled (typically used for isochronous endpoints) bit 3 EPCONDIS: Bidirectional Endpoint Control bit If EPOUTEN = 1 and EPINEN = 1: 1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed 0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed bit 2 EPOUTEN: Endpoint Output Enable bit 1 = Endpoint n output enabled 0 = Endpoint n output disabled bit 1 EPINEN: Endpoint Input Enable bit 1 = Endpoint n input enabled 0 = Endpoint n input disabled bit 0 EPSTALL: Endpoint STALL Enable bit(1) 1 = Endpoint n is stalled 0 = Endpoint n is not stalled Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored.  2012-2014 Microchip Technology Inc. DS30000684B-page 343

PIC18(L)F2X/45K50 24.2.5 USB ADDRESS REGISTER FIGURE 24-4: IMPLEMENTATION OF (UADDR) USB RAM IN DATA MEMORY SPACE The USB Address register contains the unique USB address that the peripheral will decode when active. UADDR is reset to 00h when a USB Reset is received, 000h indicated by URSTIF, or when a Reset is received from the microcontroller. The USB address must be written User Data by the microcontroller during the USB setup phase (enumeration) as part of the Microchip USB firmware support. 3FFh 400h 24.2.6 USB FRAME NUMBER REGISTERS Buffer Descriptors, (UFRMH:UFRML) Banks 4 to 7 USB Data or User Data 4FFh (USB RAM) 500h The Frame Number registers contain the 11-bit frame USB Data or number. The low-order byte is contained in UFRML, User Data 7FFh while the three high-order bits are contained in 800h UFRMH. The register pair is updated with the current frame number whenever a SOF token is received. For the microcontroller, these registers are read-only. The Frame Number registers are primarily used for isochronous transfers. The contents of the UFRMH and UFRML registers are only valid when the 48 MHz SIE clock is active (i.e., contents are inaccurate when Unused SUSPND (UCON<1>) bit = 1). Banks 8 to 14 24.3 USB RAM USB data moves between the microcontroller core and the SIE through a memory space known as the USB RAM. This is a special dual access memory that is mapped into the normal data memory space in Banks 4 through 7 (400h to 7FFh) for a total of 1024 bytes F52h (Figure24-4). F53h Bank 4 (400h through 4FFh) is used specifically for F5Fh endpoint buffer control. Depending on the type of Banks 15 F60h SFRs buffering being used, all but eight bytes of Bank 4 may FFFh also be available for use as USB buffer space. Although USB RAM is available to the microcontroller as data memory, the sections that are being accessed by the SIE should not be accessed by the microcontroller. A semaphore mechanism is used to determine the access to a particular buffer at any given time. This is discussed in Section24.4.1.1 “Buffer Ownership”. DS30000684B-page 344  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 24.4 Buffer Descriptors and the Buffer 24.4.1 BD STATUS AND CONFIGURATION Descriptor Table Buffer descriptors not only define the size of an end- point buffer, but also determine its configuration and The registers in Bank 4 are used specifically for end- control. Most of the configuration is done with the BD point buffer control in a structure known as the Buffer Status register, BDnSTAT. Each BD has its own unique Descriptor Table (BDT). This provides a flexible method and correspondingly numbered BDnSTAT register. for users to construct and control endpoint buffers of various lengths and configuration. FIGURE 24-5: EXAMPLE OF A BUFFER The BDT is composed of Buffer Descriptors (BD) which DESCRIPTOR are used to define and control the actual buffers in the USB RAM space. Each BD, in turn, consists of four Address Registers Contents registers, where n represents one of the 64 possible 400h BD0STAT (xxh) BDs (range of 0 to 63): Buffer 401h BD0CNT 40h Size of Block • BDnSTAT: BD Status register Descriptor 402h BD0ADRL 00h Starting • BDnCNT: BD Byte Count register 403h BD0ADRH 05h Address • BDnADRL: BD Address Low register 500h • BDnADRH: BD Address High register BDs always occur as a four-byte block in the sequence: BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address Buffer USB Data of BDnSTAT is always an offset of (4n – 1) (in hexa- decimal) from 400h, with n being the buffer descriptor number. 53Fh Depending on the buffering configuration used Note: Memory regions are not to scale. (Section24.4.4 “Ping-Pong Buffering”), there are up to 32, 33 or 64 sets of buffer descriptors. At a minimum, Unlike other control registers, the bit configuration for the BDT must be at least eight bytes long. This is the BDnSTAT register is context sensitive. There are because the USB specification mandates that every two distinct configurations, depending on whether the device must have Endpoint 0, with both input and out- microcontroller or the USB module is modifying the BD put for initial setup. Depending on the endpoint and and buffer at a particular time. Only three bit definitions buffering configuration, the BDT can be as long as 256 are shared between the two. bytes. Although they can be thought of as Special Function 24.4.1.1 Buffer Ownership Registers, the Buffer Descriptor Status and Address Because the buffers and their BDs are shared between registers are not hardware mapped, as conventional the CPU and the USB module, a simple semaphore microcontroller SFRs in Bank 15 are. If the endpoint cor- mechanism is used to distinguish which is allowed to responding to a particular BD is not enabled, its registers update the BD and associated buffers in memory. are not used. Instead of appearing as unimplemented This is done by using the UOWN bit (BDnSTAT<7>) as addresses, however, they appear as available RAM. a semaphore to distinguish which is allowed to update Only when an endpoint is enabled by setting the the BD and associated buffers in memory. UOWN is the UEPn<1> bit does the memory at those addresses only bit that is shared between the two configurations become functional as BD registers. As with any address of BDnSTAT. in the data memory space, the BD registers have an indeterminate value on any device Reset. When UOWN is clear, the BD entry is “owned” by the microcontroller core. When the UOWN bit is set, the BD Figure24-5 provides an example of a BD for a 64-byte entry and the buffer memory are “owned” by the USB buffer, starting at 500h. A particular set of BD registers peripheral. The core should not modify the BD or its is only valid if the corresponding endpoint has been corresponding data buffer during this time. Note that enabled using the UEPn register. All BD registers are the microcontroller core can still read BDnSTAT while available in USB RAM. The BD for each endpoint the SIE owns the buffer and vice versa. should be set up prior to enabling the endpoint. The buffer descriptors have a different meaning based on the source of the register update. Prior to placing ownership with the USB peripheral, the user can configure the basic operation of the peripheral through the BDnSTAT bits. During this time, the byte count and buffer location registers can also be set.  2012-2014 Microchip Technology Inc. DS30000684B-page 345

PIC18(L)F2X/45K50 When UOWN is set, the user can no longer depend on 24.4.1.2 BDnSTAT Register (CPU Mode) the values that were written to the BDs. From this point, When UOWN = 0, the microcontroller core owns the the SIE updates the BDs as necessary, overwriting the BD. At this point, the other seven bits of the register original BD values. The BDnSTAT register is updated take on control functions. by the SIE with the token PID and the transfer count, BDnCNT, is updated. The Data Toggle Sync Enable bit, DTSEN (BDnSTAT<3>), controls data toggle parity checking. Note: The firmware should not set the UOWN bit Setting DTSEN enables data toggle synchronization by in the same instruction cycles as any other the SIE. When enabled, it checks the data packet’s par- modifications to the BDnSTAT soft ity against the value of DTS (BDnSTAT<6>). If a packet register. The UOWN bit should only be set arrives with an incorrect synchronization, the data will in a separate instruction cycle, only after essentially be ignored. It will not be written to the USB all other bits in BDnSTAT (and RAM and the USB transfer complete interrupt flag will address/count registers) have been fully not be set. The SIE will send an ACK token back to the updated. host to Acknowledge receipt, however. The effects of The BDnSTAT byte of the BDT should always be the the DTSEN bit on the SIE are summarized in last byte updated when preparing to arm an endpoint. Table24-1. The SIE will clear the UOWN bit when a transaction The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides has completed. support for control transfers, usually one-time stalls on No hardware mechanism exists to block access when Endpoint 0. It also provides support for the SET_FEA- the UOWN bit is set. Thus, unexpected behavior can TURE/CLEAR_FEATURE commands specified in occur if the microcontroller attempts to modify memory Chapter 9 of the USB specification; typically, when the SIE owns it. Similarly, reading such memory continuous STALLs to any endpoint other than the may produce inaccurate data until the USB peripheral default control endpoint. returns ownership to the microcontroller. The BSTALL bit enables buffer stalls. Setting BSTALL causes the SIE to return a STALL token to the host if a received token would use the BD in that location. The EPSTALL bit in the corresponding UEPn control regis- ter is set and a STALL interrupt is generated when a STALL is issued to the host. The UOWN bit remains set and the BDs are not changed unless a SETUP token is received. In this case, the STALL condition is cleared and the ownership of the BD is returned to the microcontroller core. The BD<9:8> bits (BDnSTAT<1:0>) store the two Most Significant digits of the SIE byte count; the lower eight digits are stored in the corresponding BDnCNT register. See Section24.4.2 “BD Byte Count” for more information. TABLE 24-1: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION BDnSTAT Settings Device Response after Receiving Packet OUT Packet from Host DTSEN DTS Handshake UOWN TRNIF BDnSTAT and USTAT Status DATA0 1 0 ACK 0 1 Updated DATA1 1 0 ACK 1 0 Not Updated DATA0 1 1 ACK 1 0 Not Updated DATA1 1 1 ACK 0 1 Updated Either 0 x ACK 0 1 Updated Either, with error x x NAK 1 0 Not Updated Legend: x = don’t care DS30000684B-page 346  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 24-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), CPU MODE (BANKED 4xxh) R/W-x R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x UOWN(1) DTS(2) —(3) —(3) DTSEN BSTALL BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit(1) 0 = The microcontroller core owns the BD and its corresponding buffer bit 6 DTS: Data Toggle Synchronization bit(2) 1 = Data 1 packet 0 = Data 0 packet bit 5-4 Unimplemented: These bits should always be programmed to ‘0’(3). bit 3 DTSEN: Data Toggle Synchronization Enable bit 1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored except for a SETUP transaction, which is accepted even if the data toggle bits do not match 0 = No data toggle synchronization is performed bit 2 BSTALL: Buffer Stall Enable bit 1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the given location (UOWN bit remains set, BD value is unchanged) 0 = Buffer stall disabled bit 1-0 BC<9:8>: Byte Count 9 and 8 bits The byte count bits represent the number of bytes that will be transmitted for an IN token or received during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023. Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module. 2: This bit is ignored unless DTSEN=1. 3: If these bits are set, USB communication may not work. Hence, these bits should always be maintained as ‘0’.  2012-2014 Microchip Technology Inc. DS30000684B-page 347

PIC18(L)F2X/45K50 24.4.1.3 BDnSTAT Register (SIE Mode) The 10-bit byte count is distributed over two registers. The lower eight bits of the count reside in the BDnCNT When the BD and its buffer are owned by the SIE, most register. The upper two bits reside in BDnSTAT<1:0>. of the bits in BDnSTAT take on a different meaning. The This represents a valid byte range of 0 to 1023. configuration is shown in Register24-6. Once the UOWN bit is set, any data or control settings previously 24.4.3 BD ADDRESS VALIDATION written there by the user will be overwritten with data from the SIE. The BD Address register pair contains the starting RAM address location for the corresponding endpoint buffer. The BDnSTAT register is updated by the SIE with the No mechanism is available in hardware to validate the token Packet Identifier (PID) which is stored in BD address. BDnSTAT<5:3>. The transfer count in the correspond- ing BDnCNT register is updated. Values that overflow If the value of the BD address does not point to an the 8-bit register carry over to the two Most Significant address in the USB RAM, or if it points to an address digits of the count, stored in BDnSTAT<1:0>. within another endpoint’s buffer, data is likely to be lost or overwritten. Similarly, overlapping a receive buffer 24.4.2 BD BYTE COUNT (OUT endpoint) with a BD location in use can yield unexpected results. When developing USB The byte count represents the total number of bytes applications, the user may want to consider the that will be transmitted during an IN transfer. After an IN inclusion of software-based address validation in their transfer, the SIE will return the number of bytes sent to code. the host. For an OUT transfer, the byte count represents the maximum number of bytes that can be received and stored in USB RAM. After an OUT transfer, the SIE will return the actual number of bytes received. If the number of bytes received exceeds the corresponding byte count, the data packet will be rejected and a NAK handshake will be generated. When this happens, the byte count will not be updated. REGISTER 24-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE MCU) R/W-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x UOWN — PID3 PID2 PID1 PID0 BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit 1 = The SIE owns the BD and its corresponding buffer bit 6 Reserved: Not written by the SIE bit 5-2 PID<3:0>: Packet Identifier bits The received token PID value of the last transfer (IN, OUT or SETUP transactions only). bit 1-0 BC<9:8>: Byte Count 9 and 8 bits These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer and the actual number of bytes transmitted on an IN transfer. DS30000684B-page 348  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 24.4.4 PING-PONG BUFFERING the completion of a transaction (UOWN cleared by the SIE), the pointer is toggled to the Odd BD. After the An endpoint is defined to have a ping-pong buffer when completion of the next transaction, the pointer is it has two sets of BD entries: one set for an Even toggled back to the Even BD and so on. transfer and one set for an Odd transfer. This allows the CPU to process one BD while the SIE is processing the The Even/Odd status of the last transaction is stored in other BD. Double-buffering BDs in this way allows for the PPBI bit of the USTAT register. The user can reset maximum throughput to/from the USB. all Ping-Pong Pointers to Even using the PPBRST bit. The USB module supports four modes of operation: Figure24-6 shows the four different modes of operation and how USB RAM is filled with the BDs. • No ping-pong support • Ping-pong buffer support for OUT Endpoint 0 only BDs have a fixed relationship to a particular endpoint, depending on the buffering configuration. The mapping • Ping-pong buffer support for all endpoints of BDs to endpoints is detailed in Table24-2. This • Ping-pong buffer support for all other Endpoints relationship also means that gaps may occur in the except Endpoint 0 BDT if endpoints are not enabled contiguously. This The ping-pong buffer settings are configured using the theoretically means that the BDs for disabled endpoints PPB<1:0> bits in the UCFG register. could be used as buffer space. In practice, users should avoid using such spaces in the BDT unless a The USB module keeps track of the Ping-Pong Pointer method of validating BD addresses is implemented. individually for each endpoint. All pointers are initially reset to the Even BD when the module is enabled. After FIGURE 24-6: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES PPB<1:0>=00 PPB<1:0>=01 PPB<1:0>=10 PPB<1:0>=11 No Ping-Pong Ping-Pong Buffer Ping-Pong Buffers Ping-Pong Buffers Buffers on EP0 OUT on all EPs on all Other EPs Except EP0 400h 400h 400h 400h EP0 OUT EP0 OUT Even EP0 OUT Even EP0 OUT Descriptor Descriptor Descriptor Descriptor EP0 IN EP0 OUT Odd EP0 OUT Odd EP0 IN Descriptor Descriptor Descriptor Descriptor EP1 OUT EP0 IN Even EP1 OUT Even Descriptor EP0 IN Descriptor Descriptor Descriptor EP1 IN EP0 IN Odd EP1 OUT Odd Descriptor EP1 OUT Descriptor Descriptor Descriptor EP1 OUT Even EP1 IN Even EP1 IN Descriptor Descriptor Descriptor EP1 OUT Odd EP1 IN Odd EP15 IN Descriptor Descriptor Descriptor 47Fh EP1 IN Even EP15 IN Descriptor 483h Descriptor EP1 IN Odd Descriptor Available as Available Data RAM as EP15 IN Odd Data RAM Descriptor 4F7h Available as Data RAM EP15 IN Odd Descriptor 4FFh 4FFh 4FFh 4FFh Maximum Memory Maximum Memory Maximum Memory Maximum Memory Used: 128 Bytes Used: 132 Bytes Used: 256 Bytes Used: 248 Bytes Maximum BDs: Maximum BDs: Maximum BDs: Maximum BDs: 32 (BD0 to BD31) 33 (BD0 to BD32) 64 (BD0 to BD63) 62 (BD0 to BD61) Note: Memory area is not shown to scale.  2012-2014 Microchip Technology Inc. DS30000684B-page 349

PIC18(L)F2X/45K50 TABLE 24-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Mode 3 Mode 0 Mode 1 Mode 2 Endpoint (Ping-Pong on all other EPs, (No Ping-Pong) (Ping-Pong on EP0 OUT) (Ping-Pong on all EPs) except EP0) Out In Out In Out In Out In 0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1 1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O) 2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O) 3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O) 4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O) 5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O) 6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O) 7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O) 8 16 17 17 18 32 (E), 33 (O) 34 (E), 35 (O) 30 (E), 31 (O) 32 (E), 33 (O) 9 18 19 19 20 36 (E), 37 (O) 38 (E), 39 (O) 34 (E), 35 (O) 36 (E), 37 (O) 10 20 21 21 22 40 (E), 41 (O) 42 (E), 43 (O) 38 (E), 39 (O) 40 (E), 41 (O) 11 22 23 23 24 44 (E), 45 (O) 46 (E), 47 (O) 42 (E), 43 (O) 44 (E), 45 (O) 12 24 25 25 26 48 (E), 49 (O) 50 (E), 51 (O) 46 (E), 47 (O) 48 (E), 49 (O) 13 26 27 27 28 52 (E), 53 (O) 54 (E), 55 (O) 50 (E), 51 (O) 52 (E), 53 (O) 14 28 29 29 30 56 (E), 57 (O) 58 (E), 59 (O) 54 (E), 55 (O) 56 (E), 57 (O) 15 30 31 31 32 60 (E), 61 (O) 62 (E), 63 (O) 58 (E), 59 (O) 60 (E), 61 (O) Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer TABLE 24-3: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BDnSTAT(1) UOWN DTS(4) PID3(2) PID2(2) PID1(2) PID0(2) BC9 BC8 DTSEN(3) BSTALL(3) BDnCNT(1) Byte Count BDnADRL(1) Buffer Address Low BDnADRH(1) Buffer Address High Note 1: For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx). 2: Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID<3:0> values once the register is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values written for DTSEN and BSTALL are no longer valid. 3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the BDnSTAT register are used to configure the DTSEN and BSTALL settings. 4: This bit is ignored unless DTSEN = 1. DS30000684B-page 350  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 24.5 USB Interrupts Figure24-7 shows the interrupt logic for the USB module. There are two layers of interrupt registers in The USB module can generate multiple interrupt con- the USB module. The top level consists of overall USB ditions. To accommodate all of these interrupt sources, Status interrupts; these are enabled and flagged in the the module is provided with its own interrupt logic UIE and UIR registers, respectively. The second level structure, similar to that of the microcontroller. USB consists of USB error conditions, which are enabled interrupts are enabled with one set of control registers and flagged in the UEIR and UEIE registers. An and trapped with a separate set of flag registers. All interrupt condition in any of these triggers a USB Error sources are funneled into a single USB interrupt Interrupt Flag (UERRIF) in the top level. request, USBIF (PIR3<2>), in the microcontroller’s Interrupts may be used to trap routine events in a USB interrupt logic. transaction. Figure24-8 shows some common events within a USB frame and their corresponding interrupts. FIGURE 24-7: USB INTERRUPT LOGIC FUNNEL Second Level USB Interrupts Top Level USB Interrupts (USB Error Conditions) (USB Status Interrupts) UEIR (Flag) and UEIE (Enable) Registers UIR (Flag) and UIE (Enable) Registers SOFIF SOFIE BTSEF BTSEE TRNIF USBIF TRNIE BTOEF BTOEE IDLEIF DFN8EF IDLEIE DFN8EE UERRIF CRC16EF UERRIE CRC16EE STALLIF CRC5EF STALLIE CRC5EE PIDEF PIDEE ACTVIF ACTVIE URSTIF URSTIE FIGURE 24-8: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS From Host From Host To Host SETUPToken Data ACK Set TRNIF From Host To Host From Host USB Reset IN Token Data ACK Set TRNIF URSTIF From Host From Host To Host Start-of-Frame (SOF) OUT Token Empty Data ACK Set TRNIF SOFIF Transaction Transaction Complete RESET SOF SETUP DATA STATUS SOF Differential Data Control Transfer(1) 1ms Frame Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames.  2012-2014 Microchip Technology Inc. DS30000684B-page 351

PIC18(L)F2X/45K50 24.5.1 USB INTERRUPT STATUS When the USB module is in the Low-Power Suspend REGISTER (UIR) mode (UCON<1> = 1), the SIE does not get clocked. The USB Interrupt Status register (Register24-7) When in this state, the SIE cannot process packets contains the flag bits for each of the USB Status and, therefore, cannot detect new interrupt conditions interrupt sources. Each of these sources has a other than the Activity Detect Interrupt, ACTVIF. The corresponding interrupt enable bit in the UIE register. ACTVIF bit is typically used by USB firmware to detect All of the USB status flags are ORed together to when the microcontroller should bring the USB module generate the USBIF interrupt flag for the out of the Low-Power Suspend mode (UCON<1> = 0). microcontroller’s interrupt funnel. Once an interrupt bit has been set by the SIE, it must be cleared by software by writing a ‘0’. The flag bits can also be set in software which can aid in firmware debugging. REGISTER 24-7: UIR: USB INTERRUPT STATUS REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 — SOFIF STALLIF IDLEIF(1) TRNIF(2) ACTVIF(3) UERRIF(4) URSTIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOFIF: Start-of-Frame Token Interrupt bit 1 = A Start-of-Frame token received by the SIE 0 = No Start-of-Frame token received by the SIE bit 5 STALLIF: A STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the SIE 0 = A STALL handshake has not been sent bit 4 IDLEIF: Idle Detect Interrupt bit(1) 1 = Idle condition detected (constant Idle state of 3ms or more) 0 = No Idle condition detected bit 3 TRNIF: Transaction Complete Interrupt bit(2) 1 = Processing of pending transaction is complete; read USTAT register for endpoint information 0 = Processing of pending transaction is not complete or no transaction is pending bit 2 ACTVIF: Bus Activity Detect Interrupt bit(3) 1 = Activity on the D+/D- lines was detected 0 = No activity detected on the D+/D- lines bit 1 UERRIF: USB Error Condition Interrupt bit(4) 1 = An unmasked error condition has occurred 0 = No unmasked error condition has occurred bit 0 URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset occurred; 00h is loaded into UADDR register 0 = No USB Reset has occurred Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode. 2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens). 3: This bit is typically unmasked only following the detection of a UIDLE interrupt event. 4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and cannot be set or cleared by the user. DS30000684B-page 352  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 24.5.1.1 Bus Activity Detect Interrupt Bit clearing the SUSPND bit, the USB module may not be (ACTVIF) immediately operational while waiting for the 48 MHz PLL to lock. The application code should clear the The ACTVIF bit cannot be cleared immediately after ACTVIF flag as shown in Example24-1. the USB module wakes up from Suspend or while the USB module is suspended. A few clock cycles are Only one ACTVIF interrupt is generated when required to synchronize the internal hardware state resuming from the USB bus Idle condition. If user machine before the ACTVIF bit can be cleared by firmware clears the ACTVIF bit, the bit will not firmware. Clearing the ACTVIF bit before the internal immediately become set again, even when there is hardware is synchronized may not have an effect on continuous bus traffic. Bus traffic must cease long the value of ACTVIF. Additionally, if the USB module enough to generate another IDLEIF condition before uses the clock from the 48 MHz PLL source, then after another ACTVIF interrupt can be generated. EXAMPLE 24-1: CLEARING ACTVIF BIT (UIR<2>) Assembly: BCF UCON, SUSPND LOOP: BTFSS UIR, ACTVIF BRA DONE BCF UIR, ACTVIF BRA LOOP DONE: C: UCONbits.SUSPND = 0; while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }  2012-2014 Microchip Technology Inc. DS30000684B-page 353

PIC18(L)F2X/45K50 24.5.2 USB INTERRUPT ENABLE The values in this register only affect the propagation REGISTER (UIE) of an interrupt condition to the microcontroller’s interrupt logic. The flag bits are still set by their The USB Interrupt Enable register (Register24-8) interrupt conditions, allowing them to be polled and contains the enable bits for the USB Status interrupt serviced without actually generating an interrupt. sources. Setting any of these bits will enable the respective interrupt source in the UIR register. REGISTER 24-8: UIE: USB INTERRUPT ENABLE REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOFIE: Start-of-Frame Token Interrupt Enable bit 1 = Start-of-Frame token interrupt enabled 0 = Start-of-Frame token interrupt disabled bit 5 STALLIE: STALL Handshake Interrupt Enable bit 1 = STALL interrupt enabled 0 = STALL interrupt disabled bit 4 IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle detect interrupt enabled 0 = Idle detect interrupt disabled bit 3 TRNIE: Transaction Complete Interrupt Enable bit 1 = Transaction interrupt enabled 0 = Transaction interrupt disabled bit 2 ACTVIE: Bus Activity Detect Interrupt Enable bit 1 = Bus activity detect interrupt enabled 0 = Bus activity detect interrupt disabled bit 1 UERRIE: USB Error Interrupt Enable bit 1 = USB error interrupt enabled 0 = USB error interrupt disabled bit 0 URSTIE: USB Reset Interrupt Enable bit 1 = USB Reset interrupt enabled 0 = USB Reset interrupt disabled DS30000684B-page 354  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 24.5.3 USB ERROR INTERRUPT STATUS Each error bit is set as soon as the error condition is REGISTER (UEIR) detected. Thus, the interrupt will typically not correspond with the end of a token being processed. The USB Error Interrupt Status register (Register24-9) contains the flag bits for each of the error sources Once an interrupt bit has been set by the SIE, it must within the USB peripheral. Each of these sources is be cleared by software by writing a ‘0’. controlled by a corresponding interrupt enable bit in the UEIE register. All of the USB error flags are ORed together to generate the USB Error Interrupt Flag (UERRIF) at the top level of the interrupt logic. REGISTER 24-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BTSEF: Bit Stuff Error Flag bit 1 = A bit stuff error has been detected 0 = No bit stuff error bit 6-5 Unimplemented: Read as ‘0’ bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed) 0 = No bus turnaround time-out bit 3 DFN8EF: Data Field Size Error Flag bit 1 = The data field was not an integral number of bytes 0 = The data field was an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = The CRC16 failed 0 = The CRC16 passed bit 1 CRC5EF: CRC5 Host Error Flag bit 1 = The token packet was rejected due to a CRC5 error 0 = The token packet was accepted bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed  2012-2014 Microchip Technology Inc. DS30000684B-page 355

PIC18(L)F2X/45K50 24.5.4 USB ERROR INTERRUPT ENABLE As with the UIE register, the enable bits only affect the REGISTER (UEIE) propagation of an interrupt condition to the micro- controller’s interrupt logic. The flag bits are still set by The USB Error Interrupt Enable register their interrupt conditions, allowing them to be polled (Register24-10) contains the enable bits for each of and serviced without actually generating an interrupt. the USB error interrupt sources. Setting any of these bits will enable the respective error interrupt source in the UEIR register to propagate into the UERR bit at the top level of the interrupt logic. REGISTER 24-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Bit stuff error interrupt enabled 0 = Bit stuff error interrupt disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Bus turnaround time-out error interrupt enabled 0 = Bus turnaround time-out error interrupt disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Data field size error interrupt enabled 0 = Data field size error interrupt disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16 failure interrupt enabled 0 = CRC16 failure interrupt disabled bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = CRC5 host error interrupt enabled 0 = CRC5 host error interrupt disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = PID check failure interrupt enabled 0 = PID check failure interrupt disabled DS30000684B-page 356  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 24.6 USB Power Modes 24.6.2 SELF-POWER ONLY Many USB applications will likely have several different In Self-Power Only mode, the USB application provides sets of power requirements and configuration. The its own power, with very little power being pulled from most common power modes encountered are Bus the USB. Figure24-10 shows an example. Power Only, Self-Power Only and Dual Power with In order to meet compliance specifications, the USB Self-Power Dominance. The most common cases are module (and the D+ or D- pull-up resistor) should not presented here. Also provided is a means of estimating be enabled until the host actively drives VBUS high. the current consumption of the USB transceiver. The application should never source any current onto 24.6.1 BUS POWER ONLY the 5V VBUS pin of the USB cable. In Bus Power Only mode, all power for the application FIGURE 24-10: SELF-POWER ONLY is drawn from the USB (Figure24-9). This is effectively the simplest power method for the device. In order to meet the inrush current requirements of the VSELF VDD USB 2.0 specifications, the total effective capacitance appearing across VBUS and ground must be no more than 10µF. If not, some kind of inrush liming is VUSB required. For more details, see section 7.2.4 of the USB 2.0 specification. VSS According to the USB 2.0 specification, all USB devices must also support a Low-Power Suspend mode. In the USB Suspend mode, devices must consume no more than 2.5mA from the 5V VBUS line of the USB cable. The host signals the USB device to enter the Suspend mode by stopping all USB traffic to that device for more than 3ms. This condition will cause the IDLEIF bit in the UIR register to become set. During the USB Suspend mode, the D+ or D- pull-up resistor must remain active, which will consume some of the allowed suspend current: 2.5mA budget. FIGURE 24-9: BUS POWER ONLY VBUS VDD VUSB VSS  2012-2014 Microchip Technology Inc. DS30000684B-page 357

PIC18(L)F2X/45K50 24.6.3 DUAL POWER WITH SELF-POWER 24.6.4 USB TRANSCEIVER CURRENT DOMINANCE CONSUMPTION Some applications may require a dual power option. The USB transceiver consumes a variable amount of This allows the application to use internal power pri- current depending on the characteristic impedance of marily, but switch to power from the USB when no inter- the USB cable, the length of the cable, the VUSB3V3 nal power is available. Figure24-11 shows a simple supply voltage and the actual data patterns moving Dual Power with Self-Power Dominance mode exam- across the USB cable. Longer cables have larger ple, which automatically switches between Self-Power capacitances and consume more total energy when Only and USB Bus Power Only modes. switching output states. Dual power devices must also meet all of the special Data patterns that consist of “IN” traffic consume far requirements for inrush current and Suspend mode more current than “OUT” traffic. IN traffic requires the current and must not enable the USB module until PIC® device to drive the USB cable, whereas OUT VBUS is driven high. See Section24.6.1 “Bus Power traffic requires that the host drive the USB cable. Only” and Section24.6.2 “Self-Power Only” for The data that is sent across the USB cable is NRZI descriptions of those requirements. Additionally, dual encoded. In the NRZI encoding scheme, ‘0’ bits cause power devices must never source current onto the 5V a toggling of the output state of the transceiver (either VBUS pin of the USB cable. from a “J” state to a “K” state, or vise versa). With the exception of the effects of bit-stuffing, NRZI encoded ‘1’ FIGURE 24-11: DUAL POWER EXAMPLE bits do not cause the output state of the transceiver to change. Therefore, IN traffic consisting of data bits of value, ‘0’, cause the most current consumption, as the transceiver must charge/discharge the USB cable in order to change states. VBUS VDD ~5V More details about NRZI encoding and bit-stuffing can be found in the USB 2.0 specification’s section 7.1, 100k VUSB although knowledge of such details is not required to make USB applications using the PIC18F2X/45K50 of VSELF VSS microcontrollers. Among other things, the SIE handles ~5V bit-stuffing/unstuffing, NRZI encoding/decoding and CRC generation/checking in hardware. The total transceiver current consumption will be application-specific. However, to help estimate how much current actually may be required in full-speed Note: Users should keep in mind the limits for applications, Equation24-1 can be used. devices drawing power from the USB. Example24-2 shows how this equation can be used for According to USB Specification 2.0, this a theoretical application. cannot exceed 100mA per low-power device or 500mA per high-power device. DS30000684B-page 358  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 EQUATION 24-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION (60 mA • VUSB3V3 • PZERO • PIN • LCABLE) IXCVR = + IPULLUP (3.3V • 5m) Legend: VUSB: Voltage applied to the VUSB3V3 pin in volts. (Should be 3.0V to 3.6V.) PZERO: Percentage (in decimal) of the IN traffic bits sent by the PIC® device that are a value of ‘0’. PIN: Percentage (in decimal) of total bus bandwidth that is used for IN traffic. LCABLE: Length (in meters) of the USB cable. The USB 2.0 specification requires that full-speed applications use cables no longer than 5m. IPULLUP: Current which the nominal, 1.5 k pull-up resistor (when enabled) must supply to the USB cable. On the host or hub end of the USB cable, 15 k nominal resistors (14.25k to 24.8k) are present which pull both the D+ and D- lines to ground. During bus Idle conditions (such as between packets or during USB Suspend mode), this results in up to 218A of quiescent current drawn at 3.3V. IPULLUP is also dependant on bus traffic conditions and can be as high as 2.2mA when the USB bandwidth is fully utilized (either IN or OUT traffic) for data that drives the lines to the “K” state most of the time. EXAMPLE 24-2: CALCULATING USB TRANSCEIVER CURRENT† For this example, the following assumptions are made about the application: • 3.3V will be applied to VUSB3V3 and VDD, with the core voltage regulator enabled. • This is a full-speed application that uses one interrupt IN endpoint that can send one packet of 64bytes every 1ms, with no restrictions on the values of the bytes being sent. The application may or may not have addi- tional traffic on OUT endpoints. • A regular USB “B” or “mini-B” connector will be used on the application circuit board. In this case, PZERO = 100% = 1, because there should be no restriction on the value of the data moving through the IN endpoint. All 64kBps of data could potentially be bytes of value, 00h. Since ‘0’ bits cause toggling of the output state of the transceiver, they cause the USB transceiver to consume extra current charging/discharging the cable. In this case, 100% of the data bits sent can be of value ‘0’. This should be considered the “max” value, as normal data will consist of a fair mix of ones and zeros. This application uses 64kBps for IN traffic out of the total bus bandwidth of 1.5MBps (12Mbps), therefore: 64 kBps Pin = = 4.3% = 0.043 1.5 MBps Since a regular “B” or “mini-B” connector is used in this application, the end user may plug in any type of cable up to the maximum allowed 5m length. Therefore, we use the worst-case length: LCABLE = 5 meters Assume IPULLUP = 2.2mA. The actual value of IPULLUP will likely be closer to 218A, but allow for the worst-case. USB bandwidth is shared between all the devices which are plugged into the root port (via hubs). If the application is plugged into a USB 1.1 hub that has other devices plugged into it, your device may see host to device traffic on the bus, even if it is not addressed to your device. Since any traffic, regardless of source, can increase the IPULLUP current above the base 218A, it is safest to allow for the worst-case of 2.2mA. Therefore: (60 mA • 3.3V • 1 • 0.043 • 5m) IXCVR = + 2.2 mA = 4.8 mA (3.3V • 5m) The calculated value should be considered an approximation and additional guardband or application-specific prod- uct testing is recommended. The transceiver current is “in addition to” the rest of the current consumed by the PIC18F2X/45K50 device that is needed to run the core, drive the other I/O lines, power the various modules, etc.  2012-2014 Microchip Technology Inc. DS30000684B-page 359

PIC18(L)F2X/45K50 24.7 Oscillator The USB module has specific clock requirements. For full-speed operation, the clock source must be 48MHz. Even so, the microcontroller core and other peripherals are not required to run at that clock speed. Available clocking options are described in detail in Section3.14 “Oscillator Settings for USB”. 24.8 Interrupt-On-Change for D+/D- pins The PIC18(L)F2X/45K50 has interrupt-on-change functionality on both D+ and D- data pins. This feature allows the device to detect voltage level changes when first connected to a USB host/hub. The USB host/hub has 15K pull-down resistors on the D+ and D- pins. When the PIC18(L)F2X/45K50 attaches to the bus the D+ and D- pins can detect voltage changes. External resistors are needed for each pin to maintain a high state on the pins when detached. The USB module must be disabled (USBEN = 0) for the interrupt-on-change to function. Enabling the USB module (USBEN = 1) will automatically disable the interrupt-on-change for D+ and D- pins. Refer to Section11.3.2 “Interrupt-on-Change” and Section11.4.2 “Interrupt-on-Change” for more details. 24.9 USB Firmware and Drivers Microchip provides a number of application-specific resources, such as USB firmware and driver support. Refer to www.microchip.com for the latest firmware and driver support. DS30000684B-page 360  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 24-4: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR3 — — — — CTMUIP USBIP TMR3GIP TMR1GIP 125 PIR3 — — — — CTMUIF USBIF TMR3GIF TMR1GIF 119 PIE3 — — — — CTMUIE USBIE TMR3GIE TMR1GIE 122 UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 338 UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB<1:0>1 340 USTAT — ENDP<3:0> DIR PPBI — 342 UADDR — ADDR<6:0> 344 UFRML FRM<7:0> 337 UFRMH — — — — — FRM<10:8> 337 UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 352 UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 354 UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 355 UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 356 UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 343 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module. Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table24-3.  2012-2014 Microchip Technology Inc. DS30000684B-page 361

PIC18(L)F2X/45K50 24.10 Overview of USB 24.10.3 TRANSFERS This section presents some of the basic USB concepts There are four transfer types defined in the USB and useful information necessary to design a USB specification. device. Although much information is provided in this • Isochronous: This type provides a transfer section, there is a plethora of information provided method for large amounts of data (up to within the USB specifications and class specifications. 1023bytes) with timely delivery ensured; Thus, the reader is encouraged to refer to the USB however, the data integrity is not ensured. This is specifications for more information (www.usb.org). If good for streaming applications where small data you are very familiar with the details of USB, then this loss is not critical, such as audio. section serves as a basic, high-level refresher of USB. • Bulk: This type of transfer method allows for large amounts of data to be transferred with ensured 24.10.1 LAYERED FRAMEWORK data integrity; however, the delivery timeliness is USB device functionality is structured into a layered not ensured. framework graphically shown in Figure24-12. Each • Interrupt: This type of transfer provides for level is associated with a functional level within the ensured timely delivery for small blocks of data, device. The highest layer, other than the device, is the plus data integrity is ensured. configuration. A device may have multiple configura- • Control: This type provides for device setup tions. For example, a particular device may have control. multiple power requirements based on Self-Power Only or Bus Power Only modes. While full-speed devices support all transfer types, low-speed devices are limited to interrupt and control For each configuration, there may be multiple transfers only. interfaces. Each interface could support a particular mode of that configuration. 24.10.4 POWER Below the interface is the endpoint(s). Data is directly Power is available from the Universal Serial Bus. The moved at this level. There can be as many as USB specification defines the bus power requirements. 16bidirectional endpoints. Endpoint 0 is always a Devices may either be self-powered or bus powered. control endpoint and by default, when the device is on Self-powered devices draw power from an external the bus, Endpoint 0 must be available to configure the source, while bus powered devices use power supplied device. from the bus. 24.10.2 FRAMES Information communicated on the bus is grouped into 1ms time slots, referred to as frames. Each frame can contain many transactions to various devices and endpoints. Figure24-8 shows an example of a transaction within a frame. FIGURE 24-12: USB LAYERS Device To other Configurations (if any) Configuration To other Interfaces (if any) Interface Interface Endpoint Endpoint Endpoint Endpoint Endpoint DS30000684B-page 362  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 The USB specification limits the power taken from the 24.10.6.2 Configuration Descriptor bus. Each device is ensured 100mA at approximately The configuration descriptor provides information on 5V (one unit load). Additional power may be requested, the power requirements of the device and how many up to a maximum of 500mA. Note that power above different interfaces are supported when in this configu- one unit load is a request and the host or hub is not ration. There may be more than one configuration for a obligated to provide the extra current. Thus, a device device (i.e., low-power and high-power configurations). capable of consuming more than one unit load must be able to maintain a low-power configuration of a one unit 24.10.6.3 Interface Descriptor load or less, if necessary. The interface descriptor details the number of end- The USB specification also defines a Suspend mode. points used in this interface, as well as the class of the In this situation, current must be limited to 500A, interface. There may be more than one interface for a averaged over 1 second. A device must enter a configuration. Suspend state after 3ms of inactivity (i.e., no SOF tokens for 3ms). A device entering Suspend mode 24.10.6.4 Endpoint Descriptor must drop current consumption within 10ms after The endpoint descriptor identifies the transfer type Suspend. Likewise, when signaling a wake-up, the (Section24.10.3 “Transfers”) and direction, as well device must signal a wake-up within 10ms of drawing as some other specifics for the endpoint. There may be current above the Suspend limit. many endpoints in a device and endpoints may be 24.10.5 ENUMERATION shared in different configurations. When the device is initially attached to the bus, the host 24.10.6.5 String Descriptor enters an enumeration process in an attempt to identify Many of the previous descriptors reference one or the device. Essentially, the host interrogates the device, more string descriptors. String descriptors provide gathering information such as power consumption, data human readable information about the layer rates and sizes, protocol and other descriptive (Section24.10.1 “Layered Framework”) they information; descriptors contain this information. A describe. Often these strings show up in the host to typical enumeration process would be as follows: help the user identify the device. String descriptors are 1. USB Reset: Reset the device. Thus, the device generally optional to save memory and are encoded in is not configured and does not have an address a unicode format. (address 0). 2. Get Device Descriptor: The host requests a 24.10.7 BUS SPEED small portion of the device descriptor. Each USB device must indicate its bus presence and 3. USB Reset: Reset the device again. speed to the host. This is accomplished through a 4. Set Address: The host assigns an address to the 1.5k resistor which is connected to the bus at the device. time of the attachment event. 5. Get Device Descriptor: The host retrieves the Depending on the speed of the device, the resistor device descriptor, gathering info such as either pulls up the D+ or D- line to 3.3V. For a manufacturer, type of device, maximum control low-speed device, the pull-up resistor is connected to packet size. the D- line. For a full-speed device, the pull-up resistor 6. Get configuration descriptors. is connected to the D+ line. 7. Get any other descriptors. 24.10.8 CLASS SPECIFICATIONS AND 8. Set a configuration. DRIVERS The exact enumeration process depends on the host. USB specifications include class specifications which 24.10.6 DESCRIPTORS operating system vendors optionally support. Examples of classes include Audio, Mass Storage, There are eight different standard descriptor types of Communications and Human Interface (HID). In most which five are most important for this device. cases, a driver is required at the host side to ‘talk’ to the USB device. In custom applications, a driver may need 24.10.6.1 Device Descriptor to be developed. Fortunately, drivers are available for The device descriptor provides general information, most common host systems for the most common such as manufacturer, product number, serial number, classes of devices. Thus, these drivers can be reused. the class of the device and the number of configurations. There is only one device descriptor.  2012-2014 Microchip Technology Inc. DS30000684B-page 363

PIC18(L)F2X/45K50 25.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect Control register (HLVD) (Register25-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned The PIC18(L)F2X/45K50 devices have a High/Low- off” by the user under software control, which Voltage Detect module (HLVD). This is a programmable minimizes the current consumption for the device. circuit that sets both a device voltage trip point and the The module’s block diagram is shown in Figure25-1. direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution branches to the interrupt vector address and the software responds to the interrupt. 25.1 Register – HLVD Control REGISTER 25-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 BGVST: Band Gap Reference Voltages Stable Status Flag bit 1 = Internal band gap voltage references are stable 0 = Internal band gap voltage reference is not stable bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL<3:0>: Voltage Detection Level bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting Note 1: See Table29-15 for specifications. DS30000684B-page 364  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 The module is enabled by setting the HLVDEN bit trip point voltage. The “trip point” voltage is the voltage (HLVDCON<4>). Each time the HLVD module is level at which the device detects a high or low-voltage enabled, the circuitry requires some time to stabilize. event, depending on the configuration of the module. The IRVST bit (HLVDCON<5>) is a read-only bit used When the supply voltage is equal to the trip point, the to indicate when the circuit is stable. The module can voltage tapped off of the resistor array is equal to the only generate an interrupt after the circuit is stable and internal reference voltage generated by the voltage IRVST is set. reference module. The comparator then generates an The VDIRMAG bit (HLVDCON<7>) determines the interrupt signal by setting the HLVDIF bit. overall operation of the module. When VDIRMAG is The trip point voltage is software programmable to any of cleared, the module monitors for drops in VDD below a 16 values. The trip point is selected by programming the predetermined set point. When the bit is set, the HLVDL<3:0> bits (HLVDCON<3:0>). module monitors for rises in VDD above the set point. The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an 25.2 Operation external source. This mode is enabled when bits, When the HLVD module is enabled, a comparator uses HLVDL<3:0>, are set to ‘1111’. In this state, the an internally generated reference voltage as the set comparator input is multiplexed from the external input point. The set point is compared with the trip point, pin, HLVDIN. This gives users the flexibility of configur- where each node in the resistor divider represents a ing the High/Low-Voltage Detect interrupt to occur at any voltage in the valid operating range. FIGURE 25-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL<3:0> HLVDCON Register HLVDEN VDIRMAG HLVDIN X Set U M HLVDIF 1 o- 6-t 1 HLVDEN Internal Voltage BOREN Reference 1.024V Typical  2012-2014 Microchip Technology Inc. DS30000684B-page 365

PIC18(L)F2X/45K50 25.3 HLVD Setup 25.4 Current Consumption To set up the HLVD module: When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static 1. Select the desired HLVD trip point by writing the current. The total current consumption, when enabled, value to the HLVDL<3:0> bits. is specified in Section29.0 “Electrical Specifica- 2. Set the VDIRMAG bit to detect high voltage tions”. Depending on the application, the HLVD mod- (VDIRMAG = 1) or low voltage (VDIRMAG = 0). ule does not need to operate constantly. To reduce 3. Enable the HLVD module by setting the current requirements, the HLVD circuitry may only HLVDEN bit. need to be enabled for short periods where the voltage 4. Clear the HLVD interrupt flag (PIR2<2>), which is checked. After such a check, the module could be may have been set from a previous interrupt. disabled. 5. If interrupts are desired, enable the HLVD interrupt by setting the HLVDIE and GIE/GIEH 25.5 HLVD Start-up Time bits (PIE2<2> and INTCON<7>, respectively). The internal reference voltage of the HLVD module, An interrupt will not be generated until the specified in Section29.0 “Electrical Specifications”, IRVST bit is set. may be used by other internal circuitry, such as the Note: Before changing any module settings programmable Brown-out Reset. If the HLVD or other (VDIRMAG, HLVDL<3:0>), first disable the circuits using the voltage reference are disabled to module (HLVDEN = 0), make the changes lower the device’s current consumption, the reference and re-enable the module. This prevents voltage circuit will require time to become stable before the generation of false HLVD events. a low or high-voltage condition can be reliably detected. This start-up time, TIRVST, is an interval that is independent of device clock speed. The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval (see Figure25-2 or Figure25-3). DS30000684B-page 366  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 25-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VDD VHLVD HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal Reference is stable HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists  2012-2014 Microchip Technology Inc. DS30000684B-page 367

PIC18(L)F2X/45K50 FIGURE 25-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists 25.6 Applications FIGURE 25-4: TYPICAL LOW-VOLTAGE DETECT APPLICATION In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach VA would indicate a high-voltage detect from, for example, VB 3.3V to 5V (the voltage on USB) and vice versa for a e g detach. This feature could save a design a few extra a t components and an attach signal (input pin). ol V For general battery applications, Figure25-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an ISR, Time TA TB which would allow the application to perform “house- keeping tasks” and a controlled shutdown before the Legend: VA = HLVD trip point device voltage exits the valid operating range at TB. VB = Minimum valid device This would give the application a time window, operating voltage represented by the difference between TA and TB, to safely exit. DS30000684B-page 368  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 25.7 Operation During Sleep 25.8 Effects of a Reset When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state. during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off. point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 25-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> 364 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149 Legend: — = Unimplemented locations, read as ‘0’. Shaded bits are unused by the HLVD module.  2012-2014 Microchip Technology Inc. DS30000684B-page 369

PIC18(L)F2X/45K50 26.0 SPECIAL FEATURES OF 26.1 Configuration Bits THE CPU The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various PIC18(L)F2X/45K50 devices include several features device configurations. These bits are mapped starting intended to maximize reliability and minimize cost through at program memory location 300000h. elimination of external components. These are: The user will note that address 300000h is beyond the • Oscillator Selection user program memory space. In fact, it belongs to the • Resets: configuration memory space (300000h-3FFFFFh), which - Power-on Reset (POR) can only be accessed using table reads and table writes. - Power-up Timer (PWRT) Programming the Configuration registers is done in a - Oscillator Start-up Timer (OST) manner similar to programming the Flash memory. The - Brown-out Reset (BOR) WR bit in the EECON1 register starts a self-timed write • Interrupts to the Configuration register. In normal operation mode, • Watchdog Timer (WDT) a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and the data • Code Protection for the Configuration register write. Setting the WR bit • ID Locations starts a long write to the Configuration register. The • In-Circuit Serial Programming™ Configuration registers are written a byte at a time. To The oscillator can be configured for the application write or erase a configuration cell, a TBLWT instruction depending on frequency, power, accuracy and cost. All can write a ‘1’ or a ‘0’ into the cell. For additional details of the options are discussed in detail in Section3.0 on Flash programming, refer to Section7.6 “Writing “Oscillator Module (With Fail-Safe Clock Monitor)”. to Flash Program Memory”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18(L)F2X/45K50 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. Two- Speed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits. DS30000684B-page 370  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 26-1: CONFIGURATION BITS AND DEVICE IDs Default/ Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300000h CONFIG1L — — LS48MHZ CPUDIV<1:0> — CFGPLLEN PLLSEL 0000 0000 300001h CONFIG1H IESO FCMEN PCLKEN — FOSC<3:0> 0010 0101 300002h CONFIG2L — LPBOR — BORV<1:0> BOREN<1:0> PWRTEN 0101 1111 300003h CONFIG2H — — WDTPS<3:0> WDTEN<1:0> 0011 1111 300004h CONFIG3L — — — — — — — — 0000 0000 300005h CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 1101 0011 300006h CONFIG4L DEBUG XINST ICPRT(5) — — LVP(1) — STRVEN 1010 0101 300007h CONFIG4H — — — — — — — — 1111 1111 300008h CONFIG5L — — — — CP3(2) CP2(2) CP1 CP0 0000 1111 300009h CONFIG5H CPD CPB — — — — — — 1100 0000 30000Ah CONFIG6L — — — — WRT3(2) WRT2(2) WRT1 WRT0 0000 1111 30000Bh CONFIG6H WRTD WRTB WRTC(3) — — — — — 1110 0000 30000Ch CONFIG7L — — — — EBTR3(2) EBTR2(2) EBTR1 EBTR0 0000 1111 30000Dh CONFIG7H — EBTRB — — — — — — 0100 0000 3FFFFEh DEVID1(4) DEV<2:0> REV<4:0> qqqq qqqq 3FFFFFh DEVID2(4) DEV<10:3> 0101 1100 Legend: – = unimplemented, q = value depends on condition. Shaded bits are unimplemented, read as ‘0’. Note 1: Can only be changed when in high voltage programming mode. 2: Available on PIC18(L)F45K50 and PIC18(L)F25K50 devices only. 3: In user mode, this bit is read-only and cannot be self-programmed. 4: See Register26-13 and Register26-14 for DEVID values. DEVID registers are read-only and cannot be programmed by the user. 5: Available only on 44-pin TQFP package devices. Program this bit clear on all other devices.  2012-2014 Microchip Technology Inc. DS30000684B-page 371

PIC18(L)F2X/45K50 26.2 Register Definitions: Configuration Word REGISTER 26-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW U-0 U-0 R/P-0 R/P-0 R/P-0 U-0 R/P-0 R/P-0 — — LS48MHZ CPUDIV<1:0> — CFGPLLEN PLLSEL bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 LS48MHZ: USB Low-Speed Clock Selection bit Selects the clock source for Low-speed USB operation 1 = System clock is expected at 48 MHz, FS/LS USB clock divide-by is set to 8 0 = System clock is expected at 24 MHz, FS/LS USB clock divide-by is set to 4 bit 4-3 CPUDIV<1:0>: CPU System Clock Selection bits 11 = CPU system clock divided by 6 10 = CPU system clock divided by 3 01 = CPU system clock divided by 2 00 = No CPU system clock divide bit 2 Unimplemented: Read as ‘0’ bit 1 CFGPLLEN: PLL Enable bit(1) 1 = Oscillator multiplied by 3 or 4, depending on the PLLSEL bit 0 = Oscillator used directly bit 0 PLLSEL: PLL Multiplier Selection bit 1 = Output frequency is 3x the input frequency 0 = Output frequency is 4x the input frequency Note 1: See Table3-1 for conditions under which the CFGPLLEN fuse is available. DS30000684B-page 372  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 26-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH R/P-0 R/P-0 R/P-1 U-0 R/P-0 R/P-1 R/P-0 R/P-1 IESO FCMEN PCLKEN — FOSC<3:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7 IESO(1): Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN(1): Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5 PCLKEN: Primary Clock Enable bit 1 = Primary Clock is always enabled 0 = Primary Clock can be disabled by software bit 4 Unimplemented: Read as ‘0’ bit 3-0 FOSC<3:0>: Oscillator Selection bits 1111 = Reserved 1110 = Reserved 1101 = EC oscillator (low power, <4 MHz) 1100 = EC oscillator, CLKO function on OSC2 (low power, <4 MHz) 1011 = EC oscillator (medium power, 4 MHz - 16 MHz) 1010 = EC oscillator, CLKO function on OSC2 (medium power, 4 MHz - 16 MHz) 1001 = Internal oscillator block, CLKO function on OSC2 1000 = Internal oscillator block 0111 = External RC oscillator 0110 = External RC oscillator, CLKO function on OSC2 0101 = EC oscillator (high power, 16 MHz - 48 MHz) 0100 = EC oscillator, CLKO function on OSC2 (high power, 16 MHz - 48 MHz) 0011= HS oscillator (medium power, 4 MHz - 16 MHz) 0010= HS oscillator (high power, 16 MHz - 25 MHz) 0001= XT oscillator 0000= LP oscillator Note 1: When FOSC<3:0> is configured for HS, XT, or LP oscillator and FCMEN bit is set, then the IESO bit should also be set to prevent a false failed clock indication and to enable automatic clock switch over from the internal oscillator block to the external oscillator when the OST times out.  2012-2014 Microchip Technology Inc. DS30000684B-page 373

PIC18(L)F2X/45K50 REGISTER 26-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW U-0 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — LPBOR — BORV<1:0>(1) BOREN<1:0>(2) PWRTEN(2) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 LPBOR: Low-Power Brown-out Reset Enable bits 1 = Low-Power Brown-out Reset disabled 0 = Low-Power Brown-out Reset enabled bit 5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1) 11 = VBOR set to 1.9V nominal 10 = VBOR set to 2.2V nominal 01 = VBOR set to 2.5V nominal 00 = VBOR set to 2.85V nominal bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits(2) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled Note 1: See Table29-1 for specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. DS30000684B-page 374  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 26-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — WDTPS<3:0> WDTEN<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 1-0 WDTEN<1:0>: Watchdog Timer Enable bits 11 = WDT enabled in hardware; SWDTEN bit disabled 10 = WDT controlled by the SWDTEN bit 01 = WDT enabled when device is active, disabled when device is in Sleep; SWDTEN bit disabled 00 = WDT disabled in hardware; SWDTEN bit disabled  2012-2014 Microchip Technology Inc. DS30000684B-page 375

PIC18(L)F2X/45K50 R EGISTER 26-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH R/P-1 R/P-1 U-0 R/P-1 U-0 U-0 R/P-1 R/P-1 MCLRE SDOMX — T3CMX — — PBADEN CCP2MX bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6 SDOMX: SDO Output MUX bit 1 = SDO is on RB3 0 = SDO is on RC7 bit 5 Unimplemented: Read as ‘0’ bit 4 T3CMX: Timer3 Clock Input MUX bit 1 = T3CKI is on RC0 0 = T3CKI is on RB5 bit 3-2 Unimplemented: Read as ‘0’ bit 1 PBADEN: PORTB A/D Enable bit 1 = ANSELB<5:0> resets to 1, PORTB<5:0> pins are configured as analog inputs on Reset 0 = ANSELB<5:0> resets to 0, PORTB<4:0> pins are configured as digital I/O on Reset bit 0 CCP2MX: CCP2 MUX bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 DS30000684B-page 376  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 26-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW R/P-1 R/P-0 R/P-1 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG(2) XINST ICPRT(3) — — LVP(1) — STVREN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit(2) 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5 ICPRT: Dedicated In-Circuit (ICD) Port Enable bit(3) 1 = ICPORT enabled (ICD function on dedicated ICD pins) 0 = ICPORT disabled (ICD function on default ICD pins, RB6/7) bit 4-3 Unimplemented: Read as ‘0’ bit 2 LVP: Single-Supply ICSP™ Enable bit 1 = Single-Supply ICSP™ enabled 0 = Single-Supply ICSP™ disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Note 1: Can only be changed by a programmer in high-voltage programming mode. 2: The DEBUG bit is managed automatically by device development tools including debuggers and programmers. For normal device operations, this bit should be maintained as a ‘1’. 3: Available only on 44-pin TQFP package devices. Program this bit clear on all other devices.  2012-2014 Microchip Technology Inc. DS30000684B-page 377

PIC18(L)F2X/45K50 REGISTER 26-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2(1) CP1 CP0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 not code-protected 0 = Block 3 code-protected bit 2 CP2: Code Protection bit(1) 1 = Block 2 not code-protected 0 = Block 2 code-protected bit 1 CP1: Code Protection bit 1 = Block 1 not code-protected 0 = Block 1 code-protected bit 0 CP0: Code Protection bit 1 = Block 0 not code-protected 0 = Block 0 code-protected Note 1: Available on PIC18(L)F45K50 and PIC18(L)F25K50 devices. REGISTER 26-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot Block not code-protected 0 = Boot Block code-protected bit 5-0 Unimplemented: Read as ‘0’ DS30000684B-page 378  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 26-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3(1) WRT2(1) WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 not write-protected 0 = Block 3 write-protected bit 2 WRT2: Write Protection bit(1) 1 = Block 2 not write-protected 0 = Block 2 write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 not write-protected 0 = Block 1 write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 not write-protected 0 = Block 0 write-protected Note 1: Available on PIC18(L)F45K50 and PIC18(L)F25K50 devices.  2012-2014 Microchip Technology Inc. DS30000684B-page 379

PIC18(L)F2X/45K50 REGISTER 26-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH R/C-1 R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot Block not write-protected 0 = Boot Block write-protected bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers not write-protected 0 = Configuration registers write-protected bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is read-only in normal execution mode; it can be written only in ICSP™ mode. REGISTER 26-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 not protected from table reads executed in other blocks 0 = Block 3 protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit(1) 1 = Block 2 not protected from table reads executed in other blocks 0 = Block 2 protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 not protected from table reads executed in other blocks 0 = Block 1 protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 not protected from table reads executed in other blocks 0 = Block 0 protected from table reads executed in other blocks Note 1: Available on PIC18(L)F45K50 and PIC18(L)F25K50 devices. DS30000684B-page 380  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 REGISTER 26-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot Block not protected from table reads executed in other blocks 0 = Boot Block protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ REGISTER 26-13: DEVID1: DEVICE ID REGISTER 1 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-5 DEV<2:0>: Device ID bits These bits, together with DEV<10:3> in DEVID2, determine the device ID. See Table26-2 for complete Device ID list. bit 4-0 REV<4:0>: Revision ID bits These bits indicate the device revision. REGISTER 26-14: DEVID2: DEVICE ID REGISTER 2 R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-0 DEV<10:3>: Device ID bits These bits, together with DEV<2:0> in DEVID1, determine the device ID. See Table26-2 for complete Device ID list.  2012-2014 Microchip Technology Inc. DS30000684B-page 381

PIC18(L)F2X/45K50 TABLE 26-2: DEVICE ID TABLE FOR THE PIC18(L)F2X/45K50 FAMILY DEV<10:3> DEV<2:0> Part Number 000 PIC18F45K50 001 PIC18F25K50 011 PIC18F24K50 0101 1100 100 PIC18LF45K50 101 PIC18LF25K50 111 PIC18LF24K50 DS30000684B-page 382  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 26.3 Watchdog Timer (WDT) For PIC18(L)F2X/45K50 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4ms and has the same stability as the INTRC oscillator. The 4ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configu- ration Register 2H. Available periods range from 4ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: a SLEEP or CLRWDT instruction is executed, the IRCF bits of the OSCCON register are changed or a clock failure has occurred. Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits of the OSCCON register clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared. FIGURE 26-1: WDT BLOCK DIAGRAM SWDTEN Enable WDT WDTEN WDT Counter INTRC Source 128 Wake-up from Power Managed Modes Change on IRCF bits Programmable Postscaler Reset WDT CLRWDT Reset 1:1 to 1:32,768 All Device Resets 4 WDTPS<3:0> Sleep  2012-2014 Microchip Technology Inc. DS30000684B-page 383

PIC18(L)F2X/45K50 26.3.1 CONTROL REGISTER Register26-15 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable Configuration bit, but only if the Configuration bit has disabled the WDT. 26.4 Register Definitions: WDT Control REGISTER 26-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note 1: This bit has no effect unless the Configuration bit, WDTEN<1:0>, is set to 10b (SWDTEN enabled). TABLE 26-3: REGISTERS ASSOCIATED WITH WATCHDOG TIMER Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page RCON IPEN SBOREN — RI TO PD POR BOR 64 WDTCON — — — — — — — SWDTEN 384 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the Watchdog Timer. TABLE 26-4: CONFIGURATION REGISTERS ASSOCIATED WITH WATCHDOG TIMER Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page CONFIG2H — — WDTPS<3:0> WDTEN<1:0> 375 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the Watchdog Timer. DS30000684B-page 384  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 26.5 Program Verification and Each of the blocks has three code protection bits Code Protection associated with them. They are: • Code-Protect bit (CPn) The overall structure of the code protection on the • Write-Protect bit (WRTn) PIC18 Flash devices differs significantly from other PIC microcontroller devices. • External Block Table Read bit (EBTRn) The user program memory is divided into three or five Figure26-2 shows the program memory organization blocks, depending on the device. One of these is a for 16 and 32-Kbyte devices and the specific code Boot Block of 0.5K or 2K bytes, depending on the protection bit associated with each block. The actual device. The remainder of the memory is divided into locations of the bits are summarized in Table26-5. individual blocks on binary boundaries. FIGURE 26-2: CODE-PROTECTED PROGRAM MEMORY FOR PIC18(L)F2X/45K50 MEMORY SIZE/DEVICE Block Code Protection 16Kbytes 32Kbytes Controlled By: (PIC18(L)F24K50) (PIC18(L)FX5K50) Boot Block Boot Block CPB, WRTB, EBTRB (000h-7FFh) (000h-7FFh) Block 0 Block 0 CP0, WRT0, EBTR0 (800h-1FFFh) (800h-1FFFh) Block 1 Block 1 CP1, WRT1, EBTR1 (2000h-3FFFh) (2000h-3FFFh) Block 2 CP2, WRT2, EBTR2 (4000h-5FFFh) Block 3 CP3, WRT3, EBTR3 (6000h-7FFFh) Unimplemented Read ‘0’s (4000h-1FFFFFh) Unimplemented (Unimplemented Read ‘0’s Memory Space) (8000h-1FFFFFh) TABLE 26-5: CONFIGURATION REGISTERS ASSOCIATED WITH CODE PROTECTION File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3(1) CP2(1) CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3(1) WRT2(1) WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC(2) — — — — — 30000Ch CONFIG7L — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded bits are unimplemented. Note 1: Available on PIC18(L)F45K50 and PIC18(L)F25K50 devices only. 2: In User mode, this bit is read-only and cannot be self-programmed.  2012-2014 Microchip Technology Inc. DS30000684B-page 385

PIC18(L)F2X/45K50 26.5.1 PROGRAM MEMORY instruction that executes from a location outside of that CODE PROTECTION block is not allowed to read and will result in reading ‘0’s. Figures26-3 through26-5 illustrate table write and table The program memory may be read to or written from read protection. any location using the table read and table write instructions. The device ID may be read with table Note: Code protection bits may only be written reads. The Configuration registers may be read and to a ‘0’ from a ‘1’ state. It is not possible to written with the table read and table write instructions. write a ‘1’ to a bit in the ‘0’ state. Code pro- tection bits are only set to ‘1’ by a full chip In normal execution mode, the CPn bits have no direct erase or block erase function. The full chip effect. CPn bits inhibit external reads and writes. A block erase and block erase functions can only of user memory may be protected from table writes if the be initiated via ICSP™ or an external WRTn Configuration bit is ‘0’. The EBTRn bits control programmer. table reads. For a block of user memory with the EBTRn bit cleared to ‘0’, a table READ instruction that executes from within that block is allowed to read. A table read FIGURE 26-3: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 01 PC = 001FFEh TBLWT* 001FFFh 002000h WRT1, EBTR1 = 11 003FFFh 004000h PC = 005FFEh TBLWT* WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table writes disabled to Blockn whenever WRTn = 0. DS30000684B-page 386  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 26-4: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 001FFFh 002000h PC = 003FFEh TBLRD* WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. FIGURE 26-5: INTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 PC = 001FFEh TBLRD* 001FFFh 002000h WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR.  2012-2014 Microchip Technology Inc. DS30000684B-page 387

PIC18(L)F2X/45K50 26.5.2 DATA EEPROM To use the In-Circuit Debugger function of the CODE PROTECTION microcontroller, the design must implement In-Circuit Serial Programming connections to the following pins: The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD • MCLR/VPP/RE3 inhibits external reads and writes of data EEPROM. • VDD WRTD inhibits internal and external writes to data • VSS EEPROM. The CPU can always read data EEPROM • RB7 under normal operation, regardless of the protection bit • RB6 settings. This will interface to the In-Circuit Debugger module 26.5.3 CONFIGURATION REGISTER available from Microchip or one of the third party PROTECTION development tool companies. The Configuration registers can be write-protected. 26.9 Special ICPORT Features The WRTC bit controls protection of the Configuration registers. In normal execution mode, the WRTC bit is (44-Pin TQFP Package Only) readable only. WRTC can only be written via ICSP or Under specific circumstances, the No Connect (NC) an external programmer. pins of devices in 44-pin TQFP packages can provide additional functionality. These features are controlled 26.6 ID Locations by device Configuration bits and are available only in Eight memory locations (200000h-200007h) are this package type and pin count. designated as ID locations, where the user can store 26.9.1 DEDICATED ICD/ICSP PORT checksum or other code identification numbers. These locations are both readable and writable during normal The 44-pin TQFP devices can use NC pins to provide execution through the TBLRD and TBLWT instructions an alternate port for In-Circuit Debugging (ICD) and In- or during program/verify. The ID locations can be read Circuit Serial Programming (ICSP). These pins are col- when the device is code-protected. lectively known as the dedicated ICSP/ICD port, since they are not shared with any other function of the 26.7 In-Circuit Serial Programming device. When implemented, the dedicated port activates three PIC18(L)F2X/45K50 devices can be serially NC pins to provide an alternate device Reset, data and programmed while in the end application circuit. This is clock ports. None of these ports overlap with standard simply done with two lines for clock and data and three I/O pins, making the I/O pins available to the user’s other lines for power, ground and the programming application. The port functions the same way as the voltage. This allows customers to manufacture boards legacy ICSP/ICD/MCLR pins on RB6/RB7/MCLR and with unprogrammed devices and then program the they have the same electrical specifications as their microcontroller just before shipping the product. This respective pins. also allows the most recent firmware or a custom firmware to be programmed. Table26-7 identifies the functionally equivalent pins for ICSP and ICD purposes. The dedicated ICSP/ICD 26.8 In-Circuit Debugger port is enabled by setting the ICPRT Configuration bit. This bit is set by default on 44-pin TQFP devices and When the DEBUG Configuration bit is programmed to can only be set and cleared when using the MCLR/ a ‘0’, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when RB6/RB7 ICSP interface. used with MPLAB® IDE. When the microcontroller has When ICPRT is set, several things must be taken into this feature enabled, some resources are not available consideration. First and foremost, the ICRST pin for general use. Table26-6 shows which resources are functions as an additional MCLR pin and must be required by the background debugger. pulled high to keep the part out of Reset. Second, while the MCLR/RB6/RB7 pins can still be used to program TABLE 26-6: DEBUGGER RESOURCES the part, the dedicated ICPORT pins must be used to debug the part. Finally, the MCLRE bit still works as I/O pins: RB6, RB7 normal, meaning that if ICPRT = 1 and MCLRE = 0, MCLR will function as a general purpose RE3 input, with the ICRST providing the normal MCLR Reset functions. DS30000684B-page 388  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 26-7: EQUIVALENT PINS FOR 26.10 Single-Supply ICSP Programming LEGACY AND DEDICATED The LVP Configuration bit enables Single-Supply ICSP ICD/ICSP™ PORTS Programming (formerly known as Low-Voltage ICSP Pin Name Programming or LVP). When Single-Supply Program- Pin ming is enabled, the microcontroller can be programmed Pin Function Legacy Dedicated Type without requiring high voltage being applied to the Port Port MCLR/VPP/RE3 pin. See “PIC18(L)F2X/4XK50 Flash MCLR/VPP/ NC/ICRST/ P Device Reset and Memory Programming Specification” (DS41630) for RE3 ICVPP Programming more details about low voltage programming. Enable Note1: High-voltage programming is always RB6/IOCB6/ NC/ICCK/ I Serial Clock available, regardless of the state of the PGC ICPGC LVP bit, by applying VIHH to the MCLR RB7/IOCB7/ NC/ICDT/ I/O Serial Data pin. PGD ICPGD 2: By default, Single-Supply ICSP™ is Legend: I = Input, O = Output, P = Power enabled in unprogrammed devices (as supplied from Microchip) and erased devices. 3: While in Low-Voltage ICSP™ mode, MCLR is always enabled, regardless of the MCLRE bit, and the RE3 pin can no longer be used as a general purpose input. The LVP bit may be set or cleared only when using standard high-voltage programming (VIHH applied to the MCLR/VPP/RE3 pin). Once LVP has been disabled, only the standard high-voltage programming is available and must be used to program the device. Memory that is not code-protected can be erased using either a block erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a block erase is required.  2012-2014 Microchip Technology Inc. DS30000684B-page 389

PIC18(L)F2X/45K50 27.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: PIC18(L)F2X/45K50 devices incorporate the standard • A literal value to be loaded into a file register set of 75 PIC18 core instructions, as well as an extended (specified by ‘k’) set of eight new instructions, for the optimization of code that is recursive or that utilizes a software stack. The • The desired FSR register to load the literal value extended set is discussed later in this section. into (specified by ‘f’) • No operand required 27.1 Standard Instruction Set (specified by ‘—’) The control instructions may use some of the following The standard PIC18 instruction set adds many operands: enhancements to the previous PIC MCU instruction sets, while maintaining an easy migration from these • A program memory address (specified by ‘n’) PIC MCU instruction sets. Most instructions are a • The mode of the CALL or RETURN instructions single program memory word (16 bits), but there are (specified by ‘s’) four instructions that require two program memory • The mode of the table read and table write locations. instructions (specified by ‘m’) Each single-word instruction is a 16-bit word divided • No operand required into an opcode, which specifies the instruction type and (specified by ‘—’) one or more operands, which further specify the All instructions are a single word, except for four operation of the instruction. double-word instructions. These instructions were The instruction set is highly orthogonal and is grouped made double-word to contain the required information into four basic categories: in 32 bits. In the second word, the 4 MSbs are ‘1’s. If this second word is executed as an instruction (by • Byte-oriented operations itself), it will execute as a NOP. • Bit-oriented operations All single-word instructions are executed in a single • Literal operations instruction cycle, unless a conditional test is true or the • Control operations program counter is changed as a result of the instruc- The PIC18 instruction set summary in Table27-2 lists tion. In these cases, the execution takes two instruction byte-oriented, bit-oriented, literal and control cycles, with the additional instruction cycle(s) executed operations. Table27-1 shows the opcode field as a NOP. descriptions. The double-word instructions execute in two instruction Most byte-oriented instructions have three operands: cycles. 1. The file register (specified by ‘f’) One instruction cycle consists of four oscillator periods. 2. The destination of the result (specified by ‘d’) Thus, for an oscillator frequency of 4MHz, the normal 3. The accessed memory (specified by ‘a’) instruction execution time is 1s. If a conditional test is true, or the program counter is changed as a result of The file register designator ‘f’ specifies which file an instruction, the instruction execution time is 2 s. register is to be used by the instruction. The destination Two-word branch instructions (if true) would take 3 s. designator ‘d’ specifies where the result of the opera- Figure27-1 shows the general formats that the instruc- tion is to be placed. If ‘d’ is zero, the result is placed in tions can have. All examples use the convention ‘nnh’ the WREG register. If ‘d’ is one, the result is placed in to represent a hexadecimal number. the file register specified in the instruction. The Instruction Set Summary, shown in Table27-2, All bit-oriented instructions have three operands: lists the standard instructions recognized by the 1. The file register (specified by ‘f’) Microchip Assembler (MPASMTM). 2. The bit in the file register (specified by ‘b’) Section27.1.1 “Standard Instruction Set” provides 3. The accessed memory (specified by ‘a’) a description of each instruction. The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register designator ‘f’ represents the number of the file in which the bit is located. DS30000684B-page 390  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 27-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). f 12-bit Register file address (000h to FFFh). This is the source address. s f 12-bit Register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for CALL/BRANCH and RETURN instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for indirect addressing of register files (source). s z 7-bit offset value for indirect addressing of register files (destination). d { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr.  Assigned to. < > Register bit field.  In the set of. italics User defined term (font is Courier).  2012-2014 Microchip Technology Inc. DS30000684B-page 391

PIC18(L)F2X/45K50 FIGURE 27-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC DS30000684B-page 392  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 27-2: PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and CARRY bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N borrow SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.  2012-2014 Microchip Technology Inc. DS30000684B-page 393

PIC18(L)F2X/45K50 TABLE 27-2: PIC18 INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL k, s Call subroutine 1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO k Go to address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software device Reset 1 0000 0000 1111 1111 All RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS30000684B-page 394  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 27-2: PIC18 INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY  PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.  2012-2014 Microchip Technology Inc. DS30000684B-page 395

PIC18(L)F2X/45K50 27.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) + k  W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f)  dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. Q Cycle Activity: If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to W set is enabled, this instruction operates literal ‘k’ Data in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Example: ADDLW 15h Bit-Oriented Instructions in Indexed Before Instruction Literal Offset Mode” for details. W = 10h Words: 1 After Instruction Cycles: 1 W = 25h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS30000684B-page 396  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 ADDWFC ADD W and CARRY bit to f ANDLW AND literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0  f  255 Operands: 0  k  255 d [0,1] Operation: (W) .AND. k  W a [0,1] Status Affected: N, Z Operation: (W) + (f) + (C)  dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are AND’ed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the CARRY flag and data mem- Words: 1 ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Decode Read literal Process Write to W If ‘a’ is ‘0’ and the extended instruction ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ANDLW 05Fh mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = A3h Literal Offset Mode” for details. After Instruction Words: 1 W = 03h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction CARRY bit= 1 REG = 02h W = 4Dh After Instruction CARRY bit= 0 REG = 02h W = 50h  2012-2014 Microchip Technology Inc. DS30000684B-page 397

PIC18(L)F2X/45K50 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0  f  255 Operands: -128  n  127 d [0,1] Operation: if CARRY bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: (W) .AND. (f)  dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the CARRY bit is ‘1’, then the program Description: The contents of W are AND’ed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’. incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC+2+2n. This instruction is then a GPR bank. two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Q Cycle Activity: Section27.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to PC Words: 1 ‘n’ Data Cycles: 1 No No No No operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If CARRY = 1; W = 02h PC = address (HERE + 12) REG = C2h If CARRY = 0; PC = address (HERE + 2) DS30000684B-page 398  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0  f  255 Operands: -128  n  127 0  b  7 Operation: if NEGATIVE bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: 0  f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the NEGATIVE bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank. incremented to fetch the next If ‘a’ is ‘0’ and the extended instruction instruction, the new address will be set is enabled, this instruction operates PC+2+2n. This instruction is then a in Indexed Literal Offset Addressing two-cycle instruction. mode whenever f 95 (5Fh). See Words: 1 Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1(2) Literal Offset Mode” for details. Q Cycle Activity: Words: 1 If Jump: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC Q Cycle Activity: ‘n’ Data Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No Before Instruction ‘n’ Data operation FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If NEGATIVE = 1; PC = address (Jump) If NEGATIVE = 0; PC = address (HERE + 2)  2012-2014 Microchip Technology Inc. DS30000684B-page 399

PIC18(L)F2X/45K50 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128  n  127 Operands: -128  n  127 Operation: if CARRY bit is ‘0’ Operation: if NEGATIVE bit is ‘0’ (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the CARRY bit is ‘0’, then the program Description: If the NEGATIVE bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If CARRY = 0; If NEGATIVE = 0; PC = address (Jump) PC = address (Jump) If CARRY = 1; If NEGATIVE = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS30000684B-page 400  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128  n  127 Operands: -128  n  127 Operation: if OVERFLOW bit is ‘0’ Operation: if ZERO bit is ‘0’ (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the OVERFLOW bit is ‘0’, then the Description: If the ZERO bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If OVERFLOW= 0; If ZERO = 0; PC = address (Jump) PC = address (Jump) If OVERFLOW= 1; If ZERO = 1; PC = address (HERE + 2) PC = address (HERE + 2)  2012-2014 Microchip Technology Inc. DS30000684B-page 401

PIC18(L)F2X/45K50 BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024  n  1023 Operands: 0  f  255 0  b  7 Operation: (PC) + 2 + 2n  PC a [0,1] Status Affected: None Operation: 1  f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incre- mented to fetch the next instruction, the Description: Bit ‘b’ in register ‘f’ is set. new address will be PC+2+2n. This If ‘a’ is ‘0’, the Access Bank is selected. instruction is a two-cycle instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section27.2.3 “Byte-Oriented and Decode Read literal Process Write to PC Bit-Oriented Instructions in Indexed ‘n’ Data Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah DS30000684B-page 402  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0  f  255 Operands: 0  f  255 0  b  7 0  b < 7 a [0,1] a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in set is enabled, this instruction operates Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and See Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: Three cycles if skip and followed Note: Three cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE)  2012-2014 Microchip Technology Inc. DS30000684B-page 403

PIC18(L)F2X/45K50 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0  f  255 Operands: -128  n  127 0  b < 7 Operation: if OVERFLOW bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: (f<b>)  f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the OVERFLOW bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank. instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC+2+2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: PORTC = 0110 0101 [65h] Before Instruction PC = address (HERE) After Instruction If OVERFLOW= 1; PC = address (Jump) If OVERFLOW= 0; PC = address (HERE + 2) DS30000684B-page 404  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128  n  127 Operands: 0  k  1048575 s [0,1] Operation: if ZERO bit is ‘1’ (PC) + 2 + 2n  PC Operation: (PC) + 4  TOS, k  PC<20:1>, Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (W)  WS, Description: If the ZERO bit is ‘1’, then the program (Status)  STATUSS, will branch. (BSR)  BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will Encoding: have incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk PC+2+2n. This instruction is then a 19 8 two-cycle instruction. Description: Subroutine call of entire 2-Mbyte memory range. First, return address Words: 1 (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, Status and BSR Q Cycle Activity: registers are also pushed into their If Jump: respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs. Then, the Decode Read literal Process Write to PC 20-bit value ‘k’ is loaded into PC<20:1>. ‘n’ Data CALL is a two-cycle instruction. No No No No Words: 2 operation operation operation operation If No Jump: Cycles: 2 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process No Q1 Q2 Q3 Q4 ‘n’ Data operation Decode Read literal PUSH PC to Read literal ‘k’<7:0>, stack ‘k’<19:8>, Example: HERE BZ Jump Write to PC No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction If ZERO = 1; Example: HERE CALL THERE, 1 PC = address (Jump) If ZERO = 0; Before Instruction PC = address (HERE + 2) PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= Status  2012-2014 Microchip Technology Inc. DS30000684B-page 405

PIC18(L)F2X/45K50 CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0  f  255 Operands: None a [0,1] Operation: 000h  WDT, Operation: 000h  f 000h  WDT postscaler, 1  Z 1  TO, 1  PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the post- If ‘a’ is ‘1’, the BSR is used to select the scaler of the WDT. Status bits, TO and GPR bank. PD, are set. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1 mode whenever f 95 (5Fh). See Q Cycle Activity: Section27.2.3 “Byte-Oriented and Q1 Q2 Q3 Q4 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Decode No Process No operation Data operation Words: 1 Cycles: 1 Example: CLRWDT Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 WDT Counter = ? Decode Read Process Write After Instruction register ‘f’ Data register ‘f’ WDT Counter = 00h WDT Postscaler = 0 TO = 1 Example: CLRF FLAG_REG, 1 PD = 1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h DS30000684B-page 406  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: (f)  dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’. If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank. instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank. mode whenever f 95 (5Fh). See If ‘a’ is ‘0’ and the extended instruction Section27.2.3 “Byte-Oriented and set is enabled, this instruction operates Bit-Oriented Instructions in Indexed in Indexed Literal Offset Addressing Literal Offset Mode” for details. mode whenever f 95 (5Fh). See Words: 1 Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process Write to Note: Three cycles if skip and register ‘f’ Data destination followed by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h Q1 Q2 Q3 Q4 W = ECh No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG  W; PC = Address (NEQUAL)  2012-2014 Microchip Technology Inc. DS30000684B-page 407

PIC18(L)F2X/45K50 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0  f  255 Operands: 0  f  255 a  [0,1] a  [0,1] Operation: (f) –W), Operation: (f) –W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory Description: Compares the contents of data memory location ‘f’ to the contents of the W by location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the , If the contents of ‘f’ are less than the contents of WREG then the fetched contents of W, then the fetched instruction is discarded and a NOP is instruction is discarded and a NOP is executed instead, making this a executed instead, making this a two-cycle instruction. two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Note: Three cycles if skip and Section27.2.3 “Byte-Oriented and followed by a 2-word instruction. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process No Cycles: 1(2) Note: Three cycles if skip and followed register ‘f’ Data operation by a 2-word instruction. If skip: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No Decode Read Process No operation operation operation operation register ‘f’ Data operation If skip and followed by 2-word instruction: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; Before Instruction PC = Address (LESS) PC = Address (HERE) If REG  W; W = ? PC = Address (NLESS) After Instruction If REG  W; PC = Address (GREATER) If REG  W; PC = Address (NGREATER) DS30000684B-page 408  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0  f  255 d  [0,1] Operation: If [W<3:0> > 9] or [DC = 1] then a  [0,1] (W<3:0>) + 6  W<3:0>; else Operation: (f) – 1  dest ( W<3:0>)  W<3:0>; Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then Encoding: 0000 01da ffff ffff ( W<7:4>) + 6 + DC  W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the C = 1; result is stored in W. If ‘d’ is ‘1’, the else result is stored back in register ‘f’. (W<7:4>) + DC  W<7:4> If ‘a’ is ‘0’, the Access Bank is selected. Status Affected: C If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘0’ and the extended instruction Description: DAW adjusts the eight-bit value in W, set is enabled, this instruction operates resulting from the earlier addition of two in Indexed Literal Offset Addressing variables (each in packed BCD format) mode whenever f 95 (5Fh). See and produces a correct packed BCD Section27.2.3 “Byte-Oriented and result. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write Q1 Q2 Q3 Q4 register W Data W Decode Read Process Write to Example1: register ‘f’ Data destination DAW Before Instruction Example: DECF CNT, 1, 0 W = A5h Before Instruction C = 0 CNT = 01h DC = 0 Z = 0 After Instruction After Instruction CNT = 00h W = 05h Z = 1 C = 1 DC = 0 Example 2: Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0  2012-2014 Microchip Technology Inc. DS30000684B-page 409

PIC18(L)F2X/45K50 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – 1  dest, Operation: (f) – 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’. placed back in register ‘f’. If the result is ‘0’, the next instruction, If the result is not ‘0’, the next which is already fetched, is discarded instruction, which is already fetched, is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank. set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing Section27.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See Bit-Oriented Instructions in Indexed Section27.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: Three cycles if skip and Cycles: 1(2) followed by a 2-word instruction. Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT - 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT  0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP  0; PC = Address (NZERO) DS30000684B-page 410  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0  k  1048575 Operands: 0  f  255 d  [0,1] Operation: k  PC<20:1> a  [0,1] Status Affected: None Operation: (f) + 1  dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire incremented. If ‘d’ is ‘0’, the result is 2-Mbyte memory range. The 20-bit placed in W. If ‘d’ is ‘1’, the result is value ‘k’ is loaded into PC<20:1>. placed back in register ‘f’. GOTO is always a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 2 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section27.2.3 “Byte-Oriented and Decode Read literal No Read literal Bit-Oriented Instructions in Indexed ‘k’<7:0>, operation ‘k’<19:8>, Literal Offset Mode” for details. Write to PC Words: 1 No No No No operation operation operation operation Cycles: 1 Q Cycle Activity: Example: GOTO THERE Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to PC = Address (THERE) register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1  2012-2014 Microchip Technology Inc. DS30000684B-page 411

PIC18(L)F2X/45K50 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) + 1  dest, Operation: (f) + 1  dest, skip if result  0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’. placed back in register ‘f’. If the result is not ‘0’, the next If the result is ‘0’, the next instruction, instruction, which is already fetched, is which is already fetched, is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG  0; PC = Address (ZERO) PC = Address (NZERO) If CNT  0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) DS30000684B-page 412  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) .OR. k  W a  [0,1] Status Affected: N, Z Operation: (W) .OR. (f)  dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. Q Cycle Activity: If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to W set is enabled, this instruction operates literal ‘k’ Data in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: IORLW 35h Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Before Instruction Literal Offset Mode” for details. W = 9Ah Words: 1 After Instruction Cycles: 1 W = BFh Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h  2012-2014 Microchip Technology Inc. DS30000684B-page 413

PIC18(L)F2X/45K50 LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0  f  2 Operands: 0  f  255 0  k  4095 d  [0,1] a  [0,1] Operation: k  FSRf Operation: f  dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to File Select Register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’. Location ‘f’ Q Cycle Activity: can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read literal Process Write If ‘a’ is ‘1’, the BSR is used to select the ‘k’ MSB Data literal ‘k’ GPR bank. MSB to If ‘a’ is ‘0’ and the extended instruction FSRfH set is enabled, this instruction operates Decode Read literal Process Write literal in Indexed Literal Offset Addressing ‘k’ LSB Data ‘k’ to FSRfL mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Example: LFSR 2, 3ABh Literal Offset Mode” for details. After Instruction Words: 1 FSR2H = 03h FSR2L = ABh Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write W register ‘f’ Data Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h DS30000684B-page 414  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLB k s d Operands: 0  f  4095 Operands: 0  k  255 s 0  f  4095 d Operation: k  BSR Operation: (f )  f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffffs Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffffd of BSR<7:4> always remains ‘0’, Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Either source or destination can be W Decode Read Process Write literal (a useful special situation). literal ‘k’ Data ‘k’ to BSR MOVFF is particularly useful for transferring a data memory location to a Example: MOVLB 5 peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h The MOVFF instruction cannot use the After Instruction PCL, TOSU, TOSH or TOSL as the BSR Register = 05h destination register. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h  2012-2014 Microchip Technology Inc. DS30000684B-page 415

PIC18(L)F2X/45K50 MOVLW Move literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: k  W Operation: (W)  f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: MOVLW 5Ah mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 5Ah Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh DS30000684B-page 416  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 MULLW Multiply literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: (W) x k  PRODH:PRODL Operation: (W) x (f)  PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried 8-bit literal ‘k’. The 16-bit result is out between the contents of W and the placed in the PRODH:PRODL register register file location ‘f’. The 16-bit pair. PRODH contains the high byte. result is stored in the PRODH:PRODL W is unchanged. register pair. PRODH contains the None of the Status flags are affected. high byte. Both W and ‘f’ are Note that neither overflow nor carry is unchanged. possible in this operation. A zero result None of the Status flags are affected. is possible but not detected. Note that neither overflow nor carry is possible in this operation. A zero Words: 1 result is possible but not detected. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is Q Cycle Activity: selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write set is enabled, this instruction literal ‘k’ Data registers operates in Indexed Literal Offset PRODH: Addressing mode whenever PRODL f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Bit-Oriented Example: MULLW 0C4h Instructions in Indexed Literal Offset Mode” for details. Before Instruction Words: 1 W = E2h PRODH = ? Cycles: 1 PRODL = ? Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = E2h PRODH = ADh Decode Read Process Write PRODL = 08h register ‘f’ Data registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h  2012-2014 Microchip Technology Inc. DS30000684B-page 417

PIC18(L)F2X/45K50 NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0  f  255 Operands: None a  [0,1] Operation: No operation Operation: (f) + 1  f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Decode No No No in Indexed Literal Offset Addressing operation operation operation mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Example: Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] DS30000684B-page 418  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC+2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah  2012-2014 Microchip Technology Inc. DS30000684B-page 419

PIC18(L)F2X/45K50 RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n  PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset by software. address (PC+2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC+2+2n. This instruction is a two-cycle instruction. Decode Start No No Reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to PC Flags* = Reset Value ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2) DS30000684B-page 420  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 RETFIE Return from Interrupt RETLW Return literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, Operation: k  W, 1  GIE/GIEH or PEIE/GIEL, (TOS)  PC, if s = 1 PCLATU, PCLATH are unchanged (WS)  W, Status Affected: None (STATUSS)  Status, (BSRS)  BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged. Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers, WS, Q1 Q2 Q3 Q4 STATUSS and BSRS, are loaded into their corresponding registers, W, Decode Read Process POP PC STATUS and BSR. If ‘s’ = 0, no update literal ‘k’ Data from stack, of these registers occurs. Write to W No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS W = WS RETLW kn ; End of table BSR = BSRS Status = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn  2012-2014 Microchip Technology Inc. DS30000684B-page 421

PIC18(L)F2X/45K50 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s  [0,1] Operands: 0  f  255 d  [0,1] Operation: (TOS)  PC, a  [0,1] if s = 1 (WS)  W, Operation: (f<n>)  dest<n + 1>, (STATUSS)  Status, (f<7>)  C, (BSRS)  BSR, (C)  dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the CARRY popped and the top of the stack (TOS) flag. If ‘d’ is ‘0’, the result is placed in is loaded into the program counter. If W. If ‘d’ is ‘1’, the result is stored back ‘s’= 1, the contents of the shadow in register ‘f’. registers, WS, STATUSS and BSRS, If ‘a’ is ‘0’, the Access Bank is are loaded into their corresponding selected. If ‘a’ is ‘1’, the BSR is used to registers, W, STATUS and BSR. If select the GPR bank. ‘s’ = 0, no update of these registers If ‘a’ is ‘0’ and the extended instruction occurs. set is enabled, this instruction operates in Indexed Literal Offset Words: 1 Addressing mode whenever Cycles: 2 f 95 (5Fh). See Section27.2.3 Q Cycle Activity: “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Q1 Q2 Q3 Q4 Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 DS30000684B-page 422  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f<n>)  dest<n + 1>, Operation: (f<n>)  dest<n – 1>, (f<7>)  dest<0> (f<0>)  C, (C)  dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the CARRY stored back in register ‘f’. flag. If ‘d’ is ‘0’, the result is placed in W. If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘1’, the BSR is used to select the register ‘f’. GPR bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the set is enabled, this instruction operates GPR bank. in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f 95 (5Fh). See set is enabled, this instruction operates Section27.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f 95 (5Fh). See Literal Offset Mode” for details. Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0  2012-2014 Microchip Technology Inc. DS30000684B-page 423

PIC18(L)F2X/45K50 RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a [0,1] a  [0,1] Operation: FFh  f Operation: (f<n>)  dest<n – 1>, Status Affected: None (f<0>)  dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank. placed back in register ‘f’. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f 95 (5Fh). See per the BSR value. Section27.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG, 1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 DS30000684B-page 424  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 SLEEP Enter Sleep mode SUBFWB Subtract f from W with borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 f 255 d  [0,1] Operation: 00h  WDT, a  [0,1] 0  WDT postscaler, 1  TO, Operation: (W) – (f) – (C) dest 0  PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and CARRY flag Description: The Power-down Status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out Status bit (TO) method). If ‘d’ is ‘0’, the result is stored is set. The Watchdog Timer and its in W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’. The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is with the oscillator stopped. selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction Q Cycle Activity: operates in Indexed Literal Offset Addressing mode whenever Q1 Q2 Q3 Q4 f 95 (5Fh). See Section27.2.3 Decode No Process Go to “Byte-Oriented and Bit-Oriented operation Data Sleep Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? After Instruction Q1 Q2 Q3 Q4 TO = 1 † Decode Read Process Write to PD = 0 register ‘f’ Data destination Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0  2012-2014 Microchip Technology Inc. DS30000684B-page 425

PIC18(L)F2X/45K50 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 k 255 Operands: 0 f 255 d  [0,1] Operation: k – (W) W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the Q Cycle Activity: result is stored back in register ‘f’. If ‘a’ is ‘0’, the Access Bank is Q1 Q2 Q3 Q4 selected. If ‘a’ is ‘1’, the BSR is used Decode Read Process Write to W to select the GPR bank. literal ‘k’ Data If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction Example 1: SUBLW 02h operates in Indexed Literal Offset Before Instruction Addressing mode whenever W = 01h f 95 (5Fh). See Section27.2.3 C = ? “Byte-Oriented and Bit-Oriented After Instruction W = 01h Instructions in Indexed Literal Offset C = 1 ; result is positive Mode” for details. Z = 0 Words: 1 N = 0 Example 2: SUBLW 02h Cycles: 1 Before Instruction Q Cycle Activity: W = 02h Q1 Q2 Q3 Q4 C = ? Decode Read Process Write to After Instruction W = 00h register ‘f’ Data destination C = 1 ; result is zero Z = 1 Example 1: SUBWF REG, 1, 0 N = 0 Before Instruction REG = 3 Example 3: SUBLW 02h W = 2 Before Instruction C = ? W = 03h After Instruction C = ? REG = 1 After Instruction W = 2 W = FFh ; (2’s complement) C = 1 ; result is positive C = 0 ; result is negative Z = 0 Z = 0 N = 0 N = 1 Example 2: SUBWF REG, 0, 0 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 DS30000684B-page 426  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: (f<3:0>)  dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>)  dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the CARRY flag Encoding: 0011 10da ffff ffff (borrow) from register ‘f’ (2’s comple- Description: The upper and lower nibbles of register ment method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is ‘f’ are exchanged. If ‘d’ is ‘0’, the result stored back in register ‘f’. is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1100) After Instruction W = 0Dh (0000 1101) C = 1 REG = 35h Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1110) C = 1 After Instruction REG = F5h (1111 0101) ; [2’s comp] W = 0Eh (0000 1110) C = 0 Z = 0 N = 1 ; result is negative  2012-2014 Microchip Technology Inc. DS30000684B-page 427

PIC18(L)F2X/45K50 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR))  TABLAT; MEMORY (00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR))  TABLAT; TBLPTR = 00A357h (TBLPTR) + 1  TBLPTR; Example2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR))  TABLAT; Before Instruction (TBLPTR) – 1  TBLPTR; TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY (01A357h) = 12h (TBLPTR) + 1  TBLPTR; MEMORY (01A358h) = 34h (Prog Mem (TBLPTR))  TABLAT; After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write TABLAT) Memory) DS30000684B-page 428  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT)  Holding Register; TBLPTR = 00A356h TBLPTR – No Change; HOLDING REGISTER (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT)  Holding Register; TABLAT = 55h (TBLPTR) + 1  TBLPTR; TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT)  Holding Register; (00A356h) = 55h (TBLPTR) – 1  TBLPTR; Example 2: TBLWT +*; if TBLWT+*, (TBLPTR) + 1  TBLPTR; Before Instruction (TABLAT)  Holding Register; TABLAT = 34h TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the three LSBs of (01389Ah) = FFh TBLPTR to determine which of the eight HOLDING REGISTER holding registers the TABLAT is written to. (01389Bh) = 34h The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section7.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register )  2012-2014 Microchip Technology Inc. DS30000684B-page 429

PIC18(L)F2X/45K50 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0  f  255 Operands: 0 k 255 a  [0,1] Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Decode Read Process Write to W in Indexed Literal Offset Addressing literal ‘k’ Data mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Example: XORLW 0AFh Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Before Instruction W = B5h Words: 1 After Instruction Cycles: 1(2) W = 1Ah Note: Three cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT  00h, PC = Address (NZERO) DS30000684B-page 430  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h  2012-2014 Microchip Technology Inc. DS30000684B-page 431

PIC18(L)F2X/45K50 27.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table27-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section27.2.2 “Extended Instruction instruction set, PIC18(L)F2X/45K50 devices also Set”. The opcode field descriptions in Table27-1 apply provide an optional extension to the core CPU to both the standard and extended PIC18 instruction functionality. The added features include eight sets. additional instructions that augment indirect and indexed addressing operations and the implementation Note: The instruction set extension and the of Indexed Literal Offset Addressing mode for many of Indexed Literal Offset Addressing mode the standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction set these instructions directly in assembler. are disabled by default. To enable them, users must set The syntax for these commands is pro- the XINST Configuration bit. vided as a reference for users who may be The instructions in the extended set can all be reviewing code that has been generated classified as literal operations, which either manipulate by a compiler. the File Select Registers, or use them for indexed addressing. Two of the instructions, ADDFSR and 27.2.1 EXTENDED INSTRUCTION SYNTAX SUBFSR, each have an additional special instantiation Most of the extended instructions use indexed for using FSR2. These versions (ADDULNK and arguments, using one of the File Select Registers and SUBULNK) allow for automatic return after execution. some offset to specify a source or destination register. The extended instructions are specifically implemented When an argument for an instruction serves as part of to optimize re-entrant program code (that is, code that indexed addressing, it is enclosed in square brackets is recursive or that uses a software stack) written in (“[ ]”). This is done to indicate that the argument is used high-level languages, particularly C. Among other as an index or offset. MPASM™ Assembler will flag an things, they allow users working in high-level error if it determines that an index or offset value is not languages to perform certain operations on data bracketed. structures more efficiently. These include: When the extended instruction set is enabled, brackets • dynamic allocation and deallocation of software are also used to indicate index arguments in byte- stack space when entering and leaving oriented and bit-oriented instructions. This is in addition subroutines to other changes in their syntax. For more details, see • function pointer invocation Section27.2.3.1 “Extended Instruction Syntax with • software Stack Pointer manipulation Standard PIC18 Commands”. • manipulation of variables located in a software Note: In the past, square brackets have been stack used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 27-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add literal to FSR2 and return 2 1110 1000 11kk kkkk None CALLW Call subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz PUSHL k Store literal at FSR2, 1 1110 1010 kkkk kkkk None decrement FSR2 SUBFSR f, k Subtract literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract literal from FSR2 and 2 1110 1001 11kk kkkk None return DS30000684B-page 432  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 27.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 + k  FSR2, Operation: FSR(f) + k  FSR(f) (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during Q1 Q2 Q3 Q4 the second cycle. Decode Read Process Write to This may be thought of as a special literal ‘k’ Data FSR case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Example: ADDFSR 2, 23h Words: 1 Before Instruction Cycles: 2 FSR2 = 03FFh After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).  2012-2014 Microchip Technology Inc. DS30000684B-page 433

PIC18(L)F2X/45K50 CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0  z  127 s 0  f  4095 Operation: (PC + 2)  TOS, d (W)  PCL, Operation: ((FSR2) + z )  f s d (PCLATH)  PCH, Status Affected: None (PCLATU)  PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’ in the first word to the value of s latched into PCH and PCU, FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘f ’ in the second word. Both addresses d new next instruction is fetched. can be anywhere in the 4096-byte data Unlike CALL, there is no option to space (000h to FFFh). update W, Status or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an indirect addressing register, the value returned will be 00h. Q1 Q2 Q3 Q4 Decode Read PUSH PC to No Words: 2 WREG stack operation Cycles: 2 No No No No Q Cycle Activity: operation operation operation operation Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Decode No No Write Before Instruction operation operation register ‘f’ PC = address (HERE) PCLATH = 10h No dummy (dest) PCLATU = 00h read W = 06h After Instruction PC = 001006h Example: MOVSF [05h], REG2 TOS = address (HERE + 2) PCLATH = 10h Before Instruction PCLATU = 00h FSR2 = 80h W = 06h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h DS30000684B-page 434  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0  zs  127 Operands: 0k  255 0  z  127 d Operation: k  (FSR2), Operation: ((FSR2) + zs)  ((FSR2) + zd) FSR2 – 1  FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1111 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. FSR2 Description The contents of the source register are is decremented by 1 after the operation. moved to the destination register. The This instruction allows users to push values addresses of the source and destination onto a software stack. registers are determined by adding the 7-bit literal offsets ‘z ’ or ‘z ’, Words: 1 s d respectively, to the value of FSR2. Both Cycles: 1 registers can be located anywhere in the 4096-byte data memory space Q Cycle Activity: (000h to FFFh). Q1 Q2 Q3 Q4 The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to PCL, TOSU, TOSH or TOSL as the data destination destination register. If the resultant source address points to an indirect addressing register, the Example: PUSHL 08h value returned will be 00h. If the resultant destination address points to Before Instruction an indirect addressing register, the FSR2H:FSR2L = 01ECh Memory (01ECh) = 00h instruction will execute as a NOP. Words: 2 After Instruction FSR2H:FSR2L = 01EBh Cycles: 2 Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h  2012-2014 Microchip Technology Inc. DS30000684B-page 435

PIC18(L)F2X/45K50 SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 – k  FSR2 Operation: FSR(f) – k  FSRf (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified by contents of the FSR2. A RETURN is then ‘f’. executed by loading the PC with the TOS. Words: 1 The instruction takes two cycles to execute; a NOP is performed during the Cycles: 1 second cycle. Q Cycle Activity: This may be thought of as a special case of Q1 Q2 Q3 Q4 the SUBFSR instruction, where f = 3 (binary Decode Read Process Write to ‘11’); it operates only on FSR2. register ‘f’ Data destination Words: 1 Cycles: 2 Q Cycle Activity: Example: SUBFSR 2, 23h Q1 Q2 Q3 Q4 Before Instruction FSR2 = 03FFh Decode Read Process Write to register ‘f’ Data destination After Instruction FSR2 = 03DCh No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) DS30000684B-page 436  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 27.2.3 BYTE-ORIENTED AND 27.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file register argument, ‘f’, in the standard byte-oriented and Note: Enabling the PIC18 instruction set bit-oriented commands is replaced with the literal offset extension may cause legacy applications value, ‘k’. As already noted, this occurs only when ‘f’ is to behave erratically or fail entirely. less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing mode (Section6.7.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within brackets, will generate an the standard PIC18 instruction set are interpreted. error in the MPASM assembler. When the extended set is disabled, addresses If the index argument is properly bracketed for Indexed embedded in opcodes are treated as literal memory Literal Offset Addressing, the Access RAM argument is locations: either as a location in the Access Bank (‘a’ = never specified; it will automatically be assumed to be 0), or in a GPR bank designated by the BSR (‘a’ = 1). ‘0’. This is in contrast to standard operation (extended When the extended instruction set is enabled and ‘a’ = instruction set disabled) when ‘a’ is set on the basis of 0, however, a file register argument of 5Fh or less is the target address. Declaring the Access RAM bit in interpreted as an offset from the pointer value in FSR2 this mode will also generate an error in the MPASM and not as a literal address. For practical purposes, this assembler. means that all instructions that use the Access RAM bit The destination argument, ‘d’, functions as before. as an argument – that is, all byte-oriented and bit- oriented instructions, or almost half of the core PIC18 In the latest versions of the MPASM™ assembler, instructions – may behave differently when the language support for the extended instruction set must extended instruction set is enabled. be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the When the content of FSR2 is 00h, the boundaries of the source listing. Access RAM are essentially remapped to their original values. This may be useful in creating backward 27.2.4 CONSIDERATIONS WHEN compatible code. If this technique is used, it may be ENABLING THE EXTENDED necessary to save the value of FSR2 and restore it INSTRUCTION SET when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users It is important to note that the extensions to the instruc- must also keep in mind the syntax requirements of the tion set may not be beneficial to all users. In particular, extended instruction set (see Section27.2.3.1 users who are not writing code that uses a software “Extended Instruction Syntax with Standard PIC18 stack may not benefit from using the extensions to the Commands”). instruction set. Although the Indexed Literal Offset Addressing mode Additionally, the Indexed Literal Offset Addressing can be very useful for dynamic stack and pointer mode may create issues with legacy applications manipulation, it can also be very annoying if a simple written to the PIC18 assembler. This is because arithmetic operation is carried out on the wrong instructions in the legacy code may attempt to address register. Users who are accustomed to the PIC18 registers in the Access Bank below 5Fh. Since these programming must keep in mind that, when the addresses are interpreted as literal offsets to FSR2 extended instruction set is enabled, register addresses when the instruction set extension is enabled, the of 5Fh or less are used for Indexed Literal Offset application may read or write to the wrong data Addressing. addresses. Representative examples of typical byte-oriented and When porting an application to the PIC18(L)F2X/ bit-oriented instructions in the Indexed Literal Offset 45K50, it is very important to consider the type of code. Addressing mode are provided on the following page to A large, re-entrant application that is written in ‘C’ and show how execution is affected. The operand condi- would benefit from efficient compilation will do well tions shown in the examples are applicable to all when using the instruction set extensions. Legacy instructions of these types. applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set.  2012-2014 Microchip Technology Inc. DS30000684B-page 437

PIC18(L)F2X/45K50 ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0  k  95 Operands: 0  f  95 d  [0,1] 0  b  7 Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in Cycles: 1 register ‘f’. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Example: ADDWF [OFST], 0 Contents of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction W = 37h Set Indexed Contents SETF of 0A2Ch = 20h (Indexed Literal Offset mode) Syntax: SETF [k] Operands: 0  k  95 Operation: FFh  ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh DS30000684B-page 438  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 27.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18(L)F2X/45K50 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is ‘0’, disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: • A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project • A command line option • A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information.  2012-2014 Microchip Technology Inc. DS30000684B-page 439

PIC18(L)F2X/45K50 28.0 DEVELOPMENT SUPPORT 28.1 MPLAB X Integrated Development Environment Software The PIC microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, - MPLAB® X IDE Software Linux and Mac OS® X. Based on the NetBeans IDE, • Compilers/Assemblers/Linkers MPLAB X IDE is an entirely new IDE with a host of free - MPLAB XC Compiler software components and plug-ins for high- - MPASMTM Assembler performance application development and debugging. - MPLINKTM Object Linker/ Moving between tools and upgrading from software MPLIBTM Object Librarian simulators to hardware debugging and programming - MPLAB Assembler/Linker/Librarian for tools is simple with the seamless user interface. Various Device Families With complete project management, visual call graphs, • Simulators a configurable watch window and a feature-rich editor - MPLAB X SIM Software Simulator that includes code completion and context menus, • Emulators MPLAB X IDE is flexible and friendly enough for new - MPLAB REAL ICE™ In-Circuit Emulator users. With the ability to support multiple tools on • In-Circuit Debuggers/Programmers multiple projects with simultaneous debugging, MPLAB - MPLAB ICD 3 X IDE is also suitable for the needs of experienced - PICkit™ 3 users. • Device Programmers Feature-Rich Editor: - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, • Color syntax highlighting Evaluation Kits and Starter Kits • Smart code completion makes suggestions and • Third-party development tools provides hints as you type • Automatic code formatting based on user-defined rules • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker DS30000684B-page 440  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 28.2 MPLAB XC Compilers 28.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other related modules together relocatable object files and archives to create an • Flexible creation of libraries with easy module executable file. MPLAB XC Compiler uses the listing, replacement, deletion and extraction assembler to produce its object file. Notable features of the assembler include: 28.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine • Flexible macro language code from symbolic assembly language for PIC24, • MPLAB X IDE compatibility PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The 28.3 MPASM Assembler assembler generates relocatable object files that can then be archived or linked with other relocatable object The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable macro assembler for PIC10/12/16/18 MCUs. features of the assembler include: The MPASM Assembler generates relocatable object • Support for the entire device instruction set files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process  2012-2014 Microchip Technology Inc. DS30000684B-page 441

PIC18(L)F2X/45K50 28.6 MPLAB X SIM Software Simulator 28.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by The MPLAB ICD 3 In-Circuit Debugger System is simulating the PIC MCUs and dsPIC DSCs on an Microchip’s most cost-effective, high-speed hardware instruction level. On any given instruction, the data debugger/programmer for Microchip Flash DSC and areas can be examined or modified and stimuli can be MCU devices. It debugs and programs PIC Flash applied from a comprehensive stimulus controller. microcontrollers and dsPIC DSCs with the powerful, Registers can be logged to files for further run-time yet easy-to-use graphical user interface of the MPLAB analysis. The trace buffer and logic analyzer display IDE. extend the power of the simulator to record and track The MPLAB ICD 3 In-Circuit Debugger probe is program execution, actions on I/O, most peripherals connected to the design engineer’s PC using a high- and internal registers. speed USB 2.0 interface and is connected to the target The MPLAB X SIM Software Simulator fully supports with a connector compatible with the MPLAB ICD 2 or symbolic debugging using the MPLAB XCCompilers, MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 and the MPASM and MPLAB Assemblers. The supports all MPLAB ICD 2 headers. software simulator offers the flexibility to develop and debug code outside of the hardware laboratory 28.9 PICkit 3 In-Circuit Debugger/ environment, making it an excellent, economical Programmer software development tool. The MPLAB PICkit 3 allows debugging and 28.7 MPLAB REAL ICE In-Circuit programming of PIC and dsPIC Flash microcontrollers Emulator System at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The The MPLAB REAL ICE In-Circuit Emulator System is MPLAB PICkit 3 is connected to the design engineer’s Microchip’s next generation high-speed emulator for PC using a full-speed USB interface and can be Microchip Flash DSC and MCU devices. It debugs and connected to the target via a Microchip debug (RJ-11) programs all 8, 16 and 32-bit MCU, and DSC devices connector (compatible with MPLAB ICD 3 and MPLAB with the easy-to-use, powerful graphical user interface of REAL ICE). The connector uses two device I/O pins the MPLAB X IDE. and the Reset line to implement in-circuit debugging The emulator is connected to the design engineer’s and In-Circuit Serial Programming (ICSP). PC using a high-speed USB 2.0 interface and is connected to the target with either a connector 28.10 MPLAB PM3 Device Programmer compatible with in-circuit debugger systems (RJ-11) The MPLAB PM3 Device Programmer is a universal, or with the new high-speed, noise tolerant, Low- CE compliant device programmer with programmable Voltage Differential Signal (LVDS) interconnection (CAT5). voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display The emulator is field upgradeable through future (128 x 64) for menus and error messages, and a firmware downloads in MPLAB X IDE. MPLAB REAL modular, detachable socket assembly to support ICE offers significant advantages over competitive various package types. The ICSP cable assembly is emulators including full-speed emulation, run-time included as a standard item. In Stand-Alone mode, the variable watches, trace analysis, complex breakpoints, MPLAB PM3 Device Programmer can read, verify and logic probes, a ruggedized probe interface and long (up program PIC devices without a PC connection. It can to three meters) interconnection cables. also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS30000684B-page 442  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 28.11 Demonstration/Development 28.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide and Trace Systems application firmware and source code for examination • Protocol Analyzers from companies, such as and modification. Saleae and Total Phase • Demonstration Boards from companies, such as The boards support a variety of features, including LEDs, MikroElektronika, Digilent® and Olimex temperature sensors, switches, speakers, RS-232 • Embedded Ethernet Solutions from companies, interfaces, LCD displays, potentiometers and additional such as EZ Web Lynx, WIZnet and IPLogika® EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2012-2014 Microchip Technology Inc. DS30000684B-page 443

PIC18(L)F2X/45K50 29.0 ELECTRICAL SPECIFICATIONS 29.1 Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on pins with respect to VSS on VDD pin PIC18LF2X/45K50.................................................................................................... -0.3V to +4.5V PIC18F2X/45K50...................................................................................................... -0.3V to +6.5V on VUSB3V3 pin(3)......................................................................................................................-0.3V to +4.0V on D+ and D- pins 0 source impedance(5)..........................................................................-0.5V to (VUSB3V3 + 0.5V) source impedance 28, VUSB3V3 3.0V ...............................................................-1.0V to + 4.6V) on MCLR/nICRST pin(2)..............................................................................................................0V to +11.0V on all other pins.............................................................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)..........................................................................................................................................1.0W Maximum current out of VSS pin -40°C to +125°C.................................................................................................................. 125mA into VDD pin -40°C to +125°C.................................................................................................................... 85mA Input clamp current, IIK (VI < 0 or VI > VDD)(4)20mA Output clamp current, IOK (VO < 0 or VO > VDD)(4)20mA Maximum output current sunk by any I/O pin...............................................................................................................................25mA sourced by any I/O pin..........................................................................................................................25mA Maximum current sunk byall ports (-40°C to +125°C)................................................................................................... 110mA sourced by all ports (-40°C to +125°C).................................................................................................70mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP/ RE3 pin, rather than pulling this pin directly to VSS. 3: VUSB3V3 must always be VDD + 0.3V. VUSB3V3 must also be maintained VDD – 0.3V on PIC18LF2X/ 45K50 devices. 4: Stress rating only. For proper functional operation, I/O pins should be maintained within the -0.3V to (VDD+0.3V) range, which will not result in injected current. See TB3013 technical brief (DS93013) for details. 5: The original Universal Serial Bus Specification Revision 2.0 indicated that USB devices should withstand 24-hour short circuits of D+ or D- to VBUS voltages. This requirement was later removed in an Engineering Change Notice (ECN) supplement to the USB specifications, which supersedes the original specifications. PIC18F2X/45K50 family devices will typically be able to survive this short-circuit test, but it is recommended to adhere to the absolute maximum specified here to avoid damaging the device. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DS30000684B-page 444  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 29.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: VDDMIN VDD VDDMAX Operating Temperature: TA_MIN TA TA_MAX VDD — Operating Supply Voltage PIC18LF2X/45K50 VDDMIN (Fosc  4 MHz, Industrial Temperature)...................................................................... +1.8V VDDMIN (Fosc  48 MHz)......................................................................................................... +2.7V VDDMAX.................................................................................................................................... +3.6V PIC18F2X/45K50 VDDMIN (Fosc  20 MHz, Industrial Temperature).................................................................... +2.3V VDDMIN (Fosc  16 MHz, Extended Temperature)................................................................... +2.3V VDDMIN (Fosc  48 MHz)......................................................................................................... +2.7V VDDMAX.................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN...................................................................................................................................... -40°C TA_MAX.................................................................................................................................... +85°C Extended Temperature TA_MIN...................................................................................................................................... -40°C TA_MAX.................................................................................................................................. +125°C  2012-2014 Microchip Technology Inc. DS30000684B-page 445

PIC18(L)F2X/45K50 FIGURE 29-1: PIC18LF2X/45K50 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL AND EXTENDED TEMPERATURE) 5.5V 5.0V e 4.0V g a olt 3.6V V 3.0V 2.7V 2.3V 1.8V 4 16 20 48 Frequency (MHz) Note1: Maximum Frequency 4 MHz, 1.8V to 2.7V, -40°C to +85°C 2: Maximum Frequency 48 MHz, 2.7V to 3.6V, -40°C to +85°C FIGURE 29-2: PIC18F2X/45K50 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL TEMPERATURE) 5.5V 5.0V e 4.0V g a olt 3.6V V 3.0V 2.7V 2.3V 1.8V 20 30 40 48 Frequency (MHz) Note1: Maximum Frequency 20 MHz, 2.3V to 2.7V, -40°C to +85°C 2: Maximum Frequency 48 MHz, 2.7V to 5.5V, -40°C to +85°C DS30000684B-page 446  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 29-3: PIC18F2X/45K50 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE) 5.5V 5.0V e 4.0V g a olt 3.6V V 3.0V 2.7V 2.3V 1.8V 10 16 20 30 40 48 60 64 Frequency (MHz) Note1: Maximum Frequency 16 MHz, 2.3V to 2.7V, +85°C to +125°C 2: Maximum Frequency 48 MHz, 2.7V to 5.5V, +85°C to +125°C  2012-2014 Microchip Technology Inc. DS30000684B-page 447

PIC18(L)F2X/45K50 29.3 DC Characteristics TABLE 29-1: SUPPLY VOLTAGE, PIC18(L)F2X/45K50 Standard Operating Conditions (unless otherwise PIC18(L)F2X/45K50 stated) Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. D001 VDD Supply Voltage PIC18LF2X/45K50 1.8 — 3.6 V Regulator disabled PIC18F2X/45K50 2.3 — 5.5 V Regulator enabled D001B VUSB3V3 USB Supply Voltage 3.0 3.3 3.6 V USB module enabled VUSB3V3 Capacitor Charging (PIC18F2X/45K50) D001C Charging current — 200 — mA Note 4, 5 D001D Source/sink capability when charging is — 0.0 — mA Note 4 complete D002 VDR RAM Data Retention Voltage(1) 1.5 — — V D003 VPOR VDD Start Voltage to ensure internal — — 0.7 V See section on Power-on Power-on Reset signal Reset for details D004 SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See section on Power-on Power-on Reset signal Reset for details D005 VBOR Brown-out Reset Voltage BORV<1:0> = 11(2) 1.75 1.9 2.05 V BORV<1:0> = 10 2.05 2.2 2.35 V BORV<1:0> = 01 2.35 2.5 2.65 V BORV<1:0> = 00(3) 2.65 2.85 3.05 V D006 VLPBOR Low-Power Brown-out Reset (LPBOR) 1.8V — 2.1 V Voltage Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: On LF devices with BOR enabled, operation is supported until a BOR occurs. This is valid although VDD may be below the minimum rated supply voltage. 3: With BOR enabled, full-speed operation (FOSC = 48 MHz) is supported until a BOR occurs. This is valid although VDD may be below the minimum voltage for this frequency. 4: This is the inrush current associated with initial charging of the VUSB3V3 capacitor during a fast VDD ramp. The microcontroller can still start-up from VDD power sources that are limited to significantly less than this value. 5: The VUSB3V3 regulator is only designed to supply the current requirements of the microcontroller and USB transceiver. It is not intended to supply external loads. DS30000684B-page 448  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-2: POWER-DOWN CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Conditions Param. Typ. Typ. Max. Max. Device Characteristics Units No. +25°C +60°C +85°C +125°C VDD Notes Power-down Base Current (IPD)(1) D006 Sleep mode 0.01 0.04 2 10 A 1.8V WDT, BOR, FVR and SOSC disabled, all Peripherals 0.01 0.06 2 40 A 3.0V inactive 12 13 25 35 A 2.3V 13 14 30 40 A 3.0V 13 14 35 50 A 5.0V Power-down Module Differential Current (delta IPD) D007 Watchdog Timer 0.3 0.3 2.5 2.5 A 1.8V 0.5 0.5 2.5 5 A 3.0V 0.35 0.35 5.0 5.0 A 2.3V 0.5 0.5 5.0 5.0 A 3.0V 0.5 0.5 5.0 5.0 A 5.0V D008 Brown-out Reset(2) 8 8.5 15 16 A 2.0V 9 9.5 15 16 A 3.0V 3.4 3.4 15 16 A 2.3V 3.8 3.8 15 16 A 3.0V 5.2 5.2 15 16 A 5.0V D010 High/Low Voltage Detect(2) 6.5 6.7 15 15 A 2.0V 7 7.5 15 15 A 3.0V 2.1 2.1 15 15 A 2.3V 2.4 2.4 15 15 A 3.0V 3.2 3.2 15 15 A 5.0V D011 Secondary Oscillator 0.5 1 3 10 A 1.8V 0.6 1.1 4 10 A 3.0V 0.5 1 3 10 A 2.3V 32 kHz on SOSC 0.6 1.1 4 10 A 3.0V 0.6 1.1 5 10 A 5.0V Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: On LF devices, the BOR, HLVD and FVR enable internal band gap reference. With more than one of these modules enabled, the current consumption will be less than the sum of the specifications. On F devices, the internal band gap reference is always enabled and its current consumption is included in the Power-down Base Current (IPD). 3: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the FRC turn off as soon as conversion (if any) is complete.  2012-2014 Microchip Technology Inc. DS30000684B-page 449

PIC18(L)F2X/45K50 TABLE 29-2: POWER-DOWN CURRENT, PIC18(L)F2X/45K50 (CONTINUED) PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Conditions Param. Typ. Typ. Max. Max. Device Characteristics Units No. +25°C +60°C +85°C +125°C VDD Notes D015 Comparators 7 7 18 18 A 1.8V 7 7 18 18 A 3.0V 7 7 18 18 A 2.3V LP mode 7 7 18 18 A 3.0V 8 8 20 20 A 5.0V D16 Comparators 38 38 95 95 A 1.8V 40 40 105 105 A 3.0V 39 39 95 95 A 2.3V HP mode 40 40 105 105 A 3.0V 40 40 105 105 A 5.0V D017 DAC 12 12 22 25 A 1.8V 20 20 35 35 A 3.0V 15 15 30 30 A 2.3V 20 20 35 35 A 3.0V 32 32 60 60 A 5.0V D018 FVR(2) 15 16 25 25 A 1.8V 15 16 25 25 A 3.0V 28 28 45 45 A 2.3V 31 31 55 55 A 3.0V 66 66 100 100 A 5.0V D013 A/D Converter(3) 185 185 370 370 A 1.8V 210 210 400 400 A 3.0V 200 200 380 380 A 2.3V A/D on, not converting 210 210 400 400 A 3.0V 250 250 450 450 A 5.0V Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: On LF devices, the BOR, HLVD and FVR enable internal band gap reference. With more than one of these modules enabled, the current consumption will be less than the sum of the specifications. On F devices, the internal band gap reference is always enabled and its current consumption is included in the Power-down Base Current (IPD). 3: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the FRC turn off as soon as conversion (if any) is complete. DS30000684B-page 450  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-3: RC RUN SUPPLY CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D020 Supply Current (IDD)(1),(2) 3.6 23 A -40°C VDD = 1.8V FOSC = 31kHz (RC_RUN mode, 3.9 25 A +25°C INTRC source) 3.9 — A +60°C 3.9 28 A +85°C 4.0 30 A +125°C D021 8.1 26 A -40°C VDD = 3.0V 8.4 30 A +25°C 8.6 — A +60°C 8.7 35 A +85°C 10.7 40 A +125°C D022 16 35 A -40°C VDD = 2.3V FOSC = 31kHz (RC_RUN mode, 17 35 A +25°C INTRC source) 18 35 A +85°C 19 50 A +125°C D023 18 50 A -40°C VDD = 3.0V 20 50 A +25°C 21 50 A +85°C 22 60 A +125°C D024 19 55 A -40°C VDD = 5.0V 21 55 A +25°C 22 55 A +85°C 23 70 A +125°C Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2012-2014 Microchip Technology Inc. DS30000684B-page 451

PIC18(L)F2X/45K50 TABLE 29-3: RC RUN SUPPLY CURRENT, PIC18(L)F2X/45K50 (CONTINUED) PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D030 0.35 0.50 mA -40°C to +125°C VDD = 1.8V FOSC = 1MHz (RC_RUN mode, D031 0.45 0.65 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D032 0.40 0.60 mA -40°C to +125°C VDD = 2.3V FOSC = 1MHz (RC_RUN mode, D033 0.50 0.65 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D034 0.55 0.75 mA -40°C to +125°C VDD = 5.0V D035 1.3 2.0 mA -40°C to +125°C VDD = 1.8V FOSC = 16MHz (RC_RUN mode, D036 2.2 3.0 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D037 1.7 2.0 mA -40°C to +125°C VDD = 2.3V FOSC = 16MHz (RC_RUN mode, D038 2.2 3.0 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D039 2.5 3.5 mA -40°C to +125°C VDD = 5.0V D041 6.2 8.5 mA -40°C to +125°C VDD = 3.0V FOSC = 48MHz (RC_RUN mode, HFINTOSC + PLL source) D043 6.2 8.5 mA -40°C to +125°C VDD = 3.0V FOSC = 48MHz (RC_RUN mode, D044 6.8 9.5 mA -40°C to +125°C VDD = 5.0V HFINTOSC + PLL source) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS30000684B-page 452  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-4: RC IDLE SUPPLY CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D045 Supply Current (IDD)(1),(2) 0.5 18 A -40°C VDD = 1.8V FOSC = 31kHz (RC_IDLE mode, 0.6 18 A +25°C INTRC source) 0.7 — A +60°C 0.75 20 A +85°C 2.3 22 A +125°C D046 1.1 20 A -40°C VDD = 3.0V 1.2 20 A +25°C 1.3 — A +60°C 1.4 22 A +85°C 3.2 25 A +125°C D047 17 30 A -40°C VDD = 2.3V FOSC = 31kHz (RC_IDLE mode, 13 30 A +25°C INTRC source) 14 30 A +85°C 15 45 A +125°C D048 19 35 A -40°C VDD = 3.0V 15 35 A +25°C 16 35 A +85°C 17 50 A +125°C D049 21 40 A -40°C VDD = 5.0V 15 40 A +25°C 16 40 A +85°C 18 60 A +125°C Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2012-2014 Microchip Technology Inc. DS30000684B-page 453

PIC18(L)F2X/45K50 TABLE 29-4: RC IDLE SUPPLY CURRENT, PIC18(L)F2X/45K50 (CONTINUED) PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D055 0.25 0.40 mA -40°C to +125°C VDD = 1.8V FOSC = 1MHz (RC_IDLE mode, D056 0.35 0.50 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D057 0.30 0.45 mA -40°C to +125°C VDD = 2.3V FOSC = 1MHz (RC_IDLE mode, D058 0.40 0.50 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D059 0.45 0.60 mA -40°C to +125°C VDD = 5.0V D060 0.50 0.7 mA -40°C to +125°C VDD = 1.8V FOSC = 16MHz (RC_IDLE mode, D061 0.80 1.1 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D062 0.65 1.0 mA -40°C to +125°C VDD = 2.3V FOSC = 16MHz (RC_IDLE mode, D063 0.80 1.1 mA -40°C to +125°C VDD = 3.0V HFINTOSC source) D064 0.95 1.2 mA -40°C to +125°C VDD = 5.0V D066 2.5 3.5 mA -40°C to +125°C VDD = 3.0V FOSC = 48MHz (RC_IDLE mode, HFINTOSC + PLL source) D068 2.5 3.5 mA -40°C to +125°C VDD = 3.0V FOSC = 48MHz (RC_IDLE mode, D069 3.0 4.5 mA -40°C to +125°C VDD = 5.0V HFINTOSC + PLL source) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS30000684B-page 454  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-5: PRIMARY RUN SUPPLY CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D070 Supply Current (IDD)(1),(2) 0.11 0.20 mA -40°C to +125°C VDD = 1.8V FOSC = 1MHz (PRI_RUN mode, D071 0.17 0.25 mA -40°C to +125°C VDD = 3.0V ECM source) D072 0.15 0.25 mA -40°C to +125°C VDD = 2.3V FOSC = 1MHz (PRI_RUN mode, D073 0.20 0.30 mA -40°C to +125°C VDD = 3.0V ECM source) D074 0.25 0.35 mA -40°C to +125°C VDD = 5.0V D075 1.45 2.0 mA -40°C to +125°C VDD = 1.8V FOSC = 20MHz (PRI_RUN mode, D076 2.60 3.5 mA -40°C to +125°C VDD = 3.0V ECH source) D077 1.95 2.5 mA -40°C to +125°C VDD = 2.3V FOSC = 20MHz (PRI_RUN mode, D078 2.65 3.5 mA -40°C to +125°C VDD = 3.0V ECH source) D079 2.95 4.5 mA -40°C to +125°C VDD = 5.0V D080 7.5 10 mA -40°C to +125°C VDD = 3.0V FOSC = 48MHz (PRI_RUN, ECH oscillator) D081 7.5 10 mA -40°C to +125°C VDD = 3.0V FOSC = 48MHz (PRI_RUN mode, D082 8.5 11.5 mA -40°C to +125°C VDD = 5.0V ECH source) D083 1.0 1.5 mA -40°C to +125°C VDD = 1.8V FOSC = 4MHz 16MHz Internal D084 1.8 3.0 mA -40°C to +125°C VDD = 3.0V (PRI_RUN mode, ECM + PLL source) D085 1.4 2.0 mA -40°C to +125°C VDD = 2.3V FOSC = 4MHz 16MHz Internal D086 1.85 2.5 mA -40°C to +125°C VDD = 3.0V (PRI_RUN mode, D087 2.1 3.0 mA -40°C to +125°C VDD = 5.0V ECM + PLL source) D088 6.35 9.0 mA -40°C to +125°C VDD = 3.0V FOSC = 16MHz 48MHz Internal (PRI_RUN mode, ECH + PLL source) D089 6.35 9.0 mA -40°C to +125°C VDD = 3.0V FOSC = 16MHz 48MHz Internal D090 7.0 10 mA -40°C to +125°C VDD = 5.0V (PRI_RUN mode, ECH + PLL source) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2012-2014 Microchip Technology Inc. DS30000684B-page 455

PIC18(L)F2X/45K50 TABLE 29-6: PRIMARY IDLE SUPPLY CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D100 Supply Current (IDD)(1),(2) 0.030 0.050 mA -40°C to +125°C VDD = 1.8V Fosc = 1MHz (PRI_IDLE mode, D101 0.045 0.065 mA -40°C to +125°C VDD = 3.0V ECM source) D102 0.06 0.12 mA -40°C to +125°C VDD = 2.3V Fosc = 1MHz (PRI_IDLE mode, D103 0.08 0.15 mA -40°C to +125°C VDD = 3.0V ECM source) D104 0.13 0.20 mA -40°C to +125°C VDD = 5.0V D105 0.45 0.8 mA -40°C to +125°C VDD = 1.8V Fosc = 20MHz (PRI_IDLE mode, D106 0.70 1.0 mA -40°C to +125°C VDD = 3.0V ECH source) D107 0.55 0.8 mA -40°C to +125°C VDD = 2.3V Fosc = 20MHz (PRI_IDLE mode, D108 0.75 1.0 mA -40°C to +125°C VDD = 3.0V ECH source) D109 0.90 1.2 mA -40°C to +125°C VDD = 5.0V D110 2.25 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 48MHz (PRI_IDLE mode, ECH source) D111 2.25 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 48MHz (PRI_IDLE mode, D112 2.60 3.5 mA -40°C to +125°C VDD = 5.0V ECH source) D113 0.35 0.6 mA -40°C to +125°C VDD = 1.8V Fosc = 4MHz 16MHz Internal D114 0.55 0.8 mA -40°C to +125°C VDD = 3.0V (PRI_IDLE mode, ECM + PLL source) D115 0.45 0.6 mA -40°C to +125°C VDD = 2.3V Fosc = 4MHz 16MHz Internal D116 0.60 0.9 mA -40°C to +125°C VDD = 3.0V (PRI_IDLE mode, D117 0.70 1.0 mA -40°C to +125°C VDD = 5.0V ECM + PLL source) D118 2.2 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 16MHz 48MHz Internal (PRI_IDLE mode, ECH + PLL source) D119 2.2 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 16MHz 48MHz Internal D120 2.5 3.5 mA -40°C to +125°C VDD = 5.0V (PRI_IDLE mode, ECH + PLL source) Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS30000684B-page 456  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-7: SECONDARY OSCILLATOR SUPPLY CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D130 Supply Current (IDD)(1),(2) 3.5 23 A -40°C VDD = 1.8V Fosc = 32kHz (SEC_RUN mode, 3.7 25 A +25°C SOSC source) 3.8 — A +60°C 4.0 28 A +85°C 5.1 30 A +125°C D131 6.2 26 A -40°C VDD = 3.0V 6.4 30 A +25°C 6.5 — A +60°C 6.8 35 A +85°C 7.8 40 A +125°C D132 15 35 A -40°C VDD = 2.3V Fosc = 32kHz (SEC_RUN mode, 16 35 A +25°C SOSC source) 17 35 A +85°C 19 50 A +125°C D133 18 50 A -40°C VDD = 3.0V 19 50 A +25°C 21 50 A +85°C 22 60 A +125°C D134 19 55 A -40°C VDD = 5.0V 20 55 A +25°C 22 55 A +85°C 23 70 A +125°C Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; SOSCI / SOSCO = complementary external square wave, from rail-to-rail.  2012-2014 Microchip Technology Inc. DS30000684B-page 457

PIC18(L)F2X/45K50 TABLE 29-7: SECONDARY OSCILLATOR SUPPLY CURRENT, PIC18(L)F2X/45K50 (CONTINUED) PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics Typ. Max. Units Conditions No. D135 0.9 18 A -40°C VDD = 1.8V Fosc = 32kHz (SEC_IDLE mode, 1.0 18 A +25°C SOSC source) 1.1 — A +60°C 1.3 20 A +85°C 2.3 22 A +125°C D136 1.3 20 A -40°C VDD = 3.0V 1.4 20 A +25°C 1.5 — A +60°C 1.8 22 A +85°C 2.9 25 A +125°C D137 12 30 A -40°C VDD = 2.3V Fosc = 32kHz (SEC_IDLE mode, 13 30 A +25°C SOSC source) 14 30 A +85°C 16 45 A +125°C D138 13 35 A -40°C VDD = 3.0V 14 35 A +25°C 16 35 A +85°C 18 50 A +125°C D139 14 40 A -40°C VDD = 5.0V 15 40 A +25°C 16 40 A +85°C 18 60 A +125°C Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. 2: The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; SOSCI / SOSCO = complementary external square wave, from rail-to-rail. DS30000684B-page 458  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-8: INPUT/OUTPUT CHARACTERISTICS, PIC18(L)F2X/45K50 DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Typ.† Max. Units Conditions No. VIL Input Low Voltage I/O PORT: D140 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V D140A — — 0.15VDD V 1.8V  VDD  4.5V D141 with Schmitt Trigger buffer — — 0.2VDD V 2.0V  VDD  5.5V with I2C™ levels — — 0.3VDD V with SMBus levels — — 0.8 V 2.7V  VDD  5.5V D142 MCLR, OSC1 (RC mode)(1) — — 0.2VDD V D142A OSC1 (HS mode) — — 0.3VDD V VIH Input High Voltage I/O ports: D147 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V D147A 0.25VDD + 0.8 — — V 1.8V  VDD  4.5V D148 with Schmitt Trigger buffer 0.8VDD — — V 2.0V  VDD  5.5V with I2C levels 0.7VDD — — V with SMBus levels 2.1 — — V 2.7V  VDD  5.5V D149 MCLR 0.8VDD — — V D150A OSC1 (HS mode) 0.7VDD — — V D150B OSC1 (RC mode)(1) 0.9VDD — — V IIL Input Leakage I/O and VSS VPIN VDD, MCLR(2),(3) Pin at high-impedance D155 I/O ports and MCLR — 0.1 50 nA +25°C(4) — 0.7 100 nA +60°C — 4 200 nA +85°C IPU Weak Pull-up Current(4) D158 IPURB PORTB weak pull-up current 25 85 200 A VDD = 3.3V, VPIN = VSS 25 130 300 A VDD = 5.0V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested.  2012-2014 Microchip Technology Inc. DS30000684B-page 459

PIC18(L)F2X/45K50 TABLE 29-8: INPUT/OUTPUT CHARACTERISTICS, PIC18(L)F2X/45K50 (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Typ.† Max. Units Conditions No. VOL Output Low Voltage D159 I/O ports — — 0.6 V IOL = 8 mA, VDD = 5V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V IPUMCLR MCLR and ICRST weak 25 85 200 A VDD = 3.3V, VPIN = VSS pull-up current D160 25 130 300 A VDD = 5.0V, VPIN = VSS VOH Output High Voltage(3) D161 I/O ports VDD - 0.7 — — V IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. DS30000684B-page 460  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-9: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Min. Typ.† Max. Units Conditions No. Internal Program Memory Programming Specifications(1) D170 VPP Voltage on MCLR/VPP pin 8 — 9 V (Note 3), (Note 4) D171 IDDP Supply Current during — — 10 mA Programming Data EEPROM Memory D172 ED Byte Endurance 100K — — E/W -40C to +85C D173 VDRW VDD for Read/Write VDDMIN — VDDMAX V Using EECON to read/ write D175 TDEW Erase/Write Cycle Time — 3 4 ms D176 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D177 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +85°C Cycles before Refresh(2) Program Flash Memory D178 EP Cell Endurance 10K — — E/W -40C to +85C (Note 5) D179 VPR VDD for Read VDDMIN — VDDMAX V D181 VIW VDD for Row Erase or Write 2.2 — VDDMAX V PIC18LF2X/45K50 D182 VIW VDDMIN — VDDMAX V PIC18F2X/45K50 D183 TIW Self-timed Write Cycle Time — 2 — ms D184 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section8.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2. 5: Self-write and Block Erase.  2012-2014 Microchip Technology Inc. DS30000684B-page 461

PIC18(L)F2X/45K50 TABLE 29-10: USB MODULE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Min. Typ. Max. Units Conditions No. D313 VUSB USB Voltage 3.0 — 3.6 V Voltage on VUSB3V3 pin must be in this range for proper USB operation D314 IIL Input Leakage on pin — — ± 1 A VSS VPIN VDD pin athighimpedance D315 VILUSB Input Low Voltage for USB — — 0.8 V For VUSB3V3 range Buffer D316 VIHUSB Input High Voltage for USB 2.0 — — V For VUSB3V3 range Buffer D318 VDIFS Differential Input Sensitivity — — 0.2 V The difference between D+ and D- must exceed this value while VCM is met D319 VCM Differential Common Mode 0.8 — 2.5 V Range D320 ZOUT Driver Output Impedance(1) 28 — 44  D321 VOL Voltage Output Low 0.0 — 0.3 V 1.5 kload connected to 3.6V D322 VOH Voltage Output High 2.8 — 3.6 V 1.5 kload connected to ground D323 CUSB VUSB Capacitor Value 0.33 0.47 8 µF Note1: The D+ and D- signal lines have been built-in impedance matching resistors. No external resistors, capacitors or magnetic components are necessary on the D+/D- signal paths between the PIC18(L)F2X/ 45K50 family device and USB cable. DS30000684B-page 462  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 29.4 Analog Characteristics TABLE 29-11: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristics Min. Typ. Max. Units Comments No. CM01 VIOFF Input Offset Voltage — 3 30 mV High-Power mode VREF = VDD/2 — 4 40 mV Low-Power mode VREF = VDD/2 CM02 VICM Input Common-mode Voltage VSS — VDD V CM04* TRESP Response Time(1) — 200 400 ns High-Power mode — 600 3500 ns Low-Power mode CM05* TMC2OV Comparator Mode Change to — — 10 s Output Valid * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. TABLE 29-12: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) 2.0V < VDD < 5.5V, -40°C < TA < +125°C Param. Sym. Characteristics Min. Typ. Max. Units Comments No. CV01* CLSB Step Size(2) — VDD/32 — V CV02* CACC Absolute Accuracy — — 1/2 LSb VSRC 2.0V CV03* CR Unit Resistor Value (R) — 5k —  CV04* CST Settling Time(1) — — 10 s CV05* VSRC+ DAC Positive Reference VSRC- + 2 — VDD V CV06* VSRC- DAC Negative Reference VSS — VSRC+ – 2 V CV07* VSRC DAC Reference Range (VSRC+ - VSRC-) 2 — VDD V * These parameters are characterized but not tested. Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. 2: See Section23.0 “Digital-to-Analog Converter (DAC) Module” for more information.  2012-2014 Microchip Technology Inc. DS30000684B-page 463

PIC18(L)F2X/45K50 TABLE 29-13: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristics Min. Typ. Max. Units Comments No. VR01 VROUT VR voltage output to ADC 0.973 1.024 1.085 V 1x output, VDD 2.5V 1.946 2.048 2.171 V 2x output, VDD 2.5V 3.891 4.096 4.342 V 4x output, VDD 4.75V (PIC18F2X/45K50) VR02 VROUT VR voltage output all other 0.942 1.024 1.096 V 1x output, VDD 2.5V modules 1.884 2.048 2.191 V 2x output, VDD 2.5V 3.768 4.096 4.383 V 4x output, VDD 4.75V (PIC18F2X/45K50) VR04* TSTABLE Settling Time — 25 100 s 0 to 85°C * These parameters are characterized but not tested. TABLE 29-14: CHARGE TIME MEASUREMENT UNIT (CTMU) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristics Min. Typ.(1) Max. Units Comments No. CT01 IOUT1 CTMU Current Source, — 0.55 — A IRNG<1:0> = 01 Base Range CT02 IOUT2 CTMU Current Source, — 5.5 — A IRNG<1:0> = 10 10X Range CT03 IOUT3 CTMU Current Source, — 55 — A IRNG<1:0> = 11 100X Range VDD  3.0V Note 1: Nominal value at center point of current trim range (CTMUICON<7:2> = 000000). FIGURE 29-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be cleared by software) VHLVD (HLVDIF set by hardware) HLVDIF DS30000684B-page 464  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-15: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic HLVDL<3:0> Min. Typ.† Max. Units Conditions No. D420 — HLVD Voltage on VDD 0000 1.69 1.84 1.99 V Transition High-to-Low 0001 1.92 2.07 2.22 V 0010 2.08 2.28 2.48 V 0011 2.24 2.44 2.64 V 0100 2.34 2.54 2.74 V 0101 2.54 2.74 2.94 V 0110 2.62 2.87 3.12 V 0111 2.76 3.01 3.26 V 1000 3.00 3.30 3.60 V 1001 3.18 3.48 3.78 V 1010 3.44 3.69 3.94 V 1011 3.66 3.91 4.16 V 1100 3.90 4.15 4.40 V 1101 4.11 4.41 4.71 V 1110 4.39 4.74 5.09 V 1111 V(HLVDIN pin) v † Production tested at TAMB = +25°C. Specifications over temperature limits ensured by characterization.  2012-2014 Microchip Technology Inc. DS30000684B-page 465

PIC18(L)F2X/45K50 29.5 AC (Timing) Characteristics 29.5.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C™ specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS30000684B-page 466  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 29.5.2 TIMING CONDITIONS The temperature and voltages specified in Table29-16 apply to all timing specifications unless otherwise noted. Figure29-5 specifies the Load conditions for the timing specifications. TABLE 29-16: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) AC CHARACTERISTICS Operating voltage VDD range as described in Table29-1 and Table29-9. FIGURE 29-5: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Legend: Pin RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports  2012-2014 Microchip Technology Inc. DS30000684B-page 467

PIC18(L)F2X/45K50 29.5.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 29-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 29-17: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 1A FOSC External CLKIN DC 4 MHz EC, ECIO Oscillator mode (low power) Frequency(1) DC 16 MHz EC, ECIO Oscillator mode (medium power) DC 48 MHz EC, ECIO Oscillator mode (high power) Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 5 200 kHz LP Oscillator mode 0.1 4 MHz XT Oscillator mode 4 4 MHz HS Oscillator mode, VDD < 2.7V 4 16 MHz HS Oscillator mode, VDD 2.7V, Medium-Power mode (HSMP) 4 20 MHz HS Oscillator mode, VDD 2.7V, High-Power mode (HSHP) 1 TOSC External CLKIN Period(1) 0.25 — s EC, ECIO Oscillator mode (low power) 62.5 — ns EC, ECIO Oscillator mode (medium power) 20.8 — ns EC, ECIO Oscillator mode (high power) Oscillator Period(1) 250 — ns RC Oscillator mode 5 200 s LP Oscillator mode 0.25 10 s XT Oscillator mode 250 250 ns HS Oscillator mode, VDD < 2.7V 62.5 250 ns HS Oscillator mode, VDD 2.7V, Medium-Power mode (HSMP) 50 250 ns HS Oscillator mode, VDD 2.7V, High-Power mode (HSHP) 2 TCY Instruction Cycle Time(1) 83.3 — ns TCY = 4/FOSC 3 TOSL, External Clock in (OSC1) 2.5 — s LP Oscillator mode TOSH High or Low Time 30 — ns XT Oscillator mode 10 — ns HS Oscillator mode 4 TOSR, External Clock in (OSC1) — 50 ns LP Oscillator mode TOSF Rise or Fall Time — 20 ns XT Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating condi- tions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS30000684B-page 468  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-18: PLL CLOCK TIMING SPECIFICATIONS Param. Sym. Characteristic Min. Max. Units Conditions No. F10 FOSC 4xPLL Oscillator Frequency Range 4 5 MHz VDD < 2.7V, -40°C to +85°C 4 12 MHz 2.7V  VDD, -40°C to +85°C F10B FOSC 3xPLL Oscillator Frequency Range 4 4 MHz 2.7V  VDD, -40°C to +85°C F11 FSYS On-Chip VCO System Frequency 16 20 MHz VDD < 2.7V, -40°C to +85°C 16 48 MHz 2.7V  VDD, -40°C to +85°C F12 t PLL Start-up Time (Lock Time) — 2 ms rc TABLE 29-19: INTERNAL OSCILLATORS ACCURACY (PIC18(L)F2X/45K50) Standard Operating Conditions (unless otherwise stated) Param. Characteristic Min. Typ. Max. Units Conditions No. OA1 HF-INTOSC Accuracy(1) -2 ±1 +2 % +0°C to +70°C -3 — +2 % +70°C to +85°C -5 — +5 % -40°C to +125°C OA1B HF-INTOSC Accuracy with Active Clock Tuning (ACT) -0.20 ±0.05 +0.20 % -40°C to +85°C(2), Active Clock Tune is enabled and locked. OA1C OSCTUNE Step Size — 0.1 — % OA2 INTRC Accuracy @ Freq = 31.25 kHz 26.5625 — 35.9375 kHz -40°C to +85°C 25 — 37.2 kHz +85°C to +125°C Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift. 2: Accuracy measured with respect to reference source.  2012-2014 Microchip Technology Inc. DS30000684B-page 469

PIC18(L)F2X/45K50 FIGURE 29-7: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure29-5 for Load conditions. TABLE 29-20: CLKO AND I/O TIMING REQUIREMENTS Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. 10 TOSH2CKL OSC1  to CLKO  — 75 200 ns Note 1 11 TOSH2CKH OSC1  to CLKO  — 75 200 ns Note 1 12 TCKR CLKO Rise Time — 35 100 ns Note 1 13 TCKF CLKO Fall Time — 35 100 ns Note 1 14 TCKL2IOV CLKO  to Port Out Valid — — 0.5 TCY + 20 ns Note 1 15 TIOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns Note 1 16 TCKH2IOI Port In Hold after CLKO  0 — — ns Note 1 17 TOSH2IOV OSC1  (Q1 cycle) to Port Out — 50 150 ns Valid 18 TOSH2IOI OSC1  (Q2 cycle) to Port Input 100 — — ns Invalid (I/O in hold time) 19 TIOV2OSH Port Input Valid to OSC1 (I/O in 0 — — ns setup time) 20 TIOR Port Output Rise Time — 40 72 ns VDD = 1.8V — 15 32 ns VDD = 3.3V – 5.0V 21 TIOF Port Output Fall Time — 28 55 ns VDD = 1.8V — 15 30 ns VDD = 3.3V – 5.0V 22† TINP INTx pin High or Low Time 20 — — ns 23† TRBP RB<7:4> Change KBIx High or TCY — — ns Low Time † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. DS30000684B-page 470  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 29-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure29-5 for Load conditions. FIGURE 29-9: BROWN-OUT RESET TIMING VDD BVDD 35 VBGAP = 1.2V VIVRST Enable Internal Reference Voltage Internal Reference Voltage Stable 36  2012-2014 Microchip Technology Inc. DS30000684B-page 471

PIC18(L)F2X/45K50 TABLE 29-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDT Watchdog Timer Time-out Period 3.5 4.1 4.7 ms 1:1 prescaler (no postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 54.8 64.4 74.1 ms 34 TIOZ I/O High-Impedance from MCLR — 2 — s Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200(1) — — s VDD  BVDD (see D005) 36 TIVRST Internal Reference Voltage Stable — 25 35 s 37 THLVD High/Low-Voltage Detect Pulse 200(1) — — s VDD  VHLVD Width 38 TCSD CPU Start-up Time 5 — 10 s 39 TIOBST Time for HF-INTOSC to Stabilize — 0.25 1 ms Note 1: Minimum pulse width that will consistently trigger a Reset or interrupt. Shorter pulses may intermittently trigger a response. FIGURE 29-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI/T3CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure29-5 for Load conditions. DS30000684B-page 472  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-22: TIMER0 AND TIMER1/3 EXTERNAL CLOCK REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale value 20ns or (1, 2, 4,..., 256) (TCY + 40)/N 45 TT1H TxCKI High Synchronous, no prescaler 0.5 TCY + 20 — ns Time Synchronous, 10 — ns with prescaler Asynchronous 30 — ns 46 TT1L TxCKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns Time Synchronous, 10 — ns with prescaler Asynchronous 30 — ns 47 TT1P TxCKI Synchronous Greater of: — ns N = prescale value Input 20ns or (1, 2, 4, 8) Period (TCY + 40)/N Asynchronous 60 — ns FT1 TxCKI Clock Input Frequency Range DC 50 kHz 48 TCKE2TMRL Delay from External TxCKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment FIGURE 29-11: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure29-5 for Load conditions.  2012-2014 Microchip Technology Inc. DS30000684B-page 473

PIC18(L)F2X/45K50 TABLE 29-23: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param. Symbol Characteristic Min. Max. Units Conditions No. 50 TCCL CCPx Input Low Time No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 51 TCCH CCPx Input High Time No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale value N (1, 4 or 16) 53 TCCR CCPx Output Fall Time — 25 ns 54 TCCF CCPx Output Fall Time — 25 ns FIGURE 29-12: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure29-5 for Load conditions. DS30000684B-page 474  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-24: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0 OR 1) Param. Symbol Characteristic Min. Max. Units Conditions No. 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 25 — ns TDIV2SCL 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 25 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time — 30 ns Note 1 76 TDOF SDO Data Output Fall Time — 20 ns Note 1 78 TSCR SCK Output Rise Time (Master mode) — 30 ns Note 1 79 TSCF SCK Output Fall Time (Master mode) — 20 ns Note 1 80 TSCH2DOV, SDO Data Output Valid after SCK Edge — 20 ns TSCL2DOV 81 TDOV2SCH, SDO Data Output Setup to SCK Edge TCY — ns TDOV2SCL Note 1: When the slew rate control limiting I/O port feature is disabled. FIGURE 29-13: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure29-5 for Load conditions.  2012-2014 Microchip Technology Inc. DS30000684B-page 475

PIC18(L)F2X/45K50 FIGURE 29-14: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure29-5 for Load conditions. TABLE 29-25: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0 OR 1) Param. Symbol Characteristic Min. Max. Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input TCY — ns TSSL2SCL 71 TSCH SCK Input High Time Continuous 25 — ns 72 TSCL SCK Input Low Time Continuous 30 — ns 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 25 — ns TDIV2SCL 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 25 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time — 30 ns Note 1 76 TDOF SDO Data Output Fall Time — 20 ns Note 1 77 TSSH2DOZ SS to SDO Output High-Impedance 10 50 ns 80 TSCH2DOV, SDO Data Output Valid after SCK Edge — 60 ns Note 1 TSCL2DOV 82 TSSL2DOV SDO Data Output Valid after SS  Edge — 60 ns Note 1 83 TSCH2SSH, SS  after SCK edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: When the slew rate control limiting I/O port feature is disabled. DS30000684B-page 476  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 FIGURE 29-15: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure29-5 for Load conditions. FIGURE 29-16: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure29-5 for Load conditions.  2012-2014 Microchip Technology Inc. DS30000684B-page 477

PIC18(L)F2X/45K50 TABLE 29-26: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min. Max. Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Start condition Setup Time 400 kHz mode 600 — 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first clock pulse is generated Hold Time 400 kHz mode 600 — 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 29-17: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure29-5 for Load conditions. DS30000684B-page 478  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-27: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min. Max. Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 102 TR SDA and SCL Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup 100 kHz mode 4.7 — s Only relevant for Repeated Time Start condition 400 kHz mode 0.6 — s 91 THD:STA Start Condition Hold 100 kHz mode 4.0 — s After this period, the first Time clock pulse is generated 400 kHz mode 0.6 — s 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup 100 kHz mode 4.7 — s Time 400 kHz mode 0.6 — s 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns Note 1 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before a new transmission 400 kHz mode 1.3 — s can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A fast mode I2C™ bus device can be used in a standard mode I2C bus system but the requirement, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT=1000+250=1250ns (according to the standard mode I2C bus specification), before the SCL line is released.  2012-2014 Microchip Technology Inc. DS30000684B-page 479

PIC18(L)F2X/45K50 FIGURE 29-18: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure29-5 for Load conditions. TABLE 29-28: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Repeated Start Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the first clock pulse is Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. FIGURE 29-19: MASTER SSP I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure29-5 for Load conditions. DS30000684B-page 480  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-29: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be Rise Time from 10 to 400 pF 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be Fall Time from 10 to 400 pF 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time Repeated Start 400 kHz mode 2(TOSC)(BRG + 1) — ms condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time clock pulse is generated 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 107 TSU:DAT Data Input 100 kHz mode 250 — ns Note 2 Setup Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free before a new 400 kHz mode 1.3 — ms transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter 107250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter 102 + parameter 107=1000+250=1250ns (for 100 kHz mode), before the SCL line is released.  2012-2014 Microchip Technology Inc. DS30000684B-page 481

PIC18(L)F2X/45K50 FIGURE 29-20: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TX/CK pin 121 121 RX/DT pin 120 122 Note: Refer to Figure29-5 for Load conditions. TABLE 29-30: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid — 40 ns 121 TCKRF Clock Out Rise Time and Fall Time — 20 ns Note 1 (Master mode) 122 TDTRF Data Out Rise Time and Fall Time — 20 ns Note 1 Note 1: When the slew rate control limiting I/O port feature is disabled. FIGURE 29-21: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TX/CK pin 125 RX/DT pin 126 Note: Refer to Figure29-5 for Load conditions. TABLE 29-31: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Setup before CK  (DT setup time) 10 — ns 126 TCKL2DTL Data Hold after CK  (DT hold time) 15 — ns DS30000684B-page 482  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 TABLE 29-32: A/D CONVERTER CHARACTERISTICS (PIC18(L)F2X/45K50)(1) Standard Operating Conditions (unless otherwise stated) PIC18(L)F2X/45K50 Operating temperature: Tested at +25°C Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. A01 NR Resolution — — 10 bits VREF  3.0V A03 EIL Integral Linearity Error — ±0.5 ±1 LSb VREF = 3.0V A04 EDL Differential Linearity Error — ±0.5 ±1 LSb VREF  3.0V A06 EOFF Offset Error — ±0.7 ±2 LSb VREF  3.0V A07 EGN Gain Error — ±0.7 ±2 LSb VREF  3.0V A08 ETOTL Total Error — ±0.8 ±3 LSb VREF  3.0V A20 VREF Reference Voltage Range 2 — VDD V (VREFH – VREFL) A21 VREFH Reference Voltage High VDD/2 — VDD + 0.3 V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD/2 V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 10 k Analog Voltage Source Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. FIGURE 29-22: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 .. . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.  2012-2014 Microchip Technology Inc. DS30000684B-page 483

PIC18(L)F2X/45K50 TABLE 29-33: A/D CONVERSION REQUIREMENTS (PIC18(L)F2X/45K50) Standard Operating Conditions (unless otherwise stated) Operating temperature: Tested at +25°C Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. 130 TAD A/D Clock Period 1 — 25 s -40C to +85C 131 TCNV Conversion Time 12 — 12 TAD (not including acquisition time)(1) 132 TACQ Acquisition Time(2) 1.4 — — s VDD = 3V, Rs = 50 135 TSWC Switching Time from Convert  Sample — — (Note 3) — 136 TDIS Discharge Time 2 — 2 TAD Note 1: ADRES register may be read on the following TCY cycle. 2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50 . 3: On the following cycle of the device clock. DS30000684B-page 484  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 30.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time.  2012-2014 Microchip Technology Inc. DS30000684B-page 485

PIC18(L)F2X/45K50 31.0 PACKAGING INFORMATION 31.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC18F25K50 -E/SP e3 1407017 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX PIC18F25K50 XXXXXXXXXXXXXXXXXXXX -E/SO e3 XXXXXXXXXXXXXXXXXXXX 1407017 YYWWNNN 28-Lead SSOP (5.30 mm) Example PIC18F25K50 -E/SS e3 1407017 Legend: XX...X Customer-specific information or Microchip part number Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS30000684B-page 486  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 XXXXXXXX 18F25K50 XXXXXXXX -E/ML e3 YYWWNNN 1407017 40-Lead PDIP (600 mil) Example XXXXXXXXXXXXXXXXXX PIC18F45K50 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -E/P e3 YYWWNNN 1401017 40-Lead UQFN (5x5x0.5 mm) Example PIN 1 PIN 1 PIC18F 45K50 -E/MV e3 1407017 Legend: XX...X Customer-specific information or Microchip part number Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2012-2014 Microchip Technology Inc. DS30000684B-page 487

PIC18(L)F2X/45K50 Package Marking Information (Continued) 44-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX 18F45K50 XXXXXXXXXX -E/PT e3 XXXXXXXXXX YYWWNNN 1407017 Legend: XX...X Customer-specific information or Microchip part number Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS30000684B-page 488  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 31.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)(cid:26)(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1  2012-2014 Microchip Technology Inc. DS30000684B-page 489

PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30000684B-page 490  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2014 Microchip Technology Inc. DS30000684B-page 491

PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30000684B-page 492  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)#$(cid:12)(cid:13)(cid:11)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)%(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:10)(cid:24)(cid:9)(cid:25)(cid:9)&’(cid:26)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:10)%(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:30)(cid:4)(cid:20)(cid:3)(cid:4) (cid:30)(cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)-1  2012-2014 Microchip Technology Inc. DS30000684B-page 493

PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30000684B-page 494  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50  2012-2014 Microchip Technology Inc. DS30000684B-page 495

PIC18(L)F2X/45K50 ((cid:27)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9))(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS30000684B-page 496  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2014 Microchip Technology Inc. DS30000684B-page 497

PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30000684B-page 498  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2014 Microchip Technology Inc. DS30000684B-page 499

PIC18(L)F2X/45K50 (((cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)*#(cid:12)(cid:13)(cid:9)+(cid:21)(cid:7)(cid:8)(cid:9),(cid:16)(cid:7)(cid:18)-(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)*(cid:24)(cid:9)(cid:25)(cid:9).(cid:27)/.(cid:27)/.(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)0(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)*+,(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)9(cid:14)(cid:28)#! 7 (cid:23)(cid:23) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)<(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:24)(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ -(cid:20)(cid:29)@ (cid:5)@ : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:5) (cid:4)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:30)(cid:30)@ (cid:30)(cid:3)@ (cid:30)-@ (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:30)(cid:30)@ (cid:30)(cid:3)@ (cid:30)-@ !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ,(cid:11)(cid:28)’%(cid:14)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:8)(cid:10)(cid:9)(cid:15)(cid:14)(cid:9)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:2)(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)V(cid:2)!(cid:7)W(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:30)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)?1 DS30000684B-page 500  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2014 Microchip Technology Inc. DS30000684B-page 501

PIC18(L)F2X/45K50 NOTES: DS30000684B-page 502  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 APPENDIX A: REVISION HISTORY Revision A (08/2012) Initial release. Revision B (07/2014) Updated Figures 2, 4 and 3-1; Updated Section 1.2 (Other Special Features), Section 2.4 (Voltage Regulator Pins (VUSB3V3)) and Section 26.9.1 (Dedicated ICD/ICSP Port); Added note to Section24.4.1.1 (Buffer Ownership), Updated Tables 3-6 and 3-7; Updated Chapter 29.0 (Electrical Specifications), Chapter 31 (Packaging Information) and the Product Identification System page; Other minor corrections.  2012-2014 Microchip Technology Inc. DS30000684B-page 503

PIC18(L)F2X/45K50 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in TableB-1. TABLE B-1: DEVICE DIFFERENCES Features PIC18F24K50 PIC18LF24K50 PIC18F25K50 PIC18LF25K50 PIC18F45K50 PIC18LF45K50 Program Memory (Bytes) 16384 16384 32768 32768 32768 32768 VDD Range 2.3V to 5.5V 1.8V to 3.6V 2.3V to 5.5V 1.8V to 3.6V 2.3V to 5.5V 1.8V to 3.6V I/O Ports Ports A, B, C, Ports A, B, C, (E) Ports A, B, C, Ports A, B, C, (E) Ports A, B, C, Ports A, B, C, D, (E) (E) D, E E 10-Bit Analog-to-Digital 14 input 14 input 14 input 14 input 25 input 25 input Module channels channels channels channels channels channels Packages 28-pin SPDIP 28-pin SPDIP 28-pin SPDIP 28-pin SPDIP 40-pin PDIP 40-pin PDIP 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin SOIC 40-pin UQFN 40-pin UQFN 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 44-pin TQFP 44-pin TQFP 28-pin QFN 28-pin QFN 28-pin QFN 28-pin QFN DS30000684B-page 504  2012-2014 Microchip Technology Inc.

PIC18(L)F2X/45K50 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2012-2014 Microchip Technology Inc. DS30000684B-page 505

PIC18(L)F2X/45K50 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](2) - X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC18F45K50-E/P 301 = Extended temp., Option Range PDIP package, QTP pattern #301. b) PIC18LF25K50-E/SO = Extended temp., SOIC package. c) PIC18F45K50-E/P = Extended temp., PDIP Device: PIC18F45K50, PIC18LF45K50 package. PIC18F25K50, PIC18LF25K50 PIC18F24K50, PIC18LF24K50 d) PIC18F24K50T-E/ML = Tape and reel, Extended temp., QFN package. Tape and Reel Blank = standard packaging (tube or tray) Option: T = Tape and Reel(1), (2) Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Package: ML = QFN Note1: Tape and Reel option is available for ML, MV = UQFN MV, PT, SO and SS packages with industrial P = PDIP Temperature Range only. PT = TQFP (Thin Quad Flatpack) SO = SOIC 2: Tape and Reel identifier only appears in SP = Skinny Plastic DIP catalog part number description. This SS = SSOP identifier is used for ordering purposes and is not printed on the device package. Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) DS30000684B-page 506  2012-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2012-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-360-0 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2012-2014 Microchip Technology Inc. DS30000684B-page 507

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2943-5100 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://www.microchip.com/ support Fax: 852-2401-3431 India - Pune France - Paris Web Address: Australia - Sydney Tel: 91-20-3019-1500 Tel: 33-1-69-53-63-20 Tel: 61-2-9868-6733 Fax: 33-1-69-30-90-79 www.microchip.com Japan - Osaka Atlanta Fax: 61-2-9868-6755 Tel: 81-6-6152-7160 Germany - Dusseldorf Duluth, GA China - Beijing Fax: 81-6-6152-9310 Tel: 49-2129-3766400 TFealx: :6 67788-9-95577-9-1641545 TFealx: :8 866-1-100-8-8556298-7-2010004 JTealp: a8n1 --3 T-6o8k8y0o- 3770 GTeel:r m49a-n8y9 --6 M27u-n1i4c4h-0 China - Chengdu Fax: 49-89-627-144-44 Austin, TX Fax: 81-3-6880-3771 Tel: 512-257-3370 Tel: 86-28-8665-5511 Korea - Daegu Germany - Pforzheim Fax: 86-28-8665-7889 Tel: 49-7231-424750 Boston Tel: 82-53-744-4301 Westborough, MA China - Chongqing Fax: 82-53-744-4302 Italy - Milan Tel: 774-760-0087 Tel: 86-23-8980-9588 Korea - Seoul Tel: 39-0331-742611 Fax: 774-760-0088 Fax: 86-23-8980-9500 Tel: 82-2-554-7200 Fax: 39-0331-466781 Chicago China - Hangzhou Fax: 82-2-558-5932 or Italy - Venice Itasca, IL Tel: 86-571-8792-8115 82-2-558-5934 Tel: 39-049-7625286 Tel: 630-285-0071 Fax: 86-571-8792-8116 Malaysia - Kuala Lumpur Netherlands - Drunen Fax: 630-285-0075 China - Hong Kong SAR Tel: 60-3-6201-9857 Tel: 31-416-690399 Cleveland Tel: 852-2943-5100 Fax: 60-3-6201-9859 Fax: 31-416-690340 Independence, OH Fax: 852-2401-3431 Malaysia - Penang Poland - Warsaw Tel: 216-447-0464 China - Nanjing Tel: 60-4-227-8870 Tel: 48-22-3325737 Fax: 216-447-0643 Tel: 86-25-8473-2460 Fax: 60-4-227-4068 Spain - Madrid Dallas Fax: 86-25-8473-2470 Philippines - Manila Tel: 34-91-708-08-90 Addison, TX China - Qingdao Tel: 63-2-634-9065 Fax: 34-91-708-08-91 Tel: 972-818-7423 Tel: 86-532-8502-7355 Fax: 63-2-634-9069 Sweden - Stockholm Fax: 972-818-2924 Fax: 86-532-8502-7205 Singapore Tel: 46-8-5090-4654 Detroit Novi, MI China - Shanghai Tel: 65-6334-8870 UK - Wokingham Tel: 248-848-4000 Tel: 86-21-5407-5533 Fax: 65-6334-8850 Tel: 44-118-921-5800 Fax: 86-21-5407-5066 Taiwan - Hsin Chu Fax: 44-118-921-5820 Houston, TX China - Shenyang Tel: 886-3-5778-366 Tel: 281-894-5983 Tel: 86-24-2334-2829 Fax: 886-3-5770-955 Indianapolis Fax: 86-24-2334-2393 Noblesville, IN Taiwan - Kaohsiung China - Shenzhen Tel: 886-7-213-7830 Tel: 317-773-8323 Tel: 86-755-8864-2200 Fax: 317-773-5453 Taiwan - Taipei Fax: 86-755-8203-1760 Tel: 886-2-2508-8600 Los Angeles China - Wuhan Fax: 886-2-2508-0102 Mission Viejo, CA Tel: 86-27-5980-5300 Tel: 949-462-9523 Thailand - Bangkok Fax: 86-27-5980-5118 Fax: 949-462-9608 Tel: 66-2-694-1351 China - Xian Fax: 66-2-694-1350 New York, NY Tel: 86-29-8833-7252 Tel: 631-435-6000 Fax: 86-29-8833-7256 San Jose, CA Tel: 408-735-9110 China - Xiamen Tel: 86-592-2388138 Canada - Toronto Fax: 86-592-2388130 Tel: 905-673-0699 Fax: 905-673-6509 China - Zhuhai Tel: 86-756-3210040 03/25/14 Fax: 86-756-3210049 DS30000684B-page 508  2012-2014 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18LF45K50-I/PT PIC18LF24K50-I/SS PIC18LF25K50-I/SO PIC18F24K50-I/ML PIC18LF25K50-I/ML PIC18LF24K50-I/SP PIC18F25K50-I/SO PIC18LF45K50-I/P PIC18F24K50-I/SO PIC18F45K50-I/PT PIC18LF25K50- I/SP PIC18F45K50-I/P PIC18LF24K50-I/SO PIC18F24K50-I/SS PIC18F25K50-I/ML PIC18F25K50-I/SS PIC18F45K50-I/MV PIC18F25K50-I/SP PIC18LF24K50-I/ML PIC18LF45K50-I/MV PIC18LF25K50-I/SS PIC18F24K50-I/SP PIC18F45K50-E/MV PIC18F45K50T-I/PT PIC18F45K50-E/PT PIC18F45K50-E/P PIC18F45K50T-I/MV PIC18F24K50T-I/SO PIC18LF25K50T-I/SO PIC18F24K50T-I/SS PIC18F25K50T-I/SS PIC18LF24K50T-I/SS PIC18LF45K50T-I/PT PIC18LF25K50T-I/ML PIC18LF45K50T-I/MV PIC18LF25K50T-I/SS PIC18F25K50T-I/SO PIC18F24K50T-I/ML PIC18LF24K50T-I/ML PIC18LF24K50T-I/SO PIC18F25K50T-I/ML PIC18LF45K50-E/PT