PIC18F46J11 Family Data Sheet 28/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology  2011 Microchip Technology Inc. DS39932D

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-959-4 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39932D-page 2  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 28/44-Pin, Low-Power, High-Performance Microcontrollers Power Management Features with Peripheral Highlights (Continued): nanoWatt XLP for Extreme Low Power: • Four Programmable External Interrupts • Four Input Change Interrupts • Deep Sleep mode: CPU off, Peripherals off, Currents Down to 13 nA and 850 nA with RTCC • Two Enhanced Capture/Compare/PWM (ECCP) modules: - Able to wake-up on external triggers, - One, two or four PWM outputs programmable WDT or RTCC alarm - Selectable polarity - Ultra Low-Power Wake-up (ULPWU) - Programmable dead time • Sleep mode: CPU off, Peripherals off, SRAM on, - Auto-shutdown and auto-restart Fast Wake-up, Currents Down to 105 nA Typical - Pulse steering control • Idle: CPU off, Peripherals on, Currents Down to • Two Master Synchronous Serial Port (MSSP) 2.3 A Typical modules featuring: • Run: CPU on, Peripherals on, Currents Down to - 3-wire SPI (all 4 modes) 6.2 A Typical - 1024-byte SPI Direct Memory Access (DMA) • Timer1 Oscillator/w RTCC: 1 A, 32 kHz Typical channel • Watchdog Timer: 813 nA, 2V Typical - I2C™ Master and Slave modes • 8-Bit Parallel Master Port/Enhanced Parallel Special Microcontroller Features: Slave Port • 5.5V Tolerant Inputs (digital only pins) • Two-Rail – Rail Analog Comparators with Input • Low-Power, High-Speed CMOS Flash Technology Multiplexing • C Compiler Optimized Architecture for Re-Entrant • 10-Bit, up to 13-Channel Analog-to-Digital (A/D) Code Converter module: - Auto-acquisition capability • Priority Levels for Interrupts - Conversion available during Sleep • Self-Programmable under Software Control - Self-Calibration • 8 x 8 Single-Cycle Hardware Multiplier • High/Low-Voltage Detect module • Extended Watchdog Timer (WDT): • Charge Time Measurement Unit (CTMU): - Programmable period from 4ms to 131s - Supports capacitive touch sensing for touch • Single-Supply In-Circuit Serial Programming™ screens and capacitive switches (ICSP™) via Two Pins - Provides a Precise Resolution Time • In-Circuit Debug (ICD) with Three Breakpoints via Measurement for Both Flow Measurement Two Pins and Simple Temperature Sensing • Operating Voltage Range of 2.0V to 3.6V • Two Enhanced USART modules: • On-Chip 2.5V Regulator - Supports RS-485, RS-232 and LIN/J2602 • Flash Program Memory of 10,000 Erase/Write - Auto-wake-up on Start bit Cycles Minimum and 20-Year Data Retention • Auto-Baud Detect Flexible Oscillator Structure: Peripheral Highlights: • 1% Accurate High-Precision Internal Oscillator • Peripheral Pin Select: • Two External Clock modes, up to 48MHz (12 MIPS) - Allows independent I/O mapping of many • Low-Power 31kHz Internal RC Oscillator peripherals • Tunable Internal Oscillator (31kHz to 8MHz, - Continuous hardware integrity checking and ±0.15% Typical, ±1% Max). safety interlocks prevent unintentional • 4x PLL Option configuration changes • Secondary Oscillator using Timer1 @ 32kHz • Hardware Real-Time Clock and Calendar (RTCC): • Fail-Safe Clock Monitor: - Provides clock, calendar and alarm functions - Allows for safe shutdown if any clock stops • High-Current Sink/Source 25mA/25mA • Two-Speed Oscillator Start-up (PORTB and PORTC) • Programmable Reference Clock Output Generator  2011 Microchip Technology Inc. DS39932D-page 3

PIC18F46J11 FAMILY PICD1e8vFi/cLeF(1) Pins Program Memory (bytes) SRAM (bytes) Remappable Pins Timers8/16-Bit ECCP/(PWM) EUSART MSPI w/DMASSP 2C™I 10-Bit A/D (ch) Comparators Deep Sleep PMP/PSP CTMU RTCC PIC18F24J11 28 16K 3776 19 2/3 2 2 2 Y Y 10 2 Y N Y Y PIC18F25J11 28 32K 3776 19 2/3 2 2 2 Y Y 10 2 Y N Y Y PIC18F26J11 28 64K 3776 19 2/3 2 2 2 Y Y 10 2 Y N Y Y PIC18F44J11 44 16K 3776 25 2/3 2 2 2 Y Y 13 2 Y Y Y Y PIC18F45J11 44 32K 3776 25 2/3 2 2 2 Y Y 13 2 Y Y Y Y PIC18F46J11 44 64K 3776 25 2/3 2 2 2 Y Y 13 2 Y Y Y Y PIC18LF24J11 28 16K 3776 19 2/3 2 2 2 Y Y 10 2 N N Y Y PIC18LF25J11 28 32K 3776 19 2/3 2 2 2 Y Y 10 2 N N Y Y PIC18LF26J11 28 64K 3776 19 2/3 2 2 2 Y Y 10 2 N N Y Y PIC18LF44J11 44 16K 3776 25 2/3 2 2 2 Y Y 13 2 N Y Y Y PIC18LF45J11 44 32K 3776 25 2/3 2 2 2 Y Y 13 2 N Y Y Y PIC18LF46J11 44 64K 3776 25 2/3 2 2 2 Y Y 13 2 N Y Y Y Note 1: See Section1.3 “Details on Individual Family Devices”, Section4.6 “Deep Sleep Mode” and Section26.3 “On-Chip Voltage Regulator” for details describing the functional differences between PIC18F and PIC18LF variants in this device family. DS39932D-page 4  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY Pin Diagrams 28-Pin SPDIP/SOIC/SSOP(1) = Pins are up to 5.5V tolerant MCLR 1 28 RB7/KBI3/PGD/RP10 RA0/AN0/C1INA/ULPWU/RP0 2 27 RB6/KBI2/PGC/RP9 RA1/AN1/C2INA/RP1 3 26 RB5/KBI1/RP8 RA2/AN2/VREF-/CVREF/C2INB 4 25 RB4/KBI0/RP7 RA3/AN3/VREF+/C1INB 5 1 24 RB3/AN9/CTED2/RP6 VDDCORE/VCAP(2) 6 J1 23 RB2/AN8/CTED1/REFO/RP5 X RA5/AN4/SS1/HLVDIN/RP2 7 2 22 RB1/AN10/RTCC/RP4 F VSS 8 8 21 RB0/AN12/INT0/RP3 1 OSC1/CLKI/RA7 9 C 20 VDD OSC2/CLKO/RA6 10 PI 19 VSS RC0/T1OSO/T1CKI/RP11 11 18 RC7/RX1/DT1/RP18 RC1/T1OSI/RP12 12 17 RC6/TX1/CK1/RP17 RC2/AN11/CTPLS/RP13 13 16 RC5/SDO1/RP16 RC3/SCK1/SCL1/RP14 14 15 RC4/SDI1/SDA1/RP15 0 P R U/ 28-Pin QFN(1,3) 1PW 0 NA/RPNA/UL D/RP1C/RP987 = Pins are up to 5.5V tolerant C2IC1I PGPGRPRP N1/N0/ BI3/BI2/BI1/BI0/ AARKKKK A1/A0/CLB7/B6/B5/B4/ RRMRRRR 28272625242322 RA2/AN2/VREF-/CVREF/C2INB 1 21 RB3/AN9/CTED2/RP6 RA3/AN3/VREF+/C1INB 2 20 RB2/AN8/CTED1/REFO/RP5 VDDCORE/VCAP(2) 3 19 RB1/AN10/RTCC/RP4 RA5/AN4/SS1/HLVDIN/RP2 4 PIC18F2XJ11 18 RB0/AN12/INT0/RP3 VSS 5 17 VDD OSC1/CLKI/RA7 6 16 VSS OSC2/CLKO/RA6 7 15 RC7/RX1/DT1/RP18 8 91011121314 P11P12P13P14P15P16P17 RRRRRRR C0/T1OSO/T1CKI/RC1/T1OSI/RC2/AN11/CTPLS/RC3\SCK1\SCL1\RC4/SDA1RC5/SDO1/RC6/TX1/CK1/ R Legend: RPn represents remappable pins. Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table10-13 and Table10-14, respectively. For details on configuring the PPS module, see Section10.7 “Peripheral Pin Select (PPS)”. 2: See Section26.3 “On-Chip Voltage Regulator” for details on how to connect the VDDCORE/VCAP pin. 3: For the QFN package, it is recommended that the bottom pad be connected to VSS.  2011 Microchip Technology Inc. DS39932D-page 5

PIC18F46J11 FAMILY Pin Diagrams (Continued) = Pins are up to 5.5V tolerant 44-Pin QFN(1,3) 7 1 1 P 3 1 MA5/TX1/CK1/RDO1/RP16DI1/SDA1\RP15MD3/RP20MD2/RP19MD1/SDA2MD0/SCL2CK1/SCL1/RP14N11/CTPLS/RP11OSI/RP121OSO/T1CKI/RP PSSPPPPSATT 6/5/4/3/2/1/0/3\2/1/0/ CCCDDDDCCCC RRRRRRRRRRR 4443424140393837363534 RC7/PMA4/RX1/DT1/RP18 1 33 OSC2/CLKO/RA6 RD4/PMD4/RP21 2 32 OSC1/CLKI/RA7 RD5/PMD5/RP22 3 31 VSS RD6/PMD6/RP23 4 30 AVSS RD7/PMD7/RP24 5 29 VDD VSS 6 PIC18F4XJ11 28 AVDD AVDD 7 27 RE2/AN7/PMCS VDD 8 26 RE1/AN6/PMWR RB0/AN12/INT0/RP3 9 25 RE0/AN5/PMRD RB1/AN10/PMBE/RTCC/RP4 10 24 RA5/AN4/SS1/HLVDIN/RP2 RB2/AN8/CTED1/PMA3/REFO/RP5 11 23 VDDCORE/VCAP(2) 23456789012 11111111222 RB3/AN9/CTED2/PMA2/RP6NCRB4/PMA1/KBI0/RP7RB5/PMA0/KBI1/RP8RB6/KBI2/PGC/RP9RB7/KBI3/PGD/RP10MCLR0/C1INA/ULPWU/PMA6/RP0RA1/AN1/C2INA/PMA7/RP1A2/AN2/V-/CV-/C2INBREFREFRA3/AN3/V+/C1INBREF N R A 0/ A R Legend: RPn represents remappable pins. Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table10-13 and Table10-14, respectively. For details on configuring the PPS module, see Section10.7 “Peripheral Pin Select (PPS)”. 2: See Section26.3 “On-Chip Voltage Regulator” for details on how to connect the VDDCORE/VCAP pin. 3: For the QFN package, it is recommended that the bottom pad be connected to VSS. DS39932D-page 6  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY Pin Diagrams (Continued) 7 44-Pin TQFP(1) MA5/TX1/CK1/RP1DO1/RP16DI1/SDA1/RP15MD3/RP20MD2/RP19MD1/SDA2MD0/SCL2CK1/SCL1/RP14N11/CTPLS/RP131OSI/RP12 = Pins are up to 5.5V tolerant PSSPPPPSAT 6/5/4/3/2/1/0/3/2/1/ CCCDDDDCCCC RRRRRRRRRRN 43210987654 44444333333 RC7/PMA4/RX1/DT1/RP18 1 33 NC RD4/PMD4/RP21 2 32 RC0/T1OSO/T1CKI/RP11 RD5/PMD5/RP22 3 31 OSC2/CLKO/RA6 RD6/PMD6/RP23 4 30 OSC1/CLKI/RA7 RD7/PMD7/RP24 5 29 VSS VSS 6 PIC18F4XJ11 28 VDD VDD 7 27 RE2/AN7/PMCS RB0/AN12/INT0/RP3 8 26 RE1/AN6/PMWR RB1/AN10/PMBE/RTCC/RP4 9 25 RE0/AN5/PMRD RB2/AN8/CTED1/PMA3/REFO/RP5 10 24 RA5/AN4/SS1/HLVDIN/RP2 RB3/AN9/CTED2/PMA2/RP6 11 23 VDDCORE/VCAP(2) 23456789012 11111111222 NCNC4/PMA1/KBI0/RP75/PMA0/KBI1/RP8B6/KBI2/PGC/RP97/KBI3/PGD/RP10MCLRLPWU/PMA6/RP0C2INA/PMA7/RP1-/CV-/C2INBEFREFAN3/V+/C1INBREF RBRBRRB 0/C1INA/URA1/AN1/A2/AN2/VRRA3/ N R A 0/ A R Legend: RPn represents remappable pins. Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table10-13 and Table10-14, respectively. For details on configuring the PPS module, see Section10.7 “Peripheral Pin Select (PPS)”. 2: See Section26.3 “On-Chip Voltage Regulator” for details on how to connect the VDDCORE/VCAP pin.  2011 Microchip Technology Inc. DS39932D-page 7

PIC18F46J11 FAMILY Table of Contents Device Overview .................................................................................................................................................................................11 Guidelines for Getting Started with PIC18FJ Microcontrollers ............................................................................................................31 Oscillator Configurations .....................................................................................................................................................................37 Low-Power Modes ..............................................................................................................................................................................47 Reset ...................................................................................................................................................................................................63 Memory Organization ..........................................................................................................................................................................77 Flash Program Memory .....................................................................................................................................................................103 8 x 8 Hardware Multiplier ..................................................................................................................................................................113 Interrupts ...........................................................................................................................................................................................115 I/O Ports ............................................................................................................................................................................................131 Parallel Master Port (PMP) ...............................................................................................................................................................171 Timer0 Module ..................................................................................................................................................................................197 Timer1 Module ..................................................................................................................................................................................201 Timer2 Module ..................................................................................................................................................................................213 Timer3 Module ..................................................................................................................................................................................215 Timer4 Module ..................................................................................................................................................................................225 Real-Time Clock and Calendar (RTCC) ............................................................................................................................................227 Enhanced Capture/Compare/PWM (ECCP) Module ........................................................................................................................247 Master Synchronous Serial Port (MSSP) Module .............................................................................................................................271 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ........................................................................327 10-bit Analog-to-Digital Converter (A/D) Module ...............................................................................................................................351 Comparator Module ..........................................................................................................................................................................361 Comparator Voltage Reference Module ............................................................................................................................................369 High/Low Voltage Detect (HLVD) ......................................................................................................................................................373 Charge Time Measurement Unit (CTMU) .........................................................................................................................................379 Special Features of the CPU .............................................................................................................................................................395 Instruction Set Summary ...................................................................................................................................................................413 Development Support .......................................................................................................................................................................463 Electrical Characteristics ...................................................................................................................................................................467 Packaging Information ......................................................................................................................................................................507 Appendix A: Revision History ............................................................................................................................................................519 Appendix B: Device Differences ........................................................................................................................................................519 The Microchip Web Site ....................................................................................................................................................................533 Customer Change Notification Service .............................................................................................................................................533 Customer Support .............................................................................................................................................................................533 Reader Response .............................................................................................................................................................................534 Product Identification System ............................................................................................................................................................535 DS39932D-page 8  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2011 Microchip Technology Inc. DS39932D-page 9

PIC18F46J11 FAMILY NOTES: DS39932D-page 10  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 1.0 DEVICE OVERVIEW 1.1.2 OSCILLATOR OPTIONS AND FEATURES This document contains device-specific information for the following devices: All of the devices in the PIC18F46J11 family offer five different oscillator options, allowing users a range of • PIC18F24J11 • PIC18LF24J11 choices in developing application hardware. These • PIC18F25J11 • PIC18LF25J11 include: • PIC18F26J11 • PIC18LF26J11 • Two Crystal modes using crystals or ceramic • PIC18F44J11 • PIC18LF44J11 resonators. • Two External Clock modes offering the option of a • PIC18F45J11 • PIC18LF45J11 divide-by-4 clock output. • PIC18F46J11 • PIC18LF46J11 • An internal oscillator block, which provides an 8MHz clock and an INTRC source (approxi- 1.1 Core Features mately 31 kHz, stable over temperature and VDD), as well as a range of six user-selectable clock 1.1.1 nanoWatt TECHNOLOGY frequencies, between 125 kHz to 4 MHz, for a All of the devices in the PIC18F46J11 family incorporate total of eight clock frequencies. This option frees a range of features that can significantly reduce power an oscillator pin for use as an additional general consumption during operation. Key features are: purpose I/O. • Alternate Run Modes: By clocking the controller • A Phase Lock Loop (PLL) frequency multiplier, from the Timer1 source or the internal RC available to the high-speed crystal, and external oscillator, power consumption during code and internal oscillators, providing a clock speed execution can be reduced by as much as 90%. up to 48 MHz. • Multiple Idle Modes: The controller can also run The internal oscillator block provides a stable reference with its CPU core disabled but the peripherals still source that gives the PIC18F46J11 family additional active. In these states, power consumption can be features for robust operation: reduced even further, to as little as 4% of normal • Fail-Safe Clock Monitor: This option constantly operational requirements. monitors the main clock source against a reference • On-the-Fly Mode Switching: The signal provided by the internal oscillator. If a clock power-managed modes are invoked by user code failure occurs, the controller is switched to the during operation, allowing the users to incorporate internal oscillator, allowing for continued low-speed power-saving ideas into their application’s operation or a safe application shutdown. software design. • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset (POR), or wake-up from Sleep mode, until the primary clock source is available. 1.1.3 EXPANDED MEMORY The PIC18F46J11 family provides ample room for application code, from 16 Kbytes to 64 Kbytes of code space. The Flash cells for program memory are rated to last in excess of 10000 erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 20 years. The Flash program memory is readable and writable during normal operation. The PIC18F46J11 family also provides plenty of room for dynamic application data with up to 3.8Kbytes of data RAM.  2011 Microchip Technology Inc. DS39932D-page 11

PIC18F46J11 FAMILY 1.1.4 EXTENDED INSTRUCTION SET • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a The PIC18F46J11 family implements the optional channel to be selected and a conversion to be extension to the PIC18 instruction set, adding eight initiated without waiting for a sampling period, and new instructions and an Indexed Addressing mode. thus, reducing code overhead. Enabled as a device configuration option, the extension has been specifically designed to optimize re-entrant • Extended Watchdog Timer (WDT): This application code originally developed in high-level enhanced version incorporates a 16-bit prescaler, languages, such as C. allowing an extended time-out range that is stable across operating voltage and temperature. See 1.1.5 EASY MIGRATION Section29.0 “Electrical Characteristics” for time-out periods. Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth 1.3 Details on Individual Family migration path as applications grow and evolve. Devices The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger Devices in the PIC18F46J11 family are available in device. 28-pin and 44-pin packages. Block diagrams for the two groups are shown in Figure1-1 and Figure1-2. The PIC18F46J11 family is also pin compatible with The devices are differentiated from each other in two other PIC18 families, such as the PIC18F4620, ways: PIC18F4520 and PIC18F45J10. This allows a new dimension to the evolution of applications, allowing • Flash program memory (three sizes: 16Kbytes developers to select different price points within for the PIC18FX4J11, 32 Kbytes for PIC18FX5J11 Microchip’s PIC18 portfolio, while maintaining the devices and 64Kbytes for PIC18FX6J11) same feature set. • I/O ports (three bidirectional ports on 28-pin devices, five bidirectional ports on 44-pin devices) 1.2 Other Special Features All other features for devices in this family are identical. • Communications: The PIC18F46J11 family These are summarized in Table1-1 and Table1-2. incorporates a range of serial and parallel The pinouts for the PIC18F2XJ11 devices are listed in communication peripherals. This device also Table1-3 and the pinouts for the PIC18F4XJ11 devices includes two independent Enhanced USARTs and are listed in Table1-4. two Master Synchronous Serial Port (MSSP) The PIC18F46J11 family of devices provides an modules, capable of both Serial Peripheral Inter- face (SPI) and I2C™ (Master and Slave) modes of on-chip voltage regulator to supply the correct voltage levels to the core. Parts designated with an “F” part operation. The device also has a parallel port and number (such as PIC18F46J11) have the voltage can be configured to serve as either a Parallel regulator enabled. Master Port (PMP) or as a Parallel Slave Port (PSP). These parts can run from 2.15V-3.6V on VDD, but should • ECCP Modules: All devices in the family have the VDDCORE pin connected to VSS through a low-ESR capacitor. Parts designated with an “LF” part incorporate three Enhanced Capture/Compare/PWM (ECCP) modules to number (such as PIC18LF46J11) do not enable the volt- age regulator. For “LF” parts, an external supply of maximize flexibility in control applications. Up to four different time bases may be used to perform 2.0V-2.7V has to be supplied to the VDDCORE pin with several different operations at once. Each of the 2.0V-3.6V supplied to VDD (VDDCORE should never ECCPs offers up to four PWM outputs, allowing for exceed VDD). a total of eightPWMs. The ECCPs also offer many For more details about the internal voltage regulator, beneficial features, including polarity selection, pro- see Section26.3 “On-Chip Voltage Regulator”. grammable dead time, auto-shutdown and restart and Half-Bridge and Full-Bridge Output modes. DS39932D-page 12  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XJ11 (28-PIN DEVICES) Features PIC18F24J11 PIC18F25J11 PIC18F26J11 Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz Program Memory (Bytes) 16K 32K 64K Program Memory (Instructions) 8,192 16,384 32,768 Data Memory (Bytes) 3.8K 3.8K 3.8K Interrupt Sources 30 I/O Ports Ports A, B, C Timers 5 Enhanced Capture/Compare/PWM Modules 2 Serial Communications MSSP (2), Enhanced USART (2) Parallel Communications (PMP/PSP) No 10-Bit Analog-to-Digital Module 10 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 28-Pin QFN, SOIC, SSOP and SPDIP (300mil) TABLE 1-2: DEVICE FEATURES FOR THE PIC18F4XJ11 (44-PIN DEVICES) Features PIC18F44J11 PIC18F45J11 PIC18F46J11 Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz Program Memory (Bytes) 16K 32K 64K Program Memory (Instructions) 8,192 16,384 32,768 Data Memory (Bytes) 3.8K 3.8K 3.8K Interrupt Sources 30 I/O Ports Ports A, B, C, D, E Timers 5 Enhanced Capture/Compare/PWM Modules 2 Serial Communications MSSP (2), Enhanced USART (2) Parallel Communications (PMP/PSP) Yes 10-Bit Analog-to-Digital Module 13 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 44-Pin QFN and TQFP  2011 Microchip Technology Inc. DS39932D-page 13

PIC18F46J11 FAMILY FIGURE 1-1: PIC18F2XJ11 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch inc/dec logic 8 8 RA0:RA7(1) Data Memory (3.8 Kbytes) 21 PCLAT U PCLATH 20 Address Latch PCU PCH PCL Program Counter 12 PORTB Data Address<12> RB0:RB7(1) 31-Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (16 Kbytes-64Kbytes) FSR1 Data Latch FSR2 12 PORTC inc/dec RC0:RC7(1) 8 logic Table Latch Address ROM Latch Instruction Bus <16> Decode IR 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL 8 x 8 Multiply OSC2/CLKO GeTnimeriantgion Power-up 3 8 OSC1/CLKI IN8T MOHSzC Timer BITO8P W8 8 Oscillator INTRC Start-up Timer Oscillator 8 8 Power-on ALU<8> Reset 8 Precision Watchdog Band Gap Timer Reference Brown-out Voltage Reset(2) Regulator VDDCORE/VCAP VDD,VSS MCLR ADC RTCC LVD 10-Bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators CTMU ECCP1 ECCP2 EUSART1 EUSART2 MSSP1 MSSP2 Note 1: See Table1-3 for I/O port pin descriptions. 2: BOR functionality is provided when the on-chip voltage regulator is enabled. DS39932D-page 14  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 1-2: PIC18F4XJ11 (44-PIN) BLOCK DIAGRAM Data Bus<8> PORTA Table Pointer<21> 8 8 Data Latch RA0:RA7(1) Data Memory inc/dec logic PCLAT U PCLATH (3.8 Kbytes) 21 20 Address Latch PCU PCH PCL PORTB Program Counter 12 RB0:RB7(1) Data Address<12> 31-Level Stack e Address Latch 4 12 4 nterfac (16P rKobgyrtaems- 6M4eKmboyrtyes) STKPTR BSR FFSSRR01 ABccaensks RCP0O:RRCTC7(1) us I Data Latch FSR2 12 B m ste 8 inloc/gdiecc PORTD Sy Table Latch RD0:RD7(1) Address ROM Latch Decode Instruction Bus <16> PORTE IR RE0:RE2(1) AD<15:0>, A<19:16> (Multiplexed with PORTD 8 and PORTE) PRODH PRODL State Machine Instruction Decode and Control Signals Control 8 x 8 Multiply 3 8 BITOP W OSC2/CLKO GeTnimeriantgion Power-up 8 8 8 OSC1/CLKI Timer 8 MHz INTOSC 8 8 Oscillator INTRC Start-up Timer ALU<8> Oscillator 8 Power-on Reset Precision Watchdog Band Gap Timer Reference Brown-out Voltage Reset(2) Regulator VDDCORE/VCAP VDD,VSS MCLR ADC RTCC LVD 10-Bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators PMP CTMU ECCP1 ECCP2 EUSART1 EUSART2 MSSP1 MSSP2 Note 1: See Table1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-chip voltage regulator is enabled.  2011 Microchip Technology Inc. DS39932D-page 15

PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name 28-SPDIP/ Description Type Type SSOP/ 28-QFN SOIC MCLR 1 26 I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OSC1/CLKI/RA7 9 6 OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. Main oscillator input connection. CLKI I CMOS External clock source input; always associated with pin function OSC1 (see related OSC1/CLKI pins). RA7(1) I/O TTL Digital I/O. OSC2/CLKO/RA6 10 7 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — Main oscillator feedback output connection. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6(1) I/O TTL Digital I/O. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932D-page 16  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name 28-SPDIP/ Description Type Type SSOP/ 28-QFN SOIC PORTA is a bidirectional I/O port. RA0/AN0/C1INA/ULPWU/RP0 2 27 RA0 I/O DIG Digital I/O. AN0 I Analog Analog input 0. C1INA I Analog Comparator 1 input A. ULPWU I Analog Ultra low-power wake-up input. RP0 I/O DIG Remappable peripheral pin 0. RA1/AN1/C2INA/RP1 3 28 RA1 I/O DIG Digital I/O. AN1 O Analog Analog input 1. C2INA I Analog Comparator 2 input A. RP1 I/O DIG Remappable peripheral pin 1. RA2/AN2/VREF-/CVREF/C2INB 4 1 RA2 I/O DIG Digital I/O. AN2 I Analog Analog input 2. VREF- O Analog A/D reference voltage (low) input. CVREF I Analog Comparator reference voltage output. C2INB I Analog Comparator 2 input B. RA3/AN3/VREF+/C1INB 5 2 RA3 I/O DIG Digital I/O AN3 I Analog Analog input 3 VREF+ I Analog A/D reference voltage (high) input C1INB I Analog Comparator 1 input B RA5/AN4/SS1/HLVDIN/ 7 4 RP2 RA5 I/O DIG Digital I/O. AN4 I Analog Analog input 4. SS1 I TTL SPI slave select input. HLVDIN I Analog High/low-voltage detect input. RP2 I/O DIG Remappable peripheral pin 2. RA6(1) See the OSC2/CLKO/RA6 pin. RA7(1) See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.  2011 Microchip Technology Inc. DS39932D-page 17

PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name 28-SPDIP/ Description Type Type SSOP/ 28-QFN SOIC PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0/RP3 21 18 RB0 I/O DIG Digital I/O. AN12 I Analog Analog input 12. INT0 I ST External interrupt 0. RP3 I/O DIG Remappable peripheral pin 3. RB1/AN10/RTCC/RP4 22 19 RB1 I/O DIG Digital I/O. AN10 I Analog Analog input 10. RTCC O DIG Real Time Clock Calendar output. RP4 I/O DIG Remappable peripheral pin 4. RB2/AN8/CTED1/ 23 20 REFO/RP5 RB2 I/O DIG Digital I/O. AN8 I Analog Analog input 8. CTED1 I ST CTMU edge 1 input. REFO O DIG Reference output clock. RP5 I/O DIG Remappable peripheral pin 5. RB3/AN9/CTED2/RP6 24 21 RB3 I/O DIG Digital I/O. AN9 I Analog Analog input 9. CTED2 I/O ST CTMU edge 2 input. RP6 I DIG Remappable peripheral pin 6. RB4/KBI0/RP7 25 22 RB4 I/O DIG Digital I/O. KBI0 I TTL Interrupt-on-change pin. RP7 I/O DIG Remappable peripheral pin 7. RB5/KBI1/RP8 26 23 RB5 I/O DIG Digital I/O. KBI1 I TTL Interrupt-on-change pin. RP8 I/O DIG Remappable peripheral pin 8. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932D-page 18  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name 28-SPDIP/ Description Type Type SSOP/ 28-QFN SOIC PORTB (continued) RB6/KBI2/PGC/RP9 27 24 RB6 I/O DIG Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I ST ICSP™ clock input. RP9 I/O DIG Remappable peripheral pin 9. RB7/KBI3/PGD/RP10 28 25 RB7 I/O DIG Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. RP10 I/O DIG Remappable peripheral pin 10. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.  2011 Microchip Technology Inc. DS39932D-page 19

PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name 28-SPDIP/ Description Type Type SSOP/ 28-QFN SOIC PORTC is a bidirectional I/O port RC0/T1OSO/T1CKI/RP11 11 8 RC0 I/O ST Digital I/O. T1OSO O Analog Timer1 oscillator output. T1CKI I ST Timer1/Timer3 external clock input. RP11 I/O DIG Remappable peripheral pin 11. RC1/T1OSI/RP12 12 9 RC1 I/O ST Digital I/O. T1OSI I Analog Timer1 oscillator input. RP12 I/O DIG Remappable peripheral pin 12. RC2/AN11/CTPLS/RP13 13 10 RC2 I/O ST Digital I/O. AN11 I Analog Analog input 11. CTPLS O DIG CTMU pulse generator output. RP13 I/O DIG Remappable peripheral pin 13. RC3/SCK1/SCL1/RP14 14 11 RC3 I/O ST Digital I/O. SCK1 I/O DIG Synchronous serial clock input/output for SPI mode. SCL1 I/O I2C Synchronous serial clock input/output for I2C™ mode. RP14 I/O DIG Remappable peripheral pin 14. RC4/SDI1/SDA1/RP15 15 12 RC4 I/O ST Digital I/O. SDI1 I ST SPI data input. SDA1 I/O I2C I2C data I/O. RP15 I/O DIG Remappable peripheral pin 15. RC5/SDO1/RP16 16 13 RC5 I/O ST Digital I/O. SDO1 O DIG SPI data output. RP16 I/O DIG Remappable peripheral pin 16. RC6/TX1/CK1/RP17 17 14 RC6 I/O ST Digital I/O. TX1 O DIG EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1). RP17 I/O DIG Remappable peripheral pin 17. RC7/RX1/DT1/RP18 18 15 RC7 I/O ST Digital I/O. RX1 I ST Asynchronous serial receive data input. DT1 I/O ST Synchronous serial data output/input. RP18 I/O DIG Remappable peripheral pin 18. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932D-page 20  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name 28-SPDIP/ Description Type Type SSOP/ 28-QFN SOIC VSS1 8 5 P — Ground reference for logic and I/O pins. VSS2 19 16 — — VDD 20 17 P — Positive supply for peripheral digital logic and I/O pins. VDDCORE/VCAP 6 3 Core logic power or external filter capacitor connection. VDDCORE P — Positive supply for microcontroller core logic (regulator disabled). VCAP P — External filter capacitor connection (regulator enabled). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.  2011 Microchip Technology Inc. DS39932D-page 21

PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description 44- 44- Type Type QFN TQFP MCLR 18 18 I ST Master Clear (Reset) input; this is an active-low Reset to the device. OSC1/CLKI/RA7 32 30 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. Main oscillator input connection. CLKI I CMOS External clock source input; always associated with pin function OSC1 (see related OSC1/CLKI pins). RA7(1) I/O TTL Digital I/O. OSC2/CLKO/RA6 33 31 Oscillator crystal or clock output OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — Main oscillator feedback output connection in RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6(1) I/O TTL Digital I/O. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932D-page 22  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description 44- 44- Type Type QFN TQFP PORTA is a bidirectional I/O port. RA0/AN0/C1INA/ULPWU/PMA6/ 19 19 RP0 RA0 I/O DIG Digital I/O. AN0 I Analog Analog input 0. C1INA I Analog Comparator 1 input A. ULPWU I Analog Ultra low-power wake-up input. PMA6 O DIG Parallel Master Port digital output. RP0 I/O DIG Remappable peripheral pin 0. RA1/AN1/C2INA/PMA7/RP1 20 20 RA1 I/O DIG Digital I/O. AN1 O Analog Analog input 1. C2INA I Analog Comparator 2 input A. PMA7 O DIG Parallel Master Port digital output. RP1 I/O DIG Remappable peripheral pin 1. RA2/AN2/VREF-/CVREF/C2INB 21 21 RA2 I/O DIG Digital I/O. AN2 I Analog Analog input 2. VREF- O Analog A/D reference voltage (low) input. CVREF I Analog Comparator reference voltage output. C2INB I Analog Comparator 2 input B. RA3/AN3/VREF+/C1INB 22 22 RA3 I/O DIG Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. C1INB I Analog Comparator 1 input B. RA5/AN4/SS1/HLVDIN/RP2 24 24 RA5 I/O DIG Digital I/O. AN4 I Analog Analog input 4. SS1 I TTL SPI slave select input. HLVDIN I Analog High/low-voltage detect input. RP2 I/O DIG Remappable peripheral pin 2. RA6(1) See the OSC2/CLKO/RA6 pin. RA7(1) See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.  2011 Microchip Technology Inc. DS39932D-page 23

PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description 44- 44- Type Type QFN TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0/RP3 9 8 RB0 I/O DIG Digital I/O. AN12 I Analog Analog input 12. INT0 I ST External interrupt 0. RP3 I/O DIG Remappable peripheral pin 3. RB1/AN10/PMBE/RTCC/RP4 10 9 RB1 I/O DIG Digital I/O. AN10 I Analog Analog input 10. PMBE O DIG Parallel Master Port byte enable. RTCC O DIG Real Time Clock Calendar output. RP4 I/O DIG Remappable peripheral pin 4. RB2/AN8/CTED1/PMA3/REFO/ 11 10 RP5 RB2 I/O DIG Digital I/O. AN8 I Analog Analog input 8. CTED1 I ST CTMU edge 1 input. PMA3 O DIG Parallel Master Port address. REFO O DIG Reference output clock. RP5 I/O DIG Remappable peripheral pin 5. RB3/AN9/CTED2/PMA2/RP6 12 11 RB3 I/O DIG Digital I/O. AN9 I Analog Analog input 9. CTED2 I ST CTMU edge 2 input. PMA2 O DIG Parallel Master Port address. RP6 I/O DIG Remappable peripheral pin 6. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932D-page 24  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description 44- 44- Type Type QFN TQFP PORTB (continued) RB4/PMA1/KBI0/RP7 14 14 RB4 I/O DIG Digital I/O. PMA1 O DIG Parallel Master Port address. KBI0 I TTL Interrupt-on-change pin. RP7 I/O DIG Remappable peripheral pin 7 RB5/PMA0/KBI1/RP8 15 15 RB5 I/O DIG Digital I/O. PMA0 O DIG Parallel Master Port address. KBI1 I TTL Interrupt-on-change pin. RP8 I/O DIG Remappable peripheral pin 8. RB6/KBI2/PGC/RP9 16 16 RB6 I/O DIG Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I ST ICSP™ clock input. RP9 I/O DIG Remappable peripheral pin 9. RB7/KBI3/PGD/RP10 17 17 RB7 I/O DIG Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. RP10 I/O DIG Remappable peripheral pin 10. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.  2011 Microchip Technology Inc. DS39932D-page 25

PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description 44- 44- Type Type QFN TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI/RP11 34 32 RC0 I/O ST Digital I/O. T1OSO O Analog Timer1 oscillator output. T1CKI I ST Timer1/Timer3 external clock input. RP11 I/O DIG Remappable peripheral pin 11. RC1/T1OSI/RP12 35 35 RC1 I/O ST Digital I/O. T1OSI I Analog Timer1 oscillator input. RP12 I/O DIG Remappable peripheral pin 12. RC2/AN11/CTPLS/RP13 36 36 RC2 I/O ST Digital I/O. AN11 I Analog Analog input 11. CTPLS O DIG CTMU pulse generator output. RP13 I/O DIG Remappable peripheral pin 13. RC3/SCK1/SCL1/RP14 37 37 RC3 I/O ST Digital I/0. SCK1 I/O DIG Synchronous serial clock input/output for SPI mode. SCL1 I/O I2C Synchronous serial clock input/output for I2C™ mode. RP14 I/O DIG Remappable peripheral pin 14. RC4/SDI1/SDA1/RP15 42 42 RC4 I/O ST Digital I/O. SDI1 I ST SPI data input. SDA1 I/O I2C I2C data I/O. RP15 I/O DIG Remappable peripheral pin 15. RC5/SDO1/RP16 43 43 RC5 I/O ST Digital /O. SDO1 O DIG SPI data output. RP16 I/O DIG Remappable peripheral pin 16. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932D-page 26  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description 44- 44- Type Type QFN TQFP PORTC (continued) RC6/PMA5/TX1/CK1/RP17 44 44 RC6 I/O ST Digital I/O. PMA5 O DIG Parallel Master Port address. TX1 O DIG EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1). RP17 I/O DIG Remappable peripheral pin 17. RC7/PMA4/RX1/DT1/RP18 1 1 RC7 I/O ST Digital I/O. PMA4 O DIG Parallel Master Port address. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1). RP18 I/O DIG Remappable peripheral pin 18. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.  2011 Microchip Technology Inc. DS39932D-page 27

PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description 44- 44- Type Type QFN TQFP PORTD is a bidirectional I/O port. RD0/PMD0/SCL2 38 38 RD0 I/O ST Digital I/O. PMD0 I/O DIG Parallel Master Port data. SCL2 I/O I2C I2C™ data input/output. RD1/PMD1/SDA2 39 39 RD1 I/O ST Digital I/O. PMD1 I/O DIG Parallel Master Port data. SDA2 I/O I2C I2C data input/output. RD2/PMD2/RP19 40 40 RD2 I/O ST Digital I/O. PMD2 I/O DIG Parallel Master Port data. RP19 I/O DIG Remappable peripheral pin 19. RD3/PMD3/RP20 41 41 RD3 I/O ST Digital I/O. PMD3 I/O DIG Parallel Master Port data. RP20 I/O DIG Remappable peripheral pin 20. RD4/PMD4/RP21 2 2 RD4 I/O ST Digital I/O. PMD4 I/O DIG Parallel Master Port data. RP21 I/O DIG Remappable peripheral pin 21. RD5/PMD5/RP22 3 3 RD5 I/O ST Digital I/O. PMD5 I/O DIG Parallel Master Port data. RP22 I/O DIG Remappable peripheral pin 22. RD6/PMD6/RP23 4 4 RD6 I/O ST Digital I/O. PMD6 I/O DIG Parallel Master Port data. RP23 I/O DIG Remappable peripheral pin 23. RD7/PMD7/RP24 5 5 RD7 I/O ST Digital I/O. PMD7 I/O DIG Parallel Master Port data. RP24 I/O DIG Remappable peripheral pin 24. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. DS39932D-page 28  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description 44- 44- Type Type QFN TQFP PORTE is a bidirectional I/O port. RE0/AN5/PMRD 25 25 RE0 I/O ST Digital I/O. AN5 I Analog Analog input 5. PMRD I/O DIG Parallel Master Port input/output. RE1/AN6/PMWR 26 26 RE1 I/O ST Digital I/O. AN6 I Analog Analog input 6. PMWR I/O DIG Parallel Master Port write strobe. RE2/AN7/PMCS 27 27 RE2 I/O ST Digital I/O. AN7 I Analog Analog input 7. PMCS O — Parallel Master Port byte enable. VSS1 6 6 P — Ground reference for logic and I/O pins. VSS2 31 29 — — AVSS1 30 — P — Ground reference for analog modules. VDD1 8 7 P — Positive supply for peripheral digital logic and VDD2 29 28 P — I/O pins. VDDCORE/VCAP 23 23 Core logic power or external filter capacitor connection. VDDCORE P — Positive supply for microcontroller core logic (regulator disabled). VCAP P — External filter capacitor connection (regulator enabled). AVDD1 7 — P — Positive supply for analog modules. AVDD2 28 — — — Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.  2011 Microchip Technology Inc. DS39932D-page 29

PIC18F46J11 FAMILY NOTES: DS39932D-page 30  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED MINIMUM STARTED WITH PIC18FJ CONNECTIONS MICROCONTROLLERS C2(1) 2.1 Basic Connection Requirements VDD Getting started with the PIC18F46J11 family of 8-bit R1 DD SS microcontrollers requires attention to a minimal set of V V R2 device pin connections before proceeding with MCLR development. VCAP/VDDCORE C1 The following pins must always be connected: C7 PIC18FXXJXX • All VDD and VSS pins (see Section2.2 “Power Supply Pins”) VSS VDD C6(1) C3(1) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S VSS D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(1) C4(1) • VCAP/VDDCORE pins (see Section2.4 “Voltage Regulator Pins (VCAP/VDDCORE)”) These pins must also be connected if they are being Key (all values are recommendations): used in the end application: C1 through C6: 0.1 F, 20V ceramic • PGC/PGD pins used for In-Circuit Serial C7: 10 F, 6.3V or greater, tantalum or ceramic Programming™ (ICSP™) and debugging purposes R1: 10 kΩ (see Section2.5 “ICSP Pins”) R2: 100Ω to 470Ω • OSCI and OSCO pins when an external oscillator Note 1: The example shown is for a PIC18F device source is used with five VDD/VSS and AVDD/AVSS pairs. (see Section2.6 “External Oscillator Pins”) Other devices may have more or less pairs; Additionally, the following pins may be required: adjust the number of decoupling capacitors appropriately. • VREF+/VREF- pins are used when external voltage reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1.  2011 Microchip Technology Inc. DS39932D-page 31

PIC18F46J11 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: Device Reset, and Device Programming The use of decoupling capacitors on every pair of and Debugging. If programming and debugging are power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct AVSS, is required. connection to VDD may be all that is required. The Consider the following criteria when using decoupling addition of other components, to help increase the capacitors: application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical • Value and type of capacitor: A 0.1 F (100 nF), configuration is shown in Figure2-1. Other circuit 10-20V capacitor is recommended. The capacitor designs may be implemented, depending on the should be a low-ESR device, with a resonance application’s requirements. frequency in the range of 200MHz and higher. Ceramic capacitors are recommended. During programming and debugging, the resistance • Placement on the printed circuit board: The and capacitance that can be added to the pin must decoupling capacitors should be placed as close be considered. Device programmers and debuggers to the pins as possible. It is recommended to drive the MCLR pin. Consequently, specific voltage place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the capacitor can be placed on another layer on the application and PCB requirements. For example, it is PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated length from the pin to the capacitor is no greater from the MCLR pin during programming and than 0.25inch (6mm). debugging operations by using a jumper (Figure2-2). • Handling high-frequency noise: If the board is The jumper is replaced for normal run-time experiencing high-frequency noise (upward of operations. tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling Any components associated with the MCLR pin capacitor. The value of the second capacitor can should be placed within 0.25 inch (6mm) of the pin. be in the range of 0.01F to 0.001F. Place this second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN capacitor. In high-speed circuit designs, consider CONNECTIONS implementing a decade pair of capacitances as close to the power and ground pins as possible VDD (e.g., 0.1F in parallel with 0.001F). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the JP PIC18FXXJXX decoupling capacitors are first in the power chain. Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R1 10k is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10k. Ensure that the On boards with power traces running longer than MCLR pin VIH and VIL specifications are met. sixinches in length, it is suggested to use a tank capac- 2: R2470 will limit any current flowing into itor for integrated circuits, including microcontrollers, to MCLR from the external capacitor, C, in the supply a local power source. The value of the tank event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical capacitor should be determined based on the trace Overstress (EOS). Ensure that the MCLR pin resistance that connects the power supply source to VIH and VIL specifications are met. the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7F to 47F. DS39932D-page 32  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 2.4 Voltage Regulator Pins (VCAP/ Note that the “LF” versions are provided with the VDDCORE) voltage regulator permanently disabled; they must always be provided with a supply voltage on the When the regulator is enabled (“F” devices), a low-ESR VDDCORE pin. (<5Ω) capacitor is required on the VCAP/VDDCORE pin to stabilize the voltage regulator output voltage. The VCAP/ FIGURE 2-3: FREQUENCY vs. ESR VDDCORE pin must not be connected to VDD and must PERFORMANCE FOR use a capacitor of 10 µF connected to ground. The type SUGGESTED VCAP can be ceramic or tantalum. Suitable examples of capacitors are shown in Table2-1. Capacitors with 10 equivalent specifications can be used. Designers may use Figure2-3 to evaluate ESR 1 equivalence of candidate devices. ) It is recommended that the trace length not exceed R ( 0.1 0.25inch (6mm). Refer to Section28.0 “Electrical S E Characteristics” for additional information. 0.01 When the regulator is disabled (“LF” devices), the VCAP/VDDCORE pin must be tied to a voltage supply at the VDDCORE level. Refer to Section28.0 “Electrical 0.001 0.01 0.1 1 10 100 1000 10,000 Characteristics” for information on VDD and Frequency (MHz) VDDCORE. Note: Typical data measurement at 25°C, 0V DC bias. . TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Nominal Make Part # Base Tolerance Rated Voltage Temp. Range Capacitance TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC  2011 Microchip Technology Inc. DS39932D-page 33

PIC18F46J11 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC FIGURE 2-4: DC BIAS VOLTAGE vs. CAPACITORS CAPACITANCE CHARACTERISTICS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic %) 10 e ( 0 capacitors very attractive in many types of applications. ng-10 16V Capacitor ha-20 Ceramic capacitors are suitable for use with the C-30 VDDCORE voltage regulator of this microcontroller. ance --5400 10V Capacitor However, some care is needed in selecting the capac- cit-60 itor to ensure that it maintains sufficient capacitance Capa--8700 6.3V Capacitor over the intended operating range of the application. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage (VDC) Typical low-cost, 10µF ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial toler- When selecting a ceramic capacitor to be used with the ance specifications for these types of capacitors are VDDCORE voltage regulator, it is suggested to select a often specified as ±10% to ±20% (X5R and X7R), or - high-voltage rating, so that the operating voltage is a 20%/+80% (Y5V). However, the effective capacitance small percentage of the maximum rated capacitor volt- that these capacitors provide in an application circuit will age. For example, choose a ceramic capacitor rated at also vary based on additional factors, such as the 16V for the 2.5V VDDCORE voltage. Suggested applied DC bias voltage and the temperature. The total capacitors are shown in Table2-1. in-circuit tolerance is, therefore, much wider than the initial tolerance specification. 2.5 ICSP Pins The X5R and X7R capacitors typically exhibit satisfac- The PGC and PGD pins are used for In-Circuit Serial tory temperature stability (ex: ±15% over a wide Programming™ (ICSP™) and debugging purposes. It temperature range, but consult the manufacturer's data is recommended to keep the trace length between the sheets for exact specifications). However, Y5V capaci- ICSP connector and the ICSP pins on the device as tors typically have extreme temperature tolerance short as possible. If the ICSP connector is expected to specifications of +22%/-82%. Due to the extreme experience an ESD event, a series resistor is recom- temperature tolerance, a 10µF nominal rated Y5V type mended, with the value in the range of a few tens of capacitor may not deliver enough total capacitance to ohms, not to exceed 100Ω. meet minimum VDDCORE voltage regulator stability and Pull-up resistors, series diodes, and capacitors on the transient response requirements. Therefore, Y5V PGC and PGD pins are not recommended as they will capacitors are not recommended for use with the interfere with the programmer/debugger communica- VDDCORE regulator if the application must operate over tions to the device. If such discrete components are an a wide temperature range. application requirement, they should be removed from In addition to temperature tolerance, the effective the circuit during programming and debugging. Alter- capacitance of large value ceramic capacitors can vary natively, refer to the AC/DC characteristics and timing substantially, based on the amount of DC voltage requirements information in the respective device applied to the capacitor. This effect can be very signifi- Flash programming specification for information on cant, but is often overlooked or is not always capacitive loading limits, and pin input voltage high documented. (VIH) and input low (VIL) requirements. A typical DC bias voltage vs. capacitance graph for For device emulation, ensure that the “Communication X7R type and Y5V type capacitors is shown in Channel Select” (i.e., PGCx/PGDx pins), programmed Figure2-4. into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section28.0 “Development Support”. DS39932D-page 34  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: SUGGESTED PLACEMENT OF THE OSCILLATOR Many microcontrollers have options for at least two CIRCUIT oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Single-Sided and In-Line Layouts: Section3.0 “Oscillator Configurations” for details). Copper Pour Primary Oscillator The oscillator circuit should be placed on the same (tied to ground) Crystal side of the board as the device. Place the oscillator DEVICE PINS circuit close to the respective oscillator pins with no more than 0.5inch (12mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Primary OSC1 Oscillator of the board. C1 ` OSC2 Use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. The C2 GND grounded copper pour should be routed directly to the ` MCU ground. Do not run any signal traces or power T1OSO traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board T1OS I Timer1 Oscillator where the crystal is placed. Crystal ` Layout suggestions are shown in Figure2-5. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With T1 Oscillator: C1 T1 Oscillator: C2 fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts: ground layer. In all cases, the guard trace(s) must be returned to ground. Top Layer Copper Pour (tied to ground) In planning the application’s routing and I/O assign- ments, ensure that adjacent port pins, and other Bottom Layer signals in close proximity to the oscillator, are benign Copper Pour (i.e., free of high frequencies, short rise and fall times, (tied to ground) and other similar noise). OSCO For additional information and design guidance on oscillator circuits, please refer to these Microchip C2 Application Notes, available at the corporate web site Oscillator (www.microchip.com): GND Crystal • AN826, “Crystal Oscillator Basics and Crystal C1 Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” OSCI • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” 2.7 Unused I/Os DEVICE PINS Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the output to logic low.  2011 Microchip Technology Inc. DS39932D-page 35

PIC18F46J11 FAMILY NOTES: DS39932D-page 36  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 3.0 OSCILLATOR TABLE 3-1: OSCILLATOR MODES CONFIGURATIONS Mode Description ECPLL External Clock Input mode, the PLL can 3.1 Overview be enabled or disabled in software, CLKO on RA6, apply external clock Devices in the PIC18F46J11 family incorporate a signal to RA7. different oscillator and microcontroller clock system EC External Clock Input mode, the PLL is than general purpose PIC18F devices. always disabled, CLKO on RA6, apply The PIC18F46J11 family has additional prescalers and external clock signal to RA7. postscalers, which have been added to accommodate HSPLL High-Speed Crystal/Resonator mode, a wide range of oscillator frequencies. Figure3-1 PLL can be enabled or disabled in provides an overview of the oscillator structure. software, crystal/resonator connected Other oscillator features used in PIC18 enhanced between RA6 and RA7. microcontrollers, such as the internal oscillator block HS High-Speed Crystal/Resonator mode, and clock switching, remain the same. They are PLL always disabled, crystal/resonator discussed later in this chapter. connected between RA6 and RA7. INTOSCPLLO Internal Oscillator mode, PLL can be 3.1.1 OSCILLATOR CONTROL enabled or disabled in software, CLKO The operation of the oscillator in PIC18F46J11 family on RA6, port function on RA7, the devices is controlled through three Configuration regis- internal oscillator block is used to derive ters and two control registers. Configuration registers, both the primary clock source and the CONFIG1L, CONFIG1H and CONFIG2L, select the postscaled internal clock. oscillator mode, PLL prescaler and CPU divider INTOSCPLL Internal Oscillator mode, PLL can be options. As Configuration bits, these are set when the enabled or disabled in software, port device is programmed and left in that configuration until function on RA6 and RA7, the internal the device is reprogrammed. oscillator block is used to derive both the primary clock source and the postscaled The OSCCON register (Register3-2) selects the Active internal clock. Clock mode; it is primarily used in controlling clock INTOSCO Internal Oscillator mode, PLL is always switching in power-managed modes. Its use is disabled, CLKO on RA6, port function on discussed in Section3.3.1 “Oscillator Control RA7, the output of the INTOSC Register”. postscaler serves as both the postscaled The OSCTUNE register (Register3-1) is used to trim the internal clock and the primary clock INTOSC frequency source and select the low-frequency source. clock source that drives several special features. The INTOSC Internal Oscillator mode, PLL is always OSCTUNE register is also used to activate or disable the disabled, port function on RA6 and RA7, Phase Locked Loop (PLL). Its use is described in the output of the INTOSC postscaler Section3.2.5.1 “OSCTUNE Register”. serves as both the postscaled internal clock and the primary clock source. 3.2 Oscillator Types PIC18F46J11 family devices can be operated in eight distinct oscillator modes. Users can program the FOSC<2:0> Configuration bits to select one of the modes listed in Table3-1. For oscillator modes which produce a clock output (CLKO) on pin RA6, the output frequency will be one fourth of the peripheral clock frequency. The clock output stops when in Sleep mode, but will continue during Idle mode (see Figure3-1).  2011 Microchip Technology Inc. DS39932D-page 37

PIC18F46J11 FAMILY 3.2.1 OSCILLATOR MODES Figure3-1 helps in understanding the oscillator structure of the PIC18F46J11 family of devices. FIGURE 3-1: PIC18F46J11 FAMILY CLOCK DIAGRAM PIC18F46J11 Family Primary Oscillator HS, EC OSC2 Sleep OSCTUNE<7> HSPLL, ECPLL, INTPLL 4 x PLL(1) OSC1 Secondary Oscillator T1OSC X Peripherals T1OSO U M T1OSCEN Enable T1OSI Oscillator OSCCON<6:4> OSCCON<6:4> 8 MHz Internal Oscillator CPU 111 4 MHz Internal 110 Oscillator 2 MHz IDLEN 101 Block er 1 MHz Clock al 100 X Control S8o MurHcze (IN8 TMOHSzC) Postsc 520500 kkHHzz 001110 MU FOSC<2:0> OSCCON< 1:0> 125 kHz 001 Clock Source Option 1 31 kHz 000 for Other Modules 0 INTRC OSCTUNE<7> Source 31 kHz (INTRC) WDT, PWRT, FSCM and Two-Speed Start-up Note 1: 8 MHz and 4 MHz are valid INTOSC postscaler settings for the PLL. Selecting other INTOSC postscaler settings will operate the PLL outside of the specification. DS39932D-page 38  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 3.2.2 CRYSTAL OSCILLATOR/CERAMIC TABLE 3-3: CAPACITOR SELECTION FOR RESONATORS CRYSTAL OSCILLATOR In HS and HSPLL Oscillator modes, a crystal or Typical Capacitor Values ceramic resonator is connected to the OSC1 and Crystal Tested: Osc Type OSC2 pins to establish oscillation. Figure3-2 displays Freq C1 C2 the pin connections. The oscillator design requires the use of a parallel HS 4 MHz 27 pF 27 pF resonant crystal. 8 MHz 22 pF 22 pF Note: Use of a series resonant crystal may give 20 MHz 15 pF 15 pF a frequency out of the crystal manufac- Capacitor values are for design guidance only. turer’s specifications. These capacitors were tested with the crystals listed below for basic start-up and operation. These values FIGURE 3-2: CRYSTAL/CERAMIC are not optimized. RESONATOR OPERATION Different capacitor values may be required to produce (HS OR HSPLL acceptable oscillator operation. The user should test CONFIGURATION) the performance of the oscillator over the expected C1(1) OSC1 VDD and temperature range for the application. See the notes following this table for additional To information. Internal XTAL Logic RF Crystals Used: Sleep 4 MHz RS(2) C2(1) OSC2 PIC18F46J11 8 MHz 20 MHz Note 1: See Table3-2 and Table3-3 for initial values of C1 and C2. 2: Rs may be required to avoid overdriving Note1: Higher capacitance not only increases crystals with low drive level specification. the stability of oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own TABLE 3-2: CAPACITOR SELECTION FOR characteristics, the user should consult CERAMIC RESONATORS the resonator/crystal manufacturer for Typical Capacitor Values Used: appropriate values of external components. Mode Freq OSC1 OSC2 3: Rs may be required to avoid overdriving HS 8.0 MHz 27 pF 27 pF crystals with low drive level specification. 16.0 MHz 22 pF 22 pF 4: Always verify oscillator performance over Capacitor values are for design guidance only. the VDD and temperature range that is These capacitors were tested with the resonators expected for the application. listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table3-3 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz  2011 Microchip Technology Inc. DS39932D-page 39

PIC18F46J11 FAMILY 3.2.3 EXTERNAL CLOCK INPUT 3.2.5 INTERNAL OSCILLATOR BLOCK The EC and ECPLL Oscillator modes require an The PIC18F46J11 family devices include an internal external clock source to be connected to the OSC1 pin. oscillator block which generates two different clock There is no oscillator start-up time required after a signals; either can be used as the microcontroller’s Power-on Reset (POR) or after an exit from Sleep clock source. The internal oscillator may eliminate the mode. need for external oscillator circuits on the OSC1 and/or OSC2 pins. In the EC Oscillator mode, the oscillator frequency divided-by-4 is available on the OSC2 pin. In the The main output (INTOSC) is an 8 MHz clock source ECPLL Oscillator mode, the PLL output divided-by-4 is which can be used to directly drive the device clock. It available on the OSC2 pin. This signal may be used for also drives the INTOSC postscaler, which can provide test purposes or to synchronize other logic. Figure3-3 a range of clock frequencies from 31 kHz to 8 MHz. displays the pin connections for the EC Oscillator Additionally, the INTOSC may be used in conjunction mode. with the PLL to generate clock frequencies up to 32MHz. FIGURE 3-3: EXTERNAL CLOCK INPUT The other clock source is the internal RC oscillator OPERATION (EC AND (INTRC), which provides a nominal 31 kHz output. ECPLL CONFIGURATION) INTRC is enabled if it is selected as the device clock source. It is also enabled automatically when any of the Clock from OSC1/CLKI following are enabled: Ext. System PIC18F46J11 • Power-up Timer FOSC/4 OSC2/CLKO • Fail-Safe Clock Monitor • Watchdog Timer • Two-Speed Start-up 3.2.4 PLL FREQUENCY MULTIPLIER These features are discussed in more detail in A Phase Locked Loop (PLL) circuit is provided as an Section26.0 “Special Features of the CPU”. option for users who want to use a lower frequency The clock source frequency (INTOSC direct, INTRC oscillator circuit, or to clock the device up to its highest direct or INTOSC postscaler) is selected by configuring rated frequency from a crystal oscillator. This may be the IRCF bits of the OSCCON register (page44). useful for customers who are concerned with EMI due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator. DS39932D-page 40  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 3.2.5.1 OSCTUNE Register 3.2.5.3 Compensating for INTOSC Drift The internal oscillator’s output has been calibrated at It is possible to adjust the INTOSC frequency by the factory but can be adjusted in the user’s applica- modifying the value in the OSCTUNE register. This has tion. This is done by writing to the OSCTUNE register no effect on the INTRC clock source frequency. (Register3-1). Tuning the INTOSC source requires knowing when to When the OSCTUNE register is modified, the INTOSC make the adjustment, in which direction it should be frequency will begin shifting to the new frequency. made, and in some cases, how large a change is Code execution continues during this shift. There is no needed. When using the EUSART, for example, an indication that the shift has completed. adjustment may be required when it begins to generate framing errors or receives data with errors while in The OSCTUNE register also contains the INTSRC bit. Asynchronous mode. Framing errors indicate that the The INTSRC bit allows users to select which internal device clock frequency is too high; to adjust for this, oscillator provides the clock source when the 31kHz decrement the value in OSCTUNE to reduce the clock frequency option is selected. This is covered in more frequency. On the other hand, errors in data may sug- detail in Section3.3.1 “Oscillator Control Register”. gest that the clock speed is too low; to compensate, The 4x Phase Locked Loop (PLL) can be used with increment OSCTUNE to increase the clock frequency. the internal oscillator block to produce faster device It is also possible to verify device clock speed against clock speeds than are normally possible with the a reference clock. Two timers may be used: one timer internal oscillator sources. When enabled, the PLL is clocked by the peripheral clock, while the other is produces a clock speed up to 32 MHz. clocked by a fixed reference source, such as the PLL operation is controlled through software. The Timer1 oscillator. Both timers are cleared, but the timer control bit, PLLEN (OSCTUNE<6>), is used to enable clocked by the reference generates interrupts. When or disable its operation. The PLL is available only to an interrupt occurs, the internally clocked timer is read INTOSC when the device is configured to use one of and both timers are cleared. If the internally clocked the INTPLL modes as the primary clock source, timer value is greater than expected, then the internal SCS<1:0> = 00 (FOSC<2:0> = 011 or 010). oscillator block is running too fast. To adjust for this, Additionally, the PLL will only function when the decrement the OSCTUNE register. selected output frequency is either 4 MHz or 8 MHz Finally, an ECCP module can use free-running Timer1 (OSCCON<6:4> = 111 or 110). (or Timer3), clocked by the internal oscillator block and When configured for one of the PLL enabled modes, set- an external event with a known period (i.e., AC power ting the PLLEN bit does not immediately switch the frequency). The time of the first event is captured in the device clock to the PLL output. The PLL requires up to CCPRxH:CCPRxL registers and is recorded for use two milliseconds to start-up and lock, during which time, later. When the second event causes a capture, the the device continues to be clocked. Once the PLL output time of the first event is subtracted from the time of the is ready, the microcontroller core will automatically second event. Since the period of the external event is switch to the PLL derived frequency. known, the time difference between events can be calculated. 3.2.5.2 Internal Oscillator Output Frequency and Drift If the measured time is greater than the calculated time, the internal oscillator block is running too fast; to The internal oscillator block is calibrated at the factory compensate, decrement the OSCTUNE register. If the to produce an INTOSC output frequency of 8.0MHz. measured time is less than the calculated time, the inter- However, this frequency may drift as VDD or tempera- nal oscillator block is running too slow; to compensate, ture changes, which can affect the controller operation increment the OSCTUNE register. in a variety of ways. The low-frequency INTRC oscillator operates indepen- dently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa.  2011 Microchip Technology Inc. DS39932D-page 41

PIC18F46J11 FAMILY REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER (ACCESS F9Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock derived from 8MHz INTOSC source (divide-by-256 enabled) 0 = 31kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN: Frequency Multiplier Enable bit 1 = PLL enabled 0 = PLL disabled bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 • • • 000001 000000 = Center frequency; oscillator module is running at the calibrated frequency 111111 • • • 100000 = Minimum frequency 3.3 Clock Sources and Oscillator The Secondary Oscillators are external sources that Switching are not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the Like previous PIC18 enhanced devices, the controller is placed in a power-managed mode. PIC18F46J11 family includes a feature that allows the PIC18F46J11 family devices offer the Timer1 oscillator device clock source to be switched from the main as a secondary oscillator. This oscillator, in all oscillator to an alternate, low-frequency clock source. power-managed modes, is often the time base for PIC18F46J11 family devices offer two alternate clock functions such as a Real-Time Clock (RTC). Most often, sources. When an alternate clock source is enabled, a 32.768kHz watch crystal is connected between the the various power-managed operating modes are RC0/T1OSO/T1CKI/RP11 and RC1/T1OSI/RP12 pins. available. Like the HS Oscillator mode circuits, loading capacitors Essentially, there are three clock sources for these are also connected from each pin to ground. The Timer1 devices: oscillator is discussed in more detail in Section13.5 • Primary Oscillators “Timer1 Oscillator”. • Secondary Oscillators In addition to being a primary clock source, the • Internal Oscillator Block postscaled internal clock is available as a power-managed mode clock source. The INTRC The Primary Oscillators include the External Crystal source is also used as the clock source for several and Resonator modes, the External Clock modes and special features, such as the WDT and Fail-Safe Clock the internal oscillator block. The particular mode is Monitor (FSCM). defined by the FOSC<2:0> Configuration bits. The details of these modes are covered earlier in this chapter. DS39932D-page 42  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 3.3.1 OSCILLATOR CONTROL REGISTER The IDLEN bit determines if the device goes into Sleep mode, or one of the Idle modes, when the SLEEP The OSCCON register (Register3-2) controls several instruction is executed. aspects of the device clock’s operation, both in full-power operation and in power-managed modes. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section4.0 The System Clock Select bits, SCS<1:0>, select the “Low-Power Modes”. clock source. The available clock sources are the primary clock (defined by the FOSC<2:0> Configura- Note1: The Timer1 crystal driver is enabled by tion bits), the secondary clock (Timer1 oscillator) and setting the T1OSCEN bit in the Timer1 the postscaled internal clock.The clock source changes Control register (T1CON<3>). If the immediately, after one or more of the bits is written to, Timer1 oscillator is not enabled, then any following a brief clock transition interval. The SCS bits attempt to select the Timer1 clock source are cleared on all forms of Reset. will be ignored, unless the CONFIG2L The Internal Oscillator Frequency Select bits, register’s T1DIG bit is set. IRCF<2:0>, select the frequency output provided on the 2: If Timer1 is driving a crystal, it is recom- postscaled internal clock line. The choices are the mended that the Timer1 oscillator be INTRC source, the INTOSC source (8MHz) or one of operating and stable prior to switching to the frequencies derived from the INTOSC postscaler it as the clock source; otherwise, a very (31kHz to 4MHz). If the postscaled internal clock is long delay may occur while the Timer1 supplying the device clock, changing the states of these oscillator starts. bits will have an immediate change on the internal oscil- lator’s output. On device Resets, the default output 3.3.2 OSCILLATOR TRANSITIONS frequency of the INTOSC postscaler is set at 4MHz. PIC18F46J11 family devices contain circuitry to When an output frequency of 31kHz is selected prevent clock “glitches” when switching between clock (IRCF<2:0> = 000), users may choose the internal sources. A short pause in the device clock occurs dur- oscillator, which acts as the source. This is done with ing the clock switch. The length of this pause is the sum the INTSRC bit in the OSCTUNE register of two cycles of the old clock source and three to four (OSCTUNE<7>). Setting this bit selects INTOSC as a cycles of the new clock source. This formula assumes 31.25kHz clock source by enabling the divide-by-256 that the new clock source is stable. output of the INTOSC postscaler. Clearing INTSRC Clock transitions are discussed in more detail in selects INTRC (nominally 31kHz) as the clock source. Section4.1.2 “Entering Power-Managed Modes”. This option allows users to select the tunable and more precise INTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the WDT and the FSCM. The OSTS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer (OST) has timed out and the primary clock is providing the device clock in primary clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable.  2011 Microchip Technology Inc. DS39932D-page 43

PIC18F46J11 FAMILY REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER (ACCESS FD3h) R/W-0 R/W-1 R/W-1 R/W-0 R-1(1) U-1 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS — SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits(4) 111 = 8MHz (INTOSC drives clock directly) 110 = 4MHz(2) 101 = 2MHz 100 = 1MHz 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31kHz (from either INTOSC/256 or INTRC directly)(3) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready bit 2 Unimplemented: Read as ‘1’ bit 1-0 SCS<1:0>: System Clock Select bits 11 = Postscaled internal clock (INTRC/INTOSC derived) 10 = Reserved 01 = Timer1 oscillator 00 = Primary clock source (INTOSC postscaler output when FOSC<2:0> = 001 or 000) 00 = Primary clock source (CPU divider output for other values of FOSC<2:0>) Note 1: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 2: Default output frequency of INTOSC on Reset (4 MHz). 3: Source selected by the INTSRC bit (OSCTUNE<7>). 4: When using INTOSC to drive the 4x PLL, select 8MHz or 4MHz only to avoid operating the 4x PLL outside of specification. DS39932D-page 44  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 3.4 Reference Clock Output The ROSSLP and ROSEL bits (REFOCON<5:4>) control the availability of the reference output during In addition to the peripheral clock/4 output in certain Sleep mode. The ROSEL bit determines if the oscillator oscillator modes, the device clock in the PIC18F46J11 is on OSC1 and OSC2, or the current system clock family can also be configured to provide a reference source is used for the reference clock output. The clock output signal to a port pin. This feature is avail- ROSSLP bit determines if the reference source is able in all oscillator configurations and allows the user available on RB2 when the device is in Sleep mode. to select a greater range of clock submultiples to drive To use the reference clock output in Sleep mode, both external devices in the application. the ROSSLP and ROSEL bits must be set. The device This reference clock output is controlled by the clock must also be configured for an EC or HS mode; REFOCON register (Register3-3). Setting the ROON otherwise, the oscillator on OSC1 and OSC2 will be bit (REFOCON<7>) makes the clock signal available powered down when the device enters Sleep mode. on the REFO (RB2) pin. The RODIV<3:0> bits enable Clearing the ROSEL bit allows the reference output the selection of 16 different clock divider options. frequency to change as the system clock changes during any clock switches. REGISTER 3-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (BANKED F3Dh) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator enabled on REFO pin 0 = Reference oscillator disabled bit 6 Unimplemented: Read as ‘0’ bit 5 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 4 ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator used as the base clock(1) 0 = System clock used as the base clock; base clock reflects any clock switching of the device bit 3-0 RODIV<3:0>: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value Note 1: The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode.  2011 Microchip Technology Inc. DS39932D-page 45

PIC18F46J11 FAMILY 3.5 Effects of Power-Managed Modes 3.6 Power-up Delays on Various Clock Sources Power-up delays are controlled by two timers so that no When the PRI_IDLE mode is selected, the designated external Reset circuitry is required for most applica- primary oscillator continues to run without tions. The delays ensure that the device is kept in interruption.In secondary clock modes (SEC_RUN Reset until the device power supply is stable under and SEC_IDLE), the Timer1 oscillator is operating and normal circumstances and the primary clock is operat- providing the device clock. The Timer1 oscillator may ing and stable. For additional information on power-up also run in all power-managed modes if required to delays, see Section5.6 “Power-up Timer (PWRT)”. clock Timer1 or Timer3. The first timer is the Power-up Timer (PWRT), which In internal oscillator modes (RC_RUN and RC_IDLE), provides a fixed delay on power-up (parameter 33, the internal oscillator block provides the device clock Table29-15). source. The 31kHz INTRC output can be used directly The second timer is the Oscillator Start-up Timer to provide the clock and may be enabled to support (OST), intended to keep the chip in Reset until the various special features regardless of the crystal oscillator is stable (HS mode). The OST does power-managed mode (see Section26.2 “Watchdog this by counting 1024 oscillator cycles before allowing Timer (WDT)”, Section26.4 “Two-Speed Start-up” the oscillator to clock the device. and Section26.5 “Fail-Safe Clock Monitor” for more There is a delay of interval, TCSD (parameter 38, information on WDT, FSCM and Two-Speed Start-up). Table29-15), following POR, while the controller The INTOSC output at 8MHz may be used directly to becomes ready to execute instructions. This delay runs clock the device or may be divided down by the concurrently with any other delays. This may be the only postscaler. The INTOSC output is disabled if the clock delay that occurs when any of the internal oscillator or is provided directly from the INTRC output. EC modes are used as the primary clock source. If Sleep mode is selected, all clock sources, which are no longer required, are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents) outside of Deep Sleep mode. Enabling any on-chip feature that will operate during Sleep mode increases the current consumed during Sleep mode. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support an RTC. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PMP, INTx pins, etc.). Peripherals that may add significant current consumption are listed in Section29.2 “DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial)”. DS39932D-page 46  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 4.0 LOW-POWER MODES The IDLEN bit (OSCCON<7>) controls CPU clocking and the SCS<1:0> bits (OSCCON<1:0>) select the The PIC18F46J11 family devices can manage power clock source. The individual modes, bit settings, clock consumption through clocking to the CPU and the sources and affected modules are summarized in peripherals. In general, reducing the clock frequency Table4-1. and the amount of circuitry being clocked reduces power consumption. 4.1.1 CLOCK SOURCES For managing power in an application, the primary The SCS<1:0> bits allow the selection of one of three modes of operation are: clock sources for power-managed modes. They are: • Run Mode • Primary clock source – Defined by the • Idle Mode FOSC<2:0> Configuration bits • Sleep Mode • Timer1 clock – Provided by the secondary • Deep Sleep Mode oscillator • Postscaled internal clock – Derived from the Additionally, there is an Ultra Low-Power Wake-up internal oscillator block (ULPWU) mode for generating an interrupt-on-change on RA0. 4.1.2 ENTERING POWER-MANAGED These modes define which portions of the device are MODES clocked and at what speed. Switching from one clock source to another begins by • The Run and Idle modes can use any of the three loading the OSCCON register. The SCS<1:0> bits available clock sources (primary, secondary or select the clock source. internal oscillator blocks). Changing these bits causes an immediate switch to the • The Sleep mode does not use a clock source. new clock source, assuming that it is running. The The ULPWU mode on RA0 allows a slow falling voltage switch also may be subject to clock transition delays. to generate an interrupt-on-change on RA0 without These delays are discussed in Section4.1.3 “Clock excess current consumption. See Section4.7 “Ultra Transitions and Status Indicators” and subsequent Low-Power Wake-up”. sections. The power-managed modes include several Entry to the power-managed Idle or Sleep modes is power-saving features offered on previous PIC® triggered by the execution of a SLEEP instruction. The devices, such as clock switching, ULPWU and Sleep actual mode that results depends on the status of the mode. In addition, the PIC18F46J11 family devices add IDLEN bit. a new power-managed Deep Sleep mode. Depending on the current mode and the mode being switched to, a change to a power-managed mode does 4.1 Selecting Power-Managed Modes not always require setting all of these bits. Many transi- tions may be done by changing the oscillator select Selecting a power-managed mode requires these bits, the IDLEN bit or the DSEN bit prior to issuing a decisions: SLEEP instruction. • Will the CPU be clocked? If the IDLEN and DSEN bits are already configured • If so, which clock source will be used? correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode.  2011 Microchip Technology Inc. DS39932D-page 47

PIC18F46J11 FAMILY TABLE 4-1: LOW-POWER MODES DSCONH<7> OSCCON<7,1:0> Module Clocking Mode Available Clock and Oscillator Source DSEN(1) IDLEN(1) SCS<1:0> CPU Peripherals Sleep 0 0 N/A Off Off Timer1 oscillator and/or RTCC optionally enabled Deep 1 0 N/A Off — RTCC can run uninterrupted using the Timer1 or Sleep(2) internal low-power RC oscillator PRI_RUN 0 N/A 00 Clocked Clocked The normal, full-power execution mode. Primary clock source (defined by FOSC<2:0>) SEC_RUN 0 N/A 01 Clocked Clocked Secondary – Timer1 oscillator RC_RUN 0 N/A 11 Clocked Clocked Postscaled internal clock PRI_IDLE 0 1 00 Off Clocked Primary clock source (defined by FOSC<2:0>) SEC_IDLE 0 1 01 Off Clocked Secondary – Timer1 oscillator RC_IDLE 0 1 11 Off Clocked Postscaled internal clock Note 1: IDLEN and DSEN reflect their values when the SLEEP instruction is executed. 2: Deep Sleep entirely shuts off the voltage regulator for ultra low-power consumption. See Section4.6 “Deep Sleep Mode” for more information. 4.1.3 CLOCK TRANSITIONS AND STATUS 4.2.1 PRI_RUN MODE INDICATORS The PRI_RUN mode is the normal, full-power execu- The length of the transition between clock sources is tion mode of the microcontroller. This is also the default the sum of two cycles of the old clock source and three mode upon a device Reset unless Two-Speed Start-up to four cycles of the new clock source. This formula is enabled (see Section26.4 “Two-Speed Start-up” assumes that the new clock source is stable. for details). In this mode, the OSTS bit is set (see Section3.3.1 “Oscillator Control Register”). Two bits indicate the current clock source and its status: OSTS (OSCCON<3>) and T1RUN 4.2.2 SEC_RUN MODE (T1CON<6>). In general, only one of these bits will be set in a given power-managed mode. When the OSTS The SEC_RUN mode is the compatible mode to the bit is set, the primary clock would be providing the “clock switching” feature offered in other PIC18 device clock. When the T1RUN bit is set, the Timer1 devices. In this mode, the CPU and peripherals are oscillator would be providing the clock. If neither of clocked from the Timer1 oscillator. This gives users the these bits is set, INTRC would be clocking the device. option of low-power consumption while still using a high-accuracy clock source. Note: Executing a SLEEP instruction does not SEC_RUN mode is entered by setting the SCS<1:0> necessarily place the device into Sleep bits to ‘01’. The device clock source is switched to the mode. It acts as the trigger to place the Timer1 oscillator (see Figure4-1), the primary controller into either the Sleep or Deep oscillator is shut down, the T1RUN bit (T1CON<6>) is Sleep mode, or one of the Idle modes, set and the OSTS bit is cleared. depending on the setting of the IDLEN bit. 4.1.4 MULTIPLE SLEEP COMMANDS Note: The Timer1 oscillator should already be running prior to entering SEC_RUN The power-managed mode that is invoked with the mode. If the T1OSCEN bit is not set when SLEEP instruction is determined by the setting of the the SCS<1:0> bits are set to ‘01’, entry to IDLEN and DSEN bits at the time the instruction is exe- SEC_RUN mode will not occur. If the cuted. If another SLEEP instruction is executed, the Timer1 oscillator is enabled, but not yet device will enter the power-managed mode specified running, device clocks will be delayed until by IDLEN and DSEN at that time. If IDLEN or DSEN the oscillator has started. In such situa- have changed, the device will enter the new tions, initial oscillator operation is far from power-managed mode specified by the new setting. stable and unpredictable operation may result. 4.2 Run Modes In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. DS39932D-page 48  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY On transitions from SEC_RUN mode to PRI_RUN Figure4-2). When the clock switch is complete, the mode, the peripherals and CPU continue to be clocked T1RUN bit is cleared, the OSTS bit is set and the from the Timer1 oscillator while the primary clock is primary clock would be providing the clock. The IDLEN started. When the primary clock becomes ready, a and SCS bits are not affected by the wake-up; the clock switch back to the primary clock occurs (see Timer1 oscillator continues to run. FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> Bits Changed OSTS Bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale.  2011 Microchip Technology Inc. DS39932D-page 49

PIC18F46J11 FAMILY 4.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC In RC_RUN mode, the CPU and peripherals are block while the primary clock is started. When the clocked from the internal oscillator; the primary clock is primary clock becomes ready, a clock switch to the shut down. This mode provides the best power conser- primary clock occurs (see Figure4-4). When the clock vation of all the Run modes while still executing code. switch is complete, the OSTS bit is set and the primary It works well for user applications, which are not highly clock is providing the device clock. The IDLEN and timing-sensitive or do not require high-speed clocks at SCS bits are not affected by the switch. The INTRC all times. clock source will continue to run if either the WDT or the This mode is entered by setting the SCS<1:0> bits FSCM is enabled. (OSCCON<1:0>) to ‘11’. When the clock source is switched to the internal oscillator block (see Figure4-3), the primary oscillator is shut down and the OSTS bit is cleared. FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> Bits Changed OSTS Bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS39932D-page 50  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 4.3 Sleep Mode When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked The power-managed Sleep mode is identical to the until the clock source selected by the SCS<1:0> bits legacy Sleep mode offered in all other PIC devices. It is becomes ready (see Figure4-6), or it will be clocked entered by clearing the IDLEN bit (the default state on from the internal oscillator if either the Two-Speed device Reset) and executing the SLEEP instruction. Start-up or the FSCM is enabled (see Section26.0 This shuts down the selected oscillator (Figure4-5). All “Special Features of the CPU”). In either case, the clock source status bits are cleared. OSTS bit is set when the primary clock is providing the Entering the Sleep mode from any other mode does not device clocks. The IDLEN and SCS bits are not require a clock switch. This is because no clocks are affected by the wake-up. needed once the controller has entered Sleep mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS Bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale.  2011 Microchip Technology Inc. DS39932D-page 51

PIC18F46J11 FAMILY 4.4 Idle Modes execution starts. This is required to allow the CPU to become ready to execute instructions. After the The Idle modes allow the controller’s CPU to be wake-up, the OSTS bit remains set. The IDLEN and selectively shut down while the peripherals continue to SCS bits are not affected by the wake-up (see operate. Selecting a particular Idle mode allows users Figure4-8). to further manage power consumption. 4.4.2 SEC_IDLE MODE If the IDLEN bit is set to ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock In SEC_IDLE mode, the CPU is disabled but the source selected using the SCS<1:0> bits; however, the peripherals continue to be clocked from the Timer1 CPU will not be clocked. The clock source status bits are oscillator. This mode is entered from SEC_RUN by set- not affected. Setting IDLEN and executing a SLEEP ting the IDLEN bit and executing a SLEEP instruction. If instruction provides a quick method of switching from a the device is in another Run mode, set IDLEN first, then given Run mode to its corresponding Idle mode. set SCS<1:0> to ‘01’ and execute SLEEP. When the If the WDT is selected, the INTRC source will continue clock source is switched to the Timer1 oscillator, the to operate. If the Timer1 oscillator is enabled, it will also primary oscillator is shut down, the OSTS bit is cleared continue to run. and the T1RUN bit is set. Since the CPU is not executing instructions, the only When a wake event occurs, the peripherals continue to exits from any of the Idle modes are by interrupt, WDT be clocked from the Timer1 oscillator. After the wake time-out or a Reset. When the CPU begins executing event, the CPU begins executing code being clocked code, it resumes with the same clock source for the by the Timer1 oscillator. The IDLEN and SCS bits are current Idle mode. For example, when waking from not affected by the wake-up; the Timer1 oscillator con- RC_IDLE mode, the internal oscillator block will clock tinues to run (see Figure4-8). the CPU and peripherals (in other words, RC_RUN Note: The Timer1 oscillator should already be mode). The IDLEN and SCS bits are not affected by the running prior to entering SEC_IDLE wake-up. mode. If the T1OSCEN bit is not set when While in any Idle or Sleep mode, a WDT time-out will the SLEEP instruction is executed, the result in a WDT wake-up to the Run mode currently SLEEP instruction will be ignored and specified by the SCS<1:0> bits. entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not 4.4.1 PRI_IDLE MODE yet running, peripheral clocks will be This mode is unique among the three low-power Idle delayed until the oscillator has started. In modes, in that it does not disable the primary device such situations, initial oscillator operation clock. For timing-sensitive applications, this allows for is far from stable and unpredictable oper- the fastest resumption of device operation with its more ation may result. accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN first, then set the SCS bits to ‘00’ and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC<1:0> Configuration bits. The OSTS bit remains set (see Figure4-7). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, TCSD, is required between the wake event and when code DS39932D-page 52  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 CPU Clock Peripheral Clock Program PC Counter Wake Event  2011 Microchip Technology Inc. DS39932D-page 53

PIC18F46J11 FAMILY 4.4.3 RC_IDLE MODE If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the In RC_IDLE mode, the CPU is disabled but the power-managed mode (see Section4.2 “Run peripherals continue to be clocked from the internal Modes” and Section4.3 “Sleep Mode”). If the device oscillator block. This mode allows for controllable is executing code (all Run modes), the time-out will power conservation during Idle periods. result in a WDT Reset (see Section26.2 “Watchdog From RC_RUN, this mode is entered by setting the Timer (WDT)”). IDLEN bit and executing a SLEEP instruction. If the The WDT and postscaler are cleared by one of the device is in another Run mode, first set IDLEN, then following events: clear the SCS bits and execute SLEEP. When the clock source is switched to the INTOSC block, the primary • Executing a SLEEP or CLRWDT instruction oscillator is shut down and the OSTS bit is cleared. • The loss of a currently selected clock source (if When a wake event occurs, the peripherals continue to the FSCM is enabled) be clocked from the internal oscillator block. After the 4.5.3 EXIT BY RESET wake event, the CPU begins executing code being clocked by the INTRC. The IDLEN and SCS bits are not Exiting an Idle or Sleep mode by Reset automatically affected by the wake-up. The INTRC source will con- forces the device to run from the INTRC. tinue to run if either the WDT or the FSCM is enabled. 4.5.4 EXIT WITHOUT AN OSCILLATOR 4.5 Exiting Idle and Sleep Modes START-UP DELAY Certain exits from power-managed modes do not An exit from Sleep mode, or any of the Idle modes, is invoke the OST at all. There are two cases: triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits • PRI_IDLE mode (where the primary clock source from power-managed modes. The clocking subsystem is not stopped) and the primary clock source is actions are discussed in each of the power-managed the EC mode modes sections (see Section4.2 “Run Modes”, • PRI_IDLE mode and the primary clock source is Section4.3 “Sleep Mode” and Section4.4 “Idle the ECPLL mode Modes”). In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already 4.5.1 EXIT BY INTERRUPT running (PRI_IDLE), or normally does not require an Any of the available interrupt sources can cause the oscillator start-up delay (EC). device to exit from an Idle mode, or the Sleep mode, to a Run mode. To enable this functionality, an interrupt 4.6 Deep Sleep Mode source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is Deep Sleep mode brings the device into its lowest initiated when the corresponding interrupt flag bit is set. power consumption state without requiring the use of external switches to remove power from the device. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the During deep sleep, the on-chip VDDCORE voltage regulator is powered down, effectively disconnecting GIE/GIEH bit (INTCON<7>) is set. Otherwise, code power to the core logic of the microcontroller. execution continues or resumes without branching (see Section9.0 “Interrupts”). Note: Since Deep Sleep mode powers down the microcontroller by turning off the on-chip 4.5.2 EXIT BY WDT TIME-OUT VDDCORE voltage regulator, Deep Sleep A WDT time-out will cause different actions depending capability is available only on PIC18FXXJ on which power-managed mode the device is in when members in the device family. The on-chip the time-out occurs. voltage regulator is not available in PIC18LFXXJ members of the device family, and therefore, they do not support Deep Sleep. DS39932D-page 54  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY On devices that support it, the Deep Sleep mode is 4.6.2 I/O PINS DURING DEEP SLEEP entered by: During Deep Sleep, the general purpose I/O pins will • Setting the REGSLP (WDTCON<7>) bit (the retain their previous states. default state on device Reset) Pins that are configured as inputs (TRIS bit set) prior to • Clearing the IDLEN bit (the default state on device entry into Deep Sleep will remain high-impedance Reset) during Deep Sleep. • Setting the DSEN bit (DSCONH<7>) Pins that are configured as outputs (TRIS bit clear) • Executing the SLEEP instruction immediately after prior to entry into Deep Sleep will remain as output pins setting DSEN (no delay in between) during Deep Sleep. While in this mode, they will drive In order to minimize the possibility of inadvertently enter- the output level determined by their corresponding LAT ing Deep Sleep, the DSEN bit is cleared in hardware bit at the time of entry into Deep Sleep. two instruction cycles after having been set. Therefore, When the device wakes back up, the I/O pin behavior in order to enter Deep Sleep, the SLEEP instruction must depends on the type of wake-up source. be executed in the immediate instruction cycle after set- If the device wakes back up by an RTCC alarm, INT0 ting DSEN. If DSEN is not set when Sleep is executed, interrupt, DSWDT or ULPWU event, all I/O pins will the device will enter conventional Sleep mode instead. continue to maintain their previous states, even after the During Deep Sleep, the core logic circuitry of the device has finished the POR sequence and is executing microcontroller is powered down to reduce leakage application code again. Pins configured as inputs during current. Therefore, most peripherals and functions of Deep Sleep will remain high-impedance, and pins con- the microcontroller become unavailable during Deep figured as outputs will continue to drive their previous Sleep. However, a few specific peripherals and func- value. tions are powered directly from the VDD supply rail of After waking up, the TRIS and LAT registers will be the microcontroller, and therefore, can continue to reset, but the I/O pins will still maintain their previous function in Deep Sleep. states. If firmware modifies the TRIS and LAT values for Entering Deep Sleep mode clears the DSWAKEL regis- the I/O pins, they will not immediately go to the newly ter. However, if the Real-Time Clock and Calendar configured states. Once the firmware clears the (RTCC) is enabled prior to entering Deep Sleep, it will RELEASE bit (DSCONL<0>), the I/O pins will be continue to operate uninterrupted. “released”. This causes the I/O pins to take the states The device has dedicated low-power Brown-out Reset configured by their respective TRIS and LAT bit values. (DSBOR) and Watchdog Timer Reset (DSWDT) for If the Deep Sleep BOR (DSBOR) circuit is enabled, and monitoring voltage and time-out events in Deep Sleep. VDD drops below the DSBOR and VDD rail POR thresh- The DSBOR and DSWDT are independent of the stan- olds, the I/O pins will be immediately released similar to dard BOR and WDT used with other power-managed clearing the RELEASE bit. All previous state informa- modes (Run, Idle and Sleep). tion will be lost, including the general purpose DSGPR0 When a wake event occurs in Deep Sleep mode (by and DSGPR1 contents. See Section4.6.5 “Deep MCLR Reset, RTCC alarm, INT0 interrupt, ULPWU or Sleep Brown Out Reset (DSBOR)” for additional DSWDT), the device will exit Deep Sleep mode and details about this scenario. perform a Power-on Reset (POR). When the device is If a MCLR Reset event occurs during Deep Sleep, the I/O released from Reset, code execution will resume at the pins will also be released automatically, but in this case, device’s Reset vector. the DSGPR0 and DSGPR1 contents will remain valid. 4.6.1 PREPARING FOR DEEP SLEEP In all other Deep Sleep wake-up cases, application firmware needs to clear the RELEASE bit in order to Because VDDCORE could fall below the SRAM retention reconfigure the I/O pins. voltage while in Deep Sleep mode, SRAM data could be lost in Deep Sleep. Exiting Deep Sleep mode causes a POR; as a result, most Special Function Registers will reset to their default POR values. Applications needing to save a small amount of data throughout a Deep Sleep cycle can save the data to the general purpose DSGPR0 and DSGPR1 registers. The contents of these registers are preserved while the device is in Deep Sleep, and will remain valid throughout an entire Deep Sleep entry and wake-up sequence.  2011 Microchip Technology Inc. DS39932D-page 55

PIC18F46J11 FAMILY 4.6.3 DEEP SLEEP WAKE-UP SOURCES 4.6.4 DEEP SLEEP WATCHDOG TIMER (DSWDT) While in Deep Sleep mode, the device can be awakened by a MCLR, POR, RTCC, INT0 I/O pin interrupt, Deep Sleep has its own dedicated WDT (DSWDT) with DSWDT or ULPWU event. After waking, the device per- a postscaler for time-outs of 2.1 ms to 25.7 days, forms a POR. When the device is released from Reset, configurable through the bits, DSWDTPS<3:0> code execution will begin at the device’s Reset vector. (CONFIG3L<7:4>). The software can determine if the wake-up was caused The DSWDT can be clocked from either the INTRC or from an exit from Deep Sleep mode by reading the DS the T1OSC/T1CKI input. If the T1OSC/T1CKI source will bit (WDTCON<3>). If this bit is set, the POR was be used with a crystal, the T1OSCEN bit in the T1CON caused by a Deep Sleep exit. The DS bit must be register needs to be set prior to entering Deep Sleep. manually cleared by the software. The reference clock source is configured through the The software can determine the wake event source by DSWDTOSC bit (CONFIG3L<0>). reading the DSWAKEH and DSWAKEL registers. DSWDT is enabled through the DSWDTEN bit When the application firmware is done using the (CONFIG3L<3>). Entering Deep Sleep mode automati- DSWAKEH and DSWAKEL status registers, individual cally clears the DSWDT. See Section26.0 “Special bits do not need to be manually cleared before entering Features of the CPU” for more information. Deep Sleep again. When entering Deep Sleep mode, these registers are automatically cleared. 4.6.5 DEEP SLEEP BROWN OUT RESET (DSBOR) 4.6.3.1 Wake-up Event Considerations The Deep Sleep module contains a dedicated Deep Deep Sleep wake-up events are only monitored while Sleep BOR (DSBOR) circuit. This circuit may be the processor is fully in Deep Sleep mode. If a wake-up optionally enabled through the DSBOREN Configuration event occurs before Deep Sleep mode is entered, the bit (CONFIG3L<2>). event status will not be reflected in the DSWAKE regis- The DSBOR circuit monitors the VDD supply rail ters. If the wake-up source asserts prior to entering voltage. The behavior of the DSBOR circuit is Deep Sleep, the CPU may go to the interrupt vector (if described in Section5.4 “Brown-out Reset (BOR)”. the wake source has an interrupt bit and the interrupt is fully enabled), and may abort the Deep Sleep entry 4.6.6 RTCC PERIPHERAL AND DEEP sequence by executing past the SLEEP instruction. In SLEEP this case, a wake-up event handler should be placed after the SLEEP instruction to process the event and The RTCC can operate uninterrupted during Deep re-attempt entry into Deep Sleep if desired. Sleep mode. It can wake the device from Deep Sleep by configuring an alarm. When the device is in Deep Sleep with more than one wake-up source simultaneously enabled, only the first The RTCC clock source is configured with the RTCOSC wake-up source to assert will be detected and logged bit (CONFIG3L<1>). The available reference clock in the DSWAKEH/DSWAKEL status registers. sources are the INTRC and T1OSC/T1CKI. If the INTRC is used, the RTCC accuracy will directly depend on the INTRC tolerance. For more information on configuring the RTCC peripheral, see Section17.0 “Real-Time Clock and Calendar (RTCC)”. DS39932D-page 56  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 4.6.7 TYPICAL DEEP SLEEP SEQUENCE 4.6.8 DEEP SLEEP FAULT DETECTION This section gives the typical sequence for using the If during Deep Sleep the device is subjected to unusual Deep Sleep mode. Optional steps are indicated, and operating conditions, such as an Electrostatic Dis- additional information is given in notes at the end of the charge (ESD) event, it is possible that the internal procedure. circuit states used by the Deep Sleep module could 1. Enable DSWDT (optional).(1) become corrupted. If this were to happen, the device may exhibit unexpected behavior, such as a failure to 2. Configure DSWDT clock source (optional).(2) wake back up. 3. Enable DSBOR (optional).(1) In order to prevent this type of scenario from occurring, 4. Enable RTCC (optional).(3) the Deep Sleep module includes automatic 5. Configure the RTCC peripheral (optional).(3) self-monitoring capability. During Deep Sleep, critical 6. Configure the ULPWU peripheral (optional).(4) internal nodes are continuously monitored in order to 7. Enable the INT0 Interrupt (optional).(4) detect possible Fault conditions (which would not 8. Context save SRAM data by writing to the ordinarily occur). If a Fault condition is detected, the DSGPR0 and DSGPR1 registers (optional). circuitry will set the DSFLT status bit (DSWAKEL<7>) and automatically wake the microcontroller from Deep 9. Set the REGSLP bit (WDTCON<7>) and clear Sleep, causing a POR Reset. the IDLEN bit (OSCCON<7>). 10. If using an RTCC alarm for wake-up, wait until During Deep Sleep, the Fault detection circuitry is the RTCSYNC (RTCCFG<4>) bit is clear. always enabled and does not require any specific configuration prior to entering Deep Sleep. 11. Enter Deep Sleep mode by setting the DSEN bit (DSCONH<7>) and issuing a SLEEP instruction. These two instructions must be executed back to back. 12. Once a wake-up event occurs, the device will perform a POR reset sequence. Code execution resumes at the device’s Reset vector. 13. Determine if the device exited Deep Sleep by reading the Deep Sleep bit, DS (WDTCON<3>). This bit will be set if there was an exit from Deep Sleep mode. 14. Clear the Deep Sleep bit, DS (WDTCON<3>). 15. Determine the wake-up source by reading the DSWAKEH and DSWAKEL registers. 16. Determine if a DSBOR event occurred during Deep Sleep mode by reading the DSBOR bit (DSCONL<1>). 17. Read the DSGPR0 and DSGPR1 context save registers (optional). 18. Clear the RELEASE bit (DSCONL<0>). Note1: DSWDT and DSBOR are enabled through the devices’ Configuration bits. For more information, see Section26.1 “Configuration Bits”. 2: The DSWDT and RTCC clock sources are selected through the devices’ Con- figuration bits. For more information, see Section26.1 “Configuration Bits”. 3: For more information, see Section17.0 “Real-Time Clock and Calendar (RTCC)”. 4: For more information on configuring this peripheral, see Section4.7 “Ultra Low-Power Wake-up”.  2011 Microchip Technology Inc. DS39932D-page 57

PIC18F46J11 FAMILY 4.6.9 DEEP SLEEP MODE REGISTERS Deep Sleep mode registers are provided in Register4-1 through Register4-6. REGISTER 4-1: DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh) R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 DSEN(1) — — — — (Reserved) DSULPEN RTCWDIS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DSEN: Deep Sleep Enable bit(1) 1 = Deep Sleep mode is entered on a SLEEP command 0 = Sleep mode is entered on a SLEEP command bit 6-3 Unimplemented: Read as ‘0’ bit 2 (Reserved): Always write ‘0’ to this bit bit 1 DSULPEN: Ultra Low-Power Wake-up Module Enable bit 1 = ULPWU module is enabled in Deep Sleep 0 = ULPWU module is disabled in Deep Sleep bit 0 RTCWDIS: RTCC Wake-up Disable bit 1 = Wake-up from RTCC is disabled 0 = Wake-up from RTCC is enabled Note 1: In order to enter Deep Sleep, Sleep must be executed immediately after setting DSEN. REGISTER 4-2: DSCONL: DEEP SLEEP CONTROL LOW BYTE REGISTER (BANKED F4Ch) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0(1) R/W-0(1) — — — — — ULPWDIS DSBOR RELEASE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 ULPWDIS: Ultra Low-Power Wake-up Disable bit 1 = ULPWU wake-up source is disabled 0 = ULPWU wake-up source is enabled (must also set DSULPEN = 1) bit 1 DSBOR: Deep Sleep BOR Event Status bit 1 = DSBOREN was enabled and VDD dropped below the DSBOR arming voltage during Deep Sleep, but did not fall below VDSBOR 0 = DSBOREN was disabled or VDD did not drop below the DSBOR arming voltage during Deep Sleep bit 0 RELEASE: I/O Pin State Release bit Upon waking from Deep Sleep, the I/O pins maintain their previous states. Clearing this bit will release the I/O pins and allow their respective TRIS and LAT bits to control their states. Note 1: This is the value when VDD is initially applied. DS39932D-page 58  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 4-3: DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0 (BANKED F4Eh) R/W-xxxx(1) Deep Sleep Persistent General Purpose bits bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 Deep Sleep Persistent General Purpose bits Contents are retained even in Deep Sleep mode. Note 1: All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep Sleep, or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS. REGISTER 4-4: DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1 (BANKED F4Fh) R/W-xxxx(1) Deep Sleep Persistent General Purpose bits bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 Deep Sleep Persistent General Purpose bits Contents are retained even in Deep Sleep mode. Note 1: All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep Sleep, or, the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS.  2011 Microchip Technology Inc. DS39932D-page 59

PIC18F46J11 FAMILY REGISTER 4-5: DSWAKEH: DEEP SLEEP WAKE HIGH BYTE REGISTER (BANKED F4Bh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — DSINT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 DSINT0: Interrupt-on-Change bit 1 = Interrupt-on-change was asserted during Deep Sleep 0 = Interrupt-on-change was not asserted during Deep Sleep REGISTER 4-6: DSWAKEL: DEEP SLEEP WAKE LOW BYTE REGISTER (BANKED F4Ah) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-1 DSFLT — DSULP(2) DSWDT(2) DSRTC(2) DSMCLR(2) — DSPOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DSFLT: Deep Sleep Fault Detected bit 1 = A Deep Sleep Fault was detected during Deep Sleep 0 = A Deep Sleep fault was not detected during Deep Sleep bit 6 Unimplemented: Read as ‘0’ bit 5 DSULP: Ultra Low-Power Wake-up status bit(2) 1 = An Ultra Low-Power Wake-up event occurred during Deep Sleep 0 = An Ultra Low-Power Wake-up event did not occur during Deep Sleep bit 4 DSWDT: Deep Sleep Watchdog Timer Time-out bit(2) 1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep 0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep bit 3 DSRTC: Real-Time Clock and Calendar Alarm bit(2) 1 = The Real-Time Clock/Calendar triggered an alarm during Deep Sleep 0 = The Real-Time Clock /Calendar did not trigger an alarm during Deep Sleep bit 2 DSMCLR: MCLR Event bit(2) 1 = The MCLR pin was asserted during Deep Sleep 0 = The MCLR pin was not asserted during Deep Sleep bit 1 Unimplemented: Read as ‘0’ bit 0 DSPOR: Power-on Reset Event bit 1 = The VDD supply POR circuit was active and a POR event was detected(1) 0 = The VDD supply POR circuit was not active, or was active, but did not detect a POR event Note 1: Unlike the other bits in this register, this bit can be set outside of Deep Sleep. 2: If multiple wake-up triggers are fired around the same time, only the first wake-up event triggered will have its wake-up status bit set. DS39932D-page 60  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 4.7 Ultra Low-Power Wake-up See Example4-1 for initializing the ULPWU module. The Ultra Low-Power Wake-up (ULPWU) on RA0 allows Note: For module-related bit definitions, see the a slow falling voltage to generate an interrupt without WDTCON register in Section26.2 excess current consumption. “Watchdog Timer (WDT)” and the DSWAKEL register (Register4-6). Follow these steps to use this feature: A series resistor between RA0 and the external 1. Configure a remappable output pin to output the capacitor provides overcurrent protection for the ULPOUT signal. RA0/AN0/C1INA/ULPWU/RP0 pin and can allow for 2. Map an INTx interrupt-on-change input function software calibration of the time-out (see Figure4-9). to the same pin as used for the ULPOUT output function. Alternatively, in step 1, configure FIGURE 4-9: SERIAL RESISTOR ULPOUT to output onto a PORTB interrupt-on-change pin. R 1 3. Charge the capacitor on RA0 by configuring the RA0 RA0 pin to an output and setting it to ‘1’. 4. Enable interrupt for the corresponding pin selected in step 2. C1 5. Stop charging the capacitor by configuring RA0 as an input. 6. Discharge the capacitor by setting the ULPEN and ULPSINK bits in the WDTCON register. 7. Configure Sleep mode. A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can 8. Enter Sleep mode. then be adjusted to provide the desired interrupt delay. When the voltage on RA0 drops below VIL, an interrupt This technique will compensate for the affects of will be generated, which will cause the device to temperature, voltage and component accuracy. The wake-up and execute the next instruction. peripheral can also be configured as a simple Program- This feature provides a low-power technique for mable Low-Voltage Detect (LVD) or temperature periodically waking up the device from Sleep mode. sensor. The time-out is dependent on the discharge time of the Note: For more information, refer to AN879, RC circuit on RA0. “Using the Microchip Ultra Low-Power When the ULPWU module causes the device to Wake-up Module” application note wake-up from Sleep mode, the WDTCON<ULPLVL> (DS00879). bit is set. When the ULPWU module causes the device to wake-up from Deep Sleep, the DSULP (DSWAKEL<5>) bit is set. Software can check these bits upon wake-up to determine the wake-up source. Also in Sleep mode, only the remappable output func- tion, ULPWU, will output this bit value to an RPn pin for externally detecting wake-up events.  2011 Microchip Technology Inc. DS39932D-page 61

PIC18F46J11 FAMILY EXAMPLE 4-1: ULTRA LOW-POWER WAKE-UP INITIALIZATION //********************************************************************************* //Configure a remappable output pin with interrupt capability //for ULPWU function (RP21 => RD4/INT1 in this example) //********************************************************************************* RPOR21 = 13;// ULPWU function mapped to RP21/RD4 RPINR1 = 21;// INT1 mapped to RP21 (RD4) //*************************** //Charge the capacitor on RA0 //*************************** TRISAbits.TRISA0 = 0; LATAbits.LATA0 = 1; for(i = 0; i < 10000; i++) Nop(); //********************************** //Stop Charging the capacitor on RA0 //********************************** TRISAbits.TRISA0 = 1; //***************************************** //Enable the Ultra Low Power Wakeup module //and allow capacitor discharge //***************************************** WDTCONbits.ULPEN = 1; WDTCONbits.ULPSINK = 1; //****************************************** //For Sleep, Enable Interrupt for ULPW. //****************************************** INTCON3bits.INT1IF = 0; INTCON3bits.INT1IE = 1; //******************** //Configure Sleep Mode //******************** //For Sleep OSCCONbits.IDLEN = 0; //For Deep Sleep OSCCONbits.IDLEN = 0;// enable deep sleep DSCONHbits.DSEN = 1;// Note: must be set just before executing Sleep(); //**************** //Enter Sleep Mode //**************** Sleep(); // for sleep, execution will resume here // for deep sleep, execution will restart at reset vector (use WDTCONbits.DS to detect) DS39932D-page 62  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 5.0 RESET Figure5-1 provides a simplified block diagram of the on-chip Reset circuit. The PIC18F46J11 family of devices differentiates among various kinds of Reset: 5.1 RCON Register a) Power-on Reset (POR) b) MCLR Reset during normal operation Device Reset events are tracked through the RCON register (Register5-1). The lower five bits of the register c) MCLR Reset during power-managed modes indicate that a specific Reset event has occurred. In d) Watchdog Timer (WDT) Reset (during most cases, these bits can only be set by the event and execution) must be cleared by the application after the event. The e) Configuration Mismatch (CM) state of these flag bits, taken together, can be read to f) Brown-out Reset (BOR) indicate the type of Reset that just occurred. This is g) RESET Instruction described in more detail in Section5.7 “Reset State of Registers”. h) Stack Full Reset i) Stack Underflow Reset The ECON register also has a control bit for setting interrupt priority (IPEN). Interrupt priority is discussed j) Deep Sleep Reset in Section9.0 “Interrupts”. This section discusses Resets generated by MCLR, POR and BOR, and covers the operation of the various start-up timers. For information on WDT Resets, see Section26.2 “Watchdog Timer (WDT)”. For Stack Reset events, see Section6.1.4.4 “Stack Full and Underflow Resets” and for Deep Sleep mode, see Section4.6 “Deep Sleep Mode”. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Configuration Word Mismatch Stack Stack Full/Underflow Reset Pointer External Reset MCLR ( )_IDLE Deep Sleep Reset Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset(1) S Brown-out Reset(2) VDDCORE PWRT PWRT Chip_Reset F: 5-bit Ripple Counter R Q INTRC LF: 11-bit Ripple Counter Note 1: The VDD monitoring BOR circuit can be enabled or disabled on “LF” devices based on the CONFIG3L<DSBOREN> Configuration bit. On “F” devices, the VDD monitoring BOR circuit is only enabled during Deep Sleep mode by CONFIG3L<DSBOREN>. 2: The VDDCORE monitoring BOR circuit is only implemented on “F” devices. It is always used, except while in Deep Sleep mode. The VDDCORE monitoring BOR circuit has a trip point threshold of VBOR (parameter D005).  2011 Microchip Technology Inc. DS39932D-page 63

PIC18F46J11 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER (ACCESS FD0h) R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0’ bit 5 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration Mismatch Reset occurs) bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. 2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section5.4.1 “Detecting BOR” for more information. 3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39932D-page 64  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 5.2 Master Clear (MCLR) Additionally, if any I/O pins had been configured as out- puts during Deep Sleep, these pins will be tri-stated The Master Clear Reset (MCLR) pin provides a method and the device will no longer be held in Deep Sleep. for triggering a hard external Reset of the device. A Once the VDD voltage recovers back above the Reset is generated by holding the pin low. PIC18 VDSBOR threshold, and once the core voltage regulator extended microcontroller devices have a noise filter in achieves a VDDCORE voltage above VBOR, the device the MCLR Reset path, which detects and ignores small will begin executing code again normally, but the DS bit pulses. in the WDTCON register will not be set. The device The MCLR pin is not driven low by any internal Resets, behavior will be similar to hard cycling all power to the including the WDT. device. On “LF” devices, the VDDCORE BOR circuit is always 5.3 Power-on Reset (POR) disabled because the internal core voltage regulator is disabled. Instead of monitoring VDDCORE, PIC18LF A POR condition is generated on-chip whenever VDD devices in this family can use the VDD BOR circuit to rises above a certain threshold. This allows the device monitor VDD excursions below the VDSBOR threshold. to start in the initialized state when VDD is adequate for The VDD BOR circuit can be disabled by setting the operation. DSBOREN bit = 0. To take advantage of the POR circuitry, tie the MCLR The VDD BOR circuit is enabled when DSBOREN = 1 pin through a resistor (1k to 10k) to VDD. This will on “LF” devices, or on “F” devices while in Deep Sleep eliminate external RC components usually needed to with DSBOREN = 1. When enabled, the VDD BOR create a POR delay. circuit is extremely low power (typ. 40 nA) during nor- When the device starts normal operation (i.e., exits the mal operation above ~2.3V on VDD. If VDD drops below Reset condition), device operating parameters this DSBOR arming level when the VDD BOR circuit is (voltage, frequency, temperature, etc.) must be met to enabled, the device may begin to consume additional ensure operation. If these conditions are not met, the current (typ. 50 A) as internal features of the circuit device must be held in Reset until the operating power up. The higher current is necessary to achieve conditions are met. more accurate sensing of the VDD level. However, the POR events are captured by the POR bit (RCON<1>). device will not enter Reset until VDD falls below the The state of the bit is set to ‘0’ whenever a Power-on VDSBOR threshold. Reset occurs; it does not change for any other Reset 5.4.1 DETECTING BOR event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets The BOR bit always resets to ‘0’ on any VDDCORE, BOR the bit to ‘1’ in software following any POR. or POR event. This makes it difficult to determine if a Brown-out Reset event has occurred just by reading 5.4 Brown-out Reset (BOR) the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. “F” devices incorporate two types of BOR circuits: one This assumes that the POR bit is reset to ‘1’ in software which monitors VDDCORE and one which monitors VDD. immediately after any Power-on Reset event. If BOR is Only one BOR circuit can be active at a time. When in ‘0’ while POR is ‘1’, it can be reliably assumed that a normal Run mode, Idle or normal Sleep modes, the Brown-out Reset event has occurred. BOR circuit that monitors VDDCORE is active and will If the voltage regulator is disabled (LF devices), the cause the device to be held in BOR if VDDCORE drops VDDCORE BOR functionality is disabled. In this case, below VBOR (parameter D005). Once VDDCORE rises the BOR bit cannot be used to determine a Brown-out back above VBOR, the device will be held in Reset until Reset event. The BOR bit is still cleared by a Power-on the expiration of the Power-up Timer, with period, Reset event. TPWRT (parameter 33). During Deep Sleep operation, the on-chip core voltage regulator is disabled and VDDCORE is allowed to drop to ground levels. If the Deep Sleep BOR circuit is enabled by the DSBOREN Configuration bit (CONFIG3L<2> = 1), it will monitor VDD. If VDD drops below the VDSBOR threshold, the device will be held in a Reset state similar to POR. All registers will be set back to their POR Reset values and the contents of the DSGPR0 and DSGPR1 holding registers will be lost.  2011 Microchip Technology Inc. DS39932D-page 65

PIC18F46J11 FAMILY 5.5 Configuration Mismatch (CM) 5.6 Power-up Timer (PWRT) The Configuration Mismatch (CM) Reset is designed to PIC18F46J11 family devices incorporate an on-chip detect, and attempt to recover from, random memory PWRT to help regulate the POR process. The PWRT is corrupting events. These include Electrostatic always enabled. The main function is to ensure that the Discharge (ESD) events, which can cause widespread device voltage is stable before code is executed. single bit changes throughout the device and result in The Power-up Timer (PWRT) of the PIC18F46J11 family catastrophic failure. devices is a 5-bit counter which uses the INTRC source In PIC18FXXJ Flash devices, the device Configuration as the clock input. This yields an approximate time registers (located in the configuration memory space) interval of 32x32s=1ms. While the PWRT is are continuously monitored during operation by com- counting, the device is held in Reset. paring their values to complimentary shadow registers. The power-up time delay depends on the INTRC clock If a mismatch is detected between the two sets of and will vary from chip-to-chip due to temperature and registers, a CM Reset automatically occurs. These process variation. See DC parameter 33 (TPWRT) for events are captured by the CM bit (RCON<5>). The details. state of the bit is set to ‘0’ whenever a CM event occurs; it does not change for any other Reset event. 5.6.1 TIME-OUT SEQUENCE A CM Reset behaves similarly to a MCLR, RESET The PWRT time-out is invoked after the POR pulse has instruction, WDT time-out or Stack Event Resets. As cleared. The total time-out will vary based on the status with all hard and power Reset events, the device of the PWRT. Figure5-2, Figure5-3, Figure5-4 and Configuration Words are reloaded from the Flash Figure5-5 all depict time-out sequences on power-up Configuration Words in program memory as the device with the PWRT. restarts. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the PWRT will expire. Bringing MCLR high will begin execution immediately if a clock source is available (Figure5-4). This is useful for testing purposes, or to synchronize more than one PIC18FXXXX device operating in parallel. FIGURE 5-2: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET DS39932D-page 66  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-5: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET  2011 Microchip Technology Inc. DS39932D-page 67

PIC18F46J11 FAMILY 5.7 Reset State of Registers TO, PD, POR and BOR) are set or cleared differently in different Reset situations, as indicated in Table5-1. Most registers are unaffected by a Reset. Their status These bits are used in software to determine the nature is unknown on POR and unchanged by all other of the Reset. Resets. The other registers are forced to a “Reset Table5-2 describes the Reset states for all of the state” depending on the type of Reset that occurred. Special Function Registers. These are categorized by Most registers are not affected by a WDT wake-up, POR and BOR, MCLR and WDT Resets, and WDT since this is viewed as the resumption of normal wake-ups. operation. Status bits from the RCON register (CM, RI, TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter(1) CM RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET instruction 0000h u 0 u u u u u u Brown-out Reset 0000h 1 1 1 1 u 0 u u Configuration Mismatch Reset 0000h 0 u u u u u u u MCLR Reset during 0000h u u 1 u u u u u power-managed Run modes MCLR Reset during 0000h u u 1 0 u u u u power-managed Idle modes and Sleep mode MCLR Reset during full-power 0000h u u u u u u u u execution Stack Full Reset (STVREN = 1) 0000h u u u u u u 1 u Stack Underflow Reset 0000h u u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u u u u u u u 1 actual Reset, STVREN = 0) WDT time-out during full-power 0000h u u 0 u u u u u or power-managed Run modes WDT time-out during PC + 2 u u 0 0 u u u u power-managed Idle or Sleep modes Interrupt exit from PC + 2 u u u 0 u u u u power-managed modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). DS39932D-page 68  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Wake From or Interrupt Stack Resets Deep Sleep CM Resets TOSU PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu(1) TOSH PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu(1) TOSL PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu(1) STKPTR PIC18F2XJ11 PIC18F4XJ11 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PCL PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F2XJ11 PIC18F4XJ11 --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F2XJ11 PIC18F4XJ11 0000 000x 0000 000u uuuu uuuu(3) INTCON2 PIC18F2XJ11 PIC18F4XJ11 1111 1111 1111 1111 uuuu uuuu(3) INTCON3 PIC18F2XJ11 PIC18F4XJ11 1100 0000 1100 0000 uuuu uuuu(3) INDF0 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A POSTINC0 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A POSTDEC0 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A PREINC0 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A PLUSW0 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A FSR0H PIC18F2XJ11 PIC18F4XJ11 ---- 0000 ---- 0000 ---- uuuu FSR0L PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A POSTINC1 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A POSTDEC1 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A PREINC1 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A PLUSW1 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A FSR1H PIC18F2XJ11 PIC18F4XJ11 ---- 0000 ---- 0000 ---- uuuu FSR1L PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F2XJ11 PIC18F4XJ11 ---- 0000 ---- 0000 ---- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. 6: Not implemented on "LF" devices.  2011 Microchip Technology Inc. DS39932D-page 69

PIC18F46J11 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Wake From or Interrupt Stack Resets Deep Sleep CM Resets INDF2 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A POSTINC2 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A POSTDEC2 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A PREINC2 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A PLUSW2 PIC18F2XJ11 PIC18F4XJ11 N/A N/A N/A FSR2H PIC18F2XJ11 PIC18F4XJ11 ---- 0000 ---- 0000 ---- uuuu FSR2L PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F2XJ11 PIC18F4XJ11 ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu TMR0L PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F2XJ11 PIC18F4XJ11 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F2XJ11 PIC18F4XJ11 0110 q100 0110 q100 0110 q1uu CM1CON PIC18F2XJ11 PIC18F4XJ11 0001 1111 0001 1111 uuuu uuuu CM2CON PIC18F2XJ11 PIC18F4XJ11 0001 1111 0001 1111 uuuu uuuu RCON(4) PIC18F2XJ11 PIC18F4XJ11 0-11 11qq 0-qq qquu u-qq qquu TMR1H PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F2XJ11 PIC18F4XJ11 0000 0000 uuuu uuuu uuuu uuuu TMR2 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F2XJ11 PIC18F4XJ11 1111 1111 1111 1111 uuuu uuuu T2CON PIC18F2XJ11 PIC18F4XJ11 -000 0000 -000 0000 -uuu uuuu SSP1BUF PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu SSP1ADD PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu SSP1MSK PIC18F2XJ11 PIC18F4XJ11 1111 1111 1111 1111 uuuu uuuu SSP1STAT PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu SSP1CON1 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu SSP1CON2 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu ADRESH PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu ADCON1 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu WDTCON PIC18F2XJ11 PIC18F4XJ11 1qq- q000 1qq- 0000 uqq- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. 6: Not implemented on "LF" devices. DS39932D-page 70  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Wake From or Interrupt Stack Resets Deep Sleep CM Resets PSTR1CON PIC18F2XJ11 PIC18F4XJ11 00-0 0001 00-0 0001 uu-u uuuu ECCP1AS PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu ECCP1DEL PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu CCPR1H PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PSTR2CON PIC18F2XJ11 PIC18F4XJ11 00-0 0001 00-0 0001 uu-u uuuu ECCP2AS PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu ECCP2DEL PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu CTMUCONH PIC18F2XJ11 PIC18F4XJ11 0-00 000- 0-00 000- u-uu uuu- CTMUCONL PIC18F2XJ11 PIC18F4XJ11 0000 00xx 0000 00xx uuuu uuuu CTMUICON PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu SPBRG1 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu RCREG1 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu TXREG1 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu TXSTA1 PIC18F2XJ11 PIC18F4XJ11 0000 0010 0000 0010 uuuu uuuu RCSTA1 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu SPBRG2 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu RCREG2 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu TXREG2 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu TXSTA2 PIC18F2XJ11 PIC18F4XJ11 0000 0010 0000 0010 uuuu uuuu EECON2 PIC18F2XJ11 PIC18F4XJ11 ---- ---- ---- ---- ---- ---- EECON1 PIC18F2XJ11 PIC18F4XJ11 --00 x00- --00 q00- --00 u00- IPR3 PIC18F2XJ11 PIC18F4XJ11 1111 1111 1111 1111 uuuu uuuu PIR3 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu(3) PIE3 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu IPR2 PIC18F2XJ11 PIC18F4XJ11 111- 1111 111- 1111 uuu- uuuu PIR2 PIC18F2XJ11 PIC18F4XJ11 000- 0000 000- 0000 uuu- uuuu(3) PIE2 PIC18F2XJ11 PIC18F4XJ11 000- 0000 000- 0000 uuu- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. 6: Not implemented on "LF" devices.  2011 Microchip Technology Inc. DS39932D-page 71

PIC18F46J11 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Wake From or Interrupt Stack Resets Deep Sleep CM Resets IPR1 PIC18F2XJ11 PIC18F4XJ11 1111 1111 1111 1111 uuuu uuuu PIR1 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu(3) PIE1 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu RCSTA2 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu OSCTUNE PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu T1GCON PIC18F2XJ11 PIC18F4XJ11 0000 0x00 0000 0x00 uuuu uxuu RTCVALH PIC18F2XJ11 PIC18F4XJ11 0xxx xxxx 0uuu uuuu 0uuu uuuu RTCVALL PIC18F2XJ11 PIC18F4XJ11 0xxx xxx 0uuu uuuu 0uuu uuuu T3GCON PIC18F2XJ11 PIC18F4XJ11 0000 0x00 uuuu uxuu uuuu uxuu TRISE(5) — PIC18F4XJ11 ---- -111 ---- -111 ---- -uuu TRISD(5) — PIC18F4XJ11 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F2XJ11 PIC18F4XJ11 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F2XJ11 PIC18F4XJ11 1111 1111 1111 1111 uuuu uuuu TRISA PIC18F2XJ11 PIC18F4XJ11 111- 1111 111- 1111 uuu- uuuu ALRMCFG PIC18F2XJ11 PIC18F4XJ11 0000 0000 uuuu uuuu uuuu uuuu ALRMRPT PIC18F2XJ11 PIC18F4XJ11 0000 0000 uuuu uuuu uuuu uuuu ALRMVALH PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu ALRMVALL PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu LATE(5) — PIC18F4XJ11 ---- -xxx ---- -uuu ---- -uuu LATD(5) — PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu LATC PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu LATA PIC18F2XJ11 PIC18F4XJ11 xxx- xxxx uuu- uuuu uuu- uuuu DMACON1 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu DMACON2 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu HLVDCON PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PORTE(5) — PIC18F4XJ11 00-- -xxx uu-- -uuu uu-- -uuu PORTD(5) — PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu PORTA PIC18F2XJ11 PIC18F4XJ11 xxx- xxxx uuu- uuuu uuu- uuuu SPBRGH1 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. 6: Not implemented on "LF" devices. DS39932D-page 72  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Wake From or Interrupt Stack Resets Deep Sleep CM Resets BAUDCON1 PIC18F2XJ11 PIC18F4XJ11 0100 0-00 0100 0-00 uuuu u-uu SPBRGH2 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu BAUDCON2 PIC18F2XJ11 PIC18F4XJ11 0100 0-00 0100 0-00 uuuu u-uu TMR3H PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F2XJ11 PIC18F4XJ11 0000 -000 uuuu -uuu uuuu -uuu TMR4 PIC18F2XJ11 PIC18F4XJ11 0000 0000 uuuu uuuu uuuu uuuu PR4 PIC18F2XJ11 PIC18F4XJ11 1111 1111 1111 1111 uuuu uuuu T4CON PIC18F2XJ11 PIC18F4XJ11 -000 0000 -000 0000 -uuu uuuu SSP2BUF PIC18F2XJ11 PIC18F4XJ11 xxxx xxxx uuuu uuuu uuuu uuuu SSP2ADD PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu SSP2MSK PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu SSP2STAT PIC18F2XJ11 PIC18F4XJ11 1111 1111 1111 1111 uuuu uuuu SSP2CON1 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu SSP2CON2 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu CMSTAT PIC18F2XJ11 PIC18F4XJ11 ---- --11 ---- --11 ---- --uu PMADDRH(5) — PIC18F4XJ11 -000 0000 -000 0000 -uuu uuuu PMDOUT1H(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PMADDRL(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PMDOUT1L(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PMDIN1H(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PMDIN1L(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu TXADDRL PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu TXADDRH PIC18F2XJ11 PIC18F4XJ11 ---- 0000 ---- 0000 ---- uuuu RXADDRL PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu RXADDRH PIC18F2XJ11 PIC18F4XJ11 ---- 0000 ---- 0000 ---- uuuu DMABCL PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu DMABCH PIC18F2XJ11 PIC18F4XJ11 ---- --00 ---- --00 ---- --uu PMCONH(5) — PIC18F4XJ11 0--0 0000 0--0 0000 u--u uuuu PMCONL(5) — PIC18F4XJ11 000- 0000 000- 0000 uuu- uuuu PMMODEH(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PMMODEL(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. 6: Not implemented on "LF" devices.  2011 Microchip Technology Inc. DS39932D-page 73

PIC18F46J11 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Wake From or Interrupt Stack Resets Deep Sleep CM Resets PMDOUT2H(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PMDOUT2L(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PMDIN2H(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PMDIN2L(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PMEH(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PMEL(5) — PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu PMSTATH(5) — PIC18F4XJ11 00-- 0000 00-- 0000 uu-- uuuu PMSTATL(5) — PIC18F4XJ11 10-- 1111 10-- 1111 uu-- uuuu CVRCON PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu TCLKCON PIC18F2XJ11 PIC18F4XJ11 ---0 --00 ---0 --uu ---u --uu DSGPR1(6) PIC18F2XJ11 PIC18F4XJ11 uuuu uuuu uuuu uuuu uuuu uuuu DSGPR0(6) PIC18F2XJ11 PIC18F4XJ11 uuuu uuuu uuuu uuuu uuuu uuuu DSCONH(6) PIC18F2XJ11 PIC18F4XJ11 0--- -000 0--- -uuu u--- -uuu DSCONL(6) PIC18F2XJ11 PIC18F4XJ11 ---- -000 ---- -u00 ---- -uuu DSWAKEH(6) PIC18F2XJ11 PIC18F4XJ11 ---- ---0 ---- ---0 ---- ---u DSWAKEL(6) PIC18F2XJ11 PIC18F4XJ11 0-00 00-1 0-00 00-0 u-uu uu-u ANCON1 PIC18F2XJ11 PIC18F4XJ11 00-0 0000 00-0 0000 uu-u uuuu ANCON0 PIC18F2XJ11 PIC18F4XJ11 0000 0000 0000 0000 uuuu uuuu ODCON1 PIC18F2XJ11 PIC18F4XJ11 ---- --00 ---- --uu ---- --uu ODCON2 PIC18F2XJ11 PIC18F4XJ11 ---- --00 ---- --uu ---- --uu ODCON3 PIC18F2XJ11 PIC18F4XJ11 ---- --00 ---- --uu ---- --uu RTCCFG PIC18F2XJ11 PIC18F4XJ11 0-00 0000 u-uu uuuu u-uu uuuu RTCCAL PIC18F2XJ11 PIC18F4XJ11 0000 0000 uuuu uuuu uuuu uuuu REFOCON PIC18F2XJ11 PIC18F4XJ11 0-00 0000 0-00 0000 u-uu uuuu PADCFG1 PIC18F2XJ11 PIC18F4XJ11 ---- -000 ---- -000 ---- -uuu PPSCON PIC18F2XJ11 PIC18F4XJ11 ---- ---0 ---- ---0 ---- ---u RPINR24 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPINR23 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPINR22 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPINR21 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPINR17 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPINR16 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. 6: Not implemented on "LF" devices. DS39932D-page 74  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, Wake-up via WDT Register Applicable Devices RESET Instruction Wake From or Interrupt Stack Resets Deep Sleep CM Resets RPINR8 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPINR7 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPINR6 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPINR4 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPINR3 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPINR2 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPINR1 PIC18F2XJ11 PIC18F4XJ11 ---1 1111 ---1 1111 ---u uuuu RPOR24 — PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR23 — PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR22 — PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR21 — PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR20 — PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR19 — PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR18 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR17 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR16 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR15 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR14 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR13 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR12 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR11 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR10 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR9 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR8 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR7 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR6 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR5 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR4 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR3 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR2 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR1 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu RPOR0 PIC18F2XJ11 PIC18F4XJ11 ---0 0000 ---0 0000 ---u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. 6: Not implemented on "LF" devices.  2011 Microchip Technology Inc. DS39932D-page 75

PIC18F46J11 FAMILY NOTES: DS39932D-page 76  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 6.0 MEMORY ORGANIZATION 6.1 Program Memory Organization There are two types of memory in PIC18 Flash PIC18 microcontrollers implement a 21-bit program microcontrollers: counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address returns all ‘0’s (a As Harvard architecture devices, the data and program NOP instruction). memories use separate busses; this allows for The PIC18F46J11 family offers a range of on-chip concurrent access of the two memory spaces. Flash program memory sizes, from 16Kbytes (up to Section7.0 “Flash Program Memory” provides 8,192 single-word instructions) to 64Kbytes additional information on the operation of the Flash (32,768single-word instructions). program memory. Figure6-1 provides the program memory maps for individual family devices. FIGURE 6-1: MEMORY MAPS FOR PIC18F46J11 FAMILY DEVICES PC<20:0> 21 CALL, CALLW, RCALL, RETURN, RETFIE, RETLW, ADDULNK, SUBULNK Stack Level 1    Stack Level 31 PIC18FX4J11 PIC18FX5J50 PIC18FX6J11 000000h On-Chip On-Chip On-Chip Memory Memory Memory Config. Words 003FFFh Config. Words 007FFFh Config. Words e 00FFFFh c a p S y or m e M er s U Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ 1FFFFFF Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.  2011 Microchip Technology Inc. DS39932D-page 77

PIC18F46J11 FAMILY 6.1.1 HARD MEMORY VECTORS 6.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded Because PIC18F46J11 family devices do not have return vectors in their program memory space. The persistent configuration memory, the top four words of Reset vector address is the default value to which the on-chip program memory are reserved for configuration program counter returns on all device Resets; it is information. On Reset, the configuration information is located at 0000h. copied into the Configuration registers. PIC18 devices also have two interrupt vector The Configuration Words are stored in their program addresses for handling high-priority and low-priority memory location in numerical order, starting with the interrupts. The high-priority interrupt vector is located at lower byte of CONFIG1 at the lowest address and 0008h and the low-priority interrupt vector at 0018h. ending with the upper byte of CONFIG4. Figure6-2 provides their locations in relation to the Table6-1 provides the actual addresses of the Flash program memory map. Configuration Word for devices in the PIC18F46J11 family. Figure6-2 displays their location in the memory FIGURE 6-2: HARD VECTOR AND map with other memory vectors. CONFIGURATION WORD Additional details on the device Configuration Words LOCATIONS FOR are provided in Section26.1 “Configuration Bits”. PIC18F46J11 FAMILY DEVICES TABLE 6-1: FLASH CONFIGURATION WORD FOR PIC18F46J11 Reset Vector 0000h FAMILY DEVICES High-Priority Interrupt Vector 0008h Program Configuration Device Memory Word Low-Priority Interrupt Vector 0018h (Kbytes) Addresses PIC18F24J11 16 3FF8h to 3FFFh PIC18F44J11 On-Chip PIC18F25J11 32 7FF8h to 7FFFh Program Memory PIC18F45J11 PIC18F26J11 64 FFF8h to FFFFh PIC18F46J11 Flash Configuration Words (Top of Memory-7) (Top of Memory) Read as ‘0’ 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure6-1 for device-specific values). Shaded area represents unimplemented memory. Areas are not shown to scale. DS39932D-page 78  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 6.1.3 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer (SP), STKPTR. The stack space is The Program Counter (PC) specifies the address of the not part of either program or data space. The Stack instruction to fetch for execution. The PC is 21 bits wide Pointer is readable and writable, and the address on and is contained in three separate 8-bit registers. The the top of the stack is readable and writable through the low byte, known as the PCL register, is both readable Top-of-Stack Special Function Registers (SFRs). Data and writable. The high byte, or PCH register, contains can also be pushed to, or popped from, the stack using the PC<15:8> bits; it is not directly readable or writable. these registers. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack. register contains the PC<20:16> bits; it is also not The Stack Pointer is first incremented and the location directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the register are performed through the PCLATU register. contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred a pop from the stack. The contents of the location to the program counter by any operation that writes to pointed to by the STKPTR are transferred to the PC PCL. Similarly, the upper 2 bytes of the program and then the Stack Pointer is decremented. counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all offsets to the PC (see Section6.1.6.1 “Computed Resets. There is no RAM associated with the location GOTO”). corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is The PC addresses bytes in the program memory. To full, has overflowed or has underflowed. prevent the PC from becoming misaligned with word instructions, the Least Significant bit (LSb) of PCL is 6.1.4.1 Top-of-Stack Access fixed to a value of ‘0’. The PC increments by two to address sequential instructions in the program Only the top of the return address stack (TOS) is read- memory. able and writable. A set of three registers, TOSU:TOSH:TOSL, holds the contents of the stack The CALL, RCALL, GOTO and program branch location pointed to by the STKPTR register instructions write to the program counter directly. For (Figure6-3). This allows users to implement a software these instructions, the contents of PCLATH and stack if necessary. After a CALL, RCALL or interrupt PCLATU are not transferred to the program counter. (and ADDULNK and SUBULNK instructions if the extended instruction set is enabled), the software can 6.1.4 RETURN ADDRESS STACK read the pushed value by reading the The return address stack allows any combination of up TOSU:TOSH:TOSL registers. These values can be to 31 program calls and interrupts to occur. The PC is placed on a user-defined software stack. At return time, pushed onto the stack when a CALL or RCALL instruc- the software can return these values to tion is executed, or an interrupt is Acknowledged. The TOSU:TOSH:TOSL and do a return. PC value is pulled off the stack on a RETURN, RETLW The user must disable the Global Interrupt Enable or a RETFIE instruction (and on ADDULNK and (GIE) bits while accessing the stack to prevent inadver- SUBULNK instructions if the extended instruction set is tent stack corruption. enabled). PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 6-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> Top-of-Stack Registers Stack Pointer 11111 TOSU TOSH TOSL 11110 STKPTR<4:0> 00h 1Ah 34h 11101 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000  2011 Microchip Technology Inc. DS39932D-page 79

PIC18F46J11 FAMILY 6.1.4.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return zero to the PC The STKPTR register (Register6-1) contains the Stack and set the STKUNF bit, while the Stack Pointer Pointer value, the STKFUL (Stack Full) and the remains at zero. The STKUNF bit will remain set until STKUNF (Stack Underflow) status bits. The value of cleared by software or until a POR occurs. the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System (RTOS) for return stack maintenance. not the same as a Reset, as the contents After the PC is pushed onto the stack 31 times (without of the SFRs are not affected. popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a 6.1.4.3 PUSH and POP Instructions Power-on Reset (POR). Since the Top-of-Stack is readable and writable, the The action that takes place when the stack becomes ability to push values onto the stack and pull values off full depends on the state of the Stack Overflow Reset the stack, without disturbing normal program execution Enable (STVREN) Configuration bit. is necessary. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be Refer to Section26.1 “Configuration Bits” for device manipulated under software control. TOSU, TOSH and Configuration bits’ description. TOSL can be modified to place data or a return address If STVREN is set (default), the 31st push will push the on the stack. (PC + 2) value onto the stack, set the STKFUL bit and The PUSH instruction places the current PC value onto reset the device. The STKFUL bit will remain set and the stack. This increments the Stack Pointer and loads the Stack Pointer will be set to zero. the current PC value onto the stack. If STVREN is cleared, the STKFUL bit will be set on the The POP instruction discards the current TOS by 31st push and the Stack Pointer will increment to 31. decrementing the Stack Pointer. The previous value Any additional pushes will not overwrite the 31st push pushed onto the stack then becomes the TOS value. and the STKPTR will remain at 31. REGISTER 6-1: STKPTR: STACK POINTER REGISTER (ACCESS FFCh) R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: Bits 7 and 6 are cleared by user software or by a POR. DS39932D-page 80  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 6.1.4.4 Stack Full and Underflow Resets 6.1.6 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in There may be programming situations that require the Configuration register 1L. When STVREN is set, a full creation of data structures or look-up tables in program or underflow condition sets the appropriate STKFUL or memory. For PIC18 devices, look-up tables can be STKUNF bit and then causes a device Reset. When implemented in two ways: STVREN is cleared, a full or underflow condition sets • Computed GOTO the appropriate STKFUL or STKUNF bit, but does not • Table Reads cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a POR. 6.1.6.1 Computed GOTO 6.1.5 FAST REGISTER STACK (FRS) A computed GOTO is accomplished by adding an offset to the PC. An example is shown in Example6-2. A Fast Register Stack (FRS) is provided for the STATUS, WREG and BSR registers to provide a “fast A look-up table can be formed with an ADDWF PCL return” option for interrupts. This stack is only one level instruction and a group of RETLW nn instructions. The deep and is neither readable nor writable. It is loaded W register is loaded with an offset into the table before with the current value of the corresponding register executing a call to that table. The first instruction of the when the processor vectors for an interrupt. All inter- called routine is the ADDWF PCL instruction. The next rupt sources push values into the Stack registers. The executed instruction will be one of the RETLW nn values in the registers are then loaded back into the instructions that returns the value ‘nn’ to the calling working registers if the RETFIE, FAST instruction is function. used to return from the interrupt. The offset value (in WREG) specifies the number of If both low-priority and high-priority interrupts are bytes that the PC should advance and should be enabled, the Stack registers cannot be used reliably to multiples of 2 (LSb = 0). return from low-priority interrupts. If a high-priority In this method, only one byte may be stored in each interrupt occurs while servicing a low-priority interrupt, instruction location; room on the return address stack is the Stack register values stored by the low-priority required. interrupt will be overwritten. In these cases, users must save the key registers in software during a low-priority EXAMPLE 6-2: COMPUTED GOTO USING interrupt. AN OFFSET VALUE If interrupt priority is not used, all interrupts may use the MOVF OFFSET, W FRS for returns from interrupt. If no interrupts are used, CALL TABLE the FRS can be used to restore the STATUS, WREG ORG nn00h and BSR registers at the end of a subroutine call. To TABLE ADDWF PCL use the Fast Register Stack for a subroutine call, a RETLW nnh CALL label, FAST instruction must be executed to RETLW nnh save the STATUS, WREG and BSR registers to the RETLW nnh Fast Register Stack. A RETURN, FAST instruction is . then executed to restore these registers from the FRS. . . Example6-1 provides a source code example that uses the FRS during a subroutine call and return. 6.1.6.2 Table Reads EXAMPLE 6-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per ;STACK program word while programming. The Table Pointer  (TBLPTR) specifies the byte address and the Table  Latch (TABLAT) contains the data that is read from the program memory. Data is transferred from program SUB1  memory one byte at a time.  RETURN FAST ;RESTORE VALUES SAVED Table read operation is discussed further in ;IN FAST REGISTER STACK Section7.1 “Table Reads and Table Writes”.  2011 Microchip Technology Inc. DS39932D-page 81

PIC18F46J11 FAMILY 6.2 PIC18 Instruction Cycle 6.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles, Q1 6.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are pipe- The microcontroller clock input, whether from an lined in such a manner that a fetch takes one instruction internal or external source, is internally divided by ‘4’ to cycle, while the decode and execute take another generate four non-overlapping quadrature clocks (Q1, instruction cycle. However, due to the pipelining, each Q2, Q3 and Q4). Internally, the PC is incremented on instruction effectively executes in one cycle. If an every Q1; the instruction is fetched from the program instruction causes the PC to change (e.g., GOTO), then memory and latched into the Instruction Register (IR) two cycles are required to complete the instruction during Q4. The instruction is decoded and executed (Example6-3). during the following Q1 through Q4. Figure6-4 A fetch cycle begins with the PC incrementing in Q1. illustrates the clocks and instruction execution flow. In the execution cycle, the fetched instruction is latched into the IR in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Q3 Phase Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF LATB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF LATA, 3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 Note: All instructions are single-cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then exe- cuted. DS39932D-page 82  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruc- tion. Since instructions are always stored on word The program memory is addressed in bytes. Instruc- boundaries, the data contained in the instruction is a tions are stored as 2 bytes or 4 bytes in program word address. The word address is written to PC<20:1>, memory. The Least Significant Byte (LSB) of an which accesses the desired byte address in program instruction word is always stored in a program memory memory. Instruction #2 in Figure6-5 displays how the location with an even address (LSB = 0). To maintain instruction, GOTO 0006h, is encoded in the program alignment with instruction boundaries, the PC memory. Program branch instructions, which encode a increments in steps of 2 and the LSB will always read relative address offset, operate in the same manner. The ‘0’ (see Section6.1.3 “Program Counter”). offset value stored in a branch instruction represents the Figure6-5 provides an example of how instruction number of single-word instructions that the PC will be words are stored in the program memory. offset by. Section27.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 6-5: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0  Program Memory 000000h Byte Locations  000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 6.2.4 TWO-WORD INSTRUCTIONS used by the instruction sequence. If the first word is skipped for some reason, and the second word is The standard PIC18 instruction set has four two-word executed by itself, a NOP is executed instead. This is instructions: CALL, MOVFF, GOTO and LSFR. In all necessary for cases when the two-word instruction is cases, the second word of the instructions always has preceded by a conditional instruction that changes the ‘1111’ as its four Most Significant bits (MSbs); the other PC. Example6-4 illustrates how this works. 12 bits are literal data, usually a data memory address. The use of ‘1111’ in the 4 MSbs of an instruction Note: See Section6.5 “Program Memory and specifies a special form of NOP. If the instruction is the Extended Instruction Set” for infor- mation on two-word instructions in the executed in proper sequence immediately after the first word, the data in the second word is accessed and extended instruction set. EXAMPLE 6-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code  2011 Microchip Technology Inc. DS39932D-page 83

PIC18F46J11 FAMILY 6.3 Data Memory Organization Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register Note: The operation of some aspects of data (BSR). This SFR holds the 4 MSbs of a location’s memory is changed when the PIC18 address; the instruction itself includes the 8LSbs. Only extended instruction set is enabled. See the four lower bits of the BSR are implemented Section6.6 “Data Memory and the (BSR<3:0>). The upper four bits are unused; they will Extended Instruction Set” for more always read ‘0’ and cannot be written to. The BSR can information. be loaded directly by using the MOVLB instruction. The data memory in PIC18 devices is implemented as The value of the BSR indicates the bank in data static RAM. Each register in the data memory has a memory. The 8 bits in the instruction show the location 12-bit address, allowing up to 4096 bytes of data in the bank and can be thought of as an offset from the memory. The memory space is divided into as many as bank’s lower boundary. The relationship between the 16 banks that contain 256 bytes each. The BSR’s value and the bank division in data memory is PIC18F46J11 family implements all available banks illustrated in Figure6-7. and provides 3.8Kbytes of data memory available to Since, up to 16 registers may share the same low-order the user. Figure6-6 provides the data memory address, the user must always be careful to ensure that organization for the devices. the proper bank is selected before performing a data The data memory contains Special Function Registers read or write. For example, writing what should be (SFRs) and General Purpose Registers (GPRs). The program data to an 8-bit address of F9h while the BSR SFRs are used for control and status of the controller is 0Fh, will end up resetting the PC. and peripheral functions, while GPRs are used for data While any bank can be selected, only those banks that storage and scratchpad operations in the user’s are actually implemented can be read or written to. application. Any read of an unimplemented location will Writes to unimplemented banks are ignored, while read as ‘0’s. reads from unimplemented banks will return ‘0’s. Even The instruction set and architecture allow operations so, the STATUS register will still be affected as if the across all banks. The entire data memory may be operation was successful. The data memory map in accessed by Direct, Indirect or Indexed Addressing Figure6-6 indicates which banks are implemented. modes. Addressing modes are discussed later in this In the core PIC18 instruction set, only the MOVFF section. instruction fully specifies the 12-bit address of the To ensure that commonly used registers (select SFRs source and target registers. This instruction ignores the and select GPRs) can be accessed in a single cycle, BSR completely when it executes. All other instructions PIC18 devices implement an Access Bank. This is a include only the low-order address as an operand and 256-byte memory space that provides fast access to must use either the BSR or the Access Bank to locate select SFRs and the lower portion of GPR Bank 0 with- their target registers. out using the BSR. Section6.3.2 “Access Bank” provides a detailed description of the Access RAM. 6.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. DS39932D-page 84  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 6-6: DATA MEMORY MAP FOR PIC18F46J11 FAMILY DEVICES BSR3:BSR0 Data Memory Map When a = 0: The BSR is ignored and the 00h 000h Access Bank is used. Access RAM = 0000 Bank 0 05Fh The first 96 bytes are general 060h purpose RAM (from Bank 0). GPR FFh 0FFh The remaining 160 bytes are = 0001 00h 100h Special Function Registers Bank 1 GPR (from Bank 15). FFh 1FFh 00h 200h = 0010 Bank 2 GPR When a = 1: FFh 2FFh The BSR specifies the bank 00h 300h used by the instruction. = 0011 Bank 3 GPR FFh 3FFh 00h 400h = 0100 Bank 4 GPR, BDT FFh 4FFh 00h 500h = 0101 Bank 5 GPR FFh 5FFh 00h 600h = 0110 Bank 6 GPR Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 GPR Access RAM Low 5Fh FFh 7FFh Access RAM High 60h 00h 800h = 1000 (SFRs) Bank 8 GPR FFh FFh 8FFh 00h 900h = 1001 Bank 9 GPR FFh 9FFh 00h A00h = 1010 Bank 10 GPR FFh AFFh 00h B00h = 1011 Bank 11 GPR FFh BFFh 00h C00h = 1100 GPR Bank 12 FFh CFFh 00h D00h = 1101 GPR Bank 13 FFh DFFh 00h E00h = 1110 GPR EBFh Bank 14 C0h Non-Access SFR(1) EC0h FFh EFFh = 1111 00h F00h Bank 15 Non-Access SFR(1) 60h F5Fh Access SFRs FFh FFFh Note 1: Addresses EC0h through F5Fh are not part of the Access Bank. Either the BANKED or the MOVFF instruction should be used to access these SFRs.  2011 Microchip Technology Inc. DS39932D-page 85

PIC18F46J11 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 7 BSR(1) 0 000h Data Memory 00h 7 From Opcode(2) 0 0 0 0 0 0 0 1 0 Bank 0 11 11 11 11 11 11 11 11 FFh 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 6.3.2 ACCESS BANK Using this “forced” addressing allows the instruction to operate on a data address in a single cycle without While the use of the BSR with an embedded 8-bit updating the BSR first. For 8-bit addresses of 60h and address allows users to address the entire range of above, this means that users can evaluate and operate data memory, it also means that the user must always on SFRs more efficiently. The Access RAM below 60h ensure that the correct bank is selected. Otherwise, is a good place for data values that the user might need data may be read from or written to the wrong location. to access rapidly, such as immediate computational This can be disastrous if a GPR is the intended target results or common program variables. Access RAM of an operation, but an SFR is written to instead. also allows for faster and more code efficient context Verifying and/or changing the BSR for each read or saving and switching of variables. write to data memory can become very inefficient. The mapping of the Access Bank is slightly different To streamline access for the most commonly used data when the extended instruction set is enabled (XINST memory locations, the data memory is configured with Configuration bit = 1). This is discussed in more detail an Access Bank, which allows users to access a in Section6.6.3 “Mapping the Access Bank in mapped block of memory without specifying a BSR. Indexed Literal Offset Mode”. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of 6.3.3 GENERAL PURPOSE memory (60h-FFh) in Bank 15. The lower half is known REGISTER FILE as the Access RAM and is composed of GPRs. The upper half is where the device’s SFRs are mapped. PIC18 devices may have banked memory in the GPR These two areas are mapped contiguously in the area. This is data RAM, which is available for use by all Access Bank and can be addressed in a linear fashion instructions. GPRs start at the bottom of Bank 0 by an 8-bit address (Figure6-6). (address 000h) and grow upward toward the bottom of the SFR area. GPRs are not initialized by a POR and The Access Bank is used by core PIC18 instructions are unchanged on all other Resets. that include the Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. DS39932D-page 86  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral The SFRs are registers used by the CPU and periph- features are described in the chapter for that peripheral. eral modules for controlling the desired operation of the device. These registers are implemented as static The SFRs are typically distributed among the RAM. SFRs start at the top of data memory (FFFh) and peripherals whose functions they control. Unused SFR extend downward to occupy more than the top half of locations are unimplemented and read as ‘0’s Bank 15 (F40h to FFFh). Table6-2 and Table6-3 pro- Note: The SFRs located between EC0h and vide a list of these registers. F5Fh are not part of the Access Bank. The SFRs can be classified into two sets: those Either banked instructions (using BSR) or associated with the “core” device functionality (ALU, the MOVFF instruction should be used to Resets and interrupts) and those related to the access these locations. When program- peripheral functions. The Reset and Interrupt registers ming in MPLAB® C18, the compiler will are described in their corresponding chapters, while the automatically use the appropriate addressing mode. TABLE 6-2: ACCESS BANK SPECIAL FUNCTION REGISTER MAP Address Name Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh PSTR1CON F9Fh IPR1 F7Fh SPBRGH1 FFEh TOSH FDEh POSTINC2(1) FBEh ECCP1AS F9Eh PIR1 F7Eh BAUDCON1 FFDh TOSL FDDh POSTDEC2(1) FBDh ECCP1DEL F9Dh PIE1 F7Dh SPBRGH2 FFCh STKPTR FDCh PREINC2(1) FBCh CCPR1H F9Ch RCSTA2 F7Ch BAUDCON2 FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR1L F9Bh OSCTUNE F7Bh TMR3H FFAh PCLATH FDAh FSR2H FBAh CCP1CON F9Ah T1GCON F7Ah TMR3L FF9h PCL FD9h FSR2L FB9h PSTR2CON F99h RTCVALH F79h T3CON FF8h TBLPTRU FD8h STATUS FB8h ECCP2AS F98h RTCVALL F78h TMR4 FF7h TBLPTRH FD7h TMR0H FB7h ECCP2DEL F97h T3GCON F77h PR4 FF6h TBLPTRL FD6h TMR0L FB6h CCPR2H F96h TRISE F76h T4CON FF5h TABLAT FD5h T0CON FB5h CCPR2L F95h TRISD F75h SSP2BUF FF4h PRODH FD4h —(5) FB4h CCP2CON F94h TRISC F74h SSP2ADD(3) FF3h PRODL FD3h OSCCON FB3h CTMUCONH F93h TRISB F73h SSP2STAT FF2h INTCON FD2h CM1CON FB2h CTMUCONL F92h TRISA F72h SSP2CON1 FF1h INTCON2 FD1h CM2CON FB1h CTMUICON F91h ALRMCFG F71h SSP2CON2 FF0h INTCON3 FD0h RCON FB0h SPBRG1 F90h ALRMRPT F70h CMSTAT FEFh INDF0(1) FCFh TMR1H FAFh RCREG1 F8Fh ALRMVALH F6Fh PMADDRH(2,4) FEEh POSTINC0(1) FCEh TMR1L FAEh TXREG1 F8Eh ALRMVALL F6Eh PMADDRL(2,4) FEDh POSTDEC0(1) FCDh T1CON FADh TXSTA1 F8Dh LATE(2) F6Dh PMDIN1H(2) FECh PREINC0(1) FCCh TMR2 FACh RCSTA1 F8Ch LATD(2) F6Ch PMDIN1L(2) FEBh PLUSW0(1) FCBh PR2 FABh SPBRG2 F8Bh LATC F6Bh TXADDRL FEAh FSR0H FCAh T2CON FAAh RCREG2 F8Ah LATB F6Ah TXADDRH FE9h FSR0L FC9h SSP1BUF FA9h TXREG2 F89h LATA F69h RXADDRL FE8h WREG FC8h SSP1ADD(3) FA8h TXSTA2 F88h DMACON1 F68h RXADDRH FE7h INDF1(1) FC7h SSP1STAT FA7h EECON2 F87h —(5) F67h DMABCL FE6h POSTINC1(1) FC6h SSP1CON1 FA6h EECON1 F86h DMACON2 F66h DMABCH FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h HLVDCON F65h —(5) FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE(2) F64h —(5) FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD(2) F63h —(5) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h —(5) FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h —(5) FE0h BSR FC0h WDTCON FA0h PIE2 F80h PORTA F60h —(5) Note 1: This is not a physical register. 2: This register is not available on 28-pin devices. 3: SSPxADD and SSPxMSK share the same address. 4: PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address. PMADDRx is used in Master modes and PMDOUTx is used in Slave modes. 5: Reserved: Do not write to this location.  2011 Microchip Technology Inc. DS39932D-page 87

PIC18F46J11 FAMILY TABLE 6-3: NON-ACCESS BANK SPECIAL FUNCTION REGISTER MAP Address Name Address Name Address Name Address Name Address Name F5Fh PMCONH(1) F3Fh RTCCFG F1Fh — EFFh PPSCON EDFh — F5Eh PMCONL(1) F3Eh RTCCAL F1Eh — EFEh RPINR24 EDEh RPOR24(1) F5Dh PMMODEH(1) F3Dh REFOCON F1Dh — EFDh RPINR23 EDDh RPOR23(1) F5Ch PMMODEL(1) F3Ch PADCFG1 F1Ch — EFCh RPINR22 EDCh RPOR22(1) F5Bh PMDOUT2H(1) F3Bh — F1Bh — EFBh RPINR21 EDBh RPOR21(1) F5Ah PMDOUT2L(1) F3Ah — F1Ah — EFAh — EDAh RPOR20(1) F59h PMDIN2H(1) F39h — F19h — EF9h — ED9h RPOR19(1) F58h PMDIN2L(1) F38h — F18h — EF8h — ED8h RPOR18 F57h PMEH(1) F37h — F17h — EF7h RPINR17 ED7h RPOR17 F56h PMEL(1) F36h — F16h — EF6h RPINR16 ED6h RPOR16 F55h PMSTATH(1) F35h — F15h — EF5h — ED5h RPOR15 F54h PMSTATL(1) F34h — F14h — EF4h — ED4h RPOR14 F53h CVRCON F33h — F13h — EF3h — ED3h RPOR13 F52h TCLKCON F32h — F12h — EF2h — ED2h RPOR12 F51h — F31h — F11h — EF1h — ED1h RPOR11 F50h — F30h — F10h — EF0h — ED0h RPOR10 F4Fh DSGPR1(2) F2Fh — F0Fh — EEFh — ECFh RPOR9 F4Eh DSGPR0(2) F2Eh — F0Eh — EEEh RPINR8 ECEh RPOR8 F4Dh DSCONH(2) F2Dh — F0Dh — EEDh RPINR7 ECDh RPOR7 F4Ch DSCONL(2) F2Ch — F0Ch — EECh RPINR6 ECCh RPOR6 F4Bh DSWAKEH(2) F2Bh — F0Bh — EEBh — ECBh RPOR5 F4Ah DSWAKEL(2) F2Ah — F0Ah — EEAh RPINR4 ECAh RPOR4 F49h ANCON1 F29h — F09h — EE9h RPINR3 EC9h RPOR3 F48h ANCON0 F28h — F08h — EE8h RPINR2 EC8h RPOR2 F47h — F27h — F07h — EE7h RPINR1 EC7h RPOR1 F46h — F26h — F06h — EE6h — EC6h RPOR0 F45h — F25h — F05h — EE5h — EC5h — F44h — F24h — F04h — EE4h — EC4h — F43h — F23h — F03h — EE3h — EC3h — F42h ODCON1 F22h — F02h — EE2h — EC2h — F41h ODCON2 F21h — F01h — EE1h — EC1h — F40h ODCON3 F20h — F00h — EE0h — EC0h — Note 1: This register is not available on 28-pin devices. 2: Deep Sleep registers are not available on LF devices. DS39932D-page 88  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 6.3.4.1 Context Defined SFRs There are several registers that share the same address in the SFR space. The register’s definition and usage depends on the operating mode of its associated peripheral. These registers are: • SSPxADD and SSPxMSK: These are two separate hardware registers, accessed through a single SFR address. The operating mode of the MSSP modules determines which register is being accessed. See Section19.5.3.4 “7-Bit Address Masking Mode” for additional details. • PMADDRH/L and PMDOUT2H/L: In this case, these named buffer pairs are actually the same physical registers. The Parallel Master Port (PMP) module’s operating mode determines what func- tion the registers take on. See Section11.1.2 “Data Registers” for additional details.  2011 Microchip Technology Inc. DS39932D-page 89

PIC18F46J11 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 69, 81 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 69, 79 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 69, 79 STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 69, 80 PCLATU — — bit 21(1) Holding Register for PC<20:16> ---0 0000 69, 79 PCLATH Holding Register for PC<15:8> 0000 0000 69, 79 PCL PC Low Byte (PC<7:0>) 0000 0000 69, 79 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 69, 112 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 69, 112 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 69, 112 TABLAT Program Memory Table Latch 0000 0000 69, 112 PRODH Product Register High Byte xxxx xxxx 69, 69 PRODL Product Register Low Byte xxxx xxxx 69, 113 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 69, 117 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 69, 118 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 69, 119 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 69, 98 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 69, 99 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 69, 99 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 69, 99 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value N/A 69, 99 of FSR0 offset by W FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 69, 98 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 69, 98 WREG Working Register xxxx xxxx 69, 81 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 69, 98 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 69, 99 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 69, 99 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 69, 99 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value N/A 69, 99 of FSR1 offset by W FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 69, 98 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 69, 98 BSR — — — — Bank Select Register ---- 0000 69, 84 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 69, 98 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 70, 99 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 70, 99 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 70, 99 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value N/A 70, 99 of FSR2 offset by W FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 70, 98 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 70, 98 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes. 2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.5.3.2 “Address Masking Modes” for details. 5: These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 44-pin devices. 6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information. DS39932D-page 90  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: STATUS — — — N OV Z DC C ---x xxxx 70, 96 TMR0H Timer0 Register High Byte 0000 0000 70 TMR0L Timer0 Register Low Byte xxxx xxxx 70 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 70, 197 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS(2) — SCS1 SCS0 0110 q-00 70, 44 CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 70, 362 CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 70, 362 RCON IPEN — CM RI TO PD POR BOR 0-11 1100 70, 129 TMR1H Timer1 Register High Byte xxxx xxxx 70 TMR1L Timer1 Register Low Byte xxxx xxxx 70 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON 0000 0000 70, 201 TMR2 Timer2 Register 0000 0000 70 PR2 Timer2 Period Register 1111 1111 70 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 70, 213 SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 70 SSP1ADD MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) 0000 0000 70 SSP1MSK(4) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 70, 295 SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 70, 292 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 70, 293 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 70, 294 GCEN ACKSTAT ADMSK5(4) ADMSK4(4) ADMSK3(4) ADMSK2(4) ADMSK1(4) SEN ADRESH A/D Result Register High Byte xxxx xxxx 70 ADRESL A/D Result Register Low Byte xxxx xxxx 70 ADCON0 VCFG1 VCFG0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 70, 351 ADCON1 ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0000 0000 70, 352 WDTCON REGSLP LVDSTAT ULPLVL — DS ULPEN ULPSINK SWDTEN 1qq- q00 70, 406 PSTR1CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 00-0 0001 70, 267 ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 70 ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 71 CCPR1H Capture/Compare/PWM Register 1 HIgh Byte xxxx xxxx 71 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 71 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 71 PSTR2CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 00-0 0001 71, 267 ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 71 ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 71 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 71 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 71 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 71 CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN — 0-00 000- 71 CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 00xx 71 CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 0000 0000 71 SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 71 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes. 2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.5.3.2 “Address Masking Modes” for details. 5: These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 44-pin devices. 6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information.  2011 Microchip Technology Inc. DS39932D-page 91

PIC18F46J11 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: RCREG1 EUSART1 Receive Register 0000 0000 71 TXREG1 EUSART1 Transmit Register 0000 0000 71 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 71, 328 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 71, 329 SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 71 RCREG2 EUSART2 Receive Register 0000 0000 71 TXREG2 EUSART2 Transmit Register 0000 0000 71 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 71, 328 EECON2 Program Memory Control Register 2 (not a physical register) ---- ---- 71 EECON1 — — WPROG FREE WRERR WREN WR — --00 x00- 71, 105 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 1111 1111 71, 128 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 0000 0000 71, 122 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 0000 0000 71, 125 IPR2 OSCFIP CM2IP CM1IP — BCL1IP LVDIP TMR3IP CCP2IP 111- 1111 71, 127 PIR2 OSCFIF CM2IF CM1IF — BCL1IF LVDIF TMR3IF CCP2IF 000- 0000 71, 121 PIE2 OSCFIE CM2IE CM1IE — BCL1IE LVDIE TMR3IE CCP2IE 000- 0000 71, 124 IPR1 PMPIP(5) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 71, 126 PIR1 PMPIF(5) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 71, 120 PIE1 PMPIE(5) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 71, 123 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 72, 329 OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 72, 42 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 0000 0x00 72, 202 T1DONE RTCVALH RTCC Value Register Window High Byte, Based on RTCPTR<1:0> 0xxx xxxx 72 RTCVALL RTCC Value Register Window Low Byte, Based on RTCPTR<1:0> 0xxx xxxx 72 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS1 T3GSS0 0000 0x00 72, 216 T3DONE TRISE — — — — — TRISE2 TRISE1 TRISE0 ---- -111 72 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 72 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 72 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 72 TRISA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 111- 1111 72 ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000 0000 72, 231 ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 0000 72, 232 ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0> xxxx xxxx 72 ALRMVALL Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0> xxxx xxxx 72 LATE — — — — — LATE2 LATE1 LATE0 ---- -xxx 72 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 72 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 72 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 72 LATA LATA7 LATA6 LATA5 — LATA3 LATA2 LATA1 LATA0 xxx- xxxx 72 DMACON1 SSCON1 SSCON0 TXINC RXINC DUPLEX1 DUPLEX0 DLYINTEN DMAEN 0000 0000 72, 284 DMATXBUF SPI DMA Transmit Buffer xxxx xxxx 72 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes. 2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.5.3.2 “Address Masking Modes” for details. 5: These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 44-pin devices. 6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information. DS39932D-page 92  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: DMACON2 DLYCYC3 DLYCYC2 DLYCYC1 DLYCYC0 INTLVL3 INTLVL2 INTLVL1 INTLVL0 0000 0000 72, 285 HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 0000 72 PORTE RDPU REPU — — — RE2 RE1 RE0 00-- -xxx 72 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 72 PORTC RC7 RC6 RC5 RC4 RC4 RC2 RC1 RC0 xxxx xxxx 72 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 72 PORTA RA7 RA6 RA5 — RA3 RA2 RA1 RA0 xxx- xxxx 72 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 72 BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 72, 330 SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 72 BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 72, 330 TMR3H Timer3 Register High Byte xxxx xxxx 73 TMR3L Timer3 Register Low Byte xxxx xxxx 73 T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 — T3SYNC RD16 TMR3ON 0000 -000 73, 215 TMR4 Timer4 Register 0000 0000 73 PR4 Timer4 Period Register 1111 1111 73 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 73, 225 SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 73 SSP2ADD/ MSSP2 Address Register (I2C™ Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) 0000 0000 73, 295 SSP2MSK(4) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 73, 295 SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 73, 273 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 73, 293 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 73, 294 GCEN ACKSTAT ADMSK5(4) ADMSK4(4) ADMSK3(4) ADMSK2(4) ADMSK1(4) SEN CMSTAT — — — — — — COUT2 COUT1 ---- --11 73, 363 PMADDRH/ — CS1 Parallel Master Port Address High Byte -000 0000 73, 179 PMDOUT1H(5) Parallel Port Out Data High Byte (Buffer 1) 0000 0000 73, 179 PMADDRL/ Parallel Master Port Address Low Byte 0000 0000 73, 179 PMDOUT1L(5) Parallel Port Out Data Low Byte (Buffer 0) 0000 0000 73, 179 PMDIN1H(5) Parallel Port In Data High Byte (Buffer 1) 0000 0000 73 PMDIN1L(5) Parallel Port In Data Low Byte (Buffer 0) 0000 0000 73 TXADDRL SPI DMA Transit Data Pointer Low Byte 0000 0000 73 TXADDRH — — — — SPI DMA Transit Data Pointer High Byte ---- 0000 73 RXADDRL SPI DMA Receive Data Pointer Low Byte 0000 0000 73 RXADDRH — — — — SPI DMA Receive Data Pointer High Byte ---- 0000 73 DMABCL SPI DMA Byte Count Low Byte 0000 0000 73 DMABCH — — — — — — SPI DMA Receive Data ---- --00 73 Pointer High Byte PMCONH(5) PMPEN — — ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 0--0 0000 73, 172 PMCONL(5) CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 000- 0000 73, 173 PMMODEH(5) BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 0000 0000 73, 174 PMMODEL(5) WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000 0000 73, 175 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes. 2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.5.3.2 “Address Masking Modes” for details. 5: These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 44-pin devices. 6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information.  2011 Microchip Technology Inc. DS39932D-page 93

PIC18F46J11 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: PMDOUT2H(5) Parallel Port Out Data High Byte (Buffer 3) 0000 0000 73 PMDOUT2L(5) Parallel Port Out Data Low Byte (Buffer 2) 0000 0000 73 PMDIN2H(5) Parallel Port In Data High Byte (Buffer 3) 0000 0000 73 PMDIN2L(5) Parallel Port In Data Low Byte (Buffer 2) 0000 0000 73 PMEH(5) PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 0000 0000 73, 176 PMEL(5) PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000 0000 73, 176 PMSTATH(5) IBF IBOV — — IB3F IB2F IB1F IB0F 00-- 0000 73, 177 PMSTATL(5) OBE OBUF — — OB3E OB2E OB1E OB0E 10-- 1111 73, 177 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 73, 370 TCLKCON — — — T1RUN — — T3CCP2 T3CCP1 ---0 --00 203 DSGPR1 Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) uuuu uuuu 59 DSGPR0 Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) uuuu uuuu 59 DSCONH DSEN — — — — (Reserved) DSULPEN RTCWDIS 0--- -000 58 DSCONL — — — — — ULPWDIS DSBOR RELEASE ---- -000 58 DSWAKEH — — — — — — — DSINT0 ---- ---0 60 DSWAKEL DSFLT — DSULP DSWDT DSRTC DSMCLR — DSPOR 0-00 00-1 60 ANCON1 VBGEN r — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 00-0 0000 73, 353 ANCON0 PCFG7(5) PCFG6(5) PCFG5(5) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 73, 353 ODCON1 — — — — — — ECCP20D ECCP10D ---- --00 73, 133 ODCON2 — — — — — — U2OD U1OD ---- --00 73, 133 ODCON3 — — — — — — SPI2OD SPI1OD ---- --00 73, 134 RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0-00 0000 73, 229 RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 0000 73, 230 REFOCON ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 0-00 0000 73, 45 PADCFG1 — — — — — RTSECSEL1 RTSECSEL0 PMPTTL ---- -000 73, 134 PPSCON — — — — — — — IOLOCK ---- ---0 155 RPINR24 — — — Input Function FLT0 to Input Pin Mapping Bits ---1 1111 74, 160 RPINR23 — — — Input Function SS2 to Input Pin Mapping Bits ---1 1111 74, 160 RPINR22 — — — Input Function SCK2 to Input Pin Mapping Bits ---1 1111 74, 160 RPINR21 — — — Input Function SDI2 to Input Pin Mapping Bits ---1 1111 74, 159 RPINR17 — — — Input Function CK2 to Input Pin Mapping Bits ---1 1111 74, 159 RPINR16 — — — Input Function RX2DT2 to Input Pin Mapping Bits ---1 1111 159 RPINR13 — — — Input Function T3G to Input Pin Mapping Bits ---1 1111 75, 158 RPINR12 — — — Input Function T1G to Input Pin Mapping Bits ---1 1111 75, 158 RPINR8 — — — Input Function IC2 to Input Pin Mapping Bits ---1 1111 75, 158 RPINR7 — — — Input Function IC1 to Input Pin Mapping Bits ---1 1111 75, 157 RPINR6 — — — Input Function T3CKI to Input Pin Mapping Bits ---1 1111 75, 157 RPINR4 — — — Input Function T0CKI to Input Pin Mapping Bits ---1 1111 75, 157 RPINR3 — — — Input Function INT3 to Input Pin Mapping Bits ---1 1111 75, 156 RPINR2 — — — Input Function INT2 to Input Pin Mapping Bits ---1 1111 75 RPINR1 — — — Input Function INT1 to Input Pin Mapping Bits ---1 1111 75, 156 RPOR24(5) — — — Remappable Pin RP24 Output Signal Select Bits ---0 0000 74, 169 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes. 2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.5.3.2 “Address Masking Modes” for details. 5: These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 44-pin devices. 6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information. DS39932D-page 94  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) Details Value on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on POR, BOR Page: RPOR23(5) — — — Remappable Pin RP23 Output Signal Select Bits ---0 0000 74, 169 RPOR22(5) — — — Remappable Pin RP22 Output Signal Select Bits ---0 0000 74, 168 RPOR21(5) — — — Remappable Pin RP21 Output Signal Select Bits ---0 0000 74, 168 RPOR20(5) — — — Remappable Pin RP20 Output Signal Select Bits ---0 0000 74, 168 RPOR19(5) — — — Remappable Pin RP19 Output Signal Select Bits ---0 0000 74, 167 RPOR18 — — — Remappable Pin RP18 Output Signal Select Bits ---0 0000 74, 167 RPOR17 — — — Remappable Pin RP17 Output Signal Select Bits ---0 0000 75, 167 RPOR16 — — — Remappable Pin RP16 Output Signal Select Bits ---0 0000 75, 166 RPOR15 — — — Remappable Pin RP15 Output Signal Select Bits ---0 0000 75, 166 RPOR14 — — — Remappable Pin RP14 Output Signal Select Bits ---0 0000 75, 166 RPOR13 — — — Remappable Pin RP13 Output Signal Select Bits ---0 0000 75, 165 RPOR12 — — — Remappable Pin RP12 Output Signal Select Bits ---0 0000 75, 165 RPOR11 — — — Remappable Pin RP11 Output Signal Select Bits ---0 0000 75, 165 RPOR10 — — — Remappable Pin RP10 Output Signal Select Bits ---0 0000 75, 164 RPOR9 — — — Remappable Pin RP9 Output Signal Select Bits ---0 0000 75, 164 RPOR8 — — — Remappable Pin RP8 Output Signal Select Bits ---0 0000 75, 163 RPOR7 — — — Remappable Pin RP7 Output Signal Select Bits ---0 0000 75, 163 RPOR6 — — — Remappable Pin RP6 Output Signal Select Bits ---0 0000 75, 163 RPOR5 — — — Remappable Pin RP5 Output Signal Select Bits ---0 0000 75, 162 RPOR4 — — — Remappable Pin RP4 Output Signal Select Bits ---0 0000 75, 162 RPOR3 — — — Remappable Pin RP3 Output Signal Select Bits ---0 0000 75, 162 RPOR2 — — — Remappable Pin RP2 Output Signal Select Bits ---0 0000 75, 161 RPOR1 — — — Remappable Pin RP1 Output Signal Select Bits ---0 0000 75, 161 RPOR0 — — — Remappable Pin RP0 Output Signal Select Bits ---0 0000 75, 161 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs. Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes. 2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section19.5.3.2 “Address Masking Modes” for details. 5: These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for 44-pin devices. 6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different functions determined by the module’s operating mode. See Section11.1.2 “Data Registers” for more information.  2011 Microchip Technology Inc. DS39932D-page 95

PIC18F46J11 FAMILY 6.3.5 STATUS REGISTER register then reads back as ‘000u u1uu’. It is recom- mended, therefore, that only BCF, BSF, SWAPF, MOVFF The STATUS register in Register6-2, contains the and MOVWF instructions are used to alter the STATUS arithmetic status of the ALU. The STATUS register can register because these instructions do not affect the Z, be the operand for any instruction, as with any other C, DC, OV or N bits in the STATUS register. register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then For other instructions not affecting any Status bits, see the write to these five bits is disabled. the instruction set summary in Table27-2 and Table27-3. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the Note: The C and DC bits operate as a borrow STATUS register as destination may be different than and digit borrow bits respectively, in intended. For example, CLRF STATUS will set the Z bit subtraction. but leave the other bits unchanged. The STATUS REGISTER 6-2: STATUS REGISTER (ACCESS FD8h) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the MSb of the result occurred 0 = No carry-out from the MSb of the result occurred Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. DS39932D-page 96  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 6.4 Data Addressing Modes Register File”), or a location in the Access Bank (Section6.3.2 “Access Bank”) as the data source for Note: The execution of some instructions in the the instruction. core PIC18 instruction set is changed The Access RAM bit, ‘a’, determines how the address when the PIC18 extended instruction set is is interpreted. When ‘a’ is ‘1’, the contents of the BSR enabled. See Section6.6 “Data Memory (Section6.3.1 “Bank Select Register”) are used with and the Extended Instruction Set” for the address to determine the complete 12-bit address more information. of the register. When ‘a’ is ‘0’, the address is interpreted While the program memory can be addressed in only as being a register in the Access Bank. Addressing that one way, through the PC, information in the data uses the Access RAM is sometimes also known as memory space can be addressed in several ways. For Direct Forced Addressing mode. most instructions, the addressing mode is fixed. Other A few instructions, such as MOVFF, include the entire instructions may use up to three modes, depending on 12-bit address (either source or destination) in their which operands are used and whether or not the opcodes. In these cases, the BSR is ignored entirely. extended instruction set is enabled. The destination of the operation’s results is determined The addressing modes are: by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are • Inherent stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored • Literal in the W register. Instructions without the ‘d’ argument • Direct have a destination that is implicit in the instruction; their • Indirect destination is either the target register being operated An additional addressing mode, Indexed Literal Offset, on or the W register. is available when the extended instruction set is 6.4.3 INDIRECT ADDRESSING enabled (XINST Configuration bit = 1). Its operation is discussed in more detail in Section6.6.1 “Indexed Indirect Addressing allows the user to access a location Addressing with Literal Offset”. in data memory without giving a fixed address in the instruction. This is done by using File Select Registers 6.4.1 INHERENT AND LITERAL (FSRs) as pointers to the locations to be read or written ADDRESSING to. Since the FSRs are themselves located in RAM as Many PIC18 control instructions do not need any SFRs, they can also be directly manipulated under argument at all; they either perform an operation that program control. This makes FSRs very useful in globally affects the device, or they operate implicitly on implementing data structures such as tables and arrays one register. This addressing mode is known as in data memory. Inherent Addressing. Examples include SLEEP, RESET The registers for Indirect Addressing are also and DAW. implemented with Indirect File Operands (INDFs) that Other instructions work in a similar way, but require an permit automatic manipulation of the pointer value with additional explicit argument in the opcode. This is auto-incrementing, auto-decrementing or offsetting known as Literal Addressing mode, because they with another value. This allows for efficient code using require some literal value as an argument. Examples loops, such as the example of clearing an entire RAM include ADDLW and MOVLW, which respectively, add or bank in Example6-5. It also enables users to perform move a literal value to the W register. Other examples Indexed Addressing and other Stack Pointer include CALL and GOTO, which include a 20-bit operations for program memory in data memory. program memory address. EXAMPLE 6-5: HOW TO CLEAR RAM 6.4.2 DIRECT ADDRESSING (BANK 1) USING INDIRECT ADDRESSING Direct Addressing specifies all or part of the source and/or destination address of the operation within the LFSR FSR0, 0x100; opcode itself. The options are specified by the NEXT CLRF POSTINC0 ; Clear INDF arguments accompanying the instruction. ; register then ; inc pointer In the core PIC18 instruction set, bit-oriented and BTFSS FSR0H, 1 ; All done with byte-oriented instructions use some version of Direct ; Bank1? Addressing by default. All of these instructions include BRA NEXT ; NO, clear next some 8-bit Literal Address as their LSB. This address CONTINUE ; YES, continue specifies either a register address in one of the banks of data RAM (Section6.3.3 “General Purpose  2011 Microchip Technology Inc. DS39932D-page 97

PIC18F46J11 FAMILY 6.4.3.1 FSR Registers and the INDF SFR space but are not physically implemented. Read- Operand (INDF) ing or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read At the core of Indirect Addressing are three sets of from INDF1, for example, reads the data at the address registers: FSR0, FSR1 and FSR2. Each represents a indicated by FSR1H:FSR1L. Instructions that use the pair of 8-bit registers, FSRnH and FSRnL. The four INDF registers as operands actually use the contents upper bits of the FSRnH register are not used, so each of their corresponding FSR as a pointer to the instruc- FSR pair holds a 12-bit value. This represents a value tion’s target. The INDF operand is just a convenient that can address the entire range of the data memory way of using the pointer. in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current Indirect Addressing is accomplished with a set of INDF contents of the BSR and the Access RAM bit have no operands, INDF0 through INDF2. These can be pre- effect on determining the target address. sumed to be “virtual” registers: they are mapped in the FIGURE 6-8: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 Indirect Addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 1 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains E00h FCCh. This means the contents of Bank 14 location FCCh will be added to that F00h of the W register and stored back in Bank 15 FCCh. FFFh Data Memory DS39932D-page 98  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 6.4.3.2 FSR Registers and POSTINC, Since the FSRs are physical registers mapped in the POSTDEC, PREINC and PLUSW SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when In addition to the INDF operand, each FSR register pair working on these registers, particularly if their code also has four additional indirect operands. Like INDF, uses Indirect Addressing. these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually Similarly, operations by Indirect Addressing are gener- accesses the associated FSR register pair, but also ally permitted on all other SFRs. Users should exercise performs a specific action on its stored value. They are: appropriate caution that they do not inadvertently change settings that might affect the operation of the • POSTDEC: accesses the FSR value, then device. automatically decrements it by ‘1’ thereafter • POSTINC: accesses the FSR value, then 6.5 Program Memory and the automatically increments it by ‘1’ thereafter Extended Instruction Set • PREINC: increments the FSR value by ‘1’, then uses it in the operation The operation of program memory is unaffected by the • PLUSW: adds the signed value of the W register use of the extended instruction set. (range of -128 to 127) to that of the FSR and uses Enabling the extended instruction set adds five the new value in the operation additional two-word commands to the existing PIC18 In this context, accessing an INDF register uses the instruction set: ADDFSR, CALLW, MOVSF, MOVSS and value in the FSR registers without changing them. SUBFSR. These instructions are executed as described Similarly, accessing a PLUSW register gives the FSR in Section6.2.4 “Two-Word Instructions”. value offset by the value in the W register; neither value is actually changed in the operation. Accessing the 6.6 Data Memory and the Extended other virtual registers changes the value of the FSR Instruction Set registers. Enabling the PIC18 extended instruction set (XINST Operations on the FSRs with POSTDEC, POSTINC Configuration bit = 1) significantly changes certain and PREINC affect the entire register pair; that is, roll- aspects of data memory and its addressing. Specifically, overs of the FSRnL register from FFh to 00h carry over the use of the Access Bank for many of the core PIC18 to the FSRnH register. On the other hand, results of instructions is different. This is due to the introduction of these operations do not change the value of any flags a new addressing mode for the data memory space. in the STATUS register (e.g., Z, N, OV, etc.). This mode also alters the behavior of Indirect The PLUSW register can be used to implement a form Addressing using FSR2 and its associated operands. of Indexed Addressing in the data memory space. By What does not change is just as important. The size of manipulating the value in the W register, users can the data memory space is unchanged, as well as its reach addresses that are fixed offsets from pointer linear addressing. The SFR map remains the same. addresses. In some applications, this can be used to Core PIC18 instructions can still operate in both Direct implement some powerful program control structure, and Indirect Addressing mode; inherent and literal such as software stacks, inside of data memory. instructions do not change at all. Indirect Addressing 6.4.3.3 Operations by FSRs on FSRs with FSR0 and FSR1 also remains unchanged. Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1, using INDF0 as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as the operand, will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to FSR2H:FSR2L.  2011 Microchip Technology Inc. DS39932D-page 99

PIC18F46J11 FAMILY 6.6.1 INDEXED ADDRESSING WITH 6.6.2 INSTRUCTIONS AFFECTED BY LITERAL OFFSET INDEXED LITERAL OFFSET MODE Enabling the PIC18 extended instruction set changes Any of the core PIC18 instructions that can use Direct the behavior of Indirect Addressing using the FSR2 Addressing are potentially affected by the Indexed register pair and its associated file operands. Under Literal Offset Addressing mode. This includes all byte proper conditions, instructions that use the Access and bit-oriented instructions, or almost one-half of the Bank, that is, most bit and byte-oriented instructions, standard PIC18 instruction set. Instructions that only can invoke a form of Indexed Addressing using an use Inherent or Literal Addressing modes are offset specified in the instruction. This special address- unaffected. ing mode is known as Indexed Addressing with Literal Additionally, byte and bit-oriented instructions are not Offset, or Indexed Literal Offset mode. affected if they do not use the Access Bank (Access When using the extended instruction set, this RAM bit is ‘1’) or include a file address of 60h or above. addressing mode requires the following: Instructions meeting these criteria will continue to execute as before. A comparison of the different possi- • The use of the Access Bank is forced (‘a’ = 0); ble addressing modes when the extended instruction set and is enabled is provided in Figure6-9. • The file address argument is less than or equal to 5Fh. Those who desire to use byte or bit-oriented instruc- tions in the Indexed Literal Offset mode should note the Under these conditions, the file address of the instruc- changes to assembler syntax for this mode. This is tion is not interpreted as the lower byte of an address described in more detail in Section27.2.1 “Extended (used with the BSR in Direct Addressing) or as an 8-bit Instruction Syntax”. address in the Access Bank. Instead, the value is inter- preted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. DS39932D-page 100  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When a = 0 and f  60h: The instruction executes in 060h Direct Forced mode. ‘f’ is Bank 0 interpreted as a location in the 100h Access RAM between 060h 00h and FFFh. This is the same as Bank 1 through 60h locations F60h to FFFh Bank 14 (Bank15) of data memory. Valid range for ‘f’ Locations below 060h are not FFh available in this addressing F00h Access RAM mode. Bank 15 F60h SFRs FFFh Data Memory When a = 0 and f5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 060h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is: F60h ADDWF [k], d SFRs where ‘k’ is same as ‘f’. FFFh Data Memory BSR When a = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 060h Direct mode (also known as Direct Long mode). ‘f’ is 100h interpreted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F60h SFRs FFFh Data Memory  2011 Microchip Technology Inc. DS39932D-page 101

PIC18F46J11 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue The use of Indexed Literal Offset Addressing mode to use Direct Addressing as before. Any Indirect or effectively changes how the lower part of Access RAM Indexed Addressing operation that explicitly uses any (00h to 5Fh) is mapped. Rather than containing just the of the indirect file operands (including FSR2) will con- contents of the bottom part of Bank 0, this mode maps tinue to operate as standard Indirect Addressing. Any the contents from Bank 0 and a user-defined “window” instruction that uses the Access Bank, but includes a that can be located anywhere in the data memory register address of greater than 05Fh, will use Direct space. The value of FSR2 establishes the lower Addressing and the normal Access Bank map. boundary of the addresses mapped to the window, while the upper boundary is defined by FSR2 plus 95 6.6.4 BSR IN INDEXED LITERAL OFFSET (5Fh). Addresses in the Access RAM above 5Fh are MODE mapped as previously described (see Section6.3.2 “Access Bank”). Figure6-10 provides an example of Although the Access Bank is remapped when the Access Bank remapping in this addressing mode. extended instruction set is enabled, the operation of the BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. FIGURE 6-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a Not Accessible FSR2H:FSR2L = 120h 05Fh Locations in the region Bank 0 from the FSR2 Pointer 100h (120h) to the pointer plus 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Bank 1 “Window” Access RAM (000h-05Fh). 200h 5Fh Special Function Registers 60h at F60h through FFFh are mapped to 60h through Bank 2 FFh, as usual. through SFRs Bank 0 addresses below Bank 14 5Fh are not available in FFh this mode. They can still Access Bank be addressed by using the F00h BSR. Bank 15 F60h SFRs FFFh Data Memory DS39932D-page 102  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on 1 byte at • Table Read (TBLRD) a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 64 bytes at a time or 2 bytes at a time. The program memory space is 16 bits wide, while the Program memory is erased in blocks of 1024 bytes at data RAM space is 8 bits wide. Table reads and table a time. A bulk erase operation may not be issued from writes move data between these two memory spaces user code. through an 8-bit register (TABLAT). Writing or erasing program memory will cease Table read operations retrieve data from program instruction fetches until the operation is complete. The memory and place it into the data RAM space. program memory cannot be accessed during the write Figure7-1 illustrates the operation of a table read with or erase, therefore, code cannot execute. An internal program memory and data RAM. programming timer terminates program memory writes and erases. Table write operations store data from the data memory space into holding registers in program memory. The A value written to program memory does not need to be procedure to write the contents of the holding registers a valid instruction. Executing a program memory into program memory is detailed in Section7.5 “Writing location that forms an invalid instruction results in a to Flash Program Memory”. Figure7-2 illustrates the NOP. operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory.  2011 Microchip Technology Inc. DS39932D-page 103

PIC18F46J11 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section7.5 “Writing to Flash Program Memory”. 7.2 Control Registers The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase Several control registers are used in conjunction with operation is initiated on the next WR command. When the TBLRD and TBLWT instructions. Those are: FREE is clear, only writes are enabled. • EECON1 register The WREN bit, when set, will allow a write operation. • EECON2 register On power-up, the WREN bit is clear. The WRERR bit is • TABLAT register set in hardware when the WR bit is set, and cleared • TBLPTR registers when the internal programming timer expires and the write operation is complete. 7.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is The EECON1 register (Register7-1) is the control read as ‘1’. This can indicate that a write register for memory accesses. The EECON2 register is operation was prematurely terminated by not a physical register; it is used exclusively in the a Reset, or a write operation was memory write and erase sequences. Reading attempted improperly. EECON2 will read all ‘0’s. The WR control bit initiates write operations. The bit The WPROG bit, when set, will allow programming cannot be cleared, only set, in software. It is cleared in twobytes per word on the execution of the WR hardware at the completion of the write operation. command. If this bit is cleared, the WR command will result in programming on a block of 64 bytes. DS39932D-page 104  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 (ACCESS FA6h) U-0 U-0 R/W-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 — — WPROG FREE WRERR WREN WR — bit 7 bit 0 Legend: S = Settable bit (cannot be cleared in software) R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 WPROG: One Word-Wide Program bit 1 = Program 2 bytes on the next WR command 0 = Program 64 bytes on the next WR command bit 4 FREE: Flash Erase Enable bit 1 = Perform an erase operation on the next WR command (cleared by hardware after completion of erase) 0 = Perform write only bit 3 WRERR: Flash Program Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program Write Enable bit 1 = Allows write cycles to Flash program memory 0 = Inhibits write cycles to Flash program memory bit 1 WR: Write Control bit 1 = Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is complete bit 0 Unimplemented: Read as ‘0’  2011 Microchip Technology Inc. DS39932D-page 105

PIC18F46J11 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the Special Function Register (SFR) space. The Flash program memory. Table Latch register is used to hold 8-bit data during When a TBLRD is executed, all 22 bits of the TBLPTR data transfers between program memory and data determine which byte is read from program memory RAM. into TABLAT. 7.2.3 TABLE POINTER REGISTER When a TBLWT is executed, the seven Least Significant (TBLPTR) bits (LSbs) of the Table Pointer register (TBLPTR<6:0>) determine which of the 64 program memory holding The Table Pointer (TBLPTR) register addresses a byte registers is written to. When the timed write to program within the program memory. The TBLPTR is comprised memory begins (via the WR bit), the 12 Most Significant of three SFR registers: Table Pointer Upper Byte, Table bits (MSbs) of the TBLPTR (TBLPTR<21:10>) Pointer High Byte and Table Pointer Low Byte determine which program memory block of 1024 bytes (TBLPTRU:TBLPTRH:TBLPTRL). These three registers is written to. For more information, see Section7.5 join to form a 22-bit wide pointer. The low-order 21bits “Writing to Flash Program Memory”. allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device When an erase of program memory is executed, the ID, the user ID and the Configuration bits. 12MSbs of the Table Pointer register point to the 1024-byte block that will be erased. The LSbs are The Table Pointer register, TBLPTR, is used by the ignored. TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the Figure7-3 illustrates the relevant boundaries of table operation. TBLPTR based on Flash program memory operations. Table7-1 provides these operations. These operations on the TBLPTR only affect the low-order 21bits. TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE: TBLPTR<20:10> TABLE WRITE: TBLPTR<20:6> TABLE READ: TBLPTR<21:0> DS39932D-page 106  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 7.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The LSb of the address selects between the high a time. and low bytes of the word. Figure7-4 illustrates the interface between the internal program memory and the TABLAT. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT (IR) FETCH TBLRD Read Register EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_ODD  2011 Microchip Technology Inc. DS39932D-page 107

PIC18F46J11 FAMILY 7.4 Erasing Flash Program Memory 7.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or The sequence of events for erasing a block of internal through ICSP control, can larger blocks of program program memory location is: memory be bulk erased. Word erase in the Flash array 1. Load Table Pointer register with address of row is not supported. being erased. When initiating an erase sequence from the micro- 2. Set the WREN and FREE bits (EECON1<2,4>) controller itself, a block of 1024 bytes of program to enable the erase operation. memory is erased. The Most Significant 12 bits of the 3. Disable interrupts. TBLPTR<21:10> point to the block being erased. 4. Write 55h to EECON2. TBLPTR<9:0> are ignored. 5. Write 0AAh to EECON2. The EECON1 register commands the erase operation. 6. Set the WR bit; this will begin the erase cycle. The WREN bit must be set to enable write operations. 7. The CPU will stall for the duration of the erase The FREE bit is set to select an erase operation. For for TIE (see parameter D133B). protection, the write initiate sequence for EECON2 8. Re-enable interrupts. must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 7-2: ERASING FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 0x55 Sequence MOVWF EECON2 ; write 55h MOVLW 0xAA MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS39932D-page 108  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 7.5 Writing to Flash Program Memory The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip The programming block is 32 words or 64 bytes. charge pump, rated to operate over the voltage range Programming one word or 2 bytes at a time is also of the device. supported. Note1: Unlike previous PIC® devices, devices of Table writes are used internally to load the holding the PIC18F46J11 family do not reset the registers needed to program the Flash memory. There holding registers after a write occurs. The are 64 holding registers used by the table writes for holding registers must be cleared or programming. overwritten before a programming Since the Table Latch (TABLAT) is only a single byte, the sequence. TBLWT instruction may need to be executed 64times for 2: To maintain the endurance of the pro- each programming operation (if WPROG = 0). All of the gram memory cells, each Flash byte table write operations will essentially be short writes should not be programmed more than because only the holding registers are written. At the once between erase operations. Before end of updating the 64 holding registers, the EECON1 attempting to modify the contents of the register must be written to in order to start the target cell a second time, an erase of the programming operation with a long write. target page, or a bulk erase of the entire The long write is necessary for programming the memory, must be performed. internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxx3F Holding Register Holding Register Holding Register Holding Register Program Memory 7.5.1 FLASH PROGRAM MEMORY WRITE 8. Disable interrupts. SEQUENCE 9. Write 55h to EECON2. The sequence of events for programming an internal 10. Write 0AAh to EECON2. program memory location should be: 11. Set the WR bit. This will begin the write cycle. 1. Read 1024 bytes into RAM. 12. The CPU will stall for the duration of the write for TIW (see parameter D133A). 2. Update data values in RAM as necessary. 13. Re-enable interrupts. 3. Load Table Pointer register with address being erased. 14. Repeat steps 6 through 13 until all 1024 bytes are written to program memory. 4. Execute the erase procedure. 15. Verify the memory (table read). 5. Load Table Pointer register with address of first byte being written, minus 1. An example of the required code is provided in 6. Write the 64 bytes into the holding registers with Example7-3 on the following page. auto-increment. Note: Before setting the WR bit, the Table 7. Set the WREN bit (EECON1<2>) to enable byte Pointer address needs to be within the writes. intended address range of the 64 bytes in the holding register.  2011 Microchip Technology Inc. DS39932D-page 109

PIC18F46J11 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base address MOVWF TBLPTRU ; of the memory block, minus 1 MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 0x55 MOVWF EECON2 ; write 55h MOVLW 0xAA MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts MOVLW D'16' MOVWF WRITE_COUNTER ; Need to write 16 blocks of 64 to write ; one erase block of 1024 RESTART_BUFFER MOVLW D'64' MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L FILL_BUFFER ... ; read the new data from I2C, SPI, ; PSP, USART, etc. WRITE_BUFFER MOVLW D’64’ ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS MOVFF POSTINC0, WREG ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_BYTE_TO_HREGS PROGRAM_MEMORY BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 0x55 Required MOVWF EECON2 ; write 55h Sequence MOVLW 0xAA MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory DECFSZ WRITE_COUNTER ; done with one write cycle BRA RESTART_BUFFER ; if not done replacing the erase block DS39932D-page 110  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 7.5.2 FLASH PROGRAM MEMORY WRITE 3. Set the WREN bit (EECON1<2>) to enable SEQUENCE (WORD PRORAMMING). writes and the WPROG bit (EECON1<5>) to select Word Write mode. The PIC18F46J11 family of devices has a feature that 4. Disable interrupts. allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the 5. Write 55h to EECON2. memory location is already erased, the following 6. Write 0AAh to EECON2. sequence is required to enable this feature: 7. Set the WR bit; this will begin the write cycle. 1. Load the Table Pointer register with the address 8. The CPU will stall for the duration of the write for of the data to be written. (It must be an even TIW (see parameter D133A). address.) 9. Re-enable interrupts. 2. Write the 2 bytes into the holding registers by performing table writes. (Do not post-increment on the second table write.) EXAMPLE 7-4: SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base address MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW ; The table pointer must be loaded with an even address MOVWF TBLPTRL MOVLW DATA0 ; LSB of word to be written MOVWF TABLAT TBLWT*+ MOVLW DATA1 ; MSB of word to be written MOVWF TABLAT TBLWT* ; The last table write must not increment the table pointer! The table pointer needs to point to the MSB before starting the write operation. PROGRAM_MEMORY BSF EECON1, WPROG ; enable single word write BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 0x55 Required MOVWF EECON2 ; write 55h Sequence MOVLW 0xAA MOVWF EECON2 ; write AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WPROG ; disable single word write BCF EECON1, WREN ; disable write to memory  2011 Microchip Technology Inc. DS39932D-page 111

PIC18F46J11 FAMILY 7.5.3 WRITE VERIFY reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT time-out Reset Depending on the application, good programming during normal operation, the user can check the practice may dictate that the value written to the WRERR bit and rewrite the location(s) as needed. memory should be verified against the original value. This should be used in applications where excessive 7.6 Flash Program Operation During writes can stress bits near the specification limit. Code Protection 7.5.4 UNEXPECTED TERMINATION OF See Section26.6 “Program Verification and Code WRITE OPERATION Protection” for details on code protection of Flash If a write is terminated by an unplanned event, such as program memory. loss of power or an unexpected Reset, the memory location just programmed should be verified and TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 69 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 69 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 69 TABLAT Program Memory Table Latch 69 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 EECON2 Program Memory Control Register 2 (not a physical register) 71 EECON1 — — WPROG FREE WRERR WREN WR — 71 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access. DS39932D-page 112  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 8.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 8-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 8.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY operation does not affect any flags in the STATUS ROUTINE register. MOVF ARG1, W Making multiplication a hardware operation allows it to MULWF ARG2 ; ARG1 * ARG2 -> be completed in a single instruction cycle. This has the ; PRODH:PRODL advantages of higher computational throughput and BTFSC ARG2, SB ; Test Sign Bit reduced code size for multiplication algorithms and SUBWF PRODH, F ; PRODH = PRODH allows the PIC18 devices to be used in many applica- ; - ARG1 tions previously reserved for digital signal processors. MOVF ARG2, W BTFSC ARG1, SB ; Test Sign Bit Table8-1 provides a comparison of various hardware SUBWF PRODH, F ; PRODH = PRODH and software multiply operations, along with the ; - ARG2 savings in memory and execution time. 8.2 Operation Example8-1 provides the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example8-2 provides the instruction sequence for an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 48 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 5.7 s 27.6 s 69 s 8 x 8 unsigned Hardware multiply 1 1 83.3 ns 400 ns 1 s Without hardware multiply 33 91 7.5 s 36.4 s 91 s 8 x 8 signed Hardware multiply 6 6 500 ns 2.4 s 6 s Without hardware multiply 21 242 20.1 s 96.8 s 242 s 16 x 16 unsigned Hardware multiply 28 28 2.3 s 11.2 s 28 s Without hardware multiply 52 254 21.6 s 102.6 s 254 s 16 x 16 signed Hardware multiply 35 40 3.3 s 16.0 s 40 s  2011 Microchip Technology Inc. DS39932D-page 113

PIC18F46J11 FAMILY Example8-3 provides the instruction sequence for a EQUATION 8-2: 16 x 16 SIGNED 16x 16 unsigned multiplication. Equation8-1 provides MULTIPLICATION the algorithm that is used. The 32-bit result is stored in ALGORITHM four registers (RES<3:0>). RES3:RES0 = ARG1H:ARG1L · ARG2H:ARG2L = (ARG1H · ARG2H · 216) + EQUATION 8-1: 16 x 16 UNSIGNED (ARG1H · ARG2L · 28) + MULTIPLICATION (ARG1L · ARG2H · 28) + ALGORITHM (ARG1L · ARG2L) + (-1 · ARG2H<7> · ARG1H:ARG1L · 216) + RES3:RES0 = ARG1H:ARG1L · ARG2H:ARG2L (-1 · ARG1H<7> · ARG2H:ARG2L · 216) = (ARG1H · ARG2H · 216) + (ARG1H · ARG2L · 28) + (ARG1L · ARG2H · 28) + (ARG1L · ARG2L) EXAMPLE 8-4: 16 x 16 SIGNED MULTIPLY ROUTINE EXAMPLE 8-3: 16 x 16 UNSIGNED MOVF ARG1L, W MULTIPLY ROUTINE MULWF ARG2L ; ARG1L * ARG2L -> ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES1 ; MULWF ARG2L ; ARG1L * ARG2L-> MOVFF PRODL, RES0 ; ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1H, W MOVFF PRODL, RES0 ; MULWF ARG2H ; ARG1H * ARG2H -> ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1H * ARG2H-> MOVFF PRODL, RES2 ; ; PRODH:PRODL MOVFF PRODH, RES3 ; MOVF ARG1L, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1L * ARG2H -> ; PRODH:PRODL MOVF ARG1L, W MOVF PRODL, W ; MULWF ARG2H ; ARG1L * ARG2H-> ADDWF RES1, F ; Add cross ; PRODH:PRODL MOVF PRODH, W ; products MOVF PRODL, W ; ADDWFC RES2, F ; ADDWF RES1, F ; Add cross CLRF WREG ; MOVF PRODH, W ; products ADDWFC RES3, F ; ADDWFC RES2, F ; CLRF WREG ; MOVF ARG1H, W ; ADDWFC RES3, F ; MULWF ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL MOVF ARG1H, W ; MOVF PRODL, W ; MULWF ARG2L ; ARG1H * ARG2L-> ADDWF RES1, F ; Add cross ; PRODH:PRODL MOVF PRODH, W ; products MOVF PRODL, W ; ADDWFC RES2, F ; ADDWF RES1, F ; Add cross CLRF WREG ; MOVF PRODH, W ; products ADDWFC RES3, F ; ADDWFC RES2, F ; CLRF WREG ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? ADDWFC RES3, F ; BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L, W ; Example8-4 provides the sequence to do a 16 x 16 SUBWF RES2 ; signed multiply. Equation8-2 provides the algorithm MOVF ARG1H, W ; used. The 32-bit result is stored in four registers SUBWFB RES3 (RES<3:0>). To account for the sign bits of the arguments, the MSb for each argument pair is tested SIGN_ARG1 BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? and the appropriate subtractions are done. BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 CONT_CODE : DS39932D-page 114  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 9.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are Devices of the PIC18F46J11 family have multiple inter- compatible with PIC® mid-range devices. In rupt sources and an interrupt priority feature that allows Compatibility mode, the interrupt priority bits for each most interrupt sources to be assigned a high-priority source have no effect. INTCON<6> is the PEIE bit, level or a low-priority level. The high-priority interrupt which enables/disables all peripheral interrupt sources. vector is at 0008h and the low-priority interrupt vector INTCON<7> is the GIE bit, which enables/disables all is at 0018h. High-priority interrupt events will interrupt interrupt sources. All interrupts branch to address any low-priority interrupts that may be in progress. 0008h in Compatibility mode. There are 13 registers, which are used to control When an interrupt is responded to, the Global Interrupt interrupt operation. These registers are: Enable bit is cleared to disable further interrupts. If the • RCON IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. • INTCON High-priority interrupt sources can interrupt a • INTCON2 low-priority interrupt. Low-priority interrupts are not • INTCON3 processed while high-priority interrupts are in progress. • PIR1, PIR2, PIR3 The return address is pushed onto the stack and the • PIE1, PIE2, PIE3 PC is loaded with the interrupt vector address (0008h • IPR1, IPR2, IPR3 or 0018h). Once in the Interrupt Service Routine, the It is recommended that the Microchip header files source(s) of the interrupt can be determined by polling supplied with MPLAB® IDE be used for the symbolic bit the interrupt flag bits. The interrupt flag bits must be names in these registers. This allows the cleared in software before re-enabling interrupts to assembler/compiler to automatically take care of the avoid recursive interrupts. placement of these bits within the specified register. The “return from interrupt” instruction, RETFIE, exits In general, interrupt sources have three bits to control the interrupt routine and sets the GIE bit (GIEH or GIEL their operation. They are: if priority levels are used), which re-enables interrupts. • Flag bit to indicate that an interrupt event For external interrupt events, such as the INTx pins or occurred the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact • Enable bit that allows program execution to latency is the same for one or two-cycle instructions. branch to the interrupt vector address when the Individual interrupt flag bits are set regardless of the flag bit is set status of their corresponding enable bit or the GIE bit. • Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to mod- The interrupt priority feature is enabled by setting the ify any of the interrupt control registers IPEN bit (RCON<7>). When interrupt priority is while any interrupt is enabled. Doing so enabled, there are two bits which enable interrupts may cause erratic microcontroller behav- globally. Setting the GIEH bit (INTCON<7>) enables all ior. interrupts that have the priority bit set (high priority). Setting the GIEH and GIEL bits (INTCON<7:6>) enables interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate Global Interrupt Enable (GIE) bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits.  2011 Microchip Technology Inc. DS39932D-page 115

PIC18F46J11 FAMILY FIGURE 9-1: PIC18F46J11 FAMILY INTERRUPT LOGIC TMR0IF Wake-up if in TMR0IE Idle or Sleep modes TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE Interrupt to CPU INT1IP Vector to Location INT2IF PIR1<7:0> INT2IE 0008h PIE1<7:0> INT2IP IPR1<7:0> INT3IF INT3IE INT3IP GIE/GIEH PIR2<7:0> PIE2<7:0> IPR2<7:0> IPEN PIR3<7:0> IPEN PIE3<7:0> IPR3<7:0> PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> Interrupt to CPU PIR3<7:0> TTMMRR00IIEF IPEN V00e1ct8ohr to Location PIE3<7:0> TMR0IP IPR3<7:0> RBIF RBIE RBIP GIE/GIEH PEIE/GIEL INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP DS39932D-page 116  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 9.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the Global registers, which contain various enable, priority and Interrupt Enable bit. User software should flag bits. ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER (ACCESS FF2h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1 and GIEH = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB and waiting 1TCY will end the mismatch condition and allow the bit to be cleared.  2011 Microchip Technology Inc. DS39932D-page 117

PIC18F46J11 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 (ACCESS FF1h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port tri-state values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39932D-page 118  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 (ACCESS FF0h) R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2011 Microchip Technology Inc. DS39932D-page 119

PIC18F46J11 FAMILY 9.2 PIR Registers Note1: Interrupt flag bits are set when an inter- rupt condition occurs regardless of the The PIR registers contain the individual flag bits for the state of its corresponding enable bit or the peripheral interrupts. Due to the number of peripheral Global Interrupt Enable bit, GIE (INT- interrupt sources, there are three Peripheral Interrupt CON<7>). Request (Flag) registers (PIR1, PIR2, PIR3). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ACCESS F9Eh) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PMPIF: Parallel Master Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART1 receive buffer is empty bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART1 transmit buffer is full bit 3 SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: These bits are unimplemented on 28-pin devices. DS39932D-page 120  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ACCESS FA1h) R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CM2IF CM1IF — BCL1IF LVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6 CM2IF: Comparator 2 Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5 CM1IF: Comparator 1 Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 4 Unimplemented: Read as ‘0’ bit 3 BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 LVDIF: High/Low-Voltage Detect (HLVD) Interrupt Flag bit 1 = A high/low-voltage condition occurred (must be cleared in software) 0 = An HLVD event has not occurred bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode.  2011 Microchip Technology Inc. DS39932D-page 121

PIC18F46J11 FAMILY REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (ACCESS FA4h) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 6 BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 5 RC2IF: EUSART2 Receive Interrupt Flag bit 1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The EUSART2 receive buffer is empty bit 4 TX2IF: EUSART2 Transmit Interrupt Flag bit 1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The EUSART2 transmit buffer is full bit 3 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred bit 2 CTMUIF: Charge Time Measurement Unit Interrupt Flag bit 1 = A CTMU event has occurred (must be cleared in software) 0 = CTMU event has not occurred bit 1 TMR3GIF: Timer3 Gate Event Interrupt Flag bit 1 = A Timer3 gate event completed (must be cleared in software) 0 = No Timer3 gate event completed bit 0 RTCCIF: RTCC Interrupt Flag bit 1 = RTCC interrupt occurred (must be cleared in software) 0 = No RTCC interrupt occurred DS39932D-page 122  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ACCESS F9Dh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PMPIE: Parallel Master Port Read/Write Interrupt Enable bit(1) 1 = Enables the PMP read/write interrupt 0 = Disables the PMP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enables the EUSART1 receive interrupt 0 = Disables the EUSART1 receive interrupt bit 4 TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enables the EUSART1 transmit interrupt 0 = Disables the EUSART1 transmit interrupt bit 3 SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt bit 2 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enables the ECCP1 interrupt 0 = Disables the ECCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: These bits are unimplemented on 28-pin devices.  2011 Microchip Technology Inc. DS39932D-page 123

PIC18F46J11 FAMILY REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ACCESS FA0h) R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CM2IE CM1IE — BCL1IE LVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CM2IE: Comparator 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 CM1IE: Comparator 1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 Unimplemented: Read as ‘0’ bit 3 BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module) 1 = Enabled 0 = Disabled bit 2 LVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39932D-page 124  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 (ACCESS FA3h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module) 1 = Enabled 0 = Disabled bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CTMUIE: Charge Time Measurement Unit (CTMU) Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled  2011 Microchip Technology Inc. DS39932D-page 125

PIC18F46J11 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 (ACCESS F9Fh) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PMPIP: Parallel Master Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSP1IP: Master Synchronous Serial Port Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority bit 2 CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: These bits are unimplemented on 28-pin devices. DS39932D-page 126  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (ACCESS FA2h) R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CM2IP CM1IP — BCL1IP LVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CM2IP: Comparator 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 C12IP: Comparator 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 Unimplemented: Read as ‘0’ bit 3 BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority bit 2 LVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority  2011 Microchip Technology Inc. DS39932D-page 127

PIC18F46J11 FAMILY REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 (ACCESS FA5h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module) 1 = High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IE: TMR4 to PR4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CTMUIP: Charge Time Measurement Unit (CTMU) Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3GIP: Timer3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RTCCIP: RTCC Interrupt Priority bit 1 = High priority 0 = Low priority DS39932D-page 128  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep mode. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 9-13: RCON: RESET CONTROL REGISTER (ACCESS FD0h) R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0’ bit 5 CM: Configuration Mismatch Flag bit For details on bit operation, see Register5-1. bit 4 RI: RESET Instruction Flag bit For details on bit operation, see Register5-1. bit 3 TO: Watchdog Timer Time-out Flag bit For details on bit operation, see Register5-1. bit 2 PD: Power-Down Detection Flag bit For details on bit operation, see Register5-1. bit 1 POR: Power-on Reset Status bit For details on bit operation, see Register5-1. bit 0 BOR: Brown-out Reset Status bit For details on bit operation, see Register5-1.  2011 Microchip Technology Inc. DS39932D-page 129

PIC18F46J11 FAMILY 9.6 INTx Pin Interrupts pair (FFFFh0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, External interrupts on the INT0, INT1, INT2 and INT3 TMR0IE (INTCON<5>). Interrupt priority for Timer0 is pins are edge-triggered. If the corresponding INTEDGx determined by the value contained in the interrupt prior- bit in the INTCON2 register is set (= 1), the interrupt is ity bit, TMR0IP (INTCON2<2>). See Section12.0 triggered by a rising edge; if the bit is clear, the trigger “Timer0 Module” for further details on the Timer0 is on the falling edge. When a valid edge appears on module. the INTx pin, the corresponding flag bit and INTxIF are set. This interrupt can be disabled by clearing the 9.8 PORTB Interrupt-on-Change corresponding enable bit, INTxIE. Flag bit, INTxIF, must be cleared in software in the Interrupt Service An input change on PORTB<7:4> sets flag bit, RBIF Routine before re-enabling the interrupt. (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). All external interrupts (INT0, INT1, INT2 and INT3) can Interrupt priority for PORTB interrupt-on-change is wake-up the processor from the Sleep and Idle modes determined by the value contained in the interrupt if bit, INTxIE, was set prior to going into the power-man- priority bit, RBIP (INTCON2<0>). aged modes. After waking from Sleep or Idle mode, the processor will branch to the interrupt vector if the Global Interrupt Enable bit (GIE) is set. Deep Sleep 9.9 Context Saving During Interrupts mode can wake up from INT0, but the processor will During interrupts, the return PC address is saved on start execution from the Power-on Reset vector rather the stack. Additionally, the WREG, STATUS and BSR than branch to the interrupt vector. registers are saved on the Fast Return Stack. If a fast Interrupt priority for INT1, INT2 and INT3 is determined return from interrupt is not used (see Section6.3 by the value contained in the Interrupt Priority bits, “Data Memory Organization”), the user may need to INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and save the WREG, STATUS and BSR registers on entry INT3IP (INTCON2<1>). There is no priority bit to the Interrupt Service Routine. Depending on the associated with INT0. It is always a high-priority user’s application, other registers may also need to be interrupt source. saved. Example9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service 9.7 TMR0 Interrupt Routine. In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in access bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TEMP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS39932D-page 130  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 10.0 I/O PORTS 10.1 I/O Port Pin Capabilities Depending on the device selected and features When developing an application, the capabilities of the enabled, there are up to five ports available. Some pins port pins must be considered. Outputs on some pins of the I/O ports are multiplexed with an alternate have higher output drive strength than others. Similarly, function from the peripheral features on the device. In some pins can tolerate higher than VDD input levels. general, when a peripheral is enabled, that pin may not 10.1.1 PIN OUTPUT DRIVE be used as a general purpose I/O pin. Each port has three registers for its operation. These The output pin drive strengths vary for groups of pins registers are: intended to meet the needs for a variety of applications. PORTB and PORTC are designed to drive higher • TRIS register (Data Direction register) loads, such as LEDs. All other ports are designed for • PORT register (reads the levels on the pins of the small loads, typically indication only. Table10-1 sum- device) marizes the output capabilities. Refer to Section29.0 • LAT register (Data Latch) “Electrical Characteristics” for more details. The Data Latch (LAT register) is useful for read-modify- write operations on the value that the I/O pins are TABLE 10-1: OUTPUT DRIVE LEVELS driving. Port Drive Description Figure10-1 displays a simplified model of a generic I/O PORTA port, without the interfaces to other peripherals. (except RA6) Minimum Intended for indication. FIGURE 10-1: GENERIC I/O PORT PORTD OPERATION PORTE PORTB Suitable for direct LED PORTC High drive levels. RD LAT PORTA<6> Data Bus 10.1.2 INPUT PINS AND VOLTAGE D Q WR LAT I/O pin(1) CONSIDERATIONS or PORT CK The voltage tolerance of pins used as device inputs is Data Latch dependent on the pin’s input function. Pins that are used as digital only inputs are able to handle DC voltages up D Q to 5.5V; a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind WR TRIS CK can only tolerate voltages up to VDD. Voltage excursions TRIS Latch Input beyond VDD on these pins should be avoided. Table10- Buffer 2 summarizes the input capabilities. Refer to RD TRIS Section29.0 “Electrical Characteristics” for more details. Q D TABLE 10-2: INPUT VOLTAGE LEVELS ENEN Tolerated Port or Pin Description Input RD PORT PORTA<7:0> Note 1: I/O pins have diode protection to VDD and PORTB<3:0> Only VDD input levels VDD VSS. PORTC<2:0> tolerated. PORTE<2:0> PORTB<7:4> Tolerates input levels PORTC<7:3> 5.5V above VDD, useful for most standard logic. PORTD<7:0>  2011 Microchip Technology Inc. DS39932D-page 131

PIC18F46J11 FAMILY 10.1.3 INTERFACING TO A 5V SYSTEM The open-drain option is implemented on port pins specifically associated with the data and clock outputs Though the VDDMAX of the PIC18F46J11 family is 3.6V, of the EUSARTs, the MSSP modules (in SPI mode) and these devices are still capable of interfacing with 5V the ECCP modules. It is selectively enabled by setting systems, even if the VIH of the target system is above the open-drain control bit for the corresponding module 3.6V. This is accomplished by adding a pull-up resistor in the ODCON registers (Register10-1, Register10-2 to the port pin (Figure10-2), clearing the LAT bit for that and Register10-3). Their configuration is discussed in pin and manipulating the corresponding TRIS bit more detail with the individual port where these (Figure10-1) to either allow the line to be pulled high or peripherals are multiplexed. to drive the pin low. Only port pins that are tolerant of voltages up to 5.5V can be used for this type of When the open-drain option is required, the output pin interface (refer to Section10.1.2 “Input Pins and must also be tied through an external pull-up resistor Voltage Considerations”). provided by the user to a higher voltage level, up to 5.5V (Figure10-3). When a digital logic high signal is FIGURE 10-2: +5V SYSTEM HARDWARE output, it is pulled up to the higher voltage level. INTERFACE FIGURE 10-3: USING THE OPEN-DRAIN OUTPUT (USART SHOWN PIC18F46J11 +5V +5V Device AS EXAMPLE) 3.3V +5V PIC18F46J11 RD7 VDD TXX 5V (at logic ‘1’) EXAMPLE 10-1: COMMUNICATING WITH THE +5V SYSTEM BCF LATD, 7 ; set up LAT register so ; changing TRIS bit will 10.1.5 TTL INPUT BUFFER OPTION ; drive line low BCF TRISD, 7 ; send a 0 to the 5V system Many of the digital I/O ports use Schmitt Trigger (ST) BSF TRISD, 7 ; send a 1 to the 5V system input buffers. While this form of buffering works well with many types of input, some applications may require TTL level signals to interface with external logic 10.1.4 OPEN-DRAIN OUTPUTS devices. This is particularly true for the Parallel Master Port (PMP), which is likely to be interfaced to TTL level The output pins for several peripherals are also logic or memory devices. equipped with a configurable open-drain output option. This allows the peripherals to communicate with The inputs for the PMP can be optionally configured for external digital logic operating at a higher voltage level, TTL buffers with the PMPTTL bit in the PADCFG1 reg- without the use of level translators. ister (Register10-4). Setting this bit configures all data and control input pins for the PMP to use TTL buffers. By default, these PMP inputs use the port’s ST buffers. DS39932D-page 132  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 10-1: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1 (BANKED F42h) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — ECCP2OD ECCP1OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 ECCP2OD: ECCP2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 0 ECCP1OD: ECCP1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled REGISTER 10-2: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 (BANKED F41h) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — U2OD U1OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 U2OD: USART2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 0 U1OD: USART1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled  2011 Microchip Technology Inc. DS39932D-page 133

PIC18F46J11 FAMILY REGISTER 10-3: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SPI2OD SPI1OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 SPI2OD: SPI2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 0 SPI1OD: SPI1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled REGISTER 10-4: PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1 (BANKED F3Ch) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — RTSECSEL1(1) RTSECSEL0(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1) 11 = Reserved; do not use 10 = RTCC source clock is selected for the RTCC pin (can be INTRC or T1OSC, depending on the RTCOSC (CONFIG3L<1>) setting) 01 = RTCC seconds clock is selected for the RTCC pin 00 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers Note 1: To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit needs to be set. DS39932D-page 134  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 10.2 PORTA, TRISA and LATA Registers EXAMPLE 10-2: INITIALIZING PORTA PORTA is a 7-bit wide, bidirectional port. It may CLRF LATA ; Initialize LATA function as a 5-bit port, depending on the oscillator ; to clear output mode selected. Setting a TRISA bit (= 1) will make the ; data latches corresponding PORTA pin an input (i.e., put the MOVLB 0x0F ; ANCONx register not in ; Access Bank corresponding output driver in a high-impedance MOVLW 0x0F ; Configure A/D mode). Clearing a TRISA bit (= 0) will make the MOVWF ANCON0 ; for digital inputs corresponding PORTA pin an output (i.e., put the MOVLW 0xCF ; Value used to contents of the output latch on the selected pin). ; initialize data Reading the PORTA register reads the status of the ; direction MOVWF TRISA ; Set RA<3:0> as inputs pins, whereas writing to it, will write to the port latch. ; RA<5:4> as outputs The Data Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the com- parator voltage reference output. The operation of pins, RA<3:0> and RA5, as A/D converter inputs is selected by clearing or setting the control bits in the ANCON0 register (A/D Port Configuration Register 0). Pins, RA0 and RA3, may also be used as comparator inputs by setting the appropriate bits in the CMCON reg- ister. To use RA<3:0> as digital inputs, it is also necessary to turn off the comparators. Note: On a Power-on Reset (POR), RA5 and RA<3:0> are configured as analog inputs and read as ‘0’. All PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.  2011 Microchip Technology Inc. DS39932D-page 135

PIC18F46J11 FAMILY TABLE 10-3: PORTA I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RA0/AN0/C1INA/ RA0 1 I TTL PORTA<0> data input; disabled when analog input enabled. ULPWU/PMA6/ 0 O DIG LATA<0> data output; not affected by analog input. RP0 AN0 1 I ANA A/D input channel 0 and Comparator C1- input. Default input configuration on POR; does not affect digital output. C1INA 1 I ANA Comparator 1 input A. ULPWU 1 I ANA Ultra low-power wake-up input. PMA6(1) 0 O DIG Parallel Master Port address. RP0 1 I ST Remappable peripheral pin 0 input. 0 O DIG Remappable peripheral pin 0 output. RA1/AN1/C2INA/ RA1 1 I TTL PORTA<1> data input; disabled when analog input enabled. PMA7/RP1 0 O DIG LATA<1> data output; not affected by analog input. AN1 1 I ANA A/D input channel 1 and Comparator C2- input. Default input configuration on POR; does not affect digital output. C2INA 1 I ANA Comparator 1 input A. PMA7(1) 0 O DIG Parallel Master Port address. RP1 1 I ST Remappable peripheral pin 1 input. 0 O DIG Remappable peripheral pin 1 output. RA2/AN2/ RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled VREF-/CVREF/ when CVREF output enabled. C2INB 1 I TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. AN2 1 I ANA A/D input channel 2 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. VREF- 1 I ANA A/D and comparator voltage reference low input. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. C2INB I I ANA Comparator 2 input B. 0 O ANA CTMU pulse generator charger for the C2INB comparator input. RA3/AN3/VREF+/ RA3 0 O DIG LATA<3> data output; not affected by analog input. C1INB 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D input channel 3 and Comparator C1+ input. Default input configuration on POR. VREF+ 1 I ANA A/D and comparator voltage reference high input. C1INB 1 I ANA Comparator 1 input B. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This bit is only available on 44-pin devices. DS39932D-page 136  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 10-3: PORTA I/O SUMMARY (CONTINUED) TRIS I/O Pin Function I/O Description Setting Type RA5/AN4/SS1/ RA5 0 O DIG LATA<5> data output; not affected by analog input. HLVDIN/RP2 1 I TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 I ANA A/D input channel 4. Default configuration on POR. SS1 1 I TTL Slave select input for MSSP1. HLVDIN 1 I ANA High/Low-Voltage Detect external trip point reference input. RP2 1 I ST Remappable Peripheral pin 2 input. 0 O DIG Remappable Peripheral pin 2 output. OSC2/CLKO/ OSC2 x O ANA Main oscillator feedback output connection (HS mode). RA6 CLKO x O DIG System cycle clock output (FOSC/4) in RC and EC Oscillator modes. RA6 1 I TTL PORTA<6> data input. 0 O DIG LATA<6> data output. OSC1/CLKI/RA7 OSC1 1 I ANA Main oscillator input connection. CLKI 1 I ANA Main clock input connection. RA7 1 I TTL PORTA<6> data input. 0 O DIG LATA<6> data output. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This bit is only available on 44-pin devices. TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTA RA7 RA6 RA5 — RA3 RA2 RA1 RA0 87 LATA LAT7 LAT6 LAT5 — LAT3 LAT2 LAT1 LAT0 87 TRISA TRIS7 TRIS6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 87 ANCON0 PCFG7(1) PCFG6(1) PCFG5(1) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 88 CMxCON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 87 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 88 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: These bits are only available in 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 137

PIC18F46J11 FAMILY 10.3 PORTB, TRISB and LATB Four of the PORTB pins (RB<7:4>) have an interrupt- Registers on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB<7:4> pin PORTB is an 8-bit wide, bidirectional port. The corre- configured as an output is excluded from the interrupt- sponding Data Direction register is TRISB. Setting a on-change comparison). The input pins (of RB<7:4>) TRISB bit (= 1) will make the corresponding PORTB are compared with the old value latched on the last pin an input (i.e., put the corresponding output driver in read of PORTB. The “mismatch” outputs of RB<7:4> a high-impedance mode). Clearing a TRISB bit (= 0) are ORed together to generate the RB Port Change will make the corresponding PORTB pin an output (i.e., Interrupt with Flag bit, RBIF (INTCON<0>). put the contents of the output latch on the selected pin). This interrupt can wake the device from Sleep mode or The Data Latch register (LATB) is also memory any of the Idle modes. The user, in the Interrupt Service mapped. Read-modify-write operations on the LATB Routine (ISR), can clear the interrupt using the following register read and write the latched output value for steps: PORTB. 1. Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). EXAMPLE 10-3: INITIALIZING PORTB 2. Wait one instruction cycle (such as executing a CLRF LATB ; Initialize LATB NOP instruction). ; to clear output 3. Clear flag bit, RBIF. ; data latches A mismatch condition continues to set flag bit, RBIF. MOVLB 0x0F ; ANCON1 not in Access ; Bank Reading PORTB will end the mismatch condition and MOVLW 0x17 ; Configure as digital I/O allow flag bit, RBIF, to be cleared after one instruction MOVWF ANCON1 ; pins in this example cycle of delay. MOVLW 0xCF ; Value used to The interrupt-on-change feature is recommended for ; initialize data wake-up on key depression operation and operations ; direction MOVWF TRISB ; Set RB<3:0> as inputs where PORTB is only used for the interrupt-on-change ; RB<5:4> as outputs feature. Polling of PORTB is not recommended while ; RB<7:6> as inputs using the interrupt-on-change feature. The RB5 pin is multiplexed with the Timer0 module Each of the PORTB pins has a weak internal pull-up. A clock input and one of the comparator outputs to single control bit can turn on all the pull-ups. This is become the RB5/KBI1/SDI1/SDA1/RP8 pin. performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a POR. Note: On a POR, the RB<3:0> bits are configured as analog inputs by default and read as ‘0’; RB<7:4> bits are configured as digital inputs. DS39932D-page 138  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 10-5: PORTB I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RB0/AN12/ RB0 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is INT0/RP3 cleared. Disabled when analog input enabled.(1) 0 O DIG LATB<0> data output; not affected by analog input. AN12 1 I ANA A/D input channel 12.(1) INT0 1 I ST External interrupt 0 input. RP3 1 I ST Remappable peripheral pin 3 input. 0 O DIG Remappable peripheral pin 3 output. RB1/AN10/ RB1 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is PMBE/RTCC/ cleared. Disabled when analog input enabled.(1) RP4 0 O DIG LATB<1> data output; not affected by analog input. AN10 1 I ANA A/D input channel 10.(1) PMBE(3) 0 O DIG Parallel Master Port byte enable output. RTCC 0 O DIG Real Time Clock Calendar output. RP4 1 I ST Remappable peripheral pin 4 input. 0 O DIG Remappable peripheral pin 4 output. RB2/AN8/ RB2 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is CTED1/PMA3/ cleared. Disabled when analog input enabled.(1) REFO/RP5 0 O DIG LATB<2> data output; not affected by analog input. AN8 1 I ANA A/D input channel 8.(1) CTED1 1 I ST CTMU Edge 1 input. PMA3(3) 0 O DIG Parallel Master Port address. REFO 0 O DIG Reference output clock. RP5 1 I ST Remappable peripheral pin 5 input. 0 O DIG Remappable peripheral pin 5 output. RB3/AN9/ RB3 0 O DIG LATB<3> data output; not affected by analog input. CTED2/PMA2/ 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is RP6 cleared. Disabled when analog input enabled.(1) AN9 1 I ANA A/D input channel 9.(1) CTED2 1 I ST CTMU edge 2 input. PMA2(3) 0 O DIG Parallel Master Port address. RP6 1 I ST Remappable peripheral pin 6 input. 0 O DIG Remappable peripheral pin 6 output. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting the appropriate bits in ANCON1 first. 2: All other pin functions are disabled when ICSP™ or ICD are enabled. 3: This bit is not available on 28-pin devices.  2011 Microchip Technology Inc. DS39932D-page 139

PIC18F46J11 FAMILY TABLE 10-5: PORTB I/O SUMMARY (CONTINUED) TRIS I/O Pin Function I/O Description Setting Type RB4/PMA1/ RB4 0 O DIG LATB<4> data output; not affected by analog input. KBI0/RP7 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) PMA1(3) 0 O DIG Parallel Master Port address. 1 I ST/TTL Parallel Slave Port address input. KBI0 1 I TTL Interrupt-on-change pin. RP7 1 I ST Remappable peripheral pin 7 input. 0 O DIG Remappable peripheral pin 7 output. RB5/PMA0/ RB5 0 O DIG LATB<5> data output. KBI1/RP8 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. PMA0(3) 0 O DIG Parallel Master Port address. 1 I ST/TTL Parallel Slave Port address input. KBI1 1 I TTL Interrupt-on-change pin. RP8 1 I ST Remappable peripheral pin 8 input. 0 O DIG Remappable peripheral pin 8 output. RB6/KBI2/ RB6 0 O DIG LATB<6> data output. PGC/RP9 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-change pin. PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(2) RP9 1 I ST Remappable peripheral pin 9 input. 0 O DIG Remappable peripheral pin 9 output. RB7/KBI3/ RB7 0 O DIG LATB<7> data output. PGD/RP10 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-change pin. PGD x O DIG Serial execution data output for ICSP and ICD operation.(2) x I ST Serial execution data input for ICSP and ICD operation.(2) RP10 1 I ST Remappable peripheral pin 10 input. 0 O ST Remappable peripheral pin 10 output. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting the appropriate bits in ANCON1 first. 2: All other pin functions are disabled when ICSP™ or ICD are enabled. 3: This bit is not available on 28-pin devices. DS39932D-page 140  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 87 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 87 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 87 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 87 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 87 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 87 ANCON0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 87 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.  2011 Microchip Technology Inc. DS39932D-page 141

PIC18F46J11 FAMILY 10.4 PORTC, TRISC and LATC Note: On a Power-on Reset, PORTC pins Registers (except RC2) are configured as digital inputs. RC2 will default as an analog input PORTC is an 8-bit wide, bidirectional port. The corre- (controlled by the ANCON1 register). sponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC The contents of the TRISC register are affected by pin an input (i.e., put the corresponding output driver in peripheral overrides. Reading TRISC always returns a high-impedance mode). Clearing a TRISC bit (= 0) the current contents, even though a peripheral device will make the corresponding PORTC pin an output (i.e., may be overriding one or more of the pins. put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory EXAMPLE 10-4: INITIALIZING PORTC mapped. Read-modify-write operations on the LATC CLRF LATC ; Initialize PORTC by register read and write the latched output value for ; clearing output PORTC. ; data latches PORTC is multiplexed with several peripheral functions MOVLW 0x3F ; Value used to (see Table10-7). The pins have Schmitt Trigger input ; initialize data buffers. ; direction MOVWF TRISC ; Set RC<5:0> as inputs When enabling peripheral functions, care should be ; RC<7:6> as outputs taken in defining TRIS bits for each PORTC pin. Some MOVLB 0x0F ; ANCON register is not in peripherals override the TRIS bit to make a pin an output, Access Bank while other peripherals override the TRIS bit to make a BSF ANCON1,PCFG11 pin an input. The user should refer to the corresponding ;Configure RC2/AN11 as peripheral section for additional information. digital input DS39932D-page 142  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 10-7: PORTC I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RC0/T1OSO/ RC0 1 I ST PORTC<0> data input. T1CKI/RP11 0 O DIG LATC<0> data output. T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T1CKI 1 I ST Timer1 counter input. RP11 1 I ST Remappable peripheral pin 11 input. 0 O DIG Remappable peripheral pin 11 output. RC1/T1OSI/ RC1 1 I ST PORTC<1> data input. RP12 0 O DIG LATC<1> data output. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. RP12 1 I ST Remappable peripheral pin 12 input. 0 O DIG Remappable peripheral pin 12 output. RC2/AN11/ RC2 1 I ST PORTC<2> data input. CTPLS/RP13 0 O DIG LATC<2> data output. AN11 1 I ANA A/D input channel 11. CTPLS 0 O DIG CTMU pulse generator output. RP13 1 I ST Remappable peripheral pin 13 input. 0 O DIG Remappable peripheral pin 13 output. RC3/SCK1/ RC3 1 I ST PORTC<3> data input. SCL1/RP14 0 O DIG LATC<3> data output. SCK1 1 I ST SPI clock input (MSSP1 module). 0 O DIG SPI clock output (MSSP1 module). SCL1 1 I I2C/ I2C™ clock input (MSSP1 module). SMBus 0 O DIG I2C clock output (MSSP1 module). RP14 1 I ST Remappable peripheral pin 14 input. 0 O DIG Remappable peripheral pin 14 output. RC4/SDI1/ RC4 1 I ST PORTC<4> data input. SDA1/RP15 0 O DIG LATC<4> data output. SDI1 1 I ST SPI data input (MSSP1 module). SDA1 1 I I2C/ I2C data input (MSSP1 module). SMBus 0 O DIG I2C/SMBus. RP15 1 I ST Remappable peripheral pin 15 input. 0 O DIG Remappable peripheral pin 15 output. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This bit is only available on 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 143

PIC18F46J11 FAMILY TABLE 10-7: PORTC I/O SUMMARY (CONTINUED) TRIS I/O Pin Function I/O Description Setting Type RC5/SDO1/ RC5 1 I ST PORTC<5> data input. RP16 0 O DIG LATC<5> data output. SDO1 0 O DIG SPI data output (MSSP1 module). RP16 1 I ST Remappable peripheral pin 16 input. 0 O DIG Remappable peripheral pin 16 output. RC6/PMA5/ RC6 1 I ST PORTC<6> data input. TX1/CK1/RP17 0 O DIG LATC<6> data output. PMA5(1) 0 O DIG Parallel Master Port address. TX1 0 O DIG Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as output. CK1 1 I ST Synchronous serial clock input (EUSART module). 0 O DIG Synchronous serial clock output (EUSART module); takes priority over port data. RP17 1 I ST Remappable peripheral pin 17 input. 0 O DIG Remappable peripheral pin 17 output. RC7/PMA4/ RC7 1 I ST PORTC<7> data input. RX1/DT1/RP18 0 O DIG LATC<7> data output. PMA4(1) 0 O DIG Parallel Master Port address. RX1 1 I ST Asynchronous serial receive data input (EUSART module). DT1 1 1 ST Synchronous serial data input (EUSART module). User must configure as an input. 0 O DIG Synchronous serial data output (EUSART module); takes priority over port data. RP18 1 I ST Remappable peripheral pin 18 input. 0 O DIG Remappable peripheral pin 18 output. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This bit is only available on 44-pin devices. TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page: PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 87 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 87 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 87 DS39932D-page 144  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 10.5 PORTD, TRISD and LATD Note: On a POR, these pins are configured as Registers digital inputs. Note: PORTD is available only in 44-pin EXAMPLE 10-5: INITIALIZING PORTD devices. CLRF LATD ; Initialize LATD PORTD is an 8-bit wide, bidirectional port. The corre- ; to clear output sponding Data Direction register is TRISD. Setting a ; data latches TRISD bit (= 1) will make the corresponding PORTD MOVLW 0xCF ; Value used to pin an input (i.e., put the corresponding output driver in ; initialize data a high-impedance mode). Clearing a TRISD bit (= 0) ; direction will make the corresponding PORTD pin an output (i.e., MOVWF TRISD ; Set RD<3:0> as inputs put the contents of the output latch on the selected pin). ; RD<5:4> as outputs ; RD<7:6> as inputs The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for Each of the PORTD pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is per- PORTD. formed by setting bit, RDPU (PORTE<7>). The weak All pins on PORTD are implemented with Schmitt Trigger pull-up is automatically turned off when the port pin is input buffers. Each pin is individually configurable as an configured as an output. The pull-ups are disabled on a input or output. POR. Note that the pull-ups can be used for any set of features, similar to the pull-ups found on PORTB.  2011 Microchip Technology Inc. DS39932D-page 145

PIC18F46J11 FAMILY TABLE 10-9: PORTD I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RD0/PMD0/ RD0 1 I ST PORTD<0> data input. SCL2 0 O DIG LATD<0> data output. PMD0 1 I ST/TTL Parallel Master Port data in. 0 O DIG Parallel Master Port data out. SCL2 1 I I2C/ I2C™ clock input (MSSP2 module); input type depends on SMB module setting. 0 O DIG I2C™ clock output (MSSP2 module); takes priority over port data. RD1/PMD1/ RD1 1 I ST PORTD<1> data input. SDA2 0 O DIG LATD<1> data output. PMD1 1 I ST/TTL Parallel Master Port data in. 0 O DIG Parallel Master Port data out. SDA2 1 I I2C/ I2C data input (MSSP2 module); input type depends on SMB module setting. 0 O DIG I2C data output (MSSP2 module); takes priority over port data. RD2/PMD2/ RD2 1 I ST PORTD<2> data input. RP19 0 O DIG LATD<2> data output. PMD2 1 I ST/TTL Parallel Master Port data in. 0 O DIG Parallel Master Port data out. RP19 1 I ST Remappable peripheral pin 19 input. 0 O DIG Remappable peripheral pin 19 output. RD3/PMD3/ RD3 1 I DIG PORTD<3> data input. RP20 0 O DIG LATD<3> data output. PMD3 1 I ST/TTL Parallel Master Port data in. 0 O DIG Parallel Master Port data out. RP20 1 I ST Remappable peripheral pin 20 input. 0 O DIG Remappable peripheral pin 20 output. RD4/PMD4/ RD4 1 I ST PORTD<4> data input. RP21 0 O DIG LATD<4> data output. PMD4 1 I ST/TTL Parallel Master Port data in. 0 O DIG Parallel Master Port data out. RP21 1 I ST Remappable peripheral pin 21 input. 0 O DIG Remappable peripheral pin 21 output. RD5/PMD5/ RD5 1 I ST PORTD<5> data input. RP22 0 O DIG LATD<5> data output. PMD5 1 I ST/TTL Parallel Master Port data in. 0 O DIG Parallel Master Port data out. RP22 1 I ST Remappable peripheral pin 22 input. 0 O DIG Remappable peripheral pin 22 output. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). DS39932D-page 146  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 10-9: PORTD I/O SUMMARY (CONTINUED) TRIS I/O Pin Function I/O Description Setting Type RD6/PMD6/ RD6 1 I ST PORTD<6> data input. RP23 0 O DIG LATD<6> data output. PMD6 1 I ST/TTL Parallel Master Port data in. 0 O DIG Parallel Master Port data out. RP23 1 I ST Remappable peripheral pin 23 input. 0 O DIG Remappable peripheral pin 23 output. RD7/PMD7/ RD7 1 I ST PORTD<7> data input. RP24 0 O DIG LATD<7> data output. PMD7 1 I ST/TTL Parallel Master Port data in. 0 O DIG Parallel Master Port data out. RP24 1 I ST Remappable peripheral pin 24 input. 0 O DIG Remappable peripheral pin 24 output. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 93 LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 92 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 92 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers are not available in 28-pin devices.  2011 Microchip Technology Inc. DS39932D-page 147

PIC18F46J11 FAMILY 10.6 PORTE, TRISE and LATE The Data Latch register (LATE) is also memory Registers mapped. Read-modify-write operations on the LATE register read and write the latched output value for Note: PORTE is available only in 44-pin PORTE. devices. EXAMPLE 10-6: INITIALIZING PORTE Depending on the particular PIC18F46J11 family device selected, PORTE is implemented in two CLRF LATE ; Initialize LATE different ways. ; to clear output ; data latches For 44-pin devices, PORTE is a 3-bit wide port. Three MOVLW 0xE0 ; Configure REx pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/ MOVWF ANCON0 ; for digital inputs AN7/PMCS) are individually configurable as inputs or MOVLW 0x03 ; Value used to outputs. These pins have Schmitt Trigger input buffers. ; initialize data When selected as analog inputs, these pins will read as ; direction ‘0’s. MOVWF TRISE ; Set RE<0> as inputs ; RE<1> as outputs The corresponding Data Direction register is TRISE. ; RE<2> as inputs Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit Each of the PORTE pins has a weak internal pull-up. A (= 0) will make the corresponding PORTE pin an output single control bit can turn on all the pull-ups. This is per- (i.e., put the contents of the output latch on the selected formed by setting bit, REPU (PORTE<6>). The weak pin). pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a TRISE controls the direction of the RE pins, even when POR. they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when Note that the pull-ups can be used for any set of using them as analog inputs. features, similar to the pull-ups found on PORTB. Note: On a POR, RE<2:0> are configured as analog inputs. DS39932D-page 148  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 10-11: PORTE I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RE0/AN5/ RE0 1 I ST PORTE<0> data input; disabled when analog input enabled. PMRD 0 O DIG LATE<0> data output; not affected by analog input. AN5 1 I ANA A/D input channel 5; default input configuration on POR. PMRD 1 I ST/TTL Parallel Master Port io_rd_in. 0 O DIG Parallel Master Port read strobe. RE1/AN6/ RE1 1 I ST PORTE<1> data input; disabled when analog input enabled. PMWR 0 O DIG LATE<1> data output; not affected by analog input. AN6 1 I ANA A/D input channel 6; default input configuration on POR. PMWR 1 I ST/TTL Parallel Master Port io_wr_in. 0 O DIG Parallel Master Port write strobe. RE2/AN7/ RE2 1 I ST PORTE<2> data input; disabled when analog input enabled. PMCS 0 O DIG LATE<2> data output; not affected by analog input. AN7 1 I ANA A/D input channel 7; default input configuration on POR. PMCS 0 O DIG Parallel Master Port byte enable. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level I = Input; O = Output; P = Power TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTE(1) RDPU(3) REPU(4) — — — RE2 RE1 RE0 93 LATE(1) — — — — — LATE2 LATE1 LATE0 92 TRISE(1) — — — — — TRISE2 TRISE1 TRISE0 92 ANCON0 PCFG7(2) PCFG6(2) PCFG5(2) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 94 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: These registers are not available in 28-pin devices. 2: These bits are only available in 44-pin devices. 3: PORTD Pull-up Enable bit 0 = All PORTD pull-ups are disabled 1 = PORTD pull-ups are enabled for any input pad 4: PORTE Pull-up Enable bit 0 = All PORTE pull-ups are disabled 1 = PORTE pull-ups are enabled for any input pad  2011 Microchip Technology Inc. DS39932D-page 149

PIC18F46J11 FAMILY 10.7 Peripheral Pin Select (PPS) 10.7.2 AVAILABLE PERIPHERALS A major challenge in general purpose devices is provid- The peripherals managed by the PPS are all digital ing the largest possible set of peripheral features while only peripherals. These include general serial commu- minimizing the conflict of features on I/O pins. The nications (UART and SPI), general purpose timer clock challenge is even greater on low pin count devices inputs, timer-related peripherals (input capture and similar to the PIC18F46J11 family. In an application output compare) and external interrupt inputs. Also that needs to use more than one peripheral multiplexed included are the outputs of the comparator module, on single pin, inconvenient workarounds in application since these are discrete digital signals. code or a complete redesign may be the only option. The PPS module is not applied to I2C, change notifica- tion inputs, RTCC alarm outputs or peripherals with The Peripheral Pin Select (PPS) feature provides an analog inputs. Additionally, the MSSP1 and EUSART1 alternative to these choices by enabling the user’s modules are not routed through the PPS module. peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options A key difference between pin select and non-pin select available on a particular device, users can better tailor peripherals is that pin select peripherals are not asso- the microcontroller to their entire application, rather than ciated with a default I/O pin. The peripheral must trimming the application to fit the device. always be assigned to a specific I/O pin before it can be used. In contrast, non PPS peripherals are always The PPS feature operates over a fixed subset of digital available on a default pin, assuming that the peripheral I/O pins. Users may independently map the input and/ is active and not conflicting with another peripheral. or output of any one of the many digital peripherals to any one of these I/O pins. PPS is performed in software 10.7.2.1 Peripheral Pin Select Function and generally does not require the device to be Priority reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the When a pin selectable peripheral is active on a given I/O peripheral mapping once it has been established. pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. 10.7.1 AVAILABLE PINS Priority is given regardless of the type of peripheral that The PPS feature is used with a range of up to 22 pins; is mapped. Pin select peripherals never take priority the number of available pins is dependent on the over any analog functions associated with the pin. particular device and its pin count. Pins that support the 10.7.3 CONTROLLING PERIPHERAL PIN PPS feature include the designation “RPn” in their full SELECT pin designation, where “RP” designates a remappable peripheral and “n” is the remappable pin number. See PPS features are controlled through two sets of Special Table1-2 for pinout options in each package offering. Function Registers (SFRs): one to map peripheral inputs and the other to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or an output is being mapped. DS39932D-page 150  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 10.7.3.1 Input Mapping ated with one of the pin selectable peripherals. Program- ming a given peripheral’s bit field with an appropriate 5- The inputs of the PPS options are mapped on the basis bit value maps the RPn pin with that value to that of the peripheral; that is, a control register associated peripheral. For any given device, the valid range of with a peripheral dictates the pin it will be mapped to. values for any of the bit fields corresponds to the The RPINRx registers are used to configure peripheral maximum number of peripheral pin selections supported input mapping (see Register10-6 through Register10- by the device. 20). Each register contains a 5-bit field, which is associ- TABLE 10-13: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Configuration Input Name Function Name Register Bits External Interrupt 1 INT1 RPINR1 INTR1R<4:0> External Interrupt 2 INT2 RPINR2 INTR2R<4:0> External Interrupt 3 INT3 RPINR3 INTR3R<4:0> Timer0 External Clock Input T0CKI RPINR4 T0CKR<4:0> Timer3 External Clock Input T3CKI RPINR6 T3CKR<4:0> Input Capture 1 CCP1 RPINR7 IC1R<4:0> Input Capture 2 CCP2 RPINR8 IC2R<4:0> Timer1 Gate Input T1G RPINR12 T1GR<4:0> Timer3 Gate Input T3G RPINR13 T3GR<4:0> EUSART2 Asynchronous Receive/Synchronous RX2/DT2 RPINR16 RX2DT2R<4:0> Receive EUSART2 Asynchronous Clock Input CK2 RPINR17 CK2R<4:0> SPI2 Data Input SDI2 RPINR21 SDI2R<4:0> SPI2 Clock Input SCK2IN RPINR22 SCK2R<4:0> SPI2 Slave Select Input SS2IN RPINR23 SS2R<4:0> PWM Fault Input FLT0 RPINR24 OCFAR<4:0> Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.  2011 Microchip Technology Inc. DS39932D-page 151

PIC18F46J11 FAMILY 10.7.3.2 Output Mapping field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table10- In contrast to inputs, the outputs of the PPS options are 14). mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the Because of the mapping technique, the list of peripheral output to be mapped. The RPORx registers peripherals for output mapping also includes a null are used to control output mapping. The value of the bit value of ‘00000’. This permits any given pin to remain disconnected from the output of any of the pin selectable peripherals. TABLE 10-14: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Output Function Function Output Name Number(1) NULL 0 NULL(2) C1OUT 1 Comparator 1 Output C2OUT 2 Comparator 2 Output TX2/CK2 5 EUSART2 Asynchronous Transmit/Asynchronous Clock Output DT2 6 EUSART2 Synchronous Transmit SDO2 9 SPI2 Data Output SCK2 10 SPI2 Clock Output SSDMA 12 SPI DMA Slave Select ULPOUT 13 Ultra Low-Power Wake-up Event CCP1/P1A 14 ECCP1 Compare or PWM Output Channel A P1B 15 ECCP1 Enhanced PWM Output, Channel B P1C 16 ECCP1 Enhanced PWM Output, Channel C P1D 17 ECCP1 Enhanced PWM Output, Channel D CCP2/P2A 18 ECCP2 Compare or PWM Output P2B 19 ECCP2 Enhanced PWM Output, Channel B P2C 20 ECCP2 Enhanced PWM Output, Channel C P2D 21 ECCP2 Enhanced PWM Output, Channel D Note 1: Value assigned to the RPn<4:0> pins corresponds to the peripheral output function number. 2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. DS39932D-page 152  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 10.7.3.3 Mapping Limitations 10.7.4.3 Configuration Bit Pin Select Lock The control schema of the PPS is extremely flexible. As an additional level of safety, the device can be con- Other than systematic blocks that prevent signal con- figured to prevent more than one write session to the tention caused by two physical pins being configured RPINRx and RPORx registers. The IOL1WAY as the same functional input or two functional outputs (CONFIG3H<0>) Configuration bit blocks the IOLOCK configured as the same pin, there are no hardware bit from being cleared after it has been set once. If enforced lock outs. The flexibility extends to the point of IOLOCK remains set, the register unlock procedure will allowing a single input to drive multiple peripherals or a not execute and the PPS control registers cannot be single functional output to drive multiple output pins. written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. 10.7.4 CONTROLLING CONFIGURATION In the default (unprogrammed) state, IOL1WAY is set, CHANGES restricting users to one write session. Programming Because peripheral remapping can be changed during IOL1WAY allows users unlimited access (with the run time, some restrictions on peripheral remapping proper use of the unlock sequence) to the PPS are needed to prevent accidental configuration registers. changes. PIC18F devices include three features to prevent alterations to the peripheral map: 10.7.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION • Control register lock sequence • Continuous state monitoring The ability to control peripheral pin selection introduces several considerations into application design that • Configuration bit remapping lock could be overlooked. This is particularly true for several 10.7.4.1 Control Register Lock common peripherals that are available only as remappable peripherals. Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will The main consideration is that the PPS is not available appear to execute normally, but the contents of the on default pins in the device’s default (Reset) state. registers will remain unchanged. To change these reg- Since all RPINRx registers reset to ‘11111’ and all isters, they must be unlocked in hardware. The register RPORx registers reset to ‘00000’, all PPS inputs are lock is controlled by the IOLOCK bit (PPSCON<0>). tied to RP31 and all PPS outputs are disconnected. Setting IOLOCK prevents writes to the control Note: In tying PPS inputs to RP31, RP31 does registers; clearing IOLOCK allows writes. not have to exist on a device for the To set or clear IOLOCK, a specific command sequence registers to be reset to it. must be executed: This situation requires the user to initialize the device 1. Write 55h to EECON2<7:0>. with the proper peripheral configuration before any 2. Write AAh to EECON2<7:0>. other application code is executed. Since the IOLOCK 3. Clear (or set) IOLOCK as a single operation. bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has IOLOCK remains in one state until changed. This come out of Reset. allows all of the PPS registers to be configured with a single unlock sequence followed by an update to all For application safety, however, it is best to set control registers, then locked with a second lock IOLOCK and lock the configuration after writing to the sequence. control registers. Because the unlock sequence is timing critical, it must 10.7.4.2 Continuous State Monitoring be executed as an assembly language routine. If the In addition to being protected from direct writes, the bulk of the application is written in C or another high- contents of the RPINRx and RPORx registers are level language, the unlock sequence should be constantly monitored in hardware by shadow registers. performed by writing in-line assembly. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered.  2011 Microchip Technology Inc. DS39932D-page 153

PIC18F46J11 FAMILY Choosing the configuration requires the review of all EXAMPLE 10-7: CONFIGURING EUSART2 PPSs and their pin assignments, especially those that INPUT AND OUTPUT will not be used in the application. In all cases, unused FUNCTIONS pin selectable peripherals should be disabled com- ;************************************* pletely. Unused peripherals should have their inputs ; Unlock Registers assigned to an unused RPn pin function. I/O pins with ;************************************* unused RPn functions should be configured with the ; PPS registers are in BANK 14 null peripheral output. MOVLB 0x0E BCF INTCON, GIE ; Disable interrupts The assignment of a peripheral to a particular pin does MOVLW 0x55 not automatically perform any other configuration of the MOVWF EECON2, 0 pin’s I/O circuitry. In theory, this means adding a pin MOVLW 0xAA selectable output to a pin may mean inadvertently driv- MOVWF EECON2, 0 ing an existing peripheral input when the output is driven. Users must be familiar with the behavior of ; Turn off PPS Write Protect other fixed peripherals that share a remappable pin and BCF PPSCON, IOLOCK, BANKED know when to enable or disable them. To be safe, fixed digital peripherals that share the same pin should be ;*************************** disabled when not in use. ; Configure Input Functions ; (See Table 9-13) Along these lines, configuring a remappable pin for a ;*************************** specific peripheral does not automatically turn that ;*************************** feature on. The peripheral must be specifically config- ; Assign RX2 To Pin RP0 ured for operation and enabled, as if it were tied to a ;*************************** fixed pin. Where this happens in the application code MOVLW 0x00 (immediately following device Reset and peripheral MOVWF RPINR16, BANKED configuration or inside the main application routine) ;*************************** depends on the peripheral and its use in the ; Configure Output Functions application. ; (See Table 9-14) A final consideration is that the PPS functions neither ;*************************** override analog inputs nor reconfigure pins with analog ;*************************** functions for digital I/O. If a pin is configured as an ; Assign TX2 To Pin RP1 ;*************************** analog input on device Reset, it must be explicitly MOVLW 0x05 reconfigured as digital I/O when used with a PPS. MOVWF RPOR1, BANKED Example10-7 provides a configuration for bidirectional communication with flow control using EUSART2. The ;************************************* following input and output functions are used: ; Lock Registers ;************************************* • Input Function RX2 MOVLW 0x55 • Output Function TX2 MOVWF EECON2, 0 MOVLW 0xAA MOVWF EECON2, 0 ; Write Protect PPS BSF PPSCON, IOLOCK, BANKED Note: If the Configuration bit, IOL1WAY = 1, once the IOLOCK bit is set, it cannot be cleared, preventing any future RP register changes. The IOLOCK bit is cleared back to ‘0’ on any device Reset. DS39932D-page 154  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 10.7.6 PERIPHERAL PIN SELECT Note: Input and output register values can only REGISTERS be changed if PPS<IOLOCK> = 0. See The PIC18F46J11 family of devices implements a total Example10-7 for a specific command of 37 registers for remappable peripheral configuration sequence. of 44-pin devices. The 28-pin devices have 31 registers for remappable peripheral configuration. REGISTER 10-5: PPSCON: PERIPHERAL PIN SELECT INPUT REGISTER 0 (BANKED EFFh)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IOLOCK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 IOLOCK: I/O Lock Enable bit 1 = I/O lock active, RPORx and RPINRx registers are write-protected 0 = I/O lock not active, pin configurations can be changed Note 1: Register values can only be changed if PPSCON<IOLOCK>=0.  2011 Microchip Technology Inc. DS39932D-page 155

PIC18F46J11 FAMILY REGISTER 10-6: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 (BANKED EE7h) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INTR1R4 INTR1R3 INTR1R2 INTR1R1 INTR1R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 INTR1R<4:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits REGISTER 10-7: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 (BANKED EE8h) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INTR2R4 INTR2R3 INTR2R2 INTR2R1 INTR2R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 INTR2R<4:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn pin bits REGISTER 10-8: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 (BANKED EE9h) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INTR3R4 INTR3R3 INTR3R2 INTR3R1 INTR3R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 INTR3R<4:0>: Assign External Interrupt 3 (INT3) to the Corresponding RPn Pin bits DS39932D-page 156  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 10-9: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 (BANKED EEAh) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T0CKR4 T0CKR3 T0CKR2 T0CKR1 T0CKR0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T0CKR<4:0>: Timer0 External Clock Input (T0CKI) to the Corresponding RPn Pin bits REGISTER 10-10: RPINR6: PERIPHERAL PIN SELECT INPUT REGISTER 6 (BANKED EECh) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T3CKR<4:0>: Timer 3 External Clock Input (T3CKI) to the Corresponding RPn Pin bits REGISTER 10-11: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 (BANKED EEDh) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC1R<4:0>: Assign Input Capture 1 (ECCP1) to the Corresponding RPn Pin bits  2011 Microchip Technology Inc. DS39932D-page 157

PIC18F46J11 FAMILY REGISTER 10-12: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 (BANKED EEEh) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC2R<4:0>: Assign Input Capture 2 (ECCP2) to the Corresponding RPn Pin bits REGISTER 10-13: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (BANKED EF2h) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T1GR4 T1GR3 T1GR2 T1GR1 T1GR0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T1GR<4:0>: Timer1 Gate Input (T1G) to the Corresponding RPn Pin bits REGISTER 10-14: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 (BANKED EF3h) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T3GR4 T3GR3 T3GR2 T3GR1 T3GR0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T3GR<4:0>: Timer3 Gate Input (T3G) to the Corresponding RPn Pin bits DS39932D-page 158  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 10-15: RPINR16: PERIPHERAL PIN SELECT INPUT REGISTER 16 (BANKED EF6h) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — RX2DT2R4 RX2DT2R3 RX2DT2R2 RX2DT2R1 RX2DT2R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RX2DT2R<4:0>: EUSART2 Synchronous/Asynchronous Receive (RX2/DT2) to the Corresponding RPn Pin bits REGISTER 10-16: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 (BANKED EF7h) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — CK2R4 CK2R3 CK2R2 CK2R1 CK2R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 CK2R<4:0>: EUSART2 Clock Input (CK2) to the Corresponding RPn Pin bits REGISTER 10-17: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 (BANKED EFBh) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits  2011 Microchip Technology Inc. DS39932D-page 159

PIC18F46J11 FAMILY REGISTER 10-18: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 (BANKED EFCh) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SCK2R<4:0>: Assign SPI2 Clock Input (SCLK2) to the Corresponding RPn Pin bits REGISTER 10-19: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 (BANKED EFDh) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SS2R<4:0>: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits REGISTER 10-20: RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24 (BANKED EFEh) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign PWM Fault Input (FLT0) to the Corresponding RPn Pin bits DS39932D-page 160  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 10-21: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 (BANKED EC6h)(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table10-14 for peripheral function numbers) Note 1: Register values can be changed only if PPSCON<IOLOCK>=0. REGISTER 10-22: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 (BANKED EC7h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-23: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 (BANKED EC8h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table10-14 for peripheral function numbers)  2011 Microchip Technology Inc. DS39932D-page 161

PIC18F46J11 FAMILY REGISTER 10-24: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 (BANKED EC9h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-25: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 (BANKED ECAh) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-26: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 (BANKED ECBh) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP5R4 RP5R3 RP5R2 RP5R1 RP5R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table10-14 for peripheral function numbers) DS39932D-page 162  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 10-27: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 (BANKED ECCh) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-28: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 (BANKED ECDh) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-29: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 (BANKED ECEh) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table10-14 for peripheral function numbers)  2011 Microchip Technology Inc. DS39932D-page 163

PIC18F46J11 FAMILY REGISTER 10-30: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 (BANKED ECFh) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-31: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 (BANKED ED0h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-32: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 (BANKED ED1h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table10-14 for peripheral function numbers) DS39932D-page 164  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 10-33: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 (BANKED ED2h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-34: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 (BANKED ED3h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-35: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 (BANKED ED4h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table10-14 for peripheral function numbers)  2011 Microchip Technology Inc. DS39932D-page 165

PIC18F46J11 FAMILY REGISTER 10-36: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15 (BANKED ED5h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-37: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16 (BANKED ED6h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP16R<4:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-38: RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17 (BANKED ED7h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table10-14 for peripheral function numbers) DS39932D-page 166  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 10-39: RPOR18: PERIPHERAL PIN SELECT OUTPUT REGISTER 18 (BANKED ED8h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table10-14 for peripheral function numbers) REGISTER 10-40: RPOR19: PERIPHERAL PIN SELECT OUTPUT REGISTER 19 (BANKED ED9h)(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table10-14 for peripheral function numbers) Note 1: RP19 pins are not available on 28-pin devices. REGISTER 10-41: RPOR20: PERIPHERAL PIN SELECT OUTPUT REGISTER 20 (BANKED EDAh)(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table10-14 for peripheral function numbers) Note 1: RP20 pins are not available on 28-pin devices.  2011 Microchip Technology Inc. DS39932D-page 167

PIC18F46J11 FAMILY REGISTER 10-42: RPOR21: PERIPHERAL PIN SELECT OUTPUT REGISTER 21 (BANKED EDBh)(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits (see Table10-14 for peripheral function numbers) Note 1: RP21 pins are not available on 28-pin devices. REGISTER 10-43: RPOR22: PERIPHERAL PIN SELECT OUTPUT REGISTER 22 (BANKED EDCh)(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table10-14 for peripheral function numbers) Note 1: RP22 pins are not available on 28-pin devices. REGISTER 10-44: RPOR23: PERIPHERAL PIN SELECT OUTPUT REGISTER 23 (BANKED EDDh)(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table10-14 for peripheral function numbers) Note 1: RP23 pins are not available on 28-pin devices. DS39932D-page 168  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 10-45: RPOR24: PERIPHERAL PIN SELECT OUTPUT REGISTER 24 (BANKED EDEh)(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R/W = Readable, Writable if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table10-14 for peripheral function numbers) Note 1: RP24 pins are not available on 28-pin devices.  2011 Microchip Technology Inc. DS39932D-page 169

PIC18F46J11 FAMILY NOTES: DS39932D-page 170  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 11.0 PARALLEL MASTER PORT Key features of the PMP module are: (PMP) • Up to 16 bits of Addressing when Using Data/Address Multiplexing The Parallel Master Port module (PMP) is an 8-bit • Up to 8 Programmable Address Lines parallel I/O module, specifically designed to communi- • One Chip Select Line cate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory • Programmable Strobe Options: devices and microcontrollers. Because the interface to - Individual Read and Write Strobes or; parallel peripherals varies significantly, the PMP is - Read/Write Strobe with Enable Strobe highly configurable. The PMP module can be • Address Auto-Increment/Auto-Decrement configured to serve as either a PMP or as a Parallel • Programmable Address/Data Multiplexing Slave Port (PSP). • Programmable Polarity on Control Signals • Legacy Parallel Slave Port Support • Enhanced Parallel Slave Support: - Address Support - 4-Byte Deep, Auto-Incrementing Buffer • Programmable Wait States • Selectable Input Voltage Levels FIGURE 11-1: PMP MODULE OVERVIEW Address Bus Data Bus PMA<0> Control Lines PIC18 PMALL Parallel Master Port PMA<1> PMALH Up to 8-Bit Address PMA<7:2> EEPROM PMCS PMBE PMRD Microcontroller LCD FIFO PMRD/PMWR Buffer PMWR PMENB PMD<7:0> PMA<7:0> PMA<15:8> 8-Bit Data  2011 Microchip Technology Inc. DS39932D-page 171

PIC18F46J11 FAMILY 11.1 Module Registers The PMCON registers (Register11-1 and Register11-2) control basic module operations, includ- The PMP module has a total of 14 Special Function ing turning the module on or off. They also configure Registers (SFRs) for its operation, plus one additional address multiplexing and control strobe configuration. register to set configuration options. Of these, eight The PMMODE registers (Register11-3 and registers are used for control and six are used for PMP Register11-4) configure the various Master and Slave data transfer. modes, the data width and interrupt generation. 11.1.1 CONTROL REGISTERS The PMEH and PMEL registers (Register11-5 and The eight PMP Control registers are: Register11-6) configure the module’s operation at the hardware (I/O pin) level. • PMCONH and PMCONL The PMSTAT registers (Register11-5 and • PMMODEH and PMMODEL Register11-6) provide status flags for the module’s • PMSTATL and PMSTATH input and output buffers, depending on the operating mode. • PMEH and PMEL REGISTER 11-1: PMCONH: PARALLEL PORT CONTROL REGISTER HIGH BYTE (BANKED F5Fh)(1) R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPEN — — ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed bit 6-5 Unimplemented: Read as ‘0’ bit 4-3 ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins (only eight bits of address are available in this mode) 00 = Address and data appear on separate pins (only eight bits of address are available in this mode) bit 2 PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled bit 1 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled bit 0 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled Note 1: This register is only available in 44-pin devices. DS39932D-page 172  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 11-2: PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE (BANKED F5Eh)(1) R/W-0 R/W-0 R/W-0(2) U-0 R/W-0(2) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP — CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CSF<1:0>: Chip Select Function bits 11 = Reserved 10 = Chip select function is enabled and PMCS acts as chip select (in Master mode). Up to 13address bits only can be generated. 01 = Reserved 00 = Chip select function is disabled (in Master mode). All 16 address bits can be generated. bit 5 ALP: Address Latch Polarity bit(2) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 Unimplemented: Maintain as ‘0’ bit 3 CS1P: Chip Select Polarity bit(2) 1 = Active-high (PMCS) 0 = Active-low (PMCS) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODEH<1:0>=00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master Mode 1 (PMMODEH<1:0>=11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODEH<1:0>=00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master Mode 1 (PMMODEH<1:0>=11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: This register is only available in 44-pin devices. 2: These bits have no effect when their corresponding pins are used as address lines.  2011 Microchip Technology Inc. DS39932D-page 173

PIC18F46J11 FAMILY REGISTER 11-3: PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh)(1) R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 6-5 IRQM<1:0>: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated bit 4-3 INCM<1:0>: Increment Mode bits 11 =PSP read and write buffers auto-increment (Legacy PSP mode only) 10 =Decrement ADDR<15,13:0> by 1 every read/write cycle 01 =Increment ADDR<15,13:0> by 1 every read/write cycle 00 =No increment or decrement of address bit 2 MODE16: 8/16-Bit Mode bit 1 = 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers 0 = 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer bit 1-0 MODE<1:0>: Parallel Port Mode Select bits 11 =Master Mode 1 (PMCS, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>) 10 =Master Mode 2 (PMCS, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>) 01 =Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>) 00 =Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>) Note 1: This register is only available in 44-pin devices. DS39932D-page 174  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 11-4: PMMODEL: PARALLEL PORT MODE REGISTER LOW BYTE (BANKED F5Ch)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITB1(2) WAITB0(2) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(2) WAITE0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(2) 11 =Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 =Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 =Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 =Data wait of 1 TCY; multiplexed address phase of 1 TCY bit 5-2 WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY . . . 0001 = Wait of additional 1 TCY 0000 = No additional Wait cycles (operation forced into one TCY) bit 1-0 WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(2) 11 =Wait of 4 TCY 10 =Wait of 3 TCY 01 =Wait of 2 TCY 00 =Wait of 1 TCY Note 1: This register is only available in 44-pin devices. 2: WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000.  2011 Microchip Technology Inc. DS39932D-page 175

PIC18F46J11 FAMILY REGISTER 11-5: PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h)(1) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — PTEN14 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PTEN14: PMCS Port Enable bit 1 = PMCS chip select line 0 = PMCS functions as port I/O bit 5-0 Unimplemented: Read as ‘0’ Note 1: This register is only available in 44-pin devices. REGISTER 11-6: PMEL: PARALLEL PORT ENABLE REGISTER LOW BYTE (BANKED F56h)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 PTEN<7:2>: PMP Address Port Enable bits 1 = PMA<7:2> function as PMP address lines 0 = PMA<7:2> function as port I/O bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits 1 = PMA<1:0> function as either PMA<1:0> or PMALH and PMALL 0 = PMA<1:0> pads functions as port I/O Note 1: This register is only available in 44-pin devices. DS39932D-page 176  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 11-7: PMSTATH: PARALLEL PORT STATUS REGISTER HIGH BYTE (BANKED F55h)(1) R-0 R/W-0 U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 6 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 IB3F:IB0F: Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data Note 1: This register is only available in 44-pin devices. REGISTER 11-8: PMSTATL: PARALLEL PORT STATUS REGISTER LOW BYTE (BANKED F54h)(1) R-1 R/W-0 U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OB3E:OB0E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted Note 1: This register is only available in 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 177

PIC18F46J11 FAMILY 11.1.2 DATA REGISTERS PMADDRH differs from PMADDRL in that it can also have limited PMP control functions. When the module is The PMP module uses eight registers for transferring operating in select Master mode configurations, the data into and out of the microcontroller. They are upper two bits of the register can be used to determine arranged as four pairs to allow the option of 16-bit data the operation of chip select signals. If these are not operations: used, PMADDR simply functions to hold the upper 8 bits • PMDIN1H and PMDIN1L of the address. Register11-9 provides the function of • PMDIN2H and PMDIN2L the individual bits in PMADDRH. • PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L The PMDOUT2H and PMDOUT2L registers are only • PMDOUT2H and PMDOUT2L used in Buffered Slave modes and serve as a buffer for outgoing data. The PMDIN1 register is used for incoming data in Slave modes and both input and output data in Master 11.1.3 PAD CONFIGURATION CONTROL modes. The PMDIN2 register is used for buffering input REGISTER data in select Slave modes. In addition to the module level configuration options, The PMADDR/PMDOUT1 registers are actually a the PMP module can also be configured at the I/O pin single register pair; the name and function are dictated for electrical operation. This option allows users to by the module’s operating mode. In Master modes, the select either the normal Schmitt Trigger input buffer on registers function as the PMADDRH and PMADDRL digital I/O pins shared with the PMP, or use TTL level registers and contain the address of any incoming or compatible buffers instead. Buffer configuration is outgoing data. In Slave modes, the registers function controlled by the PMPTTL bit in the PADCFG1 register. as PMDOUT1H and PMDOUT1L and are used for outgoing data. DS39932D-page 178  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 11-9: PMADDRH: PARALLEL PORT ADDRESS REGISTER HIGH BYTE – MASTER MODES ONLY (ACCESS F6Fh)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CS1 Parallel Master Port Address High Byte<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ r = Reserved -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 CS1: Chip Select bit If PMCON<7:6> = 10: 1 = Chip select is active 0 = Chip select is inactive If PMCON<7:6> = 11 or 00: Bit functions as ADDR<14>. bit 5-0 Parallel Master Port Address: High Byte<13:8> bits Note 1: In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers. REGISTER 11-10: PMADDRL: PARALLEL PORT ADDRESS REGISTER LOW BYTE – MASTER MODES ONLY (ACCESS F6Eh)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Parallel Master Port Address Low Byte<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ r = Reserved -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 Parallel Master Port Address: Low Byte<7:0> bits Note 1: In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers.  2011 Microchip Technology Inc. DS39932D-page 179

PIC18F46J11 FAMILY 11.2 Slave Port Modes pins dedicated to the module. In this mode, an external device, such as another microcontroller or micro- The primary mode of operation for the module is processor, can asynchronously read and write data configured using the MODE<1:0> bits in the using the 8-bit data bus (PMD<7:0>), the read (PMRD), PMMODEH register. The setting affects whether the write (PMWR) and chip select (PMCS1) inputs. It acts module acts as a slave or a master, and it determines as a slave on the bus and responds to the read/write the usage of the control pins. control signals. 11.2.1 LEGACY MODE (PSP) Figure11-2 displays the connection of the PSP. When chip select is active and a write strobe occurs In Legacy mode (PMMODEH<1:0>=00 and (PMCS = 1 and PMWR = 1), the data from PMPEN=1), the module is configured as a Parallel PMD<7:0> is captured into the PMDIN1L register. Slave Port (PSP) with the associated enabled module FIGURE 11-2: LEGACY PARALLEL SLAVE PORT EXAMPLE Address Bus Master PIC18 Slave Data Bus PMD<7:0> PMD<7:0> Control Lines PMCS1 PMCS PMRD PMRD PMWR PMWR DS39932D-page 180  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 11.2.2 WRITE TO SLAVE PORT 11.2.3 READ FROM SLAVE PORT When chip select is active and a write strobe occurs When chip select is active and a read strobe occurs (PMCS=1 and PMWR=1), the data from PMD<7:0> (PMCS=1 and PMRD=1), the data from the is captured into the lower PMDIN1L register. The PMDOUT1L register (PMDOUT1L<7:0>) is presented PMPIF and IBF flag bits are set when the write onto PMD<7:0>. Figure11-4 provides the timing for the ends.The timing for the control signals in Write mode is control signals in Read mode. displayed in Figure11-3. The polarity of the control signals are configurable. FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD<7:0> IBF OBE PMPIF FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD<7:0> IBF OBE PMPIF  2011 Microchip Technology Inc. DS39932D-page 181

PIC18F46J11 FAMILY 11.2.4 BUFFERED PARALLEL SLAVE 11.2.4.2 WRITE TO SLAVE PORT PORT MODE For write operations, the data has to be stored Buffered Parallel Slave Port mode is functionally sequentially, starting with Buffer 0 (PMDIN1L<7:0>) identical to the legacy PSP mode with one exception, and ending with Buffer 3 (PMDIN2H<7:0>). As with the implementation of 4-level read and write buffers. read operations, the module maintains an internal Buffered PSP mode is enabled by setting the INCM bits pointer to the buffer that is to be written next. in the PMMODEH register. If the INCM<1:0> bits are The input buffers have their own write status bits, IBxF set to ‘11’, the PMP module will act as the Buffered in the PMSTATH register. The bit is set when the buffer PSP. contains unread incoming data, and cleared when the When the Buffered mode is active, the PMDIN1L, data has been read. The flag bit is set on the write PMDIN1H, PMDIN2L and PMDIN2H registers become strobe. If a write occurs on a buffer when its associated the write buffers and the PMDOUT1L, PMDOUT1H, IBxF bit is set, the Buffer Overflow flag, IBOV, is set; PMDOUT2L and PMDOUT2H registers become the any incoming data in the buffer will be lost. If all four read buffers. Buffers are numbered 0 through 3, start- IBxF flags are set, the Input Buffer Full Flag (IBF) is set. ing with the lower byte of PMDIN1L to PMDIN2H as the In Buffered Slave mode, the module can be configured read buffers and PMDOUT1L to PMDOUT2H as the to generate an interrupt on every read or write strobe write buffers. (IRQM<1:0>=01). It can be configured to generate an interrupt on a read from Read Buffer 3 or a write to 11.2.4.1 READ FROM SLAVE PORT Write Buffer 3, which is essentially an interrupt every For read operations, the bytes will be sent out fourth read or write strobe (RQM<1:0>=11). When sequentially, starting with Buffer 0 (PMDOUT1L<7:0>) interrupting every fourth byte for input data, all input and ending with Buffer 3 (PMDOUT2H<7:0>) for every buffer registers should be read to clear the IBxF flags. read strobe. The module maintains an internal pointer If these flags are not cleared, then there is a risk of to keep track of which buffer is to be read. Each buffer hitting an overflow condition. has a corresponding read status bit, OBxE, in the PMSTATL register. This bit is cleared when a buffer contains data that has not been written to the bus, and is set when data is written to the bus. If the current buf- fer location being read from is empty, a buffer underflow is generated, and the Buffer Overflow flag bit, OBUF, is set. If all four OBxE status bits are set, then the Output Buffer Empty flag (OBE) will also be set. FIGURE 11-5: PARALLEL MASTER/SLAVE CONNECTION BUFFERED EXAMPLE Master PIC18 Slave PMD<7:0> Write Read PMD<7:0> Address Address Pointer Pointer PMDOUT1L (0) PMDIN1L (0) PMCS PMCS PMDOUT1H (1) PMDIN1H (1) PMRD PMRD PMDOUT2L (2) PMDIN2L (2) PMWR PMWR PMDOUT2H (3) PMDIN2H (3) Data Bus Control Lines DS39932D-page 182  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 11.2.5 ADDRESSABLE PARALLEL SLAVE TABLE 11-1: SLAVE MODE BUFFER PORT MODE ADDRESSING In the Addressable Parallel Slave Port mode Output Input Register (PMMODEH<1:0>=01), the module is configured with PMA<1:0> Register (Buffer) two extra inputs, PMA<1:0>, which are the address (Buffer) lines 1 and 0. This makes the 4-byte buffer space 00 PMDOUT1L (0) PMDIN1L (0) directly addressable as fixed pairs of read and write buffers. As with Legacy Buffered mode, data is output 01 PMDOUT1H (1) PMDIN1H (1) from PMDOUT1L, PMDOUT1H, PMDOUT2L and 10 PMDOUT2L (2) PMDIN2L (2) PMDOUT2H, and is read in on PMDIN1L, PMDIN1H, 11 PMDOUT2H((3) PMDIN2H (3) PMDIN2L and PMDIN2H. Table11-1 provides the buffer addressing for the incoming address to the input and output registers. FIGURE 11-6: PARALLEL MASTER/SLAVE CONNECTION ADDRESSED BUFFER EXAMPLE Master PIC18F Slave PMA<1:0> PMA<1:0> PMD<7:0> Write Read PMD<7:0> Address Address Decode Decode PMDOUT1L (0) PMDIN1L (0) PMCS PMCS PMDOUT1H (1) PMDIN1H (1) PMRD PMRD PMDOUT2L (2) PMDIN2L (2) PMWR PMWR PMDOUT2H (3) PMDIN2H (3) Address Bus Data Bus Control Lines 11.2.5.1 READ FROM SLAVE PORT output registers and their associated address. When an output buffer is read, the corresponding OBxE bit is set. When chip select is active and a read strobe occurs The OBxE flag bit is set when all the buffers are empty. (PMCS = 1 and PMRD = 1), the data from one of the If any buffer is already empty, OBxE = 1, the next read four output bytes is presented onto PMD<7:0>. Which to that buffer will generate an OBUF event. byte is read depends on the 2-bit address placed on ADDR<1:0>. Table11-1 provides the corresponding FIGURE 11-7: PARALLEL SLAVE PORT READ WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD<7:0> PMA<1:0> OBE PMPIF  2011 Microchip Technology Inc. DS39932D-page 183

PIC18F46J11 FAMILY 11.2.5.2 WRITE TO SLAVE PORT When an input buffer is written, the corresponding IBxF bit is set. The IBF flag bit is set when all the buffers are When chip select is active and a write strobe occurs written. If any buffer is already written (IBxF = 1), the (PMCS = 1 and PMWR = 1), the data from PMD<7:0> next write strobe to that buffer will generate an OBUF is captured into one of the four input buffer bytes. event and the byte will be discarded. Which byte is written depends on the 2-bit address placed on ADDRL<1:0>. Table11-1 provides the corresponding input registers and their associated address. FIGURE 11-8: PARALLEL SLAVE PORT WRITE WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD<7:0> PMA<1:0> IBF PMPIF DS39932D-page 184  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 11.3 MASTER PORT MODES Note that the polarity of control signals that share the same output pin (for example, PMWR and PMENB) are In its Master modes, the PMP module provides an 8-bit controlled by the same bit; the configuration depends data bus, up to 16 bits of address, and all the necessary on which Master Port mode is being used. control signals to operate a variety of external parallel devices, such as memory devices, peripherals and 11.3.3 DATA WIDTH slave microcontrollers. To use the PMP as a master, The PMP supports data widths of both 8 bits and the module must be enabled (PMPEN = 1) and the 16bits. The data width is selected by the MODE16 bit mode must be set to one of the two possible Master (PMMODEH<2>). Because the data path into and out modes (PMMODEH<1:0> = 10 or 11). of the module is only 8 bits wide, 16-bit operations are Because there are a number of parallel devices with a always handled in a multiplexed fashion, with the Least variety of control methods, the PMP module is designed Significant Byte (LSB) of data being presented first. To to be extremely flexible to accommodate a range of differentiate data bytes, the byte enable control strobe, configurations. Some of these features include: PMBE, is used to signal when the Most Significant Byte • 8-Bit and 16-Bit Data modes on an 8-bit data bus (MSB) of data is being presented on the data lines. • Configurable address/data multiplexing 11.3.4 ADDRESS MULTIPLEXING • Up to two chip select lines In either of the Master modes (PMMODEH<1:0> = 1x), • Up to 16 selectable address lines the user can configure the address bus to be multiplexed • Address auto-increment and auto-decrement together with the data bus. This is accomplished by • Selectable polarity on all control lines using the ADRMUX<1:0> bits (PMCONH<4:3>). There • Configurable Wait states at different stages of the are three address multiplexing modes available; typical read/write cycle pinout configurations for these modes are displayed in Figure11-9, Figure11-10 and Figure11-11. 11.3.1 PMP AND I/O PIN CONTROL In Demultiplexed mode (PMCONH<4:3> = 00), data and Multiple control bits are used to configure the presence address information are completely separated. Data bits or absence of control and address signals in the are presented on PMD<7:0> and address bits are module. These bits are PTBEEN, PTWREN, PTRDEN presented on PMADDRH<6:0> and PMADDRL<7:0>. and PTEN<15:0>. They give the user the ability to con- In Partially Multiplexed mode (PMCONH<4:3> = 01), the serve pins for other functions and allow flexibility to lower eight bits of the address are multiplexed with the control the external address. When any one of these data pins on PMD<7:0>. The upper eight bits of address bits is set, the associated function is present on its are unaffected and are presented on PMADDRH<6:0>. associated pin; when clear, the associated pin reverts The PMA0 pin is used as an address latch, and presents to its defined I/O port function. the address latch low enable strobe (PMALL). The read Setting a PTENx bit will enable the associated pin as and write sequences are extended by a complete CPU an address pin and drive the corresponding data cycle during which the address is presented on the contained in the PMADDR register. Clearing a PTENx PMD<7:0> pins. bit will force the pin to revert to its original I/O function. In Fully Multiplexed mode (PMCONH<4:3> = 10), the For the pins configured as chip select (PMCS) with the entire 16 bits of the address are multiplexed with the corresponding PTENx bit set, the PTEN0 and PTEN1 data pins on PMD<7:0>. The PMA0 and PMA1 pins are bits will also control the PMALL and PMALH signals. used to present address latch low enable (PMALL) and When multiplexing is used, the associated address address latch high enable (PMALH) strobes, latch signals should be enabled. respectively. The read and write sequences are extended by two complete CPU cycles. During the first 11.3.2 READ/WRITE CONTROL cycle, the lower eight bits of the address are presented The PMP module supports two distinct read/write on the PMD<7:0> pins with the PMALL strobe active. signaling methods. In Master Mode 1, read and write During the second cycle, the upper eight bits of the strobes are combined into a single control line, address are presented on the PMD<7:0> pins with the PMRD/PMWR. A second control line, PMENB, deter- PMALH strobe active. In the event the upper address mines when a read or write action is to be taken. In bits are configured as chip select pins, the Master Mode 2, separate read and write strobes corresponding address bits are automatically forced (PMRD and PMWR) are supplied on separate pins. to‘0’. All control signals (PMRD, PMWR, PMBE, PMENB, PMAL and PMCS) can be individually configured as either positive or negative polarity. Configuration is controlled by separate bits in the PMCONL register.  2011 Microchip Technology Inc. DS39932D-page 185

PIC18F46J11 FAMILY FIGURE 11-9: DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F PMA<7:0> PMD<7:0> PMCS PMRD Address Bus Data Bus PMWR Control Lines FIGURE 11-10: PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F PMD<7:0> PMA<7:0> PMCS PMALL Address Bus PMRD Multiplexed Data and Address Bus PMWR Control Lines FIGURE 11-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F PMD<7:0> PMA<13:8> PMCS PMALL PMALH Multiplexed PMRD Data and Address Bus PMWR Control Lines DS39932D-page 186  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 11.3.5 CHIP SELECT FEATURES Note that the read data obtained from the PMDIN1L register is actually the read value from the previous One chip select line, PMCS, is available for the Master read operation. Hence, the first user read will be a modes of the PMP. The chip select line is multiplexed dummy read to initiate the first bus read and fill the read with the second Most Significant bit (MSb) of the register. Also, the requested read value will not be address bus (PMADDRH<6>). When configured for ready until after the BUSY bit is observed low. Thus, in chip select, the PMADDRH<7:6> bits are not included a back-to-back read operation, the data read from the in any address auto-increment/decrement. The register will be the same for both reads. The next read function of the chip select signal is configured using the of the register will yield the new value. chip select function bits (PMCONL<7:6>). 11.3.9 WRITE OPERATION 11.3.6 AUTO-INCREMENT/DECREMENT To perform a write onto the parallel bus, the user writes While the module is operating in one of the Master to the PMDIN1L register. This causes the module to modes, the INCMx bits (PMMODEH<4:3>) control the first output the desired values on the chip select lines behavior of the address value. The address can be and the address bus. The write data from the PMDIN1L made to automatically increment or decrement after register is placed onto the PMD<7:0> data bus. Then each read and write operation. The address increments the write line (PMWR) is strobed. If the 16-bit mode is once each operation is completed and the BUSY bit enabled (MODE16 = 1), the write to the PMDIN1L goes to ‘0’. If the chip select signals are disabled and register will initiate two bus writes. The first write will configured as address bits, the bits will participate in consist of the data contained in PMDIN1L and the the increment and decrement operations; otherwise, second write will contain the PMDIN1H. the CS1 bit values will be unaffected. 11.3.10 PARALLEL MASTER PORT STATUS 11.3.7 WAIT STATES In Master mode, the user has control over the duration 11.3.10.1 The BUSY Bit of the read, write and address cycles by configuring the In addition to the PMP interrupt, a BUSY bit is provided module Wait states. Three portions of the cycle, the to indicate the status of the module. This bit is used beginning, middle and end, are configured using the only in Master mode. While any read or write operation corresponding WAITBx, WAITMx and WAITEx bits in is in progress, the BUSY bit is set for all but the very last the PMMODEL register. CPU cycle of the operation. In effect, if a single-cycle The WAITBx bits (PMMODEL<7:6>) set the number of read or write operation is requested, the BUSY bit will Wait cycles for the data setup prior to the never be active. This allows back-to-back transfers. PMRD/PMWT strobe in Mode 10, or prior to the While the bit is set, any request by the user to initiate a PMENB strobe in Mode 11. The WAITMx bits new operation will be ignored (i.e., writing or reading (PMMODEL<5:2>) set the number of Wait cycles for the lower byte of the PMDIN1L register will neither the PMRD/PMWT strobe in Mode 10, or for the PMENB initiate a read nor a write). strobe in Mode 11. When this Wait state setting is ‘0’, then WAITB and WAITE have no effect. The WAITE 11.3.10.2 Interrupts bits (PMMODEL<1:0>) define the number of Wait When the PMP module interrupt is enabled for Master cycles for the data hold time after the PMRD/PMWT mode, the module will interrupt on every completed strobe in Mode 10, or after the PMENB strobe in read or write cycle; otherwise, the BUSY bit is available Mode11. to query the status of the module. 11.3.8 READ OPERATION To perform a read on the PMP, the user reads the PMDIN1L register. This causes the PMP to output the desired values on the chip select lines and the address bus. Then the read line (PMRD) is strobed. The read data is placed into the PMDIN1L register. If the 16-bit mode is enabled (MODE16 = 1), the read of the low byte of the PMDIN1L register will initiate two bus reads. The first read data byte is placed into the PMDIN1L register, and the second read data is placed into the PMDIN1H.  2011 Microchip Technology Inc. DS39932D-page 187

PIC18F46J11 FAMILY 11.3.11 MASTER MODE TIMING This section contains a number of timing examples that represent the common Master mode configuration options. These options vary from 8-bit to 16-bit data, fully demultiplexed to fully multiplexed address and Wait states. FIGURE 11-12: READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> PMA<7:0> PMWR PMRD PMPIF BUSY FIGURE 11-13: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> Address<7:0> Data PMWR PMRD PMALL PMPIF BUSY FIGURE 11-14: READ TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - PMCS PMD<7:0> Address<7:0> Data PMRD PMWR PMALL PMPIF BUSY WAITB<1:0> = 01 WAITE<1:0> = 00 WAITM<3:0> = 0010 DS39932D-page 188  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 11-15: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> Address<7:0> Data PMWR PMRD PMALL PMPIF BUSY FIGURE 11-16: WRITE TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - PMCS PMD<7:0> Address<7:0> Data PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> = 01 WAITE<1:0> = 00 WAITM<3:0> = 0010 FIGURE 11-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> Address<7:0> Data PMRD/PMWR PMENB PMALL PMPIF BUSY  2011 Microchip Technology Inc. DS39932D-page 189

PIC18F46J11 FAMILY FIGURE 11-18: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> Address<7:0> Data PMRD/PMWR PMENB PMALL PMPIF BUSY FIGURE 11-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> Address<7:0> Address<13:8> Data PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 11-20: WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> Address<7:0> Address<13:8> Data PMWR PMRD PMALL PMALH PMPIF BUSY DS39932D-page 190  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 11-21: READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> LSB MSB PMA<7:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-22: WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> LSB MSB PMA<7:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> Address<7:0> LSB MSB PMWR PMRD PMBE PMALL PMPIF BUSY  2011 Microchip Technology Inc. DS39932D-page 191

PIC18F46J11 FAMILY FIGURE 11-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> Address<7:0> LSB MSB PMWR PMRD PMBE PMALL PMPIF BUSY FIGURE 11-25: READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> Address<7:0> Address<13:8> LSB MSB PMWR PMRD PMBE PMALL PMALH PMPIF BUSY FIGURE 11-26: WRITE TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD<7:0> Address<7:0> Address<13:8> LSB MSB PMWR PMRD PMBE PMALL PMALH PMPIF BUSY DS39932D-page 192  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 11.4 Application Examples 11.4.1 MULTIPLEXED MEMORY OR PERIPHERAL This section introduces some potential applications for the PMP module. Figure11-27 demonstrates the hookup of a memory or another addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective. However, for this configuration, there needs to be some external latches to maintain the address. FIGURE 11-27: EXAMPLE – MULTIPLEXED ADDRESSING APPLICATION PIC18F A<7:0> PMD<7:0> 373 A<13:0> PMALL D<7:0> D<7:0> CE A<15:8> 373 OE WR PMALH PMCS Address Bus PMRD Data Bus PMWR Control Lines 11.4.2 PARTIALLY MULTIPLEXED an external latch. If the peripheral has internal latches, MEMORY OR PERIPHERAL as displayed in Figure11-29, then no extra circuitry is required except for the peripheral itself. Partial multiplexing implies using more pins; however, for a few extra pins, some extra performance can be achieved. Figure11-28 provides an example of a memory or peripheral that is partially multiplexed with FIGURE 11-28: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC18F A<7:0> PMD<7:0> 373 A<7:0> PMALL D<7:0> D<7:0> CE PMCS OE WR Address Bus PMRD Data Bus PMWR Control Lines FIGURE 11-29: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC18F Parallel Peripheral PMD<7:0> AD<7:0> PMALL ALE PMCS CS Address Bus PMRD RD Data Bus PMWR WR Control Lines  2011 Microchip Technology Inc. DS39932D-page 193

PIC18F46J11 FAMILY 11.4.3 PARALLEL EEPROM EXAMPLE Figure11-30 provides an example connecting parallel EEPROM to the PMP. Figure11-31 demonstrates a slight variation to this, configuring the connection for 16-bit data from a single EEPROM. FIGURE 11-30: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA) PIC18F Parallel EEPROM PMA<n:0> A<n:0> PMD<7:0> D<7:0> PMCS CE Address Bus PMRD OE Data Bus PMWR WR Control Lines FIGURE 11-31: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA) PIC18F Parallel EEPROM PMA<n:0> A<n:1> PMD<7:0> D<7:0> PMBE A0 PMCS CE Address Bus PMRD OE Data Bus PMWR WR Control Lines 11.4.4 LCD CONTROLLER EXAMPLE The PMP module can be configured to connect to a typical LCD controller interface, as displayed in Figure11-32. In this case, the PMP module is config- ured for active-high control signals since common LCD displays require active-high control. FIGURE 11-32: LCD CONTROL EXAMPLE (BYTE MODE OPERATION) PIC18F LCD Controller PM<7:0> D<7:0> PMA0 RS PMRD/PMWR R/W Address Bus PMCS E Data Bus Control Lines DS39932D-page 194  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 11-2: REGISTERS ASSOCIATED WITH PMP MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PMPIF(2) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE(2) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP(2) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72 PMCONH(2) PMPEN — — ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 73 PMCONL(2) CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 73 PMADDRH(1,2)/ — CS1 Parallel Master Port Address High Byte 73 PMDOUT1H(1,2) Parallel Port Out Data High Byte (Buffer 1) 73 PMADDRL(1,2)/ Parallel Master Port Address Low Byte 73 PMDOUT1L(1,2) Parallel Port Out Data Low Byte (Buffer 0) 73 PMDOUT2H(2) Parallel Port Out Data High Byte (Buffer 3) 73 PMDOUT2L(2) Parallel Port Out Data Low Byte (Buffer 2) 73 PMDIN1H(2) Parallel Port In Data High Byte (Buffer 1) 73 PMDIN1L(2) Parallel Port In Data Low Byte (Buffer 0) 73 PMDIN2H(2) Parallel Port In Data High Byte (Buffer 3) 73 PMDIN2L(2) Parallel Port In Data Low Byte (Buffer 2) 73 PMMODEH(2) BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 73 PMMODEL(2) WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 73 PMEH(2) — PTEN14 — — — — — — 74 PMEL(2) PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 74 PMSTATH(2) IBF IBOV — — IB3F IB2F IB1F IB0F 74 PMSTATL(2) OBE OBUF — — OB3E OB2E OB1E OB0E 74 PADCFG1 — — — — — RTSECSEL1 RTSECSEL0 PMPTTL 74 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during PMP operation. Note 1: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. 2: These bits and/or registers are only available in 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 195

PIC18F46J11 FAMILY NOTES: DS39932D-page 196  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 12.0 TIMER0 MODULE The T0CON register (Register12-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or Figure12-1 provides a simplified block diagram of the counter in both 8-bit or 16-bit modes Timer0 module in 8-bit mode. Figure12-2 provides a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER (ACCESS FD5h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin input edge 0 = Internal clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = Timer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value  2011 Microchip Technology Inc. DS39932D-page 197

PIC18F46J11 FAMILY 12.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter. The timer/counter. mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on 12.2 Timer0 Reads and Writes in 16-Bit every clock by default unless a different prescaler value Mode is selected (see Section12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited TMR0H is not the actual high byte of Timer0 in 16-bit for the following two instruction cycles. The user can mode. It is actually a buffered version of the real high work around this by writing an adjusted value to the byte of Timer0, which is not directly readable nor TMR0 register. writable (refer to Figure12-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of The Counter mode is selected by setting the T0CS bit TMR0L. This provides the ability to read all 16 bits of (= 1). In this mode, Timer0 increments either on every Timer0 without having to verify that the read of the high rising edge or falling edge of pin, T0CKI. The and low byte were valid, due to a rollover between incrementing edge is determined by the Timer0 Source successive reads of the high and low byte. Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external Similarly, a write to the high byte of Timer0 must also clock input are discussed below. take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a An external clock source can be used to drive Timer0; write occurs to TMR0L. This allows all 16 bits of Timer0 however, it must meet certain requirements to ensure to be updated at once. that the external clock can be synchronized with the FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) T0CS 3 8 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with TMR0 Set 1 Internal TMR0L High Byte TMR0IF T0CKI pin ProPgrreasmcamlearble 0 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39932D-page 198  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 12.3 Prescaler 12.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. The prescaler assignment is fully under software Its value is set by the PSA and T0PS<2:0> bits control and can be changed “on-the-fly” during program (T0CON<3:0>), which determine the prescaler execution. assignment and prescale ratio. 12.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0 from 1:2 through 1:256 in power-of-2 increments are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before TMR0, BSF TMR0, etc.) clear the prescaler count. re-enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine Note: Writing to TMR0 when the prescaler is (ISR). assigned to Timer0 will clear the prescaler count but will not change the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 assignment. interrupt cannot awaken the processor from Sleep. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: TMR0L Timer0 Register Low Byte 91 TMR0H Timer0 Register High Byte 91 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 90 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 91 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.  2011 Microchip Technology Inc. DS39932D-page 199

PIC18F46J11 FAMILY NOTES: DS39932D-page 200  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 13.0 TIMER1 MODULE Figure13-1 displays a simplified block diagram of the Timer1 module. The Timer1 timer/counter module incorporates these The module incorporates its own low-power oscillator features: to provide an additional clocking option. The Timer1 • Software selectable operation as a 16-bit timer or oscillator can also be used as a low-power clock source counter for the microcontroller in power-managed operation. • Readable and writable 8-bit registers (TMR1H Timer1 is controlled through the T1CON Control and TMR1L) register (Register13-1). It also contains the Timer1 • Selectable clock source (internal or external) with oscillator Enable bit (T1OSCEN). Timer1 can be device clock or Timer1 oscillator internal options enabled or disabled by setting or clearing control bit, • Interrupt-on-overflow TMR1ON (T1CON<0>). • Reset on ECCP Special Event Trigger The FOSC clock source (TMR1CS<1:0> = 01) should • Device clock status flag (T1RUN) not be used with the ECCP capture/compare features. • Timer with gated control If the timer will be used with the capture or compare features, always select one of the other timer clocking options. REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER (ACCESS FCDh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 10 = Timer1 clock source is T1OSC or T1CKI pin 01 = Timer1 clock source is system clock (FOSC)(1) 00 = Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Crystal Oscillator Enable bit 1 = Timer1 oscillator circuit enabled 0 = Timer1 oscillator circuit disabled The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit TMR1CS<1:0> = 10: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS<1:0> = 0x: This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 0x. bit 1 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features.  2011 Microchip Technology Inc. DS39932D-page 201

PIC18F46J11 FAMILY 13.1 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), displayed in Register13-2, is used to control the Timer1 gate. REGISTER 13-2: T1GCON: TIMER1 GATE CONTROL REGISTER (F9Ah)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0 TMR1GE T1GPOL T1GTM T1GSPM T1GGO/T1DONE T1GVAL T1GSS1 T1GSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored. If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single Pulse Mode bit 1 = Timer1 Gate Single Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single Pulse mode is disabled bit 3 T1GGO/T1DONE: Timer1 Gate Single Pulse Acquisition Status bit 1 = Timer1 gate single pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L; unaffected by Timer1 Gate Enable (TMR1GE) bit. bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 gate pin 01 = Timer0 overflow output 10 = TMR2 to match PR2 output Note 1: Programming the T1GCON prior to T1CON is recommended. DS39932D-page 202  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 13-3: TCLKCON: TIMER CLOCK CONTROL REGISTER (BANKED F52h) U-0 U-0 U-0 R-0 U-0 U-0 R/W-0 R/W-0 — — — T1RUN — — T3CCP2 T3CCP1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 T1RUN: Timer1 Run Status bit 1 = Device is currently clocked by T1OSC/T1CKI 0 = System clock comes from an oscillator other than T1OSC/T1CKI bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 T3CCP<2:1>: ECCP Timer Assignment bits 10 = ECCP1 and ECCP2 both use Timer3 (capture/compare) and Timer4 (PWM) 01 = ECCP1 uses Timer1 (compare/capture) and Timer2 (PWM); ECCP2 uses Timer3 (capture/compare) and Timer4 (PWM) 00 = ECCP1 and ECCP2 both use Timer1 (capture/compare) and Timer2 (PWM)  2011 Microchip Technology Inc. DS39932D-page 203

PIC18F46J11 FAMILY 13.2 Timer1 Operation 13.3.1 INTERNAL CLOCK SOURCE The Timer1 module is an 8-bit or 16-bit incrementing When the internal clock source is selected, the counter, which is accessed through the TMR1H:TMR1L register pair will increment on multiples TMR1H:TMR1L register pair. of FOSC as determined by the Timer1 prescaler. When used with an internal clock source, the module is 13.3.2 EXTERNAL CLOCK SOURCE a timer and increments on every instruction cycle. When the external clock source is selected, the Timer1 When used with an external clock source, the module module may work as a timer or a counter. can be used as either a timer or counter and increments on every selected edge of the external When enabled to count, Timer1 is incremented on the source. rising edge of the external clock input, T1CKI, or the capacitive sensing oscillator signal. Either of these Timer1 is enabled by configuring the TMR1ON and external clock sources can be synchronized to the TMR1GE bits in the T1CON and T1GCON registers, microcontroller system clock or they can run respectively. asynchronously. When Timer1 is enabled, the RC1/T1OSI/RP12 and When used as a timer with a clock oscillator, an RC0/T1OSO/T1CKI/RP11 pins become inputs. This external 32.768 kHz crystal can be used in conjunction means the values of TRISC<1:0> are ignored and the with the dedicated internal oscillator circuit. pins are read as ‘0’. Note: In Counter mode, a falling edge must be 13.3 Clock Source Selection registered by the counter prior to the first incrementing rising edge after any one or The TMR1CS<1:0> and T1OSCEN bits of the T1CON more of the following conditions: register are used to select the clock source for Timer1. • Timer1 enabled after POR Reset Register13-1 displays the clock source selections. • Write to TMR1H or TMR1L When switching clock sources and using the clock • Timer1 is disabled prescaler, write to TMR1L afterwards to reset the • Timer1 is disabled (TMR1ON = 0) internal prescaler count to 0. when T1CKI is high, then Timer1 is enabled (TMR1ON = 1) when T1CKI is low. TABLE 13-1: TIMER1 CLOCK SOURCE SELECTION TMR1CS1 TMR1CS0 T1OSCEN Clock Source 0 1 x Clock Source (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 0 0 External Clock on T1CKI Pin 1 0 1 Oscillator Circuit on T1OSI/T1OSO Pin DS39932D-page 204  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 13-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 T1GSPM From Timer0 01 T1G_IN 0 Data Bus Overflow 0 T1GVAL D Q FMraotmch T PimRe2r2 10 SAicnqg.l eC Ponutlrsoel 1 Q1 EN T1GRCDON D Q 1 CK Q T1GGO/T1DONE Interrupt Set TMR1ON R det RTCCIF T1GPOL T1GTM TMR1GE Set Flag bit TMR1ON TMR1IF on Overflow TMR1(2) EN Synchronized TMR1H TMR1L T1CLK 0 Clock Input Q D 1 TMR1CS<1:0> T1SYNC T1OSO/T1CKI OUT T1OSC Prescaler Synchronize(3) 1 1, 2, 4, 8 det T1OSI 10 EN 2 0 FOSC T1CKPS<1:0> Internal 01 Clock T1OSCEN IFnOteSrCn/a2l Sleep Input IFnOteSrCn/a4l 00 Clock (1) Clock T1CKI Note 1: ST Buffer is high-speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2011 Microchip Technology Inc. DS39932D-page 205

PIC18F46J11 FAMILY 13.4 Timer1 16-Bit Read/Write Mode TABLE 13-2: CAPACITOR SELECTION FOR THE TIMER Timer1 can be configured for 16-bit reads and writes. OSCILLATOR(2,3,4,5) When the RD16 control bit (T1CON<1>) is set, the address for TMR1H is mapped to a buffer register for Oscillator Freq. C1 C2 the high byte of Timer1. A read from TMR1L loads the Type contents of the high byte of Timer1 into the Timer1 High LP 32kHz 12pF(1) 12pF(1) Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without Note1: Microchip suggests these values as a having to determine whether a read of the high byte, starting point in validating the oscillator followed by a read of the low byte, has become invalid circuit. due to a rollover between reads. 2: Higher capacitance increases the stabil- A write to the high byte of Timer1 must also take place ity of the oscillator but also increases the through the TMR1H Buffer register. The Timer1 high start-up time. byte is updated with the contents of TMR1H when a 3: Since each resonator/crystal has its own write occurs to TMR1L. This allows a user to write all characteristics, the user should consult 16 bits to both the high and low bytes of Timer1 at once. the resonator/crystal manufacturer for The high byte of Timer1 is not directly readable or appropriate values of external writable in this mode. All reads and writes must take components. place through the Timer1 High Byte Buffer register. 4: Capacitor values are for design Writes to TMR1H do not clear the Timer1 prescaler. guidance only. Values listed would be The prescaler is only cleared on writes to TMR1L. typical of a CL = 10 pF rated crystal, when LPT1OSC = 1. 13.5 Timer1 Oscillator 5: Incorrect capacitance value may result in An on-chip crystal oscillator circuit is incorporated a frequency not meeting the crystal between pins, T1OSI (input) and T1OSO (amplifier manufacturer’s tolerance specification. output). It is enabled by setting the Timer1 Oscillator The Timer1 crystal oscillator drive level is determined Enable bit, T1OSCEN (T1CON<3>). The oscillator is a based on the LPT1OSC (CONFIG2L<4>) Configura- low-power circuit rated for 32kHz crystals. It will tion bit. The higher drive level mode, LPT1OSC = 1, is continue to run during all power-managed modes. The intended to drive a wide variety of 32.768 kHz crystals circuit for a typical LP oscillator is depicted in with a variety of load capacitance (CL) ratings. Figure13-2. Table13-2 provides the capacitor selection for the Timer1 oscillator. The lower drive level mode is highly optimized for extremely low-power consumption. It is not intended to The user must provide a software time delay to ensure drive all types of 32.768 kHz crystals. In the low drive proper start-up of the Timer1 oscillator. level mode, the crystal oscillator circuit may not work if excessively large discrete capacitors are placed on the FIGURE 13-2: EXTERNAL COMPONENTS T1OSI and T1OSO pins. This mode is only designed to FOR THE TIMER1 LP work with discrete capacitances of approximately OSCILLATOR 3pF-10 pF on each pin. C1 Crystal manufacturers usually specify a CL (load PIC18F46J11 12 pF capacitance) rating for their crystals. This value is T1OSI related to, but not necessarily the same as, the values that should be used for C1 and C2 in Figure13-2. See XTAL the crystal manufacturer’s applications’ information for 32.768 kHz more details on how to select the optimum C1 and C2 for a given crystal. The optimum value depends in part T1OSO on the amount of parasitic capacitance in the circuit, C2 which is often unknown. Therefore, after values have 12 pF been selected, it is highly recommended that thorough Note: See the Notes with Table13-2 for additional testing and validation of the oscillator be performed. information about capacitor selection. DS39932D-page 206  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 13.5.1 USING TIMER1 AS A FIGURE 13-3: OSCILLATOR CIRCUIT CLOCKSOURCE WITH GROUNDED GUARD RING The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select VDD bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device switches to SEC_RUN mode; both the CPU and VSS peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP OSC1 instruction is executed, the device enters SEC_IDLE OSC2 mode. Additional details are available in Section4.0 “Low-Power Modes”. Whenever the Timer1 oscillator is providing the clock source, the Timer1 system clock status flag, T1RUN RC0 (TCLKCON<4>), is set. This can be used to determine RC1 the controller’s current clocking mode. It can also indicate the clock source currently being used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled RC2 and the Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is Note: Not drawn to scale. being provided by the Timer1 oscillator or another source. In the low drive level mode, LPT1OSC = 0, it is critical that RC2 I/O pin signals be kept away from the oscillator 13.5.2 TIMER1 OSCILLATOR LAYOUT circuit. Configuring RC2 as a digital output, and toggling CONSIDERATIONS it, can potentially disturb the oscillator circuit, even with relatively good PCB layout. If possible, it is recom- The Timer1 oscillator circuit draws very little power mended to either leave RC2 unused, or use it as an input during operation. Due to the low-power nature of the pin with a slew rate limited signal source. If RC2 must be oscillator, it may also be sensitive to rapidly changing used as a digital output, it may be necessary to use the signals in close proximity. This is especially true when the oscillator is configured for extremely low power higher drive level oscillator mode (LPT1OSC = 1) with many PCB layouts. Even in the higher drive level mode, mode (LPT1OSC = 0). careful layout procedures should still be followed when The oscillator circuit, displayed in Figure13-2, should designing the oscillator circuit. be located as close as possible to the microcontroller. In addition to dV/dt induced noise considerations, it is There should be no circuits passing within the oscillator also important to ensure that the circuit board is clean. circuit boundaries other than VSS or VDD. Even a very small amount of conductive soldering flux If a high-speed circuit must be located near the residue can cause PCB leakage currents, which can oscillator (such as the ECCP1 pin in Output Compare overwhelm the oscillator circuit. or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as displayed in Figure13-3, may be helpful 13.6 Timer1 Interrupt when used on a single-sided PCB or in addition to a The TMR1 register pair (TMR1H:TMR1L) increments ground plane. from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>).  2011 Microchip Technology Inc. DS39932D-page 207

PIC18F46J11 FAMILY 13.7 Resetting Timer1 Using the ECCP 13.8.1 TIMER1 GATE COUNT ENABLE Special Event Trigger The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity If ECCP1 or ECCP2 is configured to use Timer1 and to of the Timer1 Gate Enable mode is configured using generate a Special Event Trigger in Compare mode the T1GPOL bit of the T1GCON register. (CCPxM<3:0>=1011), this signal will reset Timer3. The trigger from ECCP2 will also start an A/D conver- When Timer1 Gate Enable mode is enabled, Timer1 sion if the A/D module is enabled (see Section18.3.4 will increment on the rising edge of the Timer1 clock “Special Event Trigger” for more information). source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the The module must be configured as either a timer or a current count. See Figure13-4 for timing details. synchronous counter to take advantage of this feature. When used this way, the CCPRxH:CCPRxL register TABLE 13-3: TIMER1 GATE ENABLE pair effectively becomes a Period register for Timer1. SELECTIONS If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. T1CLK T1GPOL T1G Timer1 Operation In the event that a write to Timer1 coincides with a  0 0 Counts Special Event Trigger, the write operation will take  0 1 Holds Count precedence.  1 0 Holds Count  1 1 Counts Note: The Special Event Trigger from the ECCPx module will not set the TMR1IF interrupt flag bit (PIR1<0>). 13.8 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using the Timer1 gate circuitry. This is also referred to as Timer1 gate count enable. The Timer1 gate can also be driven by multiple selectable sources. DS39932D-page 208  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 13-4: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 13.8.2 TIMER1 GATE SOURCE 13.8.2.1 T1G Pin Gate Operation SELECTION The T1G pin is one source for Timer1 gate control. It The Timer1 gate source can be selected from one of can be used to supply an external source to the Timer1 four different sources. Source selection is controlled by gate circuitry. the T1GSSx bits of the T1GCON register. The polarity 13.8.2.2 Timer0 Overflow Gate Operation for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the When Timer0 increments from FFh to 00h, a T1GCON register. low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. TABLE 13-4: TIMER1 GATE SOURCES 13.8.2.3 Timer2 Match Gate Operation T1GSS<1:0> Timer1 Gate Source The TMR2 register will increment until it matches the 00 Timer1 Gate Pin value in the PR2 register. On the very next increment 01 Overflow of Timer0 cycle, TMR2 will be reset to 00h. When this Reset (TMR0 increments from FFh to 00h) occurs, a low-to-high pulse will automatically be 10 TMR2 to Match PR2 generated and internally supplied to the Timer1 gate (TMR2 increments to match PR2) circuitry. The pulse remains high for one instruction cycle and returns to low until the next match. When T1GPOL = 1, Timer1 increments for a single instruction cycle following TMR2 matching PR2. With T1GPOL = 0, Timer1 increments except during the cycle following the match.  2011 Microchip Technology Inc. DS39932D-page 209

PIC18F46J11 FAMILY 13.8.3 TIMER1 GATE TOGGLE MODE The T1GVAL bit will indicate when the Toggled mode is active and the timer is counting. When Timer1 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer1 The Timer1 Gate Toggle mode is enabled by setting the gate signal, as opposed to the duration of a single level T1GTM bit of the T1GCON register. When the T1GTM pulse. bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is The Timer1 gate source is routed through a flip-flop that measured. changes state on every incrementing edge of the signal. See Figure13-5 for timing details. FIGURE 13-5: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 DS39932D-page 210  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 13.8.4 TIMER1 GATE SINGLE PULSE Clearing the T1GSPM bit of the T1GCON register will MODE also clear the T1GGO/T1DONE bit. See Figure13-6 for timing details. When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Enabling the Toggle mode and the Single Pulse mode, Gate Single Pulse mode is first enabled by setting the simultaneously, will permit both sections to work together. T1GSPM bit in the T1GCON register. Next, the This allows the cycle times on the Timer1 gate source to T1GGO/T1DONE bit in the T1GCON register must be be measured. See Figure13-7 for timing details. set. The Timer1 will be fully enabled on the next incre- 13.8.5 TIMER1 GATE VALUE STATUS menting edge. On the next trailing edge of the pulse, the T1GGO/T1DONE bit will automatically be cleared. When the Timer1 gate value status is utilized, it is No other gate events will be allowed to increment possible to read the most current level of the gate Timer1 until the T1GGO/T1DONE bit is once again set control value. The value is stored in the T1GVAL bit in in software. the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). FIGURE 13-6: TIMER1 GATE SINGLE PULSE MODE TMR1GE T1GPOL T1GSPM Cleared by Hardware on T1GGO/ Set by Software Falling Edge of T1GVAL T1DONE Counting Enabled on Rising Edge of T1G T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 Cleared by RTCCIF Cleared by Software Set by Hardware on Software Falling Edge of T1GVAL  2011 Microchip Technology Inc. DS39932D-page 211

PIC18F46J11 FAMILY FIGURE 13-7: TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM Cleared by Hardware on T1GGO/ Set by Software Falling Edge of T1GVAL T1DONE Counting Enabled on Rising Edge of T1G T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 Set by Hardware on Cleared by RTCCIF Cleared by Software Falling Edge of T1GVAL Software TABLE 13-5: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 90 PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 92 PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 92 IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 92 TMR1L Timer1 Register Low Byte 91 TMR1H Timer1 Register High Byte 91 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON 91 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 92 T1DONE TCLKCON — — — T1RUN — — T3CCP2 T3CCP1 94 Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are only available in 44-pin devices. DS39932D-page 212  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 14.0 TIMER2 MODULE 14.1 Timer2 Operation The Timer2 module incorporates the following features: In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 4-bit counter/prescaler on the • 8-bit Timer and Period registers (TMR2 and PR2, clock input gives direct input, divide-by-4 and respectively) divide-by-16 prescale options. These are selected by • Readable and writable (both registers) the prescaler control bits, T2CKPS<1:0> • Software programmable prescaler (T2CON<1:0>). The value of TMR2 is compared to that (1:1, 1:4 and 1:16) of the Period register, PR2, on each clock cycle. When • Software programmable postscaler the two values match, the comparator generates a (1:1 through 1:16) match signal as the timer output. This signal also resets • Interrupt on TMR2 to PR2 match the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section14.2 • Optional use as the shift clock for the “Timer2 Interrupt”). MSSP modules The TMR2 and PR2 registers are both directly readable The module is controlled through the T2CON register and writable. The TMR2 register is cleared on any (Register14-1) which enables or disables the timer and device Reset, while the PR2 register initializes at FFh. configures the prescaler and postscaler. Timer2 can be Both the prescaler and postscaler counters are cleared shut off by clearing control bit, TMR2ON (T2CON<2>), on the following events: to minimize power consumption. • a write to the TMR2 register A simplified block diagram of the module is shown in Figure14-1. • a write to the T2CON register • any device Reset (Power-on Reset (POR), MCLR Reset, Watchdog Timer Reset (WDTR) or Brown-out Reset (BOR)) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER (ACCESS FCAh) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16  2011 Microchip Technology Inc. DS39932D-page 213

PIC18F46J11 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 Output Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2 to PR2 match) pro- the ECCP modules, where it is used as a time base for vides the input for the 4-bit output counter/postscaler. operations in PWM mode. This counter generates the TMR2 Match Interrupt Flag, Timer2 can be optionally used as the shift clock source which is latched in TMR2IF (PIR1<1>). The interrupt is for the MSSP modules operating in SPI mode. enabled by setting the TMR2 Match Interrupt Enable Additional information is provided in Section19.0 bit, TMR2IE (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”. A range of 16 postscaler options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set TMR2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSPx) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 90 PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 92 PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 92 IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 92 TMR2 Timer2 Register 91 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 91 PR2 Timer2 Period Register 91 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: These bits are only available in 44-pin devices. DS39932D-page 214  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 15.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure15-1. The Timer3 timer/counter module incorporates these The Timer3 module is controlled through the T3CON features: register (Register15-1). It also selects the clock source • Software selectable operation as a 16-bit timer or options for the ECCP modules; see Section18.1.1 counter “ECCP Module and Timer Resources” for more • Readable and writable 8-bit registers (TMR3H information. and TMR3L) The FOSC clock source (TMR3CS<1:0> = 01) should • Selectable clock source (internal or external) with not be used with the ECCP capture/compare features. device clock or Timer1 oscillator internal options If the timer will be used with the capture or compare • Interrupt-on-overflow features, always select one of the other timer clocking • Module Reset on ECCP Special Event Trigger options. REGISTER 15-1: T3CON: TIMER3 CONTROL REGISTER (ACCESS F79h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 — T3SYNC RD16 TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TMR3CS<1:0>: Timer3 Clock Source Select bits(2) 10 = Timer3 clock source is the T3CKI input pin (assigned in the PPS module) 01 = Timer3 clock source is the system clock (FOSC)(1) 00 = Timer3 clock source is the instruction clock (FOSC/4) bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 Reserved: Program as ‘0’ bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit When TMR3CS<1:0> = 10: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS<1:0> = 0x: This bit is ignored; Timer3 uses the internal clock. bit 1 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features. 2: When switching clock sources and using the clock prescaler, write to TMR3L afterwards to reset the inter- nal prescaler count to 0.  2011 Microchip Technology Inc. DS39932D-page 215

PIC18F46J11 FAMILY 15.1 Timer3 Gate Control Register The Timer3 Gate Control register (T3GCON), provided in Register 14-2, is used to control the Timer3 gate. REGISTER 15-2: T3GCON: TIMER3 GATE CONTROL REGISTER (ACCESS F97h)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0 TMR3GE T3GPOL T3GTM T3GSPM T3GGO/T3DONE T3GVAL T3GSS1 T3GSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR3GE: Timer3 Gate Enable bit If TMR3ON = 0: This bit is ignored. If TMR3ON = 1: 1 = Timer3 counting is controlled by the Timer3 gate function 0 = Timer3 counts regardless of Timer3 gate function bit 6 T3GPOL: Timer3 Gate Polarity bit 1 = Timer3 gate is active-high (Timer3 counts when gate is high) 0 = Timer3 gate is active-low (Timer3 counts when gate is low) bit 5 T3GTM: Timer3 Gate Toggle Mode bit 1 = Timer3 Gate Toggle mode is enabled 0 = Timer3 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer3 gate flip-flop toggles on every rising edge. bit 4 T3GSPM: Timer3 Gate Single Pulse Mode bit 1 = Timer3 Gate Single Pulse mode is enabled and is controlling Timer3 gate 0 = Timer3 Gate Single Pulse mode is disabled bit 3 T3GGO/T3DONE: Timer3 Gate Single Pulse Acquisition Status bit 1 = Timer3 gate single pulse acquisition is ready, waiting for an edge 0 = Timer3 gate single pulse acquisition has completed or has not been started This bit is automatically cleared when T3GSPM is cleared. bit 2 T3GVAL: Timer3 Gate Current State bit Indicates the current state of the Timer3 gate that could be provided to TMR3H:TMR3L. Unaffected by Timer3 Gate Enable bit (TMR3GE). bit 1-0 T3GSS<1:0>: Timer3 Gate Source Select bits 10 = TMR2 to match PR2 output 01 = Timer0 overflow output 00 = Timer3 gate pin (T3G) Note 1: Programming the T3GCON prior to T3CON is recommended. DS39932D-page 216  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 15-3: TCLKCON: TIMER CLOCK CONTROL REGISTER (BANKED F52h) U-0 U-0 U-0 R-0 U-0 U-0 R/W-0 R/W-0 — — — T1RUN — — T3CCP2 T3CCP1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 T1RUN: Timer1 Run Status bit 1 = Device is currently clocked by T1OSC/T1CKI 0 = System clock comes from an oscillator other than T1OSC/T1CKI bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 T3CCP<2:1>: ECCP Timer Assignment bits 10 = ECCP1 and ECCP2 both use Timer3 (capture/compare) and Timer4 (PWM) 01 = ECCP1 uses Timer1 (compare/capture) and Timer2 (PWM); ECCP2 uses Timer3 (capture/compare) and Timer4 (PWM) 00 = ECCP1 and ECCP2 both use Timer1 (capture/compare) and Timer2 (PWM)  2011 Microchip Technology Inc. DS39932D-page 217

PIC18F46J11 FAMILY 15.2 Timer3 Operation The operating mode is determined by the clock select bits, TMR3CSx (T3CON<7:6>). When the TMR3CSx bits Timer3 can operate in one of three modes: are cleared (= 00), Timer3 increments on every internal • Timer instruction cycle (FOSC/4). When TMR3CSx = 01, the • Synchronous Counter Timer3 clock source is the system clock (FOSC), and when it is ‘10’, Timer3 works as a counter from the • Asynchronous Counter external clock from the T3CKI pin (on the rising edge • Timer with Gated Control after the first falling edge) or the Timer1 oscillator. FIGURE 15-1: TIMER3 BLOCK DIAGRAM T3GSS<1:0> T3G 00 T3GSPM From Timer0 01 T3G_IN 0 Overflow 0 T3GVAL D Q Data Bus FMraotmch T PimRe2r2 10 SAicnqg.l eC Ponutlrsoel 1 Q1 EN RT3DGCON D Q 1 CK Q T3GGO/T3DONE Interrupt Set TMR3ON R det TMR3GIF T3GPOL T3GTM TMR3GE Set Flag bit, TMR3ON TMR3IF, on Overflow TMR3(2) EN Synchronized TMR3H TMR3L T3CLK 0 Clock Input Q D 1 TMR3CS<1:0> T3SYNC T3CKI Prescaler Synchronize(3) 1, 2, 4, 8 10 det 2 FOSC T3CKPS<1:0> Internal 01 Clock FOSC/2 Sleep Input FOSC/4 Internal Internal 00 Clock Clock Note 1: ST Buffer is high-speed type when using T3CKI. 2: Timer3 register increments on rising edge. 3: Synchronize does not operate while in Sleep. DS39932D-page 218  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 15.3 Timer3 16-Bit Read/Write Mode The Timer1 oscillator is described in Section13.0 “Timer1 Module”. Timer3 can be configured for 16-bit reads and writes (see Section15.3 “Timer3 16-Bit Read/Write 15.5 Timer3 Gate Mode”). When the RD16 control bit (T3CON<1>) is set, the address for TMR3H is mapped to a buffer reg- Timer3 can be configured to count freely, or the count ister for the high byte of Timer3. A read from TMR3L can be enabled and disabled using Timer3 gate will load the contents of the high byte of Timer3 into the circuitry. This is also referred to as Timer3 gate count Timer3 High Byte Buffer register. This provides the user enable. with the ability to accurately read all 16 bits of Timer3 Timer3 gate can also be driven by multiple selectable without having to determine whether a read of the high sources. byte, followed by a read of the low byte, has become invalid due to a rollover between reads. 15.5.1 TIMER3 GATE COUNT ENABLE A write to the high byte of Timer3 must also take place The Timer3 Gate Enable mode is enabled by setting through the TMR3H Buffer register. The Timer3 high the TMR3GE bit of the T3GCON register. The polarity byte is updated with the contents of TMR3H when a of the Timer3 Gate Enable mode is configured using write occurs to TMR3L. This allows a user to write all the T3GPOL bit of the T3GCON register. 16 bits to both the high and low bytes of Timer3 at once. When Timer3 Gate Enable mode is enabled, Timer3 The high byte of Timer3 is not directly readable or will increment on the rising edge of the Timer3 clock writable in this mode. All reads and writes must take source. When Timer3 Gate Enable mode is disabled, place through the Timer3 High Byte Buffer register. no incrementing will occur and Timer3 will hold the Writes to TMR3H do not clear the Timer3 prescaler. current count. See Figure15-2 for timing details. The prescaler is only cleared on writes to TMR3L. TABLE 15-1: TIMER3 GATE ENABLE 15.4 Using the Timer1 Oscillator as the SELECTIONS Timer3 Clock Source T3CLK T3GPOL T3G Timer3 Operation The Timer1 internal oscillator may be used as the clock  0 0 Counts source for Timer3. The Timer1 oscillator is enabled by  0 1 Holds Count setting the T1OSCEN (T1CON<3>) bit. To use it as the Timer3 clock source, the TMR3CS bit must also be set.  1 0 Holds Count As previously noted, this also configures Timer3 to  1 1 Counts increment on every rising edge of the oscillator source. FIGURE 15-2: TIMER3 GATE COUNT ENABLE MODE TMR3GE T3GPOL T3G_IN T1CKI T3GVAL Timer3 N N + 1 N + 2 N + 3 N + 4  2011 Microchip Technology Inc. DS39932D-page 219

PIC18F46J11 FAMILY 15.5.2 TIMER3 GATE SOURCE 15.5.2.3 Timer2 Match Gate Operation SELECTION The TMR2 register will increment until it matches the The Timer3 gate source can be selected from one of value in the PR2 register. On the very next increment four different sources. Source selection is controlled by cycle, TMR2 will be reset to 00h. When this Reset the T3GSSx bits of the T3GCON register. The polarity occurs, a low-to-high pulse will automatically be for each available source is also selectable. Polarity generated and internally supplied to the Timer3 gate selection is controlled by the T3GPOL bit of the circuitry. T3GCON register. 15.5.3 TIMER3 GATE TOGGLE MODE TABLE 15-2: TIMER3 GATE SOURCES When Timer3 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer3 T3GSS<1:0> Timer3 Gate Source gate signal, as opposed to the duration of a single level 00 Timer3 Gate Pin pulse. 01 Overflow of Timer0 The Timer1 gate source is routed through a flip-flop that (TMR0 increments from FFh to 00h) changes state on every incrementing edge of the 10 TMR2 to Match PR2 signal. See Figure15-3 for timing details. (TMR2 increments to match PR2) The T3GVAL bit will indicate when the Toggled mode is 11 Reserved active and the timer is counting. Timer3 Gate Toggle mode is enabled by setting the 15.5.2.1 T3G Pin Gate Operation T3GTM bit of the T3GCON register. When the T3GTM The T3G pin is one source for Timer3 gate control. It bit is cleared, the flip-flop is cleared and held clear. This can be used to supply an external source to the Timer3 is necessary in order to control which edge is gate circuitry. measured. 15.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer3 gate circuitry. FIGURE 15-3: TIMER3 GATE TOGGLE MODE TMR3GE T3GPOL T3GTM T3G_IN T1CKI T3GVAL Timer3 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 DS39932D-page 220  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 15.5.4 TIMER3 GATE SINGLE PULSE other gate events will be allowed to increment Timer3 MODE until the T3GGO/T3DONE bit is once again set in software. When Timer3 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer3 Clearing the T3GSPM bit of the T3GCON register will Gate Single Pulse mode is first enabled by setting the also clear the T3GGO/T3DONE bit. See Figure15-4 T3GSPM bit in the T3GCON register. Next, the for timing details. T3GGO/T3DONE bit in the T3GCON register must be Enabling the Toggle mode and the Single Pulse mode, set. simultaneously, will permit both sections to work The Timer3 will be fully enabled on the next increment- together. This allows the cycle times on the Timer3 gate ing edge. On the next trailing edge of the pulse, the source to be measured. See Figure15-5 for timing T3GGO/T3DONE bit will automatically be cleared. No details. FIGURE 15-4: TIMER3 GATE SINGLE PULSE MODE TMR3GE T3GPOL T3GSPM Cleared by Hardware on T3GGO/ Set by Software Falling Edge of T3GVAL T3DONE Counting Enabled on Rising Edge of T3G T3G_IN T1CKI T3GVAL Timer3 N N + 1 N + 2 Cleared by TMR3GIF Cleared by Software Set by Hardware on Software Falling Edge of T3GVAL  2011 Microchip Technology Inc. DS39932D-page 221

PIC18F46J11 FAMILY FIGURE 15-5: TIMER3 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMR3GE T3GPOL T3GSPM T3GTM Cleared by Hardware on T3GGO/ Set by Software Falling Edge of T3GVAL T3DONE Counting Enabled on Rising Edge of T3G T3G_IN T1CKI T3GVAL Timer3 N N + 1 N + 2 N + 3 N + 4 Set by Hardware on Cleared by TMR3GIF Cleared by Software Falling Edge of T3GVAL Software 15.5.5 TIMER3 GATE VALUE STATUS 15.5.6 TIMER3 GATE EVENT INTERRUPT When Timer3 gate value status is utilized, it is possible When the Timer3 gate event interrupt is enabled, it is to read the most current level of the gate control value. possible to generate an interrupt upon the completion The value is stored in the T3GVAL bit in the T3GCON of a gate event. When the falling edge of T3GVAL register. The T3GVAL bit is valid even when the Timer3 occurs, the TMR3GIF flag bit in the PIR3 register will be gate is not enabled (TMR3GE bit is cleared). set. If the TMR3GIE bit in the PIE3 register is set, then an interrupt will be recognized. The TMR3GIF flag bit operates even when the Timer3 gate is not enabled (TMR3GE bit is cleared). DS39932D-page 222  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 15.6 Timer3 Interrupt The trigger from ECCP2 will also start an A/D conver- sion if the A/D module is enabled (see Section18.3.4 The TMR3 register pair (TMR3H:TMR3L) increments “Special Event Trigger” for more information). from 0000h to FFFFh and overflows to 0000h. The The module must be configured as either a timer or Timer3 interrupt, if enabled, is generated on overflow synchronous counter to take advantage of this feature. and is latched in interrupt flag bit, TMR3IF (PIR2<1>). When used this way, the CCPRxH:CCPRxL register This interrupt can be enabled or disabled by setting or pair effectively becomes a Period register for Timer3. clearing the Timer3 Interrupt Enable bit, TMR3IE (PIE2<1>). If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. 15.7 Resetting Timer3 Using the ECCP In the event that a write to Timer3 coincides with a Special Event Trigger Special Event Trigger from an ECCP module, the write will take precedence. If ECCP1 or ECCP2 is configured to use Timer3 and to generate a Special Event Trigger in Compare mode Note: The Special Event Triggers from the (CCPxM<3:0>=1011), this signal will reset Timer3. ECCPx module will not set the TMR3IF interrupt flag bit (PIR1<0>). TABLE 15-3: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 90 PIR2 OSCFIF CM2IF CM1IF — BCL1IF LVDIF TMR3IF CCP2IF 92 PIE2 OSCFIE CM2IE CM1IE — BCL1IE LVDIE TMR3IE CCP2IE 92 IPR2 OSCFIP CM2IP CM1IP — BCL1IP LVDIP TMR3IP CCP2IP 92 TMR3L Timer3 Register Low Byte 93 TMR3H Timer3 Register High Byte 93 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON 91 T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 — T3SYNC RD16 TMR3ON 93 T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS1 T3GSS0 92 T3DONE TCLKCON — — — T1RUN — — T3CCP2 T3CCP1 94 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 92 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 92 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 92 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.  2011 Microchip Technology Inc. DS39932D-page 223

PIC18F46J11 FAMILY NOTES: DS39932D-page 224  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 16.0 TIMER4 MODULE 16.1 Timer4 Operation The Timer4 timer module has the following features: Timer4 can be used as the PWM time base for the PWM mode of the ECCP modules. The TMR4 register • 8-Bit Timer register (TMR4) is readable and writable and is cleared on any device • 8-Bit Period register (PR4) Reset. The input clock (FOSC/4) has a prescale option • Readable and writable (both registers) of 1:1, 1:4 or 1:16, selected by control bits, • Software programmable prescaler (1:1, 1:4, 1:16) T4CKPS<1:0> (T4CON<1:0>). The match output of • Software programmable postscaler (1:1 to 1:16) TMR4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR4 • Interrupt on TMR4 match of PR4 interrupt, latched in flag bit, TMR4IF (PIR3<3>). Timer4 has a control register shown in Register16-1. The prescaler and postscaler counters are cleared Timer4 can be shut off by clearing control bit, TMR4ON when any of the following occurs: (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 is also • a write to the TMR4 register controlled by this register. Figure16-1 is a simplified • a write to the T4CON register block diagram of the Timer4 module. • any device Reset (Power-on Reset (POR), MCLR Reset, Watchdog Timer Reset (WDTR) or Brown-out Reset (BOR)) TMR4 is not cleared when T4CON is written. REGISTER 16-1: T4CON: TIMER4 CONTROL REGISTER (ACCESS F76h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T4OUTPS<3:0>: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off bit 1-0 T4CKPS<1:0>: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16  2011 Microchip Technology Inc. DS39932D-page 225

PIC18F46J11 FAMILY 16.2 Timer4 Interrupt 16.3 Output of TMR4 The Timer4 module has an 8-bit Period register, PR4, The output of TMR4 (before the postscaler) is used which is both readable and writable. Timer4 increments only as a PWM time base for the ECCP modules. It is from 00h until it matches PR4 and then resets to 00h on not used as a baud rate clock for the MSSP modules as the next increment cycle. The PR4 register is initialized is the Timer2 output. to FFh upon Reset. FIGURE 16-1: TIMER4 BLOCK DIAGRAM 4 1:1 to 1:16 T4OUTPS<3:0> Set TMR4IF Postscaler 2 T4CKPS<1:0> TMR4 Output (to PWM) TMR4/PR4 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR4 Comparator PR4 Prescaler 8 8 8 Internal Data Bus TABLE 16-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 90 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCIP 92 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCIF 92 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCIE 92 TMR4 Timer4 Register 93 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 93 PR4 Timer4 Period Register 93 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module. DS39932D-page 226  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 17.0 REAL-TIME CLOCK AND The RTCC module is intended for applications where CALENDAR (RTCC) accurate time must be maintained for an extended period with minimum to no intervention from the CPU. The key features of the Real-Time Clock and Calendar The module is optimized for low-power usage in order (RTCC) module are: to provide extended battery life while keeping track of time. • Time: hours, minutes and seconds • 24-hour format (military time) The module is a 100-year clock and calendar with auto- matic leap year detection. The range of the clock is • Calendar: weekday, date, month and year from 00:00:00 (midnight) on January 1, 2000 to • Alarm configurable 23:59:59 on December 31, 2099. Hours are measured • Year range: 2000 to 2099 in 24-hour (military time) format. The clock provides a • Leap year correction granularity of one second with half-second visibility to • BCD format for compact firmware the user. • Optimized for low-power operation • User calibration with auto-adjust • Calibration range: 2.64 seconds error per month • Requirements: external 32.768 kHz clock crystal • Alarm pulse or seconds clock output on RTCC pin FIGURE 17-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain 32.768 kHz Input RTCCFG from Timer1 Oscillator RTCC Prescalers or Internal RC ALRMRPT YEAR 0.5s MTHDY RTCC Timer RTCVALx WKDYHR Alarm Event MINSEC Comparator ALMTHDY Compare Registers ALRMVALx ALWDHR with Masks ALMINSEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE  2011 Microchip Technology Inc. DS39932D-page 227

PIC18F46J11 FAMILY 17.1 RTCC MODULE REGISTERS Alarm Value Registers The RTCC module registers are divided into following • ALRMVALH and ALRMVALL – Can access the categories: following registers: - ALRMMNTH RTCC Control Registers - ALRMDAY - ALRMWD • RTCCFG - ALRMHR • RTCCAL - ALRMMIN • PADCFG1 - ALRMSEC • ALRMCFG • ALRMRPT Note: The RTCVALH and RTCVALL registers can be accessed through RTCRPT<1:0>. RTCC Value Registers ALRMVALH and ALRMVALL can be accessed through ALRMPTR<1:0>. • RTCVALH and RTCVALL – Can access the following registers - YEAR - MONTH - DAY - WEEKDAY - HOUR - MINUTE - SECOND DS39932D-page 228  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 17.1.1 RTCC CONTROL REGISTERS REGISTER 17-1: RTCCFG: RTCC CONFIGURATION REGISTER (BANKED F3Fh)(1) R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR1 RTCPTR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 4 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALRMRPT registers can change while reading due to a rollover ripple resulting in an invalid data read If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 3 HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 2 RTCOE: RTCC Output Enable bit 1 = RTCC clock output enabled 0 = RTCC clock output disabled bit 1-0 RTCPTR<1:0>: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH<7:0> and RTCVALL<7:0> registers; the RTCPTR<1:0> value decrements on every read or write of RTCVALH<7:0> until it reaches ‘00’. RTCVALH<7:0>: 00 = Minutes 01 = Weekday 10 = Month 11 = Reserved RTCVALL<7:0>: 00 = Seconds 01 = Hours 10 = Day 11 = Year Note 1: The RTCCFG register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.  2011 Microchip Technology Inc. DS39932D-page 229

PIC18F46J11 FAMILY REGISTER 17-2: RTCCAL: RTCC CALIBRATION REGISTER (BANKED F3Eh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 =Maximum positive adjustment; adds 508 RTC clock pulses every minute . . . 00000001 =Minimum positive adjustment; adds four RTC clock pulses every minute 00000000 =No adjustment 11111111 =Minimum negative adjustment; subtracts four RTC clock pulses every minute . . . 10000000 =Maximum negative adjustment; subtracts 512 RTC clock pulses every minute REGISTER 17-3: PADCFG1: PAD CONFIGURATION REGISTER (BANKED F3Ch) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — RTSECSEL1(1) RTSECSEL0(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1) 11 =Reserved, do not use 10 =RTCC source clock is selected for the RTCC pin (pin can be INTRC or T1OSC, depending on the RTCOSC (CONFIG3L<1>) setting) 01 =RTCC seconds clock is selected for the RTCC pin 00 =RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt input buffers Note 1: To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set. DS39932D-page 230  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 17-4: ALRMCFG: ALARM CONFIGURATION REGISTER (ACCESS F91h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0>=0000 0000 and CHIME=0) 0 = Alarm is disabled bit 6 CHIME: Chime Enable bit 1 = Chime is enabled; ALRMRPT<7:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ALRMRPT<7:0> bits stop once they reach 00h bit 5-2 AMASK<3:0>: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every four years) 101x = Reserved – do not use 11xx = Reserved – do not use bit 1-0 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVALH<15:8>: 00 =ALRMMIN 01 =ALRMWD 10 =ALRMMNTH 11 =Unimplemented ALRMVALL<7:0>: 00 =ALRMSEC 01 =ALRMHR 10 =ALRMDAY 11 =Unimplemented  2011 Microchip Technology Inc. DS39932D-page 231

PIC18F46J11 FAMILY REGISTER 17-5: ALRMRPT: ALARM REPEAT COUNTER (ACCESS F90h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times . . . 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME=1. DS39932D-page 232  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 17.1.2 RTCVALH AND RTCVALL REGISTER MAPPINGS REGISTER 17-6: RESERVED REGISTER (ACCESS F99h, PTR 11b) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 Unimplemented: Read as ‘0’ REGISTER 17-7: YEAR: YEAR VALUE REGISTER (ACCESS F98h, PTR 11b)(1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to the YEAR register is only allowed when RTCWREN=1. REGISTER 17-8: MONTH: MONTH VALUE REGISTER (ACCESS F99h, PTR 10b)(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 3-0 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1.  2011 Microchip Technology Inc. DS39932D-page 233

PIC18F46J11 FAMILY REGISTER 17-9: DAY: DAY VALUE REGISTER (ACCESS F98h, PTR 10b)(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 17-10: WKDY: WEEKDAY VALUE REGISTER (ACCESS F99h, PTR 01b)(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. Note 1: A write to this register is only allowed when RTCWREN=1. DS39932D-page 234  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 17-11: HOURS: HOURS VALUE REGISTER (ACCESS F98h, PTR 01b)(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 17-12: MINUTES: MINUTES VALUE REGISTER (ACCESS F99h, PTR 00b) U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. REGISTER 17-13: SECONDS: SECONDS VALUE REGISTER (ACCESS F98h, PTR 00b) U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2011 Microchip Technology Inc. DS39932D-page 235

PIC18F46J11 FAMILY 17.1.3 ALRMVALH AND ALRMVALL REGISTER MAPPINGS REGISTER 17-14: ALRMMNTH: ALARM MONTH VALUE REGISTER (ACCESS F8Fh, PTR 10b)(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 3-0 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 17-15: ALRMDAY: ALARM DAY VALUE REGISTER (ACCESS F8Eh, PTR 10b)(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. DS39932D-page 236  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 17-16: ALRMWD: ALARM WEEKDAY VALUE REGISTER (ACCESS F8Fh, PTR 01b)(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 17-17: ALRMHR: ALARM HOURS VALUE REGISTER (ACCESS F8Eh, PTR 01b)(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE3:HRONE0: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1.  2011 Microchip Technology Inc. DS39932D-page 237

PIC18F46J11 FAMILY REGISTER 17-18: ALRMMIN: ALARM MINUTES VALUE REGISTER (ACCESS F8Fh, PTR 00b) U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. REGISTER 17-19: ALRMSEC: ALARM SECONDS VALUE REGISTER (ACCESS F8Eh, PTR 00b) U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9. DS39932D-page 238  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 17.1.4 RTCEN BIT WRITE 17.2 Operation An attempt to write to the RTCEN bit while 17.2.1 REGISTER INTERFACE RTCWREN=0 will be ignored. RTCWREN must be set before a write to RTCEN can take place. The register interface for the RTCC and alarm values is implemented using the Binary Coded Decimal (BCD) Like the RTCEN bit, the RTCVALH<15:8> and format. This simplifies the firmware, when using the RTCVALL<7:0> registers can only be written to when module, as each of the digits is contained within its own RTCWREN=1. A write to these registers, while 4-bit value (see Figure17-2 and Figure17-3). RTCWREN=0, will be ignored. FIGURE 17-2: TIMER DIGIT FORMAT Year Month Day Day Of Week 0-9 0-9 0-1 0-9 0-3 0-9 0-6 Hours 1/2 Second Bit (24-hour format) Minutes Seconds (binary format) 0-2 0-9 0-5 0-9 0-5 0-9 0/1 FIGURE 17-3: ALARM DIGIT FORMAT Month Day Day Of Week 0-1 0-9 0-3 0-9 0-6 Hours (24-hour format) Minutes Seconds 0-2 0-9 0-5 0-9 0-5 0-9  2011 Microchip Technology Inc. DS39932D-page 239

PIC18F46J11 FAMILY 17.2.2 CLOCK SOURCE Calibration of the crystal can be done through this module to yield an error of 3seconds or less per month. As mentioned earlier, the RTCC module is intended to (For further details, see Section 17.2.9 “Calibration”.) be clocked by an external Real-Time Clock crystal oscillating at 32.768kHz, but also can be clocked by the INTRC oscillator. The RTCC clock selection is decided by the RTCOSC bit (CONFIG3L<1>). FIGURE 17-4: CLOCK SOURCE MULTIPLEXING 32.768 kHz XTAL Half-Second from T1OSC 1:16384 Clock One-Second Clock Half Second(1) Clock Prescaler(1) Internal RC CONFIG 3L<1> Day Second Hour:Minute Month Year Day of Week Note 1: Writing to the lower half of the MINSEC register resets all counters, allowing fraction of a second synchronization; the clock prescaler is held in Reset when RTCEN =0. 17.2.2.1 Real-Time Clock Enable For the day to month rollover schedule, see Table17-2. The RTCC module can be clocked by an external, Considering that the following values are in BCD 32.768 kHz crystal (Timer1 oscillator) or the INTRC format, the carry to the upper BCD digit will occur at a oscillator, which can be selected in CONFIG3L<1>. count of 10 and not at 16 (SECONDS, MINUTES, HOURS, WEEKDAY, DAYS and MONTHS). If the Timer1 oscillator will be used as the clock source for the RTCC, make sure to enable it by setting TABLE 17-1: DAY OF WEEK SCHEDULE T1CON<3> (T1OSCEN). The selected clock can be brought out to the RTCC pin by the RTSECSEL<1:0> Day of Week bits in the PADCFG1 register. Sunday 0 17.2.3 DIGIT CARRY RULES Monday 1 This section explains which timer values are affected Tuesday 2 when there is a rollover. Wednesday 3 • Time of Day: From 23:59:59 to 00:00:00 with a Thursday 4 carry to the Day field Friday 5 • Month: From 12/31 to 01/01 with a carry to the Saturday 6 Year field • Day of Week: From 6 to 0 with no carry (see Table17-1) • Year Carry: From 99 to 00; this also surpasses the use of the RTCC DS39932D-page 240  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 17-2: DAY TO MONTH ROLLOVER 17.2.6 SAFETY WINDOW FOR REGISTER SCHEDULE READS AND WRITES Month Maximum Day Field The RTCSYNC bit indicates a time window during which the RTCC Clock Domain registers can be safely 01 (January) 31 read and written without concern about a rollover. 02 (February) 28 or 29(1) When RTCSYNC = 0, the registers can be safely 03 (March) 31 accessed by the CPU. 04 (April) 30 Whether RTCSYNC = 1 or 0, the user should employ a firmware solution to ensure that the data read did not 05 (May) 31 fall on a rollover boundary, resulting in an invalid or 06 (June) 30 partial read. This firmware solution would consist of 07 (July) 31 reading each register twice and then comparing the two 08 (August) 31 values. If the two values matched, then, a rollover did not occur. 09 (September) 30 10 (October) 31 17.2.7 WRITE LOCK 11 (November) 30 In order to perform a write to any of the RTCC Timer 12 (December) 31 registers, the RTCWREN bit (RTCCFG<5>) must be set. Note 1: See Section 17.2.4 “Leap Year”. To avoid accidental writes to the RTCC Timer register, 17.2.4 LEAP YEAR it is recommended that the RTCWREN bit Since the year range on the RTCC module is 2000 to (RTCCFG<5>) be kept clear at any time other than 2099, the leap year calculation is determined by any while writing to. For the RTCWREN bit to be set, there year divisible by ‘4’ in the above range. Only February is only one instruction cycle time window allowed is effected in a leap year. between the 55h/AA sequence and the setting of RTCWREN. For that reason, it is recommended that February will have 29 days in a leap year and 28 days in users follow the code example in Example17-1. any other year. EXAMPLE 17-1: SETTING THE RTCWREN 17.2.5 GENERAL FUNCTIONALITY BIT All Timer registers containing a time value of seconds or greater are writable. The user configures the time by movlb 0x0f writing the required year, month, day, hour, minutes and movlw 0x55 seconds to the Timer registers, via Register Pointers movwf EECON2,0 (see Section 17.2.8 “Register Mapping”). movlw 0xAA The timer uses the newly written values and proceeds movwf EECON2,0 with the count from the required starting point. bsf RTCCFG,5,1 The RTCC is enabled by setting the RTCEN bit (RTCCFG<7>). If enabled, while adjusting these 17.2.8 REGISTER MAPPING registers, the timer still continues to increment. However, To limit the register interface, the RTCC Timer and any time the MINSEC register is written to, both of the Alarm Timer registers are accessed through timer prescalers are reset to ‘0’. This allows fraction of a corresponding register pointers. The RTCC Value reg- second synchronization. ister window (RTCVALH and RTCVALL) uses the The Timer registers are updated in the same cycle as RTCPTR bits (RTCCFG<1:0>) to select the required the write instruction’s execution by the CPU. The user Timer register pair. must ensure that when RTCEN = 1, the updated By reading or writing to the RTCVALH register, the registers will not be incremented at the same time. This RTCC Pointer value (RTCPTR<1:0>) decrements by 1 can be accomplished in several ways: until it reaches ‘00’. Once it reaches ‘00’, the MINUTES • By checking the RTCSYNC bit (RTCCFG<4>) and SECONDS value will be accessible through • By checking the preceding digits from which a RTCVALH and RTCVALL until the pointer value is carry can occur manually changed. • By updating the registers immediately following the seconds pulse (or alarm interrupt) The user has visibility to the half-second field of the counter. This value is read-only and can be reset only by writing to the lower half of the SECONDS register.  2011 Microchip Technology Inc. DS39932D-page 241

PIC18F46J11 FAMILY TABLE 17-3: RTCVALH AND RTCVALL To calibrate the RTCC module: REGISTER MAPPING 1. Use another timer resource on the device to find the error of the 32.768 kHz crystal. RTCC Value Register Window RTCPTR<1:0> 2. Convert the number of error clock pulses per RTCVALH<15:8> RTCVALL<7:0> minute (see Equation17-1). 00 MINUTES SECONDS EQUATION 17-1: CONVERTING ERROR 01 WEEKDAY HOURS CLOCK PULSES 10 MONTH DAY 11 — YEAR (Ideal Frequency (32,768) – Measured Frequency) * 60 = Error Clocks per Minute The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALRMCFG<1:0>) • If the oscillator is faster than ideal (negative to select the desired Alarm register pair. result from step 2), the RTCCALL register value By reading or writing to the ALRMVALH register, the needs to be negative. This causes the specified Alarm Pointer value, ALRMPTR<1:0>, decrements number of clock pulses to be subtracted from by1 until it reaches ‘00’. Once it reaches ‘00’, the the timer counter once every minute. ALRMMIN and ALRMSEC value will be accessible • If the oscillator is slower than ideal (positive through ALRMVALH and ALRMVALL until the pointer result from step 2), the RTCCALL register value value is manually changed. needs to be positive. This causes the specified number of clock pulses to be added to the timer TABLE 17-4: ALRMVAL REGISTER counter once every minute. MAPPING 3. Load the RTCCAL register with the correct Alarm Value Register Window value. ALRMPTR<1:0> ALRMVALH<15:8> ALRMVALL<7:0> Writes to the RTCCAL register should occur only when the timer is turned off, or immediately after the rising 00 ALRMMIN ALRMSEC edge of the seconds pulse. 01 ALRMWD ALRMHR Note: In determining the crystal’s error value, it 10 ALRMMNTH ALRMDAY is the user’s responsibility to include the 11 — — crystal’s initial error from drift due to temperature or crystal aging. 17.2.9 CALIBRATION The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than three seconds per month. To perform this calibration, find the number of error clock pulses and store the value in the lower half of the RTCCAL register. The 8-bit, signed value – loaded into RTCCAL – is multiplied by ‘4’ and will either be added or subtracted from the RTCC timer, once every minute. DS39932D-page 242  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 17.3 Alarm The alarm can also be configured to repeat based on a preconfigured interval. The number of times this occurs The alarm features and characteristics are: after the alarm is enabled is stored in the ALRMRPT • Configurable from half a second to one year register. • Enabled using the ALRMEN bit (ALRMCFG<7>, Note: While the alarm is enabled (ALRMEN = Register17-4) 1), changing any of the registers – other • Offers one-time and repeat alarm options than the RTCCAL, ALRMCFG and ALRM- RPT registers and the CHIME bit – can 17.3.1 CONFIGURING THE ALARM result in a false alarm event leading to a The alarm feature is enabled using the ALRMEN bit. false alarm interrupt. To avoid this, only change the timer and alarm values while This bit is cleared when an alarm is issued. The bit will the alarm is disabled (ALRMEN=0). It is not be cleared if the CHIME bit = 1 or if ALRMRPT  0. recommended that the ALRMCFG and The interval selection of the alarm is configured ALRMRPT registers and CHIME bit be through the ALRMCFG bits (AMASK<3:0>). (See changed when RTCSYNC = 0. Figure17-5.) These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. FIGURE 17-5: ALARM MASK SETTINGS Alarm Mask Setting Day of the AMASK<3:0> Week Month Day Hours Minutes Seconds 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds s 0011 – Every minute s s 0100 – Every 10 minutes m s s 0101 – Every hour m m s s 0110 – Every day h h m m s s 0111 – Every week d h h m m s s 1000 – Every month d d h h m m s s 1001 – Every year(1) m m d d h h m m s s Note 1: Annually, except when configured for February 29.  2011 Microchip Technology Inc. DS39932D-page 243

PIC18F46J11 FAMILY When ALRMCFG = 00 and the CHIME bit = 0 17.3.2 ALARM INTERRUPT (ALRMCFG<6>), the repeat function is disabled and At every alarm event, an interrupt is generated. Addi- only a single alarm will occur. The alarm can be tionally, an alarm pulse output is provided that operates repeated up to 255 times by loading the ALRMRPT at half the frequency of the alarm. register with FFh. The alarm pulse output is completely synchronous with After each alarm is issued, the ALRMRPT register is the RTCC clock and can be used as a trigger clock to decremented by one. Once the register has reached other peripherals. This output is available on the RTCC ‘00’, the alarm will be issued one last time. pin. The output pulse is a clock with a 50% duty cycle After the alarm is issued a last time, the ALRMEN bit is and a frequency half that of the alarm event (see cleared automatically and the alarm turned off. Indefinite Figure17-6). repetition of the alarm can occur if the CHIME bit = 1. The RTCC pin also can output the seconds clock. The When CHIME = 1, the alarm is not disabled when the user can select between the alarm pulse, generated by ALRMRPT register reaches ‘00’, but it rolls over to FF the RTCC module, or the seconds clock output. and continues counting indefinitely. The RTSECSEL (PADCFG1<1:0>) bits select between these two outputs: • Alarm pulse – RTSECSEL<1:0> = 00 • Seconds clock – RTSECSEL<1:0> = 0 FIGURE 17-6: TIMER PULSE GENERATION RTCEN bit ALRMEN bit RTCC Alarm Event RTCC Pin 17.4 Low-Power Modes 17.5.2 POWER-ON RESET (POR) The timer and alarm can optionally continue to operate The RTCCFG and ALRMRPT registers are reset only while in Sleep, Idle and even Deep Sleep mode. An on a POR. Once the device exits the POR state, the alarm event can be used to wake-up the microcontroller clock registers should be reloaded with the desired from any of these Low-Power modes. values. The timer prescaler values can be reset only by writing 17.5 Reset to the SECONDS register. No device Reset can affect the prescalers. 17.5.1 DEVICE RESET When a device Reset occurs, the ALRMCFG and ALRMRPT registers are forced to a Reset state causing the alarm to be disabled (if enabled prior to the Reset). If the RTCC was enabled, it will continue to operate when a basic device Reset occurs. DS39932D-page 244  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 17.6 Register Maps Table17-5, Table17-6 and Table17-7 summarize the registers associated with the RTCC module. TABLE 17-5: RTCC CONTROL REGISTERS All File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0000 RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 PADCFG1 — — — — — RTSECSEL1 RTSECSEL0 PMPTTL 0000 ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000 ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 1111 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 0000 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices. TABLE 17-6: RTCC VALUE REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RTCVALH RTCC Value Register Window High Byte, Based on RTCPTR<1:0> xxxx RTCVALL RTCC Value Register Window Low Byte, Based on RTCPTR<1:0> xxxx RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0000 ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000 ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0> xxxx ALRMVALL Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0> xxxx Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices. TABLE 17-7: ALARM VALUE REGISTERS All File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0> xxxx ALRMVALL Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0> xxxx RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 RTCVALH RTCC Value Register Window High Byte, Based on RTCPTR<1:0> xxxx RTCVALL RTCC Value Register Window Low Byte, Based on RTCPTR<1:0> xxxx Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 245

PIC18F46J11 FAMILY NOTES: DS39932D-page 246  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 18.0 ENHANCED ECCP1 and ECCP2 are implemented as standard CCP CAPTURE/COMPARE/PWM modules with enhanced PWM capabilities. These include: (ECCP) MODULE • Provision for two or four output channels PIC18F46J11 family devices have two Enhanced • Output Steering modes Capture/Compare/PWM (ECCP) modules: ECCP1 and • Programmable polarity ECCP2. These modules contain a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit • Programmable dead-band control Compare register or a PWM Master/Slave Duty Cycle • Automatic shutdown and restart register. These ECCP modules are upward compatible The enhanced features are discussed in detail in with CCP Section18.5 “PWM (Enhanced Mode)”. Note: Register and bit names referencing one of Note: PxA, PxB, PxC and PxD are associated the two ECCP modules substitute an ‘x’ with the remappable pins (RPn). for the module number. For example, reg- isters CCP1CON and CCP2CON, which have the same definitions, are called CCPxCON. Figures and diagrams use ECCP1-based names, but those names also apply to ECCP2, with a “2” replacing the illustration name’s “1”. When writing firmware, the “x” in register and bit names must be replaced with the appropriate module number.  2011 Microchip Technology Inc. DS39932D-page 247

PIC18F46J11 FAMILY REGISTER 18-1: CCPxCON: ECCPx CONTROL (ACCESS FBAh/FB4h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as capture/compare input/output; PxB, PxC and PxD assigned as port pins If CCPxM<3:2> = 11: 00 = Single output: PxA, PxB, PxC and PxD controlled by steering (see Section18.5.7 “Pulse Steering Mode”) 01 = Full-bridge output forward: PxD modulated; PxA active; PxB, PxC inactive 10 = Half-bridge output: PxA, PxB modulated with dead-band control; PxC and PxD assigned as port pins 11 = Full-bridge output reverse: PxB modulated; PxC active; PxA and PxD inactive bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match 0011 = Capture mode 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize ECCPx pin low, set output on compare match (set CCPxIF) 1001 = Compare mode, initialize ECCPx pin high, clear output on compare match (set CCPxIF) 1010 = Compare mode, generate software interrupt only, ECCPx pin reverts to I/O state 1011 = Compare mode, trigger special event (ECCPx resets TMR1 or TMR3, starts A/D conversion, sets CCxIF bit) 1100 = PWM mode; PxA and PxC active-high; PxB and PxD active-high 1101 = PWM mode; PxA and PxC active-high; PxB and PxD active-low 1110 = PWM mode; PxA and PxC active-low; PxB and PxD active-high 1111 = PWM mode; PxA and PxC active-low; PxB and PxD active-low DS39932D-page 248  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY In addition to the expanded range of modes available 18.2 Capture Mode through the CCPxCON and ECCPxAS registers, the ECCP modules have two additional registers associated In Capture mode, the CCPRxH:CCPRxL register pair with Enhanced PWM operation and auto-shutdown captures the 16-bit value of the TMR1 or TMR3 features. They are: registers when an event occurs on the corresponding ECCPx pin. An event is defined as one of the following: • ECCPxDEL (Enhanced PWM Control) • Every falling edge • PSTRxCON (Pulse Steering Control) • Every rising edge 18.1 ECCP Outputs and Configuration • Every 4th rising edge • Every 16th rising edge The Enhanced CCP module may have up to four PWM The event is selected by the mode select bits, outputs, depending on the selected operating mode. CCPxM<3:0>, of the CCPxCON register. When a These outputs, designated PxA through PxD, are capture is made, the interrupt request flag bit, CCPxIF, routed through the Peripheral Pin Select (PPS) is set; it must be cleared by software. If another capture module. Therefore, individual functions may be occurs before the value in register CCPRx is read, the mapped to any of the remappable I/O pins, RPn. The old captured value is overwritten by the new captured outputs that are active depend on the ECCP operating value. mode selected. The pin assignments are summarized in Table18-4. 18.2.1 ECCP PIN CONFIGURATION To configure the I/O pins as PWM outputs, the proper In Capture mode, the appropriate ECCPx pin should be PWM mode must be selected by setting the PxM<1:0> configured as an input by setting the corresponding and CCPxM<3:0> bits. The appropriate TRIS direction TRIS direction bit. bits for the port pins must also be set as outputs and the output functions need to be assigned to I/O pins in the Additionally, the ECCPx input function needs to be PPS module. (For details on configuring the module, assigned to an I/O pin through the Peripheral Pin see Section10.7 “Peripheral Pin Select (PPS)”.) Select module. For details on setting up the remappable pins, see Section10.7 “Peripheral Pin 18.1.1 ECCP MODULE AND TIMER Select (PPS)”. RESOURCES Note: If the ECCPx pin is configured as an out- The ECCP modules utilize Timers 1, 2, 3 or 4, depending put, a write to the port can cause a capture on the mode selected. Timer1 and Timer3 are available condition. to modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. 18.2.2 TIMER1/TIMER3 MODE SELECTION The timers that are to be used with the capture feature TABLE 18-1: ECCP MODE – TIMER (Timer1 and/or Timer3) must be running in Timer mode RESOURCE or Synchronized Counter mode. In Asynchronous ECCP Mode Timer Resource Counter mode, the capture operation may not work. The timer to be used with each ECCP module is Capture Timer1 or Timer3 selected in the TCLKCON register (Register13-3). Compare Timer1 or Timer3 18.2.3 SOFTWARE INTERRUPT PWM Timer2 or Timer4 When the Capture mode is changed, a false capture The assignment of a particular timer to a module is interrupt may be generated. The user should keep the determined by the Timer-to-ECCP enable bits in the CCPxIE interrupt enable bit clear to avoid false interrupts. TCLKCON register (Register13-3). The interactions The interrupt flag bit, CCPxIF, should also be cleared between the two modules are depicted in Figure18-1. following any such change in operating mode. Capture operations are designed to be used when the timer is configured for Synchronous Counter mode. Capture operations may not work as expected if the associated timer is configured for Asynchronous Counter mode.  2011 Microchip Technology Inc. DS39932D-page 249

PIC18F46J11 FAMILY 18.2.4 ECCP PRESCALER recommended method for switching between capture prescalers. This example also clears the prescaler There are four prescaler settings in Capture mode; they counter and will not generate the “false” interrupt. are specified as part of the operating mode selected by the mode select bits (CCPxM<3:0>). Whenever the EXAMPLE 18-1: CHANGING BETWEEN ECCP module is turned off, or Capture mode is dis- CAPTURE PRESCALERS abled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. CLRF CCP1CON ; Turn CCP module off Switching from one capture prescaler to another may MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode generate an interrupt. Also, the prescaler counter will ; value and CCP ON not be cleared; therefore, the first capture may be from MOVWF CCP1CON ; Load CCP1CON with a non-zero prescaler. Example18-1 provides the ; this value FIGURE 18-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP1IF T3CCP1 TMR3 Enable ECCP1 pin Prescaler and CCPR1H CCPR1L  1, 4, 16 Edge Detect TMR1 T3CCP1 Enable 4 TMR1H TMR1L CCP1CON<3:0> 4 Q1:Q4 DS39932D-page 250  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 18.3 Compare Mode 18.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is Timer1 and/or Timer3 must be running in Timer mode constantly compared against either the TMR1 or TMR3 or Synchronized Counter mode if the ECCP module is register pair value. When a match occurs, the ECCPx using the compare feature. In Asynchronous Counter pin can be: mode, the compare operation will not work reliably. • Driven high 18.3.3 SOFTWARE INTERRUPT MODE • Driven low When the Generate Software Interrupt mode is chosen • Toggled (high-to-low or low-to-high) (CCPxM<3:0> = 1010), the ECCPx pin is not affected; • Remain unchanged (that is, reflects the state of only the CCPxIF interrupt flag is affected. the I/O latch) 18.3.4 SPECIAL EVENT TRIGGER The action on the pin is based on the value of the mode select bits (CCPxM<3:0>). At the same time, the The ECCP module is equipped with a Special Event interrupt flag bit, CCPxIF, is set. Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. 18.3.1 ECCP PIN CONFIGURATION The Special Event Trigger is enabled by selecting Users must configure the ECCPx pin as an output by the Compare Special Event Trigger mode clearing the appropriate TRIS bit. (CCPxM<3:0> = 1011). The Special Event Trigger resets the Timer register pair Note: Clearing the CCPxCON register will force for whichever timer resource is currently assigned as the the ECCPx compare output latch module’s time base. This allows the CCPRx registers to (depending on device configuration) to the serve as a programmable period register for either timer. default low level. This is not the PORTx I/O data latch. The Special Event Trigger can also start an A/D conver- sion. In order to do this, the A/D converter must already be enabled. FIGURE 18-2: COMPARE MODE OPERATION BLOCK DIAGRAM TMR1H TMR1L 0 1 TMR3H TMR3L Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) T3CCP1 Set CCP1IF ECCP1 Pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCPR1H CCPR1L CCP1CON<3:0>  2011 Microchip Technology Inc. DS39932D-page 251

PIC18F46J11 FAMILY 18.4 PWM Mode 18.4.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCPx pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. (PR4) register. The PWM period can be calculated using Equation18-1: Note: Clearing the CCPxCON register will force the output latch (depending on device EQUATION 18-1: configuration) to the default low level. This is not the LATx data latch. PWM Period = [(PR2) + 1] • 4 • TOSC • (TMR2 Prescale Value) Figure18-3 shows a simplified block diagram of the CCP module in PWM mode. PWM frequency is defined as 1/[PWM period]. For a step-by-step procedure on how to set up a CCP When TMR2 (TMR4) is equal to PR2 (PR4), the module for PWM operation, see Section18.4.3 following three events occur on the next increment “Setup for PWM Operation”. cycle: FIGURE 18-3: SIMPLIFIED PWM BLOCK • TMR2 (TMR4) is cleared DIAGRAM • The CCPx pin is set (exception: if PWM duty cycle=0%, the CCPx pin will not be set) Duty Cycle Register • The PWM duty cycle is latched from CCPRxL into 9 0 CCPRxL CCPxCON<5:4> CCPRxH Note: The Timer2 and Timer 4 postscalers (see Latch Duty Cycle Section14.0 “Timer2 Module” and Section16.0 “Timer4 Module”) are not CCPRxH (1) used in the determination of the PWM frequency. The postscaler could be used Comparator S Q to have a servo update rate at a different R CCPx frequency than the PWM output. Reset pin TMRx TMRMxa t=c hPRx 2 LSbs latched 18.4.2 PWM DUTY CYCLE Comparator from Q clocks The PWM duty cycle is specified by writing to the CCPRxL register and to the CCPxCON<5:4> bits. Up PRx to 10-bit resolution is available. The CCPRxL contains TRIS Set CCPx pin Output Enable the eight MSbs and the CCPxCON<5:4> contains the two LSbs. This 10-bit value is represented by Note1: The two LSbs of the Duty Cycle register are held by a 2-bit latch that is part of the module’s hardware. It is CCPRxL:CCPxCON<5:4>. Equation18-2 is used to physically separate from the CCPRx registers. calculate the PWM duty cycle in time. A PWM output (Figure18-4) has a time base (period) EQUATION 18-2: and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) • period (1/period). TOSC • (TMR2 Prescale Value) CCPRxL and CCPxCON<5:4> can be written to at any FIGURE 18-4: PWM OUTPUT time, but the duty cycle value is not latched into Period CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. Duty Cycle TMR2 (TMR4) = PR2 (PR4) TMR2 (TMR4) = Duty Cycle TMR2 (TMR4) = PR2 (TMR4) DS39932D-page 252  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY The CCPRxH register and a 2-bit internal latch are 18.4.3 SETUP FOR PWM OPERATION used to double-buffer the PWM duty cycle. This The following steps should be taken when configuring double-buffering is essential for glitchless PWM the CCP module for PWM operation: operation. 1. Set the PWM period by writing to the PR2 (PR4) When the CCPRxH and 2-bit latch match TMR2 register. (TMR4), concatenated with an internal 2-bit Q clock or 2. Set the PWM duty cycle by writing to the 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is CCPRxL register and CCPxCON<5:4> bits. cleared. 3. Make the CCPx pin an output by clearing the The maximum PWM resolution (bits) for a given PWM appropriate TRIS bit. frequency is given by Equation18-3: 4. Set the TMR2 (TMR4) prescale value, then enable Timer2 (Timer4) by writing to T2CON EQUATION 18-3: (T4CON). (FOSC ) log 5. Configure the CCPx module for PWM operation. FPWM PWM Resolution (max) = bits log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 18-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58  2011 Microchip Technology Inc. DS39932D-page 253

PIC18F46J11 FAMILY TABLE 18-3: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 RCON IPEN — CM RI TO PD POR BOR 70 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72 IPR2 OSCFIP CM2IP CM1IP — BCL1IP LVDIP TMR3IP CCP2IP 71 PIR2 OSCFIF CM2IF CM1IF — BCL1IF LVDIF TMR3IF CCP2IF 71 PIE2 OSCFIE CM2IE CM1IE — BCL1IE LVDIE TMR3IE CCP2IE 71 TCLKCON — — — T1RUN — — T3CCP2 T3CCP1 74 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 72 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 72 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 72 TMR2 Timer2 Register 70 PR2 Timer2 Period Register 70 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 70 TMR4 Timer4 Register 73 PR4 Timer4 Period Register 73 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 73 ODCON1 — — — — — — ECCP2OD ECCP1OD 74 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4. DS39932D-page 254  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 18.5 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated: PxA, PxB, PxC and PxD. The polarity of the The Enhanced PWM mode can generate a PWM signal PWM pins is configurable and is selected by setting the on up to four different output pins with up to 10 bits of CCPxM bits in the CCPxCON register appropriately. resolution. It can do this through four different PWM Table18-1 provides the pin assignments for each Output modes: Enhanced PWM mode. • Single PWM Figure18-5 provides an example of a simplified block • Half-Bridge PWM diagram of the Enhanced PWM module. • Full-Bridge PWM, Forward mode Note: To prevent the generation of an • Full-Bridge PWM, Reverse mode incomplete waveform when the PWM is To select an Enhanced PWM mode, the PxM bits of the first enabled, the ECCP module waits until CCPxCON register must be set appropriately. the start of a new PWM period before generating a PWM signal. FIGURE 18-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DC1B<1:0> PxM<1:0> CCPxM<3:0> Duty Cycle Registers 2 4 CCPR1L ECCPx/PxA(2) ECCP1/RPn TRIS CCPR1H (Slave) PxB(2) RPn Output TRIS Comparator R Q Controller PxC(2) PRn TMR2 (1) S TRIS PxD(2) PRn Comparator Clear Timer2, TRIS toggle PWM pin and latch duty cycle PR2 ECCP1DEL Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. 2: These pins are remappable. Note1: The TRIS register value for each PWM output must be configured appropriately. 2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.  2011 Microchip Technology Inc. DS39932D-page 255

PIC18F46J11 FAMILY TABLE 18-4: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Outputs are enabled by pulse steering in Single mode (see Register18-4). FIGURE 18-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse Width PR2 + 1 PxM<1:0> Signal 0 Period 00 (Single Output) PxA Modulated Delay(1) Delay(1) PxA Modulated 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCPxDEL<6:0>) Note 1: Dead-band delay is programmed using the ECCPxDEL register (Section18.5.6 “Programmable Dead-Band Delay Mode”). DS39932D-page 256  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 18-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal 0 Pulse PR2 + 1 Width Period 00 (Single Output) PxA Modulated PxA Modulated Delay(1) Delay(1) 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCPxDEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section18.5.6 “Programmable Dead-Band Delay Mode”).  2011 Microchip Technology Inc. DS39932D-page 257

PIC18F46J11 FAMILY 18.5.1 HALF-BRIDGE MODE Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be In Half-Bridge mode, two pins are used as outputs to cleared to configure PxA and PxB as outputs. drive push-pull loads. The PWM output signal is output on the PxA pin, while the complementary PWM output FIGURE 18-8: EXAMPLE OF signal is output on the PxB pin (see Figure18-8). This HALF-BRIDGE PWM mode can be used for half-bridge applications, as shown in Figure18-9, or for full-bridge applications, OUTPUT where four power switches are being modulated with Period Period two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in PxA(2) half-bridge power devices. The value of the PxDC<6:0> td bits of the ECCPxDEL register sets the number of td instruction cycles before the output is driven active. If the PxB(2) value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See (1) (1) (1) Section18.5.6 “Programmable Dead-Band Delay Mode” for more details of the dead-band delay td = Dead-Band Delay operations. Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FIGURE 18-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA - Load FET Driver + PxB - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver PxA Load FET FET Driver Driver PxB DS39932D-page 258  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 18.5.2 FULL-BRIDGE MODE In the Reverse mode, the PxC pin is driven to its active state, the PxB pin is modulated, while the PxA and PxD In Full-Bridge mode, all four pins are used as outputs. pins will be driven to their inactive state as provided An example of a full-bridge application is provided in Figure18-11. Figure18-10. The PxA, PxB, PxC and PxD outputs are multiplexed In the Forward mode, the PxA pin is driven to its active with the PORT data latches. The associated TRIS bits state, the PxD pin is modulated, while the PxB and PxC must be cleared to configure the PxA, PxB, PxC and pins will be driven to their inactive state as provided in PxD pins as outputs. Figure18-11. FIGURE 18-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver PxA Load PxB FET FET Driver Driver PxC QB QD V- PxD  2011 Microchip Technology Inc. DS39932D-page 259

PIC18F46J11 FAMILY FIGURE 18-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA(2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: The output signal is shown as active-high. DS39932D-page 260  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 18.5.2.1 Direction Change in Full-Bridge 1. The direction of the PWM output changes when Mode the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including In the Full-Bridge mode, the PxM1 bit in the CCPxCON the power device and driver circuit, is greater register allows users to control the forward/reverse than the turn-on time. direction. When the application firmware changes this direction control bit, the module will change to the new Figure18-13 shows an example of the PWM direction direction on the next PWM cycle. changing from forward to reverse, at a near 100% duty cycle. In this example, at time, t1, the PxA and PxD A direction change is initiated in software by changing outputs become inactive, while the PxC output the PxM1 bit of the CCPxCON register. The following becomes active. Since the turn-off time of the power sequence occurs prior to the end of the current PWM devices is longer than the turn-on time, a shoot-through period: current will flow through power devices, QC and QD • The modulated outputs (PxB and PxD) are placed (see Figure18-10), for the duration of ‘t’. The same in their inactive state. phenomenon will occur to power devices, QA and QB, • The associated unmodulated outputs (PxA and for PWM direction change from reverse to forward. PxC) are switched to drive in the opposite If changing PWM direction at high duty cycle is required direction. for an application, two possible solutions for eliminating • PWM modulation resumes at the beginning of the the shoot-through current are: next period. 1. Reduce PWM duty cycle for one PWM period See Figure18-12 for an illustration of this sequence. before changing directions. The Full-Bridge mode does not provide a dead-band 2. Use switch drivers that can drive the switches off delay. As one output is modulated at a time, a faster than they can drive them on. dead-band delay is generally not required. There is a Other options to prevent shoot-through current may situation where a dead-band delay is required. This exist. situation occurs when both of the following conditions are true: FIGURE 18-12: EXAMPLE OF PWM DIRECTION CHANGE Signal Period(1) Period PxA (Active-High) PxB (Active-High) Pulse Width PxC (Active-High) (2) PxD (Active-High) Pulse Width Note 1: The direction bit, PxM1 of the CCPxCON register, is written any time during the PWM cycle. 2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is: (1/FOSC)  TMR2 Prescale Value  2011 Microchip Technology Inc. DS39932D-page 261

PIC18F46J11 FAMILY FIGURE 18-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential T = TOFF – TON Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver. 18.5.3 START-UP CONSIDERATIONS polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configura- When any PWM mode is used, the application tion while the PWM pin output drivers are enabled is hardware must use the proper external pull-up and/or not recommended since it may result in damage to the pull-down resistors on the PWM output pins. application circuits. Note: When the microcontroller is released from The PxA, PxB, PxC and PxD output latches may not be Reset, all of the I/O pins are in the in the proper states when the PWM module is high-impedance state. The external initialized. Enabling the PWM pin output drivers at the circuits must keep the power switch same time as the Enhanced PWM modes may cause devices in the OFF state until the micro- damage to the application circuit. The Enhanced PWM controller drives the I/O pins with the modes must be enabled in the proper Output mode and proper signal levels or activates the PWM complete a full PWM cycle before enabling the PWM output(s). pin output drivers. The completion of a full PWM cycle The CCPxM<1:0> bits of the CCPxCON register allow is indicated by the TMR2IF or TMR4IF bit of the PIR1 the user to choose whether the PWM output signals are or PIR3 register being set as the second PWM period active-high or active-low for each pair of PWM output begins. pins (PxA/PxC and PxB/PxD). The PWM output DS39932D-page 262  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 18.5.4 ENHANCED PWM A shutdown condition is indicated by the ECCPxASE AUTO-SHUTDOWN MODE (Auto-Shutdown Event Status) bit of the ECCPxAS register. If the bit is a ‘0’, the PWM pins are operating The PWM mode supports an Auto-Shutdown mode that normally. If the bit is a ‘1’, the PWM outputs are in the will disable the PWM outputs when an external shutdown state. shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This When a shutdown event occurs, two things happen: mode is used to help prevent the PWM from damaging The ECCPxASE bit is set to ‘1’. The ECCPxASE will the application. remain set until cleared in firmware or an auto-restart The auto-shutdown sources are selected using the occurs (see Section18.5.5 “Auto-Restart Mode”). ECCPxAS<2:0> bits of the ECCPAS register. A The enabled PWM pins are asynchronously placed in shutdown event may be generated by: their shutdown states. The PWM output pins are • A logic ‘0’ on the pin that is assigned the FLT0 grouped into pairs [PxA/PxC] and [PxB/PxD]. The state input function of each pin pair is determined by the PSSxAC and PSSxBD bits of the ECCPxAS register. Each pin pair • Comparator C1 may be placed into one of three states: • Comparator C2 • Drive logic ‘1’ • Setting the ECCPxASE bit in firmware • Drive logic ‘0’ • Tri-state (high-impedance) REGISTER 18-2: ECCPxAS: ECCPx AUTO-SHUTDOWN CONTROL REGISTER (ACCESS FBEh/FB8h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPxASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in a shutdown state 0 =ECCP outputs are operating bit 6-4 ECCPxAS<2:0>: ECCP Auto-Shutdown Source Select bits 000 =Auto-shutdown is disabled 001 =Comparator C1OUT output is high 010 =Comparator C2OUT output is high 011 =Either Comparator C1OUT or C2OUT is high 100 =VIL on FLT0 pin 101 =VIL on FLT0 pin or Comparator C1OUT output is high 110 =VIL on FLT0 pin or Comparator C2OUT output is high 111 =VIL on FLT0 pin or Comparator C1OUT or Comparator C2OUT is high bit 3-2 PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits 00 =Drive pins PxA and PxC to ‘0’ 01 =Drive pins PxA and PxC to ‘1’ 10 = Pins PxA and PxC tri-state bit 1-0 PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits 00 = Drive pins PxB and PxD to ‘0’ 01 = Drive pins PxB and PxD to ‘1’ 10 = Pins PxB and PxD tri-state Note1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCPxASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period.  2011 Microchip Technology Inc. DS39932D-page 263

PIC18F46J11 FAMILY FIGURE 18-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0) PWM Period Shutdown Event ECCPxASE bit PWM Activity Normal PWM ECCPxASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes 18.5.5 AUTO-RESTART MODE The module will wait until the next PWM period begins, however, before re-enabling the output pin. This behav- The Enhanced PWM can be configured to automatically ior allows the auto-shutdown with auto-restart features restart the PWM signal once the auto-shutdown condi- to be used in applications based on current mode PWM tion has been removed. Auto-restart is enabled by control. setting the PxRSEN bit in the ECCPxDEL register. If auto-restart is enabled, the ECCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPxASE bit will be cleared via hardware and normal operation will resume. FIGURE 18-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PxRSEN = 1) PWM Period Shutdown Event ECCPxASE bit PWM Activity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes DS39932D-page 264  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 18.5.6 PROGRAMMABLE DEAD-BAND FIGURE 18-16: EXAMPLE OF DELAY MODE HALF-BRIDGE PWM OUTPUT In half-bridge applications, where all power switches are modulated at the PWM frequency, the power Period Period switches normally require more time to turn off than to turn on. If both the upper and lower power switches are Pulse Width switched at the same time (one turned on and the other PxA(2) turned off), both switches may be on for a short period td until one switch completely turns off. During this brief td interval, a very high current (shoot-through current) will PxB(2) flow through both power switches, shorting the bridge supply. To avoid this potentially destructive (1) (1) (1) shoot-through current from flowing during switching, turning on either of the power switches is normally td = Dead-Band Delay delayed to allow the other switch to completely turn off. In Half-Bridge mode, a digitally programmable Note 1: At this time, the TMR2 register is equal to the dead-band delay is available to avoid shoot-through PR2 register. current from destroying the bridge power switches. The 2: Output signals are shown as active-high. delay occurs at the signal transition from the non-active state to the active state. See Figure18-16 for illustration. The lower seven bits of the associated ECCPxDEL register (Register18-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 18-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA V - Load FET Driver + PxB V - V-  2011 Microchip Technology Inc. DS39932D-page 265

PIC18F46J11 FAMILY REGISTER 18-3: ECCPxDEL: ENHANCED PWM CONTROL REGISTER (ACCESS FBDh/FB7h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPxASE must be cleared by software to restart the PWM bit 6-0 PxDC<6:0>: PWM Delay Count bits PxDCn = Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active. 18.5.7 PULSE STEERING MODE While the PWM Steering mode is active, the CCPxM<1:0> bits of the CCPxCON register select the In Single Output mode, pulse steering allows any of the PWM output polarity for the Px<D:A> pins. PWM pins to be the modulated signal. Additionally, the same PWM signal can simultaneously be available on The PWM auto-shutdown operation also applies to multiple pins. PWM Steering mode as described in Section18.5.4 “Enhanced PWM Auto-shutdown mode”. An Once the Single Output mode is selected auto-shutdown event will only affect pins that have (CCPxM<3:2> = 11 and PxM<1:0> = 00 of the PWM outputs enabled. CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR<D:A> bits of the PSTRxCON register, as provided in Table18-4. Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. DS39932D-page 266  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 18-4: PSTRxCON: PULSE STEERING CONTROL (ACCESS FBFh/FB9h)(1) R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits 1 = Modulated output pin toggles between PxA and PxB for each period 0 = Complementary output assignment disabled; STRD:STRA bits used to determine Steering mode bit 5 Unimplemented: Read as ‘0’ bit 4 STRSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRD: Steering Enable bit D 1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxD pin is assigned to port pin bit 2 STRC: Steering Enable bit C 1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxC pin is assigned to port pin bit 1 STRB: Steering Enable bit B 1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxB pin is assigned to port pin bit 0 STRA: Steering Enable bit A 1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxA pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCPxCON register bits, CCPxM<3:2>=11 and PxM<1:0>=00.  2011 Microchip Technology Inc. DS39932D-page 267

PIC18F46J11 FAMILY FIGURE 18-18: SIMPLIFIED STEERING 18.5.7.1 Steering Synchronization BLOCK DIAGRAM The STRSYNC bit of the PSTRxCON register gives the STRA user two selections of when the steering event will happen. When the STRSYNC bit is ‘0’, the steering PxA Signal RPn pin event will happen at the end of the instruction that CCPxM1 1 writes to the PSTRxCON register. In this case, the out- PORT Data put signal at the Px<D:A> pins may be an incomplete 0 TRIS PWM waveform. This operation is useful when the user STRB firmware needs to immediately remove a PWM signal from the pin. RPn pin CCPxM0 1 When the STRSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM PORT Data 0 period. In this case, steering on/off the PWM output will TRIS STRC always produce a complete PWM waveform. Figures 18-19 and18-20 illustrate the timing diagrams RPn pin CCPxM1 1 of the PWM steering depending on the STRSYNC setting. PORT Data 0 TRIS STRD RPn pin CCPxM0 1 PORT Data 0 TRIS Note 1: Port outputs are configured as displayed when the CCPxCON register bits, PxM<1:0>=00 and CCP1M<3:2>=11. 2: Single PWM output requires setting at least one of the STRx bits. FIGURE 18-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0) PWM Period PWM STRn P1<D:A> PORT Data PORT Data P1n = PWM FIGURE 18-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) PWM STRn P1<D:A> PORT Data PORT Data P1n = PWM DS39932D-page 268  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 18.5.8 OPERATION IN POWER-MANAGED the PIR2 register will be set. The ECCPx will then be MODES clocked from the internal oscillator clock source, which may have a different clock frequency than the primary In Sleep mode, all clock sources are disabled. Timer2 clock. will not increment and the state of the module will not change. If the ECCPx pin is driving a value, it will con- 18.5.9 EFFECTS OF A RESET tinue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are Both Power-on Reset and subsequent Resets will force all ports to Input mode and the ECCP registers to their enabled, the initial start-up frequency from HFINTOSC and the postscaler may not be stable immediately. Reset states. This forces the ECCP module to reset to a state In PRI_IDLE mode, the primary clock will continue to compatible with previous, non-enhanced ECCP clock the ECCPx module without change. modules used on other PIC18 and PIC16 devices. 18.5.8.1 Operation with Fail-Safe ClockMonitor (FSCM) If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock failure will force the device into the power-managed RC_RUN mode and the OSCFIF bit of TABLE 18-5: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 69 RCON IPEN — — RI TO PD POR BOR 70 PIR1 PMPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 72 PIR2 OSCFIF CM2IF CM1IF — BCL1IF LVDIF TMR3IF CCP2IF 72 PIE2 OSCFIE CM2IE CM1IE — BCL1IE LVDIE TMR3IE CCP2IE 72 IPR2 OSCFIP CM2IP CM1IP — BCL1IP LVDIP TMR3IP CCP2IP 72 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 72 TMR1L Timer1 Register Low Byte 70 TMR1H Timer1 Register High Byte 70 TCLKCON — — — T1RUN — — T3CCP2 T3CCP1 94 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON 70 TMR2 Timer2 Register 70 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 70 PR2 Timer2 Period Register 70 TMR3L Timer3 Register Low Byte 73 TMR3H Timer3 Register High Byte 73 T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 — T3SYNC RD16 TMR3ON 73 CCPR1L Capture/Compare/PWM Register 1 Low Byte 72 CCPR1H Capture/Compare/PWM Register 1 High Byte 72 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 72 ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 70 ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: These bits are only available on 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 269

PIC18F46J11 FAMILY NOTES: DS39932D-page 270  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.0 MASTER SYNCHRONOUS All of the MSSP1 module-related SPI and I2C I/O SERIAL PORT (MSSP) functions are hard-mapped to specific I/O pins. MODULE For MSSP2 functions: • SPI I/O functions (SDO2, SDI2, SCK2 and SS2) The Master Synchronous Serial Port (MSSP) module is are all routed through the Peripheral Pin Select a serial interface, useful for communicating with other (PPS) module. peripheral or microcontroller devices. These peripheral These functions may be configured to use any of devices include serial EEPROMs, shift registers, the RPn remappable pins, as described in display drivers and A/D Converters. Section10.7 “Peripheral Pin Select (PPS)”. • I2C functions (SCL2 and SDA2) have fixed pin 19.1 Master SSP (MSSP) Module locations. Overview On all PIC18F46J11 family devices, the SPI DMA capa- The MSSP module can operate in one of two modes: bility can only be used in conjunction with MSSP2. The • Serial Peripheral Interface (SPI) SPI DMA feature is described in Section19.4 “SPI • Inter-Integrated Circuit (I2C™) DMA Module”. - Full Master mode Note: Throughout this section, generic references to an MSSP module in any of its - Slave mode (with general address call) operating modes may be interpreted as The I2C interface supports the following modes in being equally applicable to MSSP1 or hardware: MSSP2. Register names and module I/O • Master mode signals use the generic designator ‘x’ to indicate the use of a numeral to distinguish • Multi-Master mode a particular module when required. Control • Slave mode with 5-bit and 7-bit address masking bit names are not individuated. (with address masking for both 10-bit and 7-bit addressing) All members of the PIC18F46J11 family have two MSSP modules, designated as MSSP1 and MSSP2. The modules operate independently: • PIC18F4XJ11 devices – Both modules can be configured for either I2C or SPI communication • PIC18F2XJ11 devices: - MSSP1 can be used for either I2C or SPI communication - MSSP2 can be used only for SPI communication  2011 Microchip Technology Inc. DS39932D-page 271

PIC18F46J11 FAMILY 19.2 Control Registers FIGURE 19-1: MSSPx BLOCK DIAGRAM (SPIMODE) Each MSSP module has three associated control registers. These include a status register (SSPxSTAT) Internal Data Bus and two control registers (SSPxCON1 and SSPxCON2). The use of these registers and their individual Configura- Read Write tion bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. SSPxBUF reg Additional details are provided under the individual sections. SDIx Note: In devices with more than one MSSP SSPxSR reg module, it is very important to pay close attention to the SSPxCON register SDOx bit 0 CSlhoicftk names. SSP1CON1 and SSP1CON2 control different operational aspects of the same module, while SSP1CON1 and SSP2CON1 control the same features for two different modules. SSx SSxControl Enable 19.3 SPI Mode Edge Select The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four 2 modes of SPI are supported. Clock Select When MSSP2 is used in SPI mode, it can optionally be SSPM<3:0> configured to work with the SPI DMA submodule SMP:CKE ) described in Section19.4 “SPI DMA Module”. SCKx 2 4 (T M R22 Output To accomplish communication, typically three pins are Edge used: Select Prescaler TOSC 4, 16, 64 • Serial Data Out (SDOx) – RC5/SDO1/RP16 or SDO2/Remappable Data to TXx/RXx in SSPxSR • Serial Data In (SDIx) – RC4/SDI1/SDA1/RP15 or TRIS bit SDI2/Remappable Note: Only port I/O names are used in this diagram for • Serial Clock (SCKx) – RC3/SCK1/SCL1/RP14 or the sake of brevity. Refer to the text for a full list of SCK2/Remappable multiplexed functions. Additionally, a fourth pin may be used when in a Slave mode of operation: • Slave Select (SSx) – RA5/AN4/SS1/ HLVDIN/RP2 or SS2/Remappable Figure19-1 depicts the block diagram of the MSSP module when operating in SPI mode. DS39932D-page 272  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.3.1 REGISTERS In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When Each MSSP module has four registers for SPI mode SSPxSR receives a complete byte, it is transferred to operation. These are: SSPxBUF and the SSPxIF interrupt is set. • MSSPx Control Register 1 (SSPxCON1) During transmission, the SSPxBUF is not • MSSPx Status Register (SSPxSTAT) double-buffered. A write to SSPxBUF will write to both • Serial Receive/Transmit Buffer Register SSPxBUF and SSPxSR. (SSPxBUF) Note: Because the SSPxBUF register is dou- • MSSPx Shift Register (SSPxSR) – Not directly ble-buffered, using read-modify-write accessible instructions such as BCF, COMF, etc., will SSPxCON1 and SSPxSTAT are the control and status not work. registers in SPI mode operation. The SSPxCON1 Similarly, when debugging under an in-cir- register is readable and writable. The lower six bits of cuit debugger, performing actions that the SSPxSTAT are read-only. The upper two bits of the cause reads of SSPxBUF (mouse SSPxSTAT are read/write. hovering, watch, etc.) can consume data SSPxSR is the shift register used for shifting data in or that the application code was expecting to out. SSPxBUF is the buffer register to which data receive. bytes are written to or read from. REGISTER 19-1: SSPxSTAT: MSSPx STATUS REGISTER – SPI MODE (ACCESS FC7h/F73h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE(1) D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state bit 5 D/A: Data/Address bit Used in I2C™ mode only. bit 4 P: Stop bit Used in I2C mode only; this bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>).  2011 Microchip Technology Inc. DS39932D-page 273

PIC18F46J11 FAMILY REGISTER 19-2: SSPxCON1: MSSPx CONTROL REGISTER 1 – SPI MODE (ACCESS FC6H/F72h) R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of over- flow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, this pin must be properly configured as input or output. 3: Bit combinations not specifically listed here, are either reserved or implemented in I2C™ mode only. DS39932D-page 274  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.3.2 OPERATION The Buffer Full bit, BF (SSPxSTAT<0>), indicates when SSPxBUF has been loaded with the received data When initializing the SPI, several options need to be (transmission is complete). When the SSPxBUF is read, specified. This is done by programming the appropriate the BF bit is cleared. This data may be irrelevant if the control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). SPI is only a transmitter. Generally, the MSSP interrupt These control bits allow the following to be specified: is used to determine when the transmission/reception • Master mode (SCKx is the clock output) has completed. If the interrupt method is not going to be • Slave mode (SCKx is the clock input) used, then software polling can be done to ensure that a • Clock Polarity (Idle state of SCKx) write collision does not occur. • Data Input Sample Phase (middle or end of data Example19-1 provides the loading of the SSPxBUF output time) (SSPxSR) for data transmission. • Clock Edge (output data on rising/falling edge of The SSPxSR is not directly readable or writable and SCKx) can only be accessed by addressing the SSPxBUF • Clock Rate (Master mode only) register. Additionally, the SSPxSTAT register indicates • Slave Select mode (Slave mode only) the various status conditions. Each MSSP module consists of a transmit/receive shift 19.3.3 OPEN-DRAIN OUTPUT OPTION register (SSPxSR) and a buffer register (SSPxBUF). The drivers for the SDOx output and SCKx clock pins The SSPxSR shifts the data in and out of the device, can be optionally configured as open-drain outputs. MSb first. The SSPxBUF holds the data that was written This feature allows the voltage level on the pin to be to the SSPxSR until the received data is ready. Once the pulled to a higher level through an external pull-up 8 bits of data have been received, that byte is moved to resistor, provided the SDOx or SCKx pin is not multi- the SSPxBUF register. Then, the Buffer Full (BF) detect plexed with an ANx analog function. This allows the bit (SSPxSTAT<0>) and the interrupt flag bit, SSPxIF, output to communicate with external circuits without the are set. This double-buffering of the received data need for additional level shifters. For more information, (SSPxBUF) allows the next byte to start reception before see Section10.1.4 “Open-Drain Outputs”. reading the data that was just received. The open-drain output option is controlled by the Any write to the SSPxBUF register during transmis- SPI2OD and SPI1OD bits (ODCON3<1:0>). Setting an sion/reception of data will be ignored and the Write SPIxOD bit configures both SDOx and SCKx pins for the Collision Detect bit, WCOL (SSPxCON1<7>), will be set. corresponding open-drain operation. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPxBUF register completed successfully. Note: When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of transfer data is written to the SSPxBUF. Application software should follow this process even when the current contents of SSPxBUF are not important. EXAMPLE 19-1: LOADING THE SSP1BUF (SSP1SR) REGISTER LOOP BTFSS SSP1STAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSP1BUF, W ;WREG reg = contents of SSP1BUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSP1BUF ;New data to xmit  2011 Microchip Technology Inc. DS39932D-page 275

PIC18F46J11 FAMILY 19.3.4 ENABLING SPI I/O Any MSSP1 serial port function that is not desired may be overridden by programming the corresponding Data To enable the serial port, MSSP Enable bit, SSPEN Direction (TRIS) register to the opposite value. If (SSPxCON1<5>), must be set. To reset or reconfigure individual MSSP2 serial port functions will not be used, SPI mode, clear the SSPEN bit, reinitialize the they may be left unmapped. SSPxCON1 registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as Note: When MSSP2 is used in SPI Master serial port pins. For the pins to behave as the serial port mode, the SCK2 function must be config- function, the appropriate TRIS bits, ANCON/PCFG bits ured as both an output and input in the and Peripheral Pin Select registers (if using MSSP2) PPS module. SCK2 must be initialized as should be correctly initialized prior to setting the an output pin (by writing 0x0A to one of SSPEN bit. the RPORx registers). Additionally, A typical SPI serial port initialization process follows: SCK2IN must also be mapped to the same pin, by initializing the RPINR22 reg- • Initialize ODCON3 register (optional open-drain ister. Failure to initialize SCK2/SCK2IN as output control) both output and input will prevent the • Initialize remappable pin functions (if using module from receiving data on the SDI2 MSSP2, see Section10.7 “Peripheral Pin pin, as the module uses the SCK2IN sig- Select (PPS)”) nal to latch the received data. • Initialize SCKx LAT value to desired Idle SCK level (if master device) 19.3.5 TYPICAL CONNECTION • Initialize SCKx ANCON/PCFG bit (if Slave mode Figure19-2 illustrates a typical connection between two and multiplexed with ANx function) microcontrollers. The master controller (Processor 1) • Initialize SCKx TRIS bit as output (Master mode) initiates the data transfer by sending the SCKx signal. or input (Slave mode) Data is shifted out of both shift registers on their pro- • Initialize SDIx ANCON/PCFG bit (if SDIx is grammed clock edge and latched on the opposite edge multiplexed with ANx function) of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers • Initialize SDIx TRIS bit would send and receive data at the same time. Whether • Initialize SSx ANCON/PCFG bit (if Slave mode the data is meaningful (or dummy data) depends on the and multiplexed with ANx function) application software. This leads to three scenarios for • Initialize SSx TRIS bit (Slave modes) data transmission: • Initialize SDOx TRIS bit • Master sends valid data–Slave sends dummy • Initialize SSPxSTAT register data • Initialize SSPxCON1 register • Master sends valid data–Slave sends valid data • Set SSPEN bit to enable the module • Master sends dummy data–Slave sends valid data FIGURE 19-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDOx SDIx Serial Input Buffer Serial Input Buffer (SSPxBUF) (SSPxBUF) SDIx SDOx Shift Register Shift Register (SSPxSR) (SSPxSR) MSb LSb MSb LSb Serial Clock SCKx SCKx PROCESSOR 1 PROCESSOR 2 DS39932D-page 276  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.3.6 MASTER MODE The CKP is selected by appropriately programming the CKP bit (SSPxCON1<4>). This then, would give The master can initiate the data transfer at any time waveforms for SPI communication as illustrated in because it controls the SCKx. The master determines Figure19-3, Figure19-5 and Figure19-6, where the when the slave (Processor 2, Figure19-2) is to Most Significant Byte (MSB) is transmitted first. In broadcast data by the software protocol. Master mode, the SPI clock rate (bit rate) is In Master mode, the data is transmitted/received as user-programmable to be one of the following: soon as the SSPxBUF register is written to. If the SPI • FOSC/4 (or TCY) is only going to receive, the SDOx output could be dis- abled (programmed as an input). The SSPxSR register • FOSC/16 (or 4 • TCY) will continue to shift in the signal present on the SDIx • FOSC/64 (or 16 • TCY) pin at the programmed clock rate. As each byte is • Timer2 output/2 received, it will be loaded into the SSPxBUF register as When using the Timer2 output/2 option, the Period if a normal received byte (interrupts and status bits Register 2 (PR2) can be used to determine the SPI bit appropriately set). This could be useful in receiver rate. However, only PR2 values of 0x01 to 0xFF are applications as a “Line Activity Monitor” mode. valid in this mode. Note: To avoid lost data in Master mode, a read Figure19-3 illustrates the waveforms for Master mode. of the SSPxBUF must be performed to When the CKE bit is set, the SDOx data is valid before clear the Buffer Full (BF) detect bit there is a clock edge on SCKx. The change of the input (SSPxSTAT<0>) between each sample is shown based on the state of the SMP bit. The transmission. time when the SSPxBUF is loaded with the received data is shown. FIGURE 19-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDIx (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF Next Q4 Cycle SSPxSR to after Q2 SSPxBUF  2011 Microchip Technology Inc. DS39932D-page 277

PIC18F46J11 FAMILY 19.3.7 SLAVE MODE transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable In Slave mode, the data is transmitted and received as depending on the application. the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Note1: When the SPI is in Slave mode with While in Slave mode, the external clock is supplied by the SSx pin control enabled the external clock source on the SCKx pin. This (SSPxCON1<3:0>=0100), the SPI external clock must meet the minimum high and low module will reset if the SSx pin is set to times as specified in the electrical specifications. VDD. While in Sleep mode, the slave can transmit/receive 2: If the SPI is used in Slave mode with CKE data. When a byte is received, the device can be set, then the SSx pin control must be configured to wake-up from Sleep. enabled. When the SPI module resets, the bit counter is forced 19.3.8 SLAVE SELECT to ‘0’. This can be done by either forcing the SSx pin to SYNCHRONIZATION a high level or clearing the SSPEN bit. The SSx pin allows a Synchronous Slave mode. The To emulate two-wire communication, the SDOx pin can SPI must be in Slave mode with the SSx pin control be connected to the SDIx pin. When the SPI needs to enabled (SSPxCON1<3:0> = 04h). When the SSx pin operate as a receiver, the SDOx pin can be configured is low, transmission and reception are enabled and the as an input. This disables transmissions from the SDOx pin is driven. When the SSx pin goes high, the SDOx. The SDIx can always be left as an input (SDIx SDOx pin is no longer driven, even if in the middle of a function) since it cannot create a bus conflict. FIGURE 19-4: SLAVE SYNCHRONIZATION WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 7 bit 0 SDIx bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2 SSPxBUF DS39932D-page 278  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2 SSPxBUF FIGURE 19-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2 SSPxSR to SSPxBUF  2011 Microchip Technology Inc. DS39932D-page 279

PIC18F46J11 FAMILY 19.3.9 OPERATION IN POWER-MANAGED 19.3.11 BUS MODE COMPATIBILITY MODES Table19-1 provides the compatibility between the In SPI Master mode, module clocks may be operating standard SPI modes and the states of the CKP and at a different speed than when in full-power mode. In CKE control bits. the case of Sleep mode, all clocks are halted. TABLE 19-1: SPI BUS MODES In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the Control Bits State Standard SPI Mode secondary clock (Timer1 oscillator) or the INTOSC Terminology source. See Section3.3 “Clock Sources and CKP CKE Oscillator Switching” for additional information. 0, 0 0 1 In most cases, the speed that the master clocks SPI 0, 1 0 0 data is not important; however, this should be 1, 0 1 1 evaluated for each system. 1, 1 1 0 If MSSP interrupts are enabled, they can wake the controller from Sleep mode, or one of the Idle modes, There is also an SMP bit, which controls when the data when the master completes sending data. If an exit is sampled. from Sleep or Idle mode is not desired, MSSP 19.3.12 SPI CLOCK SPEED AND MODULE interrupts should be disabled. INTERACTIONS If the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in Because MSSP1 and MSSP2 are independent that state until the device wakes. After the device modules, they can operate simultaneously at different returns to Run mode, the module will resume data rates. Setting the SSPM<3:0> bits of the transmitting and receiving data. SSPxCON1 register determines the rate for the corresponding module. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This An exception is when both modules use Timer2 as a allows the device to be placed in any power-managed time base in Master mode. In this instance, any mode and data to be shifted into the SPI changes to the Timer2 module’s operation will affect Transmit/Receive Shift register. When all 8 bits have both MSSP modules equally. If different bit rates are been received, the MSSP interrupt flag bit will be set, required for each module, the user should select one of and if enabled, will wake the device. the other three time base options for one of the modules. 19.3.10 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. DS39932D-page 280  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PMPIF(2) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE(2) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP(2) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 72 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 72 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 72 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 72 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 72 SSP1BUF MSSP1 Receive Buffer/Transmit Register 70 SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 70 SSPxSTAT SMP CKE D/A P S R/W UA BF 70 SSP2BUF MSSP2 Receive Buffer/Transmit Register 73 ODCON3(1) — — — — — — SPI2OD SPI1OD 74 Legend: Shaded cells are not used by the MSSP module in SPI mode. Note 1: Configuration SFR overlaps with default SFR at this address; available only when WDTCON<4> = 1. 2: These bits are only available on 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 281

PIC18F46J11 FAMILY 19.4 SPI DMA Module In SPI Slave modes, the MSSP2 module is capable of transmitting and/or receiving one byte of data while in The SPI DMA module contains control logic to allow the Sleep mode. This allows the SSP2IF flag in the PIR3 MSSP2 module to perform SPI direct memory access register to be used as a wake-up source. When the transfers. This enables the module to quickly transmit DMAEN bit is cleared, the SPI DMA module is or receive large amounts of data with relatively little effectively disabled, and the MSSP2 module functions CPU intervention. When the SPI DMA module is used, normally, but without DMA capabilities. If the DMAEN MSSP2 can directly read and write to general purpose bit is clear prior to entering Sleep, it is still possible to SRAM. When the SPI DMA module is not enabled, use the SSP2IF as a wake-up source without any data MSSP2 functions normally, but without DMA capability. loss. The SPI DMA module is composed of control logic, a Neither MSSP2 nor the SPI DMA module will provide Destination Receive Address Pointer, a Transmit any functionality in Deep Sleep. Upon exiting from Source Address Pointer, an interrupt manager and a Deep Sleep, all of the I/O pins, MSSP2 and SPI DMA Byte Count register for setting the size of each DMA related registers will need to be fully reinitialized before transfer. The DMA module may be used with all SPI the SPI DMA module can be used again. Master and Slave modes, and supports both half-duplex and full-duplex transfers. 19.4.4 REGISTERS 19.4.1 I/O PIN CONSIDERATIONS The SPI DMA engine is enabled and controlled by the following Special Function Registers: When enabled, the SPI DMA module uses the MSSP2 module. All SPI related input and output signals related • DMACON1 • DMACON2 to MSSP2 are routed through the Peripheral Pin Select • TXADDRH • TXADDRL module. The appropriate initialization procedure as • RXADDRH • RXADDRL described in Section19.4.6 “Using the SPI DMA • DMABCH • DMABCL Module” will need to be followed prior to using the SPI DMA module. The output pins assigned to the SDO2 19.4.4.1 DMACON1 and SCK2 functions can optionally be configured as open-drain outputs, such as for level shifting operations The DMACON1 register is used to select the main mentioned in the same section. operating mode of the SPI DMA module. The SSCON1 and SSCON0 bits are used to control the slave select 19.4.2 RAM TO RAM COPY OPERATIONS pin. Although the SPI DMA module is primarily intended to When MSSP2 is used in SPI Master mode with the SPI be used for SPI communication purposes, the module DMA module, SSDMA can be controlled by the DMA can also be used to perform RAM to RAM copy opera- module as an output pin. If MSSP2 will be used to com- tions. To do this, configure the module for Full-Duplex municate with an SPI slave device that needs the SS Master mode operation, but assign the SDO2 output pin to be toggled periodically, the SPI DMA hardware and SDI2 input functions onto the same RPn pin in the can automatically be used to deassert SS between PPS module. This will allow the module to operate in each byte, every two bytes or every four bytes. Loopback mode, providing RAM copy capability. Alternatively, user firmware can manually generate slave select signals with normal general purpose I/O 19.4.3 IDLE AND SLEEP pins, if required by the slave device(s). CONSIDERATIONS When the TXINC bit is set, the TXADDR register will The SPI DMA module remains fully functional when the automatically increment after each transmitted byte. microcontroller is in Idle mode. Automatic transmit address increment can be disabled During normal sleep, the SPI DMA module is not func- by clearing the TXINC bit. If the automatic transmit tional and should not be used. To avoid corrupting a address increment is disabled, each byte which is out- transfer, user firmware should be careful to make put on SDO2, will be the same (the contents of the certain that pending DMA operations are complete by SRAM pointed to by the TXADDR register) for the polling the DMAEN bit in the DMACON1 register prior entire DMA transaction. to putting the microcontroller into Sleep. DS39932D-page 282  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY When the RXINC bit is set, the RXADDR register will SPI Master mode, DLYINTEN = 0: The DLYCYC<3:0> automatically increment after each received byte. Auto- bits in the DMACON2 register determine the amount of matic receive address increment can be disabled by additional inter-byte delay, which is added by the SPI clearing the RXINC bit. If RXINC is disabled in DMA module during a transfer. The Master mode SS2 Full-Duplex or Half-Duplex Receive modes, all incom- output feature may be used. ing data bytes on SDI2 will overwrite the same memory SPI Master mode, DLYINTEN = 1: The amount of location pointed to by the RXADDR register. After the hardware overhead is slightly reduced in this mode, SPI DMA transaction has completed, the last received and the minimum inter-byte delay is 8 TCY for FOSC/4, byte will reside in the memory location pointed to by the 9 TCY for FOSC/16 and 15 TCY for FOSC/64. This mode RXADDR register. can potentially be used to obtain slightly higher The SPI DMA module can be used for either half-duplex effective SPI bandwidth. In this mode, the SS2 control receive only communication, half-duplex transmit only feature cannot be used, and should always be disabled communication or full-duplex simultaneous transmit and (DMACON1<7:6> = 00). Additionally, the interrupt receive operations. All modes are available for both SPI generating hardware (used in Slave mode) remains master and SPI slave configurations. The DUPLEX0 active. To avoid extraneous SSP2IF interrupt events, and DUPLEX1 bits can be used to select the desired set the DMACON2 delay bits, DLYCYC<3:0> = 1111, operating mode. and ensure that the SPI serial clock rate is no slower The behavior of the DLYINTEN bit varies greatly than FOSC/64. depending on the SPI operating mode. For example In SPI Master modes, the DMAEN bit is used to enable behavior for each of the modes, see Figure19-3 the SPI DMA module and to initiate an SPI DMA trans- through Figure19-6. action. After user firmware sets the DMAEN bit, the DMA hardware will begin transmitting and/or receiving SPI Slave mode, DLYINTEN = 1: In this mode, an data bytes according to the configuration used. In SPI SSP2IF interrupt will be generated during a transfer if Slave modes, setting the DMAEN bit will finish the the time between successful byte transmission events initialization steps needed to prepare the SPI DMA is longer than the value set by the DLYCYC<3:0> bits module for communication (which must still be initiated in the DMACON2 register. This interrupt allows slave by the master device). firmware to know that the master device is taking an unusually large amount of time between byte transmis- To avoid possible data corruption, once the DMAEN bit sions. For example, this information may be useful for is set, user firmware should not attempt to modify any implementing application-defined communication of the MSSP2 or SPI DMA related registers, with the protocols involving time-outs if the bus remains Idle for exception of the INTLVL bits in the DMACON2 register. too long. When DLYINTEN = 1, the DLYLVL<3:0> If user firmware wants to halt an ongoing DMA transac- interrupts occur normally according to the selected tion, the DMAEN bit can be manually cleared by the setting. firmware. Clearing the DMAEN bit while a byte is SPI Slave mode, DLYINTEN = 0: In this mode, the currently being transmitted will not immediately halt the time-out based interrupt is disabled. No additional byte in progress. Instead, any byte currently in SSP2IF interrupt events will be generated by the SPI progress will be completed before the MSSP2 and SPI DMA module, other than those indicated by the DMA modules go back to their Idle conditions. If user INTLVL<3:0> bits in the DMACON2 register. In this firmware clears the DMAEN bit, the TXADDR, mode, always set DLYCYC<3:0> = 0000. RXADDR and DMABC registers will no longer update, and the DMA module will no longer make any additional read or writes to SRAM; therefore, state information can be lost.  2011 Microchip Technology Inc. DS39932D-page 283

PIC18F46J11 FAMILY REGISTER 19-3: DMACON1: DMA CONTROL REGISTER 1 (ACCESS F88h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSCON1 SSCON0 TXINC RXINC DUPLEX1 DUPLEX0 DLYINTEN DMAEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 SSCON<1:0>: SSDMA Output Control bits (Master modes only) 11 = SSDMA is asserted for the duration of 4 bytes; DLYINTEN is always reset low 01 = SSDMA is asserted for the duration of 2 bytes; DLYINTEN is always reset low 10 = SSDMA is asserted for the duration of 1 byte; DLYINTEN is always reset low 00 = SSDMA is not controlled by the DMA module; DLYINTEN bit is software programmable bit 5 TXINC: Transmit Address Increment Enable bit Allows the transmit address to increment as the transfer progresses. 1 = The transmit address is to be incremented from the initial value of TXADDR<11:0> 0 = The transmit address is always set to the initial value of TXADDR<11:0> bit 4 RXINC: Receive Address Increment Enable bit Allows the receive address to increment as the transfer progresses. 1 = The received address is to be incremented from the initial value of RXADDR<11:0> 0 = The received address is always set to the initial value of RXADDR<11:0> bit 3-2 DUPLEX<1:0>: Transmit/Receive Operating Mode Select bits 10 = SPI DMA operates in Full-Duplex mode, data is simultaneously transmitted and received 01 = DMA operates in Half-Duplex mode, data is transmitted only 00 = DMA operates in Half-Duplex mode, data is received only bit 1 DLYINTEN: Delay Interrupt Enable bit Enables the interrupt to be invoked after the number of SCK cycles specified in DLYCYC<2:0> has elapsed from the latest completed transfer. 1 = The interrupt is enabled, SSCON<1:0> must be set to ‘00’ 0 = The interrupt is disabled bit 0 DMAEN: DMA Operation Start/Stop bit This bit is set by the users’ software to start the DMA operation. It is reset back to zero by the DMA engine when the DMA operation is completed or aborted. 1 = DMA is in session 0 = DMA is not in session DS39932D-page 284  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.4.4.2 DMACON2 to control how much time the module will Idle between bytes in a transfer. By default, the hardware requires a The DMACON2 register contains control bits for minimum delay of: 8TCY for FOSC/4, 9 TCY for FOSC/16 controlling interrupt generation and inter-byte delay and 15 TCY for FOSC/64. Additional delays can be behavior. The INTLVL<3:0> bits are used to select when added with the DLYCYC bits. In SPI Slave modes, the an SSP2IF interrupt should be generated.The function DLYCYC<3:0> bits may optionally be used to trigger an of the DLYCYC<3:0> bits depends on the SPI operating additional time-out based interrupt. mode (Master/Slave), as well as the DLYINTEN setting. In SPI Master mode, the DLYCYC<3:0> bits can be used REGISTER 19-4: DMACON2: DMA CONTROL REGISTER 2 (ACCESS F86h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DLYCYC3 DLYCYC2 DLYCYC1 DLYCYC0 INTLVL3 INTLVL2 INTLVL1 INTLVL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 DLYCYC<3:0>: Delay Cycle Selection bits When DLYINTEN=0, these bits specify the additional delay (above the base overhead of the hardware) in number of TCY cycles before the SSP2BUF register is written again for the next transfer. When DLYINTEN=1, these bits specify the additional delay in number of TCY cycles from the latest completed transfer before an interrupt to the CPU is invoked. In this case, the delay before the SSP2BUF register is written again is 1 TCY + (base overhead of hardware). 1111 = Delay time in number of instruction cycles is 2,048 cycles 1110 = Delay time in number of instruction cycles is 1,024 cycles 1101 = Delay time in number of instruction cycles is 896 cycles 1100 = Delay time in number of instruction cycles is 768 cycles 1011 = Delay time in number of instruction cycles is 640 cycles 1010 = Delay time in number of instruction cycles is 512 cycles 1001 = Delay time in number of instruction cycles is 384 cycles 1000 = Delay time in number of instruction cycles is 256 cycles 0111 = Delay time in number of instruction cycles is 128 cycles 0110 = Delay time in number of instruction cycles is 64 cycles 0101 = Delay time in number of instruction cycles is 32 cycles 0100 = Delay time in number of instruction cycles is 16 cycles 0011 = Delay time in number of instruction cycles is 8 cycles 0010 = Delay time in number of instruction cycles is 4 cycles 0001 = Delay time in number of instruction cycles is 2 cycles 0000 = Delay time in number of instruction cycles is 1 cycle  2011 Microchip Technology Inc. DS39932D-page 285

PIC18F46J11 FAMILY REGISTER 19-4: DMACON2: DMA CONTROL REGISTER 2 (ACCESS F86h) (CONTINUED) bit 3-0 INTLVL<3:0>: Watermark Interrupt Enable bits These bits specify the amount of remaining data yet to be transferred (transmitted and/or received) upon which an interrupt is generated. 1111 = Amount of remaining data to be transferred is 576 bytes 1110 = Amount of remaining data to be transferred is 512 bytes 1101 = Amount of remaining data to be transferred is 448 bytes 1100 = Amount of remaining data to be transferred is 384 bytes 1011 = Amount of remaining data to be transferred is 320 bytes 1010 = Amount of remaining data to be transferred is 256 bytes 1001 = Amount of remaining data to be transferred is 192 bytes 1000 = Amount of remaining data to be transferred is 128 bytes 0111 = Amount of remaining data to be transferred is 67 bytes 0110 = Amount of remaining data to be transferred is 32 bytes 0101 = Amount of remaining data to be transferred is 16 bytes 0100 = Amount of remaining data to be transferred is 8 bytes 0011 = Amount of remaining data to be transferred is 4 bytes 0010 = Amount of remaining data to be transferred is 2 bytes 0001 = Amount of remaining data to be transferred is 1 byte 0000 = Transfer complete DS39932D-page 286  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.4.4.3 DMABCH and DMABCL The SPI DMA module can write received data to all general purpose memory on the device. The SPI DMA The DMABCH and DMABCL register pair forms a 10-bit module cannot be used to modify the Special Function Byte Count register, which is used by the SPI DMA Registers contained in banks 14 and 15. module to send/receive up to 1,024 bytes for each DMA transaction. When the DMA module is actively running 19.4.5 INTERRUPTS (DMAEN = 1), the DMA Byte Count register decrements after each byte is transmitted/received. The DMA trans- The SPI DMA module alters the behavior of the SSP2IF action will halt and the DMAEN bit will be automatically interrupt flag. In normal/non-DMA modes, the SSP2IF is cleared by hardware after the last byte has completed. set once after every single byte is transmitted/received After a DMA transaction is complete, the DMABC through the MSSP2 module. When MSSP2 is used with register will read 0x000. the SPI DMA module, the SSP2IF interrupt flag will be set according to the user-selected INTLVL<3:0> value Prior to initiating a DMA transaction by setting the specified in the DMACON2 register. The SSP2IF inter- DMAEN bit, user firmware should load the appropriate rupt condition will also be generated once the SPI DMA value into the DMABCH/DMABCL registers. The transaction has fully completed, and the DMAEN bit has DMABC is a “base zero” counter, so the actual number been cleared by hardware. of bytes which will be transmitted follows in Equation19-1. The SSP2IF flag becomes set once the DMA byte count value indicates that the specified INTLVL has been For example, if user firmware wants to transmit 7bytes reached. For example, if DMACON2<3:0> = 0101 in one transaction, DMABC should be loaded with (16bytes remaining), the SSP2IF interrupt flag will 006h. Similarly, if user firmware wishes to transmit become set once DMABC reaches 00Fh. If user 1,024bytes, DMABC should be loaded with 3FFh. firmware then clears the SSP2IF interrupt flag, the flag will not be set again by the hardware until after all bytes EQUATION 19-1: BYTES TRANSMITTED have been fully transmitted and the DMA transaction is FOR A GIVEN DMABC complete. Bytes DMABC+1 Note: User firmware may modify the INTLVL bits XMIT while a DMA transaction is in progress (DMAEN = 1). If an INTLVL value is 19.4.4.4 TXADDRH and TXADDRL selected which is higher than the actual remaining number of bytes (indicated by The TXADDRH and TXADDRL registers pair together DMABC + 1), the SSP2IF interrupt flag to form a 12-bit Transmit Source Address Pointer will immediately become set. register. In modes that use TXADDR (Full-Duplex and For example, if DMABC = 00Fh (implying 16bytes are Half-Duplex Transmit), the TXADDR will be incre- mented after each byte is transmitted. Transmitted data remaining) and user firmware writes ‘1111’ to INTLVL<3:0> (interrupt when 576bytes remaining), bytes will be taken from the memory location pointed to the SSP2IF interrupt flag will immediately become set. by the TXADDR register. The contents of the memory If user firmware clears this interrupt flag, a new inter- locations pointed to by TXADDR will not be modified by rupt condition will not be generated until either: user the DMA module during a transmission. firmware again writes INTLVL with an interrupt level The SPI DMA module can read from and transmit data higher than the actual remaining level, or the DMA from all general purpose memory on the device. The SPI transaction completes and the DMAEN bit is cleared. DMA module cannot be used to read from the Special Function Registers (SFRs) contained in banks 14 and Note: If the INTLVL bits are modified while a 15. DMA transaction is in progress, care should be taken to avoid inadvertently 19.4.4.5 RXADDRH and RXADDRL changing the DLYCYC<3:0> value. The RXADDRH and RXADDRL register pair together to form a 12-bit Receive Destination Address Pointer. In modes that use RXADDR (Full-Duplex and Half-Duplex Receive), the RXADDR register will be incremented after each byte is received. Received data bytes will be stored at the memory location pointed to by the RXADDR register.  2011 Microchip Technology Inc. DS39932D-page 287

PIC18F46J11 FAMILY 19.4.6 USING THE SPI DMA MODULE 4. Detect the SSP2IF interrupt condition (PIR3<7). The following steps would typically be taken to enable a) If the interrupt was configured to occur at and use the SPI DMA module: the completion of the SPI DMA transaction, the DMAEN bit (DMACON1<0>) will be 1. Configure the I/O pins, which will be used by clear. User firmware may prepare the MSSP2. module for another transaction by repeating a) Assign SCK2, SDO2, SDI2 and SS2 to RPn steps 3.b through 3.e. pins as appropriate for the SPI mode which b) If the interrupt was configured to occur prior will be used. Only functions which will be to the completion of the SPI DMA trans- used need to be assigned to a pin. action, the DMAEN bit may still be set, b) Initialize the associated LATx registers for indicating the transaction is still in progress. the desired Idle SPI bus state. User firmware would typically use this inter- c) If Open-Drain Output mode on SDO2 and rupt condition to begin preparing new data SCK2 (Master mode) is desired, set for the next DMA transaction. Firmware ODCON3<1>. should not repeat steps 3.b. through 3.e. d) Configure corresponding TRISx bits for until the DMAEN bit is cleared by the each I/O pin used hardware, indicating the transaction is complete. 2. Configure and enable MSSP2 for the desired SPI operating mode. Example19-2 provides example code demonstrating a) Select the desired operating mode (Master the initialization process and the steps needed to use or Slave, SPI Mode 0, 1, 2 and 3) and the SPI DMA module to perform a 512-byte configure the module by writing to the Full-Duplex, Master mode transfer. SSP2STAT and SSP2CON1 registers. b) Enable MSSP2 by setting SSP2CON1<5> = 1. 3. Configure the SPI DMA engine. a) Select the desired operating mode by writing the appropriate values to DMACON2 and DMACON1. b) Initialize the TXADDRH/TXADDRL Pointer (Full-Duplex or Half-Duplex Transmit Only mode). c) Initialize the RXADDRH/RXADDRL Pointer (Full-Duplex or Half-Duplex Receive Only mode). d) Initialize the DMABCH/DMABCL Byte Count register with the number of bytes to be transferred in the next SPI DMA operation. e) Set the DMAEN bit (DMACON1<0>). In SPI Master modes, this will initiate a DMA transaction. In SPI Slave modes, this will complete the initialization process, and the module will now be ready to begin receiving and/or transmitting data to the master device once the master starts the transaction. DS39932D-page 288  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY EXAMPLE 19-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER ;For this example, let's use RP5(RB2) for SCK2, ;RP4(RB1) for SDO2, and RP3(RB0) for SDI2 ;Let’s use SPI master mode, CKE = 0, CKP = 0, ;without using slave select signalling. InitSPIPins: movlb 0x0F ;Select bank 15, for access to ODCON3 register bcf ODCON3, SPI2OD ;Let’s not use open drain outputs in this example bcf LATB, RB2 ;Initialize our (to be) SCK2 pin low (idle). bcf LATB, RB1 ;Initialize our (to be) SDO2 pin to an idle state bcf TRISB, RB1 ;Make SDO2 output, and drive low bcf TRISB, RB2 ;Make SCK2 output, and drive low (idle state) bsf TRISB, RB0 ;SDI2 is an input, make sure it is tri-stated ;Now we should unlock the PPS registers, so we can ;assign the MSSP2 functions to our desired I/O pins. movlb 0x0E ;Select bank 14 for access to PPS registers bcf INTCON, GIE ;I/O Pin unlock sequence will not work if CPU ;services an interrupt during the sequence movlw 0x55 ;Unlock sequence consists of writing 0x55 movwf EECON2 ;and 0xAA to the EECON2 register. movlw 0xAA movwf EECON2 bcf PPSCON, IOLOCK ;We may now write to RPINRx and RPORx registers bsf INTCON, GIE ;May now turn back on interrupts if desired movlw 0x03 ;0x0A is SCK2 output signal movwf RPINR21 ;Assign the SDI2 function to pin RP3 movlw 0x0A ;Let’s assign SCK2 output to pin RP4 movwf RPOR4 ;RPOR4 maps output signals to RP4 pin movlw 0x04 ;SCK2 also needs to be configured as an input on the same pin movwf RPINR22 ;SCK2 input function taken from RP4 pin movlw 0x09 ;0x09 is SDO2 output movwf RPOR5 ;Assign SDO2 output signal to the RP5 (RB2) pin bsf PPSCON, IOLOCK ;Lock the PPS registers to prevent changes movlb 0x0F ;Done with PPS registers, bank 15 has other SFRs InitMSSP2: clrf SSP2STAT ;CKE = 0, SMP = 0 (sampled at middle of bit) movlw b'00000000' ;CKP = 0, SPI Master mode, Fosc/4 movwf SSP2CON1 ;MSSP2 initialized bsf SSP2CON1, SSPEN ;Enable the MSSP2 module InitSPIDMA: movlw b'00111110' ;Full duplex, RX/TXINC enabled, no SSCON movwf DMACON1 ;DLYINTEN is set, so DLYCYC3:DLYCYC0 = 1111 movlw b'11110000' ;Minimum delay between bytes, interrupt movwf DMACON2 ;only once when the transaction is complete  2011 Microchip Technology Inc. DS39932D-page 289

PIC18F46J11 FAMILY EXAMPLE 19-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER (CONTINUED) ;Somewhere else in our project, lets assume we have ;allocated some RAM for use as SPI receive and ;transmit buffers. ; udata 0x500 ;DestBuf res 0x200 ;Let’s reserve 0x500-0x6FF for use as our SPI ; ;receive data buffer in this example ;SrcBuf res 0x200 ;Lets reserve 0x700-0x8FF for use as our SPI ; ;transmit data buffer in this example PrepareTransfer: movlw HIGH(DestBuf) ;Get high byte of DestBuf address (0x05) movwf RXADDRH ;Load upper four bits of the RXADDR register movlw LOW(DestBuf) ;Get low byte of the DestBuf address (0x00) movwf RXADDRL ;Load lower eight bits of the RXADDR register movlw HIGH(SrcBuf) ;Get high byte of SrcBuf address (0x07) movwf TXADDRH ;Load upper four bits of the TXADDR register movlw LOW(SrcBuf) ;Get low byte of the SrcBuf address (0x00) movwf TXADDRL ;Load lower eight bits of the TXADDR register movlw 0x01 ;Lets move 0x200 (512) bytes in one DMA xfer movwf DMABCH ;Load the upper two bits of DMABC register movlw 0xFF ;Actual bytes transferred is (DMABC + 1), so movwf DMABCL ;we load 0x01FF into DMABC to xfer 0x200 bytes BeginXfer: bsf DMACON1, DMAEN ;The SPI DMA module will now begin transferring ;the data taken from SrcBuf, and will store ;received bytes into DestBuf. ;Execute whatever ;CPU is now free to do whatever it wants to ;and the DMA operation will continue without ;intervention, until it completes. ;When the transfer is complete, the SSP2IF flag in ;the PIR3 register will become set, and the DMAEN bit ;is automatically cleared by the hardware. ;The DestBuf (0x500-0x7FF) will contain the received ;data. To start another transfer, firmware will need ;to reinitialize RXADDR, TXADDR, DMABC and then ;set the DMAEN bit. DS39932D-page 290  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.5 I2C Mode 19.5.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call These are: support), and provides interrupts on Start and Stop bits • MSSPx Control Register 1 (SSPxCON1) in hardware to determine a free bus (multi-master • MSSPx Control Register 2 (SSPxCON2) function). The MSSP module implements the standard • MSSPx Status Register (SSPxSTAT) mode specifications and 7-bit and 10-bit addressing. • Serial Receive/Transmit Buffer Register Two pins are used for data transfer: (SSPxBUF) • Serial Clock (SCLx) – RC3/SCK1/SCL1/RP14 or • MSSPx Shift Register (SSPxSR) – Not directly RD0/PMD0/SCL2 accessible • Serial Data (SDAx) – RC4/SDI1/SDA1/RP15 or • MSSPx Address Register (SSPxADD) RD1/PMD1/SDA2 • MSSPx 7-Bit Address Mask Register (SSPxMSK) The user must configure these pins as inputs by setting SSPxCON1, SSPxCON2 and SSPxSTAT are the the associated TRIS bits. control and status registers in I2C mode operation. The SSPxCON1 and SSPxCON2 registers are readable and FIGURE 19-7: MSSPx BLOCK DIAGRAM writable. The lower six bits of the SSPxSTAT are (I2C™ MODE) read-only. The upper two bits of the SSPxSTAT are read/write. Internal SSPxSR is the shift register used for shifting data in or Data Bus out. SSPxBUF is the buffer register to which data Read Write bytes are written to or read from. SSPxADD contains the slave device address when the SSPxBUF reg SCLx MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven Shift bits of SSPxADD act as the Baud Rate Generator Clock (BRG) reload value. SSPxSR reg SDAx MSb LSb SSPxMSK holds the slave address mask value when the module is configured for 7-Bit Address Masking mode. While it is a separate register, it shares the same Match Detect Addr Match SFR address as SSPxADD; it is only accessible when Address Mask the SSPM<3:0> bits are specifically set to permit access. Additional details are provided in Section19.5.3.4 “7-Bit Address Masking Mode”. SSPxADD reg In receive operations, SSPxSR and SSPxBUF together, create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to Start and Set, Reset SSPxBUF and the SSPxIF interrupt is set. Stop bit Detect S, P bits (SSPxSTAT reg) During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions.  2011 Microchip Technology Inc. DS39932D-page 291

PIC18F46J11 FAMILY REGISTER 19-5: SSPxSTAT: MSSPx STATUS REGISTER – I2C™ MODE (ACCESS FC7h/F73h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode. DS39932D-page 292  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 19-6: SSPxCON1: MSSPx CONTROL REGISTER 1 – I2C™ MODE (ACCESS FC6h/F72h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: SCKx Release Control bit In Slave mode: 1 = Releases clock 0 = Holds clock low (clock stretch); used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(2) 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1001 = Load SSPxMSK register at SSPxADD SFR address(3,4) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs. 2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. 3: When SSPM<3:0> = 1001, any reads or writes to the SSPxADD SFR address actually accesses the SSPxMSK register. 4: This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit is ‘1’).  2011 Microchip Technology Inc. DS39932D-page 293

PIC18F46J11 FAMILY REGISTER 19-7: SSPxCON2: MSSPx CONTROL REGISTER 2 –I2C™ MASTER MODE (ACCESS FC5h/F71h) R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN(3) ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only)(3) 1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; automatically cleared by hardware 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit(2) 1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit(2) 1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable bit(2) 1 = Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Start condition Idle Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). 3: This bit is not implemented in I2C Master mode. DS39932D-page 294  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 19-8: SSPxCON2: MSSPx CONTROL REGISTER 2 – I2C™ SLAVE MODE (ACCESS FC5h/F71h) R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT(2) ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit(2) Unused in Slave mode. bit 5-2 ADMSK<5:2>: Slave Address Mask Select bits (5-Bit Address Masking) 1 = Masking of corresponding bits of SSPxADD enabled 0 = Masking of corresponding bits of SSPxADD disabled bit 1 ADMSK1: Slave Address Least Significant bit(s) Mask Select bit In 7-Bit Addressing mode: 1 = Masking of SSPxADD<1> only enabled 0 = Masking of SSPxADD<1> only disabled In 10-Bit Addressing mode: 1 = Masking of SSPxADD<1:0> enabled 0 = Masking of SSPxADD<1:0> disabled bit 0 SEN: Start Condition Enable/Stretch Enable bit(1) 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). 2: This bit is unimplemented in I2C Slave mode. REGISTER 19-9: SSPxMSK: I2C™ SLAVE ADDRESS MASK REGISTER – 7-BIT MASKING MODE (ACCESS FC8h/F74h)(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 MSK<7:0>: Slave Address Mask Select bits 1 = Masking of corresponding bit of SSPxADD enabled 0 = Masking of corresponding bit of SSPxADD disabled Note 1: This register shares the same SFR address as SSPxADD and is only addressable in select MSSP operating modes. See Section19.5.3.4 “7-Bit Address Masking Mode” for more details. 2: MSK0 is not used as a mask bit in 7-bit addressing.  2011 Microchip Technology Inc. DS39932D-page 295

PIC18F46J11 FAMILY 19.5.2 OPERATION The SCLx clock input must have a minimum high and low for proper operation. The high and low times of the The MSSP module functions are enabled by setting the I2C specification, as well as the requirement of the MSSP Enable bit, SSPEN (SSPxCON1<5>). MSSP module, are shown in timing parameter 100 and The SSPxCON1 register allows control of the I2C parameter 101. operation. Four mode selection bits (SSPxCON1<3:0>) allow one of the following I2C modes to be selected: 19.5.3.1 Addressing • I2C Master mode, clock Once the MSSP module has been enabled, it waits for • I2C Slave mode (7-bit address) a Start condition to occur. Following the Start condition, • I2C Slave mode (10-bit address) the 8 bits are shifted into the SSPxSR register. All • I2C Slave mode (7-bit address) with Start and incoming bits are sampled with the rising edge of the clock (SCLx) line. The value of register, SSPxSR<7:1>, Stop bit interrupts enabled is compared to the value of the SSPxADD register. The • I2C Slave mode (10-bit address) with Start and address is compared on the falling edge of the eighth Stop bit interrupts enabled clock (SCLx) pulse. If the addresses match and the BF • I2C Firmware Controlled Master mode, slave is and SSPOV bits are clear, the following events occur: Idle 1. The SSPxSR register value is loaded into the Selection of any I2C mode with the SSPEN bit set SSPxBUF register. forces the SCLx and SDAx pins to be open-drain, 2. The Buffer Full bit, BF, is set. provided these pins are programmed as inputs by 3. An ACK pulse is generated. setting the appropriate TRISB or TRISD bits. To ensure 4. The MSSPx Interrupt Flag bit, SSPxIF, is set proper operation of the module, pull-up resistors must (and interrupt is generated, if enabled) on the be provided externally to the SCLx and SDAx pins. falling edge of the ninth SCLx pulse. 19.5.3 SLAVE MODE In 10-Bit Addressing mode, two address bytes need to In Slave mode, the SCLx and SDAx pins must be be received by the slave. The five Most Significant bits configured as inputs (TRISB<5:4> set). The MSSP (MSbs) of the first address byte specify if this is a 10-bit module will override the input state with the output data address. Bit R/W (SSPxSTAT<2>) must specify a write when required (slave-transmitter). so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal The I2C Slave mode hardware will always generate an ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two interrupt on an address match. Address masking will MSbs of the address. The sequence of events for 10-bit allow the hardware to generate an interrupt for more addressing is as follows, with steps 7 through 9 for the than one address (up to 31 in 7-bit addressing and up slave-transmitter: to 63 in 10-bit addressing). Through the mode select bits, the user can also choose to interrupt on Start and 1. Receive first (high) byte of address (bits, Stop bits. SSPxIF, BF and UA, are set on address match). 2. Update the SSPxADD register with second (low) When an address is matched, or the data transfer after byte of address (clears bit, UA, and releases the an address match is received, the hardware auto- SCLx line). matically will generate the Acknowledge (ACK) pulse and load the SSPxBUF register with the received value 3. Read the SSPxBUF register (clears bit, BF) and currently in the SSPxSR register. clear flag bit, SSPxIF. 4. Receive second (low) byte of address (bits, Any combination of the following conditions will cause SSPxIF, BF and UA, are set). the MSSP module not to give this ACK pulse: 5. Update the SSPxADD register with the first • The Buffer Full bit, BF (SSPxSTAT<0>), was set (high) byte of address. If match releases SCLx before the transfer was received. line, this will clear bit, UA. • The overflow bit, SSPOV (SSPxCON1<6>), was 6. Read the SSPxBUF register (clears bit, BF) and set before the transfer was received. clear flag bit, SSPxIF. In this case, the SSPxSR register value is not loaded 7. Receive Repeated Start condition. into the SSPxBUF, but bit, SSPxIF, is set. The BF bit is 8. Receive first (high) byte of address (bits, cleared by reading the SSPxBUF register, while bit, SSPxIF and BF, are set). SSPOV, is cleared through software. 9. Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF. DS39932D-page 296  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.5.3.2 Address Masking Modes the incoming address. This allows the module to Acknowledge up to 31 addresses when using 7-bit Masking an address bit causes that bit to become a addressing, or 63 addresses with 10-bit addressing (see “don’t care”. When one address bit is masked, two Example19-3). This Masking mode is selected when addresses will be Acknowledged and cause an inter- the MSSPMSK Configuration bit is programmed (‘0’). rupt. It is possible to mask more than one address bit at a time, which greatly expands the number of addresses The address mask in this mode is stored in the Acknowledged. SSPxCON2 register, which stops functioning as a control The I2C slave behaves the same way, whether address register in I2C Slave mode (Register19-8). In 7-Bit Address Masking mode, address mask bits, masking is used or not. However, when address mask- ing is used, the I2C slave can Acknowledge multiple ADMSK<5:1> (SSPxCON2<5:1>), mask the corresponding address bits in the SSPxADD register. For addresses and cause interrupts. When this occurs, it is any ADMSK bits that are set (ADMSK<n>=1), the cor- necessary to determine which address caused the responding address bit is ignored (SSPxADD<n>=x). interrupt by checking SSPxBUF. For the module to issue an address Acknowledge, it is The PIC18F46J11 family of devices is capable of using sufficient to match only on addresses that do not have an two different Address Masking modes in I2C slave active address mask. operation: 5-Bit Address Masking and 7-Bit Address In 10-Bit Address Masking mode, bits, ADMSK<5:2>, Masking. The Masking mode is selected at device mask the corresponding address bits in the SSPxADD configuration using the MSSPMSK Configuration bit. register. In addition, ADMSK1 simultaneously masks The default device configuration is 7-Bit Address the two LSbs of the address (SSPxADD<1:0>). For any Masking. ADMSK bits that are active (ADMSK<n>=1), the cor- Both Masking modes, in turn, support address masking responding address bit is ignored (SPxADD<n>=x). of 7-bit and 10-bit addresses. The combination of Also note, that although in 10-Bit Address Masking Masking modes and addresses provide different mode, the upper address bits reuse part of the ranges of Acknowledgable addresses for each SSPxADD register bits. The address mask bits do not combination. interact with those bits; they only affect the lower While both Masking modes function in roughly the address bits. same manner, the way they use address masks is Note1: ADMSK1 masks the two Least Signifi- different. cant bits of the address. 19.5.3.3 5-Bit Address Masking Mode 2: The two MSbs of the address are not affected by address masking. As the name implies, 5-Bit Address Masking mode uses an address mask of up to five bits to create a range of addresses to be Acknowledged, using bits 5 through 1 of EXAMPLE 19-3: ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE 7-Bit Addressing: SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be ‘0’) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh 10-Bit Addressing: SSPxADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since they are not affected by masking) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh  2011 Microchip Technology Inc. DS39932D-page 297

PIC18F46J11 FAMILY 19.5.3.4 7-Bit Address Masking Mode Setting or clearing mask bits in SSPxMSK behaves in the opposite manner of the ADMSK bits in 5-Bit Unlike 5-Bit Address Masking mode, 7-Bit Address Address Masking mode. That is, clearing a bit in Masking mode uses a mask of up to eight bits (in 10-bit SSPxMSK causes the corresponding address bit to be addressing) to define a range of addresses than can be masked; setting the bit requires a match in that Acknowledged, using the lowest bits of the incoming position. SSPxMSK resets to all ‘1’s upon any Reset address. This allows the module to Acknowledge up to condition and, therefore, has no effect on the standard 127 different addresses with 7-bit addressing, or MSSP operation until written with a mask value. 255with 10-bit addressing (see Example19-4). This mode is the default configuration of the module, and is With 7-Bit Address Masking mode, SSPxMSK<7:1> selected when MSSPMSK is unprogrammed (‘1’). bits mask the corresponding address bits in the SSPxADD register. For any SSPxMSK bits that are The address mask for 7-Bit Address Masking mode is active (SSPxMSK<n>=0), the corresponding stored in the SSPxMSK register, instead of the SSPxADD address bit is ignored (SSPxADD<n>=x). SSPxCON2 register. SSPxMSK is a separate hard- For the module to issue an address Acknowledge, it is ware register within the module, but it is not directly sufficient to match only on addresses that do not have addressable. Instead, it shares an address in the SFR an active address mask. space with the SSPxADD register. To access the SSPxMSK register, it is necessary to select MSSP With 10-Bit Address Masking mode, SSPxMSK<7:0> mode, ‘1001’ (SSPCON1<3:0> = 1001), and then read bits mask the corresponding address bits in the or write to the location of SSPxADD. SSPxADD register. For any SSPxMSK bits that are active (=0), the corresponding SSPxADD address bit To use 7-Bit Address Masking mode, it is necessary to is ignored (SSPxADD<n>=x). initialize SSPxMSK with a value before selecting the I2C Slave Addressing mode. Thus, the required Note: The two MSbs of the address are not sequence of events is: affected by address masking. 1. Select SSPxMSK Access mode (SSPxCON2<3:0> = 1001). 2. Write the mask value to the appropriate SSPxADD register address (FC8h for MSSP1, F6Eh for MSSP2). 3. Set the appropriate I2C Slave mode (SSPxCON2<3:0> = 0111 for 10-bit addressing, 0110 for 7-bit addressing). EXAMPLE 19-4: ADDRESS MASKING EXAMPLES IN 7-BIT MASKING MODE 7-Bit Addressing: SSPxADD<7:1>= 1010 000 SSPxMSK<7:1>= 1111 001 Addresses Acknowledged = ACh, A8h, A4h, A0h 10-Bit Addressing: SSPxADD<7:0> = 1010 0000 (The two MSbs are ignored in this example since they are not affected) SSPxMSK<7:0> = 1111 0011 Addresses Acknowledged = ACh, A8h, A4h, A0h DS39932D-page 298  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.5.3.5 Reception 19.5.3.6 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPxSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPxSTAT register is set. The received address is the SSPxBUF register and the SDAx line is held low loaded into the SSPxBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin SCLx is held low regard- less of SEN (see Section19.5.4 “Clock Stretching” When the address byte overflow condition exists, then for more details). By stretching the clock, the master the no Acknowledge (ACK) pulse is given. An overflow will be unable to assert another clock pulse until the condition is defined as either bit, BF (SSPxSTAT<0>), slave is done preparing the transmit data. The transmit is set or bit, SSPOV (SSPxCON1<6>), is set. data must be loaded into the SSPxBUF register, which An MSSP interrupt is generated for each data transfer also loads the SSPxSR register. Then, the SCLx pin byte. The interrupt flag bit, SSPxIF, must be cleared in should be enabled by setting bit, CKP software. The SSPxSTAT register is used to determine (SSPxCON1<4>). The eight data bits are shifted out on the status of the byte. the falling edge of the SCLx input. This ensures that the If SEN is enabled (SSPxCON2<0> = 1), SCLx will be SDAx signal is valid during the SCLx high time held low (clock stretch) following each data transfer. (Figure19-10). The clock must be released by setting bit, CKP The ACK pulse from the master-receiver is latched on (SSPxCON1<4>). See Section19.5.4 “Clock the rising edge of the ninth SCLx input pulse. If the Stretching” for more details. SDAx line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave monitors for another occurrence of the Start bit. If the SDAx line was low (ACK), the next trans- mit data must be loaded into the SSPxBUF register. Again, the SCLx pin must be enabled by setting bit, CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse.  2011 Microchip Technology Inc. DS39932D-page 299

PIC18F46J11 FAMILY FIGURE 19-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e eceiving D4 4 n softwarF is read R D6D5 23 Cleared iSSPxBU 7 D 1 = 0 ACK 9 W 8 R/ A1 7 2 )0 A 6 = ddress A3 5 n SEN A e Receiving A5A4 34 set to ‘’ wh0 e SDAxA7A6 SCLx12S SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP (SSPxCON1<4>) (CKP does not r DS39932D-page 300  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 19-9: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 D7 1 pt. u ACK 9 nterr D0 8 e an i s D1 7 au c d D2 6 an d e a 3 g at D 5 d D e e Receiving D7D6D5D4 1234 Cleared in softwarSSPxBUF is read or a ‘’).0 3.X.X will be Acknowl = 0 ACK 9 e a ‘’ 1 A5.X.A R/W 8 er b A6. Receiving Address SDAxA7A6A5XA3XX SCLx1234567S SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP (SSPxCON1<4>) (CKP does not reset to ‘’ when SEN = )00 Note1:x = Don’t care (i.e., address bit can eith 2:In this example, an address equal to A7.  2011 Microchip Technology Inc. DS39932D-page 301

PIC18F46J11 FAMILY FIGURE 19-10: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S ACK 9 PIF I S D0 8 m S o Data D1 7 Fr Transmitting D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software KP is set in software C D7 1 R ACK 9 PIF IS S D0 8 m S o 1 Fr D 7 a g Dat D2 6 ware Transmittin D6D5D4D3 2345 Cleared in software SSPBUF is written in soft ding CKP is set in software D7 1 SCL held lowwhile CPUresponds to SSPIF Clear by rea K C A 9 1 = W 8 R/ 1 A 7 2 ess A 6 Addr A3 5 g eivin A4 4 ec R A5 3 A6A7 12 Data in sampled >) 0>) 3 < < T 1 A R T DA CL S SPIF (PI F (SSPS KP S S S B C DS39932D-page 302  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 19-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 ACKD0D 891 nterrupt. Clock is held low untilupdate of SSPxADD has taken place Receive Data Byte ACKD7D6D5D4D3D1D2 891234576 Cleared in software Cleared by hardware whenSSPxADD is updated with highbyte of address X will be Acknowledged and cause an i by the bit masking. Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACKDAx11110A9A8A7A6A5XA3A2XX CLx1234567891234567S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPxADD needs to bewhen SSPxADD is updatedupdatedwith low byte of address UA is set indicating thatSSPxADD needs to beupdatedKP (SSPxCON1<4>) (CKP does not reset to ‘’ when SEN = )00 Note1:x = Don’t care (i.e., address bit can either be a ‘’ or a ‘’).10 2:In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X. 3:Note that the Most Significant bits of the address are not affected S S S B S U C  2011 Microchip Technology Inc. DS39932D-page 303

PIC18F46J11 FAMILY FIGURE 19-12: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 untilDD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPxADD is updated with highbyte of address d low SPxA D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACKDAx11110A9A8A7A6A5A4A3A2A1 CLx1234567891234567S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPxADD needs to bewhen SSPxADD is updatedupdatedwith low byte of address UA is set indicating thatSSPxADD needs to beupdatedKP (SSPxCON1<4>) (CKP does not reset to ‘’ when SEN = )00 S S S B S U C DS39932D-page 304  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 19-13: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCLx low w Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressTransmitting Data ByteR/W = 1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPxBUFWrite of SSPxBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPxADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPxADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with lowbyte of address UA is set indicating thatSSPxADD needs to beupdated R/ 8 h be Receive First Byte of Address DAx11110A9A8 CLx1234567S SPxIF (PIR1<3> or PIR3<7>) F (SSPxSTAT<0>) SSPxBUF is written witcontents of SSPxSR A (SSPxSTAT<1>) UA is set indicating thatthe SSPxADD needs to updated KP (SSPxCON1<4>) S S S B U C  2011 Microchip Technology Inc. DS39932D-page 305

PIC18F46J11 FAMILY 19.5.4 CLOCK STRETCHING 19.5.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The 7-Bit Slave Transmit mode implements clock The SEN bit (SSPxCON2<0>) allows clock stretching stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data regardless of the state of the SEN bit. receive sequence. The user’s Interrupt Service Routine (ISR) must set the CKP bit before transmission is allowed to continue. 19.5.4.1 Clock Stretching for 7-Bit Slave By holding the SCLx line low, the user has time to Receive Mode (SEN = 1) service the ISR and load the contents of the SSPxBUF In 7-Bit Slave Receive mode, on the falling edge of the before the master device can initiate another transmit ninth clock at the end of the ACK sequence, if the BF sequence (see Figure19-10). bit is set, the CKP bit in the SSPxCON1 register is Note1: If the user loads the contents of automatically cleared, forcing the SCLx output to be SSPxBUF, setting the BF bit before the held low. The CKP bit being cleared to ‘0’ will assert falling edge of the ninth clock, the CKP bit the SCLx line low. The CKP bit must be set in the will not be cleared and clock stretching user’s ISR before reception is allowed to continue. By will not occur. holding the SCLx line low, the user has time to service 2: The CKP bit can be set in software the ISR and read the contents of the SSPxBUF before regardless of the state of the BF bit. the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure19-15). 19.5.4.4 Clock Stretching for 10-Bit Slave Transmit Mode Note1: If the user reads the contents of the SSPxBUF before the falling edge of the In 10-Bit Slave Transmit mode, clock stretching is ninth clock, thus clearing the BF bit, the controlled during the first two address sequences by CKP bit will not be cleared and clock the state of the UA bit, just as it is in 10-Bit Slave stretching will not occur. Receive mode. The first two addresses are followed by a third address sequence, which contains the 2: The CKP bit can be set in software high-order bits of the 10-bit address and the R/W bit regardless of the state of the BF bit. The set to ‘1’. After the third address sequence is user should be careful to clear the BF bit performed, the UA bit is not set, the module is now in the ISR before the next receive configured in Transmit mode and clock stretching is sequence in order to prevent an overflow controlled by the BF flag as in 7-Bit Slave Transmit condition. mode (see Figure19-13). 19.5.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPxADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPxADD register before the falling edge of the ninth clock occurs, and if the user has not cleared the BF bit by reading the SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39932D-page 306  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.5.4.5 Clock Synchronization and CKP bit already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other When the CKP bit is cleared, the SCLx output is forced devices on the I2C bus have deasserted SCLx. This to ‘0’. However, clearing the CKP bit will not assert the ensures that a write to the CKP bit will not violate the SCLx output low until the SCLx output is already minimum high time requirement for SCLx (see sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has Figure19-14). FIGURE 19-14: CLOCK SYNCHRONIZATION TIMING Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 SDAx DX DX – 1 SCLx Master device CKP asserts clock Master device deasserts clock WR SSPxCON1  2011 Microchip Technology Inc. DS39932D-page 307

PIC18F46J11 FAMILY FIGURE 19-15: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R D5 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPxBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 >) A6 2 R3<7 >) A7 1 > or PI 0>) ON1<6 1<4>) DAx CLxS SPxIF (PIR1<3 F (SSPxSTAT< SPOV (SSPxC KP (SSPxCON S S S B S C DS39932D-page 308  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 19-16: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) Clock is not held lowbecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D 8 1 D 7 e Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared in softwareCleared in softwar Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPxADD register beforethe falling edge of the ninth clock will have noeffect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 DAx11110A9A8A7A6A5A4A3A2A1A0ACK CLx12345678912345678S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardware whenthe SSPxADD needs to beSSPxADD is updated with lowupdatedbyte of address after falling edgeof ninth clock UA is set indicating thatSSPxADD needs to beupdated KP (SSPxCON1<4>)Note:An update of the SSPxADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. S S S B S U C  2011 Microchip Technology Inc. DS39932D-page 309

PIC18F46J11 FAMILY 19.5.5 GENERAL CALL ADDRESS If the general call address matches, the SSPxSR is SUPPORT transferred to the SSPxBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the The addressing procedure for the I2C bus is such that SSPxIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the the master. The exception is the general call address interrupt can be checked by reading the contents of the which can address all devices. When this address is SSPxBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device-specific or a general call address. Acknowledge. In 10-bit mode, the SSPxADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit is set (SSPxSTAT<1>). If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second The general call address is recognized when the half of the address is not necessary, the UA bit will not General Call Enable bit, GCEN, is enabled be set and the slave will begin receiving data after the (SSPxCON2<7> set). Following a Start bit detect, 8 bits Acknowledge (Figure19-17). are shifted into the SSPxSR and the address is compared against the SSPxADD. It is also compared to the general call address and fixed in hardware. FIGURE 19-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7-BIT OR 10-BIT ADDRESSING MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK General Call Address SDAx ACK D7 D6 D5 D4 D3 D2 D1 D0 SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPxIF BF (SSPxSTAT<0>) Cleared in software SSPxBUF is read SSPOV (SSPxCON1<6>) ‘0’ GCEN (SSPxCON2<7>) ‘1’ 19.5.6 MASTER MODE Once Master mode is enabled, the user has six options. Master mode is enabled by setting and clearing the 1. Assert a Start condition on SDAx and SCLx. appropriate SSPM bits in SSPxCON1 and by setting 2. Assert a Repeated Start condition on SDAx and the SSPEN bit. In Master mode, the SCLx and SDAx SCLx. lines are manipulated by the MSSP hardware if the TRIS bits are set. 3. Write to the SSPxBUF register initiating transmission of data/address. Master mode of operation is supported by interrupt 4. Configure the I2C port to receive data. generation on the detection of the Start and Stop con- 5. Generate an Acknowledge condition at the end ditions. The Start (S) and Stop (P) bits are cleared from of a received byte of data. a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the Stop bit is set, or 6. Generate a Stop condition on SDAx and SCLx. the bus is Idle, with both the Start and Stop bits clear. In Firmware Controlled Master mode, user code conducts all I2C bus operations based on Start and Stop bit conditions. DS39932D-page 310  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY The following events will cause the MSSP Interrupt Note: The MSSP module, when configured in I2C Master mode, does not allow queueing Flag bit, SSPxIF, to be set (and MSSP interrupt, if enabled): of events. For instance, the user is not allowed to initiate a Start condition and • Start condition immediately write the SSPxBUF register • Stop condition to initiate transmission before the Start • Data transfer byte transmitted/received condition is complete. In this case, the • Acknowledge transmitted SSPxBUF will not be written to and the • Repeated Start WCOL bit will be set, indicating that a write to the SSPxBUF did not occur. FIGURE 19-18: MSSPx BLOCK DIAGRAM (I2C™ MASTER MODE) Internal SSPM<3:0> Data Bus SSPxADD<6:0> Read Write SSPxBUF Baud Rate Generator SDAx Shift SDAx In Clock ct e SSPxSR Detce) MSb LSb L ur e Oo abl WCk s SCLx Receive En StAarcGtk bneiont,we Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCLx In Write Collision Detect Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1) Clock Arbitration Set SSPxIF, BCLxIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPxCON2) End of XMIT/RCV 19.5.6.1 I2C Master Mode Operation In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device The master device generates all of the serial clock (7bits) and the R/W bit. In this case, the R/W bit will be pulses and the Start and Stop conditions. A transfer is logic ‘1’. Thus, the first byte transmitted is a 7-bit slave ended with a Stop condition or with a Repeated Start address, followed by a ‘1’ to indicate the receive bit. condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will Serial data is received via SDAx, while SCLx outputs the serial clock. Serial data is received 8 bits at a time. not be released. After each byte is received, an Acknowledge bit is In Master Transmitter mode, serial data is output transmitted. S and P conditions indicate the beginning through SDAx while SCLx outputs the serial clock. The and end of transmission. first byte transmitted contains the slave address of the The BRG, used for the SPI mode operation, is used to receiving device (7 bits) and the Read/Write (R/W) bit. set the SCLx clock frequency for either 100kHz, In this case, the R/W bit will be logic ‘0’. Serial data is 400kHz or 1MHz I2C operation. See Section19.5.7 transmitted 8 bits at a time. After each byte is transmit- “Baud Rate” for more details. ted, an Acknowledge bit is received. S and P conditions are output to indicate the beginning and the end of a serial transfer.  2011 Microchip Technology Inc. DS39932D-page 311

PIC18F46J11 FAMILY A typical transmit sequence would go as follows: 19.5.7 BAUD RATE 1. The user generates a Start condition by setting In I2C Master mode, the BRG reload value is placed in the Start Enable bit, SEN (SSPxCON2<0>). the lower seven bits of the SSPxADD register 2. SSPxIF is set. The MSSP module will wait for (Figure19-19). When a write occurs to SSPxBUF, the the required start time before any other Baud Rate Generator will automatically begin counting. operation takes place. The BRG counts down to 0 and stops until another 3. The user loads the SSPxBUF with the slave reload has taken place. The BRG count is decre- address to transmit. mented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded 4. Address is shifted out of the SDAx pin until all automatically. 8bits are transmitted. 5. The MSSP module shifts in the ACK bit from the Once the given operation is complete (i.e., transmis- slave device and writes its value into the sion of the last data bit is followed by ACK), the internal SSPxCON2 register (SSPxCON2<6>). clock will automatically stop counting and the SCLx pin will remain in its last state. 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the Table19-3 demonstrates clock rates based on SSPxIF bit. instruction cycles and the BRG value loaded into 7. The user loads the SSPxBUF with 8 bits of data. SSPxADD. The SSPADD BRG value of 0x00 is not supported. 8. Data is shifted out the SDAx pin until all 8 bits are transmitted. 9. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPxCON2 register (SSPxCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPxCON2<2>). 12. Interrupt is generated once the Stop condition is complete. DS39932D-page 312  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.5.7.1 Baud Rate and Module Because this mode derives its basic clock source from Interdependence the system clock, any changes to the clock will affect both modules in the same proportion. It may be Because MSSP1 and MSSP2 are independent, they possible to change one or both baud rates back to a can operate simultaneously in I2C Master mode at previous value by changing the BRG reload value. different baud rates. This is done by using different BRG reload values for each module. FIGURE 19-19: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPxADD<6:0> SSPM<3:0> Reload Reload SCLx Control CLKO BRG Down Counter FOSC/4 TABLE 19-3: I2C™ CLOCK RATE w/BRG FSCL FOSC FCY FCY * 2 BRG Value (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 18h 400 kHz(1) 40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 20 MHz 63h 100 kHz 16 MHz 4 MHz 8 MHz 09h 400 kHz(1) 16 MHz 4 MHz 8 MHz 0Ch 308 kHz 16 MHz 4 MHz 8 MHz 27h 100 kHz 4 MHz 1 MHz 2 MHz 02h 333 kHz(1) 4 MHz 1 MHz 2 MHz 09h 100 kHz 16 MHz 4 MHz 8 MHz 03h 1 MHz(1) Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application.  2011 Microchip Technology Inc. DS39932D-page 313

PIC18F46J11 FAMILY 19.5.7.2 Clock Arbitration sampled high. When the SCLx pin is sampled high, the BRG is reloaded with the contents of SSPxADD<6:0> Clock arbitration occurs when the master, during any and begins counting. This ensures that the SCLx high receive, transmit or Repeated Start/Stop condition, time will always be at least one BRG rollover count in deasserts the SCLx pin (SCLx allowed to float high). the event that the clock is held low by an external When the SCLx pin is allowed to float high, the BRG is device (Figure19-20). suspended from counting until the SCLx pin is actually FIGURE 19-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX DX – 1 SCLx deasserted but slave holds SCLx allowed to transition high SCLx low (clock arbitration) SCLx BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCLx is sampled high, reload takes place and BRG starts its count BRG Reload 19.5.8 I2C MASTER MODE START Note: If, at the beginning of the Start condition, CONDITION TIMING the SDAx and SCLx pins are already sam- To initiate a Start condition, the user sets the Start pled low or if during the Start condition, the Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx line is sampled low, before the SDAx SCLx pins are sampled high, the BRG is reloaded with line is driven low, a bus collision occurs, the the contents of SSPxADD<6:0> and starts its count. If Bus Collision Interrupt Flag, BCLxIF, is set, SCLx and SDAx are both sampled high when the Baud the Start condition is aborted and the I2C Rate Generator times out (TBRG), the SDAx pin is module is reset into its Idle state. driven low. The action of the SDAx being driven low 19.5.8.1 WCOL Status Flag while SCLx is high is the Start condition and causes the Start bit (SSPxSTAT<3>) to be set. Following this, the If the user writes the SSPxBUF when a Start sequence BRG is reloaded with the contents of SSPxADD<6:0> is in progress, the WCOL bit is set and the contents of and resumes its count. When the BRG times out the buffer are unchanged (the write does not occur). (TBRG), the SEN bit (SSPxCON2<0>) will be Note: Because queueing of events is not automatically cleared by hardware. The BRG is allowed, writing to the lower five bits of suspended, leaving the SDAx line held low and the Start SSPxCON2 is disabled until the Start condition is complete. condition is complete. FIGURE 19-21: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPxSTAT<3>) SDAx = 1, At completion of Start bit, SCLx = 1 hardware clears SEN bit and sets SSPxIF bit TBRG TBRG Write to SSPxBUF occurs here 1st bit 2nd bit SDAx TBRG SCLx TBRG S DS39932D-page 314  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.5.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPxCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDAx is sampled low when SCLx the SCLx pin is asserted low. When the SCLx pin is goes from low-to-high. sampled low, the BRG is loaded with the contents of SSPxADD<5:0> and begins counting. The SDAx pin is • SCLx goes low before SDAx is released (brought high) for one BRG count (TBRG). asserted low. This may indicate that When the BRG times out, and if SDAx is sampled high, another master is attempting to the SCLx pin will be deasserted (brought high). When transmit a data ‘1’. SCLx is sampled high, the BRG is reloaded with the Immediately following the SSPxIF bit getting set, the contents of SSPxADD<6:0> and begins counting. user may write the SSPxBUF with the 7-bit address in SDAx and SCLx must be sampled high for one TBRG. 7-bit mode, or the default first address in 10-bit mode. This action is then followed by assertion of the SDAx After the first eight bits are transmitted and an ACK is pin (SDAx = 0) for one TBRG while SCLx is high. received, the user may then transmit an additional 8 bits Following this, the RSEN bit (SSPxCON2<1>) will be of address (10-bit mode) or 8 bits of data (7-bit mode). automatically cleared and the BRG will not be reloaded, leaving the SDAx pin held low. As soon as a 19.5.9.1 WCOL Status Flag Start condition is detected on the SDAx and SCLx pins, the Start bit (SSPxSTAT<3>) will be set. The SSPxIF bit If the user writes the SSPxBUF when a Repeated Start will not be set until the BRG has timed out. sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Note: Because queueing of events is not allowed, writing of the lower five bits of SSPxCON2 is disabled until the Repeated Start condition is complete. FIGURE 19-22: REPEATED START CONDITION WAVEFORM S bit set by hardware SDAx = 1, At completion of Start bit, Write to SSPxCON2 occurs here:SDAx = 1, SCLx = 1 hardware clears RSEN bit SCLx (no change). and sets SSPxIF TBRG TBRG TBRG SDAx 1st bit RSEN bit set by hardware on falling edge of ninth clock, Write to SSPxBUF occurs here end of XMIT TBRG SCLx TBRG Sr = Repeated Start  2011 Microchip Technology Inc. DS39932D-page 315

PIC18F46J11 FAMILY 19.5.10 I2C MASTER MODE The user should verify that the WCOL bit is clear after TRANSMISSION each write to SSPxBUF to ensure the transfer is correct. In all cases, WCOL must be cleared in software. Transmission of a data byte, a 7-bit address or the other half of a 10-bit address, is accomplished by 19.5.10.3 ACKSTAT Status Flag simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the In Transmit mode, the ACKSTAT bit (SSPxCON2<6>) BRG to begin counting and start the next transmission. is cleared when the slave has sent an Acknowledge Each bit of address/data will be shifted out onto the (ACK=0) and is set when the slave does not Acknowl- SDAx pin after the falling edge of SCLx is asserted (see edge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), data hold time specification parameter106). SCLx is held low for one BRG rollover count (TBRG). Data or when the slave has properly received its data. should be valid before SCLx is released high (see data 19.5.11 I2C MASTER MODE RECEPTION setup time specification parameter 107). When the SCLx pin is released high, it is held that way for TBRG. Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPxCON2<3>). The data on the SDAx pin must remain stable for that duration and some hold time after the next falling edge Note: The MSSP module must be in an inactive of SCLx. After the eighth bit is shifted out (the falling state before the RCEN bit is set or the edge of the eighth clock), the BF flag is cleared and the RCEN bit will be disregarded. master releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the The BRG begins counting and on each rollover, the ninth bit time if an address match occurred, or if data state of the SCLx pin changes (high-to-low/low-to-high) was received properly. The status of ACK is written into and data is shifted into the SSPxSR. After the falling the ACKDT bit on the falling edge of the ninth clock. edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are If the master receives an Acknowledge, the Acknowl- loaded into the SSPxBUF, the BF flag bit is set, the edge Status bit, ACKSTAT, is cleared; if not, the bit is SSPxIF flag bit is set and the BRG is suspended from set. After the ninth clock, the SSPxIF bit is set and the counting, holding SCLx low. The MSSP is now in Idle master clock (BRG) is suspended until the next data state awaiting the next command. When the buffer is byte is loaded into the SSPxBUF, leaving SCLx low and read by the CPU, the BF flag bit is automatically SDAx unchanged (Figure19-23). cleared. The user can then send an Acknowledge bit at After the write to the SSPxBUF, each bit of the address the end of reception by setting the Acknowledge will be shifted out on the falling edge of SCLx until all Sequence Enable bit, ACKEN (SSPxCON2<4>). seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will 19.5.11.1 BF Status Flag deassert the SDAx pin, allowing the slave to respond In receive operation, the BF bit is set when an address with an Acknowledge. On the falling edge of the ninth or data byte is loaded into SSPxBUF from SSPxSR. It clock, the master will sample the SDAx pin to see if the is cleared when the SSPxBUF register is read. address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit 19.5.11.2 SSPOV Status Flag (SSPxCON2<6>). Following the falling edge of the In receive operation, the SSPOV bit is set when 8 bits ninth clock transmission of the address, the SSPxIF are received into the SSPxSR and the BF flag bit is flag is set, the BF flag is cleared and the BRG is turned already set from a previous reception. off until another write to the SSPxBUF takes place, holding SCLx low and allowing SDAx to float. 19.5.11.3 WCOL Status Flag 19.5.10.1 BF Status Flag If users write the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), In Transmit mode, the BF bit (SSPxSTAT<0>) is set the WCOL bit is set and the contents of the buffer are when the CPU writes to SSPxBUF and is cleared when unchanged (the write does not occur). all eight bits are shifted out. 19.5.10.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur) after 2TCY after the SSPxBUF write. If SSPxBUF is rewritten within 2 TCY, the WCOL bit is set and SSPxBUF is updated. This may result in a corrupted transfer. DS39932D-page 316  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 19-23: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7-BIT OR 10-BIT ADDRESS) 1 AT in ON2 = oftware STxC P n s ACKSSP ared i K e >) AC 9 Cl 6 N2< D0 8 e slave, clear ACKSTAT bit (SSPxCO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared in software service routinfrom MSSP interrupt SSPxBUF is written in software om D7 1 xIF Fr ow SP = 0 SCLx held lwhile CPUsponds to S CK re = 0 A W, 9 are R/W A1 ess and R/ 78 d by hardw ave A2 addr 6 eare PxCON2<0> (SEN = ),1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPxBUF written with 7-bit start transmit 12345 Cleared in software SSPxBUF written After Start condition, SEN cl Sn Write SStart co S T<0>) A T S x F SP SDAx SCLx SSPxI BF (S SEN PEN R/W  2011 Microchip Technology Inc. DS39932D-page 317

PIC18F46J11 FAMILY FIGURE 19-24: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) e et ACKEN, start Acknowledge sequence,DAx = ACKDT = 1 PEN bit = 1N clearedwritten herematically D0ACK Bus masterACK is not sentterminatestransfer98PSet SSPxIF at endof receiveSet SSPxIF interruptat end of Acknowledgsequence Set P bit (SSPxSTAT<4>)Cleared insoftwareand SSPxIF SSPOV is set becauseSSPxBUF is still full SS RCEauto D1 7 CLK Write to SSPxCON2<4>to start Acknowledge sequence,SDAx = ACKDT (SSPxCON2<5>) = 0 ACK from master,er configured as a receiverSDAx = ACKDT = 0ogramming SSPxCON2<3> (RCEN = )1 RCEN = , start1RCEN clearednext receiveautomatically Receiving Data from SlaveReceiving Data from SlaveACKD2D5D2D5D3D4D6D7D3D4D6D7D1D0 678956512343124 Data shifted in on falling edge of Set SSPxIF interruptSet SSPxIF interruptat end of receiveat end of Acknowledgesequence Cleared in softwareCleared in softwareCleared in software Last bit is shifted into SSPxSR andcontents are unloaded into SSPxBUF Mastby pr ACK from Slave R/W = 1A1ACK 798 e, Write to SSPxCON2<0> (SEN = ),1begin Start condition SEN = 0Write to SSPxBUF occurs herstart XMIT Transmit Address to Slave A7A6A5A4A3A2SDAx 361245SCLxS SSPxIF Cleared in softwareSDAx = , SCLx = ,01while CPU responds to SSPxIF BF (SSPxSTAT<0>) SSPOV ACKEN DS39932D-page 318  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.5.12 ACKNOWLEDGE SEQUENCE 19.5.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDAx pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPxCON2<2>). At the end of a (SSPxCON2<4>). When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDAx pin. If the user wishes to the master will assert the SDAx line low. When the generate an Acknowledge, then the ACKDT bit should SDAx line is sampled low, the BRG is reloaded and be cleared. If not, the user should set the ACKDT bit counts down to 0. When the BRG times out, the SCLx before starting an Acknowledge sequence. The BRG pin will be brought high and one Baud Rate Generator then counts for one rollover period (TBRG) and the SCLx rollover count (TBRG) later, the SDAx pin will be deas- pin is deasserted (pulled high). When the SCLx pin is serted. When the SDAx pin is sampled high while SCLx sampled high (clock arbitration), the BRG counts for is high, the Stop bit (SSPxSTAT<4>) is set. A TBRG TBRG; the SCLx pin is then pulled low. Following this, the later, the PEN bit is cleared and the SSPxIF bit is set ACKEN bit is automatically cleared, the BRG is turned (Figure19-26). off and the MSSP module then goes into an inactive 19.5.13.1 WCOL Status Flag state (Figure19-25). If the user writes the SSPxBUF when a Stop sequence 19.5.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the If the user writes the SSPxBUF when an Acknowledge contents of the buffer are unchanged (the write does sequence is in progress, then WCOL is set and the not occur). contents of the buffer are unchanged (the write does not occur). FIGURE 19-25: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPxCON2, ACKEN = 1, ACKDT = 0 TBRG TBRG SDAx D0 ACK SCLx 8 9 SSPxIF Cleared in SSPxIF set at Cleared in software the end of receive software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 19-26: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPxCON2, SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG set PEN after SDAx sampled high. P bit (SSPxSTAT<4>) is set Falling edge of PEN bit (SSPxCON2<2>) is cleared by 9th clock hardware and the SSPxIF bit is set TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period.  2011 Microchip Technology Inc. DS39932D-page 319

PIC18F46J11 FAMILY 19.5.14 SLEEP OPERATION puts a ‘1’ on SDAx, by letting SDAx float high and While in Sleep mode, the I2C module can receive another master asserts a ‘0’. When the SCLx pin floats high, data should be stable. If the expected data on addresses or data and when an address match or SDAx is a ‘1’ and the data sampled on the SDAx pin=0, complete byte transfer occurs, wake the processor then a bus collision has taken place. The master will set from Sleep (if the MSSP interrupt is enabled). the Bus Collision Interrupt Flag, BCLxIF, and reset the 19.5.15 EFFECTS OF A RESET I2C port to its Idle state (Figure19-27). If a transmit was in progress when the bus collision A Reset disables the MSSP module and terminates the occurred, the transmission is halted, the BF flag is current transfer. cleared, the SDAx and SCLx lines are deasserted and 19.5.16 MULTI-MASTER MODE the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C In Multi-Master mode, the interrupt generation on the bus is free, the user can resume communication by detection of the Start and Stop conditions allows the asserting a Start condition. determination of when the bus is free. The Start and Stop bits are cleared from a Reset or when the MSSP If a Start, Repeated Start, Stop or Acknowledge condition module is disabled. Control of the I2C bus may be taken was in progress when the bus collision occurred, the con- when the P bit (SSPxSTAT<4>) is set, or the bus is Idle, dition is aborted, the SDAx and SCLx lines are with both the Start and Stop bits clear. When the bus is deasserted and the respective control bits in the busy, enabling the MSSP interrupt will generate the SSPxCON2 register are cleared. When the user services interrupt when the Stop condition occurs. the bus collision Interrupt Service Routine (ISR), and if the I2C bus is free, the user can resume communication In multi-master operation, the SDAx line must be by asserting a Start condition. monitored for arbitration to see if the signal level is the The master will continue to monitor the SDAx and SCLx expected output level. This check is performed in hardware with the result placed in the BCLxIF bit. pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of The states where arbitration can be lost are: data at the first data bit regardless of where the • Address Transfer transmitter left off when the bus collision occurred. • Data Transfer In Multi-Master mode, the interrupt generation on the • A Start Condition detection of Start and Stop conditions allows the deter- • A Repeated Start Condition mination of when the bus is free. Control of the I2C bus • An Acknowledge Condition can be taken when the Stop bit is set in the SSPxSTAT register, or the bus is Idle and the Start and Stop bits 19.5.17 MULTI -MASTER are cleared. COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master out- FIGURE 19-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDAx. While SCLx is high, Data changes SDAx line pulled low data doesn’t match what is driven while SCLx = 0 by another source by the master; bus collision has occurred SDAx released by master SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF DS39932D-page 320  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.5.17.1 Bus Collision During a Start If the SDAx pin is sampled low during this count, the Condition BRG is reset and the SDAx line is asserted early (Figure19-30). If, however, a ‘1’ is sampled on the During a Start condition, a bus collision occurs if: SDAx pin, the SDAx pin is asserted low at the end of a) SDAx or SCLx is sampled low at the beginning the BRG count. The BRG is then reloaded and counts of the Start condition (Figure19-28). down to 0. If the SCLx pin is sampled as ‘0’ during this b) SCLx is sampled low before SDAx is asserted time, a bus collision does not occur. At the end of the low (Figure19-29). BRG count, the SCLx pin is asserted low. During a Start condition, both the SDAx and the SCLx Note: The reason that bus collision is not a fac- pins are monitored. tor during a Start condition is that no two bus masters can assert a Start condition If the SDAx pin is already low, or the SCLx pin is at the exact same time. Therefore, one already low, then all of the following occur: master will always assert SDAx before the • The Start condition is aborted other. This condition does not cause a bus • The BCLxIF flag is set collision because the two masters must be • The MSSP module is reset to its inactive state allowed to arbitrate the first address (Figure19-28) following the Start condition. If the address The Start condition begins with the SDAx and SCLx is the same, arbitration must be allowed to pins deasserted. When the SDAx pin is sampled high, continue into the data portion, Repeated the BRG is loaded from SSPxADD<6:0> and counts Start or Stop conditions. down to 0. If the SCLx pin is sampled low while SDAx is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 19-28: BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDAx = 1, SCLx = 1 MSSPx module reset into Idle state. SEN SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because BCLxIF SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared in software S SSPxIF SSPxIF and BCLxIF are cleared in software  2011 Microchip Technology Inc. DS39932D-page 321

PIC18F46J11 FAMILY FIGURE 19-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start SCLx sequence if SDAx = 1, SCLx = 1 SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared in software S ‘0’ ‘0’ SSPxIF ‘0’ ‘0’ FIGURE 19-30: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Set SSPxIF Less than TBRG TBRG SDAx SDAx pulled low by other master. Reset BRG and assert SDAx. SCLx S SCLx pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 BCLxIF ‘0’ S SSPxIF SDAx = 0, SCLx = 1, Interrupts cleared set SSPxIF in software DS39932D-page 322  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 19.5.17.2 Bus Collision During a Repeated If SDAx is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, see Figure19-31). If SDAx is sampled high, the BRG is During a Repeated Start condition, a bus collision reloaded and begins counting. If SDAx goes from occurs if: high-to-low before the BRG times out, no bus collision a) A low level is sampled on SDAx when SCLx occurs because no two masters can assert SDAx at goes from a low level to a high level. exactly the same time. b) SCLx goes low before SDAx is asserted low, If SCLx goes from high-to-low before the BRG times indicating that another master is attempting to out and SDAx has not already been asserted, a bus transmit a data ‘1’. collision occurs. In this case, another master is When the user deasserts SDAx and the pin is allowed attempting to transmit a data ‘1’ during the Repeated to float high, the BRG is loaded with SSPxADD<6:0> Start condition (see Figure19-32). and counts down to 0. The SCLx pin is then deasserted If, at the end of the BRG time-out, both SCLx and SDAx and when sampled high, the SDAx pin is sampled. are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. FIGURE 19-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared in software S ‘0’ SSPxIF ‘0’ FIGURE 19-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx SCLx goes low before SDAx, BCLxIF set BCLxIF. Release SDAx and SCLx. Interrupt cleared in software RSEN S ‘0’ SSPxIF  2011 Microchip Technology Inc. DS39932D-page 323

PIC18F46J11 FAMILY 19.5.17.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low. Condition When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the BRG is loaded with SSPxADD<6:0> and counts a) After the SDAx pin has been deasserted and down to 0. After the BRG times out, SDAx is sampled. If allowed to float high, SDAx is sampled low after SDAx is sampled low, a bus collision has occurred. This the BRG has timed out. is due to another master attempting to drive a data ‘0’ b) After the SCLx pin is deasserted, SCLx is (Figure19-33). If the SCLx pin is sampled low before sampled low before SDAx goes high. SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure19-34). FIGURE 19-33: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDAx sampled low after TBRG, set BCLxIF SDAx SDAx asserted low SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ FIGURE 19-34: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes low before SDAx goes high, Assert SDAx set BCLxIF SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ DS39932D-page 324  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 19-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PMPIF(3) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE(3) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP(3) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72 PIR2 OSCFIF CM2IF CM1IF — BCL1IF LVDIF TMR3IF CCP2IF 72 PIE2 OSCFIE CM2IE CM1IE — BCL1IE LVDIE TMR3IE CCP2IE 72 IPR2 OSCFIP CM2IP CM1IP — BCL1IP LVDIP TMR3IP CCP2IP 72 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCIF 72 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCIE 72 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCIP 72 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 72 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 72 SSP1BUF MSSP1 Receive Buffer/Transmit Register 70 SSPxADD MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) 70, 73 SSPxMSK(1) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 70, 73 SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 70, 73 SSPxCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 70, 73 GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN SSPxSTAT SMP CKE D/A P S R/W UA BF 70, 73 SSP2BUF MSSP2 Receive Buffer/Transmit Register 73 SSP2ADD MSSP2 Address Register (I2C Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) 73 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSPx module in I2C™ mode. Note 1: SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I2C Slave mode operations in 7-Bit Masking mode. See Section19.5.3.4 “7-Bit Address Masking Mode” for more details. 2: Alternate bit definitions for use in I2C Slave mode operations only. 3: These bits are only available on 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 325

PIC18F46J11 FAMILY NOTES: DS39932D-page 326  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 20.0 ENHANCED UNIVERSAL The pins of EUSART1 and EUSART2 are multiplexed SYNCHRONOUS with the functions of PORTC (RC6/PMA5/TX1/CK1/RP17 and RC7/PMA4/RX1/DT1/RP18) and remapped ASYNCHRONOUS RECEIVER (RPn1/TX2/CK2 and RPn2/RX2/DT2), respectively. In TRANSMITTER (EUSART) order to configure these pins as an EUSART: The Enhanced Universal Synchronous Asynchronous • For EUSART1: Receiver Transmitter (EUSART) module is one of two - SPEN bit (RCSTA1<7>) must be set (= 1) serial I/O modules. (Generically, the EUSART is also - TRISC<7> bit must be set (= 1) known as a Serial Communications Interface or SCI.) - TRISC<6> bit must be cleared (= 0) for The EUSART can be configured as a full-duplex Asynchronous and Synchronous Master asynchronous system that can communicate with modes peripheral devices, such as CRT terminals and - TRISC<6> bit must be set (= 1) for personal computers. It can also be configured as a Synchronous Slave mode half-duplex synchronous system that can communicate • For EUSART2: with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs and so on. - SPEN bit (RCSTA2<7>) must be set (= 1) - TRIS bit for RPn2/RX2/DT2 = 1 The Enhanced USART module implements additional features, including automatic baud rate detection and - TRIS bit for RPn1/TX2/CK2 = 0 for calibration, automatic wake-up on Sync Break recep- Asynchronous and Synchronous Master tion and 12-bit Break character transmit. These make it modes ideally suited for use in Local Interconnect Network bus - TRISC<6> bit must be set (= 1) for (LIN/J2602 bus) systems. Synchronous Slave mode All members of the PIC18F46J11 family are equipped Note: The EUSART control will automatically with two independent EUSART modules, referred to as reconfigure the pin from input to output as EUSART1 and EUSART2. They can be configured in needed. the following modes: The TXx/CKx I/O pins have an optional open-drain • Asynchronous (full-duplex) with: output capability. By default, when this pin is used by - Auto-wake-up on character reception the EUSART as an output, it will function as a standard push-pull CMOS output. The TXx/CKx I/O pins’ - Auto-baud calibration open-drain, output feature can be enabled by setting - 12-bit Break character transmission the corresponding UxOD bit in the ODCON2 register. • Synchronous – Master (half-duplex) with For more details, see Section19.3.3 “Open-Drain selectable clock polarity Output Option”. • Synchronous – Slave (half-duplex) with selectable The operation of each Enhanced USART module is clock polarity controlled through three registers: • Transmit Status and Control (TXSTAx) • Receive Status and Control (RCSTAx) • Baud Rate Control (BAUDCONx) These are covered in detail in Register20-1, Register20-2 and Register20-3, respectively. Note: Throughout this section, references to register and bit names that may be asso- ciated with a specific EUSART module are referred to generically by the use of ‘x’ in place of the specific module number. Thus, “RCSTAx” might refer to the Receive Status register for either EUSART1 or EUSART2.  2011 Microchip Technology Inc. DS39932D-page 327

PIC18F46J11 FAMILY REGISTER 20-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER (ACCESS FADh/FA8h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit is enabled and the TXX/CKX pin is configured as an output 0 = Transmit is disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39932D-page 328  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 20-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER (ACCESS FACh/F9Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-Bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-Bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be cleared by reading RCREGx register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN). UART reception will be discarded until the overun error is cleared. 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.  2011 Microchip Technology Inc. DS39932D-page 329

PIC18F46J11 FAMILY REGISTER 20-3: BAUDCONx: BAUD RATE CONTROL REGISTER (ACCESS F7Eh/F7Ch) R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 RXDTP: Data/Receive Polarity Select bit Asynchronous mode: 1 = Receive data (RXx) is inverted (active-low) 0 = Receive data (RXx) is not inverted (active-high) Synchronous mode: 1 = Data (DTx) is inverted (active-low) 0 = Data (DTx) is not inverted (active-high) bit 4 TXCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TXx) is a low level 0 = Idle state for transmit (TXx) is a high level Synchronous mode: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator – SPBRGx only (Compatible mode), SPBRGHx value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RXx pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character; requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39932D-page 330  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 20.1 Baud Rate Generator (BRG) Writing a new value to the SPBRGHx:SPBRGx registers causes the BRG timer to be reset (or cleared). The BRG is a dedicated, 8-bit or 16-bit generator that This ensures the BRG does not wait for a timer supports both the Asynchronous and Synchronous overflow before outputting the new baud rate. modes of the EUSART. By default, the BRG operates When operated in the Synchronous mode, in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) SPBRGH:SPBRG values of 0000h and 0001h are not selects 16-bit mode. supported. In the Asynchronous mode, all BRG values The SPBRGHx:SPBRGx register pair controls the period may be used. of a free-running timer. In Asynchronous mode, bits, BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>), 20.1.1 OPERATION IN POWER-MANAGED also control the baud rate. In Synchronous mode, BRGH MODES is ignored. The device clock is used to generate the desired baud Table20-1 provides the formula for computation of the rate. When one of the power-managed modes is baud rate for different EUSART modes, which only apply entered, the new clock source may be operating at a in Master mode (internally generated clock). different frequency. This may require an adjustment to Given the desired baud rate and FOSC, the nearest the value in the SPBRGx register pair. integer value for the SPBRGHx:SPBRGx registers can 20.1.2 SAMPLING be calculated using the formulas in Table20-1. From this, the error in baud rate can be determined. An The data on the RXx pin (either example calculation is provided in Example20-1. RC7/PMA4/RX1/DT1/RP18 or RPn/RX2/DT2) is sam- Typical baud rates and error values for the various pled three times by a majority detect circuit to Asynchronous modes are provided in Table20-2. It determine if a high or a low level is present at the RXx may be advantageous to use the high baud rate pin. (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. TABLE 20-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous Baud Rate = FOSC/[64 (n + 1)] n = FOSC/[64* (Baud Rate)] -1 0 0 1 8-bit/Asynchronous Baud Rate = FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous n = FOSC/[16* (Baud Rate)] -1 0 1 1 16-bit/Asynchronous Baud Rate = FOSC/[4 (n + 1)] 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous n = FOSC/[4* (Baud Rate)] -1 Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair  2011 Microchip Technology Inc. DS39932D-page 331

PIC18F46J11 FAMILY EXAMPLE 20-1: CALCULATING BAUD RATE ERROR For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG: Desired Baud Rate = Fosc/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((Fosc/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate=16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 20-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page: TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 73 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 73 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 71 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39932D-page 332  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615. -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — —  2011 Microchip Technology Inc. DS39932D-page 333

PIC18F46J11 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — DS39932D-page 334  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 20.1.3 AUTO-BAUD RATE DETECT Note1: If the WUE bit is set with the ABDEN bit, The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on detection and calibration of baud rate. This feature is the byte following the Break character. active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the bit is clear. incoming character baud rate is within the The automatic baud rate measurement sequence range of the selected BRG clock source. (Figure20-1) begins whenever a Start bit is received Some combinations of oscillator and the ABDEN bit is set. The calculation is frequency and EUSART baud rates are self-averaging. not possible due to bit error rates. Overall system timing and communication baud In the Auto-Baud Rate Detect (ABD) mode, the clock to rates must be taken into consideration the BRG is reversed. Rather than the BRG clocking the when using the Auto-Baud Rate Detection incoming RXx signal, the RXx signal is timing the BRG. feature. In ABD mode, the internal BRG is used as a counter to time the bit period of the incoming serial byte stream. 3: To maximize the baud rate range, it is recommended to set the BRG16 bit if the Once the ABDEN bit is set, the state machine will clear auto-baud feature is used. the BRG and look for a Start bit. The ABD must receive a byte with the value, 55h (ASCII “U”, which is also the LIN/J2602 bus Sync character), in order to calculate the TABLE 20-4: BRG COUNTER proper bit rate. The measurement is taken over both a CLOCK RATES low and high bit time in order to minimize any effects BRG16 BRGH BRG Counter Clock caused by asymmetry of the incoming signal. After a Start bit, the SPBRGx begins counting up, using the pre- 0 0 FOSC/512 selected clock source on the first rising edge of RXx. 0 1 FOSC/128 After eight bits on the RXx pin or the fifth rising edge, an 1 0 FOSC/128 accumulated value totaling the proper BRG period is left in the SPBRGHx:SPBRGx register pair. Once the 5th 1 1 FOSC/32 edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. 20.1.3.1 ABD and EUSART Transmission If a rollover of the BRG occurs (an overflow from FFFFh Since the BRG clock is reversed during ABD acquisi- to 0000h), the event is trapped by the ABDOVF status tion, the EUSART transmitter cannot be used during bit (BAUDCONx<7>). It is set in hardware by BRG roll- ABD. This means that whenever the ABDEN bit is set, overs and can be set or cleared by the user in software. TXREGx cannot be written to. Users should also ABD mode remains active after rollover events and the ensure that ABDEN does not become set during a ABDEN bit remains set (Figure20-2). transmit sequence. Failing to do this may result in unpredictable EUSART operation. While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock can be configured by the BRG16 and BRGH bits. The BRG16 bit must be set to use both SPBRG1 and SPBRGH1 as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table20-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCxIF interrupt is set once the fifth rising edge on RXx is detected. The value in the RCREGx needs to be read to clear the RCxIF interrupt. The contents of RCREGx should be discarded.  2011 Microchip Technology Inc. DS39932D-page 335

PIC18F46J11 FAMILY FIGURE 20-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RXx pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE=0. FIGURE 20-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RXx pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h DS39932D-page 336  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 20.2 EUSART Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is The Asynchronous mode of operation is selected by empty and the TXxIF flag bit is set. This interrupt can be clearing the SYNC bit (TXSTAx<4>). In this mode, the enabled or disabled by setting or clearing the interrupt EUSART uses standard Non-Return-to-Zero (NRZ) enable bit, TXxIE. TXxIF will be set regardless of the format (one Start bit, eight or nine data bits and one Stop state of TXxIE; it cannot be cleared in software. TXxIF is bit). The most common data format is 8 bits. An on-chip also not cleared immediately upon loading TXREGx, but dedicated 8-bit/16-bit BRG can be used to derive becomes valid in the second instruction cycle following standard baud rate frequencies from the oscillator. the load instruction. Polling TXxIF immediately following The EUSART transmits and receives the LSb first. The a load of TXREGx will return invalid results. EUSART’s transmitter and receiver are functionally While TXxIF indicates the status of the TXREGx independent but use the same data format and baud rate. The BRG produces a clock, either x16 or x64 of the register; another bit, TRMT (TXSTAx<1>), shows the bit shift rate, depending on the BRGH and BRG16 bits status of the TSR register. TRMT is a read-only bit, (TXSTAx<2> and BAUDCONx<3>). Parity is not which is set when the TSR register is empty. No inter- supported by the hardware but can be implemented in rupt logic is tied to this bit so the user has to poll this bit software and stored as the ninth data bit. in order to determine if the TSR register is empty. When operating in Asynchronous mode, the EUSART Note1: The TSR register is not mapped in data module consists of the following important elements: memory, so it is not available to the user. • Baud Rate Generator 2: Flag bit, TXxIF, is set when enable bit, • Sampling Circuit TXEN, is set. • Asynchronous Transmitter To set up an Asynchronous Transmission: • Asynchronous Receiver 1. Initialize the SPBRGHx:SPBRGx registers for • Auto-Wake-up on Sync Break Character the appropriate baud rate. Set or clear the • 12-Bit Break Character Transmit BRGH and BRG16 bits, as required, to achieve • Auto-Baud Rate Detection the desired baud rate. 2. Enable the asynchronous serial port by clearing 20.2.1 EUSART ASYNCHRONOUS bit, SYNC, and setting bit, SPEN. TRANSMITTER 3. If interrupts are desired, set enable bit, TXxIE. Figure20-3 displays the EUSART transmitter block 4. If 9-bit transmission is desired, set transmit bit, diagram. TX9. Can be used as address/data bit. The heart of the transmitter is the Transmit (Serial) Shift 5. Enable the transmission by setting bit, TXEN, which will also set bit, TXxIF. Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREGx. The 6. If 9-bit transmission is selected, the ninth bit TXREGx register is loaded with data in software. The should be loaded in bit, TX9D. TSR register is not loaded until the Stop bit has been 7. Load data to the TXREGx register (starts transmitted from the previous load. As soon as the Stop transmission). bit is transmitted, the TSR is loaded with new data from 8. If using interrupts, ensure that the GIE and PEIE the TXREGx register (if available). bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb LSb (8)  0 Pin Buffer and Control TSR Register TXx pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGHx SPBRGx TX9 Baud Rate Generator TX9D  2011 Microchip Technology Inc. DS39932D-page 337

PIC18F46J11 FAMILY FIGURE 20-4: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 20-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXxIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 72 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 72 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 72 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 72 TXREGx EUSARTx Transmit Register 72 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 72 BAUDCONx ABDOVF RCIDL RXDTP TXDTP BRG16 — WUE ABDEN 73 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 ODCON2 — — — — U2OD U1OD 74 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: These bits are only available on 44-pin devices. DS39932D-page 338  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 20.2.2 EUSART ASYNCHRONOUS RECEIVER Note: If the receive FIFO is overrun, no addi- The receiver block diagram is displayed in Figure20-6. tional characters will be received until the overrun condition is cleared. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a 20.2.2.3 Setting Up Asynchronous Receive high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the To set up an Asynchronous Reception: bit rate or at FOSC. This mode would typically be used 1. Initialize the SPBRGHx:SPBRGx registers for in RS-232 systems. the appropriate baud rate. Set or clear the 20.2.2.1 Receiving Data BRGH and BRG16 bits, as required, to achieve the desired baud rate. The receiver data recovery circuit initiates character 2. Enable the asynchronous serial port by clearing reception on the falling edge of the first bit. The first bit, SYNC, and setting bit, SPEN. bit, also known as the Start bit, is always a zero (after 3. If interrupts are desired, set enable bit, RCxIE. accounting for RXDTP setting). Following the Start bit 4. If 9-bit reception is desired, set bit, RX9. will be the Least Significant bit of the data character 5. Enable the reception by setting bit, CREN. being received. As each bit is received, the value will 6. Flag bit, RCxIF, will be set when reception is be sampled and shifted into the Receive Shift Register complete and an interrupt will be generated if (RSR). After all 8 or 9 data bits (user selectable option) enable bit, RCxIE, was set. of the character have been shifted in, one final bit time 7. Read the RCSTAx register to get the ninth bit (if is measured and the level sampled. This is the Stop enabled) and determine if any error occurred bit, which should always be a ‘1’ (after accounting for during reception. RXDTP setting). If the data recovery circuit samples a 8. Read the 8-bit received data by reading the ‘0’ in the Stop bit position then a framing error (FERR) RCREGx register. is set for this character, otherwise the framing error is 9. If any error occurred, clear the error by clearing cleared for this character. enable bit, CREN. Once all data bits of the character and the Stop bit has 10. If using interrupts, ensure that the GIE and PEIE been received, the data bits in the RSR will bits in the INTCON register (INTCON<7:6>) are immediately be transferred to a two character set. First-In-First-Out (FIFO) memory. The FIFO buffering 20.2.3 SETTING UP 9-BIT MODE WITH allows reception of two complete characters before ADDRESS DETECT software is required to service the EUSART receiver. The RSR register is not directly accessible by This mode would typically be used in RS-485 systems. software. Firmware can read data from the FIFO by To set up an Asynchronous Reception with Address reading the RCREGx register. Each firmware initiated Detect Enable: read from the RCREGx register will advance the FIFO 1. Initialize the SPBRGHx:SPBRGx registers for by one character, and will clear the receive interrupt the appropriate baud rate. Set or clear the flag (RCxIF), if no additional data exists in the FIFO. BRGH and BRG16 bits, as required, to achieve the desired baud rate. 20.2.2.2 Receive Overrun Error 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If the user firmware allows the FIFO to become full, and a third character is received before the firmware 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCxIP bit. reads from RCREGx, a buffer overrun error condition will occur. In this case, the hardware will block the 4. Set the RX9 bit to enable 9-bit reception. RSR contents (the third byte received) from being 5. Set the ADDEN bit to enable address detect. copied into the receive FIFO, the character will be lost 6. Enable reception by setting the CREN bit. and the OERR status bit in the RCSTAx register will 7. The RCxIF bit will be set when reception is become set. If an OERR condition is allowed to occur, complete. The interrupt will be Acknowledged if firmware must clear the condition by clearing and then the RCxIE and GIE bits are set. resetting CREN, before additional characters can be 8. Read the RCSTAx register to determine if any successfully received. error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREGx to determine if the device is being addressed.  2011 Microchip Technology Inc. DS39932D-page 339

PIC18F46J11 FAMILY 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. FIGURE 20-6: EUSARTx RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGHx SPBRGx  o6r4 MSb RSR Register LSb  16 or Stop (8) 7  1 0 Start Baud Rate Generator  4 RX9 Pin Buffer Data and Control Recovery { RXx RX9D RCREGx Register 2-Entry FIFO SPEN RXDTP Unread Data in FIFO 8 Interrupt RCxIF Data Bus RCxIE FIGURE 20-7: ASYNCHRONOUS RECEPTION RXx (pin) Sbtaitrt bit 0 bit 1 bit 7/8 Stop Sbtaitrt bit 0 bit 7/8 Stop Sbtaitrt bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 RCREGx RCREGx Read Rcv Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set. DS39932D-page 340  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 72 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 72 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 72 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 72 RCREGx EUSARTx Receive Register 72 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 72 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 73 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: These bits are only available on 44-pin devices. 20.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the BRG is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RXx/DTx line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>). Once set, the typical receive sequence on RXx/DTx is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RXx/DTx line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN/J2602 protocol.) Following a wake-up event, the module generates an RCxIF interrupt. The interrupt is generated synchro- nously to the Q clocks in normal operating modes (Figure20-8) and asynchronously if the device is in Sleep mode (Figure20-9). The interrupt condition is cleared by reading the RCREGx register.  2011 Microchip Technology Inc. DS39932D-page 341

PIC18F46J11 FAMILY The WUE bit is automatically cleared once a 20.2.4.2 Special Considerations Using the low-to-high transition is observed on the RXx line WUE Bit following the wake-up event. At this point, the EUSART The timing of WUE and RCxIF events may cause some module is in Idle mode and returns to normal operation. confusion when it comes to determining the validity of This signals to the user that the Sync Break event is received data. As noted, setting the WUE bit places the over. EUSART in an Idle mode. The wake-up event causes a 20.2.4.1 Special Considerations Using receive interrupt by setting the RCxIF bit. The WUE bit is cleared after this when a rising edge is seen on Auto-Wake-up RXx/DTx. The interrupt condition is then cleared by Since auto-wake-up functions by sensing rising edge reading the RCREGx register. Ordinarily, the data in transitions on RXx/DTx, information with any state RCREGx will be dummy data and should be discarded. changes before the Stop bit may signal a false The fact that the WUE bit has been cleared (or is still End-Of-Character (EOC) and cause data or framing set) and the RCxIF flag is set should not be used as an errors. To work properly, therefore, the initial character indicator of the integrity of the data in RCREGx. Users in the transmission must be all ‘0’s. This can be 00h should consider implementing a parallel method in (8 bits) for standard RS-232 devices or 000h (12bits) firmware to verify received data integrity. for LIN/J2602 bus. To assure that no actual data is lost, check the RCIDL Oscillator start-up time must also be considered, bit to verify that a receive operation is not in process. If especially in applications using oscillators with a receive operation is not occurring, the WUE bit may longer start-up intervals (i.e., HS or HSPLL mode). then be set just prior to entering the Sleep mode. The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. FIGURE 20-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RXx/DTx Line RCxIF Cleared due to user read of RCREGx Note 1: The EUSART remains in Idle while the WUE bit is set. FIGURE 20-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RXx/DTx Line Note 1 RCxIF Cleared due to user read of RCREGx SLEEP Command Executed Sleep Ends Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. DS39932D-page 342  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 20.2.5 BREAK CHARACTER SEQUENCE 20.2.5.1 Break and Sync Transmit Sequence The EUSART module has the capability of sending the The following sequence will send a message frame special Break character sequences that are required by header made up of a Break, followed by an Auto-Baud the LIN/J2602 bus standard. The Break character Sync byte. This sequence is typical of a LIN/J2602 bus transmit consists of a Start bit, followed by twelve ‘0’ master. bits and a Stop bit. The Frame Break character is sent 1. Configure the EUSART for the desired mode. whenever the SENDB and TXEN bits (TXSTAx<3> and 2. Set the TXEN and SENDB bits to set up the TXSTAx<5>) are set while the Transmit Shift Register Break character. is loaded with data. 3. Load the TXREGx with a dummy character to Note that the value of data written to TXREGx will be initiate transmission (the value is ignored). ignored and all ‘0’s will be transmitted. 4. Write ‘55h’ to TXREGx to load the Sync The SENDB bit is automatically reset by hardware after character into the transmit FIFO buffer. the corresponding Stop bit is sent. This allows the user 5. After the Break has been sent, the SENDB bit is to preload the transmit FIFO with the next transmit byte reset by hardware. The Sync character now following the Break character (typically, the Sync transmits in the preconfigured mode. character in the LIN/J2602 specification). When the TXREGx becomes empty, as indicated by the Note that the data value written to the TXREGx for the TXxIF, the next data byte can be written to TXREGx. Break character is ignored. The write simply serves the purpose of initiating the proper sequence. 20.2.6 RECEIVING A BREAK CHARACTER The TRMT bit indicates when the transmit operation is The Enhanced USART module can receive a Break active or Idle, just as it does during normal transmis- character in two ways. sion. See Figure20-10 for the timing of the Break The first method forces configuration of the baud rate character sequence. at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section20.2.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the EUSART will sample the next two transitions on RXx/DTx, cause an RCxIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABDEN bit once the TXxIF interrupt is observed. FIGURE 20-10: SEND BREAK CHARACTER SEQUENCE Write to TXREGx Dummy Write BRG Output (Shift Clock) TXx (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB bit (Transmit Shift Reg. Empty Flag)  2011 Microchip Technology Inc. DS39932D-page 343

PIC18F46J11 FAMILY 20.3 EUSART Synchronous Master Once the TXREGx register transfers the data to the Mode TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be The Synchronous Master mode is entered by setting enabled or disabled by setting or clearing the interrupt the CSRC bit (TXSTAx<7>). In this mode, the data is enable bit, TXxIE. TXxIF is set regardless of the state transmitted in a half-duplex manner (i.e., transmission of enable bit, TXxIE; it cannot be cleared in software. It and reception do not occur at the same time). When will reset only when new data is loaded into the transmitting data, the reception is inhibited and vice TXREGx register. versa. Synchronous mode is entered by setting bit, While flag bit, TXxIF, indicates the status of the TXREGx SYNC (TXSTAx<4>). In addition, enable bit, SPEN register, another bit, TRMT (TXSTAx<1>), shows the (RCSTAx<7>), is set in order to configure the TXx and status of the TSR register. TRMT is a read-only bit which RXx pins to CKx (clock) and DTx (data) lines, is set when the TSR is empty. No interrupt logic is tied to respectively. this bit, so the user must poll this bit in order to determine The Master mode indicates that the processor trans- if the TSR register is empty. The TSR is not mapped in mits the master clock on the CKx line. Clock polarity is data memory so it is not available to the user. selected with the TXCKP bit (BAUDCONx<4>). Setting To set up a Synchronous Master Transmission: TXCKP sets the Idle state on CKx as high, while clear- ing the bit sets the Idle state as low. This option is 1. Initialize the SPBRGHx:SPBRGx registers for the provided to support Microwire devices with this module. appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the required baud 20.3.1 EUSART SYNCHRONOUS MASTER rate. TRANSMISSION 2. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. The EUSART transmitter block diagram is shown in Figure20-3. The heart of the transmitter is the Transmit 3. If interrupts are desired, set enable bit, TXxIE. (Serial) Shift Register (TSR). The Shift register obtains 4. If 9-bit transmission is required, set bit, TX9. its data from the Read/Write Transmit Buffer register, 5. Enable the transmission by setting bit, TXEN. TXREGx. The TXREGx register is loaded with data in 6. If 9-bit transmission is selected, the ninth bit software. The TSR register is not loaded until the last should be loaded in bit, TX9D. bit has been transmitted from the previous load. As 7. Start transmission by loading data to the soon as the last bit is transmitted, the TSR is loaded TXREGx register. with new data from the TXREGx (if available). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1/ SDO1/RP18 bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX1/CK1/RP17 pin (TXCKP = 0) RC6/TX1/CK1 pin (TXCKP = 1) Write to TXREG1 Reg Write Word 1 Write Word 2 TX1IF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. This example is equally applicable to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2). DS39932D-page 344  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1/ bit 0 bit 1 bit 2 bit 6 bit 7 SDO1/RP18 pin RC6/TX1/CK1/RP17 pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2). TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 72 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 72 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 72 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 72 TXREGx EUSARTx Transmit Register 72 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 72 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 73 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 ODCON2 — — — — U2OD U1OD 74 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: These pins are only available on 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 345

PIC18F46J11 FAMILY 20.3.2 EUSART SYNCHRONOUS MASTER 3. Ensure bits, CREN and SREN, are clear. RECEPTION 4. If interrupts are desired, set enable bit, RCxIE. Once Synchronous mode is selected, reception is 5. If 9-bit reception is desired, set bit, RX9. enabled by setting either the Single Receive Enable bit, 6. If a single reception is required, set bit, SREN. SREN (RCSTAx<5>) or the Continuous Receive For continuous reception, set bit, CREN. Enable bit, CREN (RCSTAx<4>). Data is sampled on 7. Interrupt flag bit, RCxIF, will be set when the RXx pin on the falling edge of the clock. reception is complete and an interrupt will be If enable bit, SREN, is set, only a single word is generated if the enable bit, RCxIE, was set. received. If enable bit, CREN, is set, the reception is 8. Read the RCSTAx register to get the ninth bit (if continuous until CREN is cleared. If both bits are set, enabled) and determine if any error occurred then CREN takes precedence. during reception. To set up a Synchronous Master Reception: 9. Read the 8-bit received data by reading the RCREGx register. 1. Initialize the SPBRGHx:SPBRGx registers for 10. If any error occurred, clear the error by clearing the appropriate baud rate. Set or clear the bit, CREN. BRG16 bit, as required, to achieve the desired baud rate. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are 2. Enable the synchronous master serial port by set. setting bits, SYNC, SPEN and CSRC. FIGURE 20-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1/ SDO1/RP18 pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX1/CK1/RP17 pin (TXCKP = 0) RC6/TX1/CK1/RP17 pin (TXCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RC1IF bit (Interrupt) Read RCREG1 Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2). DS39932D-page 346  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 72 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 72 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 72 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 72 RCREGx EUSARTx Receive Register 72 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 72 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 73 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 73 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 ODCON2 — — — — U2OD U1OD 74 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: These pins are only available on 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 347

PIC18F46J11 FAMILY 20.4 EUSART Synchronous Slave To set up a Synchronous Slave Transmission: Mode 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, Synchronous Slave mode is entered by clearing bit, CSRC. CSRC (TXSTAx<7>). This mode differs from the 2. Clear bits, CREN and SREN. Synchronous Master mode in that the shift clock is sup- plied externally at the CKx pin (instead of being supplied 3. If interrupts are desired, set enable bit, TXxIE. internally in Master mode). This allows the device to 4. If 9-bit transmission is desired, set bit, TX9. transfer or receive data while in any low-power mode. 5. Enable the transmission by setting enable bit, TXEN. 20.4.1 EUSART SYNCHRONOUS SLAVE 6. If 9-bit transmission is selected, the ninth bit TRANSMISSION should be loaded in bit, TX9D. The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the modes is identical, except in the case of Sleep mode. TXREGx register. If two words are written to the TXREGx and then the 8. If using interrupts, ensure that the GIE and PEIE SLEEP instruction is executed, the following will occur: bits in the INTCON register (INTCON<7:6>) are set. a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in the TXREGx register. c) Flag bit, TXxIF, will not be set. d) When the first word has been shifted out of TSR, the TXREGx register will transfer the second word to the TSR and flag bit, TXxIF, will now be set. e) If enable bit, TXxIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. DS39932D-page 348  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 72 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 72 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 72 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 72 TXREGx EUSARTx Transmit Register 72 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 72 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 73 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 73 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Note 1: These pins are only available on 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 349

PIC18F46J11 FAMILY 20.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical, except in the case of Sleep, or any CSRC. Idle mode and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCxIE. Slave mode. 3. If 9-bit reception is desired, set bit, RX9. If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN. entering Sleep or any Idle mode, then a word may be 5. Flag bit, RCxIF, will be set when reception is received while in this low-power mode. Once the word complete. An interrupt will be generated if is received, the RSR register will transfer the data to the enable bit, RCxIE, was set. RCREGx register. If the RCxIE enable bit is set, the 6. Read the RCSTAx register to get the ninth bit (if interrupt generated will wake the chip from the enabled) and determine if any error occurred low-power mode. If the global interrupt is enabled, the during reception. program will branch to the interrupt vector. 7. Read the 8-bit received data by reading the RCREGx register. 8. If any error occurred, clear the error by clearing bit, CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 72 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 72 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 72 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 72 RCREGx EUSARTx Receive Register 72 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 72 BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 73 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 73 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: These pins are only available on 44-pin devices. DS39932D-page 350  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 21.0 10-BIT ANALOG-TO-DIGITAL • A/D Control Register 1 (ADCON1) CONVERTER (A/D) MODULE • A/D Port Configuration Register 2 (ANCON0) • A/D Port Configuration Register 1 (ANCON1) The Analog-to-Digital (A/D) Converter module has 10inputs for the 28-pin devices and 13 for the 44-pin • A/D Result Registers (ADRESH and ADRESL) devices. Additionally, two internal channels are The ADCON0 register, in Register21-1, controls the available for sampling the VDDCORE and VBG absolute operation of the A/D module. The ADCON1 register, in reference voltage. This module allows conversion of an Register21-2, configures the A/D clock source, analog input signal to a corresponding 10-bit digital programmed acquisition time and justification. number. The ANCON0 and ANCON1 registers, in Register21-3 The module has six registers: and Register21-4, configure the functions of the port • A/D Control Register 0 (ADCON0) pins. REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0 (ACCESS FC2h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VCFG1 VCFG0 CHS3(2) CHS2(2) CHS1(2) CHS0(2) GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = AVSS(4) bit 6 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = AVDD(4) bit 5-2 CHS<3:0>: Analog Channel Select bits(2) 0000 =Channel 00 (AN0) 0001 =Channel 01 (AN1) 0010 =Channel 02 (AN2) 0011 =Channel 03 (AN3) 0100 =Channel 04 (AN4) 0101 =Channel 05 (AN5)(1) 0110 =Channel 06 (AN6)(1) 0111 =Channel 07 (AN7)(1) 1000 =Channel 08 (AN8) 1001 = Channel 09 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12) 1101 =(Reserved) 1110 = VDDCORE 1111 = VBG Absolute Reference (~1.2V)(3) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled Note 1: These channels are not implemented on 28-pin devices. 2: Performing a conversion on unimplemented channels will return random values. 3: For best accuracy, the band gap reference circuit should be enabled (ANCON1<7> = 1) at least 10ms before performing a conversion on this channel. 4: On 44-pin QFN devices, AVDD and AVSS reference sources are intended to be externally connected to VDD and VSS levels. Other package types tie AVDD and AVSS to VDD and VSS internally.  2011 Microchip Technology Inc. DS39932D-page 351

PIC18F46J11 FAMILY REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1 (ACCESS FC1h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 ADCAL: A/D Calibration bit 1 = Calibration is performed on next A/D conversion 0 = Normal A/D Converter operation bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. DS39932D-page 352  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY The ANCON0 and ANCON1 registers are used to request that the band gap reference circuit should be configure the operation of the I/O pin associated with enabled. For best accuracy, firmware should allow a each analog channel. Setting any one of the PCFG bits settling time of at least 10ms prior to performing the first configures the corresponding pin to operate as a digital acquisition on this channel after enabling the band gap only I/O. Clearing a bit configures the pin to operate as reference. an analog input for either the A/D Converter or the The reference circuit may already have been turned on comparator module; all digital peripherals are disabled if some other hardware module (such as comparators and digital inputs read as ‘0’. As a rule, I/O pins that are or HLVD) has already requested it. In this case, the ini- multiplexed with analog inputs default to analog tial turn-on settling time may have already elapsed and operation on device Resets. firmware does not need to wait as long before measur- In order to correctly perform A/D conversions on the VBG ing VBG. Once the acquisition is complete, firmware band gap reference (ADCON0<5:2> = 1111), the refer- may clear the VBGEN bit, which will save a small ence circuit must be powered on first. The VBGEN bit in amount of power if no other modules are still requesting the ANCON1 register allows the firmware to manually the VBG reference. REGISTER 21-3: ANCON0: A/D PORT CONFIGURATION REGISTER 2 (BANKED F48h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG7(1) PCFG6(1) PCFG5(1) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 PCFG<7:0>: Analog Port Configuration bits (AN<7:0>) 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digital input disabled and reads ‘0’ Note 1: These bits are not implemented on 28-pin devices. REGISTER 21-4: ANCON1: A/D PORT CONFIGURATION REGISTER 1 (BANKED F49h) R/W-0 r U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VBGEN — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 bit 7 bit 0 Legend: r = Reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VBGEN: 1.2V Band Gap Reference Enable bit 1 = 1.2V band gap reference is powered on 0 = 1.2V band gap reference is turned off to save power (if no other modules are requesting it) bit 6 Reserved: Always maintain as ‘0’ for lowest power consumption bit 5 Unimplemented: Read as ‘0’ bit 4-0 PCFG<12:8>: Analog Port Configuration bits (AN<12:8>) 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digital input disabled and reads ‘0’  2011 Microchip Technology Inc. DS39932D-page 353

PIC18F46J11 FAMILY The analog reference voltage is software select- Each port pin associated with the A/D Converter can be able to either the device’s positive and negative configured as an analog input or as a digital I/O. The supply voltage (AVDD and AVSS), or the voltage ADRESH and ADRESL registers contain the result of level on the RA3/AN3/VREF+/C1INB and the A/D conversion. When the A/D conversion is com- RA2/AN2/VREF-/CVREF/C2INB pins. plete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0<1>) is The A/D Converter has a unique feature of being able cleared and the A/D Interrupt Flag bit, ADIF, is set. to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be A device Reset forces all registers to their Reset state. derived from the A/D’s internal RC oscillator. This forces the A/D module to be turned off and any conversion in progress is aborted. The value in the The output of the sample and hold is the input into the ADRESH:ADRESL register pair is not modified for a Converter, which generates the result via successive Power-on Reset (POR). These registers will contain approximation. unknown data after a POR. Figure21-1 provides the block diagram of the A/D module. FIGURE 21-1: A/D BLOCK DIAGRAM CHS<3:0> 1111 VBG 1110 VDDCORE/VCAP 1100 AN12 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7(1) 0110 AN6(1) VAIN 0101 10-Bit (Input Voltage) AN5(1) A/D Converter 0100 AN4 0011 AN3 0010 AN2 VCFG<1:0> 0001 Reference AN1 Voltage VDD(2) 0000 AN0 VREF+ VREF- VSS(2) Note 1: Channels AN5, AN6 and AN7 are not available on 28-pin devices. 2: I/O pins have diode protection to VDD and VSS. DS39932D-page 354  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY After the A/D module has been configured as desired, 2. Configure A/D interrupt (if desired): the selected channel must be acquired before the • Clear ADIF bit conversion is started. The analog input channels must • Set ADIE bit have their corresponding TRIS bits selected as an • Set GIE bit input. To determine acquisition time, see Section21.1 “A/D Acquisition Requirements”. After this acquisi- 3. Wait the required acquisition time (if required). tion time has elapsed, the A/D conversion can be 4. Start conversion: started. An acquisition time can be programmed to • Set GO/DONE bit (ADCON0<1>) occur between setting the GO/DONE bit and the actual 5. Wait for A/D conversion to complete, by either: start of the conversion. • Polling for the GO/DONE bit to be cleared The following steps should be followed to do an A/D OR conversion: • Waiting for the A/D interrupt 1. Configure the A/D module: 6. Read A/D Result registers (ADRESH:ADRESL); • Configure the required ADC pins as analog clear bit, ADIF, if required. pins using ANCON0, ANCON1 7. For next conversion, go to step 1 or step 2, as • Set voltage reference using ADCON0 required. The A/D conversion time per bit is • Select A/D input channel (ADCON0) defined as TAD. A minimum wait of 2 TAD is • Select A/D acquisition time (ADCON1) required before next acquisition starts. • Select A/D conversion clock (ADCON1) • Turn on A/D module (ADCON0) FIGURE 21-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to VDD various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) RSS = Sampling Switch Resistance 1 2 3 4 Sampling Switch (k)  2011 Microchip Technology Inc. DS39932D-page 355

PIC18F46J11 FAMILY 21.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation21-1 may be used. This equation assumes For the A/D Converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is illustrated in Figure21-2. The Equation21-3 provides the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time, TACQ. This calculation is based on the following application system required to charge the capacitor CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 25 pF at the analog input (due to pin leakage current). The Rs = 2.5 k maximum recommended impedance for analog Conversion Error  1/2 LSb sources is 2.5k. After the analog input channel is VDD = 3VRss = 2 k selected (changed), the channel must be sampled for Temperature = 85C (system max.) at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 21-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 21-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 µs TCOFF = (Temp – 25°C)(0.02 s/°C) (85°C – 25°C)(0.02 s/°C) 1.2 µs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 s. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) s -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s 1.05 µs TACQ = 0.2 s + 1.05 s + 1.2 s 2.45 µs DS39932D-page 356  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 21.2 Selecting and Configuring TABLE 21-1: TAD vs. DEVICE OPERATING Automatic Acquisition Time FREQUENCIES The ADCON1 register allows the user to select an AD Clock Source (TAD) Maximum acquisition time that occurs each time the GO/DONE Device bit is set. Operation ADCS<2:0> Frequency When the GO/DONE bit is set, sampling is stopped and 2 TOSC 000 2.86 MHz a conversion begins. The user is responsible for ensur- 4 TOSC 100 5.71 MHz ing the required acquisition time has passed between 8 TOSC 001 11.43 MHz selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT<2:0> bits 16 TOSC 101 22.86 MHz (ADCON1<5:3>) remain in their Reset state (‘000’) and 32 TOSC 010 45.71 MHz is compatible with devices that do not offer 64 TOSC 110 48.0 MHz programmable acquisition times. RC(2) 011 1.00 MHz(1) If desired, the ACQT bits can be set to select a pro- Note 1: The RC source has a typical TAD time of grammable acquisition time for the A/D module. When 4s. the GO/DONE bit is set, the A/D module continues to 2: For device frequencies above 1 MHz, the sample the input for the selected acquisition time, then device must be in Sleep mode for the automatically begins a conversion. Since the acquisi- entire conversion or the A/D accuracy may tion time is programmed, there may be no need to wait be out of specification. for an acquisition time between selecting a channel and setting the GO/DONE bit. 21.4 Configuring Analog Port Pins In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the The ANCON0, ANCON1 and TRISA registers control A/D begins sampling the currently selected channel the operation of the A/D port pins. The port pins needed again. If an acquisition time is programmed, there is as analog inputs must have their corresponding TRIS nothing to indicate if the acquisition time has ended or bits set (input). If the TRIS bit is cleared (output), the if the conversion has begun. digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the 21.3 Selecting the A/D Conversion CHS<3:0> bits and the TRIS bits. Clock Note1: When reading the PORT register, all pins The A/D conversion time per bit is defined as TAD. The configured as analog input channels will A/D conversion requires 11 TAD per 10-bit conversion. read as cleared (a low level). Pins config- The source of the A/D conversion clock is software ured as digital inputs will convert an selectable. analog input. Analog levels on a digitally There are seven possible options for TAD: configured input will be accurately converted. • 2 TOSC 2: Analog levels on any pin defined as a • 4 TOSC digital input may cause the digital input • 8 TOSC buffer to consume current out of the • 16 TOSC device’s specification limits. • 32 TOSC • 64 TOSC • Internal RC Oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD (see parameter 130 in Table29-31 for more information). Table21-1 provides the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.  2011 Microchip Technology Inc. DS39932D-page 357

PIC18F46J11 FAMILY 21.5 A/D Conversions 21.6 Use of the ECCP2 Trigger Figure21-3 displays the operation of the A/D Converter An A/D conversion can be started by the Special Event after the GO/DONE bit has been set and the Trigger of the ECCP2 module. This requires that the ACQT<2:0> bits are cleared. A conversion is started CCP2M<3:0> bits (CCP2CON<3:0>) be programmed after the following instruction to allow entry into Sleep as ‘1011’ and that the A/D module is enabled (ADON mode before the conversion begins. bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion, Figure21-4 displays the operation of the A/D Converter and the Timer1 (or Timer3) counter will be reset to zero. after the GO/DONE bit has been set, the ACQT<2:0> Timer1 (or Timer3) is reset to automatically repeat the bits are set to ‘010’ and a 4TAD acquisition time has A/D acquisition period with minimal software overhead been selected before the conversion starts. (moving ADRESH/ADRESL to the desired location). Clearing the GO/DONE bit during a conversion will The appropriate analog input channel must be selected abort the current conversion. The A/D Result register and the minimum acquisition period is either timed by pair will NOT be updated with the partially completed the user, or an appropriate TACQ time is selected before A/D conversion sample. This means the the Special Event Trigger sets the GO/DONE bit (starts ADRESH:ADRESL registers will continue to contain a conversion). the value of the last completed conversion (or the last If the A/D module is not enabled (ADON is cleared), the value written to the ADRESH:ADRESL registers). Special Event Trigger will be ignored by the A/D module After the A/D conversion is completed or aborted, a but will still reset the Timer1 (or Timer3) counter. 2TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 21-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 21-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) Next Q4: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. DS39932D-page 358  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 21.7 A/D Converter Calibration If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and The A/D Converter in the PIC18F46J11 family of ADCS<2:0> bits in ADCON1 should be updated in devices includes a self-calibration feature, which com- accordance with the power-managed mode clock that pensates for any offset generated within the module. will be used. After the power-managed mode is entered The calibration process is automated and is initiated by (either of the power-managed Run modes), an A/D setting the ADCAL bit (ADCON1<6>). The next time acquisition or conversion may be started. Once an the GO/DONE bit is set, the module will perform a acquisition or conversion is started, the device should “dummy” conversion (that is, with reading none of the continue to be clocked by the same power-managed input channels) and store the resulting value internally mode clock source until the conversion has been com- to compensate for the offset. Thus, subsequent offsets pleted. If desired, the device may be placed into the will be compensated. corresponding power-managed Idle mode during the Example21-1 provides an example of a calibration conversion. routine. If the power-managed mode clock frequency is less The calibration process assumes that the device is in a than 1MHz, the A/D RC clock source should be relatively steady-state operating condition. If A/D selected. calibration is used, it should be performed after each Operation in the Sleep mode requires the A/D RC clock device Reset or if there are other major changes in to be selected. If bits, ACQT<2:0>, are set to ‘000’ and operating conditions. a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP 21.8 Operation in Power-Managed instruction and entry to Sleep mode. The IDLEN and Modes SCS bits in the OSCCON register must have already been cleared prior to starting the conversion. The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. EXAMPLE 21-1: SAMPLE A/D CALIBRATION ROUTINE BCF ANCON0,PCFG0 ;Make Channel 0 analog BSF ADCON0,ADON ;Enable A/D module BSF ADCON1,ADCAL ;Enable Calibration BSF ADCON0,GO ;Start a dummy A/D conversion CALIBRATION ; BTFSC ADCON0,GO ;Wait for the dummy conversion to finish BRA CALIBRATION ; BCF ADCON1,ADCAL ;Calibration done, turn off calibration enable ;Proceed with the actual A/D conversion  2011 Microchip Technology Inc. DS39932D-page 359

PIC18F46J11 FAMILY TABLE 21-2: SUMMARY OF A/D REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PMPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72 PIE1 PMPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72 IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72 PIR2 OSCFIF CM2IF CM1IF — BCL1IF LVDIF TMR3IF CCP2IF 72 PIE2 OSCFIE CM2IE CM1IE — BCL1IE LVDIE TMR3IE CCP2IE 72 IPR2 OSCFIP CM2IP CM1IP — BCL1IP LVDIP TMR3IP CCP2IP 72 ADRESH A/D Result Register High Byte 70 ADRESL A/D Result Register Low Byte 70 ADCON0 VCFG1 VCFG0 CHS3 CHS3 CHS1 CHS0 GO/DONE ADON 70 ANCON0 PCFG7(1) PCFG6(1) PCFG5(1) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 74 ADCON1 ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 70 ANCON1 VBGEN r(2) — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 74 CCPxCON PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 71 PORTA RA7 RA6 RA5 — RA3 RA2 RA1 RA0 72 TRISA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 72 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These bits are only available on 44-pin devices. 2: Reserved. Always maintain as ‘0’ for minimum power consumption. DS39932D-page 360  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 22.0 COMPARATOR MODULE 22.1 Registers The analog comparator module contains two compara- The CMxCON registers (Register22-1) select the input tors that can be independently configured in a variety of and output configuration for each comparator, as well ways. The inputs can be selected from the analog inputs as the settings for interrupt generation. and two internal voltage references. The digital outputs The CMSTAT register (Register22-2) provides the out- are available at the pin level and can also be read put results of the comparators. The bits in this register through the control register. Multiple output and interrupt are read-only. event generation is also available. Figure22-1 provides a generic single comparator from the module. Key features of the module are: • Independent comparator control • Programmable input configuration • Output to both pin and register levels • Programmable output polarity • Independent interrupt generation for each comparator with configurable interrupt-on-change FIGURE 22-1: COMPARATOR SIMPLIFIED BLOCK DIAGRAM CCH<1:0> COUTx (CMSTAT<1:0>) CxINB 0 Interrupt CMxIF VIRV 3 Logic EVPOL<4:3> CREF COE VIN- CxOUT Polarity CxINA 0 VIN+ Cx Logic CVREF 1 CON CPOL  2011 Microchip Technology Inc. DS39932D-page 361

PIC18F46J11 FAMILY REGISTER 22-1: CMxCON: COMPARATOR CONTROL x REGISTER (ACCESS FD2h/FD1h) R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin (assigned in PPS module) 0 = Comparator output is internal only bit 5 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 4-3 EVPOL<1:0>: Interrupt Polarity Select bits 11 = Interrupt generation on any change of the output(1) 10 = Interrupt generation only on high-to-low transition of the output 01 = Interrupt generation only on low-to-high transition of the output 00 = Interrupt generation is disabled bit 2 CREF: Comparator Reference Select bit (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CxINA pin bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects to VIRV 10 = For CM1CON, inverting input of comparator connects to C2INB pin; for CM2CON, reserved 01 = Reserved 00 = Inverting input of comparator connects to CxINB pin Note 1: The CMxIF is automatically set any time this mode is selected and must be cleared by the application after the initial configuration. DS39932D-page 362  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 22-2: CMSTAT: COMPARATOR STATUS REGISTER (ACCESS F70h) U-0 U-0 U-0 U-0 U-0 U-0 R-1 R-1 — — — — — — COUT2 COUT1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 COUT<2:1>: Comparator x Status bits If CPOL = 0 (non-inverted polarity): 1 = Comparator VIN+ > VIN- 0 = Comparator VIN+ < VIN- If CPOL = 1 (inverted polarity): 1 = Comparator VIN+ < VIN- 0 = Comparator VIN+ > VIN-  2011 Microchip Technology Inc. DS39932D-page 363

PIC18F46J11 FAMILY 22.2 Comparator Operation 22.3 Comparator Response Time A single comparator is shown in Figure22-2, along with Response time is the minimum time, after selecting a the relationship between the analog input levels and new reference voltage or input source, before the the digital output. When the analog input at VIN+ is less comparator output has a valid level. The response time than the analog input, VIN-, the output of the compara- of the comparator differs from the settling time of the tor is a digital low level. When the analog input at VIN+ voltage reference. Therefore, both of these times must is greater than the analog input, VIN-, the output of the be considered when determining the total response to comparator is a digital high level. The shaded areas of a comparator input change. Otherwise, the maximum the output of the comparator in Figure22-2 represent delay of the comparators should be used (see the uncertainty due to input offsets and response time. Section29.0 “Electrical Characteristics”). FIGURE 22-2: SINGLE COMPARATOR 22.4 Analog Input Connection Considerations VIN+ + Figure22-3 provides a simplified circuit for an analog Output input. Since the analog pins are connected to a digital VIN- – output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. VIN- A maximum source impedance of 10 k is VIN+ recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little Output leakage current. FIGURE 22-3: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage DS39932D-page 364  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 22.5 Comparator Control and The external reference is used when CREF=0 Configuration (CMxCON<2>) and VIN+ is connected to the CxINA pin. When external voltage references are used, the Each comparator has up to eight possible combina- comparator module can be configured to have the tions of inputs: up to four external analog inputs, and reference sources externally. The reference signal one of two internal voltage references. must be between VSS and VDD, and can be applied to Both comparators allow a selection of the signal from either pin of the comparator. pin, CxINA, or the voltage from the comparator refer- The comparator module also allows the selection of an ence (CVREF) on the non-inverting channel. This is internally generated voltage reference (CVREF) from compared to either CxINB, CTMU or the microcon- the comparator voltage reference module. This module troller’s fixed internal reference voltage (VIRV, 0.6V is described in more detail in Section22.0 “Compara- nominal) on the inverting channel. tor Module”. The reference from the comparator Table22-1 provides the comparator inputs and outputs voltage reference module is only available when tied to fixed I/O pins. CREF=1. In this mode, the internal voltage reference is applied to the comparator’s VIN+ pin. Figure22-4 illustrates the available comparator configurations and their corresponding bit settings. Note: The comparator input pin selected by CCH<1:0> must be configured as an input TABLE 22-1: COMPARATOR INPUTS AND by setting both the corresponding TRIS OUTPUTS and PCFG bits in the ANCON1 register. Comparator Input or Output I/O Pin 22.5.2 COMPARATOR ENABLE AND C1INA (VIN+) RA0 OUTPUT SELECTION C1INB (VIN-) RA3 The comparator outputs are read through the CMSTAT 1 C1OUT Remapped register. The CMSTAT<0> reads the Comparator 1 out- RPn put and CMSTAT<1> reads the Comparator 2 output. These bits are read-only. C2INA(VIN+) RA1 The comparator outputs may also be directly output to C2INB(VIN-) RA2 2 the RPn I/O pins by setting the COE bit (CMxCON<6>). C2OUT Remapped When enabled, multiplexers in the output path of the RPn pins switch to the output of the comparator. 22.5.1 COMPARATOR ENABLE AND By default, the comparator’s output is at logic high INPUT SELECTION whenever the voltage on VIN+ is greater than on VIN-. The polarity of the comparator outputs can be inverted Setting the CON bit of the CMxCON register using the CPOL bit (CMxCON<5>). (CMxCON<7>) enables the comparator for operation. The uncertainty of each of the comparators is related to Clearing the CON bit disables the comparator, resulting the input offset voltage and the response time given in in minimum current consumption. the specifications, as discussed in Section22.2 The CCH<1:0> bits in the CMxCON register “Comparator Operation”. (CMxCON<1:0>) direct either one of three analog input pins, or the Internal Reference Voltage (VIRV), to the comparator VIN-. Depending on the comparator operat- ing mode, either an external or internal voltage reference may be used. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly.  2011 Microchip Technology Inc. DS39932D-page 365

PIC18F46J11 FAMILY FIGURE 22-4: COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx COE VIN- VIN+ Cx Off (Read as ‘0’) CxOUT pin Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 CON = 1, CREF = 0, CCH<1:0> = 01 COE COE CxINB VIN- CxINC VIN- CxINA VIN+ Cx CxOUT CxINA VIN+ Cx CxOUT pin pin Comparator CxIND > CxINA Compare Comparator VIRV > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 10 CON = 1, CREF = 0, CCH<1:0> = 11 COE COE CxIND VIN- VIRV VIN- CxINA VIN+ Cx CxOUT CxINA VIN+ Cx CxOUT pin pin Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 00 CON = 1, CREF = 1, CCH<1:0> = 01 COE COE CxINB VIN- CxINC VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT pin pin Comparator CxIND > CVREF Compare Comparator VIRV > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 10 CON = 1, CREF = 1, CCH<1:0> = 11 COE COE CxIND VIN- VIRV VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT pin pin Note: VIRV is the Internal Reference Voltage (see Table29-2). DS39932D-page 366  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 22.6 Comparator Interrupts When EVPOL<1:0> = 11, the comparator interrupt flag is set whenever there is a change in the output value of The comparator interrupt flag is set whenever any of either comparator. Software will need to maintain the following occurs: information about the status of the output bits, as read - Low-to-high transition of the comparator from CMSTAT<1:0>, to determine the actual change output that occurred. The CMxIF bits (PIR2<6:5>) are the - High-to-low transition of the comparator Comparator Interrupt Flags. The CMxIF bits must be output reset by clearing them. Since it is also possible to write a ‘1’ to this register, a simulated interrupt may be - Any change in the comparator output initiated. The comparator interrupt selection is done by the Table22-2 provides the interrupt generation EVPOL<1:0> bits in the CMxCON register corresponding to comparator input voltages and (CMxCON<4:3>). EVPOL bit settings. In order to provide maximum flexibility, the output of the Both the CMxIE bits (PIE2<6:5>) and the PEIE bit comparator may be inverted using the CPOL bit in the (INTCON<6>) must be set to enable the interrupt. In CMxCON register (CMxCON<5>). This is functionally addition, the GIE bit (INTCON<7>) must also be set. identical to reversing the inverting and non-inverting If any of these bits are clear, the interrupt is not inputs of the comparator for a particular mode. enabled, though the CMxIF bits will still be set if an An interrupt is generated on the low-to-high or high-to- interrupt condition occurs. low transition of the comparator output. This mode of Figure22-1 provides a simplified diagram of the interrupt generation is dependent on EVPOL<1:0> in interrupt section. the CMxCON register. When EVPOL<1:0> = 01 or 10, the interrupt is generated on a low-to-high or high-to- low transition of the comparator output. Once the interrupt is generated, it is required to clear the interrupt flag by software. TABLE 22-2: COMPARATOR INTERRUPT GENERATION Comparator Interrupt CPOL EVPOL<1:0> COUTx Transition Input Change Generated VIN+ > VIN- Low-to-High No 00 VIN+ < VIN- High-to-Low No VIN+ > VIN- Low-to-High Yes 01 VIN+ < VIN- High-to-Low No 0 VIN+ > VIN- Low-to-High No 10 VIN+ < VIN- High-to-Low Yes VIN+ > VIN- Low-to-High Yes 11 VIN+ < VIN- High-to-Low Yes VIN+ > VIN- High-to-Low No 00 VIN+ < VIN- Low-to-High No VIN+ > VIN- High-to-Low No 01 VIN+ < VIN- Low-to-High Yes 1 VIN+ > VIN- High-to-Low Yes 10 VIN+ < VIN- Low-to-High No VIN+ > VIN- High-to-Low Yes 11 VIN+ < VIN- Low-to-High Yes  2011 Microchip Technology Inc. DS39932D-page 367

PIC18F46J11 FAMILY 22.7 Comparator Operation During 22.8 Effects of a Reset Sleep A device Reset forces the CMxCON registers to their When a comparator is active and the device is placed Reset state. This forces both comparators and the in Sleep mode, the comparator remains active and the voltage reference to the OFF state. interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode when enabled. Each operational comparator will consume additional current. To minimize power consumption while in Sleep mode, turn off the comparators (CON=0) before entering Sleep. If the device wakes up from Sleep, the contents of the CMxCON register are not affected. TABLE 22-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR2 OSCFIF CM2IF CM1IF — BCL1IF LVDIF TMR3IF CCP2IF 72 PIE2 OSCFIE CM2IE CM1IE — BCL1IE LVDIE TMR3IE CCP2IE 72 IPR2 OSCFIP CM2IP CM1IP — BCL1IP LVDIP TMR3IP CCP2IP 72 CMxCON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 70 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 74 CMSTAT — — — — — — COUT2 COUT1 73 ANCON0 PCFG7(1) PCFG6(1) PCFG5(1) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 74 PORTA RA7 RA6 RA5 — RA3 RA2 RA1 RA0 72 TRISA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 72 Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not related to comparator operation. Note 1: These bits and/or registers are not implemented on 28-pin devices. DS39932D-page 368  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 23.0 COMPARATOR VOLTAGE Figure23-1 provides a block diagram of the module. REFERENCE MODULE The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to The comparator voltage reference is a 16-tap resistor conserve power when the reference is not being used. ladder network that provides a selectable reference The module’s supply reference can be provided from voltage. Although its primary purpose is to provide a either device VDD/VSS or an external voltage reference. reference for the analog comparators, it may also be used independently of them. FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ VDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0  2011 Microchip Technology Inc. DS39932D-page 369

PIC18F46J11 FAMILY 23.1 Configuring the Comparator The comparator reference supply voltage can come Voltage Reference from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The The comparator voltage reference module is controlled voltage source is selected by the CVRSS bit through the CVRCON register (Register23-1). The (CVRCON<4>). comparator voltage reference provides two ranges of The settling time of the comparator voltage reference output voltage, each with 16 distinct levels. The range must be considered when changing the CVREF to be used is selected by the CVRR bit (CVRCON<5>). output (see Table29-4 in Section29.0 “Electrical The primary difference between the ranges is the size Characteristics”). of the steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution. The equations used to calculate the output of the comparator voltage reference are as follows: EQUATION 23-1: CALCULATING OUTPUT OF THE COMPARATOR VOLTAGE REFERENCE When CVRR = 1 and CVRSS = 0: CVREF = ((CVR<3:0>)/24) x (AVDD - AVSS) When CVRR = 0 and CVRSS = 0: CVREF=((AVDD - AVSS)/4)+((CVR<3:0>)/32)x(AVDD - AVSS) When CVRR = 1 and CVRSS = 1: CVREF=((CVR<3:0>)/24) x ((VREF+) – VREF-) When CVRR = 0 and CVRSS = 1: CVREF= (((VREF+) – VREF-)/4)+((CVR<3:0>)/32)x((VREF+) – VREF-) REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER (BANKED F53h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF/C2INB pin 0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF/C2INB pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = AVDD – AVSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0  (CVR<3:0>)  15) When CVRR = 1: CVREF = ((CVR<3:0>)/24)  (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32)  (CVRSRC) Note 1: CVROE overrides the TRIS bit setting. DS39932D-page 370  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 23.2 Voltage Reference Accuracy/Error The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive The full range of voltage reference cannot be realized capability, a buffer must be used on the voltage due to the construction of the module. The transistors reference output for external connections to VREF. See on the top and bottom of the resistor ladder network Figure23-2 for an example buffering technique. (see Figure23-1) keep CVREF from approaching the reference source rails. The voltage reference is derived 23.4 Operation During Sleep from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested When the device wakes up from Sleep through an absolute accuracy of the voltage reference can be interrupt or a Watchdog Timer time-out, the contents of found in Section29.0 “Electrical Characteristics”. the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage 23.3 Connection Considerations reference should be disabled. The voltage reference module operates independently 23.5 Effects of a Reset of the comparator module. The output of the reference generator may be connected to the RA2 pin if the A device Reset disables the voltage reference by CVROE bit is set. Enabling the voltage reference out- clearing bit, CVREN (CVRCON<7>). This Reset also put onto RA2 when it is configured as a digital input will disconnects the reference from the RA2 pin by clearing increase current consumption. Connecting RA2 as a bit, CVROE (CVRCON<6>) and selects the high-voltage digital output with CVRSS enabled will also increase range by clearing bit, CVRR (CVRCON<5>). The CVR current consumption. value select bits are also cleared. FIGURE 23-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F46J11 CVREF R(1) Module + Voltage RA2 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the Comparator Voltage Reference Configuration bits, CVRCON<5> and CVRCON<3:0>. TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 74 CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 70 CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 70 TRISA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 72 ANCON0 PCFG7(1) PCFG6(1) PCFG5(1) PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 74 ANCON1 VBGEN r — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 74 Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used with the comparator voltage reference. Note 1: These bits are only available on 44-pin devices.  2011 Microchip Technology Inc. DS39932D-page 371

PIC18F46J11 FAMILY NOTES: DS39932D-page 372  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 24.0 HIGH/LOW VOLTAGE DETECT The High/Low-Voltage Detect Control register (HLVD) (Register24-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned PIC18F46J11 family devices (including PIC18LF46J11 off” by the user under software control, which family devices) have a High/Low Voltage Detect minimizes the current consumption for the device. (HLVD) module for monitoring the absolute voltage on Figure24-1 provides a block diagram for the HLVD VDD or the HLVDIN pin. This is a programmable circuit module. that allows the user to specify both a device voltage trip point and the direction of change from that point. If the module detects an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the inter- rupt vector address and the software can then respond to the interrupt. REGISTER 24-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER (ACCESS F85h) R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIRMAG BGVST IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 BGVST: Band Gap Reference Voltages Stable Status Flag bit 1 = Indicates internal band gap voltage references is stable 0 = Indicates internal band gap voltage reference is not stable bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL<3:0>: Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 1000 = Minimum setting 0xxx = Reserved Note 1: See Table29-8 in Section29.0 “Electrical Characteristics” for specifications. The module is enabled by setting the HLVDEN bit. The VDIRMAG bit determines the overall operation of Each time the module is enabled, the circuitry requires the module. When VDIRMAG is cleared, the module some time to stabilize. The IRVST bit is a read-only bit monitors for drops in VDD below a predetermined set that indicates when the circuit is stable. The module point. When the bit is set, the module monitors for rises can generate an interrupt only after the circuit is stable in VDD above the set point. and IRVST is set.  2011 Microchip Technology Inc. DS39932D-page 373

PIC18F46J11 FAMILY 24.1 Operation The trip point voltage is software programmable to any one of 8 values. The trip point is selected by When the HLVD module is enabled, a comparator uses programming the HLVDL<3:0> bits (HLVDCON<3:0>). an internally generated reference voltage as the set Additionally, the HLVD module allows the user to point. The set point is compared with the trip point, supply the trip voltage to the module from an external where each node in the resistor divider represents a source. This mode is enabled when bits, HLVDL<3:0>, trip point voltage. The “trip point” voltage is the voltage are set to ‘1111’. In this state, the comparator input is level at which the device detects a high or low-voltage multiplexed from the external input pin, HLVDIN. This event, depending on the configuration of the module. gives users flexibility because it allows them to When the supply voltage is equal to the trip point, the configure the HLVD interrupt to occur at any voltage in voltage tapped off of the resistor array is equal to the the valid operating range. internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the LVDIF bit. FIGURE 24-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL<3:0> HLVDCON Register HLVDEN VDIRMAG HLVDIN X Set U M LVDIF 1 o- 6-t 1 HLVDEN Internal Voltage Reference 1.2V Typical DS39932D-page 374  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 24.2 HLVD Setup 24.4 HLVD Start-up Time To set up the HLVD module: The internal reference voltage of the HLVD module, specified in electrical specification parameter D420 1. Disable the module by clearing the HLVDEN bit (see Table29-8 in Section29.0 “Electrical Charac- (HLVDCON<4>). teristics”), may be used by other internal circuitry, 2. Write the value to the HLVDL<3:0> bits that such as the Programmable Brown-out Reset (BOR). selects the desired HLVD trip point. If the HLVD or other circuits using the voltage reference 3. Set the VDIRMAG bit to detect one of the are disabled to lower the device’s current consumption, following: the reference voltage circuit will require time to become • High voltage (VDIRMAG = 1) stable before a low or high-voltage condition can be • Low voltage (VDIRMAG = 0) reliably detected. This start-up time, TIRVST, is an 4. Enable the HLVD module by setting the interval that is independent of device clock speed. It is HLVDEN bit. specified in electrical specification parameter36 5. Clear the HLVD Interrupt Flag, LVDIF (Table29-15). (PIR2<2>), which may have been set from a The HLVD interrupt flag is not enabled until TIRVST has previous interrupt. expired and a stable reference voltage is reached. For 6. If interrupts are desired, enable the HLVD this reason, brief excursions beyond the set point may interrupt by setting the HLVDIE and GIE/GIEH not be detected during this interval. Refer to Figure24-2 bits (PIE2<2> and INTCON<7>). or Figure24-3. An interrupt will not be generated until the IRVST bit is set. 24.3 Current Consumption When the module is enabled, the HLVD comparator and voltage divider are enabled and will consume static current. The total current consumption, when enabled, is specified in electrical specification parameter D022B (IHLVD) (Section29.2 “DC Characteristics: Power- Down and Supply Current PIC18F46J11 Family (Industrial)”). Depending on the application, the HLVD module does not need to operate constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the HLVD module may be disabled.  2011 Microchip Technology Inc. DS39932D-page 375

PIC18F46J11 FAMILY FIGURE 24-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: LVDIF may not be set VDD VHLVD LVDIF Enable HLVD TIRVST IRVST LVDIF cleared in software Internal Reference is stable CASE 2: VDD VHLVD LVDIF Enable HLVD IRVST TIRVST Internal Reference is stable LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since HLVD condition still exists DS39932D-page 376  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 24-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: LVDIF may not be set VHLVD VDD LVDIF Enable HLVD IRVST TIRVST LVDIF cleared in software Internal Reference is stable CASE 2: VHLVD VDD LVDIF Enable HLVD IRVST TIRVST Internal Reference is stable LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since HLVD condition still exists 24.5 Applications FIGURE 24-4: TYPICAL HIGH/ LOW-VOLTAGE DETECT In many applications, it is desirable to have the ability to APPLICATION detect a drop below, or rise above, a particular threshold. For general battery applications, Figure24-4 provides a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic VA generates an interrupt at time, TA. The interrupt could VB cause the execution of an ISR, which would allow the application to perform “housekeeping tasks” and e g perform a controlled shutdown before the device a voltage exits the valid operating range at TB. Volt The HLVD, thus, would give the application a time window, represented by the difference between TA and TB, to safely exit. Time TA TB Legend: VA = HLVD trip point VB = Minimum valid device operating voltage  2011 Microchip Technology Inc. DS39932D-page 377

PIC18F46J11 FAMILY 24.6 Operation During Sleep 24.7 Effects of a Reset When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state. during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off. point, the LVDIF bit will be set and the device will wake- up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 24-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 72 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR2 OSCFIF CM1IF CM2IF — BCLIF LVDIF TMR3IF CCP2IF 71 PIE2 OSCFIE CM1IE CM2IE — BCLIE LVDIE TMR3IE CCP2IE 71 IPR2 OSCFIP CM1IP CM2IP — BCLIP LVDIP TMR3IP CCP2IP 71 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. DS39932D-page 378  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 25.0 CHARGE TIME • Control of response to edges MEASUREMENT UNIT (CTMU) • Time measurement resolution of 1nanosecond • High precision time measurement The Charge Time Measurement Unit (CTMU) is a • Time delay of external or internal signal flexible analog module that provides accurate differen- asynchronous to system clock tial time measurement between pulse sources, as well • Accurate current source suitable for capacitive as asynchronous pulse generation. By working with measurement other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, The CTMU works in conjunction with the A/D Converter measure relative changes in capacitance or generate to provide up to 13 channels for time or charge output pulses with a specific time delay. The CTMU is measurement, depending on the specific device and ideal for interfacing with capacitive-based sensors. the number of A/D channels available. When config- ured for time delay, the CTMU is connected to one of The module includes the following key features: the analog comparators. The level-sensitive input edge • Up to 13 channels available for capacitive or time sources can be selected from four sources: two measurement input external inputs or ECCP1/ECCP2 Special Event • On-chip precision current source Triggers. • Four-edge input trigger sources Figure25-1 provides a block diagram of the CTMU. • Polarity control for each edge source • Control of edge sequence FIGURE 25-1: CTMU BLOCK DIAGRAM CTMUCONH:CTMUCONL CTMUICON EDGEN EDGSEQEN EDG1SEL<1:0> ITRIM<5:0> TGEN EDG1POL IRNG<1:0> IDISSEN EDG2SEL<1:0> EDG1STAT Current Source EDG2POL EDG2STAT CTED1 Edge CTMU Control Control CTED2 Logic Current Logic Control ECCP2 Pulse CTPLS ECCP1 Generator A/D Converter Comparator 2 Input Comparator 2 Output  2011 Microchip Technology Inc. DS39932D-page 379

PIC18F46J11 FAMILY 25.1 CTMU Operation Current trim is provided by the ITRIM<5:0> bits (CTMUICON<7:2>). These six bits allow trimming of The CTMU works by using a fixed current source to the current source in steps of approximately 2% per charge a circuit. The type of circuit depends on the type step. Note that half of the range adjusts the current of measurement being made. In the case of charge source positively and the other half reduces the current measurement, the current is fixed, and the amount of source. A value of ‘000000’ is the neutral position (no time the current is applied to the circuit is fixed. The change). A value of ‘100001’ is the maximum negative amount of voltage read by the A/D is then a measure- adjustment (approximately -62%) and ‘011111’ is the ment of the capacitance of the circuit. In the case of maximum positive adjustment (approximately +62%). time measurement, the current, as well as the capaci- tance of the circuit, is fixed. In this case, the voltage 25.1.3 EDGE SELECTION AND CONTROL read by the A/D is then representative of the amount of CTMU measurements are controlled by edge events time elapsed from the time the current source starts occurring on the module’s two input channels. Each and stops charging the circuit. channel, referred to as Edge 1 and Edge 2, can be con- If the CTMU is being used as a time delay, both figured to receive input pulses from one of the edge capacitance and current source are fixed, as well as the input pins (CTED1 and CTED2) or ECCPx Special voltage supplied to the comparator circuit. The delay of Event Triggers. The input channels are level-sensitive, a signal is determined by the amount of time it takes the responding to the instantaneous level on the channel voltage to charge to the comparator threshold voltage. rather than a transition between levels. The inputs are selected using the EDG1SEL and EDG2SEL bit pairs 25.1.1 THEORY OF OPERATION (CTMUCONL<3:2 and 6:5>). The operation of the CTMU is based on the equation In addition to source, each channel can be configured for for charge: event polarity using the EDGE2POL and EDGE1POL dV bits (CTMUCONL<7,4>). The input channels can also I = C------- dT be filtered for an edge event sequence (Edge 1 occur- ring before Edge 2) by setting the EDGSEQEN bit More simply, the amount of charge measured in (CTMUCONH<2>). coulombs in a circuit is defined as current in amperes (I) multiplied by the amount of time in seconds that the 25.1.4 EDGE STATUS current flows (t). Charge is also defined as the The CTMUCONL register also contains two status bits: capacitance in farads (C) multiplied by the voltage of EDG2STAT and EDG1STAT (CTMUCONL<1:0>). the circuit (V). It follows that: Their primary function is to show if an edge response It = CV. has occurred on the corresponding channel. The CTMU automatically sets a particular bit when an edge The CTMU module provides a constant, known current response is detected on its channel. The level-sensitive source. The A/D Converter is used to measure (V) in nature of the input channels also means that the status the equation, leaving two unknowns: capacitance (C) bits become set immediately if the channel’s configura- and time (t). The above equation can be used to calcu- tion is changed and is the same as the channel’s late capacitance or time, by either the relationship current state. using the known fixed capacitance of the circuit: The module uses the edge status bits to control the cur- t = CVI rent source output to external analog modules (such as the A/D Converter). Current is only supplied to external or by: modules when only one (but not both) of the status bits C = ItV is set, and shuts current off when both bits are either set or cleared. This allows the CTMU to measure cur- using a fixed time that the current source is applied to rent only during the interval between edges. After both the circuit. status bits are set, it is necessary to clear them before another measurement is taken. Both bits should be 25.1.2 CURRENT SOURCE cleared simultaneously, if possible, to avoid re-enabling At the heart of the CTMU is a precision current source, the CTMU current source. designed to provide a constant reference for measure- In addition to being set by the CTMU hardware, the ments. The level of current is user-selectable across edge status bits can also be set by software. This is three ranges or a total of two orders of magnitude, with also the user’s application to manually enable or the ability to trim the output in ±2% increments disable the current source. Setting either one (but not (nominal). The current range is selected by the both) of the bits enables the current source. Setting or IRNG<1:0> bits (CTMUICON<1:0>), with a value of clearing both bits at once disables the source. ‘01’ representing the lowest range. DS39932D-page 380  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 25.1.5 INTERRUPTS Depending on the type of measurement or pulse generation being performed, one or more additional The CTMU sets its interrupt flag (PIR3<2>) whenever modules may also need to be initialized and configured the current source is enabled, then disabled. An inter- with the CTMU module: rupt is generated only if the corresponding interrupt enable bit (PIE3<2>) is also set. If edge sequencing is • Edge Source Generation: In addition to the not enabled (i.e., Edge 1 must occur before Edge 2), it external edge input pins, both Timer1 and the is necessary to monitor the edge status bits and Output Compare/PWM1 module can be used as determine which edge occurred last and caused the edge sources for the CTMU. interrupt. • Capacitance or Time Measurement: The CTMU module uses the A/D Converter to measure the 25.2 CTMU Module Initialization voltage across a capacitor that is connected to one of the analog input channels. The following sequence is a general guideline used to • Pulse Generation: When generating system clock initialize the CTMU module: independent output pulses, the CTMU module 1. Select the current source range using the IRNG uses Comparator 2 and the associated bits (CTMUICON<1:0>). comparator voltage reference. 2. Adjust the current source trim using the ITRIM bits (CTMUICON<7:2>). 25.3 Calibrating the CTMU Module 3. Configure the edge input sources for Edge 1 and The CTMU requires calibration for precise measure- Edge 2 by setting the EDG1SEL and EDG2SEL ments of capacitance and time, as well as for accurate bits (CTMUCONL<3:2 and 6:5>). time delay. If the application only requires measurement 4. Configure the input polarities for the edge inputs of a relative change in capacitance or time, calibration is using the EDG1POL and EDG2POL bits usually not necessary. An example of this type of appli- (CTMUCONL<4,7>). The default configuration cation would include a capacitive touch switch, in which is for negative edge polarity (high-to-low the touch circuit has a baseline capacitance, and the transitions). added capacitance of the human body changes the 5. Enable edge sequencing using the EDGSEQEN overall capacitance of a circuit. bit (CTMUCONH<2>). By default, edge If actual capacitance or time measurement is required, sequencing is disabled. two hardware calibrations must take place: the current 6. Select the operating mode (Measurement or source needs calibration to set it to a precise current, Time Delay) with the TGEN bit and the circuit being measured needs calibration to (CTMUCONH<4>). The default mode is Time/ measure and/or nullify all other capacitance other than Capacitance Measurement. that to be measured. 7. Discharge the connected circuit by setting the IDISSEN bit (CTMUCONH<1>); after waiting a 25.3.1 CURRENT SOURCE CALIBRATION sufficient time for the circuit to discharge, clear The current source on board the CTMU module has a IDISSEN. range of ±62% nominal for each of three current 8. Disable the module by clearing the CTMUEN bit ranges. Therefore, for precise measurements, it is (CTMUCONH<7>). possible to measure and adjust this current source by 9. Enable the module by setting the CTMUEN bit. placing a high precision resistor, RCAL, onto an unused 10. Clear the Edge Status bits: EDG2STAT and analog channel. An example circuit is shown in EDG1STAT (CTMUCONL<1:0>). Both bits Figure25-2. The current source measurement is should be cleared simultaneously, if possible, to performed using the following steps: avoid re-enabling the CTMU current source. 1. Initialize the A/D Converter. 11. Enable both edge inputs by setting the EDGEN 2. Initialize the CTMU. bit (CTMUCONH<3>). 3. Enable the current source by setting EDG1STAT (CTMUCONL<0>). 4. Issue a time delay for voltage across RCAL to stabilize and the ADC sample/hold capacitor to charge. 5. Perform A/D conversion. 6. Calculate the present source current using I=V/RCAL, where RCAL is a high precision resistance and V is measured by performing an A/D conversion.  2011 Microchip Technology Inc. DS39932D-page 381

PIC18F46J11 FAMILY The CTMU current source may be trimmed with the A value of 70% of full-scale voltage is chosen to make trim bits in CTMUICON using an iterative process to get sure that the A/D Converter is in a range that is well an exact desired current. Alternatively, the nominal above the noise floor. Keep in mind that if an exact cur- value without adjustment may be used; it may be rent is chosen that is to incorporate the trimming bits stored by the software for use in all subsequent from CTMUICON, the resistor value of RCAL may need capacitive or time measurements. to be adjusted accordingly. RCAL may also be adjusted To calculate the optimal value for RCAL, the nominal cur- to allow for available resistor values. RCAL should be of the highest precision available, keeping in mind the rent must be chosen. For example, if the A/D Converter amount of precision needed for the circuit that the reference voltage is 3.3V, use 70% of full scale, or CTMU will be used to measure. A recommended 2.31V as the desired approximate voltage to be read by minimum would be 0.1% tolerance. the A/D Converter. If the range of the CTMU current source is selected to be 0.55 A, the resistor value The following examples show one typical method for needed is calculated as RCAL=2.31V/0.55A, for a performing a CTMU current calibration. Example25-1 value of 4.2MΩ. Similarly, if the current source is cho- demonstrates how to initialize the A/D Converter and sen to be 5.5A, RCAL would be 420,000Ω, and the CTMU; this routine is typical for applications using 42,000Ω if the current source is set to 55A. both modules. Example25-2 demonstrates one method for the actual calibration routine. FIGURE 25-2: CTMU CURRENT SOURCE CALIBRATION CIRCUIT PIC18F46J11 Device CTMU Current Source A/D Converter ANx A/D RCAL MUX DS39932D-page 382  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY EXAMPLE 25-1: SETUP FOR CTMU CALIBRATION ROUTINES #include <p18cxxx.h> /**************************************************************************/ /*Setup CTMU *****************************************************************/ /**************************************************************************/ void setup(void) { //CTMUCON - CTMU Control register CTMUCONH = 0x00; //make sure CTMU is disabled CTMUCONL = 0x90; //CTMU continues to run when emulator is stopped,CTMU continues //to run in idle mode,Time Generation mode disabled, Edges are blocked //No edge sequence order, Analog current source not grounded, trigger //output disabled, Edge2 polarity = positive level, Edge2 source = //source 0, Edge1 polarity = positive level, Edge1 source = source 0, //CTMUICON - CTMU Current Control Register CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment /**************************************************************************/ //Setup AD converter; /**************************************************************************/ TRISA=0x04; //set channel 2 as an input // Configured AN2 as an analog channel // ANCON0 ANCON0 = 0xFB; // ANCON1 ANCON1 = 0x1F; // ADCON1 ADCON1bits.ADFM=1; // Result format 1= Right justified ADCON1bits.ADCAL=0; // Normal A/D conversion operation ADCON1bits.ACQT=1; // Acquisition time 7 = 20TAD 2 = 4TAD 1=2TAD ADCON1bits.ADCS=2; // Clock conversion bits 6= FOSC/64 2=FOSC/32 ANCON1bits.VBGEN=1; // Turn on the Bandgap // ADCON0 ADCON0bits.VCFG0 =0; // Vref+ = AVdd ADCON0bits.VCFG1 =0; // Vref- = AVss ADCON0bits.CHS=2; // Select ADC channel ADCON0bits.ADON=1; // Turn on ADC }  2011 Microchip Technology Inc. DS39932D-page 383

PIC18F46J11 FAMILY EXAMPLE 25-2: CURRENT CALIBRATION ROUTINE #include <p18cxxx.h> #define COUNT 500 //@ 8MHz = 125uS. #define DELAY for(i=0;i<COUNT;i++) #define RCAL .027 //R value is 4200000 (4.2M) //scaled so that result is in //1/100th of uA #define ADSCALE 1023 //for unsigned conversion 10 sig bits #define ADREF 3.3 //Vdd connected to A/D Vr+ int main(void) { int i; int j = 0; //index for loop unsigned int Vread = 0; double VTot = 0; float Vavg=0, Vcal=0, CTMUISrc = 0; //float values stored for calcs //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero CTMUCONLbits.EDG2STAT = 0; for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag VTot += Vread; //Add the reading to the total } Vavg = (float)(VTot/10.000); //Average of 10 readings Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA } DS39932D-page 384  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 25.3.2 CAPACITANCE CALIBRATION An iterative process may need to be used to adjust the time, t, that the circuit is charged to obtain a reasonable There is a small amount of capacitance from the inter- voltage reading from the A/D Converter. The value of t nal A/D Converter sample capacitor as well as stray may be determined by setting COFFSET to a theoretical capacitance from the circuit board traces and pads that value, then solving for t. For example, if CSTRAY is affect the precision of capacitance measurements. A theoretically calculated to be 11pF, and V is expected measurement of the stray capacitance can be taken by to be 70% of VDD, or 2.31V, then t would be: making sure the desired capacitance to be measured has been removed. The measurement is then (4 pF + 11 pF) • 2.31V/0.55 A performed using the following steps: 1. Initialize the A/D Converter and the CTMU. or 63s. 2. Set EDG1STAT (=1). See Example25-3 for a typical routine for CTMU 3. Wait for a fixed delay of time t. capacitance calibration. 4. Clear EDG1STAT. 5. Perform an A/D conversion. 6. Calculate the stray and A/D sample capacitances: C = C +C = ItV OFFSET STRAY AD where I is known from the current source measurement step, t is a fixed delay and V is measured by performing an A/D conversion. This measured value is then stored and used for calculations of time measurement or subtracted for capacitance measurement. For calibration, it is expected that the capacitance of CSTRAY+CAD is approximately known. CAD is approximately 4pF.  2011 Microchip Technology Inc. DS39932D-page 385

PIC18F46J11 FAMILY EXAMPLE 25-3: CAPACITANCE CALIBRATION ROUTINE #include <p18cxxx.h> #define COUNT 25 //@ 8MHz INTFRC = 62.5 us. #define ETIME COUNT*2.5 //time in uS #define DELAY for(i=0;i<COUNT;i++) #define ADSCALE 1023 //for unsigned conversion 10 sig bits #define ADREF 3.3 //Vdd connected to A/D Vr+ #define RCAL .027 //R value is 4200000 (4.2M) //scaled so that result is in //1/100th of uA int main(void) { int i; int j = 0; //index for loop unsigned int Vread = 0; float CTMUISrc, CTMUCap, Vavg, VTot, Vcal; //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero CTMUCONLbits.EDG2STAT = 0; for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag VTot += Vread; //Add the reading to the total } Vavg = (float)(VTot/10.000); //Average of 10 readings Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA CTMUCap = (CTMUISrc*ETIME/Vcal)/100; } DS39932D-page 386  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 25.4 Measuring Capacitance with the 25.4.2 RELATIVE CHARGE CTMU MEASUREMENT An application may not require precise capacitance There are two separate methods of measuring capaci- measurements. For example, when detecting a valid tance with the CTMU. The first is the absolute method, press of a capacitance-based switch, detecting a rela- in which the actual capacitance value is desired. The tive change of capacitance is of interest. In this type of second is the relative method, in which the actual application, when the switch is open (or not touched), capacitance is not needed, rather an indication of a the total capacitance is the capacitance of the combina- change in capacitance is required. tion of the board traces, the A/D Converter, etc. A larger 25.4.1 ABSOLUTE CAPACITANCE voltage will be measured by the A/D Converter. When MEASUREMENT the switch is closed (or is touched), the total capacitance is larger due to the addition of the For absolute capacitance measurements, both the capacitance of the human body to the above listed current and capacitance calibration steps found in capacitances, and a smaller voltage will be measured Section 25.3 “Calibrating the CTMU Module” by the A/D Converter. should be followed. Capacitance measurements are Detecting capacitance changes is easily accomplished then performed using the following steps: with the CTMU using these steps: 1. Initialize the A/D Converter. 1. Initialize the A/D Converter and the CTMU. 2. Initialize the CTMU. 2. Set EDG1STAT. 3. Set EDG1STAT. 3. Wait for a fixed delay. 4. Wait for a fixed delay, T. 4. Clear EDG1STAT. 5. Clear EDG1STAT. 5. Perform an A/D conversion. 6. Perform an A/D conversion. The voltage measured by performing the A/D conver- 7. Calculate the total capacitance, CTOTAL = (I * T)/V, sion is an indication of the relative capacitance. Note where I is known from the current source that in this case, no calibration of the current source or measurement step (see Section 25.3.1 “Current circuit capacitance measurement is needed. See Source Calibration”), T is a fixed delay and V is Example25-4 for a sample software routine for a measured by performing an A/D conversion. capacitive touch switch. 8. Subtract the stray and A/D capacitance (COFFSET from Section 25.3.2 “Capacitance Calibration”) from CTOTAL to determine the measured capacitance.  2011 Microchip Technology Inc. DS39932D-page 387

PIC18F46J11 FAMILY EXAMPLE 25-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include <p18cxxx.h> #define COUNT 500 //@ 8MHz = 125uS. #define DELAY for(i=0;i<COUNT;i++) #define OPENSW 1000 //Un-pressed switch value #define TRIP 300 //Difference between pressed //and un-pressed switch #define HYST 65 //amount to change //from pressed to un-pressed #define PRESSED 1 #define UNPRESSED 0 int main(void) { unsigned int Vread; //storage for reading unsigned int switchState; int i; //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; // Enable the CTMU CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero CTMUCONLbits.EDG2STAT = 0; CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D if(Vread < OPENSW - TRIP) { switchState = PRESSED; } else if(Vread > OPENSW - TRIP + HYST) { switchState = UNPRESSED; } } DS39932D-page 388  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 25.5 Measuring Time with the CTMU It is assumed that the time measured is small enough Module that the capacitance, CAD + CEXT, provides a valid volt- age to the A/D Converter. For the smallest time mea- Time can be precisely measured after the ratio (C/I) is surement, always set the A/D Channel Select register measured from the current and capacitance calibration (AD1CHS) to an unused A/D channel; the correspond- step by following these steps: ing pin for which is not connected to any circuit board 1. Initialize the A/D Converter and the CTMU. trace. This minimizes added stray capacitance, keep- ing the total circuit capacitance close to that of the A/D 2. Set EDG1STAT. Converter itself (4-5pF). To measure longer time 3. Set EDG2STAT. intervals, an external capacitor may be connected to an 4. Perform an A/D conversion. A/D channel and this channel selected when making a 5. Calculate the time between edges as T = (C/I) * V, time measurement. where I is calculated in the current calibration step (Section 25.3.1 “Current Source Calibration”), C is calculated in the capacitance calibration step (Section 25.3.2 “Capacitance Calibration”) and V is measured by performing the A/D conversion. FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC18F46J11 CTMU CTED1 EDG1 Current Source CTED2 EDG2 A/D Converter ANX CAD CEXT  2011 Microchip Technology Inc. DS39932D-page 389

PIC18F46J11 FAMILY 25.6 Creating a Delay with the CTMU An example use of this feature is for interfacing with Module variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the pulse width output A unique feature on board the CTMU module is its on CTPLS will vary. The CTPLS output pin can be con- ability to generate system clock independent output nected to an input capture pin and the varying pulse pulses based on an external capacitor value. This is width is measured to determine the humidity in the accomplished using the internal comparator voltage application. reference module, Comparator 2 input pin and an Follow these steps to use this feature: external capacitor. The pulse is output onto the CTPLS pin. To enable this mode, set the TGEN bit. 1. Initialize Comparator 2. 2. Set CPOL = 1. See Figure25-4 for an example circuit. CPULSE is chosen by the user to determine the output pulse width 3. Initialize the comparator voltage reference. on CTPLS. The pulse width is calculated by 4. Initialize the CTMU and enable time delay T=(CPULSE/I)*V, where I is known from the current generation by setting the TGEN bit. source measurement step (Section 25.3.1 “Current 5. Set EDG1STAT. Source Calibration”) and V is the internal reference 6. When CPULSE charges to the value of the voltage voltage (CVREF). reference trip point, an output pulse is generated on CTPLS. FIGURE 25-4: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC18F46J11 Device CTMU CTED1 EDG1 CTPLS Current Source Comparator C2INB C2 CPULSE CVREF 25.7 Operation During Sleep/Idle module is performing an operation when Idle mode is Modes invoked, in this case, the results will be similar to those with Sleep mode. 25.7.1 SLEEP MODE AND DEEP SLEEP MODES 25.8 Effects of a Reset on CTMU When the device enters any Sleep mode, the CTMU Upon Reset, all registers of the CTMU are cleared. This module current source is always disabled. If the CTMU leaves the CTMU module disabled, its current source is is performing an operation that depends on the current turned off and all configuration options return to their source when Sleep mode is invoked, the operation may default settings. The module needs to be re-initialized not terminate correctly. Capacitance and time following any Reset. measurements may return erroneous values. If the CTMU is in the process of taking a measurement at the time of Reset, the measurement will be lost. A partial 25.7.2 IDLE MODE charge may exist on the circuit that was being measured, The behavior of the CTMU in Idle mode is determined and should be properly discharged before the CTMU by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL makes subsequent attempts to make a measurement. is cleared, the module will continue to operate in Idle The circuit is discharged by setting and then clearing the mode. If CTMUSIDL is set, the module’s current source IDISSEN bit (CTMUCONH<1>) while the A/D Converter is disabled when the device enters Idle mode. If the is connected to the appropriate channel. DS39932D-page 390  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 25.9 Registers The CTMUCONH and CTMUCONL registers (Register25-1 and Register25-2) contain control bits There are three control registers for the CTMU: for configuring the CTMU module edge source selec- • CTMUCONH tion, edge source polarity selection, edge sequencing, • CTMUCONL A/D trigger, analog circuit capacitor discharge and enables. The CTMUICON register (Register25-3) has • CTMUICON bits for selecting the current source range and current source trim. REGISTER 25-1: CTMUCONH: CTMU CONTROL REGISTER HIGH (ACCESS FB3h) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 4 TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation bit 3 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 2 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 1 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 0 Reserved: Write as ‘0’  2011 Microchip Technology Inc. DS39932D-page 391

PIC18F46J11 FAMILY REGISTER 25-2: CTMUCONL: CTMU CONTROL REGISTER LOW (ACCESS FB2h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x R/W-x EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = ECCP2 Special Event Trigger bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = ECCP2 Special Event Trigger bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred DS39932D-page 392  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 25-3: CTMUICON: CTMU CURRENT CONTROL REGISTER (ACCESS FB1h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current bit 1-0 IRNG<1:0>: Current Source Range Select bits 11 = 100  Base current 10 = 10  Base current 01 = Base current level (0.55A nominal) 00 = Current source disabled TABLE 25-1: REGISTERS ASSOCIATED WITH CTMU MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page: CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN — 71 CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 71 CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 71 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.  2011 Microchip Technology Inc. DS39932D-page 393

PIC18F46J11 FAMILY NOTES: DS39932D-page 394  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 26.0 SPECIAL FEATURES OF THE 26.1.1 CONSIDERATIONS FOR CPU CONFIGURING THE PIC18F46J11 FAMILY DEVICES PIC18F46J11 family devices include several features Unlike some previous PIC18 microcontrollers, devices intended to maximize reliability and minimize cost of the PIC18F46J11 family do not use persistent mem- through elimination of external components. These are: ory registers to store configuration information. The • Oscillator Selection Configuration registers, CONFIG1L through • Resets: CONFIG4H, are implemented as volatile memory. - Power-on Reset (POR) Immediately after power-up, or after a device Reset, - Power-up Timer (PWRT) the microcontroller hardware automatically loads the - Oscillator Start-up Timer (OST) CONFIG1L through CONFIG4L registers with configu- - Brown-out Reset (BOR) ration data stored in nonvolatile Flash program memory. The last four words of Flash program memory, • Interrupts known as the Flash Configuration Words (FCW), are • Watchdog Timer (WDT) used to store the configuration data. • Fail-Safe Clock Monitor (FSCM) Table26-1 provides the Flash program memory, which • Two-Speed Start-up will be loaded into the corresponding Configuration • Code Protection register. • In-Circuit Serial Programming (ICSP) When creating applications for these devices, users The oscillator can be configured for the application should always specifically allocate the location of the depending on frequency, power, accuracy and cost. All FCW for configuration data. This is to make certain that of the options are discussed in detail in Section3.0 program code is not stored in this address when the “Oscillator Configurations”. code is compiled. A complete discussion of device Resets and interrupts The four Most Significant bits (MSb) of the FCW corre- is available in previous sections of this data sheet. In sponding to CONFIG1H, CONFIG2H, CONFIG3H and addition to their Power-up and Oscillator Start-up CONFIG4H should always be programmed to ‘1111’. Timers provided for Resets, the PIC18F46J11 family of This makes these FCWs appear to be NOP instructions devices have a configurable Watchdog Timer (WDT), in the remote event that their locations are ever which is controlled in software. executed by accident. The inclusion of an internal RC oscillator also provides To prevent inadvertent configuration changes during the additional benefits of a Fail-Safe Clock Monitor code execution, the Configuration registers, (FSCM) and Two-Speed Start-up. FSCM provides for CONFIG1L through CONFIG4L, are loaded only once background monitoring of the peripheral clock and per power-up or Reset cycle. User’s firmware can still automatic switchover in the event of its failure. change the configuration by using self-reprogramming Two-Speed Start-up enables code to be executed to modify the contents of the FCW. almost immediately on start-up, while the primary clock source completes its start-up delays. Modifying the FCW will not change the active contents being used in the CONFIG1L through CONFIG4H All of these features are enabled and configured by registers until after the device is reset. setting the appropriate Configuration register bits. 26.1 Configuration Bits The Configuration bits can be programmed to select various device configurations. The configuration data is stored in the last four words of Flash program memory; Figure6-1 depicts this. The configuration data gets loaded into the volatile Configuration registers, CONFIG1L through CONFIG4H, which are readable and mapped to program memory starting at location 300000h. Table26-2 provides a complete list. A detailed explana- tion of the various bit functions is provided in Register26-1 through Register26-6.  2011 Microchip Technology Inc. DS39932D-page 395

PIC18F46J11 FAMILY TABLE 26-1: MAPPING OF THE FLASH CONFIGURATION WORDS TO THE CONFIGURATION REGISTERS Configuration Register Configuration Register Flash Configuration Byte Address (Volatile) Address CONFIG1L 300000h XXXF8h CONFIG1H 300001h XXXF9h CONFIG2L 300002h XXXFAh CONFIG2H 300003h XXXFBh CONFIG3L 300004h XXXFCh CONFIG3H 300005h XXXFDh CONFIG4L 300006h XXXFEh CONFIG4H 300007h XXXFFh TABLE 26-2: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprog. Value(1) 300000h CONFIG1L DEBUG XINST STVREN — — — — WDTEN 111- ---1 300001h CONFIG1H —(2) —(2) —(2) —(2) — CP0 — — 1111 -1-- 300002h CONFIG2L IESO FCMEN — LPT1OSC T1DIG FOSC2 FOSC1 FOSC0 11-1 1111 300003h CONFIG2H —(2) —(2) —(2) —(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 1111 1111 300004h CONFIG3L DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 DSWDTEN DSBOREN RTCOSC DSWDTOSC 1111 1111 300005h CONFIG3H —(2) —(2) —(2) —(2) MSSPMSK — — IOL1WAY 1111 1--1 300006h CONFIG4L WPCFG WPEND WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0 1111 1111 300007h CONFIG4H —(2) —(2) —(2) —(2) — — — WPDIS 1111 ---1 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxx0 0000(3) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0100 00xx(3) Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’. Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the configuration bytes maintain their previously programmed states. 2: The value of these bits in program memory should always be programmed to ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed. 3: See Register26-9 and Register26-10 for DEVID values. These registers are read-only and cannot be programmed by the user. DS39932D-page 396  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 26-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-1 U-0 U-1 U-1 U-1 R/WO-1 DEBUG XINST STVREN — — — — WDTEN bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled bit 5 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled bit 4-1 Unimplemented: Read as ‘0’ bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit)  2011 Microchip Technology Inc. DS39932D-page 397

PIC18F46J11 FAMILY REGISTER 26-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-1 U-1 U-1 U-1 U-0 R/WO-1 U-0 U-0 — — — — — CP0 — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3 Unimplemented: Maintain as ‘0’ bit 2 CP0: Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is code-protected bit 1-0 Unimplemented: Maintain as ‘0’ DS39932D-page 398  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 26-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/WO-1 R/WO-1 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 IESO FCMEN — LPT1OSC T1DIG FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5 Unimplemented: Read as ‘0’ bit 4 LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 oscillator configured for high-power operation 0 = Timer1 oscillator configured for low-power operation bit 3 T1DIG: Secondary Clock Source T1OSCEN Enforcement bit 1 = Secondary oscillator clock source may be selected (OSCCON<1:0> = 01) regardless of the T1OSCEN (T1CON<3>) state 0 = Secondary oscillator clock source may not be selected unless T1CON<3> = 1 bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = ECPLL oscillator with PLL software controlled, CLKO on RA6 110 = EC oscillator with CLKO on RA6 101 = HSPLL oscillator with PLL software controlled 100 = HS oscillator 011 = INTOSCPLLO, internal oscillator with PLL software controlled, CLKO on RA6, port function on RA7 010 = INTOSCPLL, internal oscillator with PLL software controlled, port function on RA6 and RA7 001 = INTOSCO internal oscillator block (INTRC/INTOSC) with CLKO on RA6, port function on RA7 000 = INTOSC internal oscillator block (INTRC/INTOSC), port function on RA6 and RA7  2011 Microchip Technology Inc. DS39932D-page 399

PIC18F46J11 FAMILY REGISTER 26-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 — — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 DS39932D-page 400  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 26-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 DSWDTPS3(1) DSWDTPS2(1) DSWDTPS1(1)DSWDTPS0(1)DSWDTEN(1) DSBOREN(1) RTCOSC DSWDTOSC(1) bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 DSWDTPS<3:0>: Deep Sleep Watchdog Timer Postscale Select bits(1) The DSWDT prescaler is 32. This creates an approximate base time unit of 1ms. 1111 = 1:2,147,483,648 (25.7 days) 1110 = 1:536,870,912 (6.4 days) 1101 = 1:134,217,728 (38.5 hours) 1100 = 1:33,554,432 (9.6 hours) 1011 = 1:8,388,608 (2.4 hours) 1010 = 1:2,097,152 (36 minutes) 1001 = 1:524,288 (9 minutes) 1000 = 1:131,072 (135 seconds) 0111 = 1:32,768 (34 seconds) 0110 = 1:8,192 (8.5 seconds) 0101 = 1:2,048 (2.1 seconds) 0100 = 1:512 (528 ms) 0011 = 1:128 (132 ms) 0010 = 1:32 (33 ms) 0001 = 1:8 (8.3 ms) 0000 = 1:2 (2.1 ms) bit 3 DSWDTEN: Deep Sleep Watchdog Timer Enable bit(1) 1 = DSWDT enabled 0 = DSWDT disabled bit 2 DSBOREN: Deep Sleep BOR Enable bit(1) 1 = BOR enabled in Deep Sleep (when using PIC18FXXJXX device) 0 = BOR disabled in Deep Sleep (does not affect operation in non Deep Sleep modes) bit 1 RTCOSC: RTCC Reference Clock Select bit 1 = RTCC uses T1OSC/T1CKI as reference clock 0 = RTCC uses INTRC as reference clock bit 0 DSWDTOSC: DSWDT Reference Clock Select bit(1) 1 = DSWDT uses INTRC as reference clock 0 = DSWDT uses T1OSC/T1CKI as reference clock Note 1: Deep Sleep bits are not available on “LF” devices.  2011 Microchip Technology Inc. DS39932D-page 401

PIC18F46J11 FAMILY REGISTER 26-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-1 U-1 U-1 U-1 R/WO-1 U-0 U-0 R/WO-1 — — — — MSSPMSK — — IOL1WAY bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3 MSSPMSK: MSSP 7-Bit Address Masking Mode Enable bit 1 = 7-Bit Address Masking mode enabled 0 = 5-Bit Address Masking mode enabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 IOL1WAY: IOLOCK One-Way Set Enable bit 1 = IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the unlock sequence has been completed REGISTER 26-7: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 WPCFG WPEND WPFP5(2) WPFP4(3) WPFP3 WPFP2 WPFP1 WPFP0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WPCFG: Write/Erase Protect Configuration Region Select bit 1 = Configuration Words page is not erase/write-protected, unless WPEND and WPFP<5:0> settings protect the Configuration Words page(1) 0 = Configuration Words page is erase/write-protected, regardless of WPEND and WPFP<5:0>(1) bit 6 WPEND: Write/Erase Protect Region Select bit 1 = Flash pages WPFP<5:0> through Configuration Words page are erase/write-protected 0 = Flash pages 0 through WPFP<5:0> are erase/write-protected bit 5-0 WPFP<5:0>: Write/Erase Protect Page Start/End Location bits Used with WPEND bit to define which pages in Flash will be erase/write-protected. Note 1: The “Configuration Words page” contains the FCWs and is the last page of implemented Flash memory on a given device. Each page consists of 1,024 bytes. For example, on a device with 64Kbytes of Flash, the first page is 0 and the last page (Configuration Words page) is 63 (3Fh). 2: Not available on 32K and 16K devices. 3: Not available on 16K devices. DS39932D-page 402  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY REGISTER 26-8: CONFIG4H: CONFIGURATION REGISTER 4 HIGH (BYTE ADDRESS 300007h) U-1 U-1 U-1 U-1 U-0 U-0 U-0 R/WO-1 — — — — — — — WPDIS bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3-1 Unimplemented: Read as ‘0’ bit 0 WPDIS: Write-Protect Disable bit 1 = WPFP<5:0>/WPEND region ignored 0 = WPFP<5:0>/WPEND region erase/write-protected REGISTER 26-9: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F46J11 FAMILY DEVICES (BYTE ADDRESS 3FFFFEh) R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 DEV<2:0>: Device ID bits These bits are used with DEV<10:3> bits in Device ID Register 2 to identify the part number. See Register26-10. bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision.  2011 Microchip Technology Inc. DS39932D-page 403

PIC18F46J11 FAMILY REGISTER 26-10: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F46J11 FAMILY DEVICES (BYTE ADDRESS 3FFFFFh) R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 DEV<10:3>: Device ID bits These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. DEV<10:3> DEV<2:0> Device (DEVID2<7:0>) (DEVID1<7:5>) 0100 1110 001 PIC18F46J11 0100 1110 000 PIC18F45J11 0100 1101 111 PIC18F44J11 0100 1101 110 PIC18F26J11 0100 1101 101 PIC18F25J11 0100 1101 100 PIC18F24J11 0100 1110 111 PIC18LF46J11 0100 1110 110 PIC18LF45J11 0100 1110 101 PIC18LF44J11 0100 1110 100 PIC18LF26J11 0100 1110 011 PIC18LF25J11 0100 1110 010 PIC18LF24J11 DS39932D-page 404  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 26.2 Watchdog Timer (WDT) whenever a SLEEP or CLRWDT instruction is executed, or a clock failure (primary or Timer1 oscillator) has PIC18F46J11 family devices have both a conventional occurred. WDT circuit and a dedicated, Deep Sleep capable Watchdog Timer. When enabled, the conventional Note1: The CLRWDT and SLEEP instructions WDT operates in normal Run, Idle and Sleep modes. clear the WDT and postscaler counts This data sheet section describes the conventional when executed. WDT circuit. 2: When a CLRWDT instruction is executed, The dedicated, Deep Sleep capable WDT can only be the postscaler count will be cleared. enabled in Deep Sleep mode. This timer is described in Section4.6.4 “Deep Sleep Watchdog Timer 26.2.1 CONTROL REGISTER (DSWDT)”. The WDTCON register (Register26-11) is a readable The conventional WDT is driven by the INTRC oscilla- and writable register. The SWDTEN bit enables or dis- tor. When the WDT is enabled, the clock source is also ables WDT operation. This allows software to override enabled. The nominal WDT period is 4ms and has the the WDTEN Configuration bit and enable the WDT only same stability as the INTRC oscillator. if it has been disabled by the Configuration bit. The 4ms period of the WDT is multiplied by a 16-bit LVDSTAT is a read-only status bit that is continuously postscaler. Any output of the WDT postscaler is updated and provides information about the current selected by a multiplexer, controlled by the WDTPS bits level of VDDCORE. This bit is only valid when the on-chip in Configuration Register 2H. Available periods range voltage regulator is enabled. from about 4ms to 135seconds (2.25 minutes depending on voltage, temperature and WDT postscaler). The WDT and postscaler are cleared FIGURE 26-1: WDT BLOCK DIAGRAM Enable WDT SWDTEN INTRC Control WDT Counter INTRC Oscillator 128 Wake-up from Power-Managed Modes CLRWDT Programmable Postscaler Reset WDT Reset All Device Resets 1:1 to 1:32,768 WDT 4 WDTPS<3:0> Sleep  2011 Microchip Technology Inc. DS39932D-page 405

PIC18F46J11 FAMILY REGISTER 26-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ACCESS FC0h) R/W-1 R-x R-x U-0 R-0 R/W-0 R/W-0 R/W-0 REGSLP(2) LVDSTAT(2) ULPLVL — DS(2) ULPEN ULPSINK SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 REGSLP: Voltage Regulator Low-Power Operation Enable bit(2) 1 = On-chip regulator enters low-power operation when device enters Sleep mode 0 = On-chip regulator is active even in Sleep mode bit 6 LVDSTAT: Low-Voltage Detect Status bit(2) 1 = VDDCORE > 2.45V nominal 0 = VDDCORE < 2.45V nominal bit 5 ULPLVL: Ultra Low-Power Wake-up Output bit (not valid unless ULPEN = 1) 1 = Voltage on RA0 > ~0.5V 0 = Voltage on RA0 < ~0.5V bit 4 Unimplemented: Read as ‘0’ bit 3 DS: Deep Sleep Wake-up Status bit (used in conjunction with RCON, POR and BOR bits to determine Reset source)(2) 1 = If the last exit from POR was caused by a normal wake-up from Deep Sleep 0 = If the last exit from POR was a result of hard cycling VDD, or if the Deep Sleep BOR was enabled and detected, a (VDD < VDSBOR) and (VDD < VPOR) condition bit 2 ULPEN: Ultra Low-Power Wake-up Module Enable bit 1 = Ultra Low-Power Wake-up module is enabled; ULPLVL bit indicates comparator output 0 = Ultra Low-Power Wake-up module is disabled bit 1 ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit 1 = Ultra Low-Power Wake-up current sink is enabled (if ULPEN = 1) 0 = Ultra Low-Power Wake-up current sink is disabled bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled. 2: Not available on devices where the on-chip voltage regulator is disabled (“LF” devices). TABLE 26-3: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page: RCON IPEN — CM RI TO PD POR BOR 70 WDTCON REGSLP LVDSTAT ULPLVL — DS ULPEN ULPSINK SWDTEN 70 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer. DS39932D-page 406  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 26.3 On-Chip Voltage Regulator On “LF” devices, the on-chip regulator is always disabled. This allows the device to save a small amount Note1: The on-chip voltage regulator is only of quiescent current consumption, which may be available in parts designated with an “F”, advantageous in some types of applications, such as such as PIC18F25J11. The on-chip those which will entirely be running at a nominal 2.5V. regulator is disabled on devices with “LF” On PIC18LF46J11 family devices, the VDDCORE/VCAP in their part number. pin still serves as the core logic power supply input pin, 2: The VDDCORE/VCAP pin must never be and therefore, must be connected to a 2.0V to 2.7V left floating. On “F” devices, it must be supply rail at the application circuit board level. On connected to a capacitor, of size CEFC, to these devices, the I/O pins may still optionally be sup- ground. On “LF” devices, VDDCORE/VCAP plied with a voltage between 2.0V to 3.6V, provided that must be connected to a power supply VDD is always greater than, or equal to, source between 2.0V and 2.7V. VDDCORE/VCAP. For example connections for PIC18F and PIC18LF devices, see Figure26-2. The digital core logic of the PIC18F46J11 family Note: In parts designated with an “LF”, such as devices is designed on an advanced manufacturing PIC18LF46J11, VDDCORE must never process, which requires 2.0V to 2.7V. The digital core exceed VDD. logic obtains power from the VDDCORE/VCAP power supply pin. The specifications for core voltage and capacitance are listed in Section29.3 “DC Characteristics: However, in many applications it may be inconvenient PIC18F46J11 Family (Industrial)”. to run the I/O pins at the same core logic voltage, as it would restrict the ability of the device to interface with 26.3.1 VOLTAGE REGULATOR TRACKING other, higher voltage devices, such as those run at a MODE AND LOW-VOLTAGE nominal 3.3V. Therefore, all PIC18F46J11 family DETECTION devices implement a dual power supply rail topology. The core logic obtains power from the VDDCORE/VCAP When it is enabled, the on-chip regulator provides a con- pin, while the general purpose I/O pins obtain power stant voltage of 2.5V nominal to the digital core logic. from the VDD pin of the microcontroller, which may be The regulator can provide this level from a VDD of about supplied with a voltage between 2.15V to 3.6V (“F” 2.5V, all the way up to the device’s VDDMAX. It does not devices) or 2.0V to 3.6V (“LF” devices). have the capability to boost VDD levels below 2.5V. This dual supply topology allows the microcontroller to When the VDD supply input voltage drops too low to interface with standard 3.3V logic devices, while regulate to 2.5V, the regulator enters Tracking mode. In running the core logic at a lower voltage of nominally Tracking mode, the regulator output follows VDD, with a 2.5V. typical voltage drop of 100mV or less. In order to make the microcontroller more convenient to The on-chip regulator includes a simple, Low-Voltage use, an integrated 2.5V low dropout, low quiescent Detect (LVD) circuit. This circuit is separate and inde- current linear regulator has been integrated on the die pendent of the High/Low-Voltage Detect (HLVD) module inside PIC18F46J11 family devices. This regulator is described in Section24.0 “High/Low Voltage Detect designed specifically to supply the core logic of the (HLVD)”. The on-chip regulator LVD circuit continuously device. It allows PIC18F46J11 family devices to monitors the VDDCORE voltage level and updates the effectively run from a single power supply rail, without LVDSTAT bit in the WDTCON register. The LVD detect the need for external regulators. threshold is set slightly below the normal regulation set point of the on-chip regulator. The on-chip voltage regulator is always enabled on “F” devices. The VDDCORE/VCAP pin serves simultaneously Application firmware may optionally poll the LVDSTAT as the regulator output pin and the core logic supply bit to determine when it is safe to run at the maximum power input pin. A capacitor should be connected to the rated frequency, so as not to inadvertently violate the VDDCORE/VCAP pin to ground and is necessary for regu- voltage versus frequency requirements provided by lator stability. For example connections for PIC18F and Figure29-1. PIC18LF devices, see Figure26-2. The VDDCORE monitoring LVD circuit is only active when the on-chip regulator is enabled. On “LF” devices, the Analog-to-Digital Converter and the HLVD module can still be used to provide firmware with VDD and VDDCORE voltage level information.  2011 Microchip Technology Inc. DS39932D-page 407

PIC18F46J11 FAMILY FIGURE 26-2: CONNECTIONS FOR THE 26.3.2 ON-CHIP REGULATOR AND BOR ON-CHIP REGULATOR When the on-chip regulator is enabled, PIC18F46J11 PIC18FXXJ11 Devices (Regulator Enabled): family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to 3.3V maintain a minimum output level; the regulator Reset PIC18FXXJ11 circuitry will generate a Brown-out Reset (BOR). This event is captured by the BOR flag bit (RCON<0>). VDD The operation of the BOR is described in more detail in VDDCORE/VCAP Section5.4 “Brown-out Reset (BOR)” and CEFC Section5.4.1 “Detecting BOR”. The brown-out voltage VSS levels are specific in Section29.1 “DC Characteristics: Supply Voltage PIC18F46J11 Family (Industrial)”. 26.3.3 POWER-UP REQUIREMENTS PIC18LFXXJ11 Devices (Regulator Disabled): 2.5V The on-chip regulator is designed to meet the power-up PIC18LFXXJ11 requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE should not VDD exceed VDD by 0.3 volts. VDDCORE/VCAP 26.3.4 OPERATION IN SLEEP MODE VSS When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD. This OR includes when the device is in Sleep mode, even though the core digital logic does not require much 2.5V 3.3V power. To provide additional savings in applications PIC18LFXXJ11 where power resources are critical, the regulator can be configured to automatically enter a lower quiescent VDD draw standby mode whenever the device goes into Sleep mode. This feature is controlled by the REGSLP VDDCORE/VCAP bit (WDTCON<7>, Register26-11). If this bit is set VSS upon entry into Sleep mode, the regulator will transition into a lower power state. In this state, the regulator still provides a regulated output voltage necessary to maintain SRAM state information, but consumes less quiescent current. Substantial Sleep mode power savings can be obtained by setting the REGSLP bit, but device wake-up time will increase in order to insure the regulator has enough time to stabilize. DS39932D-page 408  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 26.4 Two-Speed Start-up When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the inter- The Two-Speed Start-up feature helps to minimize the nal oscillator block as the clock source, following the latency period, from oscillator start-up to code execu- time-out of the Power-up Timer after a Power-on Reset tion, by allowing the microcontroller to use the INTRC is enabled. This allows almost immediate code oscillator as a clock source until the primary clock execution while the primary oscillator starts and the source is available. It is enabled by setting the IESO OST is running. Once the OST times out, the device Configuration bit. automatically switches to PRI_RUN mode. Two-Speed Start-up should be enabled only if the In all other power-managed modes, Two-Speed primary oscillator mode is HS or HSPLL Start-up is not used. The device will be clocked by the (Crystal-Based) modes. Since the EC and ECPLL currently selected clock source until the primary clock modes do not require an Oscillator Start-up Timer source becomes available. The setting of the IESO bit (OST) delay, Two-Speed Start-up should be disabled. is ignored. FIGURE 26-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake from Interrupt Event OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 26.4.1 SPECIAL CONSIDERATIONS FOR 26.5 Fail-Safe Clock Monitor USING TWO-SPEED START-UP The Fail-Safe Clock Monitor (FSCM) allows the While using the INTRC oscillator in Two-Speed microcontroller to continue operation in the event of an Start-up, the device still obeys the normal command external oscillator failure by automatically switching the sequences for entering power-managed modes, device clock to the internal oscillator block. The FSCM including serial SLEEP instructions (refer to function is enabled by setting the FCMEN Configuration Section4.1.4 “Multiple Sleep Commands”). In bit. practice, this means that user code can change the When FSCM is enabled, the INTRC oscillator runs at SCS<1:0> bit settings or issue SLEEP instructions all times to monitor clocks to peripherals and provide a before the OST times out. This would allow an applica- backup clock in the event of a clock failure. Clock tion to briefly wake-up, perform routine “housekeeping” monitoring (shown in Figure26-4) is accomplished by tasks and return to Sleep before the device starts to creating a sample clock signal, which is the INTRC out- operate from the primary oscillator. put divided by 64. This allows ample time between User code can also check if the primary clock source is FSCM sample clocks for a peripheral clock edge to currently providing the device clocking by checking the occur. The peripheral device clock and the sample status of the OSTS bit (OSCCON<3>). If the bit is set, clock are presented as inputs to the clock monitor latch. the primary oscillator is providing the clock. Otherwise, The clock monitor is set on the falling edge of the the internal oscillator block is providing the clock during device clock source but cleared on the rising edge of wake-up from Reset or Sleep mode. the sample clock.  2011 Microchip Technology Inc. DS39932D-page 409

PIC18F46J11 FAMILY FIGURE 26-4: FSCM BLOCK DIAGRAM be desirable to select another clock configuration and enter an alternate power-managed mode. This can be Clock Monitor Latch done to attempt a partial recovery or execute a (edge-triggered) controlled shutdown. See Section4.1.4 “Multiple Peripheral Sleep Commands” and Section26.4.1 “Special S Q Clock Considerations for Using Two-Speed Start-up” for more details. The FSCM will detect failures of the primary or secondary INTRC Source ÷ 64 C Q clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be (32 s) 488 Hz possible. (2.048 ms) 26.5.1 FSCM AND THE WATCHDOG TIMER Clock Failure Both the FSCM and the WDT are clocked by the Detected INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has Clock failure is tested for on the falling edge of the no effect on the operation of the INTRC oscillator when sample clock. If a sample clock falling edge occurs the FSCM is enabled. while the clock monitor is still set, and a clock failure As already noted, the clock source is switched to the has been detected (Figure26-5), the following results: INTRC clock when a clock failure is detected; this may • The FSCM generates an oscillator fail interrupt by mean a substantial change in the speed of code execu- setting bit, OSCFIF (PIR2<7>); tion. If the WDT is enabled with a small prescale value, • The device clock source is switched to the internal a decrease in clock speed allows a WDT time-out to oscillator block (OSCCON is not updated to show occur and a subsequent device Reset. For this reason, the current clock source – this is the Fail-safe Fail-Safe Clock Monitor events also reset the WDT and condition); and postscaler, allowing it to start timing from when execu- • The WDT is reset. tion speed was changed and decreasing the likelihood of an erroneous time-out. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing-sensitive applications. In these cases, it may FIGURE 26-5: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Clock Monitor Test Clock Monitor Test Clock Monitor Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS39932D-page 410  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 26.5.2 EXITING FAIL-SAFE OPERATION out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to The Fail-Safe Clock Monitor condition is terminated by its role as the FSCM source. either a device Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock Note: The same logic that prevents false source specified in Configuration Register 2H (with any oscillator failure interrupts on POR, or required start-up delays that are required for the oscil- wake-up from Sleep, will also prevent the lator mode, such as OST or PLL timer). The INTRC detection of the oscillator’s failure to start oscillator provides the device clock until the primary at all following these events. This can be clock source becomes ready (similar to a Two-Speed avoided by monitoring the OSTS bit and Start-up). The clock source is then switched to the using a timing routine to determine if the primary clock (indicated by the OSTS bit in the oscillator is taking too long to start. Even OSCCON register becoming set). The FSCM then so, no oscillator failure interrupt will be resumes monitoring the peripheral clock. flagged. The primary clock source may never become ready As noted in Section26.4.1 “Special Considerations during start-up. In this case, operation is clocked by the for Using Two-Speed Start-up”, it is also possible to INTRC oscillator. The OSCCON register will remain in select another clock configuration and enter an alternate its Reset state until a power-managed mode is entered. power-managed mode while waiting for the primary clock to become stable. When the new power-managed 26.5.3 FSCM INTERRUPTS IN mode is selected, the primary clock is disabled. POWER-MANAGED MODES By entering a power-managed mode, the clock 26.6 Program Verification and Code multiplexer selects the clock source selected by the Protection OSCCON register. FSCM of the power-managed clock source resumes in the power-managed mode. For all devices in the PIC18F46J11 family of devices, If an oscillator failure occurs during power-managed the on-chip program memory space is treated as a operation, the subsequent events depend on whether single block. Code protection for this block is controlled or not the oscillator failure interrupt is enabled. If by one Configuration bit, CP0. This bit inhibits external reads and writes to the program memory space. It has enabled (OSCFIF=1), code execution will be clocked by the INTRC multiplexer. An automatic transition back no direct effect in normal execution mode. to the failed clock source will not occur. 26.6.1 CONFIGURATION REGISTER If the interrupt is disabled, subsequent interrupts while PROTECTION in Idle mode will cause the CPU to begin executing The Configuration registers are protected against instructions while being clocked by the INTRC source. untoward changes or reads in two ways. The primary 26.5.4 POR OR WAKE-UP FROM SLEEP protection is the write-once feature of the Configuration bits, which prevents reconfiguration once the bit has The FSCM is designed to detect oscillator failure at any been programmed during a power cycle. To safeguard point after the device has exited Power-on Reset (POR) against unpredictable events, Configuration bit or low-power Sleep mode. When the primary device changes resulting from individual cell level disruptions clock is either the EC or INTRC modes, monitoring can (such as ESD events) will cause a parity error and begin immediately following these events. trigger a device Reset. This is seen by the user as a For HS or HSPLL modes, the situation is somewhat Configuration Mismatch (CM) Reset. different. Since the oscillator may require a start-up The data for the Configuration registers is derived from time considerably longer than the FSCM sample clock the FCW in program memory. When the CP0 bit is set, time, a false clock failure may be detected. To prevent the source data for device configuration is also this, the internal oscillator block is automatically config- protected as a consequence. ured as the device clock and functions until the primary clock is stable (the OST and PLL timers have timed  2011 Microchip Technology Inc. DS39932D-page 411

PIC18F46J11 FAMILY 26.7 In-Circuit Serial Programming 26.8 In-Circuit Debugger (ICSP) When the DEBUG Configuration bit is programmed to PIC18F46J11 family microcontrollers can be serially a ‘0’, the In-Circuit Debugger functionality is enabled. programmed while in the end application circuit. This is This function allows simple debugging functions when simply done with two lines for clock and data and three used with MPLAB® IDE. When the microcontroller has other lines for power, ground and the programming this feature enabled, some resources are not available voltage. This allows customers to manufacture boards for general use. with unprogrammed devices and then program the Table26-4 lists the resources required by the microcontroller just before shipping the product. This background debugger. also allows the most recent firmware or a custom firmware to be programmed. TABLE 26-4: DEBUGGER RESOURCES I/O pins: RB6, RB7 Stack: TOSx registers reserved DS39932D-page 412  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 27.0 INSTRUCTION SET SUMMARY The Literal instructions may use some of the following operands: The PIC18F46J11 family of devices incorporates the • A literal value to be loaded into a file register standard set of 75 PIC18 core instructions, and an (specified by ‘k’) extended set of eight new instructions for the optimiza- tion of code that is recursive or that utilizes a software • The desired FSR register to load the literal value stack. The extended set is discussed later in this into (specified by ‘f’) section. • No operand required (specified by ‘—’) The Control instructions may use some of the 27.1 Standard Instruction Set following operands: The standard PIC18 instruction set adds many • A program memory address (specified by ‘n’) enhancements to the previous PIC® MCU instruction • The mode of the CALL or RETURN instructions sets, while maintaining an easy migration from these (specified by ‘s’) PIC MCU instruction sets. Most instructions are a • The mode of the table read and table write single program memory word (16 bits), but there are instructions (specified by ‘m’) four instructions that require two program memory • No operand required (specified by ‘—’) locations. All instructions are a single word, except for four Each single-word instruction is a 16-bit word divided double-word instructions. These instructions were into an opcode, which specifies the instruction type and made double-word to contain the required information one or more operands, which further specify the in 32 bits. In the second word, the 4 MSbs are ‘1’s. If operation of the instruction. this second word is executed as an instruction (by The instruction set is highly orthogonal and is grouped itself), it will execute as a NOP. into four basic categories: All single-word instructions are executed in a single • Byte-oriented operations instruction cycle, unless a conditional test is true or the • Bit-oriented operations Program Counter (PC) is changed as a result of the instruction. In these cases, the execution takes two • Literal operations instruction cycles with the additional instruction • Control operations cycle(s) executed as a NOP. The PIC18 instruction set summary in Table27-2 lists The double-word instructions execute in two instruction the byte-oriented, bit-oriented, literal and control cycles. operations. One instruction cycle consists of four oscillator periods. Table27-1 provides the opcode field descriptions. Thus, for an oscillator frequency of 4MHz, the normal Most Byte-oriented instructions have three operands: instruction execution time is 1s. If a conditional test is true, or the program counter is changed as a result of 1. The file register (specified by ‘f’) an instruction, the instruction execution time is 2 s. 2. The destination of the result (specified by ‘d’) Two-word branch instructions (if true) would take 3 s. 3. The accessed memory (specified by ‘a’) Figure27-1 provides the general formats that the The file register designator, ‘f’, specifies which file instructions can have. All examples use the convention register is to be used by the instruction. The destination ‘nnh’ to represent a hexadecimal number. designator, ‘d’, specifies where the result of the The instruction set summary, provided in Table27-2, operation is to be placed. If ‘d’ is ‘0’, the result is placed lists the standard instructions recognized by the in the WREG register. If ‘d’ is ‘1’, the result is placed in Microchip MPASMTM Assembler. the file register specified in the instruction. Section27.1.1 “Standard Instruction Set” provides All Bit-oriented instructions have three operands: a description of each instruction. 1. The file register (specified by ‘f’) 2. The bit in the file register (specified by ‘b’) 3. The accessed memory (specified by ‘a’) The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register desig- nator, ‘f’, represents the number of the file in which the bit is located.  2011 Microchip Technology Inc. DS39932D-page 413

PIC18F46J11 FAMILY TABLE 27-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7) BSR Bank Select Register. Used to select the current RAM bank C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location f 8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h) f 12-bit register file address (000h to FFFh). This is the source address s f 12-bit register file address (000h to FFFh). This is the destination address d GIE Global Interrupt Enable bit k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) label Label name mm The mode of the TBLPTR register for the table read and table write instructions Used only with table read and table write instructions * No Change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions PC Program Counter PCL Program Counter Low Byte PCH Program Counter High Byte PCLATH Program Counter High Byte Latch PCLATU Program Counter Upper Byte Latch PD Power-Down bit PRODH Product of Multiply High Byte PRODL Product of Multiply Low Byte s Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-Bit Table Pointer (points to a program memory location) TABLAT 8-Bit Table Latch TO Time-out bit TOS Top-of-Stack u Unused or Unchanged WDT Watchdog Timer WREG Working register (accumulator) x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0; it is the recommended form of use for compatibility with all Microchip software tools z 7-bit offset value for Indirect Addressing of register files (source) s z 7-bit offset value for Indirect Addressing of register files (destination) d { } Optional argument [text] Indicates Indexed Addressing (text) The contents of text [expr]<n> Specifies bit n of the register indicated by the pointer, expr  Assigned to < > Register bit field  In the set of italics User-defined term (font is Courier New) DS39932D-page 414  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY EXAMPLE 27-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC  2011 Microchip Technology Inc. DS39932D-page 415

PIC18F46J11 FAMILY TABLE 27-2: PIC18F46J11 FAMILY INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39932D-page 416  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 27-2: PIC18F46J11 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.  2011 Microchip Technology Inc. DS39932D-page 417

PIC18F46J11 FAMILY TABLE 27-2: PIC18F46J11 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move Literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY  PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39932D-page 418  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 27.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) + k  W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f)  dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ADDLW 0x15 mode whenever f 95 (5Fh). See Before Instruction Section27.2.3 “Byte-Oriented and W = 10h Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = 25h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).  2011 Microchip Technology Inc. DS39932D-page 419

PIC18F46J11 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0  f  255 Operands: 0  k  255 d [0,1] Operation: (W) .AND. k  W a [0,1] Status Affected: N, Z Operation: (W) + (f) + (C)  dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in Description: Add W, the Carry flag and data memory W. location ‘f’. If ‘d’ is ‘0’, the result is Words: 1 placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. Q Cycle Activity: If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read literal Process Write to If ‘a’ is ‘0’ and the extended instruction ‘k’ Data W set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ANDLW 0x5F mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = A3h Literal Offset Mode” for details. After Instruction W = 03h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS39932D-page 420  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0  f  255 Operands: -128  n  127 d [0,1] Operation: if Carry bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: (W) .AND. (f)  dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ’1’, then the program Description: The contents of W are ANDed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will in register ‘f’ (default). have incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a GPR bank (default). two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates Cycles: 1(2) in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Q Cycle Activity: Section27.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to Words: 1 ‘n’ Data PC No No No No Cycles: 1 operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If Carry = 1; W = 02h PC = address (HERE + 12) REG = C2h If Carry = 0; PC = address (HERE + 2)  2011 Microchip Technology Inc. DS39932D-page 421

PIC18F46J11 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0  f  255 Operands: -128  n  127 0  b  7 Operation: if Negative bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: 0  f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will GPR bank (default). have incremented to fetch the next instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Words: 1 Section27.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to Q Cycle Activity: ‘n’ Data PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No ‘n’ Data operation Before Instruction FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS39932D-page 422  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128  n  127 Operands: -128  n  127 Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’, (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will added to the PC. Since the PC will have incremented to fetch the next have incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2)  2011 Microchip Technology Inc. DS39932D-page 423

PIC18F46J11 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128  n  127 Operands: -128  n  127 Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’, (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will added to the PC. Since the PC will have incremented to fetch the next have incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS39932D-page 424  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024  n  1023 Operands: 0  f  255 0  b  7 Operation: (PC) + 2 + 2n  PC a [0,1] Status Affected: None Operation: 1  f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected. PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the two-cycle instruction. GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section27.2.3 “Byte-Oriented and Decode Read literal Process Write to Bit-Oriented Instructions in Indexed ‘n’ Data PC Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah  2011 Microchip Technology Inc. DS39932D-page 425

PIC18F46J11 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0  f  255 Operands: 0  f  255 0  b  7 0  b < 7 a [0,1] a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during then the next instruction fetched during the current instruction execution is dis- the current instruction execution is dis- carded and a NOP is executed instead, carded and a NOP is executed instead, making this a two-cycle instruction. making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39932D-page 426  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0  f  255 Operands: -128  n  127 0  b < 7 Operation: if Overflow bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: (f<b>)  f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will If ‘a’ is ‘1’, the BSR is used to select the have incremented to fetch the next GPR bank (default). instruction, the new address will be PC + 2 + 2n. This instruction is then a If ‘a’ is ‘0’ and the extended instruction two-cycle instruction. set is enabled, this instruction operates in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Cycles: 1(2) Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Q1 Q2 Q3 Q4 Words: 1 Decode Read literal Process Write to PC Cycles: 1 ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG LATC, 4, 0 ‘n’ Data operation Before Instruction: LATC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: Before Instruction LATC = 0110 0101 [65h] PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2)  2011 Microchip Technology Inc. DS39932D-page 427

PIC18F46J11 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128  n  127 Operands: 0  k  1048575 s [0,1] Operation: if Zero bit is ‘1’, (PC) + 2 + 2n  PC Operation: (PC) + 4  TOS, k  PC<20:1>; Status Affected: None if s = 1, Encoding: 1110 0000 nnnn nnnn (W)  WS, Description: If the Zero bit is ‘1’, then the program (STATUS)  STATUSS, will branch. (BSR)  BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will Encoding: have incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk 7 0 instruction, the new address will be 2nd word(k<19:8>) 1111 k kkk kkkk kkkk 19 8 PC + 2 + 2n. This instruction is then a Description: Subroutine call of entire 2-Mbyte two-cycle instruction. memory range. First, return address Words: 1 (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, STATUS and BSR Q Cycle Activity: registers are also pushed into their If Jump: respective shadow registers, WS, Q1 Q2 Q3 Q4 STATUSS and BSRS. If ‘s’ = 0, no Decode Read literal Process Write to update occurs (default). Then, the ‘n’ Data PC 20-bit value ‘k’ is loaded into No No No No PC<20:1>. CALL is a two-cycle operation operation operation operation instruction. If No Jump: Words: 2 Q1 Q2 Q3 Q4 Cycles: 2 Decode Read literal Process No Q Cycle Activity: ‘n’ Data operation Q1 Q2 Q3 Q4 Decode Read literal Push PC to Read literal Example: HERE BZ Jump ‘k’<7:0>, stack ’k’<19:8>, Before Instruction Write to PC PC = address (HERE) No No No No After Instruction operation operation operation operation If Zero = 1; PC = address (Jump) If Zero = 0; Example: HERE CALL THERE,1 PC = address (HERE + 2) Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39932D-page 428  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0  f  255 Operands: None a [0,1] Operation: 000h  WDT, Operation: 000h  f, 000h  WDT postscaler, 1  Z 1  TO, 1  PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the Watchdog Timer. It also resets the If ‘a’ is ‘0’, the Access Bank is selected. postscaler of the WDT. Status bits, TO If ‘a’ is ‘1’, the BSR is used to select the and PD, are set. GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Cycles: 1 in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Decode No Process No Literal Offset Mode” for details. operation Data operation Words: 1 Example: CLRWDT Cycles: 1 Before Instruction Q Cycle Activity: WDT Counter = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write WDT Counter = 00h register ‘f’ Data register ‘f’ WDT Postscaler = 0 TO = 1 PD = 1 Example: CLRF FLAG_REG,1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h  2011 Microchip Technology Inc. DS39932D-page 429

PIC18F46J11 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: f  dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data mem- complemented. If ‘d’ is ‘0’, the result is ory location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank (default). instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank (default). mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Words: 1 Section27.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Cycles: 1(2) register ‘f’ Data destination Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h W = ECh Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG  W; PC = Address (NEQUAL) DS39932D-page 430  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0  f  255 Operands: 0  f  255 a  [0,1] a  [0,1] Operation: (f) –W), Operation: (f) –W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data mem- ory location ‘f’ to the contents of the W Description: Compares the contents of data mem- by performing an unsigned subtraction. ory location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are greater than the contents of WREG, then the fetched If the contents of ‘f’ are less than the instruction is discarded and a NOP is contents of W, then the fetched executed instead, making this a instruction is discarded and a NOP is two-cycle instruction. executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Note: 3 cycles if skip and followed Section27.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 Words: 1 Decode Read Process No Cycles: 1(2) register ‘f’ Data operation Note: 3 cycles if skip and followed If skip: by a 2-word instruction. Q1 Q2 Q3 Q4 Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process No If skip and followed by 2-word instruction: register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; PC = Address (LESS) Before Instruction If REG  W; PC = Address (HERE) PC = Address (NLESS) W = ? After Instruction If REG  W; PC = Address (GREATER) If REG  W; PC = Address (NGREATER)  2011 Microchip Technology Inc. DS39932D-page 431

PIC18F46J11 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0  f  255 d  [0,1] Operation: If [W<3:0> > 9] or [DC = 1] then, a  [0,1] (W<3:0>) + 6  W<3:0>; else, Operation: (f) – 1  dest (W<3:0>)  W<3:0> Status Affected: C, DC, N, OV, Z If [W<7:4> > 9] or [C = 1] then, Encoding: 0000 01da ffff ffff (W<7:4>) + 6  W<7:4>, Description: Decrement register ‘f’. If ‘d’ is ‘0’, the C =1; result is stored in W. If ‘d’ is ‘1’, the else, result is stored back in register ‘f’ (W<7:4>)  W<7:4> (default). Status Affected: C If ‘a’ is ‘0’, the Access Bank is selected. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Description: DAW adjusts the eight-bit value in W, resulting from the earlier addition of two If ‘a’ is ‘0’ and the extended instruction variables (each in packed BCD format) set is enabled, this instruction operates and produces a correct packed BCD in Indexed Literal Offset Addressing result. mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Words: 1 Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write Q Cycle Activity: register W Data W Q1 Q2 Q3 Q4 Decode Read Process Write to Example 1: DAW register ‘f’ Data destination Before Instruction W = A5h C = 0 Example: DECF CNT, 1, 0 DC = 0 Before Instruction After Instruction CNT = 01h W = 05h Z = 0 C = 1 After Instruction DC = 0 CNT = 00h Example 2: Z = 1 Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS39932D-page 432  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – 1  dest, Operation: (f) – 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is ‘0’, the next instruction If the result is not ‘0’, the next which is already fetched is discarded instruction which is already fetched is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing Section27.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See Bit-Oriented Instructions in Indexed Section27.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT  0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP  0; PC = Address (NZERO)  2011 Microchip Technology Inc. DS39932D-page 433

PIC18F46J11 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0  k  1048575 Operands: 0  f  255 d  [0,1] Operation: k  PC<20:1> a  [0,1] Status Affected: None Operation: (f) + 1  dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire 2-Mbyte mem- incremented. If ‘d’ is ‘0’, the result is ory range. The 20-bit value ‘k’ is loaded placed in W. If ‘d’ is ‘1’, the result is into PC<20:1>. GOTO is always a placed back in register ‘f’ (default). two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. Words: 2 If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Cycles: 2 If ‘a’ is ‘0’ and the extended instruction Q Cycle Activity: set is enabled, this instruction operates Q1 Q2 Q3 Q4 in Indexed Literal Offset Addressing Decode Read literal No Read literal mode whenever f 95 (5Fh). See ‘k’<7:0>, operation ‘k’<19:8>, Section27.2.3 “Byte-Oriented and Write to PC Bit-Oriented Instructions in Indexed No No No No Literal Offset Mode” for details. operation operation operation operation Words: 1 Cycles: 1 Example: GOTO THERE Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 PC = Address (THERE) Decode Read Process Write to register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS39932D-page 434  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) + 1  dest, Operation: (f) + 1  dest, skip if result  0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’. (default) If the result is not ‘0’, the next If the result is ‘0’, the next instruction instruction which is already fetched is which is already fetched is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG  0; PC = Address (ZERO) PC = Address (NZERO) If CNT  0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO)  2011 Microchip Technology Inc. DS39932D-page 435

PIC18F46J11 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) .OR. k  W a  [0,1] Status Affected: N, Z Operation: (W) .OR. (f)  dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: IORLW 35h mode whenever f 95 (5Fh). See Before Instruction Section27.2.3 “Byte-Oriented and W = 9Ah Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = BFh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS39932D-page 436  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0  f  2 Operands: 0  f  255 0  k  4095 d  [0,1] a  [0,1] Operation: k  FSRf Operation: f  dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved file select register pointed to by ‘f’. to a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’ (default). Q Cycle Activity: Location ‘f’ can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 Decode Read literal Process Write If ‘a’ is ‘0’, the Access Bank is selected. ‘k’ MSB Data literal ‘k’ If ‘a’ is ‘1’, the BSR is used to select the MSB to GPR bank (default). FSRfH If ‘a’ is ‘0’ and the extended instruction Decode Read literal Process Write literal set is enabled, this instruction operates ‘k’ LSB Data ‘k’ to FSRfL in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Example: LFSR 2, 0x3AB Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. FSR2H = 03h FSR2L = ABh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data W Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h  2011 Microchip Technology Inc. DS39932D-page 437

PIC18F46J11 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLB k s d Operands: 0  f  4095 Operands: 0  k  255 s 0  f  4095 d Operation: k  BSR Operation: (f )  f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffff s Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffff d of BSR<7:4> always remains ‘0’ Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Decode Read Process Write literal Either source or destination can be W literal ‘k’ Data ‘k’ to BSR (a useful special situation). MOVFF is particularly useful for Example: MOVLB 5 transferring a data memory location to a peripheral register (such as the Before Instruction transmit buffer or an I/O port). BSR Register = 02h After Instruction The MOVFF instruction cannot use the BSR Register = 05h PCL, TOSU, TOSH or TOSL as the destination register Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS39932D-page 438  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: k  W Operation: (W)  f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: MOVLW 0x5A in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See After Instruction Section27.2.3 “Byte-Oriented and W = 5Ah Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh  2011 Microchip Technology Inc. DS39932D-page 439

PIC18F46J11 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: (W) x k  PRODH:PRODL Operation: (W) x (f)  PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried out 8-bit literal ‘k’. The 16-bit result is between the contents of W and the placed in PRODH:PRODL register pair. register file location ‘f’. The 16-bit result is PRODH contains the high byte. stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W is unchanged. W and ‘f’ are unchanged. None of the Status flags are affected. None of the Status flags are affected. Note that neither Overflow nor Carry is Note that neither Overflow nor Carry is possible in this operation. A Zero result possible in this operation. A Zero result is is possible but not detected. possible but not detected. Words: 1 If ‘a’ is ‘0’, the Access Bank is selected. If Cycles: 1 ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set Decode Read Process Write is enabled, this instruction operates in literal ‘k’ Data registers Indexed Literal Offset Addressing mode PRODH: whenever f 95 (5Fh). See PRODL Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: MULLW 0xC4 Words: 1 Before Instruction W = E2h Cycles: 1 PRODH = ? Q Cycle Activity: PRODL = ? After Instruction Q1 Q2 Q3 Q4 W = E2h Decode Read Process Write PRODH = ADh register ‘f’ Data registers PRODL = 08h PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS39932D-page 440  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0  f  255 Operands: None a  [0,1] Operation: No operation Operation: (f) + 1  f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h]  2011 Microchip Technology Inc. DS39932D-page 441

PIC18F46J11 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC + 2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS39932D-page 442  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n  PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC + 2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC Cycles: 1 will have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC + 2 + 2n. This instruction is a Decode Start No No two-cycle instruction. reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to PC Flags* = Reset Value ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2)  2011 Microchip Technology Inc. DS39932D-page 443

PIC18F46J11 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, Operation: k  W, 1  GIE/GIEH or PEIE/GIEL; (TOS)  PC, if s = 1, PCLATU, PCLATH are unchanged (WS)  W, Status Affected: None (STATUSS)  STATUS, (BSRS)  BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the top of the stack (the return Encoding: 0000 0000 0001 000s address). The high address latch Description: Return from interrupt. Stack is popped (PCLATH) remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 Global Interrupt Enable bit. If ‘s’ = 1, Q Cycle Activity: the contents of the shadow registers Q1 Q2 Q3 Q4 WS, STATUSS and BSRS are loaded Decode Read Process POP PC into their corresponding registers W, literal ‘k’ Data from stack, STATUS and BSR. If ‘s’ = 0, no update write to W of these registers occurs (default). No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS RETLW kn ; End of table W = WS BSR = BSRS STATUS = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn DS39932D-page 444  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s  [0,1] Operands: 0  f  255 d  [0,1] Operation: (TOS)  PC; a  [0,1] if s = 1, (WS)  W, Operation: (f<n>)  dest<n + 1>, (STATUSS)  STATUS, (f<7>)  C, (BSRS)  BSR, (C)  dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry flag. popped and the top of the stack (TOS) If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is loaded into the program counter. If is ‘1’, the result is stored back in register ‘s’= 1, the contents of the shadow ‘f’ (default). registers WS, STATUSS and BSRS are If ‘a’ is ‘0’, the Access Bank is selected. loaded into their corresponding If ‘a’ is ‘1’, the BSR is used to select the registers W, STATUS and BSR. If GPR bank (default). ‘s’ = 0, no update of these registers occurs (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 2 mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Q Cycle Activity: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1  2011 Microchip Technology Inc. DS39932D-page 445

PIC18F46J11 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f<n>)  dest<n + 1>, Operation: (f<n>)  dest<n – 1>, (f<7>)  dest<0> (f<0>)  C, (C)  dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back If ‘a’ is ‘0’, the Access Bank is in register ‘f’ (default). selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank (default). set is enabled, this instruction oper- ates in Indexed Literal Offset Address- If ‘a’ is ‘0’ and the extended instruction ing mode whenever f 95 (5Fh). See set is enabled, this instruction operates Section27.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f 95 (5Fh). See Literal Offset Mode” for details. Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39932D-page 446  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a [0,1] a  [0,1] Operation: FFh  f Operation: (f<n>)  dest<n – 1>, Status Affected: None (f<0>)  dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank (default). placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If in Indexed Literal Offset Addressing ‘a’ is ‘1’, then the bank will be selected mode whenever f 95 (5Fh). See as per the BSR value (default). Section27.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111  2011 Microchip Technology Inc. DS39932D-page 447

PIC18F46J11 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 f 255 d  [0,1] Operation: 00h  WDT, a  [0,1] 0  WDT postscaler, 1  TO, Operation: (W) – (f) – (C) dest 0  PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored in is set. The Watchdog Timer and its W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’ (default). The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is selected. If with the oscillator stopped. ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction operates in Q Cycle Activity: Indexed Literal Offset Addressing mode Q1 Q2 Q3 Q4 whenever f 95 (5Fh). See Decode No Process Go to Section27.2.3 “Byte-Oriented and operation Data Sleep Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to TO = 1 † register ‘f’ Data destination PD = 0 Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39932D-page 448  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 k 255 Operands: 0 f 255 d  [0,1] Operation: k – (W) W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the result Q Cycle Activity: is stored back in register ‘f’ (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read Process Write to If ‘a’ is ‘1’, the BSR is used to select the literal ‘k’ Data W GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 0x02 set is enabled, this instruction operates Before Instruction in Indexed Literal Offset Addressing W = 01h mode whenever f 95 (5Fh). See C = ? Section27.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 01h Literal Offset Mode” for details. C = 1 ; result is positive Z = 0 Words: 1 N = 0 Cycles: 1 Example 2: SUBLW 0x02 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 W = 02h C = ? Decode Read Process Write to After Instruction register ‘f’ Data destination W = 00h C = 1 ; result is zero Example 1: SUBWF REG, 1, 0 Z = 1 Before Instruction N = 0 REG = 3 W = 2 Example 3: SUBLW 0x02 C = ? Before Instruction After Instruction W = 03h REG = 1 C = ? W = 2 After Instruction C = 1 ; result is positive Z = 0 W = FFh ; (2’s complement) N = 0 C = 0 ; result is negative Z = 0 Example 2: SUBWF REG, 0, 0 N = 1 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1  2011 Microchip Technology Inc. DS39932D-page 449

PIC18F46J11 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: (f<3:0>)  dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>)  dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement Description: The upper and lower nibbles of register method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) REG = 35h C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39932D-page 450  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR))  TABLAT, MEMORY(00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR))  TABLAT, TBLPTR = 00A357h (TBLPTR) + 1  TBLPTR; Example 2: TBLRD +* if TBLRD *-, (Prog Mem (TBLPTR))  TABLAT, Before Instruction (TBLPTR) – 1  TBLPTR; TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY(01A357h) = 12h (TBLPTR) + 1  TBLPTR, MEMORY(01A358h) = 34h (Prog Mem (TBLPTR))  TABLAT After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR<0> = 0: Least Significant Byte of Program Memory Word TBLPTR<0> = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write Memory) TABLAT)  2011 Microchip Technology Inc. DS39932D-page 451

PIC18F46J11 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+ Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT)  Holding Register, TBLPTR = 00A356h HOLDING REGISTER TBLPTR – No Change; (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT)  Holding Register, TABLAT = 55h (TBLPTR) + 1  TBLPTR; TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT)  Holding Register, (00A356h) = 55h (TBLPTR) – 1  TBLPTR; Example 2: TBLWT +* if TBLWT+*, Before Instruction (TBLPTR) + 1  TBLPTR, TABLAT = 34h (TABLAT)  Holding Register TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER (01389Bh) = 34h 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section6.0 “Memory Organization” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR<0> = 0: Least Significant Byte of Program Memory Word TBLPTR<0> = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register) DS39932D-page 452  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0  f  255 Operands: 0 k 255 a  [0,1] Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to set is enabled, this instruction operates literal ‘k’ Data W in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: XORLW 0xAF Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Before Instruction Literal Offset Mode” for details. W = B5h After Instruction Words: 1 W = 1Ah Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT  00h, PC = Address (NZERO)  2011 Microchip Technology Inc. DS39932D-page 453

PIC18F46J11 FAMILY XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section27.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS39932D-page 454  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 27.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table27-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section27.2.2 “Extended Instruction instruction set, the PIC18F46J11 family of devices also Set”. The opcode field descriptions in Table27-1 provides an optional extension to the core CPU func- (page414) apply to both the standard and extended tionality. The added features include eight additional PIC18 instruction sets. instructions that augment Indirect and Indexed Addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction these instructions directly in assembler. set are enabled by default on unprogrammed The syntax for these commands is devices. Users must properly set or clear the XINST provided as a reference for users who Configuration bit during programming to enable or may be reviewing code that has been disable these features. generated by a compiler. The instructions in the extended set can all be classified as literal operations, which either manipulate 27.2.1 EXTENDED INSTRUCTION SYNTAX the File Select Registers (FSR), or use them for Most of the extended instructions use indexed argu- Indexed Addressing. Two of the instructions, ADDFSR ments, using one of the FSRs and some offset to specify and SUBFSR, each have an additional special instanti- a source or destination register. When an argument for ation for using FSR2. These versions (ADDULNK and an instruction serves as part of Indexed Addressing, it is SUBULNK) allow for automatic return after execution. enclosed in square brackets (“[ ]”). This is done to indi- The extended instructions are specifically implemented cate that the argument is used as an index or offset. The to optimize re-entrant program code (that is, code that MPASM™ Assembler will flag an error if it determines is recursive or that uses a software stack) written in that an index or offset value is not bracketed. high-level languages, particularly C. Among other When the extended instruction set is enabled, brackets things, they allow users working in high-level are also used to indicate index arguments in languages to perform certain operations on data byte-oriented and bit-oriented instructions. This is in structures more efficiently. These include: addition to other changes in their syntax. For more • Dynamic allocation and deallocation of software details, see Section27.2.3.1 “Extended Instruction stack space when entering and leaving Syntax with Standard PIC18 Commands”. subroutines Note: In the past, square brackets have been • Function Pointer invocation used to denote optional arguments in the • Software Stack Pointer manipulation PIC18 and earlier instruction sets. In this • Manipulation of variables located in a software text and going forward, optional stack arguments are denoted by braces (“{ }”). TABLE 27-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff — MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz — PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None Decrement FSR2 — SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None Return  2011 Microchip Technology Inc. DS39932D-page 455

PIC18F46J11 FAMILY 27.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 + k  FSR2, Operation: FSR(f) + k  FSR(f) (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. Q Cycle Activity: The instruction takes two cycles to Q1 Q2 Q3 Q4 execute; a NOP is performed during the second cycle. Decode Read Process Write to literal ‘k’ Data FSR This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates Example: ADDFSR 2, 0x23 only on FSR2. Before Instruction Words: 1 FSR2 = 03FFh Cycles: 2 After Instruction FSR2 = 0422h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 0x23 Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS39932D-page 456  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY CALLW Subroutine Call using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0  z  127 s 0  f  4095 Operation: (PC + 2)  TOS, d (W)  PCL, Operation: ((FSR2) + z )  f s d (PCLATH)  PCH, Status Affected: None (PCLATU)  PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffff d Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’, in the first word, to the value s latched into PCH and PCU, respec- of FSR2. The address of the destina- tively. The second cycle is executed as tion register is specified by the 12-bit lit- a NOP instruction while the new next eral ‘fd’ in the second word. Both instruction is fetched. addresses can be anywhere in the 4096-byte data space (000h to FFFh). Unlike CALL, there is no option to update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an Indirect Addressing register, the Q1 Q2 Q3 Q4 value returned will be 00h. Decode Read Push PC to No Words: 2 WREG stack operation Cycles: 2 No No No No operation operation operation operation Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Before Instruction Decode No No Write PC = address (HERE) operation operation register ‘f’ PCLATH = 10h No dummy (dest) PCLATU = 00h read W = 06h After Instruction PC = 001006h TOS = address (HERE + 2) Example: MOVSF [0x05], REG2 PCLATH = 10h PCLATU = 00h Before Instruction W = 06h FSR2 = 80h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h  2011 Microchip Technology Inc. DS39932D-page 457

PIC18F46J11 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0  zs  127 Operands: 0k  255 0  z  127 d Operation: k  (FSR2), Operation: ((FSR2) + zs)  ((FSR2) + zd) FSR2 – 1  FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1110 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. Description The contents of the source register are FSR2 is decremented by 1 after the moved to the destination register. The operation. addresses of the source and destina- tion registers are determined by adding This instruction allows users to push the 7-bit literal offsets ‘z ’ or ‘z ’, values onto a software stack. s d respectively, to the value of FSR2. Both Words: 1 registers can be located anywhere in the 4096-byte data memory space Cycles: 1 (000h to FFFh). Q Cycle Activity: The MOVSS instruction cannot use the Q1 Q2 Q3 Q4 PCL, TOSU, TOSH or TOSL as the Decode Read ‘k’ Process Write to destination register. data destination If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. If the Example: PUSHL 0x08 resultant destination address points to Before Instruction an Indirect Addressing register, the FSR2H:FSR2L = 01ECh instruction will execute as a NOP. Memory (01ECh) = 00h Words: 2 After Instruction Cycles: 2 FSR2H:FSR2L = 01EBh Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [0x05], [0x06] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS39932D-page 458  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 – k  FSR2, Operation: FSRf – k  FSRf (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified contents of the FSR2. A RETURN is then by ‘f’. executed by loading the PC with the Words: 1 TOS. Cycles: 1 The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during the second cycle. Q1 Q2 Q3 Q4 Decode Read Process Write to This may be thought of as a special case register ‘f’ Data destination of the SUBFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Words: 1 Example: SUBFSR 2, 0x23 Cycles: 2 Before Instruction Q Cycle Activity: FSR2 = 03FFh Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to FSR2 = 03DCh register ‘f’ Data destination No No No No Operation Operation Operation Operation Example: SUBULNK 0x23 Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS)  2011 Microchip Technology Inc. DS39932D-page 459

PIC18F46J11 FAMILY 27.2.3 BYTE-ORIENTED AND 27.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file register argument ‘f’ in the standard byte-oriented and Note: Enabling the PIC18 instruction set exten- bit-oriented commands is replaced with the literal offset sion may cause legacy applications to value ‘k’. As already noted, this occurs only when ‘f’ is behave erratically or fail entirely less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing (Section6.6.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within the brackets, will the standard PIC18 instruction set are interpreted. generate an error in the MPASM Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is either as a location in the Access Bank (a = 0) or in a never specified; it will automatically be assumed to be GPR bank designated by the BSR (a = 1). When the ‘0’. This is in contrast to standard operation (extended extended instruction set is enabled and a = 0, however, instruction set disabled) when ‘a’ is set on the basis of a file register argument of 5Fh or less is interpreted as the target address. Declaring the Access RAM bit in an offset from the pointer value in FSR2 and not as a this mode will also generate an error in the MPASM literal address. For practical purposes, this means that Assembler. all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bit-oriented The destination argument ‘d’ functions as before. instructions, or almost half of the core PIC18 instruc- In the latest versions of the MPASM Assembler, tions – may behave differently when the extended language support for the extended instruction set must instruction set is enabled. be explicitly invoked. This is done with either the When the content of FSR2 is 00h, the boundaries of the command line option, /y, or the PE directive in the Access RAM are essentially remapped to their original source listing. values. This may be useful in creating 27.2.4 CONSIDERATIONS WHEN backward-compatible code. If this technique is used, it ENABLING THE EXTENDED may be necessary to save the value of FSR2 and INSTRUCTION SET restore it when moving back and forth between C and assembly routines in order to preserve the Stack It is important to note that the extensions to the instruc- Pointer. Users must also keep in mind the syntax tion set may not be beneficial to all users. In particular, requirements of the extended instruction set (see users who are not writing code that uses a software Section27.2.3.1 “Extended Instruction Syntax with stack may not benefit from using the extensions to the Standard PIC18 Commands”). instruction set. Although the Indexed Literal Offset mode can be very Additionally, the Indexed Literal Offset Addressing useful for dynamic stack and pointer manipulation, it mode may create issues with legacy applications can also be very annoying if a simple arithmetic opera- written to the PIC18 assembler. This is because tion is carried out on the wrong register. Users who are instructions in the legacy code may attempt to address accustomed to the PIC18 programming must keep in registers in the Access Bank below 5Fh. Since these mind that, when the extended instruction set is addresses are interpreted as literal offsets to FSR2 enabled, register addresses of 5Fh or less are used for when the instruction set extension is enabled, the Indexed Literal Offset Addressing. application may read or write to the wrong data Representative examples of typical byte-oriented and addresses. bit-oriented instructions in the Indexed Literal Offset When porting an application to the PIC18F46J11 fam- mode are provided on the following page to show how ily, it is very important to consider the type of code. A execution is affected. The operand conditions provided large, re-entrant application that is written in C and in the examples are applicable to all instructions of would benefit from efficient compilation will do well these types. when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39932D-page 460  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0  k  95 Operands: 0  f  95 d  [0,1] 0  b  7 Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by contents of the register indicated by FSR2, offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ Cycles: 1 is ‘1’, the result is stored back in register ‘f’ (default). Q Cycle Activity: Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1 register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Contents Example: ADDWF [OFST],0 of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction Set Indexed SETF W = 37h (Indexed Literal Offset mode) Contents of 0A2Ch = 20h Syntax: SETF [k] Operands: 0  k  95 Operation: FFh  ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh  2011 Microchip Technology Inc. DS39932D-page 461

PIC18F46J11 FAMILY 27.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set for the PIC18F46J11 family. This includes the • A menu option or dialog box within the environ- MPLAB C18 C Compiler, MPASM assembly language ment that allows the user to configure the and MPLAB Integrated Development Environment language tool and its settings for the project (IDE). • A command line option When selecting a target device for software • A directive in the source code development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for These options vary between different compilers, the XINST Configuration bit is ‘1’, enabling the assemblers and development environments. Users are extended instruction set and Indexed Literal Offset encouraged to review the documentation accompany- Addressing. For proper execution of applications ing their development systems for the appropriate developed to take advantage of the extended information. instruction set, XINST must be set during programming. DS39932D-page 462  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 28.0 DEVELOPMENT SUPPORT 28.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- • Integrated Development Environment controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software operating system-based application that contains: • Assemblers/Compilers/Linkers • A single graphical interface to all debugging tools - MPASMTM Assembler - Simulator - MPLAB C18 and MPLAB C30 C Compilers - Programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) • Simulators • A full-featured editor with color-coded context - MPLAB SIM Software Simulator • A multiple project manager • Emulators • Customizable data windows with direct edit of contents - MPLAB ICE 2000 In-Circuit Emulator • High-level source code debugging - MPLAB REAL ICE™ In-Circuit Emulator • Visual device initializer for easy register • In-Circuit Debugger initialization - MPLAB ICD 2 • Mouse over variable inspection • Device Programmers • Drag and drop variables from source to watch - PICSTART® Plus Development Programmer windows - MPLAB PM3 Device Programmer • Extensive online help - PICkit™ 2 Development Programmer • Integration of select third party tools, such as • Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR Boards and Evaluation Kits C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2011 Microchip Technology Inc. DS39932D-page 463

PIC18F46J11 FAMILY 28.2 MPASM Assembler 28.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: • Support for the entire dsPIC30F instruction set • Integration into MPLAB IDE projects • Support for fixed-point and floating-point data • User-defined macros to streamline • Command line interface assembly code • Rich directive set • Conditional assembly for multi-purpose source files • Flexible macro language • Directives that allow complete control over the • MPLAB IDE compatibility assembly process 28.6 MPLAB SIM Software Simulator 28.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulat- ing the PIC MCUs and dsPIC® DSCs on an instruction The MPLAB C18 and MPLAB C30 Code Development level. On any given instruction, the data areas can be Systems are complete ANSI C compilers for examined or modified and stimuli can be applied from Microchip’s PIC18 and PIC24 families of microcon- a comprehensive stimulus controller. Registers can be trollers and the dsPIC30 and dsPIC33 family of digital logged to files for further run-time analysis. The trace signal controllers. These compilers provide powerful buffer and logic analyzer display extend the power of integration capabilities, superior code optimization and the simulator to record and track program execution, ease of use not found with other compilers. actions on I/O, most peripherals and internal registers. For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and debugger. MPLAB C30 CCompilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator 28.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside MPLIB Object Librarian of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS39932D-page 464  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 28.7 MPLAB ICE 2000 28.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes microcontrollers. Software control of the MPLAB ICE the in-circuit debugging capability built into theFlash 2000 In-Circuit Emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers cost- editing, building, downloading and source debugging effective, in-circuit Flash debugging from the graphical from a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step- ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB ICE 2000 In-Circuit Emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 28.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for simple, unified application. maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various 28.8 MPLAB REAL ICE In-Circuit package types. The ICSP™ cable assembly is included Emulator System as a standard item. In Stand-Alone mode, the MPLAB MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set Microchip Flash DSC and MCU devices. It debugs and code protection in this mode. The MPLAB PM3 programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable. with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large included with each kit. memory devices and incorporates an SD/MMC card for file storage and secure data applications. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, Low- Voltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2011 Microchip Technology Inc. DS39932D-page 465

PIC18F46J11 FAMILY 28.11 PICSTART Plus Development 28.13 Demonstration, Development and Programmer Evaluation Boards The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func- Integrated Development Environment software makes tional systems. Most boards include prototyping areas for using the programmer simple and efficient. The adding custom circuitry and provide application firmware PICSTART Plus Development Programmer supports and source code for examination and modification. most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs, Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232 PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional The PICSTART Plus Development Programmer is CE EEPROM memory. compliant. The demonstration and development boards can be used in teaching environments, for prototyping custom 28.12 PICkit 2 Development Programmer circuits and for learning about various microcontroller The PICkit™ 2 Development Programmer is a low-cost applications. programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ demon- an easy-to-use interface for programming many of stration/development board series of circuits, Microchip Microchip’s baseline, mid-range and PIC18F families of has a line of evaluation kits and demonstration software Flash memory microcontrollers. The PICkit 2 Starter Kit for analog filter design, KEELOQ® security ICs, CAN, includes a prototyping development board, twelve IrDA®, PowerSmart battery management, SEEVAL® sequential lessons, software and HI-TECH’s PICC™ evaluation system, Sigma-Delta ADC, flow rate Lite C compiler, and is designed to help get up to speed sensing, plus many more. quickly using PIC® microcontrollers. The kit provides Check the Microchip web page (www.microchip.com) everything needed to program, evaluate and develop for the complete list of demonstration, development applications using Microchip’s powerful, mid-range and evaluation kits. Flash memory family of microcontrollers. DS39932D-page 466  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 29.0 ELECTRICAL Absolute Maximum Ratings(†) CHARACTERISTICS Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any digital only I/O pin or MCLR with respect to VSS (when VDD  2.0V)..................................-0.3V to 6.0V Voltage on any digital only I/O pin or MCLR with respect to VSS (when VDD < 2.0V).....................-0.3V to (VDD + 4.0V) Voltage on any combined digital and analog pin with respect to VSS (except VDD)........................-0.3V to (VDD + 0.3V) Voltage on VDDCORE with respect to VSS...................................................................................................-0.3V to 2.75V Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Maximum output current sunk by any PORTB, PORTC and RA6 I/O pin...............................................................25mA Maximum output current sunk by any PORTA (except RA6), PORTD and PORTE I/O pin......................................4mA Maximum output current sourced by any PORTB, PORTC and RA6 I/O pin.........................................................25mA Maximum output current sourced by any PORTA (except RA6), PORTD and PORTE I/O pin................................4mA Maximum current sunk byall ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. FIGURE 29-1: PIC18F46J11 FAMILY VDD FREQUENCY GRAPH (INDUSTRIAL) 4.0V 3.6V 3.5V 3.0V ) D PIC18F46J11 Family Valid Operating Range D V 2.5V ( e g 2.35V a olt 2.15V V 8 MHz 48 MHz 0  2011 Microchip Technology Inc. DS39932D-page 467

PIC18F46J11 FAMILY FIGURE 29-2: PIC18LF46J11 VDDCORE FREQUENCY GRAPH (INDUSTRIAL)(1) 3.00V 2.75V 2.75V )E 2.50V PIC18LF46J11 Family Valid Operating Range R O 2.35V C D 2.25V D V ( e 2.00V g a t ol V 8 MHz 48 MHz 0 Frequency Note 1: VDD and VDDCORE must be maintained so that VDDCORE  VDD. DS39932D-page 468  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 29.1 DC Characteristics: Supply Voltage PIC18F46J11 Family (Industrial) Standard Operating Conditions (unless otherwise stated) PIC18F46J11 Family Operating temperature -40°C  TA  +85°C for industrial Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage 2.15 — 3.6 V PIC18F4XJ11, PIC18F2XJ11 2.0 — 3.6 V PIC18LF4XJ11, PIC18LF2XJ11 D001B VDDCORE External Supply for 2.0 — 2.75 V PIC18LF4XJ11, PIC18LF2XJ11 Microcontroller Core D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V D001D AVSS Analog Ground Potential VSS – 0.3 — VSS + 0.3 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See Section5.3 “Power-on to Ensure Internal Reset (POR)” for details Power-on Reset Signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section5.3 “Power-on to Ensure Internal Reset (POR)” for details Power-on Reset Signal D005 VBOR(2) VDDCORE Brown-out 1.9 2.0 2.2 V PIC18F4XJ11, PIC18F2XJ11 Reset Voltage only (not used on “LF” devices) D006 VDSBOR VDD Brown-out Reset — 1.8 — V DSBOREN = 1 on “LF” device, Voltage or “F” device In Deep Sleep Note 1: This is the limit to which VDDCORE can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: Device will operate normally until Brown-out Reset occurs, even though VDD may be below VDDMIN.  2011 Microchip Technology Inc. DS39932D-page 469

PIC18F46J11 FAMILY 29.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial) Standard Operating Conditions (unless otherwise stated) PIC18LFXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) – Sleep mode PIC18LFXXJ11 0.011 1.4 A -40°C 0.054 1.4 A +25°C VDD = 2.0V, 0.51 6 A +60°C VDDCORE = 2.0V 2.0 10.2 A +85°C PIC18LFXXJ11 0.029 1.5 A -40°C 0.11 1.5 A +25°C VDD = 2.5V, 0.63 8 A +60°C VDDCORE = 2.5V 2.30 12.6 A +85°C Sleep mode, PIC18FXXJ11 2.5 6 A -40°C REGSLP = 1 3.1 6 A +25°C VDD = 2.15V, VDDCORE = 10 F 3.9 8 A +60°C Capacitor 5.6 16 A +85°C PIC18FXXJ11 4.1 7 A -40°C 3.3 7 A +25°C VDD = 3.3V, VDDCORE = 10 F 4.1 10 A +60°C Capacitor 6.0 19 A +85°C Power-Down Current (IPD)(1) – Deep Sleep mode PIC18FXXJ11 1 25 nA -40°C 13 100 nA +25°C VDD = 2.15V, VDDCORE = 10 F 108 250 nA +60°C Capacitor 428 1000 nA +85°C Deep Sleep mode PIC18FXXJ11 3 50 nA -40°C 28 150 nA +25°C VDD = 3.3V, VDDCORE = 10 F 170 389 nA +60°C Capacitor 588 2000 nA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. 3: Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39932D-page 470  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 29.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LFXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LFXXJ11 5.2 14.2 A -40°C VDD = 2.0V, 6.2 14.2 A +25°C VDDCORE = 2.0V 8.6 19.0 A +85°C PIC18LFXXJ11 7.6 16.5 A -40°C VDD = 2.5V, 8.5 16.5 A +25°C VDDCORE = 2.5V 11.3 22.4 A +85°C FOSC = 31 kHz, RC_RUN mode, Internal RC PIC18FXXJ11 37 77 A -40°C VDD = 2.15V, Oscillator, INTSRC = 0 48 77 A +25°C VDDCORE = 10 F 60 93 A +85°C Capacitor PIC18FXXJ11 52 84 A -40°C VDD = 3.3V, 61 84 A +25°C VDDCORE = 10 F 70 108 A +85°C Capacitor PIC18LFXXJ11 1.1 1.5 mA -40°C VDD = 2.0V, 1.1 1.5 mA +25°C VDDCORE = 2.0V 1.2 1.6 mA +85°C PIC18LFXXJ11 1.5 1.7 mA -40°C VDD = 2.5V, 1.6 1.7 mA +25°C VDDCORE = 2.5V 1.6 1.9 mA +85°C FOSC = 4 MHz, RC_RUN PIC18FXXJ11 1.3 2.6 mA -40°C VDD = 2.15V, mode, Internal RC Oscillator 1.4 2.6 mA +25°C VDDCORE = 10 F 1.4 2.8 mA +85°C Capacitor PIC18FXXJ11 1.6 2.9 mA -40°C VDD = 3.3V, 1.6 2.9 mA +25°C VDDCORE = 10 F 1.6 3.0 mA +85°C Capacitor Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. 3: Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.  2011 Microchip Technology Inc. DS39932D-page 471

PIC18F46J11 FAMILY 29.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LFXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LFXXJ11 1.9 3.6 mA -40°C VDD = 2.0V, 2.0 3.8 mA +25°C VDDCORE = 2.0V 2.0 3.8 mA +85°C PIC18LFXXJ11 2.8 4.8 mA -40°C VDD = 2.5V, 2.8 4.8 mA +25°C VDDCORE = 2.5V 2.8 4.9 mA +85°C FOSC = 8 MHz, RC_RUN PIC18FXXJ11 2.3 4.2 mA -40°C VDD = 2.15V, mode, Internal RC Oscillator 2.3 4.2 mA +25°C VDDCORE = 10 F 2.4 4.5 mA +85°C Capacitor PIC18FXXJ11 2.8 5.1 mA -40°C VDD = 3.3V, 2.8 5.1 mA +25°C VDDCORE = 10 F 2.8 5.4 mA +85°C Capacitor PIC18LFXXJ11 1.9 9.4 A -40°C VDD = 2.0V, 2.3 9.4 A +25°C VDDCORE = 2.0V 4.5 17.2 A +85°C PIC18LFXXJ11 2.4 10.5 A -40°C VDD = 2.5V, 2.8 10.5 A +25°C VDDCORE = 2.5V 5.4 19.5 A +85°C FOSC = 31 kHz, RC_IDLE mode, Internal RC Oscillator, PIC18FXXJ11 33.3 75 A -40°C VDD = 2.15V, INTSRC = 0 43.8 75 A +25°C VDDCORE = 10 F 55.3 92 A +85°C Capacitor PIC18FXXJ11 36.1 82 A -40°C VDD = 3.3V, 44.5 82 A +25°C VDDCORE = 10 F 56.3 105 A +85°C Capacitor Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. 3: Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39932D-page 472  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 29.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LFXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LFXXJ11 0.531 0.980 mA -40°C VDD = 2.0V, 0.571 0.980 mA +25°C VDDCORE = 2.0V 0.608 1.12 mA +85°C PIC18LFXXJ11 0.625 1.14 mA -40°C VDD = 2.5V, 0.681 1.14 mA +25°C VDDCORE = 2.5V 0.725 1.25 mA +85°C FOSC = 4 MHz, RC_IDLE PIC18FXXJ11 0.613 1.21 mA -40°C VDD = 2.15V, mode, Internal RC Oscillator 0.680 1.21 mA +25°C VDDCORE = 10 F 0.730 1.30 mA +85°C Capacitor PIC18FXXJ11 0.673 1.27 mA -40°C VDD = 3.3V, 0.728 1.27 mA +25°C VDDCORE = 10 F 0.779 1.45 mA +85°C Capacitor PIC18LFXXJ11 0.750 1.4 mA -40°C VDD = 2.0V, 0.797 1.5 mA +25°C VDDCORE = 2.0V 0.839 1.6 mA +85°C PIC18LFXXJ11 0.91 2.4 mA -40°C VDD = 2.5V, 0.96 2.4 mA +25°C VDDCORE = 2.5V 1.01 2.5 mA +85°C FOSC = 8 MHz, RC_IDLE PIC18FXXJ11 0.87 2.1 mA -40°C VDD = 2.15V, mode, Internal RC Oscillator 0.93 2.1 mA +25°C VDDCORE = 10 F 0.98 2.3 mA +85°C Capacitor PIC18FXXJ11 0.95 2.6 mA -40°C VDD = 3.3V, 1.01 2.6 mA +25°C VDDCORE = 10 F 1.06 2.7 mA +85°C Capacitor Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. 3: Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.  2011 Microchip Technology Inc. DS39932D-page 473

PIC18F46J11 FAMILY 29.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LFXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LFXXJ11 0.879 1.25 mA -40°C VDD = 2.0V, 0.881 1.25 mA +25°C VDDCORE = 2.0V 0.891 1.36 mA +85°C PIC18LFXXJ11 1.35 1.70 mA -40°C VDD = 2.0V, 1.30 1.70 mA +25°C VDDCORE = 2.0V 1.27 1.82 mA +85°C FOSC = 4 MHz, PRI_RUN PIC18FXXJ11 1.09 1.60 mA -40°C VDD = 2.15V, mode, EC Oscillator 1.09 1.60 mA +25°C VDDCORE = 10 F 1.11 1.70 mA +85°C Capacitor PIC18FXXJ11 1.36 1.95 mA -40°C VDD = 3.3V, 1.36 1.89 mA +25°C VDDCORE = 10 F 1.41 1.92 mA +85°C Capacitor PIC18LFXXJ11 10.9 14.8 mA -40°C VDD = 2.5V, 10.6 14.8 mA +25°C VDDCORE = 2.5V 10.6 15.2 mA +85°C FOSC = 48 MHz, PRI_RUN PIC18FXXJ11 12.9 23.2 mA -40°C VDD = 3.3V, mode, EC Oscillator 12.8 22.7 mA +25°C VDDCORE = 10 F 12.7 22.7 mA +85°C Capacitor Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. 3: Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39932D-page 474  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 29.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LFXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LFXXJ11 0.285 0.700 mA -40°C VDD = 2.0V, 0.300 0.700 mA +25°C VDDCORE = 2.0V 0.336 0.750 mA +85°C PIC18LFXXJ11 0.372 1.00 mA -40°C VDD = 2.5V, 0.397 1.00 mA +25°C VDDCORE = 2.5V 0.495 1.10 mA +85°C FOSC = 4 MHz, PRI_IDLE PIC18FXXJ11 0.357 0.850 mA -40°C VDD = 2.15V, mode, EC Oscillator 0.383 0.850 mA +25°C VDDCORE = 10 F 0.407 0.900 mA +85°C Capacitor PIC18FXXJ11 0.449 1.30 mA -40°C VDD = 3.3V, 0.488 1.20 mA +25°C VDDCORE = 10 F 0.554 1.20 mA +85°C Capacitor PIC18LFXXJ11 4.5 6.5 mA -40°C VDD = 2.5V, 4.5 6.5 mA +25°C VDDCORE = 2.5V 4.6 6.5 mA +85°C FOSC = 48MHz PRI_IDLE mode, PIC18FXXJ11 4.9 12.4 mA -40°C VDD = 3.3V, EC oscillator 5.0 11.5 mA +25°C VDDCORE = 10 F 5.1 11.5 mA +85°C Capacitor Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. 3: Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.  2011 Microchip Technology Inc. DS39932D-page 475

PIC18F46J11 FAMILY 29.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LFXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. PIC18LFXXJ11 5.2 6.5 mA -40°C VDD = 2.5V, 5.1 6.4 mA +25°C VDDCORE = 2.5V FOSC = 16MHz 5.1 6.4 mA +85°C (PRI_RUN mode, PIC18FXXJ11 5.3 7.5 mA -40°C VDD = 3.3V, 4 MHz Internal Oscillator with PLL 5.2 7.4 mA +25°C VDDCORE = 10 F 5.2 7.4 mA +85°C Capacitor PIC18LFXXJ11 9.3 12.0 mA -40°C VDD = 2.5V, 9.2 11.8 mA +25°C VDDCORE = 2.5V FOSC = 32MHz, 9.0 11.8 mA +85°C PRI_RUN mode, PIC18FXXJ11 9.7 17.5 mA -40°C VDD = 3.3V, 8 MHz Internal Oscillator with PLL 9.6 17.2 mA +25°C VDDCORE = 10 F 9.6 17.2 mA +85°C Capacitor PIC18LFXXJ11 12.4 13.5 mA -40°C VDD = 2.5V, 12.2 13.5 mA +25°C VDDCORE = 2.5V FOSC = 48MHz, 12.1 13.9 mA +85°C PRI_RUN mode, PIC18FXXJ11 14.3 24.1 mA -40°C VDD = 3.3V, 12 MHz External Oscillator with PLL 14.2 23.0 mA +25°C VDDCORE = 10 F 14.2 23.0 mA +85°C Capacitor Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. 3: Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39932D-page 476  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 29.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LFXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. PIC18LFXXJ11 12.5 45 A -40°C VDD = 2.5V, 11.7 45 A +25°C VDDCORE = 2.5V 5.2 61 A +85°C PIC18FXXJ11 40.2 95 A -40°C VDD = 2.15V, FOSC = 32kHz(3) 50.2 95 A +25°C VDDCORE = 10 F SEC_RUN mode, 61.9 105 A +85°C Capacitor LPT1OSC = 0 PIC18LFXXJ11 44.4 110 A -40°C VDD = 3.3V, 53.1 110 A +25°C VDDCORE = 10 F 55.8 150 A +85°C Capacitor PIC18FXXJ11 4.5 31 A -40°C VDD = 2.5V, 3.8 31 A +25°C VDDCORE = 2.5V 4.1 50 A +85°C PIC18FXXJ11 34.7 87 A -40°C VDD = 2.15V, FOSC = 32kHz(3) 44.6 89 A +25°C VDDCORE = 10 F SEC_IDLE mode, 56.5 97 A +85°C Capacitor LPT1OSC = 0 PIC18LFXXJ11 37.3 100 A -40°C VDD = 3.3V, 45.7 100 A +25°C VDDCORE = 10 F 54.6 140 A +85°C Capacitor Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. 3: Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.  2011 Microchip Technology Inc. DS39932D-page 477

PIC18F46J11 FAMILY 29.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LFXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. Module Differential Currents (IWDT, IOSCB, IAD) D022 Watchdog Timer 0.86 8 A -40°C (IWDT) 0.97 8 A +25°C VDD = 2.5V, PIC18LFXXJ11 VDDCORE = 2.5V 0.98 10.4 A +85°C 0.71 7 A -40°C VDD = 2.15V, 0.82 7 A +25°C VDDCORE = 10 F PIC18FXXJ11 0.65 10 A +85°C Capacitor 1.54 12.1 A -40°C VDD = 3.3V, 1.33 12.1 A +25°C VDDCORE = 10 F PIC18FXXJ11 1.16 13.6 A +85°C Capacitor D022B High/Low-Voltage Detect 3.9 8 A -40°C VDD = 2.5V, (IHLVD) 4.7 8 A +25°C PIC18LFXXJ11 VDDCORE = 2.5V 5.4 9 A +85°C 2.7 6 A -40°C VDD = 2.15V, 3.2 6 A +25°C VDDCORE = 10 F PIC18FXXJ11 3.6 8 A +85°C Capacitor 3.5 9 A -40°C VDD = 3.3V, 4.1 9 A +25°C VDDCORE = 10 F PIC18FXXJ11 4.5 12 A +85°C Capacitor D025 Real-Time Clock/Calendar 0.67 4.0 A -40°C VDD = 2.15V, (IOSCB) with Low-Power 0.83 4.5 A +25°C VDDCORE = 10 F Timer1 Oscillator 0.95 4.5 A +60°C Capacitor 1.10 4.5 A +85°C 0.75 4.5 A -40°C VDD = 2.5V, PIC18FXXJ11 0.92 5.0 A +25°C VDDCORE = 10 F 32.768 kHz, T1OSCEN = 1, 1.04 5.0 A +60°C Capacitor LPT1OSC = 0 1.21 5.0 A +85°C 0.94 6.5 A -40°C VDD = 3.3V, 1.11 6.5 A +25°C VDDCORE = 10 F 1.24 8.0 A +60°C Capacitor 1.43 8.0 A +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. 3: Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39932D-page 478  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 29.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18LFXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXXJ11 Family Operating temperature -40°C  TA  +85°C for industrial Param Device Typ Max Units Conditions No. D026 A/D Converter 3.00 10 A -40°C VDD = 2.5V, PIC18LFXXJ11 (IAD) 3.00 10 A +25°C VDDCORE = 2.5V A/D on, not converting 3.00 10 A +85°C 3.00 10 A -40°C VDD = 2.15V, 3.00 10 A +25°C VDDCORE = 10 F Capacitor 3.00 10 A +85°C PIC18FXXJ11 3.20 11 A -40°C VDD = 3.3V, A/D on, not converting 3.20 11 A +25°C VDDCORE = 10 F 3.20 11 A +85°C Capacitor Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. All features that add delta current are disabled (WDT, etc.). The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD/VSS; MCLR = VDD; WDT disabled unless otherwise specified. 3: Low-Power Timer1 with standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.  2011 Microchip Technology Inc. DS39932D-page 479

PIC18F46J11 FAMILY 29.3 DC Characteristics: PIC18F46J11 Family (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage All I/O ports: D030 with TTL Buffer VSS 0.15 VDD V VDD < 3.3V D030A — 0.8 V 3.3V < VDD < 3.6V D031 with Schmitt Trigger Buffer VSS 0.2 VDD V D031A SDAx/SCLx — 0.3 VDD V I2C™ enabled D031B — 0.8 V SMBus enabled D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V EC, ECPLL modes D034 T1OSI VSS 0.3 V T1OSCEN = 1 VIH Input High Voltage I/O Ports with non 5.5V Tolerance:(4) D040 with TTL Buffer 0.25 VDD + 0.8V VDD V VDD < 3.3V D040A 2.0 VDD V 3.3V  VDD 3.6V D041 with Schmitt Trigger Buffer 0.8 VDD VDD V I/O Ports with 5.5V Tolerance:(4) V Dxxx with TTL Buffer 0.25 VDD + 0.8V 5.5 V VDD < 3.3V DxxxA 2.0 5.5 V 3.3V  VDD 3.6V Dxxx with Schmitt Trigger Buffer 0.8 VDD 5.5 V D041A SDAx/SCLx 0.7 VDD — V I2C™ enabled D041B 2.1 — SMBus enabled, VDD > 3V D042 MCLR 0.8 VDD 5.5 V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC, ECPLL modes D044 T1OSI 1.6 VDD V T1OSCEN = 1 IIL Input Leakage Current(1,2) D060 I/O Ports — ±0.2 A VSS VPIN VDD, Pin at high-impedance D061 MCLR — ±0.2 A Vss VPIN VDD D063 OSC1 — ±0.2 A Vss VPIN VDD IPU Weak Pull-up Current D070 IPURB PORTB, PORTD(3) and 80 400 A VDD = 3.3V, VPIN = VSS PORTE(3) Weak Pull-up Current Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2: Negative current is defined as current sourced by the pin. 3: Only available in 44-pin devices. 4: Refer to Table10-2 for the pins that have corresponding tolerance limits. DS39932D-page 480  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 29.3 DC Characteristics: PIC18F46J11 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O Ports: PORTA (Except RA6), — 0.4 V IOL = 2 mA, VDD = 3.3V, PORTD, PORTE -40C to +85C PORTB, PORTC, RA6 — 0.4 V IOL = 8.5 mA, VDD = 3.3V, -40C to +85C VOH Output High Voltage D090 I/O Ports: PORTA (Except RA6), 2.4 — V IOH = -2, VDD = 3.3V, PORTD, PORTE -40C to +85C PORTB, PORTC, RA6 2.4 — V IOH = -6 mA, VDD = 3.3V, -40C to +85C Capacitive Loading Specs on Output Pins D101 CIO All I/O Pins and OSC2 — 50 pF To meet the AC Timing Specifications D102 CB SCLx, SDAx — 400 pF I2C™ Specification Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2: Negative current is defined as current sourced by the pin. 3: Only available in 44-pin devices. 4: Refer to Table10-2 for the pins that have corresponding tolerance limits.  2011 Microchip Technology Inc. DS39932D-page 481

PIC18F46J11 FAMILY TABLE 29-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial Param Sym Characteristic Min Typ† Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 10K — — E/W -40C to +85C D131 VPR VDDcore for Read VMIN — 2.75 V VMIN = Minimum operating voltage D132B VPEW VDDCORE for Self-Timed Erase or 2.25 — 2.75 V Write D133A TIW Self-Timed Write Cycle Time — 2.8 — ms 64 bytes D133B TIE Self-Timed Block Erase Cycle Time — 33.0 — ms D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D135 IDDP Supply Current during Programming — 3 — mA † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. TABLE 29-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ±5 ±25 mV D301 VICM Input Common Mode Voltage 0 — VDD V VIRV Internal Reference Voltage 0.57 0.60 0.63 V D302 CMRR Common Mode Rejection Ratio 55 — — dB D303 TRESP Response Time(1) — 150 400 ns D304 TMC2OV Comparator Mode Change to Output Valid — — 10 s Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. TABLE 29-3: CTMU CURRENT SOURCE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Sym Characteristic Min Typ(1) Max Units Conditions No. IOUT1 CTMU Current Source, Base Range — 550 — nA CTMUICON<1:0> = 01 IOUT2 CTMU Current Source, 10x Range — 5.5 — A CTMUICON<1:0> = 10 IOUT3 CTMU Current Source, 100x Range — 55 — A CTMUICON<1:0> = 11 Note 1: Nominal value at center point of current trim range (CTMUICON<7:2> = 000000). TABLE 29-4: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb D312 VRUR Unit Resistor Value (R) — 2k —  310 TSET Settling Time(1) — — 10 s Note 1: Settling time measured while CVRR = 1 and CVR<3:0> bits transition from ‘0000’ to ‘1111’. DS39932D-page 482  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 29-5: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. VRGOUT Regulator Output Voltage 2.35 2.5 2.7 V Regulator enabled, VDD = 3.0V CEFC External Filter Capacitor Value(1) 5.4 10 18 F ESR < 3 recommended ESR < 5 required Note 1: CEFC applies for PIC18F devices in the family. For PIC18LF devices in the family, there is no specific mini- mum or maximum capacitance for VDDCORE, although proper supply rail bypassing should still be used. TABLE 29-6: ULPWU SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial Param Sym Characteristic Min Typ† Max Units Conditions No. D100 IULP Ultra Low-Power Wake-up Current — 60 — nA Net of I/O leakage and current sink at 1.6V on pin, VDD = 3.3V See Application Note AN879, “Using the Microchip Ultra Low-Power Wake-up Module” (DS00879) † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.  2011 Microchip Technology Inc. DS39932D-page 483

PIC18F46J11 FAMILY FIGURE 29-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (LVDIF set by hardware) (LVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD LVDIF TABLE 29-7: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial Param Symbol Characteristic Min Typ Max Units Conditions No. D420 HLVD Voltage on VDD HLVDL<3:0> = 1000 2.33 2.45 2.57 V Transition High-to- HLVDL<3:0> = 1001 2.47 2.60 2.73 V Low HLVDL<3:0> = 1010 2.66 2.80 2.94 V HLVDL<3:0> = 1011 2.76 2.90 3.05 V HLVDL<3:0> = 1100 2.85 3.00 3.15 V HLVDL<3:0> = 1101 2.97 3.13 3.29 V HLVDL<3:0> = 1110 3.23 3.40 3.57 V D421 TIRVST Time for Internal Reference Voltage to — 20 — s become Stable D422 TLVD High/Low-Voltage Detect Pulse Width 200 — — s DS39932D-page 484  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 29.4 AC (Timing) Characteristics 29.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition  2011 Microchip Technology Inc. DS39932D-page 485

PIC18F46J11 FAMILY 29.4.2 TIMING CONDITIONS The temperature and voltages specified in Table29-8 apply to all timing specifications unless otherwise noted. Figure29-4 specifies the load conditions for the timing specifications. TABLE 29-8: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA +85°C for industrial Operating voltage VDD range as described in Section29.1 and Section29.3. FIGURE 29-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKO/RA6 and including D and E outputs as ports CL = 15 pF for OSC2/CLKO/RA6 29.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 29-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO DS39932D-page 486  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 29-9: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 48 MHz EC Oscillator mode 4 12 ECPLL Oscillator mode Oscillator Frequency(1) 4 16 MHz HS Oscillator mode 4 12 HSPLL Oscillator mode 1 TOSC External CLKI Period(1) 20.8 — ns EC Oscillator mode 83.3 — ECPLL Oscillator mode Oscillator Period(1) 62.5 250 ns HS Oscillator mode 83.3 250 HSPLL Oscillator mode 2 TCY Instruction Cycle Time(1) 83.3 DC ns TCY = 4/FOSC, Industrial 3 TOSL, External Clock in (OSC1) 10 — ns EC Oscillator mode TOSH High or Low Time 4 TOSR, External Clock in (OSC1) — 7.5 ns EC Oscillator mode TOSF Rise or Fall Time Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. TABLE 29-10: PLL CLOCK TIMING SPECIFICATIONS Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FPLLIN PLL Input Frequency Range 4 — 12 MHz F11 FPLLO PLL Output Frequency (4x FPLLIN) 16 — 48 MHz F12 t PLL Start-up Time (lock time) — — 2 ms rc † Data in “Typ” column is at 3.3V, 25C, unless otherwise stated. TABLE 29-11: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES) Param Device Min Typ Max Units Conditions No. INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1) All Devices -1 +/-0.15 +1 % 0°C to +85°C VDD = 2.0-3.3V -1 +/-0.25 +1 % -40°C to +85°C VDD = 2.0-3.6V, VDDCORE = 2.0-2.7V INTRC Accuracy @ Freq = 31 kHz(1) All Devices 20.3 — 42.2 kHz -40°C to +85°C VDD = 2.0-3.6V, VDDCORE = 2.0-2.7V Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given time. When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’, use the INTRC accuracy specification.  2011 Microchip Technology Inc. DS39932D-page 487

PIC18F46J11 FAMILY FIGURE 29-6: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure29-4 for load conditions. TABLE 29-12: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1  to CLKO  — 75 200 ns (Note 1) 11 TOSH2CKH OSC1  to CLKO  — 75 200 ns (Note 1) 12 TCKR CLKO Rise Time — 15 30 ns (Note 1) 13 TCKF CLKO Fall Time — 15 30 ns (Note 1) 14 TCKL2IOV CLKO  to Port Out Valid — — 0.5 TCY + 20 ns 15 TIOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns 16 TCKH2IOI Port In Hold after CLKO  0 — — ns 17 TOSH2IOV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1  (Q2 cycle) to Port Input Invalid 100 — — ns (I/O in hold time) 19 TIOV2OSH Port Input Valid to OSC1  0 — — ns (I/O in setup time) 20 TIOR Port Output Rise Time — — 6 ns 21 TIOF Port Output Fall Time — — 5 ns 22† TINP INTx pin High or Low Time TCY — — ns 23† TRBP RB7:RB4 Change INTx High or Low TCY — — ns Time † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC. DS39932D-page 488  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 29-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure29-4 for load conditions. TABLE 29-13: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TMCL MCLR Pulse-Width (low) 2 — — s — 31 TWDT Watchdog Timer Time-out Period 2.8 4.0 5.3 ms — (no postscaler) 32 TOST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period — 1.0 — ms — 34 TIOZ I/O High-Impedance from MCLR — — 3 TCY + 2 s (Note 1) Low or Watchdog Timer Reset 36 TIRVST Time for Internal Reference — 20 — s — Voltage to become Stable 37 TLVD High/Low-Voltage Detect — 200 — s — Pulse Width 38 TCSD CPU Start-up Time — 200 — s (Note 2) Note 1: The maximum TIOZ is the lesser of (3 TCY + 2 s) or 700 s. 2: MCLR rising edge to code execution, assuming TPWRT (and TOST if applicable) has already expired.  2011 Microchip Technology Inc. DS39932D-page 489

PIC18F46J11 FAMILY TABLE 29-14: LOW-POWER WAKE-UP TIME Param. Symbol Characteristic Min Typ Max Units Conditions No. W1 WDS Deep Sleep — 1.5ms — s REGSLP = 1 W2 WSLEEP Sleep — 300µS — s REGSLP = 1, PLLEN =0, FOSC = 8MHz INTOSC W3 WDOZE1 Sleep — 12µS — s REGSLP = 0, PLLEN =0, FOSC = 8MHz INTOSC W4 WDOZE2 Sleep — 1.1µS — s REGSLP = 0, PLLEN =0, FOSC = 8MHz EC W5 WDOZE3 Sleep — 250nS — ns REGSLP = 0, PLLEN =0, FOSC = 48MHz EC W6 WIDLE Idle — 300nS — ns FOSC = 48MHz EC DS39932D-page 490  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 29-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure29-4 for load conditions. TABLE 29-15: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 TT1H T1CKI/T3CKI Synchronous, no prescaler 0.5 TCY + 20 — ns High Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 46 TT1L T1CKI/T3CKI Synchronous, no prescaler 0.5 TCY + 5 — ns Low Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 47 TT1P T1CKI/T3CKI Synchronous Greater of: — ns N = prescale Input Period 20ns or value (TCY + 40)/N (1, 2, 4, 8) Asynchronous 83 — ns FT1 T1CKI Input Frequency Range(1) DC 12 MHz 48 TCKE2TMRI Delay from External T1CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment Note 1: The Timer1 oscillator is designed to drive 32.768 kHz crystals. When T1CKI is used as a digital input, frequencies up to 12 MHz are supported.  2011 Microchip Technology Inc. DS39932D-page 491

PIC18F46J11 FAMILY FIGURE 29-9: ENHANCED CAPTURE/COMPARE/PWM TIMINGS ECCPx (Capture Mode) 50 51 52 ECCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure29-4 for load conditions. TABLE 29-16: ENHANCED CAPTURE/COMPARE/PWM REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 50 TCCL ECCPx Input Low Time No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 51 TCCH ECCPx Input High Time No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 52 TCCP ECCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TCCR ECCPx Output Fall Time — 25 ns 54 TCCF ECCPx Output Fall Time — 25 ns DS39932D-page 492  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 29-10: PARALLEL MASTER PORT READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 System Clock PMA<13:18> Address PMD<7:0> Address<7:0> Data PM6 PM2 PM7 PM3 PMRD PM5 PMWR PMALL/PMALH PM1 PMCS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated. TABLE 29-17: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No PM1 PMALL/PMALH Pulse Width — 0.5 TCY — ns PM2 Address Out Valid to PMALL/PMALH — 0.75 TCY — ns Invalid (address setup time) PM3 PMALL/PMALH Invalid to Address Out — 0.25 TCY — ns Invalid (address hold time) PM5 PMRD Pulse Width — 0.5 TCY — ns PM6 PMRD or PMENB Active to Data In Valid — — — ns (data setup time) PM7 PMRD or PMENB Inactive to Data In Invalid — — — ns (data hold time)  2011 Microchip Technology Inc. DS39932D-page 493

PIC18F46J11 FAMILY FIGURE 29-11: PARALLEL MASTER PORT WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 System Clock PMA<13:18> Address PMD<7:0> Address<7:0> Data PM12 PM13 PMRD PMWR PM11 PMALL/ PMALH PMCS PM16 Note: Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated. TABLE 29-18: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No PM11 PMWR Pulse Width — 0.5 TCY — ns PM12 Data Out Valid before PMWR or PMENB — — — ns goes Inactive (data setup time) PM13 PMWR or PMEMB Invalid to Data Out — — — ns Invalid (data hold time) PM16 PMCS Pulse Width TCY – 5 — — ns DS39932D-page 494  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 29-12: PARALLEL SLAVE PORT TIMING PMCS PMRD PMWR PS4 PMD<7:0> PS1 PS3 PS2 TABLE 29-19: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param. Symbol Characteristic Min Typ Max Units Conditions No. PS1 TdtV2wrH Data In Valid before PMWR or PMCS 20 — — ns Inactive (setup time) PS2 TwrH2dtI PMWR or PMCS Inactive to Data–In 20 — — ns Invalid (hold time) PS3 TrdL2dtV PMRD and PMCS Active to Data–Out — — 80 ns Valid PS4 TrdH2dtI PMRD Inactiveor PMCS Inactive to 10 — 30 ns Data–Out Invalid  2011 Microchip Technology Inc. DS39932D-page 495

PIC18F46J11 FAMILY FIGURE 29-13: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SSx SCKx (CKP = 0) 78 79 SCKx (CKP = 1) 79 78 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure29-4 for load conditions. TABLE 29-20: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 35 — ns VDD = 3.3V, TDIV2SCL VDDCORE = 2.5V 100 — ns VDD = 2.15V, VDDCORE = 2.15V 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 30 — ns VDD = 3.3V, TSCL2DIL VDDCORE = 2.5V 83 — ns VDD = 2.15V 75 TDOR SDOx Data Output Rise Time — 25 ns PORTB or PORTC 76 TDOF SDOx Data Output Fall Time — 25 ns PORTB or PORTC 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns PORTB or PORTC 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns PORTB or PORTC DS39932D-page 496  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 29-14: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SSx 81 SCKx (CKP = 0) 79 73 SCKx (CKP = 1) 78 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure29-4 for load conditions. TABLE 29-21: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 35 — ns VDD = 3.3V, TDIV2SCL VDDCORE = 2.5V 100 — ns VDD = 2.15V, VDDCORE = 2.15V 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 30 — ns VDD = 3.3V, TSCL2DIL VDDCORE = 2.5V 83 — ns VDD = 2.15V 75 TDOR SDOx Data Output Rise Time — 25 ns PORTB or PORTC 76 TDOF SDOx Data Output Fall Time — 25 ns PORTB or PORTC 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns PORTB or PORTC 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns PORTB or PORTC 81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TCY — ns TDOV2SCL  2011 Microchip Technology Inc. DS39932D-page 497

PIC18F46J11 FAMILY FIGURE 29-15: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SSx 70 SCKx (CKP = 0) 83 71 72 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure29-4 for load conditions. TABLE 29-22: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx  to SCKx  or SCKx  Input 3 TCY — ns TSSL2SCL 70A TSSL2WB SSx to Write to SSPxBUF 3 TCY — ns 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 25 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge 1.5 TCY + 40 — ns (Note 2) of Byte 2 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 35 — ns VDD = 3.3V, TSCL2DIL VDDCORE = 2.5V 100 — ns VDD = 2.15V 75 TDOR SDOx Data Output Rise Time — 25 ns PORTB or PORTC 76 TDOF SDOx Data Output Fall Time — 25 ns PORTB or PORTC 77 TSSH2DOZ SSx  to SDOx Output High-Impedance 10 70 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns VDD = 3.3V, TSCL2DOV VDDCORE = 2.5V 100 ns VDD = 2.15V 83 TSCH2SSH, SSx  after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39932D-page 498  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY FIGURE 29-16: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SSx 70 SCKx 83 (CKP = 0) 71 72 73 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure29-4 for load conditions. TABLE 29-23: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx  to SCKx  or SCKx  Input 3 TCY — ns TSSL2SCL 70A TSSL2WB SSx to Write to SSPxBUF 3 TCY — ns 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 25 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 35 — ns VDD = 3.3V, TSCL2DIL VDDCORE = 2.5V 100 — ns VDD = 2.15V 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx  to SDOx Output High-Impedance 10 70 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns VDD = 3.3V, TSCL2DOV VDDCORE = 2.5V — 100 ns VDD = 2.15V 81 TDOV2SCH SDOx Data Output Setup to SCKx Edge TCY — ns , TDOV2SCL 82 TSSL2DOV SDOx Data Output Valid after SSx  Edge — 50 ns 83 TSCH2SSH, SSx  after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used.  2011 Microchip Technology Inc. DS39932D-page 499

PIC18F46J11 FAMILY FIGURE 29-17: I2C™ BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure29-4 for load conditions. TABLE 29-24: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 29-18: I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure29-4 for load conditions. DS39932D-page 500  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 29-25: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s MSSP modules 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s MSSP modules 1.5 TCY — 102 TR SDAx and SCLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDAx and SCLx Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — s Only relevant for Repeated 400 kHz mode 0.6 — s Start condition 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — s After this period, the first clock 400 kHz mode 0.6 — s pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCLx line is released.  2011 Microchip Technology Inc. DS39932D-page 501

PIC18F46J11 FAMILY FIGURE 29-19: MSSPx I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure29-4 for load conditions. TABLE 29-26: MSSPx I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns — Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns — Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — FIGURE 29-20: MSSPx I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 91 107 92 SDAx In 109 109 110 SDAx Out Note: Refer to Figure29-4 for load conditions. DS39932D-page 502  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 29-27: MSSPx I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 102 TR SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 103 TF SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 1) Setup Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free before a new 400 kHz mode 1.3 — ms transmission can start D102 CB Bus Capacitive — 400 pF Loading Note 1: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, parameter #102 + parameter #107=1000+250=1250ns (for 100 kHz mode), before the SCLx line is released.  2011 Microchip Technology Inc. DS39932D-page 503

PIC18F46J11 FAMILY FIGURE 29-21: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 122 Note: Refer to Figure29-4 for load conditions. TABLE 29-28: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV Sync XMIT (Master and Slave) Clock High to Data Out Valid — 40 ns 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns 122 TDTRF Data Out Rise Time and Fall Time — 20 ns FIGURE 29-22: EUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TXx/CKx pin 125 RXx/DTx pin 126 Note: Refer to Figure29-4 for load conditions. TABLE 29-29: EUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL Sync RCV (Master and Slave) Data Hold before CKx  (DTx hold time) 10 — ns 126 TCKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns DS39932D-page 504  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY TABLE 29-30: A/D CONVERTER CHARACTERISTICS: PIC18F46J11 FAMILY (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit VREF  3.0V A03 EIL Integral Linearity Error — — <±1 LSb VREF  3.0V A04 EDL Differential Linearity Error — — <±1 LSb VREF  3.0V A06 EOFF Offset Error — — <±3 LSb VREF  3.0V A07 EGN Gain Error — — <±3.5 LSb VREF  3.0V A10 Monotonicity Guaranteed(1) — VSS  VAIN  VREF A20 VREF Reference Voltage Range 2.0 — — V VDD  3.0V (VREFH – VREFL) 3 — — V VDD  3.0V A21 VREFH Reference Voltage High VREFL — VDD + 0.3V V A22 VREFL Reference Voltage Low VSS – 0.3V — VREFH V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 2.5 k Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 A During VAIN acquisition. — — 150 A During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+/C1INB pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF-/CVREF/C2INB pin or VSS, whichever is selected as the VREFL source.  2011 Microchip Technology Inc. DS39932D-page 505

PIC18F46J11 FAMILY FIGURE 29-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 A/D DATA 9 8 7 . . . . . . 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY (Note 1) GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 29-31: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period 0.7 25.0(1) s TOSC based, VREF  3.0V 131 TCNV Conversion Time 11 12 TAD A/D RC Mode (not including acquisition time)(2) — 1 s 132 TACQ Acquisition Time(3) 1.4 — s -40C to +85C 135 TSWC Switching Time from Convert  Sample — (Note 4) 137 TDIS Discharge Time 0.2 — s Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. 4: On the following cycle of the device clock. DS39932D-page 506  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX PIC18F26J11 XXXXXXXXXXXXXXXXX -I/SPe3 YYWWNNN 0910017 28-Lead SSOP Example XXXXXXXXXXXX PIC18F26J11 XXXXXXXXXXXX /SSe3 YYWWNNN 0910017 28-Lead SOIC (.300”) Example XXXXXXXXXXXXXXXXXXXX PIC18F26J11/SO e3 XXXXXXXXXXXXXXXXXXXX 0910017 XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN Example XXXXXXXX 18F26J11 XXXXXXXX /MLe3 YYWWNNN 0910017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011 Microchip Technology Inc. DS39932D-page 507

PIC18F46J11 FAMILY 44-Lead QFN Example XXXXXXXXXX 18F46J11 XXXXXXXXXX -I/ML e3 XXXXXXXXXX 0910017 YYWWNNN 44-Lead TQFP Example XXXXXXXXXX 18F46J11 XXXXXXXXXX -I/PT e3 XXXXXXXXXX 0910017 YYWWNNN DS39932D-page 508  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 30.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)(cid:26)(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1  2011 Microchip Technology Inc. DS39932D-page 509

PIC18F46J11 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)#$(cid:12)(cid:13)(cid:11)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)%(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:10)(cid:24)(cid:9)(cid:25)(cid:9)&’(cid:26)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:10)%(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:30)(cid:4)(cid:20)(cid:3)(cid:4) (cid:30)(cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)-1 DS39932D-page 510  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)%(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)%(cid:24)(cid:9)(cid:25)(cid:9)((cid:12)(cid:8)(cid:6))(cid:9)*’&(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)%(cid:22)+ !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 3 e b h α h φ c A A2 L A1 L1 β 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)?(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:3)(cid:20)(cid:4)(cid:29) = = (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2)+ (cid:25)(cid:30) (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)-(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:4)(cid:20)-(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:5)(cid:20)(cid:29)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:5)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), ,(cid:11)(cid:28)’%(cid:14)(cid:9)(cid:2)A(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)B (cid:11) (cid:4)(cid:20)(cid:3)(cid:29) = (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) = (cid:30)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:23)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:3) (cid:4)@ = <@ 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:30)< = (cid:4)(cid:20)-- 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:30) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:29)@ = (cid:30)(cid:29)@ (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:29)@ = (cid:30)(cid:29)@ !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:3)1  2011 Microchip Technology Inc. DS39932D-page 511

PIC18F46J11 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18))(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7).(cid:6)(cid:9)(cid:23)/(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)010(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31),-! 2(cid:12)(cid:18)#(cid:9)(cid:27)’&&(cid:9)(cid:28)(cid:28)(cid:9)+(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13).(cid:18)# !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)- (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# C (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)(cid:29)1 DS39932D-page 512  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18))(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7).(cid:6)(cid:9)(cid:23)/(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)010(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31),-! 2(cid:12)(cid:18)#(cid:9)(cid:27)’&&(cid:9)(cid:28)(cid:28)(cid:9)+(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13).(cid:18)# !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2011 Microchip Technology Inc. DS39932D-page 513

PIC18F46J11 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18))(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7).(cid:6)(cid:9)(cid:23)/(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)(cid:3)1(cid:3)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31),-! !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE1 N L K TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:23) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:29) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-< ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:29)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# C (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)-1 DS39932D-page 514  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18))(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7).(cid:6)(cid:9)(cid:23)/(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)(cid:3)1(cid:3)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31),-! !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2011 Microchip Technology Inc. DS39932D-page 515

PIC18F46J11 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)4#(cid:12)(cid:13)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18)5(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)4(cid:24)(cid:9)(cid:25)(cid:9)6(cid:27)16(cid:27)16(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14))(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)4,-(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)9(cid:14)(cid:28)#! 7 (cid:23)(cid:23) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)<(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:24)(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ -(cid:20)(cid:29)@ (cid:5)@ : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:5) (cid:4)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:30)(cid:30)@ (cid:30)(cid:3)@ (cid:30)-@ (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:30)(cid:30)@ (cid:30)(cid:3)@ (cid:30)-@ !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ,(cid:11)(cid:28)’%(cid:14)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:8)(cid:10)(cid:9)(cid:15)(cid:14)(cid:9)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:2)(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)D(cid:2)!(cid:7)E(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:30)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)?1 DS39932D-page 516  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)4#(cid:12)(cid:13)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18)5(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)4(cid:24)(cid:9)(cid:25)(cid:9)6(cid:27)16(cid:27)16(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14))(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)4,-(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2011 Microchip Technology Inc. DS39932D-page 517

PIC18F46J11 FAMILY NOTES: DS39932D-page 518  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (October 2008) The differences between the devices listed in this data Original data sheet for the PIC18F46J11 family of sheet are shown in TableB-1, devices. Revision B (February 2009) Changes to the Electrical Characteristics and minor edits throughout text. Revision C (October 2009) Removed “Preliminary” marking. Revision D (March 2011) Committed data sheet errata changes and minor corrections throughout text. TABLE B-1: DEVICE DIFFERENCES BETWEEN PIC18F46J11 FAMILY MEMBERS Features PIC18F24J11 PIC18F25J11 PIC18F26J11 PIC18F44J11 PIC18F45J11 PIC18F46J11 Program Memory 16K 32K 64K 16K 32K 64K Program Memory 8,192 16,384 32,768 8,192 16,384 32,768 (Instructions) I/O Ports (Pins) Ports A, B, C Ports A, B, C, D, E 10-Bit ADC Module 10 Input Channels 13 Input Channels Packages 28-Pin QFN, SOIC, SSOP and SPDIP (300 mil) 44-Pin QFN and TQFP  2011 Microchip Technology Inc. DS39932D-page 519

PIC18F46J11 FAMILY NOTES: DS39932D-page 520  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY INDEX A CTMU ......................................................................379 CTMU Current Source Calibration Circuit ...............382 A/D ...................................................................................351 CTMU Typical Connections and Internal A/D Converter Interrupt, Configuring .......................355 Configuration for Pulse Delay Generation .......390 Acquisition Requirements ........................................356 CTMU Typical Connections and Internal ADCAL Bit ................................................................359 Configuration for Time Measurement ..............389 ADRESH Register ....................................................354 Demultiplexed Addressing Mode .............................186 Analog Port Pins, Configuring ..................................357 Device Clock ..............................................................38 Associated Registers ...............................................360 EUSART Transmit ...................................................337 Automatic Acquisition Time ......................................357 EUSARTx Receive ..................................................339 Calibration ................................................................359 Fail-Safe Clock Monitor ...........................................410 Configuring the Module ............................................355 Fully Multiplexed Addressing Mode .........................186 Conversion Clock (TAD) ...........................................357 Generic I/O Port Operation ......................................131 Conversion Requirements .......................................506 High/Low-Voltage Detect with External Input ..........374 Conversion Status (GO/DONE Bit) ..........................354 Interrupt Logic ..........................................................116 Conversions .............................................................358 LCD Control .............................................................194 Converter Characteristics ........................................505 Legacy Parallel Slave Port ......................................180 Operation in Power-Managed Modes ......................359 MSSPx (I2C Master Mode) ......................................311 Special Event Trigger (ECCPx) ...............................358 MSSPx (I2C Mode) ..................................................291 Use of the ECCP2 Trigger .......................................358 MSSPx (SPI Mode) .................................................272 Absolute Maximum Ratings .............................................467 Multiplexed Addressing Application .........................193 AC (Timing) Characteristics .............................................485 On-Chip Reset Circuit ................................................63 Load Conditions for Device Timing Specifications ...486 Parallel EEPROM (Up to 15-Bit Address, 16-Bit Parameter Symbology .............................................485 Data) ................................................................194 Temperature and Voltage Specifications .................486 Parallel EEPROM (Up to 15-Bit Address, 8-Bit Timing Conditions ....................................................486 Data) ................................................................194 ACKSTAT ........................................................................316 Parallel Master/Slave Connection Addressed Buffer 183 ACKSTAT Status Flag .....................................................316 Parallel Master/Slave Connection Buffered .............182 ADCAL Bit ........................................................................359 Partially Multiplexed Addressing Application ...........193 ADCON0 Register Partially Multiplexed Addressing Mode ....................186 GO/DONE Bit ...........................................................354 PIC18F2XJ11 (28-Pin) ..............................................14 ADDFSR ..........................................................................456 PIC18F4XJ11 (44-Pin) ..............................................15 ADDLW ............................................................................419 PMP Module ............................................................171 ADDULNK ........................................................................456 PWM (Enhanced) ....................................................255 ADDWF ............................................................................419 PWM Operation (Simplified) ....................................252 ADDWFC .........................................................................420 Reads From Flash Program Memory ......................107 ADRESL Register ............................................................354 RTCC .......................................................................227 Analog-to-Digital Converter. See A/D. Simplified Steering ...................................................268 ANDLW ............................................................................420 Single Comparator ...................................................364 ANDWF ............................................................................421 Table Read Operation .............................................103 Assembler Table Write Operation .............................................104 MPASM Assembler ..................................................464 Table Writes to Flash Program Memory ..................109 Auto-Wake-up on Sync Break Character .........................340 Timer0 in 16-Bit Mode .............................................198 B Timer0 in 8-Bit Mode ...............................................198 Bank Select Register .........................................................84 Timer1 .....................................................................205 Baud Rate Generator .......................................................312 Timer2 .....................................................................214 BC ....................................................................................421 Timer3 .....................................................................218 BCF ..................................................................................422 Timer4 .....................................................................226 BF ....................................................................................316 Using the Open-Drain Output ..................................132 BF Status Flag .................................................................316 Watchdog Timer ......................................................405 Block Diagrams BN ....................................................................................422 +5V System Hardware Interface ..............................132 BNC .................................................................................423 8-Bit Multiplexed Address and Data Application ......193 BNN .................................................................................423 A/D ...........................................................................354 BNOV ..............................................................................424 Analog Input Model ..................................................355 BNZ .................................................................................424 Baud Rate Generator ...............................................313 BOR. See Brown-out Reset. Capture Mode Operation .........................................250 BOV .................................................................................427 Comparator Analog Input Model ..............................364 BRA .................................................................................425 Comparator Configurations ......................................366 Break Character (12-Bit) Transmit and Receive ..............342 Comparator Output ..................................................361 BRG. See Baud Rate Generator. Comparator Voltage Reference ...............................369 Brown-out Reset (BOR) .....................................................65 Comparator Voltage Reference Output Buffer and On-Chip Voltage Regulator ..............................408 Example ...........................................................371 Detecting ...................................................................65  2011 Microchip Technology Inc. DS39932D-page 521

PIC18F46J11 FAMILY Disabling in Sleep Mode ............................................65 Effects of a Reset ....................................................368 BSF ..................................................................................425 Enable and Input Selection ......................................365 BTFSC .............................................................................426 Enable and Output Selection ...................................365 BTFSS ..............................................................................426 Interrupts .................................................................367 BTG ..................................................................................427 Operation .................................................................364 BZ .....................................................................................428 Operation During Sleep ...........................................368 Registers .................................................................361 C Response Time ........................................................364 C Compilers Comparator Specifications ...............................................482 MPLAB C18 .............................................................464 Comparator Voltage Reference .......................................369 MPLAB C30 .............................................................464 Accuracy and Error ..................................................371 Calibration (A/D Converter) ..............................................359 Associated Registers ...............................................371 CALL ................................................................................428 Configuring ..............................................................370 CALLW .............................................................................457 Connection Considerations ......................................371 Capture (ECCP Module) ..................................................249 Effects of a Reset ....................................................371 CCPRxH:CCPRxL Registers ...................................249 Operation During Sleep ...........................................371 ECCP Pin Configuration ..........................................249 Compare (ECCP Module) ................................................251 Prescaler ..................................................................250 CCPRx Register ......................................................251 Software Interrupt ....................................................249 Pin Configuration .....................................................251 Timer1/Timer3 Mode Selection ................................249 Software Interrupt ....................................................251 Clock Sources ....................................................................42 Special Event Trigger ......................................223, 251 Effects of Power-Managed Modes .............................46 Timer1/Timer3 Mode Selection ................................251 Selecting the 31 kHz Source ......................................43 Compare (ECCPx Module) Selection Using OSCCON Register ...........................43 Special Event Trigger ..............................................358 CLRF ................................................................................429 Computed GOTO ...............................................................81 CLRWDT ..........................................................................429 Configuration Bits ............................................................395 Code Examples Configuration Mismatch (CM) Reset ..................................66 16 x 16 Signed Multiply Routine ..............................114 Configuration Register Protection ....................................411 16 x 16 Unsigned Multiply Routine ..........................114 Configuration Registers 512-Byte SPI Master Mode Init and Transfer ...........289 Bits and Device IDs .................................................396 8 x 8 Signed Multiply Routine ..................................113 Mapping Flash Configuration Words .......................396 8 x 8 Unsigned Multiply Routine ..............................113 Core Features A/D Calibration Routine ...........................................359 Easy Migration ...........................................................12 Calculating Baud Rate Error ....................................332 Expanded Memory .....................................................11 Capacitance Calibration Routine .............................386 Extended Instruction Set ...........................................12 Capacitive Touch Switch Routine ............................388 nanoWatt Technology ................................................11 Changing Between Capture Prescalers ...................250 Oscillator Options and Features ................................11 Communicating with the +5V System ......................132 CPFSEQ ..........................................................................430 Computed GOTO Using an Offset Value ...................81 CPFSGT ..........................................................................431 Configuring EUSART2 Input and Output Functions .154 CPFSLT ...........................................................................431 Current Calibration Routine .....................................384 Crystal Oscillator/Ceramic Resonators ..............................39 Erasing Flash Program Memory ..............................108 CTMU Fast Register Stack ....................................................81 Associated Registers ...............................................393 How to Clear RAM (Bank 1) Using Indirect Calibrating ...............................................................381 Addressing .........................................................97 Creating a Delay with ...............................................390 Initializing PORTA ....................................................135 Effects of a Reset ....................................................390 Initializing PORTB ....................................................138 Initialization ..............................................................381 Initializing PORTC ....................................................142 Measuring Capacitance with ....................................387 Initializing PORTD ....................................................145 Measuring Time with ................................................389 Initializing PORTE ....................................................148 Operation .................................................................380 Loading the SSP1BUF (SSP1SR) Register .............275 Operation During Idle Mode .....................................390 Reading a Flash Program Memory Word ................107 Operation During Sleep Mode .................................390 Saving STATUS, WREG and BSR Registers in CTMU Current Source Specifications ..............................482 RAM .................................................................130 Customer Change Notification Service ............................533 Setup for CTMU Calibration Routines ......................383 Customer Notification Service .........................................533 Single-Word Write to Flash Program Memory .........111 Customer Support ............................................................533 Two-Word Instructions ...............................................83 D Ultra Low-Power Wake-up Initialization .....................62 Writing to Flash Program Memory ...........................110 Data Addressing Modes ....................................................97 Code Protection ...............................................................395 Comparing Addressing Modes with the COMF ...............................................................................430 Extended Instruction Set Enabled ...................101 Comparator ......................................................................361 Direct .........................................................................97 Analog Input Connection Considerations .................364 Indexed Literal Offset ..............................................100 Associated Registers ...............................................368 BSR .................................................................102 Configuration ............................................................365 Instructions Affected ........................................101 Control .....................................................................365 Mapping Access Bank .....................................102 DS39932D-page 522  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY Indirect .......................................................................97 Auto-Wake-up on Sync Break .........................340 Inherent and Literal ....................................................97 Receiver ..........................................................339 Data Memory .....................................................................84 Setting Up 9-Bit Mode with Address Detect ....339 Access Bank ..............................................................86 Transmitter ......................................................337 Extended Instruction Set ............................................99 Baud Rate Generator General Purpose Registers ........................................86 Operation in Power-Managed Mode ................331 Memory Maps Baud Rate Generator (BRG) ...................................331 Access Bank Special Function Registers ..........87 Associated Registers .......................................332 Non-Access Bank Special Function Registers ..88 Auto-Baud Rate Detect ....................................335 PIC18F46J11 Family Devices ...........................85 Baud Rates, Asynchronous Modes .................333 Special Function Registers ........................................87 Formulas ..........................................................331 Context Defined SFRs .......................................89 High Baud Rate Select (BRGH Bit) .................331 DAW .................................................................................432 Sampling .........................................................331 DC Characteristics ...........................................................480 Synchronous Master Mode ......................................343 Power-Down and Supply Current ............................470 Associated Registers, Reception .....................346 Supply Voltage .........................................................469 Associated Registers, Transmission ...............344 DCFSNZ ..........................................................................433 Reception ........................................................345 DECF ...............................................................................432 Transmission ...................................................343 DECFSZ ...........................................................................433 Synchronous Slave Mode ........................................347 Development Support ......................................................463 Associated Registers, Reception .....................349 Device Differences ...........................................................519 Associated Registers, Transmission ...............348 Device Overview ................................................................11 Reception ........................................................349 Details on Individual Family Members .......................12 Transmission ...................................................347 Features (28-Pin Devices) .........................................13 Extended Instruction Set Features (44-Pin Devices) .........................................13 ADDFSR ..................................................................456 Other Special Features ..............................................12 ADDULNK ...............................................................456 Direct Addressing ...............................................................98 CALLW ....................................................................457 MOVSF ....................................................................457 E MOVSS ....................................................................458 Effect on Standard PIC MCU Instructions ........................460 PUSHL .....................................................................458 Electrical Characteristics ..................................................467 SUBFSR ..................................................................459 Absolute Maximum Ratings .....................................467 SUBULNK ................................................................459 Enhanced Capture/Compare/PWM (ECCP) ....................247 Extended Instructions Associated Registers ...............................................269 Considerations when Enabling ................................460 Capture Mode. See Capture. External Clock Input ...........................................................40 Compare Mode. See Compare. F ECCP Mode and Timer Resources ..........................249 Enhanced PWM Mode .............................................255 Fail-Safe Clock Monitor ...........................................395, 409 Auto-Restart .....................................................264 Interrupts in Power-Managed Modes ......................411 Auto-Shutdown ................................................263 POR or Wake-up From Sleep ..................................411 Direction Change in Full-Bridge Output Mode .261 WDT During Oscillator Failure .................................410 Full-Bridge Application .....................................259 Fast Register Stack ...........................................................81 Full-Bridge Mode .............................................259 Features Overview ...............................................................3 Half-Bridge Application ....................................258 Comparative Table ......................................................4 Half-Bridge Application Examples ...................265 Firmware Instructions ......................................................413 Half-Bridge Mode .............................................258 Flash Program Memory ...................................................103 Output Relationships (Active-High) ..................256 Associated Registers ...............................................112 Output Relationships Diagram (Active-Low) ....257 Control Registers .....................................................104 Programmable Dead-Band Delay ....................265 EECON1 and EECON2 ...................................104 Shoot-Through Current ....................................265 TABLAT (Table Latch) .....................................106 Start-up Considerations ...................................262 TBLPTR (Table Pointer) Register ....................106 Outputs and Configuration .......................................249 Erase Sequence ......................................................108 Enhanced Universal Synchronous Asynchronous Erasing ....................................................................108 Receiver Transmitter (EUSART). See EUSART. Operation During Code-Protect ...............................112 Equations Reading ...................................................................107 A/D Acquisition Time ................................................356 Table Pointer A/D Minimum Charging Time ...................................356 Boundaries Based on Operation .....................106 Bytes Transmitted for a Given DMABC ...................287 Table Pointer Boundaries ........................................106 Calculating the Minimum Required Acquisition Table Reads and Table Writes ................................103 Time .................................................................356 Write Sequence .......................................................109 Errata ...................................................................................9 Write Sequence (Word Programming) ....................111 EUSART ..........................................................................327 Writing .....................................................................109 Asynchronous Mode ................................................337 Unexpected Termination .................................112 12-Bit Break Transmit and Receive .................342 Write Verify ......................................................112 Associated Registers, Reception .....................340 FSCM. See Fail-Safe Clock Monitor. Associated Registers, Transmission ................338  2011 Microchip Technology Inc. DS39932D-page 523

PIC18F46J11 FAMILY G INCF ................................................................................434 INCFSZ ............................................................................435 GOTO ...............................................................................434 In-Circuit Debugger ..........................................................412 H In-Circuit Serial Programming (ICSP) ......................395, 412 Hardware Multiplier ..........................................................113 Indexed Literal Offset Addressing 8 x 8 Multiplication Algorithms .................................113 and Standard PIC18 Instructions .............................460 Operation .................................................................113 Indexed Literal Offset Mode .............................................460 Performance Comparison (table) .............................113 Indirect Addressing ............................................................98 High/Low-Voltage Detect .................................................373 INFSNZ ............................................................................435 Applications ..............................................................377 Initialization Conditions ................................................69–75 Associated Registers ...............................................378 Instruction Cycle ................................................................82 Characteristics .........................................................484 Clocking Scheme .......................................................82 Current Consumption ...............................................375 Flow/Pipelining ...........................................................82 Effects of a Reset .....................................................378 Instruction Set ..................................................................413 Operation .................................................................374 ADDLW ....................................................................419 During Sleep ....................................................378 ADDWF ....................................................................419 Setup ........................................................................375 ADDWF (Indexed Literal Offset Mode) ....................461 Start-up Time ...........................................................375 ADDWFC .................................................................420 Typical Application ...................................................377 ANDLW ....................................................................420 ANDWF ....................................................................421 I BC ............................................................................421 I/O Ports ...........................................................................131 BCF .........................................................................422 Open-Drain Outputs .................................................132 BN ............................................................................422 Pin Capabilities ........................................................131 BNC .........................................................................423 TTL Input Buffer Option ...........................................132 BNN .........................................................................423 I2C Mode ..........................................................................291 BNOV ......................................................................424 I2C Mode (MSSP) BNZ .........................................................................424 Acknowledge Sequence Timing ...............................319 BOV .........................................................................427 Associated Registers ...............................................325 BRA .........................................................................425 Baud Rate Generator ...............................................312 BSF ..........................................................................425 Bus Collision BSF (Indexed Literal Offset Mode) ..........................461 During a Repeated Start Condition ..................323 BTFSC .....................................................................426 During a Stop Condition ...................................324 BTFSS .....................................................................426 Clock Arbitration .......................................................314 BTG .........................................................................427 Clock Stretching .......................................................306 BZ ............................................................................428 10-Bit Slave Receive Mode (SEN = 1) .............306 CALL ........................................................................428 10-Bit Slave Transmit Mode .............................306 CLRF .......................................................................429 7-Bit Slave Receive Mode (SEN = 1) ...............306 CLRWDT .................................................................429 7-Bit Slave Transmit Mode ...............................306 COMF ......................................................................430 Clock Synchronization and CKP bit .........................307 CPFSEQ ..................................................................430 Effects of a Reset .....................................................320 CPFSGT ..................................................................431 General Call Address Support .................................310 CPFSLT ...................................................................431 I2C Clock Rate w/BRG .............................................313 DAW ........................................................................432 Master Mode ............................................................310 DCFSNZ ..................................................................433 Operation .........................................................311 DECF .......................................................................432 Reception .........................................................316 DECFSZ ..................................................................433 Repeated Start Condition Timing .....................315 Extended Instructions ..............................................455 Start Condition Timing .....................................314 Considerations when Enabling ........................460 Transmission ....................................................316 Syntax ..............................................................455 Multi-Master Communication, Bus Collision and Use with MPLAB IDE Tools .............................462 Arbitration .........................................................320 General Format ........................................................415 Multi-Master Mode ...................................................320 GOTO ......................................................................434 Operation .................................................................296 INCF ........................................................................434 Read/Write Bit Information (R/W Bit) ...............296, 299 INCFSZ ....................................................................435 Registers ..................................................................291 INFSNZ ....................................................................435 Serial Clock (SCLx Pin) ...........................................299 IORLW .....................................................................436 Slave Mode ..............................................................296 IORWF .....................................................................436 Addressing .......................................................296 LFSR .......................................................................437 Addressing Masking Modes MOVF ......................................................................437 5-Bit .........................................................297 MOVFF ....................................................................438 7-Bit .........................................................298 MOVLB ....................................................................438 Reception .........................................................299 MOVLW ...................................................................439 Transmission ....................................................299 MOVWF ...................................................................439 Sleep Operation .......................................................320 MULLW ....................................................................440 Stop Condition Timing ..............................................319 MULWF ....................................................................440 DS39932D-page 524  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY NEGF .......................................................................441 L NOP .........................................................................441 LFSR ...............................................................................437 Opcode Field Descriptions .......................................414 Low-Power Modes .............................................................47 POP .........................................................................442 Clock Transitions and Status Indicators ....................48 PUSH .......................................................................442 Deep Sleep Mode ......................................................54 RCALL .....................................................................443 and RTCC Peripheral ........................................56 RESET .....................................................................443 Brown-out Reset (DSBOR) ................................56 RETFIE ....................................................................444 Preparing for ......................................................55 RETLW ....................................................................444 Registers ...........................................................58 RETURN ..................................................................445 Typical Sequence ..............................................57 RLCF ........................................................................445 Wake-up Sources ..............................................56 RLNCF .....................................................................446 Watchdog Timer (DSWDT) ................................56 RRCF .......................................................................446 Exiting Idle and Sleep Modes ....................................54 RRNCF ....................................................................447 By Interrupt ........................................................54 SETF ........................................................................447 By Reset ............................................................54 SETF (Indexed Literal Offset Mode) ........................461 By WDT Time-out ..............................................54 SLEEP .....................................................................448 Without an Oscillator Start-up Delay .................54 Standard Instructions ...............................................413 Idle Modes .................................................................52 SUBFWB ..................................................................448 PRI_IDLE ..........................................................52 SUBLW ....................................................................449 RC_IDLE ...........................................................54 SUBWF ....................................................................449 SEC_IDLE .........................................................52 SUBWFB ..................................................................450 Multiple Sleep Commands .........................................48 SWAPF ....................................................................450 Run Modes ................................................................48 TBLRD .....................................................................451 PRI_RUN ...........................................................48 TBLWT .....................................................................452 RC_RUN ............................................................50 TSTFSZ ...................................................................453 SEC_RUN .........................................................48 XORLW ....................................................................453 Sleep Mode ...............................................................51 XORWF ....................................................................454 Summary (table) ........................................................48 INTCON ...........................................................................117 Ultra Low-Power Wake-up .........................................61 INTCON Registers ...........................................................117 Inter-Integrated Circuit. See I2C. M Internal Oscillator Master Clear (MCLR) .........................................................65 Frequency Drift. See INTOSC Frequency Drift. Master Synchronous Serial Port (MSSP). See MSSP. Internal Oscillator Block .....................................................40 Memory Organization ........................................................77 Adjustment .................................................................41 Data Memory .............................................................84 OSCTUNE Register ...................................................41 Program Memory .......................................................77 Internal RC Oscillator Return Address Stack ................................................79 Use with WDT ..........................................................405 Memory Programming Requirements ..............................482 Internal Voltage Reference Specifications .......................483 Microchip Internet Web Site .............................................533 Internet Address ...............................................................533 MOVF ..............................................................................437 Interrupt Sources .............................................................395 MOVFF ............................................................................438 A/D Conversion Complete .......................................355 MOVLB ............................................................................438 Capture Complete (ECCP) ......................................249 MOVLW ...........................................................................439 Compare Complete (ECCP) ....................................251 MOVSF ............................................................................457 Interrupt-on-Change (RB7:RB4) ..............................138 MOVSS ............................................................................458 TMR0 Overflow ........................................................199 MOVWF ...........................................................................439 TMR1 Overflow ........................................................207 MPLAB ASM30 Assembler, Linker, Librarian ..................464 TMR3 Overflow ................................................215, 223 MPLAB ICD 2 In-Circuit Debugger ..................................465 TMR4 to PR4 Match ................................................226 MPLAB ICE 2000 High-Performance Universal In-Circuit TMR4 to PR4 Match (PWM) ....................................225 Emulator ..................................................................465 Interrupts ..........................................................................115 MPLAB Integrated Development Environment Software .463 Control Bits ..............................................................115 MPLAB PM3 Device Programmer ...................................465 Control Registers. See INTCON Registers. MPLAB REAL ICE In-Circuit Emulator System ...............465 During, Context Saving ............................................130 MPLINK Object Linker/MPLIB Object Librarian ...............464 INTx Pin ...................................................................130 MSSP PORTB, Interrupt-on-Change ..................................130 ACK Pulse .......................................................296, 299 RCON Register ........................................................129 I2C Mode. See I2C Mode. TMR0 .......................................................................130 Module Overview .....................................................271 Interrupts, Flag Bits SPI Master/Slave Connection ..................................276 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) .....138 TMR4 Output for Clock Shift ....................................226 INTOSC Frequency Drift ....................................................41 MULLW ............................................................................440 INTOSC, INTRC. See Internal Oscillator Block. MULWF ............................................................................440 IORLW .............................................................................436 IORWF .............................................................................436 N NEGF ...............................................................................441  2011 Microchip Technology Inc. DS39932D-page 525

PIC18F46J11 FAMILY NOP .................................................................................441 RC5/SDO1/RP16 .................................................20, 26 RC6/PMA5/TX1/CK1/RP17 .......................................27 O RC6/TX1/CK1/RP17 ..................................................20 Oscillator Configuration RC7/PMA4/RX1/DT1/RP18 .......................................27 Internal Oscillator Block .............................................40 RC7/RX1/DT1/RP18 ..................................................20 Oscillator Control .......................................................37 RD0/PMD0/SCL2 .......................................................28 Oscillator Modes ........................................................38 RD1/PMD1/SDA2 ......................................................28 Oscillator Types .........................................................37 RD2/PMD2/RP19 .......................................................28 Oscillator Configurations ....................................................37 RD3/PMD3/RP20 .......................................................28 Oscillator Selection ..........................................................395 RD4/PMD4/RP21 .......................................................28 Oscillator Start-up Timer (OST) .........................................46 RD5/PMD5/RP22 .......................................................28 Oscillator Switching ............................................................42 RD6/PMD6/RP23 .......................................................28 Oscillator Transitions ..........................................................43 RD7/PMD7/RP24 .......................................................28 Oscillator, Timer1 .............................................201, 206, 219 RE0/AN5/PMRD ........................................................29 Oscillator, Timer3 .............................................................215 RE1/AN6/PMWR .......................................................29 RE2/AN7/PMCS ........................................................29 P VDD ............................................................................21 P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/ VDD1 ..........................................................................29 PWM (ECCP). ..........................................................255 VDD2 ..........................................................................29 Packaging VDDCORE/VCAP .....................................................21, 29 Details ......................................................................509 VSS1 ....................................................................21, 29 Marking ....................................................................507 VSS2 ....................................................................21, 29 Parallel Master Port (PMP) ..............................................171 Pinout I/O Descriptions Application Examples ...............................................193 PIC18F2XJ11 (28-Pin) ...............................................16 Associated Registers ...............................................195 PIC18F4XJ11 (44-Pin) ...............................................22 Data Registers .........................................................178 PLL Frequency Multiplier ...................................................40 Master Port Modes ...................................................185 POP .................................................................................442 Module Registers .....................................................172 POR. See Power-on Reset. Slave Port Modes .....................................................180 PORTA Peripheral Pin Select (PPS) .............................................150 Additional Pin Functions PICSTART Plus Development Programmer ....................466 Ultra Low-Power Wake-up .................................61 Pin Diagrams ....................................................................5–7 Associated Registers ...............................................137 Pin Functions LATA Register .........................................................135 AVDD1 ........................................................................29 PORTA Register ......................................................135 AVDD2 ........................................................................29 TRISA Register ........................................................135 AVSS1 ........................................................................29 PORTB MCLR ...................................................................16, 22 Associated Registers ...............................................141 OSC1/CLKI/RA7 ..................................................16, 22 LATB Register .........................................................138 OSC2/CLKO/RA6 ................................................16, 22 PORTB Register ......................................................138 RA0/AN0/C1INA/ULPWU/PMA6/RP0 ........................23 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........138 RA0/AN0/C1INA/ULPWU/RP0 ..................................17 TRISB Register ........................................................138 RA1/AN1/C2INA/PMA7/RP1 ......................................23 PORTC RA1/AN1/C2INA/RP1 ................................................17 Associated Registers ...............................................144 RA2/AN2/VREF-/CVREF/C2INB ............................17, 23 LATC Register .........................................................142 RA3/AN3/VREF+/C1INB .......................................17, 23 PORTC Register ......................................................142 RA5/AN4/SS1/HLVDIN/RP2 ................................17, 23 TRISC Register ........................................................142 RA6 ......................................................................17, 23 PORTD RA7 ......................................................................17, 23 Associated Registers ...............................................147 RB0/AN12/INT0/RP3 ...........................................18, 24 LATD Register .........................................................145 RB1/AN10/PMBE/RTCC/RP4 ....................................24 PORTD Register ......................................................145 RB1/AN10/RTCC/RP4 ...............................................18 TRISD Register ........................................................145 RB2/AN8/CTEDG1/PMA3/REFO/RP5 .......................24 PORTE RB2/AN8/CTEDG1/REFO/RP5 .................................18 Associated Registers ...............................................149 RB3/AN9/CTEDG2/PMA2/RP6 ..................................24 LATE Register .........................................................148 RB3/AN9/CTEDG2/RP6 ............................................18 PORTE Register ......................................................148 RB4/KBI0/RP7 ...........................................................18 TRISE Register ........................................................148 RB4/PMA1/KBI0/RP7 ................................................25 Power-Managed Modes RB5/KBI1/RP8 ...........................................................18 and EUSART Operation ..........................................331 RB5/PMA0/KBI1/RP8 ................................................25 and PWM Operation ................................................269 RB6/KBI2/PGC/RP9 ............................................19, 25 and SPI Operation ...................................................280 RB7/KBI3/PGD/RP10 ..........................................19, 25 Clock Sources ............................................................47 RC0/T1OSO/T1CKI/RP11 ...................................20, 26 Entering .....................................................................47 RC1/T1OSI/RP12 ................................................20, 26 Selecting ....................................................................47 RC2/AN11/CTPLS/RP13 .....................................20, 26 Power-on Reset (POR) ......................................................65 RC3/SCK1/SCL1/RP14 .......................................20, 26 Power-up Delays ...............................................................46 RC4/SDI1/SDA1/RP15 ........................................20, 26 DS39932D-page 526  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY Power-up Timer (PWRT) .............................................46, 66 ALRMCFG (Alarm Configuration) ............................231 Time-out Sequence ....................................................66 ALRMDAY (Alarm Day Value) .................................236 Prescaler, Timer0 .............................................................199 ALRMHR (Alarm Hours Value) ................................237 Prescaler, Timer2 (Timer4) ..............................................253 ALRMMIN (Alarm Minutes Value) ...........................238 PRI_IDLE Mode .................................................................52 ALRMMNTH (Alarm Month Value) ..........................236 PRI_RUN Mode .................................................................48 ALRMRPT (Alarm Calibration) ................................232 Product Identification System ..........................................535 ALRMSEC (Alarm Seconds Value) .........................238 Program Counter ...............................................................79 ALRMWD (Alarm Weekday Value) ..........................237 PCL, PCH and PCU Registers ...................................79 ANCON0 (A/D Port Configuration 2) .......................353 PCLATH and PCLATU Registers ..............................79 ANCON1 (A/D Port Configuration 1) .......................353 Program Memory Associated with Comparator ....................................361 ALU Status .................................................................96 Associated with Watchdog Timer ............................406 Extended Instruction Set ............................................99 BAUDCONx (Baud Rate Control) ............................330 Flash Configuration Words ........................................78 CCPxCON (Enhanced Capture/Compare/PWM Hard Memory Vectors ................................................78 x Control) .........................................................248 Instructions .................................................................83 CMSTAT (Comparator Status) ................................363 Two-Word ..........................................................83 CMxCON (Comparator Control x) ...........................362 Interrupt Vector ..........................................................78 CONFIG1H (Configuration 1 High) ..........................398 Look-up Tables ..........................................................81 CONFIG1L (Configuration 1 Low) ...........................397 Memory Maps ............................................................77 CONFIG2H (Configuration 2 High) ..........................400 Hard Vectors and Configuration Words .............78 CONFIG2L (Configuration 2 Low) ...........................399 Reset Vector ..............................................................78 CONFIG3H (Configuration 3 High) ..........................402 Program Verification and Code Protection .......................411 CONFIG3L (Configuration 3 Low) ...........................401 Programming, Device Instructions ...................................413 CONFIG4H (Configuration 4 High) ..........................403 Pulse Steering ..................................................................266 CONFIG4L (Configuration 4 Low) ...........................402 PUSH ...............................................................................442 CTMUCONH (CTMU Control High) .........................391 PUSH and POP Instructions ..............................................80 CTMUCONL (CTMU Control Low) ..........................392 PUSHL .............................................................................458 CTMUICON (CTMU Current Control) ......................393 PWM (CCP Module) CVRCON (Comparator Voltage Reference Associated Registers ...............................................254 Control) ............................................................370 Duty Cycle ................................................................252 DAY (Day Value) .....................................................234 Example Frequencies/Resolutions ..........................253 DEVID1 (Device ID 1) ..............................................403 Operation Setup .......................................................253 DEVID2 (Device ID 2) ..............................................404 Period .......................................................................252 DMACON1 (DMA Control 1) ....................................284 PR2/PR4 Registers ..................................................252 DMACON2 (DMA Control 2) ....................................285 TMR2 (TMR4) to PR2 (PR4) Match .........................252 DSCONH (Deep Sleep Control High Byte) ................58 PWM (ECCP Module) DSCONL (Deep Sleep Control Low Byte) .................58 Effects of a Reset .....................................................269 DSGPR0 (Deep Sleep Persistent General Operation in Power-Managed Modes ......................269 Purpose 0) .........................................................59 Operation with Fail-Safe Clock Monitor ...................269 DSGPR1 (Deep Sleep Persistent General Pulse Steering ..........................................................266 Purpose 1) .........................................................59 Steering Synchronization .........................................268 DSWAKEH (Deep Sleep Wake High Byte) ...............60 TMR4 to PR4 Match ................................................225 DSWAKEL (Deep Sleep Wake Low Byte) .................60 PWM Mode. See Enhanced Capture/Compare/PWM .....255 ECCPxAS (ECCPx Auto-Shutdown Control) ...........263 ECCPxDEL (Enhanced PWM Control) ....................266 Q EECON1 (EEPROM Control 1) ...............................105 Q Clock ............................................................................253 HLVDCON (High/Low-Voltage Detect Control) .......373 HOURS (Hours Value) ............................................235 R I2C Mode (MSSP) ....................................................291 RAM. See Data Memory. INTCON (Interrupt Control) .....................................117 RBIF Bit ............................................................................138 INTCON2 (Interrupt Control 2) ................................118 RC_IDLE Mode ..................................................................54 INTCON3 (Interrupt Control 3) ................................119 RC_RUN Mode ..................................................................50 IPR1 (Peripheral Interrupt Priority 1) .......................126 RCALL .............................................................................443 IPR2 (Peripheral Interrupt Priority 2) .......................127 RCON Register IPR3 (Peripheral Interrupt Priority 3) .......................128 Bit Status During Initialization ....................................68 MINUTES (Minutes Value) ......................................235 Reader Response ............................................................534 MONTH (Month Value) ............................................233 Real-Time Clock and Calendar (RTCC) ...........................227 ODCON1 (Peripheral Open-Drain Control 1) ..........133 Operation .................................................................239 ODCON2 (Peripheral Open-Drain Control 2) ..........133 Registers ..................................................................228 ODCON3 (Peripheral Open-Drain Control 3) ..........134 Reference Clock Output .....................................................45 OSCCON (Oscillator Control) ....................................44 Register File .......................................................................86 OSCTUNE (Oscillator Tuning) ...................................42 Register File Summary ................................................90–95 PADCFG1 (Pad Configuration Control 1) ................134 Registers PADCFG1 (Pad Configuration) ...............................230 ADCON0 (A/D Control 0) .........................................351 Parallel Master Port .................................................172 ADCON1 (A/D Control 1) .........................................352  2011 Microchip Technology Inc. DS39932D-page 527

PIC18F46J11 FAMILY PIE1 (Peripheral Interrupt Enable 1) ........................123 SPI Mode (MSSP) ...................................................273 PIE2 (Peripheral Interrupt Enable 2) ........................124 SSPxCON1 (MSSPx Control 1, I2C Mode) ..............293 PIE3 (Peripheral Interrupt Enable 3) ........................125 SSPxCON1 (MSSPx Control 1, SPI Mode) .............274 PIR1 (Peripheral Interrupt Request (Flag) 1) ...........120 SSPxCON2 (MSSPx Control 2, I2C Master Mode) ..294 PIR2 (Peripheral Interrupt Request (Flag) 2) ...........121 SSPxCON2 (MSSPx Control 2, I2C Slave Mode) ....295 PIR3 (Peripheral Interrupt Request (Flag) 3) ...........122 SSPxMSK (I2C Slave Address Mask) ......................295 PMADDRH (Parallel Port Address High Byte) .........179 SSPxSTAT (MSSPx Status, I2C Mode) ...................292 PMADDRL (Parallel Port Address Low Byte) ..........179 SSPxSTAT (MSSPx Status, SPI Mode) ..................273 PMCONH (Parallel Port Control High Byte) .............172 STATUS ....................................................................96 PMCONL (Parallel Port Control Low Byte) ..............173 STKPTR (Stack Pointer) ............................................80 PMEH (Parallel Port Enable High Byte) ...................176 T0CON (Timer0 Control) .........................................197 PMEL (Parallel Port Enable Low Byte) ....................176 T1CON (Timer1 Control) .........................................201 PMMODEH (Parallel Port Mode High Byte) .............174 T1GCON (Timer1 Gate Control) ..............................202 PMMODEL (Parallel Port Mode Low Byte) ..............175 T2CON (Timer2 Control) .........................................213 PMSTATH (Parallel Port Status High Byte) .............177 T3CON (Timer3 Control) .........................................215 PMSTATL (Parallel Port Status Low Byte) ..............177 T3GCON (Timer3 Gate Control) ..............................216 PPSCON (Peripheral Pin Select Input 0) .................155 T4CON (Timer4 Control) .........................................225 PSTRxCON (Pulse Steering Control) ......................267 TCLKCON (Timer Clock Control) ....................203, 217 RCON (Reset Control) .......................................64, 129 TXSTAx (Transmit Status and Control) ...................328 RCSTAx (Receive Status and Control) ....................329 WDTCON (Watchdog Timer Control) ......................406 REF0CON (Reference Oscillator Control) .................45 WKDY (Weekday Value) .........................................234 Reserved ..................................................................233 YEAR (Year Value) ..................................................233 RPINR1 (Peripheral Pin Select Input 1) ...................156 RESET .............................................................................443 RPINR12 (Peripheral Pin Select Input 12) ...............158 Reset .................................................................................63 RPINR13 (Peripheral Pin Select Input 13) ...............158 Brown-out Reset ........................................................65 RPINR16 (Peripheral Pin Select Input 16) ...............159 Brown-out Reset (BOR) .............................................63 RPINR17 (Peripheral Pin Select Input 17) ...............159 Configuration Mismatch (CM) ....................................63 RPINR2 (Peripheral Pin Select Input 2) ...................156 Configuration Mismatch Reset ...................................66 RPINR21 (Peripheral Pin Select Input 21) ...............159 Deep Sleep ................................................................63 RPINR22 (Peripheral Pin Select Input 22) ...............160 Fast Register Stack ...................................................81 RPINR23 (Peripheral Pin Select Input 23) ...............160 MCLR ........................................................................65 RPINR24 (Peripheral Pin Select Input 24) ...............160 MCLR Reset, During Power-Managed Modes ..........63 RPINR3 (Peripheral Pin Select Input 3) ...................156 MCLR Reset, Normal Operation ................................63 RPINR4 (Peripheral Pin Select Input 4) ...................157 Power-on Reset .........................................................65 RPINR6 (Peripheral Pin Select Input 6) ...................157 Power-on Reset (POR) ..............................................63 RPINR7 (Peripheral Pin Select Input 7) ...................157 Power-up Timer .........................................................66 RPINR8 (Peripheral Pin Select Input 8) ...................158 RESET Instruction .....................................................63 RPOR0 (Peripheral Pin Select Output 0) .................161 Stack Full ...................................................................63 RPOR1 (Peripheral Pin Select Output 1) .................161 Stack Underflow .........................................................63 RPOR10 (Peripheral Pin Select Output 10) .............164 State of Registers ......................................................68 RPOR11 (Peripheral Pin Select Output 11) .............164 Watchdog Timer (WDT) Reset ..................................63 RPOR12 (Peripheral Pin Select Output 12) .............165 Resets ..............................................................................395 RPOR13 (Peripheral Pin Select Output 13) .............165 Brown-out Reset (BOR) ...........................................395 RPOR14 (Peripheral Pin Select Output 14) .............165 Oscillator Start-up Timer (OST) ...............................395 RPOR15 (Peripheral Pin Select Output 15) .............166 Power-on Reset (POR) ............................................395 RPOR16 (Peripheral Pin Select Output 16) .............166 Power-up Timer (PWRT) .........................................395 RPOR17 (Peripheral Pin Select Output 17) .............166 RETFIE ............................................................................444 RPOR18 (Peripheral Pin Select Output 18) .............167 RETLW ............................................................................444 RPOR19 (Peripheral Pin Select Output 19) .............167 RETURN ..........................................................................445 RPOR2 (Peripheral Pin Select Output 2) .................161 Return Address Stack ........................................................79 RPOR20 (Peripheral Pin Select Output 20) .............167 Associated Registers .................................................79 RPOR21 (Peripheral Pin Select Output 21) .............168 Revision History ...............................................................519 RPOR22 (Peripheral Pin Select Output 22) .............168 RLCF ...............................................................................445 RPOR23 (Peripheral Pin Select Output 23) .............168 RLNCF .............................................................................446 RPOR24 (Peripheral Pin Select Output 24) .............169 RRCF ...............................................................................446 RPOR3 (Peripheral Pin Select Output 3) .................162 RRNCF ............................................................................447 RPOR4 (Peripheral Pin Select Output 4) .................162 RTCC RPOR5 (Peripheral Pin Select Output 5) .................162 Alarm .......................................................................243 RPOR6 (Peripheral Pin Select Output 6) .................163 Configuring ......................................................243 RPOR7 (Peripheral Pin Select Output 7) .................163 Interrupt ...........................................................244 RPOR8 (Peripheral Pin Select Output 8) .................163 Mask Settings ..................................................243 RPOR9 (Peripheral Pin Select Output 9) .................164 Alarm Value Registers (ALRMVAL) .........................236 RTCCAL (RTCC Calibration) ...................................230 Control Registers .....................................................229 RTCCFG (RTCC Configuration) ..............................229 Low-Power Modes ...................................................244 SECONDS (Seconds Value) ....................................235 Operation DS39932D-page 528  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY ALRMVAL Register Mapping ...........................242 SUBLW ............................................................................449 Calibration ........................................................242 SUBULNK ........................................................................459 Clock Source ...................................................240 SUBWF ............................................................................449 Digit Carry Rules ..............................................240 SUBWFB .........................................................................450 General Functionality .......................................241 SWAPF ............................................................................450 Leap Year ........................................................241 T Register Mapping .............................................241 RTCVAL Register Mapping .............................242 Table Pointer Operations with TBLRD, TBLWT (table) ...106 Safety Window for Register Reads and Writes 241 Table Reads/Table Writes .................................................81 Write Lock ........................................................241 TAD ..................................................................................357 Peripheral Module Disable (PMD) Register .............244 TBLRD .............................................................................451 Register Interface .....................................................239 TBLWT ............................................................................452 Register Maps ..........................................................245 Timer0 .............................................................................197 Reset ........................................................................244 Associated Registers ...............................................199 Device ..............................................................244 Operation .................................................................198 Power-on Reset (POR) ....................................244 Overflow Interrupt ....................................................199 Value Registers (RTCVAL) ......................................233 Prescaler .................................................................199 RTCEN Bit Write ..............................................................239 Switching Assignment .....................................199 Prescaler Assignment (PSA Bit) ..............................199 S Prescaler Select (T0PS2:T0PS0 Bits) .....................199 SCKx ................................................................................272 Reads and Writes in 16-Bit Mode ............................198 SDIx .................................................................................272 Source Edge Select (T0SE Bit) ...............................198 SDOx ...............................................................................272 Source Select (T0CS Bit) ........................................198 SEC_IDLE Mode ................................................................52 Timer1 .............................................................................201 SEC_RUN Mode ................................................................48 16-Bit Read/Write Mode ..........................................206 Serial Clock, SCKx ...........................................................272 Associated Registers ...............................................212 Serial Data In (SDIx) ........................................................272 Clock Source Selection ...........................................204 Serial Data Out (SDOx) ...................................................272 Gate .........................................................................208 Serial Peripheral Interface. See SPI Mode. Interrupt ...................................................................207 SETF ................................................................................447 Operation .................................................................204 Shoot-Through Current ....................................................265 Oscillator ..........................................................201, 206 Slave Select (SSx) ...........................................................272 Layout Considerations .....................................207 SLEEP .............................................................................448 Resetting, Using the ECCP Special Event Trigger ..208 Software Simulator (MPLAB SIM) ....................................464 TMR1H Register ......................................................201 Special Event Trigger. See Compare (ECCP Mode). TMR1L Register ......................................................201 Special Features of the CPU ...........................................395 Use as a Clock Source ............................................207 SPI Mode (MSSP) ............................................................272 Timer2 .............................................................................213 Associated Registers ...............................................281 Associated Registers ...............................................214 Bus Mode Compatibility ...........................................280 Interrupt ...................................................................214 Clock Speed, Interactions ........................................280 Operation .................................................................213 Effects of a Reset .....................................................280 Output ......................................................................214 Enabling SPI I/O ......................................................276 Timer3 .............................................................................215 Master Mode ............................................................277 16-Bit Read/Write Mode ..........................................219 Master/Slave Connection .........................................276 Associated Registers ...............................................223 Operation .................................................................275 Gate .........................................................................219 Open-Drain Output Option ...............................275 Operation .................................................................218 Operation in Power-Managed Modes ......................280 Oscillator ..........................................................215, 219 Registers ..................................................................273 Overflow Interrupt ............................................215, 223 Serial Clock ..............................................................272 Special Event Trigger (ECCP) .................................223 Serial Data In ...........................................................272 TMR3H Register ......................................................215 Serial Data Out ........................................................272 TMR3L Register ......................................................215 Slave Mode ..............................................................278 Timer4 .............................................................................225 Slave Select .............................................................272 Associated Registers ...............................................226 Slave Select Synchronization ..................................278 Interrupt ...................................................................226 SPI Clock .................................................................277 MSSP Clock Shift ....................................................226 SSPxBUF Register ..................................................277 Operation .................................................................225 SSPxSR Register .....................................................277 Output ......................................................................226 Typical Connection ..................................................276 Postscaler. See Postscaler, Timer4. SSPOV .............................................................................316 PR4 Register ...........................................................225 SSPOV Status Flag .........................................................316 Prescaler. See Prescaler, Timer4. SSPxSTAT Register TMR4 Register ........................................................225 R/W Bit .............................................................296, 299 TMR4 to PR4 Match Interrupt ..........................225, 226 SSx ..................................................................................272 Timing Diagrams Stack Full/Underflow Resets ..............................................81 A/D Conversion .......................................................506 SUBFSR ..........................................................................459 Asynchronous Reception .........................................340 SUBFWB ..........................................................................448 Asynchronous Transmission ...................................338  2011 Microchip Technology Inc. DS39932D-page 529

PIC18F46J11 FAMILY Asynchronous Transmission (Back-to-Back) ...........338 PWM Output (Active-High) ......................................256 Automatic Baud Rate Calculation ............................336 PWM Output (Active-Low) .......................................257 Auto-Wake-up Bit (WUE) During Normal Operation 341 Read and Write, 8-Bit Data, Demultiplexed Auto-Wake-up Bit (WUE) During Sleep ...................341 Address ...........................................................188 Baud Rate Generator with Clock Arbitration ............314 Read, 16-Bit Data, Demultiplexed Address .............191 BRG Overflow Sequence .........................................336 Read, 16-Bit Multiplexed Data, Fully Multiplexed BRG Reset Due to SDAx Arbitration During Start 16-Bit Address .................................................192 Condition ..........................................................322 Read, 16-Bit Multiplexed Data, Partially Multiplexed Bus Collision During a Repeated Start Condition Address ..........................................................191 (Case 1) ...........................................................323 Read, 8-Bit Data, Fully Multiplexed 16-Bit Address .190 Bus Collision During a Repeated Start Condition Read, 8-Bit Data, Partially Multiplexed Address ......188 (Case 2) ...........................................................323 Read, 8-Bit Data, Partially Multiplexed Address, Bus Collision During a Start Condition (SCLx = 0) ...322 Enable Strobe ..................................................189 Bus Collision During a Stop Condition (Case 1) ......324 Read, 8-Bit Data, Wait States Enabled, Partially Bus Collision During a Stop Condition (Case 2) ......324 Multiplexed Address ........................................188 Bus Collision During Start Condition (SDAx Only) ...321 Repeated Start Condition ........................................315 Bus Collision for Transmit and Acknowledge ...........320 Reset, Watchdog Timer (WDT), Oscillator Start-up CLKO and I/O ..........................................................488 Timer (OST) and Power-up Timer (PWRT) .....489 Clock Synchronization .............................................307 Send Break Character Sequence ............................342 Clock/Instruction Cycle ..............................................82 Slave Synchronization .............................................278 Enhanced Capture/Compare/PWM .........................492 Slow Rise Time (MCLR Tied to VDD, VDD Rise > EUSARTx Synchronous Receive (Master/Slave) ....504 TPWRT) ...............................................................67 EUSARTx Synchronous Transmission SPI Mode (Master Mode) .........................................277 (Master/Slave) ..................................................504 SPI Mode (Slave Mode, CKE = 0) ...........................279 Example SPI Master Mode (CKE = 0) .....................496 SPI Mode (Slave Mode, CKE = 1) ...........................279 Example SPI Master Mode (CKE = 1) .....................497 Steering Event at Beginning of Instruction Example SPI Slave Mode (CKE = 0) .......................498 (STRSYNC = 1) ...............................................268 Example SPI Slave Mode (CKE = 1) .......................499 Steering Event at End of Instruction External Clock ..........................................................486 (STRSYNC = 0) ...............................................268 Fail-Safe Clock Monitor ............................................410 Synchronous Reception (Master Mode, SREN) ......345 First Start Bit ............................................................314 Synchronous Transmission .....................................343 Full-Bridge PWM Output ..........................................260 Synchronous Transmission (Through TXEN) ..........344 Half-Bridge PWM Output .................................258, 265 Time-out Sequence on Power-up (MCLR Not High/Low-Voltage Detect Characteristics ................484 Tied to VDD), Case 1 .........................................67 High-Voltage Detect (VDIRMAG = 1) .......................377 Time-out Sequence on Power-up (MCLR Not I22C Bus Data ..........................................................500 Tied to VDD), Case 2 .........................................67 I2C Acknowledge Sequence ....................................319 Time-out Sequence on Power-up (MCLR Tied to I2C Bus Start/Stop Bits .............................................500 VDD, VDD Rise < TPWRT) ...................................66 I2C Master Mode (7 or 10-Bit Transmission) ...........317 Timer Pulse Generation ...........................................244 I2C Master Mode (7-Bit Reception) ..........................318 Timer0 and Timer1 External Clock ..........................491 I2C Slave Mode (10-Bit Reception, SEN = 0, Timer1 Gate Count Enable Mode ............................209 ADMSK = 01001) .............................................303 Timer1 Gate Single Pulse Mode ..............................211 I2C Slave Mode (10-Bit Reception, SEN = 0) ..........304 Timer1 Gate Single Pulse/Toggle Combined Mode 212 I2C Slave Mode (10-Bit Reception, SEN = 1) ..........309 Timer1 Gate Toggle Mode .......................................210 I2C Slave Mode (10-Bit Transmission) .....................305 Timer3 Gate Count Enable Mode) ...........................219 I2C Slave Mode (7-Bit Reception, SEN = 0, Timer3 Gate Single Pulse Mode ..............................221 ADMSK = 01011) .............................................301 Timer3 Gate Single Pulse/Toggle Combined Mode 222 I2C Slave Mode (7-Bit Reception, SEN = 0) ............300 Timer3 Gate Toggle Mode .......................................220 I2C Slave Mode (7-Bit Reception, SEN = 1) ............308 Transition for Entry to Idle Mode ................................53 I2C Slave Mode (7-Bit Transmission) .......................302 Transition for Entry to SEC_RUN Mode ....................49 I2C Slave Mode General Call Address Sequence Transition for Entry to Sleep Mode ............................51 (7 or 10-Bit Addressing Mode) .........................310 Transition for Two-Speed Start-up (INTRC to I2C Stop Condition Receive or Transmit Mode ........319 HSPLL) ............................................................409 Low-Voltage Detect (VDIRMAG = 0) .......................376 Transition for Wake From Idle to Run Mode ..............53 MSSPx I2C Bus Data ...............................................502 Transition for Wake From Sleep (HSPLL) .................51 MSSPx I2C Bus Start/Stop Bits ................................502 Transition From RC_RUN Mode to PRI_RUN Mode .50 Parallel Master Port Read ........................................493 Transition From SEC_RUN Mode to PRI_RUN Parallel Master Port Write ........................................494 Mode (HSPLL) ...................................................49 Parallel Slave Port Read ..................................181, 183 Transition to RC_RUN Mode .....................................50 Parallel Slave Port Write ..................................181, 184 Write, 16-Bit Data, Demultiplexed Address .............191 PWM Auto-Shutdown with Auto-Restart Enabled ....264 Write, 16-Bit Multiplexed Data, Fully Multiplexed PWM Auto-Shutdown with Firmware Restart ...........264 16-Bit Address .................................................192 PWM Direction Change ...........................................261 Write, 16-Bit Multiplexed Data, Partially Multiplexed PWM Direction Change at Near 100% Duty Cycle ..262 Address ...........................................................192 PWM Output ............................................................252 Write, 8-Bit Data, Fully Multiplexed 16-Bit Address .190 DS39932D-page 530  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY Write, 8-Bit Data, Partially Multiplexed Address ......189 Write, 8-Bit Data, Partially Multiplexed Address, Enable Strobe ..................................................190 Write, 8-Bit Data, Wait States Enabled, Partially Multiplexed Address ........................................189 Timing Diagrams and Specifications AC Characteristics Internal RC Accuracy .......................................487 CLKO and I/O Requirements ...................................488 Enhanced Capture/Compare/PWM Requirements ..492 EUSARTx Synchronous Receive Requirements .....504 EUSARTx Synchronous Transmission Requirements ..................................................504 Example SPI Mode Requirements (Master Mode, CKE = 0) ..........................................................496 Example SPI Mode Requirements (Master Mode, CKE = 1) ..........................................................497 Example SPI Mode Requirements (Slave Mode, CKE = 0) ..........................................................498 Example SPI Slave Mode Requirements (CKE = 1) 499 External Clock Requirements ..................................487 I2C Bus Data Requirements (Slave Mode) ..............501 I2C Bus Start/Stop Bits Requirements (Slave Mode) ...................................................500 Low-Power Wake-up Time .......................................490 MSSPx I2C Bus Data Requirements ........................503 MSSPx I2C Bus Start/Stop Bits Requirements ........502 Parallel Master Port Read Requirements ................493 Parallel Master Port Write Requirements .................494 Parallel Slave Port Requirements ............................495 PLL Clock .................................................................487 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ..................................................489 Timer0 and Timer1 External Clock Requirements ...491 TSTFSZ ...........................................................................453 Two-Speed Start-up .................................................395, 409 Two-Word Instructions Example Cases ..........................................................83 TXSTAx Register BRGH Bit .................................................................331 U Ultra Low-Power Wake-up .................................................61 V Voltage Reference Specifications ....................................483 Voltage Regulator (On-Chip) ...........................................407 Operation in Sleep Mode .........................................408 W Watchdog Timer (WDT) ...........................................395, 405 Associated Registers ...............................................406 Control Register .......................................................405 During Oscillator Failure ..........................................410 Programming Considerations ..................................405 WCOL ......................................................314, 315, 316, 319 WCOL Status Flag ...................................314, 315, 316, 319 WWW Address .................................................................533 WWW, Online Support .........................................................9 X XORLW ............................................................................453 XORWF ............................................................................454  2011 Microchip Technology Inc. DS39932D-page 531

PIC18F46J11 FAMILY NOTES: DS39932D-page 532  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011 Microchip Technology Inc. DS39932D-page 533

PIC18F46J11 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F46J11 Family Literature Number: DS39932D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39932D-page 534  2011 Microchip Technology Inc.

PIC18F46J11 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18F46J11-I/PT 301 = Industrial temp., Range TQFP package, QTP pattern #301. b) PIC18F46J11T-I/PT = Tape and reel, Industrial temp., TQFP package. Device(1) PIC18F24J11 PIC18F25J11 PIC18F26J11 PIC18F44J11 PIC18F45J11 PIC18F46J11 PIC18LF24J11 PIC18LF25J11 PIC18LF26J11 PIC18LF44J11 PIC18LF45J11 PIC18LF46J11 Note1: F = Standard Voltage Range Temperature Range I = -40C to +85C (Industrial) LF = Extended Voltage Range 2: T=In tape and reel Package SP = Skinny PDIP SS = SSOP SO = SOIC ML = QFN PT = TQFP (Thin Quad Flatpack) Pattern QTP, SQTP, Code or Special Requirements (blank otherwise)  2011 Microchip Technology Inc. DS39932D-page 535

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://www.microchip.com/ support Fax: 852-2401-3431 India - Pune France - Paris Web Address: Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 www.microchip.com Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 Atlanta Fax: 61-2-9868-6755 Japan - Yokohama Germany - Munich Duluth, GA China - Beijing Tel: 81-45-471- 6166 Tel: 49-89-627-144-0 Tel: 86-10-8528-2100 Fax: 49-89-627-144-44 Tel: 678-957-9614 Fax: 81-45-471-6122 Fax: 678-957-1455 Fax: 86-10-8528-2104 Korea - Daegu Italy - Milan Boston China - Chengdu Tel: 82-53-744-4301 Tel: 39-0331-742611 Westborough, MA Tel: 86-28-8665-5511 Fax: 82-53-744-4302 Fax: 39-0331-466781 Tel: 774-760-0087 Fax: 86-28-8665-7889 Korea - Seoul Netherlands - Drunen Fax: 774-760-0088 China - Chongqing Tel: 82-2-554-7200 Tel: 31-416-690399 Chicago Tel: 86-23-8980-9588 Fax: 82-2-558-5932 or Fax: 31-416-690340 Itasca, IL Fax: 86-23-8980-9500 82-2-558-5934 Spain - Madrid Tel: 630-285-0071 China - Hong Kong SAR Malaysia - Kuala Lumpur Tel: 34-91-708-08-90 Fax: 630-285-0075 Tel: 852-2401-1200 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91 Cleveland Fax: 852-2401-3431 Fax: 60-3-6201-9859 UK - Wokingham Independence, OH China - Nanjing Malaysia - Penang Tel: 44-118-921-5869 Tel: 216-447-0464 Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Fax: 44-118-921-5820 Fax: 216-447-0643 Fax: 86-25-8473-2470 Fax: 60-4-227-4068 Dallas China - Qingdao Philippines - Manila Addison, TX Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Tel: 972-818-7423 Fax: 86-532-8502-7205 Fax: 63-2-634-9069 Fax: 972-818-2924 China - Shanghai Singapore Detroit Tel: 86-21-5407-5533 Tel: 65-6334-8870 Farmington Hills, MI Fax: 86-21-5407-5066 Fax: 65-6334-8850 Tel: 248-538-2250 Fax: 248-538-2260 China - Shenyang Taiwan - Hsin Chu Tel: 86-24-2334-2829 Tel: 886-3-6578-300 Indianapolis Fax: 86-24-2334-2393 Fax: 886-3-6578-370 Noblesville, IN Tel: 317-773-8323 China - Shenzhen Taiwan - Kaohsiung Fax: 317-773-5453 Tel: 86-755-8203-2660 Tel: 886-7-213-7830 Fax: 86-755-8203-1760 Fax: 886-7-330-9305 Los Angeles Mission Viejo, CA China - Wuhan Taiwan - Taipei Tel: 86-27-5980-5300 Tel: 886-2-2500-6610 Tel: 949-462-9523 Fax: 949-462-9608 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 China - Xian Thailand - Bangkok Santa Clara Santa Clara, CA Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Tel: 408-961-6444 Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Fax: 408-961-6445 China - Xiamen Tel: 86-592-2388138 Toronto Mississauga, Ontario, Fax: 86-592-2388130 Canada China - Zhuhai Tel: 905-673-0699 Tel: 86-756-3210040 Fax: 905-673-6509 Fax: 86-756-3210049 02/18/11 DS39932D-page 536  2011 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18F25J11T-I/SS PIC18F25J11T-I/SO PIC18F25J11T-I/ML PIC18F24J11T-I/SO PIC18F24J11T-I/SS PIC18F24J11T-I/ML PIC18LF24J11-I/SS PIC18LF24J11-I/SO PIC18LF25J11-I/ML PIC18LF25J11T-I/ML PIC18LF24J11-I/SP PIC18LF25J11-I/SP PIC18LF24J11T-I/ML PIC18LF25J11-I/SS PIC18LF25J11-I/SO PIC18LF24J11-I/ML PIC18F24J11-I/ML PIC18F25J11-I/SP PIC18LF24J11T-I/SO PIC18F25J11-I/SO PIC18LF24J11T-I/SS PIC18F25J11-I/SS PIC18F24J11-I/SO PIC18F24J11-I/SS PIC18F24J11-I/SP PIC18F25J11- I/ML PIC18LF25J11T-I/SS PIC18LF25J11T-I/SO PIC18F46J11T-I/PT PIC18F26J11-I/SO PIC18LF44J11T-I/PT PIC18F26J11-I/SS PIC18LF44J11-I/PT PIC18LF26J11T-I/SO PIC18F46J11T-I/ML PIC18LF26J11T-I/SS PIC18LF26J11T-I/ML PIC18F46J11-I/PT PIC18F26J11T-I/ML PIC18F26J11-I/SP PIC18LF46J11T-I/PT PIC18F46J11-I/ML PIC18LF45J11T-I/PT PIC18F44J11T-I/ML PIC18F45J11-I/ML PIC18LF46J11T-I/ML PIC18LF46J11-I/ML PIC18LF26J11-I/SS PIC18LF44J11T-I/ML PIC18LF46J11-I/PT PIC18F45J11-I/PT PIC18LF26J11-I/SO PIC18LF45J11-I/ML PIC18F44J11-I/PT PIC18F26J11-I/ML PIC18LF45J11T-I/ML PIC18F45J11T-I/ML PIC18F26J11T-I/SS PIC18LF26J11-I/ML PIC18LF44J11-I/ML PIC18F44J11-I/ML PIC18F44J11T-I/PT PIC18F45J11T-I/PT PIC18LF26J11-I/SP PIC18LF45J11-I/PT PIC18F26J11T-I/SO MA180023